STMicroelectronics
STM32L051K8
2024.05.02
STM32L051K8
false
0
0
ADC
Analog-to-digital converter
ADC
0x0
0x0
0x400
registers
n
ADC_COMP
ADC and comparator 1 and 2
12
CALFACT
CALFACT
ADC Calibration factor
0xB4
32
read-write
n
0x0
0x0
CALFACT
Calibration factor
0
7
CCR
CCR
ADC common configuration register
0x308
32
read-write
n
0x0
0x0
LFMEN
Low Frequency Mode enable
25
1
PRESC
ADC prescaler
18
4
TSEN
Temperature sensor enable
23
1
VLCDEN
VLCD enable
24
1
VREFEN
VREFINT enable
22
1
CFGR1
CFGR1
configuration register 1
0xC
32
read-write
n
0x0
0x0
ALIGN
Data alignment
5
1
AUTDLY
Auto-delayed conversion mode
14
1
AUTOFF
Auto-off mode
15
1
AWDCH
Analog watchdog channel selection
26
5
AWDEN
Analog watchdog enable
23
1
AWDSGL
Enable the watchdog on a single channel or on all channels
22
1
CONT
Single / continuous conversion mode
13
1
DISCEN
Discontinuous mode
16
1
DMACFG
Direct memery access configuration
1
1
DMAEN
Direct memory access enable
0
1
EXTEN
External trigger enable and polarity selection
10
2
EXTSEL
External trigger selection
6
3
OVRMOD
Overrun management mode
12
1
RES
Data resolution
3
2
SCANDIR
Scan sequence direction
2
1
CFGR2
CFGR2
configuration register 2
0x10
32
read-write
n
0x0
0x0
CKMODE
ADC clock mode
30
2
OVSE
Oversampler Enable
0
1
OVSR
Oversampling ratio
2
3
OVSS
Oversampling shift
5
4
TOVS
Triggered Oversampling
9
1
CHSELR
CHSELR
channel selection register
0x28
32
read-write
n
0x0
0x0
CHSEL0
Channel-x selection
0
1
CHSEL1
Channel-x selection
1
1
CHSEL10
Channel-x selection
10
1
CHSEL11
Channel-x selection
11
1
CHSEL12
Channel-x selection
12
1
CHSEL13
Channel-x selection
13
1
CHSEL14
Channel-x selection
14
1
CHSEL15
Channel-x selection
15
1
CHSEL16
Channel-x selection
16
1
CHSEL17
Channel-x selection
17
1
CHSEL18
Channel-x selection
18
1
CHSEL2
Channel-x selection
2
1
CHSEL3
Channel-x selection
3
1
CHSEL4
Channel-x selection
4
1
CHSEL5
Channel-x selection
5
1
CHSEL6
Channel-x selection
6
1
CHSEL7
Channel-x selection
7
1
CHSEL8
Channel-x selection
8
1
CHSEL9
Channel-x selection
9
1
CR
CR
control register
0x8
32
read-write
n
0x0
0x0
ADCAL
ADC calibration
31
1
ADDIS
ADC disable command
1
1
ADEN
ADC enable command
0
1
ADSTART
ADC start conversion command
2
1
ADSTP
ADC stop conversion command
4
1
ADVREGEN
ADC Voltage Regulator Enable
28
1
DR
DR
data register
0x40
32
read-only
n
0x0
0x0
DATA
Converted data
0
16
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0x0
ADRDYIE
ADC ready interrupt enable
0
1
AWDIE
Analog watchdog interrupt enable
7
1
EOCALIE
End of calibration interrupt enable
11
1
EOCIE
End of conversion interrupt enable
2
1
EOSIE
End of conversion sequence interrupt enable
3
1
EOSMPIE
End of sampling flag interrupt enable
1
1
OVRIE
Overrun interrupt enable
4
1
ISR
ISR
interrupt and status register
0x0
32
read-write
n
0x0
0x0
ADRDY
ADC ready
0
1
AWD
Analog watchdog flag
7
1
EOC
End of conversion flag
2
1
EOCAL
End Of Calibration flag
11
1
EOS
End of sequence flag
3
1
EOSMP
End of sampling flag
1
1
OVR
ADC overrun
4
1
SMPR
SMPR
sampling time register
0x14
32
read-write
n
0x0
0x0
SMPR
Sampling time selection
0
3
TR
TR
watchdog threshold register
0x20
32
read-write
n
0x0
0x0
HT
Analog watchdog higher threshold
16
12
LT
Analog watchdog lower threshold
0
12
AES
Advanced encryption standard hardware accelerator
AES
0x0
0x0
0x400
registers
n
AES_RNG_LPUART1
AES global interrupt RNG global interrupt and LPUART1 global interrupt through
29
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
CCFC
Computation Complete Flag Clear
7
1
CCFIE
CCF flag interrupt enable
9
1
CHMOD
AES chaining mode
5
2
DATATYPE
Data type selection (for data in and data out to/from the cryptographic block)
1
2
DMAINEN
Enable DMA management of data input phase
11
1
DMAOUTEN
Enable DMA management of data output phase
12
1
EN
AES enable
0
1
ERRC
Error clear
8
1
ERRIE
Error interrupt enable
10
1
MODE
AES operating mode
3
2
DINR
DINR
data input register
0x8
32
read-write
n
0x0
0x0
AES_DINR
Data Input Register.
0
32
DOUTR
DOUTR
data output register
0xC
32
read-only
n
0x0
0x0
AES_DOUTR
Data output register
0
32
IVR0
IVR0
initialization vector register 0
0x20
32
read-write
n
0x0
0x0
AES_IVR0
initialization vector register (LSB IVR [31:0])
0
32
IVR1
IVR1
initialization vector register 1
0x24
32
read-write
n
0x0
0x0
AES_IVR1
Initialization Vector Register (IVR [63:32])
0
32
IVR2
IVR2
initialization vector register 2
0x28
32
read-write
n
0x0
0x0
AES_IVR2
Initialization Vector Register (IVR [95:64])
0
32
IVR3
IVR3
initialization vector register 3
0x2C
32
read-write
n
0x0
0x0
AES_IVR3
Initialization Vector Register (MSB IVR [127:96])
0
32
KEYR0
KEYR0
key register 0
0x10
32
read-write
n
0x0
0x0
AES_KEYR0
Data Output Register (LSB key [31:0])
0
32
KEYR1
KEYR1
key register 1
0x14
32
read-write
n
0x0
0x0
AES_KEYR1
AES key register (key [63:32])
0
32
KEYR2
KEYR2
key register 2
0x18
32
read-write
n
0x0
0x0
AES_KEYR2
AES key register (key [95:64])
0
32
KEYR3
KEYR3
key register 3
0x1C
32
read-write
n
0x0
0x0
AES_KEYR3
AES key register (MSB key [127:96])
0
32
SR
SR
status register
0x4
32
read-only
n
0x0
0x0
CCF
Computation complete flag
0
1
RDERR
Read error flag
1
1
WRERR
Write error flag
2
1
CRC
Cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
read-write
n
0x0
0x0
POLYSIZE
Polynomial size
3
2
read-write
RESET
RESET bit
0
1
write-only
REV_IN
Reverse input data
5
2
read-write
REV_OUT
Reverse output data
7
1
read-write
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data register bits
0
32
IDR
IDR
Independent data register
0x4
32
read-write
n
0x0
0x0
IDR
General-purpose 8-bit data register bits
0
8
INIT
INIT
Initial CRC value
0x10
32
read-write
n
0x0
0x0
CRC_INIT
Programmable initial CRC value
0
32
POL
POL
polynomial
0x14
32
read-write
n
0x0
0x0
Polynomialcoefficients
Programmable polynomial
0
32
DBG
Debug support
DBGMCU
0x0
0x0
0x400
registers
n
APB1_FZ
APB1_FZ
APB Low Freeze Register
0x8
32
read-write
n
0x0
0x0
DBG_I2C1_STOP
I2C1 SMBUS timeout mode stopped when core is halted
21
1
DBG_I2C2_STOP
I2C2 SMBUS timeout mode stopped when core is halted
22
1
DBG_IWDG_STOP
Debug Independent Wachdog stopped when Core is halted
12
1
DBG_LPTIMER_STOP
LPTIM1 counter stopped when core is halted
31
1
DBG_RTC_STOP
Debug RTC stopped when Core is halted
10
1
DBG_TIMER2_STOP
Debug Timer 2 stopped when Core is halted
0
1
DBG_TIMER6_STOP
Debug Timer 6 stopped when Core is halted
4
1
DBG_WWDG_STOP
Debug Window Wachdog stopped when Core is halted
11
1
APB2_FZ
APB2_FZ
APB High Freeze Register
0xC
32
read-write
n
0x0
0x0
DBG_TIMER21_STOP
Debug Timer 21 stopped when Core is halted
2
1
DBG_TIMER22_STO
Debug Timer 22 stopped when Core is halted
6
1
CR
CR
Debug MCU Configuration Register
0x4
32
read-write
n
0x0
0x0
DBG_SLEEP
Debug Sleep Mode
0
1
DBG_STANDBY
Debug Standby Mode
2
1
DBG_STOP
Debug Stop Mode
1
1
IDCODE
IDCODE
MCU Device ID Code Register
0x0
32
read-only
n
0x0
0x0
DEV_ID
Device Identifier
0
12
REV_ID
Revision Identifier
16
16
DMA1
Direct memory access controller
DMA
0x0
0x0
0x400
registers
n
DMA1_Channel1
DMA1 Channel1 global interrupt
9
DMA1_Channel2_3
DMA1 Channel2 and 3 interrupts
10
DMA1_Channel4_7
DMA1 Channel4 to 7 interrupts
11
CCR1
CCR1
channel x configuration register
0x8
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
channel x configuration register
0x1C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
channel x configuration register
0x30
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
channel x configuration register
0x44
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
channel x configuration register
0x58
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
channel x configuration register
0x6C
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
channel x configuration register
0x80
32
read-write
n
0x0
0x0
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
channel x memory address register
0x14
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR2
CMAR2
channel x memory address register
0x28
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR3
CMAR3
channel x memory address register
0x3C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR4
CMAR4
channel x memory address register
0x50
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR5
CMAR5
channel x memory address register
0x64
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR6
CMAR6
channel x memory address register
0x78
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CMAR7
CMAR7
channel x memory address register
0x8C
32
read-write
n
0x0
0x0
MA
Memory address
0
32
CNDTR1
CNDTR1
channel x number of data register
0xC
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
channel x number of data register
0x20
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
channel x number of data register
0x34
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
channel x number of data register
0x48
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
channel x number of data register
0x5C
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
channel x number of data register
0x70
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
channel x number of data register
0x84
32
read-write
n
0x0
0x0
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
channel x peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR2
CPAR2
channel x peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR3
CPAR3
channel x peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR4
CPAR4
channel x peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR5
CPAR5
channel x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR6
CPAR6
channel x peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CPAR7
CPAR7
channel x peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
Peripheral address
0
32
CSELR
CSELR
channel selection register
0xA8
32
read-write
n
0x0
0x0
C1S
DMA channel 1 selection
0
4
C2S
DMA channel 2 selection
4
4
C3S
DMA channel 3 selection
8
4
C4S
DMA channel 4 selection
12
4
C5S
DMA channel 5 selection
16
4
C6S
DMA channel 6 selection
20
4
C7S
DMA channel 7 selection
24
4
IFCR
IFCR
interrupt flag clear register
0x4
32
write-only
n
0x0
0x0
CGIF1
Channel x global interrupt clear (x = 1 ..7)
0
1
CGIF2
Channel x global interrupt clear (x = 1 ..7)
4
1
CGIF3
Channel x global interrupt clear (x = 1 ..7)
8
1
CGIF4
Channel x global interrupt clear (x = 1 ..7)
12
1
CGIF5
Channel x global interrupt clear (x = 1 ..7)
16
1
CGIF6
Channel x global interrupt clear (x = 1 ..7)
20
1
CGIF7
Channel x global interrupt clear (x = 1 ..7)
24
1
CHTIF1
Channel x half transfer clear (x = 1 ..7)
2
1
CHTIF2
Channel x half transfer clear (x = 1 ..7)
6
1
CHTIF3
Channel x half transfer clear (x = 1 ..7)
10
1
CHTIF4
Channel x half transfer clear (x = 1 ..7)
14
1
CHTIF5
Channel x half transfer clear (x = 1 ..7)
18
1
CHTIF6
Channel x half transfer clear (x = 1 ..7)
22
1
CHTIF7
Channel x half transfer clear (x = 1 ..7)
26
1
CTCIF1
Channel x transfer complete clear (x = 1 ..7)
1
1
CTCIF2
Channel x transfer complete clear (x = 1 ..7)
5
1
CTCIF3
Channel x transfer complete clear (x = 1 ..7)
9
1
CTCIF4
Channel x transfer complete clear (x = 1 ..7)
13
1
CTCIF5
Channel x transfer complete clear (x = 1 ..7)
17
1
CTCIF6
Channel x transfer complete clear (x = 1 ..7)
21
1
CTCIF7
Channel x transfer complete clear (x = 1 ..7)
25
1
CTEIF1
Channel x transfer error clear (x = 1 ..7)
3
1
CTEIF2
Channel x transfer error clear (x = 1 ..7)
7
1
CTEIF3
Channel x transfer error clear (x = 1 ..7)
11
1
CTEIF4
Channel x transfer error clear (x = 1 ..7)
15
1
CTEIF5
Channel x transfer error clear (x = 1 ..7)
19
1
CTEIF6
Channel x transfer error clear (x = 1 ..7)
23
1
CTEIF7
Channel x transfer error clear (x = 1 ..7)
27
1
ISR
ISR
interrupt status register
0x0
32
read-only
n
0x0
0x0
GIF1
Channel x global interrupt flag (x = 1 ..7)
0
1
GIF2
Channel x global interrupt flag (x = 1 ..7)
4
1
GIF3
Channel x global interrupt flag (x = 1 ..7)
8
1
GIF4
Channel x global interrupt flag (x = 1 ..7)
12
1
GIF5
Channel x global interrupt flag (x = 1 ..7)
16
1
GIF6
Channel x global interrupt flag (x = 1 ..7)
20
1
GIF7
Channel x global interrupt flag (x = 1 ..7)
24
1
HTIF1
Channel x half transfer flag (x = 1 ..7)
2
1
HTIF2
Channel x half transfer flag (x = 1 ..7)
6
1
HTIF3
Channel x half transfer flag (x = 1 ..7)
10
1
HTIF4
Channel x half transfer flag (x = 1 ..7)
14
1
HTIF5
Channel x half transfer flag (x = 1 ..7)
18
1
HTIF6
Channel x half transfer flag (x = 1 ..7)
22
1
HTIF7
Channel x half transfer flag (x = 1 ..7)
26
1
TCIF1
Channel x transfer complete flag (x = 1 ..7)
1
1
TCIF2
Channel x transfer complete flag (x = 1 ..7)
5
1
TCIF3
Channel x transfer complete flag (x = 1 ..7)
9
1
TCIF4
Channel x transfer complete flag (x = 1 ..7)
13
1
TCIF5
Channel x transfer complete flag (x = 1 ..7)
17
1
TCIF6
Channel x transfer complete flag (x = 1 ..7)
21
1
TCIF7
Channel x transfer complete flag (x = 1 ..7)
25
1
TEIF1
Channel x transfer error flag (x = 1 ..7)
3
1
TEIF2
Channel x transfer error flag (x = 1 ..7)
7
1
TEIF3
Channel x transfer error flag (x = 1 ..7)
11
1
TEIF4
Channel x transfer error flag (x = 1 ..7)
15
1
TEIF5
Channel x transfer error flag (x = 1 ..7)
19
1
TEIF6
Channel x transfer error flag (x = 1 ..7)
23
1
TEIF7
Channel x transfer error flag (x = 1 ..7)
27
1
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI line detection
1
EXTI0_1
EXTI Line[1:0] interrupts
5
EXTI2_3
EXTI Line[3:2] interrupts
6
EXTI4_15
EXTI Line15 and EXTI4 interrupts
7
EMR
EMR
Event mask register (EXTI_EMR)
0x4
32
read-write
n
0x0
0x0
EM0
Event Mask on line 0
0
1
EM1
Event Mask on line 1
1
1
EM10
Event Mask on line 10
10
1
EM11
Event Mask on line 11
11
1
EM12
Event Mask on line 12
12
1
EM13
Event Mask on line 13
13
1
EM14
Event Mask on line 14
14
1
EM15
Event Mask on line 15
15
1
EM16
Event Mask on line 16
16
1
EM17
Event Mask on line 17
17
1
EM18
Event Mask on line 18
18
1
EM19
Event Mask on line 19
19
1
EM2
Event Mask on line 2
2
1
EM20
Event Mask on line 20
20
1
EM21
Event Mask on line 21
21
1
EM22
Event Mask on line 22
22
1
EM23
Event Mask on line 23
23
1
EM24
Event Mask on line 24
24
1
EM25
Event Mask on line 25
25
1
EM26
Event Mask on line 26
26
1
EM28
Event Mask on line 28
28
1
EM29
Event Mask on line 29
29
1
EM3
Event Mask on line 3
3
1
EM4
Event Mask on line 4
4
1
EM5
Event Mask on line 5
5
1
EM6
Event Mask on line 6
6
1
EM7
Event Mask on line 7
7
1
EM8
Event Mask on line 8
8
1
EM9
Event Mask on line 9
9
1
FTSR
FTSR
Falling Trigger selection register (EXTI_FTSR)
0xC
32
read-write
n
0x0
0x0
FT0
Falling trigger event configuration of line 0
0
1
FT1
Falling trigger event configuration of line 1
1
1
FT10
Falling trigger event configuration of line 10
10
1
FT11
Falling trigger event configuration of line 11
11
1
FT12
Falling trigger event configuration of line 12
12
1
FT13
Falling trigger event configuration of line 13
13
1
FT14
Falling trigger event configuration of line 14
14
1
FT15
Falling trigger event configuration of line 15
15
1
FT16
Falling trigger event configuration of line 16
16
1
FT17
Falling trigger event configuration of line 17
17
1
FT19
Falling trigger event configuration of line 19
19
1
FT2
Falling trigger event configuration of line 2
2
1
FT20
Falling trigger event configuration of line 20
20
1
FT21
Falling trigger event configuration of line 21
21
1
FT22
Falling trigger event configuration of line 22
22
1
FT3
Falling trigger event configuration of line 3
3
1
FT4
Falling trigger event configuration of line 4
4
1
FT5
Falling trigger event configuration of line 5
5
1
FT6
Falling trigger event configuration of line 6
6
1
FT7
Falling trigger event configuration of line 7
7
1
FT8
Falling trigger event configuration of line 8
8
1
FT9
Falling trigger event configuration of line 9
9
1
IMR
IMR
Interrupt mask register (EXTI_IMR)
0x0
32
read-write
n
0x0
0x0
IM0
Interrupt Mask on line 0
0
1
IM1
Interrupt Mask on line 1
1
1
IM10
Interrupt Mask on line 10
10
1
IM11
Interrupt Mask on line 11
11
1
IM12
Interrupt Mask on line 12
12
1
IM13
Interrupt Mask on line 13
13
1
IM14
Interrupt Mask on line 14
14
1
IM15
Interrupt Mask on line 15
15
1
IM16
Interrupt Mask on line 16
16
1
IM17
Interrupt Mask on line 17
17
1
IM18
Interrupt Mask on line 18
18
1
IM19
Interrupt Mask on line 19
19
1
IM2
Interrupt Mask on line 2
2
1
IM20
Interrupt Mask on line 20
20
1
IM21
Interrupt Mask on line 21
21
1
IM22
Interrupt Mask on line 22
22
1
IM23
Interrupt Mask on line 23
23
1
IM24
Interrupt Mask on line 24
24
1
IM25
Interrupt Mask on line 25
25
1
IM26
Interrupt Mask on line 27
26
1
IM28
Interrupt Mask on line 27
28
1
IM29
Interrupt Mask on line 27
29
1
IM3
Interrupt Mask on line 3
3
1
IM4
Interrupt Mask on line 4
4
1
IM5
Interrupt Mask on line 5
5
1
IM6
Interrupt Mask on line 6
6
1
IM7
Interrupt Mask on line 7
7
1
IM8
Interrupt Mask on line 8
8
1
IM9
Interrupt Mask on line 9
9
1
PR
PR
Pending register (EXTI_PR)
0x14
32
read-write
n
0x0
0x0
PIF0
Pending bit 0
0
1
PIF1
Pending bit 1
1
1
PIF10
Pending bit 10
10
1
PIF11
Pending bit 11
11
1
PIF12
Pending bit 12
12
1
PIF13
Pending bit 13
13
1
PIF14
Pending bit 14
14
1
PIF15
Pending bit 15
15
1
PIF16
Pending bit 16
16
1
PIF17
Pending bit 17
17
1
PIF19
Pending bit 19
19
1
PIF2
Pending bit 2
2
1
PIF20
Pending bit 20
20
1
PIF21
Pending bit 21
21
1
PIF22
Pending bit 22
22
1
PIF3
Pending bit 3
3
1
PIF4
Pending bit 4
4
1
PIF5
Pending bit 5
5
1
PIF6
Pending bit 6
6
1
PIF7
Pending bit 7
7
1
PIF8
Pending bit 8
8
1
PIF9
Pending bit 9
9
1
RTSR
RTSR
Rising Trigger selection register (EXTI_RTSR)
0x8
32
read-write
n
0x0
0x0
RT0
Rising trigger event configuration of line 0
0
1
RT1
Rising trigger event configuration of line 1
1
1
RT10
Rising trigger event configuration of line 10
10
1
RT11
Rising trigger event configuration of line 11
11
1
RT12
Rising trigger event configuration of line 12
12
1
RT13
Rising trigger event configuration of line 13
13
1
RT14
Rising trigger event configuration of line 14
14
1
RT15
Rising trigger event configuration of line 15
15
1
RT16
Rising trigger event configuration of line 16
16
1
RT17
Rising trigger event configuration of line 17
17
1
RT19
Rising trigger event configuration of line 19
19
1
RT2
Rising trigger event configuration of line 2
2
1
RT20
Rising trigger event configuration of line 20
20
1
RT21
Rising trigger event configuration of line 21
21
1
RT22
Rising trigger event configuration of line 22
22
1
RT3
Rising trigger event configuration of line 3
3
1
RT4
Rising trigger event configuration of line 4
4
1
RT5
Rising trigger event configuration of line 5
5
1
RT6
Rising trigger event configuration of line 6
6
1
RT7
Rising trigger event configuration of line 7
7
1
RT8
Rising trigger event configuration of line 8
8
1
RT9
Rising trigger event configuration of line 9
9
1
SWIER
SWIER
Software interrupt event register (EXTI_SWIER)
0x10
32
read-write
n
0x0
0x0
SWI0
Software Interrupt on line 0
0
1
SWI1
Software Interrupt on line 1
1
1
SWI10
Software Interrupt on line 10
10
1
SWI11
Software Interrupt on line 11
11
1
SWI12
Software Interrupt on line 12
12
1
SWI13
Software Interrupt on line 13
13
1
SWI14
Software Interrupt on line 14
14
1
SWI15
Software Interrupt on line 15
15
1
SWI16
Software Interrupt on line 16
16
1
SWI17
Software Interrupt on line 17
17
1
SWI19
Software Interrupt on line 19
19
1
SWI2
Software Interrupt on line 2
2
1
SWI20
Software Interrupt on line 20
20
1
SWI21
Software Interrupt on line 21
21
1
SWI22
Software Interrupt on line 22
22
1
SWI3
Software Interrupt on line 3
3
1
SWI4
Software Interrupt on line 4
4
1
SWI5
Software Interrupt on line 5
5
1
SWI6
Software Interrupt on line 6
6
1
SWI7
Software Interrupt on line 7
7
1
SWI8
Software Interrupt on line 8
8
1
SWI9
Software Interrupt on line 9
9
1
Firewall
Firewall
Firewall
0x0
0x0
0x400
registers
n
FIREWALL_CR
FIREWALL_CR
Configuration register
0x20
32
read-write
n
0x0
0x0
FPA
Firewall pre alarm
0
1
VDE
Volatile data execution
2
1
VDS
Volatile data shared
1
1
FIREWALL_CSL
FIREWALL_CSL
Code segment length
0x4
32
read-write
n
0x0
0x0
LENG
code segment length
8
14
FIREWALL_CSSA
FIREWALL_CSSA
Code segment start address
0x0
32
read-write
n
0x0
0x0
ADD
code segment start address
8
16
FIREWALL_NVDSL
FIREWALL_NVDSL
Non-volatile data segment length
0xC
32
read-write
n
0x0
0x0
LENG
Non-volatile data segment length
8
14
FIREWALL_NVDSSA
FIREWALL_NVDSSA
Non-volatile data segment start address
0x8
32
read-write
n
0x0
0x0
ADD
Non-volatile data segment start address
8
16
FIREWALL_VDSL
FIREWALL_VDSL
Volatile data segment length
0x14
32
read-write
n
0x0
0x0
LENG
Non-volatile data segment length
6
10
FIREWALL_VDSSA
FIREWALL_VDSSA
Volatile data segment start address
0x10
32
read-write
n
0x0
0x0
ADD
Volatile data segment start address
6
10
Flash
Flash
Flash
0x0
0x0
0x400
registers
n
FLASH
Flash global interrupt
3
ACR
ACR
Access control register
0x0
32
read-write
n
0x0
0x0
DESAB_BUF
Disable Buffer
5
1
DISAB_BUF
Disable Buffer
5
1
LATENCY
Latency
0
1
PRE_READ
Pre-read data address
6
1
PRFTEN
Prefetch enable
1
1
RUN_PD
Flash mode during Run
4
1
SLEEP_PD
Flash mode during Sleep
3
1
OBR
OBR
Option byte register
0x1C
32
read-only
n
0x0
0x0
BOR_LEV
BOR_LEV
16
4
RDPRT
Read protection
0
8
SPRMOD
Selection of protection mode of WPR bits
8
1
OPTKEYR
OPTKEYR
Option byte key register
0x14
32
write-only
n
0x0
0x0
OPTKEYR
Option byte key
0
32
OPTR
OPTR
Option byte register
0x1C
32
read-only
n
0x0
0x0
BFB2
BFB2
23
1
BOR_LEV
BOR_LEV
16
4
nBOOT1
nBOOT1
31
1
nRST_STDBY
nRST_STDBY
22
1
nRST_STOP
nRST_STOP
21
1
RDPROT
Read protection
0
8
WDG_SW
WDG_SW
20
1
WPRMOD
WPRMOD
8
1
PDKEYR
PDKEYR
Power down key register
0x8
32
write-only
n
0x0
0x0
PDKEYR
RUN_PD in FLASH_ACR key
0
32
PECR
PECR
Program/erase control register
0x4
32
read-write
n
0x0
0x0
DATA
Data EEPROM selection
4
1
EOPIE
End of programming interrupt enable
16
1
ERASE
Page or Double Word erase mode
9
1
ERRIE
Error interrupt enable
17
1
FIX
Fixed time data write for Byte, Half Word and Word programming
8
1
FPRG
Half Page/Double Word programming mode
10
1
FTDW
Fixed time data write for Byte, Half Word and Word programming
8
1
NZDISABLE
Non-Zero check notification disable
23
1
OBL_LAUNCH
Launch the option byte loading
18
1
OPTLOCK
Option bytes block lock
2
1
PARALLELBANK
Parallel bank mode
15
1
PELOCK
FLASH_PECR and data EEPROM lock
0
1
PRGLOCK
Program memory lock
1
1
PROG
Program memory selection
3
1
PEKEYR
PEKEYR
Program/erase key register
0xC
32
write-only
n
0x0
0x0
PEKEYR
FLASH_PEC and data EEPROM key
0
32
PRGKEYR
PRGKEYR
Program memory key register
0x10
32
write-only
n
0x0
0x0
PRGKEYR
Program memory key
0
32
SR
SR
Status register
0x18
32
read-write
n
0x0
0x0
BSY
Write/erase operations in progress
0
1
read-only
ENDHV
End of high voltage
2
1
read-only
EOP
End of operation
1
1
read-only
FWWERR
FWWERR
17
1
read-write
NOTZEROERR
NOTZEROERR
16
1
read-write
OPTVERR
Option validity error
11
1
read-write
PGAERR
Programming alignment error
9
1
read-write
RDERR
RDERR
13
1
read-write
READY
Flash memory module ready after low power mode
3
1
read-only
SIZERR
Size error
10
1
read-write
WRPERR
Write protected error
8
1
read-write
WRPR
WRPR
Write protection register
0x20
32
read-write
n
0x0
0x0
WRP
Write protection
0
16
WRPROT1
WRPROT1
Write protection register
0x20
32
read-only
n
0x0
0x0
WRPROT1
Write protection
0
32
WRPROT2
WRPROT2
Write protection register
0x80
32
read-only
n
0x0
0x0
WRPROT2
Write protection
0
16
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
GPIOD
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
GPIOE
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
GPIOH
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFSEL10
Alternate function selection for port x pin y (y = 8..15)
8
4
AFSEL11
Alternate function selection for port x pin y (y = 8..15)
12
4
AFSEL12
Alternate function selection for port x pin y (y = 8..15)
16
4
AFSEL13
Alternate function selection for port x pin y (y = 8..15)
20
4
AFSEL14
Alternate function selection for port x pin y (y = 8..15)
24
4
AFSEL15
Alternate function selection for port x pin y (y = 8..15)
28
4
AFSEL8
Alternate function selection for port x pin y (y = 8..15)
0
4
AFSEL9
Alternate function selection for port x pin y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFSEL0
Alternate function selection for port x pin y (y = 0..7)
0
4
AFSEL1
Alternate function selection for port x pin y (y = 0..7)
4
4
AFSEL2
Alternate function selection for port x pin y (y = 0..7)
8
4
AFSEL3
Alternate function selection for port x pin y (y = 0..7)
12
4
AFSEL4
Alternate function selection for port x pin y (y = 0..7)
16
4
AFSEL5
Alternate function selection for port x pin y (y = 0..7)
20
4
AFSEL6
Alternate function selection for port x pin y (y = 0..7)
24
4
AFSEL7
Alternate function selection for port x pin y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0x0
BR0
Port x Reset bit y (y= 0 .. 15)
0
1
BR1
Port x Reset bit y (y= 0 .. 15)
1
1
BR10
Port x Reset bit y (y= 0 .. 15)
10
1
BR11
Port x Reset bit y (y= 0 .. 15)
11
1
BR12
Port x Reset bit y (y= 0 .. 15)
12
1
BR13
Port x Reset bit y (y= 0 .. 15)
13
1
BR14
Port x Reset bit y (y= 0 .. 15)
14
1
BR15
Port x Reset bit y (y= 0 .. 15)
15
1
BR2
Port x Reset bit y (y= 0 .. 15)
2
1
BR3
Port x Reset bit y (y= 0 .. 15)
3
1
BR4
Port x Reset bit y (y= 0 .. 15)
4
1
BR5
Port x Reset bit y (y= 0 .. 15)
5
1
BR6
Port x Reset bit y (y= 0 .. 15)
6
1
BR7
Port x Reset bit y (y= 0 .. 15)
7
1
BR8
Port x Reset bit y (y= 0 .. 15)
8
1
BR9
Port x Reset bit y (y= 0 .. 15)
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x reset bit y (y = 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ID0
Port input data bit (y = 0..15)
0
1
ID1
Port input data bit (y = 0..15)
1
1
ID10
Port input data bit (y = 0..15)
10
1
ID11
Port input data bit (y = 0..15)
11
1
ID12
Port input data bit (y = 0..15)
12
1
ID13
Port input data bit (y = 0..15)
13
1
ID14
Port input data bit (y = 0..15)
14
1
ID15
Port input data bit (y = 0..15)
15
1
ID2
Port input data bit (y = 0..15)
2
1
ID3
Port input data bit (y = 0..15)
3
1
ID4
Port input data bit (y = 0..15)
4
1
ID5
Port input data bit (y = 0..15)
5
1
ID6
Port input data bit (y = 0..15)
6
1
ID7
Port input data bit (y = 0..15)
7
1
ID8
Port input data bit (y = 0..15)
8
1
ID9
Port input data bit (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODE0
Port x configuration bits (y = 0..15)
0
2
MODE1
Port x configuration bits (y = 0..15)
2
2
MODE10
Port x configuration bits (y = 0..15)
20
2
MODE11
Port x configuration bits (y = 0..15)
22
2
MODE12
Port x configuration bits (y = 0..15)
24
2
MODE13
Port x configuration bits (y = 0..15)
26
2
MODE14
Port x configuration bits (y = 0..15)
28
2
MODE15
Port x configuration bits (y = 0..15)
30
2
MODE2
Port x configuration bits (y = 0..15)
4
2
MODE3
Port x configuration bits (y = 0..15)
6
2
MODE4
Port x configuration bits (y = 0..15)
8
2
MODE5
Port x configuration bits (y = 0..15)
10
2
MODE6
Port x configuration bits (y = 0..15)
12
2
MODE7
Port x configuration bits (y = 0..15)
14
2
MODE8
Port x configuration bits (y = 0..15)
16
2
MODE9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OD0
Port output data bit (y = 0..15)
0
1
OD1
Port output data bit (y = 0..15)
1
1
OD10
Port output data bit (y = 0..15)
10
1
OD11
Port output data bit (y = 0..15)
11
1
OD12
Port output data bit (y = 0..15)
12
1
OD13
Port output data bit (y = 0..15)
13
1
OD14
Port output data bit (y = 0..15)
14
1
OD15
Port output data bit (y = 0..15)
15
1
OD2
Port output data bit (y = 0..15)
2
1
OD3
Port output data bit (y = 0..15)
3
1
OD4
Port output data bit (y = 0..15)
4
1
OD5
Port output data bit (y = 0..15)
5
1
OD6
Port output data bit (y = 0..15)
6
1
OD7
Port output data bit (y = 0..15)
7
1
OD8
Port output data bit (y = 0..15)
8
1
OD9
Port output data bit (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEED0
Port x configuration bits (y = 0..15)
0
2
OSPEED1
Port x configuration bits (y = 0..15)
2
2
OSPEED10
Port x configuration bits (y = 0..15)
20
2
OSPEED11
Port x configuration bits (y = 0..15)
22
2
OSPEED12
Port x configuration bits (y = 0..15)
24
2
OSPEED13
Port x configuration bits (y = 0..15)
26
2
OSPEED14
Port x configuration bits (y = 0..15)
28
2
OSPEED15
Port x configuration bits (y = 0..15)
30
2
OSPEED2
Port x configuration bits (y = 0..15)
4
2
OSPEED3
Port x configuration bits (y = 0..15)
6
2
OSPEED4
Port x configuration bits (y = 0..15)
8
2
OSPEED5
Port x configuration bits (y = 0..15)
10
2
OSPEED6
Port x configuration bits (y = 0..15)
12
2
OSPEED7
Port x configuration bits (y = 0..15)
14
2
OSPEED8
Port x configuration bits (y = 0..15)
16
2
OSPEED9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPD0
Port x configuration bits (y = 0..15)
0
2
PUPD1
Port x configuration bits (y = 0..15)
2
2
PUPD10
Port x configuration bits (y = 0..15)
20
2
PUPD11
Port x configuration bits (y = 0..15)
22
2
PUPD12
Port x configuration bits (y = 0..15)
24
2
PUPD13
Port x configuration bits (y = 0..15)
26
2
PUPD14
Port x configuration bits (y = 0..15)
28
2
PUPD15
Port x configuration bits (y = 0..15)
30
2
PUPD2
Port x configuration bits (y = 0..15)
4
2
PUPD3
Port x configuration bits (y = 0..15)
6
2
PUPD4
Port x configuration bits (y = 0..15)
8
2
PUPD5
Port x configuration bits (y = 0..15)
10
2
PUPD6
Port x configuration bits (y = 0..15)
12
2
PUPD7
Port x configuration bits (y = 0..15)
14
2
PUPD8
Port x configuration bits (y = 0..15)
16
2
PUPD9
Port x configuration bits (y = 0..15)
18
2
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1
I2C1 global interrupt
23
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
I2C2
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C2
I2C2 global interrupt
24
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
I2C3
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C3
I2C3 global interrupt
21
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0x0
KEY
Key value (write only, read 0x0000)
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
WVU
Watchdog counter window value update
2
1
WINR
WINR
Window register
0x10
32
read-write
n
0x0
0x0
WIN
Watchdog counter window value
0
12
LPTIM
Low power timer
LPTIM
0x0
0x0
0x400
registers
n
LPTIM1
LPTIMER1 interrupt through EXTI29
13
ARR
ARR
Autoreload Register
0x18
32
read-write
n
0x0
0x0
ARR
Auto reload value.
0
16
CFGR
CFGR
Configuration Register
0xC
32
read-write
n
0x0
0x0
CKFLT
Configurable digital filter for external clock
3
2
CKPOL
Clock Polarity
1
2
CKSEL
Clock selector
0
1
COUNTMODE
counter mode enabled
23
1
ENC
Encoder mode enable
24
1
PRELOAD
Registers update mode
22
1
PRESC
Clock prescaler
9
3
TIMOUT
Timeout enable
19
1
TRGFLT
Configurable digital filter for trigger
6
2
TRIGEN
Trigger enable and polarity
17
2
TRIGSEL
Trigger selector
13
3
WAVE
Waveform shape
20
1
WAVPOL
Waveform shape polarity
21
1
CMP
CMP
Compare Register
0x14
32
read-write
n
0x0
0x0
CMP
Compare value.
0
16
CNT
CNT
Counter Register
0x1C
32
read-only
n
0x0
0x0
CNT
Counter value.
0
16
CR
CR
Control Register
0x10
32
read-write
n
0x0
0x0
CNTSTRT
Timer start in continuous mode
2
1
ENABLE
LPTIM Enable
0
1
SNGSTRT
LPTIM start in single mode
1
1
ICR
ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0x0
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0x0
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0x0
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
UP
Counter direction change down to up
5
1
LPUART1
Lower power Universal asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
BRR
BRR
0
20
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
MSBFIRST
Most significant bit first
19
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
FE
FE
1
1
IDLE
IDLE
4
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
MPU
Memory protection unit
MPU
0x0
0x0
0x15
registers
n
CTRL
MPU_CTRL
MPU control register
0x4
32
read-write
n
0x0
0x0
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault
1
1
PRIVDEFENA
Enable priviliged software access to default memory map
2
1
RASR
MPU_RASR
MPU region attribute and size register
0x10
32
read-write
n
0x0
0x0
AP
Access permission
24
3
B
memory attribute
16
1
C
memory attribute
17
1
ENABLE
Region enable bit.
0
1
S
Shareable memory attribute
18
1
SIZE
Size of the MPU protection region
1
5
SRD
Subregion disable bits
8
8
TEX
memory attribute
19
3
XN
Instruction access disable bit
28
1
RBAR
MPU_RBAR
MPU region base address register
0xC
32
read-write
n
0x0
0x0
ADDR
Region base address field
5
27
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
RNR
MPU_RNR
MPU region number register
0x8
32
read-write
n
0x0
0x0
REGION
MPU region
0
8
TYPER
MPU_TYPER
MPU type register
0x0
32
read-only
n
0x0
0x0
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction regions
16
8
SEPARATE
Separate flag
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x33D
registers
n
ICER
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR
ICPR
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register 0
0x300
32
read-write
n
0x0
0x0
PRI_0
priority for interrupt 0
0
8
PRI_1
priority for interrupt 1
8
8
PRI_2
priority for interrupt 2
16
8
PRI_3
priority for interrupt 3
24
8
IPR1
IPR1
Interrupt Priority Register 1
0x304
32
read-write
n
0x0
0x0
PRI_4
priority for interrupt n
0
8
PRI_5
priority for interrupt n
8
8
PRI_6
priority for interrupt n
16
8
PRI_7
priority for interrupt n
24
8
IPR2
IPR2
Interrupt Priority Register 2
0x308
32
read-write
n
0x0
0x0
PRI_10
priority for interrupt n
16
8
PRI_11
priority for interrupt n
24
8
PRI_8
priority for interrupt n
0
8
PRI_9
priority for interrupt n
8
8
IPR3
IPR3
Interrupt Priority Register 3
0x30C
32
read-write
n
0x0
0x0
PRI_12
priority for interrupt n
0
8
PRI_13
priority for interrupt n
8
8
PRI_14
priority for interrupt n
16
8
PRI_15
priority for interrupt n
24
8
IPR4
IPR4
Interrupt Priority Register 4
0x310
32
read-write
n
0x0
0x0
PRI_16
priority for interrupt n
0
8
PRI_17
priority for interrupt n
8
8
PRI_18
priority for interrupt n
16
8
PRI_19
priority for interrupt n
24
8
IPR5
IPR5
Interrupt Priority Register 5
0x314
32
read-write
n
0x0
0x0
PRI_20
priority for interrupt n
0
8
PRI_21
priority for interrupt n
8
8
PRI_22
priority for interrupt n
16
8
PRI_23
priority for interrupt n
24
8
IPR6
IPR6
Interrupt Priority Register 6
0x318
32
read-write
n
0x0
0x0
PRI_24
priority for interrupt n
0
8
PRI_25
priority for interrupt n
8
8
PRI_26
priority for interrupt n
16
8
PRI_27
priority for interrupt n
24
8
IPR7
IPR7
Interrupt Priority Register 7
0x31C
32
read-write
n
0x0
0x0
PRI_28
priority for interrupt n
0
8
PRI_29
priority for interrupt n
8
8
PRI_30
priority for interrupt n
16
8
PRI_31
priority for interrupt n
24
8
ISER
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR
ISPR
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
CR
CR
power control register
0x0
32
read-write
n
0x0
0x0
CSBF
Clear standby flag
3
1
CWUF
Clear wakeup flag
2
1
DBP
Disable backup domain write protection
8
1
DS_EE_KOFF
Deep sleep mode with Flash memory kept off
13
1
FWU
Fast wakeup
10
1
LPDS
Low-power deep sleep
0
1
LPRUN
Low power run mode
14
1
PDDS
Power down deepsleep
1
1
PLS
PVD level selection
5
3
PVDE
Power voltage detector enable
4
1
ULP
Ultra-low-power mode
9
1
VOS
Voltage scaling range selection
11
2
CSR
CSR
power control/status register
0x4
32
read-write
n
0x0
0x0
BRE
Backup regulator enable
9
1
read-write
BRR
Backup regulator ready
3
1
read-only
EWUP
Enable WKUP pin
8
1
read-write
PVDO
PVD output
2
1
read-only
REGLPF
Regulator LP flag
5
1
read-only
SBF
Standby flag
1
1
read-only
VOSF
Voltage Scaling select flag
4
1
read-only
WUF
Wakeup flag
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC global interrupt
4
AHBENR
AHBENR
AHB peripheral clock enable register
0x30
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable bit
12
1
CRYPEN
Crypto clock enable bit
24
1
DMAEN
DMA clock enable bit
0
1
MIFEN
NVM interface clock enable bit
8
1
AHBRSTR
AHBRSTR
AHB peripheral reset register
0x20
32
read-write
n
0x0
0x0
CRCRST
Test integration module reset
12
1
CRYPRST
Crypto module reset
24
1
DMARST
DMA reset
0
1
MIFRST
Memory interface reset
8
1
AHBSMENR
AHBSMENR
AHB peripheral clock enable in sleep mode register
0x40
32
read-write
n
0x0
0x0
CRCSMEN
CRC clock enable during sleep mode bit
12
1
CRYPTSMEN
Crypto clock enable during sleep mode bit
24
1
DMASMEN
DMA clock enable during sleep mode bit
0
1
MIFSMEN
NVM interface clock enable during sleep mode bit
8
1
SRAMSMEN
SRAM interface clock enable during sleep mode bit
9
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register
0x38
32
read-write
n
0x0
0x0
I2C1EN
I2C1 clock enable bit
21
1
I2C2EN
I2C2 clock enable bit
22
1
I2C3EN
I2C3 clock enable bit
30
1
LPTIM1EN
Low power timer clock enable bit
31
1
LPUART1EN
LPUART1 clock enable bit
18
1
PWREN
Power interface clock enable bit
28
1
SPI2EN
SPI2 clock enable bit
14
1
TIM2EN
Timer2 clock enable bit
0
1
TIM3EN
Timer 3 clock enbale bit
2
1
TIM6EN
Timer 6 clock enable bit
4
1
TIM7EN
Timer 7 clock enable bit
5
1
USART2EN
UART2 clock enable bit
17
1
USART4EN
USART4 clock enable bit
19
1
USART5EN
USART5 clock enable bit
20
1
WWDGEN
Window watchdog clock enable bit
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x28
32
read-write
n
0x0
0x0
CRCRST
CRC reset
27
1
I2C1RST
I2C1 reset
21
1
I2C2RST
I2C2 reset
22
1
I2C3
I2C3 reset
30
1
LPTIM1RST
Low power timer reset
31
1
LPUART1RST
LPUART1 reset
18
1
PWRRST
Power interface reset
28
1
SPI2RST
SPI2 reset
14
1
TIM2RST
Timer 2 reset
0
1
TIM3RST
Timer 3 reset
1
1
TIM6RST
Timer 6 reset
4
1
TIM7RST
Timer 7 reset
5
1
USART2RST
USART2 reset
17
1
USART4RST
USART4 reset
19
1
USART5RST
USART5 reset
20
1
WWDGRST
Window watchdog reset
11
1
APB1SMENR
APB1SMENR
APB1 peripheral clock enable in sleep mode register
0x48
32
read-write
n
0x0
0x0
CRSSMEN
Clock recovery system clock enable during sleep mode bit
27
1
I2C1SMEN
I2C1 clock enable during sleep mode bit
21
1
I2C2SMEN
I2C2 clock enable during sleep mode bit
22
1
I2C3SMEN
I2C3 clock enable during sleep mode bit
30
1
LPTIM1SMEN
Low power timer clock enable during sleep mode bit
31
1
LPUART1SMEN
LPUART1 clock enable during sleep mode bit
18
1
PWRSMEN
Power interface clock enable during sleep mode bit
28
1
SPI2SMEN
SPI2 clock enable during sleep mode bit
14
1
TIM2SMEN
Timer2 clock enable during sleep mode bit
0
1
TIM3SMEN
Timer 3 clock enable during sleep mode bit
1
1
TIM6SMEN
Timer 6 clock enable during sleep mode bit
4
1
TIM7SMEN
Timer 7 clock enable during sleep mode bit
5
1
USART2SMEN
UART2 clock enable during sleep mode bit
17
1
USART4SMEN
USART4 clock enabe during sleep mode bit
19
1
USART5SMEN
USART5 clock enable during sleep mode bit
20
1
WWDGSMEN
Window watchdog clock enable during sleep mode bit
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register
0x34
32
read-write
n
0x0
0x0
ADCEN
ADC clock enable bit
9
1
DBGEN
DBG clock enable bit
22
1
FWEN
Firewall clock enable bit
7
1
SPI1EN
SPI1 clock enable bit
12
1
SYSCFGEN
System configuration controller clock enable bit
0
1
TIM21EN
TIM21 timer clock enable bit
2
1
TIM22EN
TIM22 timer clock enable bit
5
1
USART1EN
USART1 clock enable bit
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x24
32
read-write
n
0x0
0x0
ADCRST
ADC interface reset
9
1
DBGRST
DBG reset
22
1
SPI1RST
SPI 1 reset
12
1
SYSCFGRST
System configuration controller reset
0
1
TIM21RST
TIM21 timer reset
2
1
TIM22RST
TIM22 timer reset
5
1
USART1RST
USART1 reset
14
1
APB2SMENR
APB2SMENR
APB2 peripheral clock enable in sleep mode register
0x44
32
read-write
n
0x0
0x0
ADCSMEN
ADC clock enable during sleep mode bit
9
1
DBGSMEN
DBG clock enable during sleep mode bit
22
1
SPI1SMEN
SPI1 clock enable during sleep mode bit
12
1
SYSCFGSMEN
System configuration controller clock enable during sleep mode bit
0
1
TIM21SMEN
TIM21 timer clock enable during sleep mode bit
2
1
TIM22SMEN
TIM22 timer clock enable during sleep mode bit
5
1
USART1SMEN
USART1 clock enable during sleep mode bit
14
1
CCIPR
CCIPR
Clock configuration register
0x4C
32
read-write
n
0x0
0x0
I2C1SEL0
I2C1SEL0
12
1
I2C1SEL1
I2C1 clock source selection bits
13
1
I2C3SEL0
I2C3 clock source selection bits
16
1
I2C3SEL1
I2C3 clock source selection bits
17
1
LPTIM1SEL0
LPTIM1SEL0
18
1
LPTIM1SEL1
Low Power Timer clock source selection bits
19
1
LPUART1SEL0
LPUART1SEL0
10
1
LPUART1SEL1
LPUART1 clock source selection bits
11
1
USART1SEL0
USART1SEL0
0
1
USART1SEL1
USART1 clock source selection bits
1
1
USART2SEL0
USART2SEL0
2
1
USART2SEL1
USART2 clock source selection bits
3
1
CFGR
CFGR
Clock configuration register
0xC
32
read-write
n
0x0
0x0
HPRE
AHB prescaler
4
4
read-write
MCOPRE
Microcontroller clock output prescaler
28
3
read-write
MCOSEL
Microcontroller clock output selection
24
3
read-write
PLLDIV
PLL output division
22
2
read-write
PLLMUL
PLL multiplication factor
18
4
read-write
PLLSRC
PLL entry clock source
16
1
read-write
PPRE1
APB low-speed prescaler (APB1)
8
3
read-write
PPRE2
APB high-speed prescaler (APB2)
11
3
read-write
STOPWUCK
Wake-up from stop clock selection
15
1
read-write
SW
System clock switch
0
2
read-write
SWS
System clock switch status
2
2
read-only
CICR
CICR
Clock interrupt clear register
0x18
32
read-only
n
0x0
0x0
CSSHSEC
Clock Security System Interrupt clear
8
1
CSSLSEC
LSE Clock Security System Interrupt clear
7
1
HSERDYC
HSE ready Interrupt clear
3
1
HSI16RDYC
HSI16 ready Interrupt clear
2
1
LSERDYC
LSE ready Interrupt clear
1
1
LSIRDYC
LSI ready Interrupt clear
0
1
MSIRDYC
MSI ready Interrupt clear
5
1
PLLRDYC
PLL ready Interrupt clear
4
1
CIER
CIER
Clock interrupt enable register
0x10
32
read-only
n
0x0
0x0
CSSLSE
LSE CSS interrupt flag
7
1
HSERDYIE
HSE ready interrupt flag
3
1
HSI16RDYIE
HSI16 ready interrupt flag
2
1
LSERDYIE
LSE ready interrupt flag
1
1
LSIRDYIE
LSI ready interrupt flag
0
1
MSIRDYIE
MSI ready interrupt flag
5
1
PLLRDYIE
PLL ready interrupt flag
4
1
CIFR
CIFR
Clock interrupt flag register
0x14
32
read-only
n
0x0
0x0
CSSHSEF
Clock Security System Interrupt flag
8
1
CSSLSEF
LSE Clock Security System Interrupt flag
7
1
HSERDYF
HSE ready interrupt flag
3
1
HSI16RDYF
HSI16 ready interrupt flag
2
1
LSERDYF
LSE ready interrupt flag
1
1
LSIRDYF
LSI ready interrupt flag
0
1
MSIRDYF
MSI ready interrupt flag
5
1
PLLRDYF
PLL ready interrupt flag
4
1
CR
CR
Clock control register
0x0
32
read-write
n
0x0
0x0
CSSLSEON
Clock security system on HSE enable bit
19
1
read-write
HSEBYP
HSE clock bypass bit
18
1
read-write
HSEON
HSE clock enable bit
16
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSI16DIVEN
HSI16DIVEN
3
1
read-write
HSI16DIVF
HSI16DIVF
4
1
read-only
HSI16KERON
High-speed internal clock enable bit for some IP kernels
1
1
read-only
HSI16ON
16 MHz high-speed internal clock enable
0
1
read-write
HSI16OUTEN
16 MHz high-speed internal clock output enable
5
1
read-write
HSI16RDYF
Internal high-speed clock ready flag
2
1
read-write
MSION
MSI clock enable bit
8
1
read-write
MSIRDY
MSI clock ready flag
9
1
read-only
PLLON
PLL enable bit
24
1
read-write
PLLRDY
PLL clock ready flag
25
1
read-only
RTCPRE
TC/LCD prescaler
20
2
read-write
CSR
CSR
Control and status register
0x50
32
read-write
n
0x0
0x0
CSSLSED
CSS on LSE failure detection flag
14
1
read-write
CSSLSEON
CSSLSEON
13
1
read-write
FWRSTF
Firewall reset flag
24
1
read-write
IWDGRSTF
Independent watchdog reset flag
29
1
read-write
LPWRSTF
Low-power reset flag
31
1
read-write
LSEBYP
External low-speed oscillator bypass bit
10
1
read-write
LSEDRV
LSEDRV
11
2
read-write
LSEON
External low-speed oscillator enable bit
8
1
read-write
LSERDY
External low-speed oscillator ready bit
9
1
read-only
LSIIWDGLP
LSI clock input to IWDG in Ultra-low-power mode (Stop and Standby) enable bit
2
1
read-write
LSION
Internal low-speed oscillator enable
0
1
read-write
LSIRDY
Internal low-speed oscillator ready bit
1
1
read-only
OBLRSTF
OBLRSTF
25
1
read-write
PINRSTF
PIN reset flag
26
1
read-write
PORRSTF
POR/PDR reset flag
27
1
read-write
RMVF
Remove reset flag
23
1
read-write
RTCEN
RTC clock enable bit
18
1
read-write
RTCRST
RTC software reset bit
19
1
read-write
RTCSEL
RTC and LCD clock source selection bits
16
2
read-write
SFTRSTF
Software reset flag
28
1
read-write
WWDGRSTF
Window watchdog reset flag
30
1
read-write
ICSCR
ICSCR
Internal clock sources calibration register
0x4
32
read-write
n
0x0
0x0
HSI16CAL
nternal high speed clock calibration
0
8
read-only
HSI16TRIM
High speed internal clock trimming
8
5
read-write
MSICAL
MSI clock calibration
16
8
read-only
MSIRANGE
MSI clock ranges
13
3
read-write
MSITRIM
MSI clock trimming
24
8
read-write
IOPENR
IOPENR
GPIO clock enable register
0x2C
32
read-write
n
0x0
0x0
IOPAEN
IO port A clock enable bit
0
1
IOPBEN
IO port B clock enable bit
1
1
IOPCEN
IO port A clock enable bit
2
1
IOPDEN
I/O port D clock enable bit
3
1
IOPEEN
IO port E clock enable bit
4
1
IOPHEN
I/O port H clock enable bit
7
1
IOPRSTR
IOPRSTR
GPIO reset register
0x1C
32
read-write
n
0x0
0x0
IOPARST
I/O port A reset
0
1
IOPBRST
I/O port B reset
1
1
IOPCRST
I/O port A reset
2
1
IOPDRST
I/O port D reset
3
1
IOPERST
I/O port E reset
4
1
IOPHRST
I/O port H reset
7
1
IOPSMEN
IOPSMEN
GPIO clock enable in sleep mode register
0x3C
32
read-write
n
0x0
0x0
IOPASMEN
Port A clock enable during Sleep mode bit
0
1
IOPBSMEN
Port B clock enable during Sleep mode bit
1
1
IOPCSMEN
Port C clock enable during Sleep mode bit
2
1
IOPDSMEN
Port D clock enable during Sleep mode bit
3
1
IOPESMEN
Port E clock enable during Sleep mode bit
4
1
IOPHSMEN
Port H clock enable during Sleep mode bit
7
1
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC
RTC global interrupt
2
ALRMAR
ALRMAR
RTC alarm A register
0x1C
32
read-write
n
0x0
0x0
DT
Date tens in BCD format.
28
2
DU
Date units or day in BCD format.
24
4
HT
Hour tens in BCD format.
20
2
HU
Hour units in BCD format.
16
4
MNT
Minute tens in BCD format.
12
3
MNU
Minute units in BCD format.
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format.
4
3
SU
Second units in BCD format.
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
RTC alarm A sub second register
0x44
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
ALRMBR
ALRMBR
RTC alarm B register
0x20
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
RTC alarm B sub second register
0x48
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
BKP0R
BKP0R
RTC backup registers
0x50
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP1R
BKP1R
RTC backup registers
0x54
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP2R
BKP2R
RTC backup registers
0x58
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP3R
BKP3R
RTC backup registers
0x5C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP4R
BKP4R
RTC backup registers
0x60
32
read-write
n
0x0
0x0
BKP
BKP
0
32
CALR
CALR
RTC calibration register
0x3C
32
read-write
n
0x0
0x0
CALM
Calibration minus
0
9
CALP
Increase frequency of RTC by 488.5 ppm
15
1
CALW16
Use a 16-second calibration cycle period
13
1
CALW8
Use an 8-second calibration cycle period
14
1
CR
CR
RTC control register
0x8
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
write-only
ALRAE
Alarm A enable
8
1
read-write
ALRAIE
Alarm A interrupt enable
12
1
read-write
ALRBE
Alarm B enable
9
1
read-write
ALRBIE
Alarm B interrupt enable
13
1
read-write
BKP
Backup
18
1
read-write
BYPSHAD
Bypass the shadow registers
5
1
read-write
COE
Calibration output enable
23
1
read-write
COSEL
Calibration output selection
19
1
read-write
FMT
Hour format
6
1
read-write
OSEL
Output selection
21
2
read-write
POL
Output polarity
20
1
read-write
REFCKON
RTC_REFIN reference clock detection enable (50 or 60 Hz)
4
1
read-write
SUB1H
Subtract 1 hour (winter time change)
17
1
write-only
TSE
timestamp enable
11
1
read-write
TSEDGE
Time-stamp event active edge
3
1
read-write
TSIE
Time-stamp interrupt enable
15
1
read-write
WUCKSEL
Wakeup clock selection
0
3
read-write
WUTE
Wakeup timer enable
10
1
read-write
WUTIE
Wakeup timer interrupt enable
14
1
read-write
DR
DR
RTC date register
0x4
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ISR
ISR
RTC initialization and status register
0xC
32
read-write
n
0x0
0x0
ALRAF
Alarm A flag
8
1
read-write
ALRAWF
Alarm A write flag
0
1
read-only
ALRBF
Alarm B flag
9
1
read-write
ALRBWF
Alarm B write flag
1
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-only
TAMP1F
RTC_TAMP1 detection flag
13
1
read-write
TAMP2F
RTC_TAMP2 detection flag
14
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
OR
OR
option register
0x4C
32
read-write
n
0x0
0x0
RTC_ALARM_TYPE
RTC_ALARM on PC13 output type
0
1
RTC_OUT_RMP
RTC_ALARM on PC13 output type
1
1
PRER
PRER
RTC prescaler register
0x10
32
read-write
n
0x0
0x0
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
16
SHIFTR
SHIFTR
RTC shift control register
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SSR
SSR
RTC sub second register
0x28
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TAMPCR
TAMPCR
RTC tamper configuration register
0x40
32
read-write
n
0x0
0x0
TAMP1E
RTC_TAMP1 input detection enable
0
1
TAMP1IE
Tamper 1 interrupt enable
16
1
TAMP1MF
Tamper 1 mask flag
18
1
TAMP1NOERASE
Tamper 1 no erase
17
1
TAMP1TRG
Active level for RTC_TAMP1 input
1
1
TAMP2E
RTC_TAMP2 input detection enable
3
1
TAMP2IE
Tamper 2 interrupt enable
19
1
TAMP2MF
Tamper 2 mask flag
21
1
TAMP2NOERASE
Tamper 2 no erase
20
1
TAMP2_TRG
Active level for RTC_TAMP2 input
4
1
TAMPFLT
RTC_TAMPx filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPIE
Tamper interrupt enable
2
1
TAMPPRCH
RTC_TAMPx precharge duration
13
2
TAMPPUDIS
RTC_TAMPx pull-up disable
15
1
TAMPTS
Activate timestamp on tamper detection event
7
1
TR
TR
RTC time register
0x0
32
read-write
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
RTC timestamp date register
0x34
32
read-only
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
RTC time-stamp sub second register
0x38
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
TSTR
TSTR
RTC timestamp time register
0x30
32
read-only
n
0x0
0x0
HT
Hour tens in BCD format.
20
2
HU
Hour units in BCD format.
16
4
MNT
Minute tens in BCD format.
12
3
MNU
Minute units in BCD format.
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format.
4
3
SU
Second units in BCD format.
0
4
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0x0
KEY
Write protection key
0
8
WUTR
WUTR
RTC wakeup timer register
0x14
32
read-write
n
0x0
0x0
WUT
Wakeup auto-reload value bits
0
16
SCB
System control block
SCB
0x0
0x0
0x41
registers
n
AIRCR
AIRCR
Application interrupt and reset control register
0xC
32
read-write
n
0x0
0x0
ENDIANESS
ENDIANESS
15
1
SYSRESETREQ
SYSRESETREQ
2
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
VECTKEYSTAT
Register key
16
16
CCR
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0x0
BFHFNMIGN
BFHFNMIGN
8
1
DIV_0_TRP
DIV_0_TRP
4
1
NONBASETHRDENA
Configures how the processor enters Thread mode
0
1
STKALIGN
STKALIGN
9
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
USERSETMPEND
USERSETMPEND
1
1
CPUID
CPUID
CPUID base register
0x0
32
read-only
n
0x0
0x0
Architecture
Reads as 0xF
16
4
Implementer
Implementer code
24
8
PartNo
Part number of the processor
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
ICSR
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag
22
1
NMIPENDSET
NMI set-pending bit.
31
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
RETTOBASE
Return to base level
11
1
VECTACTIVE
Active vector
0
9
VECTPENDING
Pending vector
12
7
SCR
SCR
System control register
0x10
32
read-write
n
0x0
0x0
SEVEONPEND
Send Event on Pending bit
4
1
SLEEPDEEP
SLEEPDEEP
2
1
SLEEPONEXIT
SLEEPONEXIT
1
1
SHPR2
SHPR2
System handler priority registers
0x1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11
24
8
SHPR3
SHPR3
System handler priority registers
0x20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14
16
8
PRI_15
Priority of system handler 15
24
8
VTOR
VTOR
Vector table offset register
0x8
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset field
7
25
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1_global_interrupt
25
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
60
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPOL
Steady state clock polarity
3
1
DATLEN
Data length to be transferred
1
2
I2SCFG
I2S configuration mode
8
2
I2SE
I2S Enable
10
1
I2SMOD
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSYNC
PCM frame synchronization
7
1
I2SPR
I2SPR
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2S Linear prescaler
0
8
MCKOE
Master clock output enable
9
1
ODD
Odd factor for the prescaler
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
Channel side
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
Underrun flag
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
STK
SysTick timer
STK
0x0
0x0
0x11
registers
n
CALIB
CALIB
SysTick calibration value register
0xC
32
read-write
n
0x0
0x0
NOREF
NOREF flag. Reads as zero
31
1
SKEW
SKEW flag: Indicates whether the TENMS value is exact
30
1
TENMS
Calibration value
0
24
CSR
CSR
SysTick control and status register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request enable
1
1
CVR
CVR
SysTick current value register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current counter value
0
24
RVR
RVR
SysTick reload value register
0x4
32
read-write
n
0x0
0x0
RELOAD
RELOAD value
0
24
SYSCFG_COMP
System configuration controller and COMP register
SYSCFG
0x0
0x0
0x400
registers
n
CFGR1
CFGR1
SYSCFG configuration register 1
0x0
32
read-write
n
0x0
0x0
BOOT_MODE
Boot mode selected by the boot pins status bits
8
2
read-only
MEM_MODE
Memory mapping selection bits
0
2
read-write
CFGR2
CFGR2
SYSCFG configuration register 2
0x4
32
read-write
n
0x0
0x0
CAPA
Configuration of internal VLCD rail connection to optional external capacitor
1
3
FWDISEN
Firewall disable bit
0
1
I2C1_FMP
I2C1 Fm+ drive capability enable bit
12
1
I2C2_FMP
I2C2 Fm+ drive capability enable bit
13
1
I2C_PB6_FMP
Fm+ drive capability on PB6 enable bit
8
1
I2C_PB7_FMP
Fm+ drive capability on PB7 enable bit
9
1
I2C_PB8_FMP
Fm+ drive capability on PB8 enable bit
10
1
I2C_PB9_FMP
Fm+ drive capability on PB9 enable bit
11
1
CFGR3
CFGR3
SYSCFG configuration register 3
0x20
32
read-write
n
0x0
0x0
ENBUF_BGAP_ADC
VREFINT reference for ADC enable bit
8
1
read-write
ENBUF_SENSOR_ADC
Sensor reference for ADC enable bit
9
1
read-write
ENBUF_VREFINT_COMP
VREFINT reference for comparator 2 enable bit
12
1
read-write
ENREF_RC48MHz
VREFINT reference for 48 MHz RC oscillator enable bit
13
1
read-write
EN_BGAP
Vref Enable bit
0
1
read-write
REF_LOCK
REF_CTRL lock bit
31
1
write-only
REF_RC48MHz_RDYF
VREFINT for 48 MHz RC oscillator ready flag
26
1
read-only
SEL_VREF_OUT
BGAP_ADC connection bit
4
2
read-write
SENSOR_ADC_RDYF
Sensor for ADC ready flag
27
1
read-only
VREFINT_ADC_RDYF
VREFINT for ADC ready flag
28
1
read-only
VREFINT_COMP_RDYF
VREFINT for comparator ready flag
29
1
read-only
VREFINT_RDYF
VREFINT ready flag
30
1
read-only
COMP1_CSR
COMP1_CSR
Comparator 1 control and status register
0x18
32
read-write
n
0x0
0x0
COMP1EN
Comparator 1 enable bit
0
1
COMP1INNSEL
Comparator 1 Input Minus connection configuration bit
4
2
COMP1LOCK
COMP1_CSR register lock bit
31
1
COMP1LPTIMIN1
Comparator 1 LPTIM input propagation bit
12
1
COMP1POLARITY
Comparator 1 polarity selection bit
15
1
COMP1VALUE
Comparator 1 output status bit
30
1
COMP1WM
Comparator 1 window mode selection bit
8
1
COMP1_CTRL
COMP1_CTRL
Comparator 1 control and status register
0x18
32
read-write
n
0x0
0x0
COMP1EN
Comparator 1 enable bit
0
1
COMP1INNSEL
Comparator 1 Input Minus connection configuration bit
4
2
COMP1LOCK
COMP1_CSR register lock bit
31
1
COMP1LPTIMIN1
Comparator 1 LPTIM input propagation bit
12
1
COMP1POLARITY
Comparator 1 polarity selection bit
15
1
COMP1VALUE
Comparator 1 output status bit
30
1
COMP1WM
Comparator 1 window mode selection bit
8
1
COMP2_CSR
COMP2_CSR
Comparator 2 control and status register
0x1C
32
read-write
n
0x0
0x0
COMP2EN
Comparator 2 enable bit
0
1
COMP2INNSEL
Comparator 2 Input Minus connection configuration bit
4
3
COMP2INPSEL
Comparator 2 Input Plus connection configuration bit
8
3
COMP2LOCK
COMP2_CSR register lock bit
31
1
COMP2LPTIMIN1
Comparator 2 LPTIM input 1 propagation bit
13
1
COMP2LPTIMIN2
Comparator 2 LPTIM input 2 propagation bit
12
1
COMP2POLARITY
Comparator 2 polarity selection bit
15
1
COMP2SPEED
Comparator 2 power mode selection bit
3
1
COMP2VALUE
Comparator 2 output status bit
30
1
COMP2_CTRL
COMP2_CTRL
Comparator 2 control and status register
0x1C
32
read-write
n
0x0
0x0
COMP2EN
Comparator 2 enable bit
0
1
COMP2INNSEL
Comparator 2 Input Minus connection configuration bit
4
3
COMP2INPSEL
Comparator 2 Input Plus connection configuration bit
8
3
COMP2LOCK
COMP2_CSR register lock bit
31
1
COMP2LPTIMIN1
Comparator 2 LPTIM input 1 propagation bit
13
1
COMP2LPTIMIN2
Comparator 2 LPTIM input 2 propagation bit
12
1
COMP2POLARITY
Comparator 2 polarity selection bit
15
1
COMP2SPEED
Comparator 2 power mode selection bit
3
1
COMP2VALUE
Comparator 2 output status bit
30
1
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI x configuration (x = 0 to 3)
0
4
EXTI1
EXTI x configuration (x = 0 to 3)
4
4
EXTI2
EXTI x configuration (x = 0 to 3)
8
4
EXTI3
EXTI x configuration (x = 0 to 3)
12
4
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI x configuration (x = 4 to 7)
0
4
EXTI5
EXTI x configuration (x = 4 to 7)
4
4
EXTI6
EXTI x configuration (x = 4 to 7)
8
4
EXTI7
EXTI x configuration (x = 4 to 7)
12
4
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI10
8
4
EXTI11
EXTI x configuration (x = 8 to 11)
12
4
EXTI8
EXTI x configuration (x = 8 to 11)
0
4
EXTI9
EXTI x configuration (x = 8 to 11)
4
4
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI12
0
4
EXTI13
EXTI13
4
4
EXTI14
EXTI14
8
4
EXTI15
EXTI x configuration (x = 12 to 15)
12
4
TIM2
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
15
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0x0
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM21
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM21
TIMER21 global interrupt
20
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM21 option register
0x50
32
read-write
n
0x0
0x0
ETR_RMP
Timer21 ETR remap
0
2
TI1_RMP
Timer21 TI1
2
3
TI2_RMP
Timer21 TI2
5
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM22
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM22
TIMER22 global interrupt
22
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
TIE
Trigger interrupt enable
6
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM22 option register
0x50
32
read-write
n
0x0
0x0
ETR_RMP
Timer22 ETR remap
0
2
TI1_RMP
Timer22 TI1
2
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM3
General-purpose-timers
TIM
0x0
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
16
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0x0
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic-timers
TIM
0x0
0x0
0x400
registers
n
TIM6
TIM6 global interrupt and DAC
17
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
TIM7
Basic-timers
TIM
0x0
0x0
0x400
registers
n
TIM7
TIM7 global interrupt and DAC
18
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
UIF
Update interrupt flag
0
1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 global interrupt
27
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART4
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART4_USART5
USART4/USART5 global interrupt
14
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART5
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
USART2 global interrupt
28
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
WWDG
System window watchdog
WWDG
0x0
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
CFR
CFR
Configuration register
0x4
32
read-write
n
0x0
0x0
EWI
Early wakeup interrupt
9
1
W
7-bit window value
0
7
WDGTB0
WDGTB0
7
1
WDGTB1
Timer base
8
1
CR
CR
Control register
0x0
32
read-write
n
0x0
0x0
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1