STMicroelectronics
STM32L15x
2024.05.02
STM32L15x
8
32
ADC
Analog-to-digital converter
ADC
0x0
0x0
0x400
registers
n
CCR
CCR
ADC common control register
CR1
0x4
read-write
n
0x0
0x0
ADCPRE
ADCPRE
16
2
TSVREFE
TSVREFE
23
1
CR1
CR1
ADC control register 1
0x4
read-write
n
0x0
0x0
AWDCH
AWDCH
0
5
AWDEN
AWDEN
23
1
AWDIE
AWDIE
6
1
AWDSGL
AWDSGL
9
1
DISCEN
DISCEN
11
1
DISCNUM
DISCNUM
13
3
EOCIE
EOCIE
5
1
JAUTO
JAUTO
10
1
JAWDEN
JAWDEN
22
1
JDISCEN
JDISCEN
12
1
JEOCIE
JEOCIE
7
1
OVRIE
OVRIE
26
1
PDD
PDD
16
1
PDI
PDI
17
1
RES
RES
24
2
SCAN
SCAN
8
1
CR2
CR2
ADC control register 2
0x8
read-write
n
0x0
0x0
ADON
ADON
0
1
ALIGN
ALIGN
11
1
CONT
CONT
1
1
DDS
DDS
9
1
DELS
DELS
4
3
DMA
DMA
8
1
EOCS
EOCS
10
1
EXTEN
EXTEN
28
2
EXTSEL
EXTSEL
24
4
JEXTEN
JEXTEN
20
2
JEXTSEL
JEXTSEL
16
4
JSWSTART
JSWSTART
22
1
SWSTART
SWSTART
30
1
CSR
CSR
ADC common status register
0x0
read-only
n
0x0
0x0
ADONS1
ADONS1
6
1
AWD1
AWD1
0
1
EOC1
EOC1
1
1
JEOC1
JEOC1
2
1
JSTRT1
JSTRT1
3
1
OVR1
OVR1
5
1
STRT1
STRT1
4
1
DR
DR
ADC regular data register
0x58
read-only
n
0x0
0x0
DATA
DATA
0
16
HTR
HTR
ADC watchdog higher threshold register
0x28
-1
read-write
n
0x0
0x0
HT
HT
0
12
JDR1
JDR1
ADC injected data register 1
0x48
read-only
n
0x0
0x0
JDATA
JDATA
0
16
JDR2
JDR2
ADC injected data register 2
0x4C
read-only
n
0x0
0x0
JDATA
JDATA
0
16
JDR3
JDR3
ADC injected data register 3
0x50
read-only
n
0x0
0x0
JDATA
JDATA
0
16
JDR4
JDR4
ADC injected data register 4
0x54
read-only
n
0x0
0x0
JDATA
JDATA
0
16
JOFR1
JOFR1
ADC injected channel data offset register 1
0x18
read-write
n
0x0
0x0
JOFFSET
JOFFSET
0
12
JOFR2
JOFR2
ADC injected channel data offset register 2
0x1C
read-write
n
0x0
0x0
JOFFSET
JOFFSET
0
12
JOFR3
JOFR3
ADC injected channel data offset register 3
0x20
read-write
n
0x0
0x0
JOFFSET
JOFFSET
0
12
JOFR4
JOFR4
ADC injected channel data offset register 4
0x24
read-write
n
0x0
0x0
JOFFSET
JOFFSET
0
12
JSQR
JSQR
ADC injected sequence register
0x44
read-write
n
0x0
0x0
JL
JL
20
2
JSQ1
JSQ1
0
5
JSQ2
JSQ2
5
5
JSQ3
JSQ3
10
5
JSQ4
JSQ4
15
5
LTR
LTR
ADC watchdog lower threshold register
0x2C
read-write
n
0x0
0x0
LT
LT
0
12
SMPR1
SMPR1
ADC sample time register 1
0xC
read-write
n
0x0
0x0
SMP16
SMP16
18
3
SMP20
SMP20
0
3
SMP21
SMP21
3
3
SMP22
SMP22
6
3
SMP23
SMP23
9
3
SMP24
SMP24
12
3
SMP25
SMP25
15
3
SMPR2
SMPR2
ADC sample time register 2
0x10
read-write
n
0x0
0x0
SMP10
SMP10
0
3
SMP11
SMP11
3
3
SMP12
SMP12
6
3
SMP13
SMP13
9
3
SMP14
SMP14
12
3
SMP15
SMP15
15
3
SMP16
SMP16
18
3
SMP17
SMP17
21
3
SMP18
SMP18
24
3
SMP19
SMP19
27
3
SMPR3
SMPR3
ADC sample time register 3
0x14
read-write
n
0x0
0x0
SMP0
SMP0
0
3
SMP1
SMP1
3
3
SMP2
SMP2
6
3
SMP3
SMP3
9
3
SMP4
SMP4
12
3
SMP5
SMP5
15
3
SMP6
SMP6
18
3
SMP7
SMP7
21
3
SMP8
SMP8
24
3
SMP9
SMP9
27
3
SQR1
SQR1
ADC regular sequence register 1
0x30
read-write
n
0x0
0x0
L
L
20
5
SQ25
SQ25
0
5
SQ26
SQ26
5
5
SQ27
SQ27
10
5
SQR2
SQR2
ADC regular sequence register 2
0x34
read-write
n
0x0
0x0
SQ19
SQ19
0
5
SQ20
SQ20
5
5
SQ21
SQ21
10
5
SQ22
SQ22
15
5
SQ23
SQ23
20
5
SQ24
SQ24
25
5
SQR3
SQR3
ADC regular sequence register 3
0x38
read-write
n
0x0
0x0
SQ13
SQ13
0
5
SQ14
SQ14
5
5
SQ15
SQ15
10
5
SQ16
SQ16
15
5
SQ17
SQ17
20
5
SQ18
SQ18
25
5
SQR4
SQR4
ADC regular sequence register 4
0x3C
read-write
n
0x0
0x0
SQ10
SQ10
15
5
SQ11
SQ11
20
5
SQ12
SQ12
25
5
SQ7
SQ7
0
5
SQ8
SQ8
5
5
SQ9
SQ9
10
5
SQR5
SQR5
ADC regular sequence register 5
0x40
read-write
n
0x0
0x0
SQ1
SQ1
0
5
SQ2
SQ2
5
5
SQ3
SQ3
10
5
SQ4
SQ4
15
5
SQ5
SQ5
20
5
SQ6
SQ6
25
5
SR
SR
ADC status register
0x0
read-write
n
0x0
0x0
ADONS
ADONS
6
1
read-only
AWD
AWD
0
1
write-only
EOC
EOC
1
1
write-only
JCNR
JCNR
9
1
read-only
JEOC
JEOC
2
1
write-only
JSTRT
JSTRT
3
1
write-only
OVR
OVR
5
1
write-only
RCNR
RCNR
8
1
read-only
STRT
STRT
4
1
write-only
COMP
Comparators
COMP
0x0
0x0
0x400
registers
n
CSR
CSR
COMP comparator control and status register
0x0
read-write
n
0x0
0x0
CMP1EN
CMP1EN
4
1
CMP1OUT
CMP1OUT
7
1
CMP2EN
CMP2EN
10
1
CMP2OUT
CMP2OUT
13
1
INSEL
INSEL
18
3
OUTSEL
OUTSEL
21
3
SPEED
SPEED
12
1
VREFOUTEN
VREFOUTEN
16
1
WNDEN
WNDEN
17
1
_10KPD
10KPD
2
1
_10KPU
10KPU
0
1
_400KPD
400KPD
3
1
_400KPU
400KPU
1
1
CRC
CRC calculation unit
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
read-write
n
0x0
0x0
RESET
RESET
0
1
DR
DR
Data register
0x0
-1
read-write
n
0x0
0x0
DR
CRC_DR
0
32
IDR
IDR
Independent data register
0x4
read-write
n
0x0
0x0
IDR
IDR
0
8
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
CR
CR
DAC control register
0x0
read-write
n
0x0
0x0
BOFF1
BOFF1
1
1
BOFF2
BOFF2
17
1
DMAEN1
DMAEN1
12
1
DMAEN2
DMAEN2
28
1
DMAUDRIE1
DMAUDRIE1
13
1
DMAUDRIE2
DMAUDRIE2
29
1
EN1
EN1
0
1
EN2
EN2
16
1
MAMP1
MAMP1
8
4
MAMP2
MAMP2
24
4
TEN1
TEN1
2
1
TEN2
TEN2
18
1
TSEL1
TSEL1
3
3
TSEL2
TSEL2
19
3
WAVE1
WAVE1
6
2
WAVE2
WAVE2
22
2
DHR12L1
DHR12L1
DAC channel1 12-bit left aligned data holding register
0xC
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
4
12
DHR12L2
DHR12L2
DAC channel2 12-bit left aligned data holding register
0x18
read-write
n
0x0
0x0
DACC2DHR
DACC2DHR
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
4
12
DACC2DHR
DACC2DHR
20
12
DHR12R1
DHR12R1
DAC channel1 12-bit right-aligned data holding register
0x8
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
0
12
DHR12R2
DHR12R2
DAC channel2 12-bit right aligned data holding register
0x14
read-write
n
0x0
0x0
DACC2DHR
DACC2DHR
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
0
12
DACC2DHR
DACC2DHR
16
12
DHR8R1
DHR8R1
DAC channel1 8-bit right aligned data holding register
0x10
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
0
8
DHR8R2
DHR8R2
DAC channel2 8-bit right-aligned data holding register
0x1C
read-write
n
0x0
0x0
DACC2DHR
DACC2DHR
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
read-write
n
0x0
0x0
DACC1DHR
DACC1DHR
0
8
DACC2DHR
DACC2DHR
8
8
DOR1
DOR1
DAC channel1 data output register
0x2C
read-only
n
0x0
0x0
DACC1DOR
DACC1DOR
0
12
DOR2
DOR2
DAC channel2 data output register
0x30
read-only
n
0x0
0x0
DACC2DOR
DACC2DOR
0
12
SR
SR
DAC status register
0x34
write-only
n
0x0
0x0
DMAUDR1
DMAUDR1
13
1
DMAUDR2
DMAUDR2
29
1
SWTRIGR
SWTRIGR
DAC software trigger register
0x4
write-only
n
0x0
0x0
SWTRIG1
SWTRIG1
0
1
SWTRIG2
SWTRIG2
1
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
DBGMCU_APB1_FZ
DBGMCU_APB1_FZ
Debug MCU APB1 Freeze registe
0x8
read-write
n
0x0
0x0
DBG_CAN1_STOP
DBG_CAN1_STOP
25
1
DBG_CAN2_STOP
DBG_CAN2_STOP
26
1
DBG_IWDEG_STOP
DBG_IWDEG_STOP
12
1
DBG_J2C1_SMBUS_TIMEOUT
DBG_J2C1_SMBUS_TIMEOUT
21
1
DBG_J2C2_SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT
22
1
DBG_J2C3SMBUS_TIMEOUT
DBG_J2C3SMBUS_TIMEOUT
23
1
DBG_TIM12_STOP
DBG_TIM12_STOP
6
1
DBG_TIM13_STOP
DBG_TIM13_STOP
7
1
DBG_TIM14_STOP
DBG_TIM14_STOP
8
1
DBG_TIM2_STOP
DBG_TIM2_STOP
0
1
DBG_TIM3__STOP
DBG_TIM3 _STOP
1
1
DBG_TIM4_STOP
DBG_TIM4_STOP
2
1
DBG_TIM5_STOP
DBG_TIM5_STOP
3
1
DBG_TIM6_STOP
DBG_TIM6_STOP
4
1
DBG_TIM7_STOP
DBG_TIM7_STOP
5
1
DBG_WWDG_STOP
DBG_WWDG_STOP
11
1
DBGMCU_APB2_FZ
DBGMCU_APB2_FZ
Debug MCU APB2 Freeze registe
0xC
read-write
n
0x0
0x0
DBG_TIM10_STOP
no info available
2
1
DBG_TIM11_STOP
no info available
3
1
DBG_TIM9_STOP
no info available
1
1
DBGMCU_CR
DBGMCU_CR
Control Register
0x4
read-write
n
0x0
0x0
DBG_I2C2_SMBUS_TIMEOUT
DBG_I2C2_SMBUS_TIMEOUT
16
1
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STANDBY
DBG_STANDBY
2
1
DBG_STOP
DBG_STOP
1
1
DBG_TIM5_STOP
DBG_TIM5_STOP
18
1
DBG_TIM6_STOP
DBG_TIM6_STOP
19
1
DBG_TIM7_STOP
DBG_TIM7_STOP
20
1
DBG_TIM8_STOP
DBG_TIM8_STOP
17
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
DBGMCU_IDCODE
DBGMCU_IDCODE
IDCODE
0x0
-1
read-only
n
0x0
0x0
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
DMA
DMA controller
DMA
0x0
0x0
0x400
registers
n
CCR1
CCR1
DMA channel x configuration register
0x8
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR2
CCR2
DMA channel x configuration register
0x1C
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR3
CCR3
DMA channel x configuration register
0x30
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR4
CCR4
DMA channel x configuration register
0x44
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR5
CCR5
DMA channel x configuration register
0x58
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR6
CCR6
DMA channel x configuration register
0x6C
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CCR7
CCR7
DMA channel x configuration register
0x80
read-write
n
0x0
0x0
CIRC
CIRC
5
1
DIR
DIR
4
1
EN
EN
0
1
HTIE
HTIE
2
1
MEM2MEM
MEM2MEM
14
1
MINC
MINC
7
1
MSIZE
MSIZE
10
2
PINC
PINC
6
1
PL
PL
12
2
PSIZE
PSIZE
8
2
TCIE
TCIE
1
1
TEIE
TEIE
3
1
CMAR1
CMAR1
DMA channel x memory address register
0x14
read-write
n
0x0
0x0
MA
MA
0
32
CMAR2
CMAR2
DMA channel x memory address register
0x28
read-write
n
0x0
0x0
MA
MA
0
32
CMAR3
CMAR3
DMA channel x memory address register
0x3C
read-write
n
0x0
0x0
MA
MA
0
32
CMAR4
CMAR4
DMA channel x memory address register
0x50
read-write
n
0x0
0x0
MA
MA
0
32
CMAR5
CMAR5
DMA channel x memory address register
0x64
read-write
n
0x0
0x0
MA
MA
0
32
CMAR6
CMAR6
DMA channel x memory address register
0x78
read-write
n
0x0
0x0
MA
MA
0
32
CMAR7
CMAR7
DMA channel x memory address register
0x8C
read-write
n
0x0
0x0
MA
MA
0
32
CNDTR1
CNDTR1
DMA channel x number of data register
0xC
read-only
n
0x0
0x0
NDT
NDT
0
16
CNDTR2
CNDTR2
DMA channel x number of data register
0x20
read-write
n
0x0
0x0
NDT
NDT
0
16
CNDTR3
CNDTR3
DMA channel x number of data register
0x34
read-write
n
0x0
0x0
NDT
NDT
0
16
CNDTR4
CNDTR4
DMA channel x number of data register
0x48
read-write
n
0x0
0x0
NDT
NDT
0
16
CNDTR5
CNDTR5
DMA channel x number of data register
0x5C
read-write
n
0x0
0x0
NDT
NDT
0
16
CNDTR6
CNDTR6
DMA channel x number of data register
0x70
read-write
n
0x0
0x0
NDT
NDT
0
16
CNDTR7
CNDTR7
DMA channel x number of data register
0x84
read-write
n
0x0
0x0
NDT
NDT
0
16
CPAR1
CPAR1
DMA channel x peripheral address register
0x10
read-write
n
0x0
0x0
PA
PA
0
32
CPAR2
CPAR2
DMA channel x peripheral address register
0x24
read-write
n
0x0
0x0
PA
PA
0
32
CPAR3
CPAR3
DMA channel x peripheral address register
0x38
read-write
n
0x0
0x0
PA
PA
0
32
CPAR4
CPAR4
DMA channel x peripheral address register
0x4C
read-write
n
0x0
0x0
PA
PA
0
32
CPAR5
CPAR5
DMA channel x peripheral address register
0x60
read-write
n
0x0
0x0
PA
PA
0
32
CPAR6
CPAR6
DMA channel x peripheral address register
0x74
read-write
n
0x0
0x0
PA
PA
0
32
CPAR7
CPAR7
DMA channel x peripheral address register
0x88
read-write
n
0x0
0x0
PA
PA
0
32
IFCR
IFCR
DMA interrupt flag clear register
0x4
write-only
n
0x0
0x0
CGIF1
CGIF1
0
1
CGIF2
CGIF2
4
1
CGIF3
CGIF3
8
1
CGIF4
CGIF4
12
1
CGIF5
CGIF5
16
1
CGIF6
CGIF6
20
1
CGIF7
CGIF7
24
1
CHTIF1
CHTIF1
2
1
CHTIF2
CHTIF2
6
1
CHTIF3
CHTIF3
10
1
CHTIF4
CHTIF4
14
1
CHTIF5
CHTIF5
18
1
CHTIF6
CHTIF6
22
1
CHTIF7
CHTIF7
26
1
CTCIF1
CTCIF1
1
1
CTCIF2
CTCIF2
5
1
CTCIF3
CTCIF3
9
1
CTCIF4
CTCIF4
13
1
CTCIF5
CTCIF5
17
1
CTCIF6
CTCIF6
21
1
CTCIF7
CTCIF7
25
1
CTEIF1
CTEIF1
3
1
CTEIF2
CTEIF2
7
1
CTEIF3
CTEIF3
11
1
CTEIF4
CTEIF4
15
1
CTEIF5
CTEIF5
19
1
CTEIF6
CTEIF6
23
1
CTEIF7
CTEIF7
27
1
ISR
ISR
DMA interrupt status register
0x0
read-only
n
0x0
0x0
GIF1
GIF1
0
1
GIF2
GIF2
4
1
GIF3
GIF3
8
1
GIF4
GIF4
12
1
GIF5
GIF5
16
1
GIF6
GIF6
20
1
GIF7
GIF7
24
1
HTIF1
HTIF1
2
1
HTIF2
HTIF2
6
1
HTIF3
HTIF3
10
1
HTIF4
HTIF4
14
1
HTIF5
HTIF5
18
1
HTIF6
HTIF6
22
1
HTIF7
HTIF7
26
1
TCIF1
TCIF1
1
1
TCIF2
TCIF2
5
1
TCIF3
TCIF3
9
1
TCIF4
TCIF4
13
1
TCIF5
TCIF5
17
1
TCIF6
TCIF6
21
1
TCIF7
TCIF7
25
1
TEIF1
TEIF1
3
1
TEIF2
TEIF2
7
1
TEIF3
TEIF3
11
1
TEIF4
TEIF4
15
1
TEIF5
TEIF5
19
1
TEIF6
TEIF6
23
1
TEIF7
TEIF7
27
1
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
EMR
EMR
Event mask register
0x4
read-write
n
0x0
0x0
MR0
Event mask on line x
0
1
MR1
Event mask on line x
1
1
MR10
Event mask on line x
10
1
MR11
Event mask on line x
11
1
MR12
Event mask on line x
12
1
MR13
Event mask on line x
13
1
MR14
Event mask on line x
14
1
MR15
Event mask on line x
15
1
MR16
Event mask on line x
16
1
MR17
Event mask on line x
17
1
MR18
Event mask on line x
18
1
MR19
Event mask on line x
19
1
MR2
Event mask on line x
2
1
MR20
Event mask on line x
20
1
MR21
Event mask on line x
21
1
MR22
Event mask on line x
22
1
MR3
Event mask on line x
3
1
MR4
Event mask on line x
4
1
MR5
Event mask on line x
5
1
MR6
Event mask on line x
6
1
MR7
Event mask on line x
7
1
MR8
Event mask on line x
8
1
MR9
Event mask on line x
9
1
FTSR
FTSR
Falling trigger selection register
0xC
read-write
n
0x0
0x0
TR0
Falling trigger event configuration bit of line x
0
1
TR1
Falling trigger event configuration bit of line x
1
1
TR10
Falling trigger event configuration bit of line x
10
1
TR11
Falling trigger event configuration bit of line x
11
1
TR12
Falling trigger event configuration bit of line x
12
1
TR13
Falling trigger event configuration bit of line x
13
1
TR14
Falling trigger event configuration bit of line x
14
1
TR15
Falling trigger event configuration bit of line x
15
1
TR16
Falling trigger event configuration bit of line x
16
1
TR17
Falling trigger event configuration bit of line x
17
1
TR18
Falling trigger event configuration bit of line x
18
1
TR19
Falling trigger event configuration bit of line x
19
1
TR2
Falling trigger event configuration bit of line x
2
1
TR20
Falling trigger event configuration bit of line x
20
1
TR21
Falling trigger event configuration bit of line x
21
1
TR22
Falling trigger event configuration bit of line x
22
1
TR3
Falling trigger event configuration bit of line x
3
1
TR4
Falling trigger event configuration bit of line x
4
1
TR5
Falling trigger event configuration bit of line x
5
1
TR6
Falling trigger event configuration bit of line x
6
1
TR7
Falling trigger event configuration bit of line x
7
1
TR8
Falling trigger event configuration bit of line x
8
1
TR9
Falling trigger event configuration bit of line x
9
1
IMR
IMR
Interrupt mask register
0x0
read-write
n
0x0
0x0
MR0
Event mask on line 0
0
1
MR1
Event mask on line 1
1
1
MR10
Event mask on line 10
10
1
MR11
Event mask on line 11
11
1
MR12
Event mask on line 12
12
1
MR13
Event mask on line 13
13
1
MR14
Event mask on line 14
14
1
MR15
Event mask on line 15
15
1
MR16
Event mask on line 16
16
1
MR17
Event mask on line 17
17
1
MR18
Event mask on line 18
18
1
MR19
Event mask on line 19
19
1
MR2
Event mask on line 2
2
1
MR20
Event mask on line 20
20
1
MR21
Event mask on line 21
21
1
MR22
Event mask on line 22
22
1
MR3
Event mask on line 3
3
1
MR4
Event mask on line 4
4
1
MR5
Event mask on line 5
5
1
MR6
Event mask on line 6
6
1
MR7
Event mask on line 7
7
1
MR8
Event mask on line 8
8
1
MR9
Event mask on line 9
9
1
PR
PR
Pending register
0x14
read-write
n
0x0
0x0
PR0
Pending bit x
0
1
PR1
Pending bit x
1
1
PR10
Pending bit x
10
1
PR11
Pending bit x
11
1
PR12
Pending bit x
12
1
PR13
Pending bit x
13
1
PR14
Pending bit x
14
1
PR15
Pending bit x
15
1
PR16
Pending bit x
16
1
PR17
Pending bit x
17
1
PR19
Pending bit x
19
1
PR2
Pending bit x
2
1
PR20
Pending bit x
20
1
PR21
Pending bit x
21
1
PR218
Pending bit x
18
1
PR22
Pending bit x
22
1
PR3
Pending bit x
3
1
PR4
Pending bit x
4
1
PR5
Pending bit x
5
1
PR6
Pending bit x
6
1
PR7
Pending bit x
7
1
PR8
Pending bit x
8
1
PR9
Pending bit x
9
1
RTSR
RTSR
Rising trigger selection register
0x8
read-write
n
0x0
0x0
TR0
Rising trigger event configuration bit of line x
0
1
TR1
Rising trigger event configuration bit of line x
1
1
TR10
Rising trigger event configuration bit of line x
10
1
TR11
Rising trigger event configuration bit of line x
11
1
TR12
Rising trigger event configuration bit of line x
12
1
TR13
Rising trigger event configuration bit of line x
13
1
TR14
Rising trigger event configuration bit of line x
14
1
TR15
Rising trigger event configuration bit of line x
15
1
TR16
Rising trigger event configuration bit of line x
16
1
TR17
Rising trigger event configuration bit of line x
17
1
TR18
Rising trigger event configuration bit of line x
18
1
TR19
Rising trigger event configuration bit of line x
19
1
TR2
Rising trigger event configuration bit of line x
2
1
TR20
Rising trigger event configuration bit of line x
20
1
TR21
Rising trigger event configuration bit of line x
21
1
TR22
Rising trigger event configuration bit of line x
22
1
TR3
Rising trigger event configuration bit of line x
3
1
TR4
Rising trigger event configuration bit of line x
4
1
TR5
Rising trigger event configuration bit of line x
5
1
TR6
Rising trigger event configuration bit of line x
6
1
TR7
Rising trigger event configuration bit of line x
7
1
TR8
Rising trigger event configuration bit of line x
8
1
TR9
Rising trigger event configuration bit of line x
9
1
SWIER
SWIER
Software interrupt event register
0x10
read-write
n
0x0
0x0
SWIER0
Software Interrupt on line x
0
1
SWIER1
Software Interrupt on line x
1
1
SWIER10
Software Interrupt on line x
10
1
SWIER11
Software Interrupt on line x
11
1
SWIER12
Software Interrupt on line x
12
1
SWIER13
Software Interrupt on line x
13
1
SWIER14
Software Interrupt on line x
14
1
SWIER15
Software Interrupt on line x
15
1
SWIER16
Software Interrupt on line x
16
1
SWIER17
Software Interrupt on line x
17
1
SWIER18
Software Interrupt on line x
18
1
SWIER19
Software Interrupt on line x
19
1
SWIER2
Software Interrupt on line x
2
1
SWIER20
Software Interrupt on line x
20
1
SWIER22
Software Interrupt on line x
21
1
SWIER3
Software Interrupt on line x
3
1
SWIER4
Software Interrupt on line x
4
1
SWIER5
Software Interrupt on line x
5
1
SWIER6
Software Interrupt on line x
6
1
SWIER7
Software Interrupt on line x
7
1
SWIER8
Software Interrupt on line x
8
1
SWIER9
Software Interrupt on line x
9
1
Flash
Flash
Flash
0x0
0x0
0x400
registers
n
ACR
ACR
FLASH_ACR
0x0
read-write
n
0x0
0x0
ACC64
ACC64
2
1
read-write
LATENCY
LATENCY
0
1
read-only
PRFTEN
PRFTEN
1
1
read-only
RUN_PD
RUN_PD
4
1
read-only
SLEEP_PD
SLEEP_PD
3
1
read-write
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
GPIOD
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
GPIOE
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
GPIOF
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
read-write
n
0x0
0x0
AFRL10
AFRL10
8
4
AFRL11
AFRL11
12
4
AFRL12
AFRL12
16
4
AFRL13
AFRL13
20
4
AFRL14
AFRL14
24
4
AFRL15
AFRL15
28
4
AFRL8
AFRL8
0
4
AFRL9
AFRL9
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
read-write
n
0x0
0x0
AFRL0
AFRL0
0
4
AFRL1
AFRL1
4
4
AFRL2
AFRL2
8
4
AFRL3
AFRL3
12
4
AFRL4
AFRL4
16
4
AFRL5
AFRL5
20
4
AFRL6
AFRL6
24
4
AFRL7
AFRL7
28
4
BSRR
BSRR
GPIO port bit set/reset register
0x18
write-only
n
0x0
0x0
BR0
BR0
16
1
BR1
BR1
17
1
BR10
BR10
26
1
BR11
BR11
27
1
BR12
BR12
28
1
BR13
BR13
29
1
BR14
BR14
30
1
BR15
BR15
31
1
BR2
BR2
18
1
BR3
BR3
19
1
BR4
BR4
20
1
BR5
BR5
21
1
BR6
BR6
22
1
BR7
BR7
23
1
BR8
BR8
24
1
BR9
BR9
25
1
BS0
BS0
0
1
BS1
BS1
1
1
BS10
BS10
10
1
BS11
BS11
11
1
BS12
BS12
12
1
BS13
BS13
13
1
BS14
BS14
14
1
BS15
BS15
15
1
BS2
BS2
2
1
BS3
BS3
3
1
BS4
BS4
4
1
BS5
BS5
5
1
BS6
BS6
6
1
BS7
BS7
7
1
BS8
BS8
8
1
BS9
BS9
9
1
IDR
IDR
GPIO port input data register
0x10
read-only
n
0x0
0x0
IDR0
IDR0
0
1
IDR1
IDR1
1
1
IDR10
IDR10
10
1
IDR11
IDR11
11
1
IDR12
IDR12
12
1
IDR13
IDR13
13
1
IDR14
IDR14
14
1
IDR15
IDR15
15
1
IDR2
IDR2
2
1
IDR3
IDR3
3
1
IDR4
IDR4
4
1
IDR5
IDR5
5
1
IDR6
IDR6
6
1
IDR7
IDR7
7
1
IDR8
IDR8
8
1
IDR9
IDR9
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
read-write
n
0x0
0x0
LCK0
LCK0
0
1
LCK1
LCK1
1
1
LCK10
LCK10
10
1
LCK11
LCK11
11
1
LCK12
LCK12
12
1
LCK13
LCK13
13
1
LCK14
LCK14
14
1
LCK15
LCK15
15
1
LCK2
LCK2
2
1
LCK3
LCK3
3
1
LCK4
LCK4
4
1
LCK5
LCK5
5
1
LCK6
LCK6
6
1
LCK7
LCK7
7
1
LCK8
LCK8
8
1
LCK9
LCK9
9
1
LCKK
LCKK
16
1
MODER
MODER
GPIO port mode register
0x0
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
read-write
n
0x0
0x0
ODR0
ODR0
0
1
ODR1
ODR1
1
1
ODR10
ODR10
10
1
ODR11
ODR11
11
1
ODR12
ODR12
12
1
ODR13
ODR13
13
1
ODR14
ODR14
14
1
ODR15
ODR15
15
1
ODR2
ODR2
2
1
ODR3
ODR3
3
1
ODR4
ODR4
4
1
ODR5
ODR5
5
1
ODR6
ODR6
6
1
ODR7
ODR7
7
1
ODR8
ODR8
8
1
ODR9
ODR9
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
read-write
n
0x0
0x0
OSPEEDR0
OSPEEDR0
0
1
OSPEEDR1
OSPEEDR1
1
1
OSPEEDR10
OSPEEDR10
10
1
OSPEEDR11
OSPEEDR11
11
1
OSPEEDR12
OSPEEDR12
12
1
OSPEEDR13
OSPEEDR13
13
1
OSPEEDR14
OSPEEDR14
14
1
OSPEEDR15
OSPEEDR15
15
1
OSPEEDR2
OSPEEDR2
2
1
OSPEEDR3
OSPEEDR3
3
1
OSPEEDR4
OSPEEDR4
4
1
OSPEEDR5
OSPEEDR5
5
1
OSPEEDR6
OSPEEDR6
6
1
OSPEEDR7
OSPEEDR7
7
1
OSPEEDR8
OSPEEDR8
8
1
OSPEEDR9
OSPEEDR9
9
1
OTYPER
OTYPER
GPIO port output type register
0x4
read-write
n
0x0
0x0
OT0
OT0
0
1
OT1
OT1
1
1
OT10
OT10
10
1
OT11
OT11
11
1
OT12
OT12
12
1
OT13
OT13
13
1
OT14
OT14
14
1
OT15
OT15
15
1
OT2
OT2
2
1
OT3
OT3
3
1
OT4
OT4
4
1
OT5
OT5
5
1
OT6
OT6
6
1
OT7
OT7
7
1
OT8
OT8
8
1
OT9
OT9
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
read-write
n
0x0
0x0
PUPDR0
PUPDR0
0
2
PUPDR1
PUPDR1
2
2
PUPDR10
PUPDR10
20
2
PUPDR11
PUPDR11
22
2
PUPDR12
PUPDR12
24
2
PUPDR13
PUPDR13
26
2
PUPDR14
PUPDR14
28
2
PUPDR15
PUPDR15
30
2
PUPDR2
PUPDR2
4
2
PUPDR3
PUPDR3
6
2
PUPDR4
PUPDR4
8
2
PUPDR5
PUPDR5
10
2
PUPDR6
PUPDR6
12
2
PUPDR7
PUPDR7
14
2
PUPDR8
PUPDR8
16
2
PUPDR9
PUPDR9
18
2
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
CCR
CCR
Clock control register
0x1C
read-write
n
0x0
0x0
CCR
CCR
0
12
DUTY
DUTY
14
1
F_S
F_S
15
1
CR1
CR1
Control register 1
0x0
read-write
n
0x0
0x0
ACK
ACK
10
1
ALERT
ALERT
13
1
ENARP
ENARP
4
1
ENGC
ENGC
6
1
ENPEC
ENPEC
5
1
NOSTRETCH
NOSTRETCH
7
1
PE
PE
0
1
PEC
PEC
12
1
POS
POS
11
1
SMBTYPE
SMBTYPE
3
1
SMBUS
SMBUS
1
1
START
START
8
1
STOP
STOP
9
1
SWRST
SWRST
15
1
CR2
CR2
Control register 2
0x4
read-write
n
0x0
0x0
DMAEN
DMAEN
11
1
FREQ
FREQ
0
6
ITBUFEN
ITBUFEN
10
1
ITERREN
ITERREN
8
1
ITEVTEN
ITEVTEN
9
1
LAST
LAST
12
1
DR
DR
Data register
0x10
read-write
n
0x0
0x0
DR
DR
0
8
OAR1
OAR1
Own address register 1
0x8
read-write
n
0x0
0x0
ADD
ADD
1
9
ADD0
ADD0
0
1
ADDMODE
ADDMODE
15
1
OAR2
OAR2
Own address register 2
0xC
read-write
n
0x0
0x0
ADD2
ADD2
1
7
ENDUAL
ENDUAL
0
1
SR1
SR1
Status register 1
0x14
read-only
n
0x0
0x0
ADD10
ADD10
3
1
ADDR
ADDR
1
1
AF
AF
10
1
ARLO
ARLO
9
1
BERR
BERR
8
1
BTF
BTF
2
1
OVR
OVR
11
1
PECERR
PECERR
12
1
RxNE
RxNE
6
1
SB
SB
0
1
SMBALERT
SMBALERT
15
1
STOPF
STOPF
4
1
TIMEOUT
TIMEOUT
14
1
TxE
TxE
7
1
SR2
SR2
Status register 2
0x18
-1
read-only
n
0x0
0x0
BUSY
BUSY
1
1
DUALF
DUALF
7
1
GENCALL
GENCALL
4
1
MSL
MSL
0
1
PEC
PEC
8
8
SMBDEFAULT
SMBDEFAULT
5
1
SMBHOST
SMBHOST
6
1
TRA
TRA
2
1
TRISE
TRISE
TRISE register
0x20
-1
read-write
n
0x0
0x0
TRISE
TRISE
0
6
I2C2
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
CCR
CCR
Clock control register
0x1C
read-write
n
0x0
0x0
CCR
CCR
0
12
DUTY
DUTY
14
1
F_S
F_S
15
1
CR1
CR1
Control register 1
0x0
read-write
n
0x0
0x0
ACK
ACK
10
1
ALERT
ALERT
13
1
ENARP
ENARP
4
1
ENGC
ENGC
6
1
ENPEC
ENPEC
5
1
NOSTRETCH
NOSTRETCH
7
1
PE
PE
0
1
PEC
PEC
12
1
POS
POS
11
1
SMBTYPE
SMBTYPE
3
1
SMBUS
SMBUS
1
1
START
START
8
1
STOP
STOP
9
1
SWRST
SWRST
15
1
CR2
CR2
Control register 2
0x4
read-write
n
0x0
0x0
DMAEN
DMAEN
11
1
FREQ
FREQ
0
6
ITBUFEN
ITBUFEN
10
1
ITERREN
ITERREN
8
1
ITEVTEN
ITEVTEN
9
1
LAST
LAST
12
1
DR
DR
Data register
0x10
read-write
n
0x0
0x0
DR
DR
0
8
OAR1
OAR1
Own address register 1
0x8
read-write
n
0x0
0x0
ADD
ADD
1
9
ADD0
ADD0
0
1
ADDMODE
ADDMODE
15
1
OAR2
OAR2
Own address register 2
0xC
read-write
n
0x0
0x0
ADD2
ADD2
1
7
ENDUAL
ENDUAL
0
1
SR1
SR1
Status register 1
0x14
read-only
n
0x0
0x0
ADD10
ADD10
3
1
ADDR
ADDR
1
1
AF
AF
10
1
ARLO
ARLO
9
1
BERR
BERR
8
1
BTF
BTF
2
1
OVR
OVR
11
1
PECERR
PECERR
12
1
RxNE
RxNE
6
1
SB
SB
0
1
SMBALERT
SMBALERT
15
1
STOPF
STOPF
4
1
TIMEOUT
TIMEOUT
14
1
TxE
TxE
7
1
SR2
SR2
Status register 2
0x18
-1
read-only
n
0x0
0x0
BUSY
BUSY
1
1
DUALF
DUALF
7
1
GENCALL
GENCALL
4
1
MSL
MSL
0
1
PEC
PEC
8
8
SMBDEFAULT
SMBDEFAULT
5
1
SMBHOST
SMBHOST
6
1
TRA
TRA
2
1
TRISE
TRISE
TRISE register
0x20
-1
read-write
n
0x0
0x0
TRISE
TRISE
0
6
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
read-only
n
0x0
0x0
KR
KR
0
16
PR
PR
Prescaler register
0x4
read-write
n
0x0
0x0
PR
PR
0
3
RLR
RLR
Reload register
0x8
-1
read-write
n
0x0
0x0
RL
RL
0
12
SR
SR
Status register
0xC
read-only
n
0x0
0x0
PVU
PVU
0
1
RVU
RVU
1
1
LCD
LCD controller
LCD
0x0
0x0
0x400
registers
n
CLR
CLR
LCD clear register
0xC
write-only
n
0x0
0x0
ENS
ENS
0
1
FCRSF
FCRSF
5
1
RDY
RDY
4
1
SOF
SOF
1
1
UDD
UDD
3
1
UDR
UDR
2
1
CR
CR
LCD control register
0x0
read-write
n
0x0
0x0
BIAS
BIAS
5
2
DUTY
DUTY
2
3
LCDEN
LCDEN
0
1
MUX_SEG
MUX_SEG
7
1
VSEL
VSEL
1
1
FCR
FCR
LCD frame control register
0x4
read-write
n
0x0
0x0
BLINK
BLINK
16
2
BLINKF
BLINKF
13
3
CC
CC
10
3
DEAD
DEAD
7
3
DIV
DIV
18
4
HD
HD
0
1
PON
PON
4
3
PS
PS
22
4
SOFIE
SOFIE
1
1
UDDIE
UDDIE
3
1
RAM_COM00
RAM_COM00
LCD display memory
0x14
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM01
RAM_COM01
LCD display memory
0x18
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM10
RAM_COM10
LCD display memory
0x1C
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM11
RAM_COM11
LCD display memory
0x20
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM20
RAM_COM20
LCD display memory
0x24
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM21
RAM_COM21
LCD display memory
0x28
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM30
RAM_COM30
LCD display memory
0x2C
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM31
RAM_COM31
LCD display memory
0x30
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM40
RAM_COM40
LCD display memory
0x34
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM41
RAM_COM41
LCD display memory
0x38
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM50
RAM_COM50
LCD display memory
0x3C
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM51
RAM_COM51
LCD display memory
0x40
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM60
RAM_COM60
LCD display memory
0x44
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM61
RAM_COM61
LCD display memory
0x48
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
RAM_COM70
RAM_COM70
LCD display memory
0x4C
read-write
n
0x0
0x0
S00
S00
0
1
S01
S01
1
1
S02
S02
2
1
S03
S03
3
1
S04
S04
4
1
S05
S05
5
1
S06
S06
6
1
S07
S07
7
1
S08
S08
8
1
S09
S09
9
1
S10
S10
10
1
S11
S11
11
1
S12
S12
12
1
S13
S13
13
1
S14
S14
14
1
S15
S15
15
1
S16
S16
16
1
S17
S17
17
1
S18
S18
18
1
S19
S19
19
1
S20
S20
20
1
S21
S21
21
1
S22
S22
22
1
S23
S23
23
1
S24
S24
24
1
S25
S25
25
1
S26
S26
26
1
S27
S27
27
1
S28
S28
28
1
S29
S29
29
1
S30
S30
30
1
S31
S31
31
1
RAM_COM71
RAM_COM71
LCD display memory
0x50
read-write
n
0x0
0x0
S32
S32
0
1
S33
S33
1
1
S34
S34
2
1
S35
S35
3
1
S36
S36
4
1
S37
S37
5
1
S38
S38
6
1
S39
S39
7
1
S40
S40
8
1
S41
S41
9
1
S42
S42
10
1
S43
S43
11
1
SR
SR
LCD status register
0x8
-1
read-only
n
0x0
0x0
ENS
ENS
0
1
FCRSF
FCRSF
5
1
RDY
RDY
4
1
SOF
SOF
1
1
UDD
UDD
3
1
UDR
UDR
2
1
NVIC
Nested vectored interrupt controller
NVIC
0x0
0x0
0x11FC
registers
n
ACTIVE0
ACTIVE0
ACTIVE0
0x2FC
read-write
n
0x0
0x0
ACTIVE0
ACTIVE0
0
1
read-only
ACTIVE1
ACTIVE1
1
1
read-only
ACTIVE10
ACTIVE10
10
1
read-only
ACTIVE11
ACTIVE11
11
1
read-only
ACTIVE12
ACTIVE12
12
1
read-only
ACTIVE13
ACTIVE13
13
1
read-only
ACTIVE14
ACTIVE14
14
1
read-only
ACTIVE15
ACTIVE15
15
1
read-only
ACTIVE16
ACTIVE16
16
1
read-only
ACTIVE17
ACTIVE17
17
1
read-only
ACTIVE18
ACTIVE18
18
1
read-only
ACTIVE19
ACTIVE19
19
1
read-only
ACTIVE2
ACTIVE2
2
1
read-only
ACTIVE20
ACTIVE20
20
1
read-only
ACTIVE21
ACTIVE21
21
1
read-only
ACTIVE22
ACTIVE22
22
1
read-only
ACTIVE23
ACTIVE23
23
1
read-only
ACTIVE24
ACTIVE24
24
1
read-only
ACTIVE25
ACTIVE25
25
1
read-only
ACTIVE26
ACTIVE26
26
1
read-only
ACTIVE27
ACTIVE27
27
1
read-only
ACTIVE28
ACTIVE28
28
1
read-only
ACTIVE29
ACTIVE29
29
1
read-only
ACTIVE3
ACTIVE3
3
1
read-only
ACTIVE30
ACTIVE30
30
1
read-only
ACTIVE31
ACTIVE31
31
1
read-only
ACTIVE4
ACTIVE4
4
1
read-only
ACTIVE5
ACTIVE5
5
1
read-only
ACTIVE6
ACTIVE6
6
1
read-only
ACTIVE7
ACTIVE7
7
1
read-only
ACTIVE8
ACTIVE8
8
1
read-only
ACTIVE9
ACTIVE9
9
1
read-only
ACTIVE1
ACTIVE1
ACTIVE1
0x300
read-write
n
0x0
0x0
ACTIVE32
ACTIVE32
0
1
read-only
ACTIVE33
ACTIVE33
1
1
read-only
ACTIVE34
ACTIVE34
2
1
read-only
ACTIVE35
ACTIVE35
3
1
read-only
ACTIVE36
ACTIVE36
4
1
read-only
ACTIVE37
ACTIVE37
5
1
read-only
ACTIVE38
ACTIVE38
6
1
read-only
ACTIVE39
ACTIVE39
7
1
read-only
ACTIVE40
ACTIVE40
8
1
read-only
ACTIVE41
ACTIVE41
9
1
read-only
ACTIVE42
ACTIVE42
10
1
read-only
ACTIVE43
ACTIVE43
11
1
read-only
ACTIVE44
ACTIVE44
12
1
read-only
ACTIVE45
ACTIVE45
13
1
read-only
ACTIVE46
ACTIVE46
14
1
read-only
ACTIVE47
ACTIVE47
15
1
read-only
ACTIVE48
ACTIVE48
16
1
read-only
ACTIVE49
ACTIVE49
17
1
read-only
ACTIVE50
ACTIVE50
18
1
read-only
ACTIVE51
ACTIVE51
19
1
read-only
ACTIVE52
ACTIVE52
20
1
read-only
ACTIVE53
ACTIVE53
21
1
read-only
ACTIVE54
ACTIVE54
22
1
read-only
ACTIVE55
ACTIVE55
23
1
read-only
ACTIVE56
ACTIVE56
24
1
read-only
ACTIVE57
ACTIVE57
25
1
read-only
ACTIVE58
ACTIVE58
26
1
read-only
ACTIVE59
ACTIVE59
27
1
read-only
ACTIVE60
ACTIVE60
28
1
read-only
ACTIVE61
ACTIVE61
29
1
read-only
ACTIVE62
ACTIVE62
30
1
read-only
ACTIVE63
ACTIVE63
31
1
read-only
AIRCR
AIRCR
AIRCR
0xD08
-1
read-write
n
0x0
0x0
ENDIANESS
ENDIANESS
15
1
read-only
PRIGROUP
PRIGROUP
8
3
read-only
SYSRESETREQ
SYSRESETREQ
2
1
read-only
VECTCLRACTIVE
VECTCLRACTIVE
1
1
read-only
VECTKEY
VECTKEY
16
16
read-only
VECTRESET
VECTRESET
0
1
read-only
BFAR
BFAR
BFAR
0xD34
-1
read-write
n
0x0
0x0
CCR
CCR
CCR
0xD10
-1
read-write
n
0x0
0x0
BFHFNMIGN
BFHFNMIGN
8
1
read-write
DIV_0_TRP
DIV_0_TRP
4
1
read-write
NONEBASETHRDENA
NONEBASETHRDENA
0
1
read-write
STKALIGN
STKALIGN
9
1
read-write
UNALIGN_TRP
UNALIGN_TRP
3
1
read-write
USERSETMPEND
USERSETMPEND
1
1
read-write
CFSR
CFSR
CFSR
0xD24
-1
read-write
n
0x0
0x0
BFARVALID
BFARVALID
15
1
read-only
DACCVIOL
DACCVIOL
1
1
read-only
DIVBYZERO
DIVBYZERO
25
1
read-only
IACCVIOL
IACCVIOL
0
1
read-only
IBUSERR
IBUSERR
8
1
read-only
IMPRECISERR
IMPRECISERR
10
1
read-only
INVPC
INVPC
18
1
read-only
INVSTATE
INVSTATE
17
1
read-only
MMARVALID
MMARVALID
7
1
read-only
MSTKERR
MSTKERR
4
1
read-only
MUNSTKERR
MUNSTKERR
3
1
read-only
NOCP
NOCP
19
1
read-only
PRECISERR
PRECISERR
9
1
read-only
STKERR
STKERR
12
1
read-only
UNALIGNED
UNALIGNED
24
1
read-only
UNDEFINSTR
UNDEFINSTR
16
1
read-only
UNSTKERR
UNSTKERR
11
1
read-only
CLRENA0
CLRENA0
CLRENA0
0x17C
read-write
n
0x0
0x0
CLRENA0
CLRENA0
0
1
read-only
CLRENA1
CLRENA1
1
1
read-only
CLRENA10
CLRENA10
10
1
read-only
CLRENA11
CLRENA11
11
1
read-only
CLRENA12
CLRENA12
12
1
read-only
CLRENA13
CLRENA13
13
1
read-only
CLRENA14
CLRENA14
14
1
read-only
CLRENA15
CLRENA15
15
1
read-only
CLRENA16
CLRENA16
16
1
read-only
CLRENA17
CLRENA17
17
1
read-only
CLRENA18
CLRENA18
18
1
read-only
CLRENA19
CLRENA19
19
1
read-only
CLRENA2
CLRENA2
2
1
read-only
CLRENA20
CLRENA20
20
1
read-only
CLRENA21
CLRENA21
21
1
read-only
CLRENA22
CLRENA22
22
1
read-only
CLRENA23
CLRENA23
23
1
read-only
CLRENA24
CLRENA24
24
1
read-only
CLRENA25
CLRENA25
25
1
read-only
CLRENA26
CLRENA26
26
1
read-only
CLRENA27
CLRENA27
27
1
read-only
CLRENA28
CLRENA28
28
1
read-only
CLRENA29
CLRENA29
29
1
read-only
CLRENA3
CLRENA3
3
1
read-only
CLRENA30
CLRENA30
30
1
read-only
CLRENA31
CLRENA31
31
1
read-only
CLRENA4
CLRENA4
4
1
read-only
CLRENA5
CLRENA5
5
1
read-only
CLRENA6
CLRENA6
6
1
read-only
CLRENA7
CLRENA7
7
1
read-only
CLRENA8
CLRENA8
8
1
read-only
CLRENA9
CLRENA9
9
1
read-only
CLRENA1
CLRENA1
CLRENA1
0x180
read-write
n
0x0
0x0
CLRENA32
CLRENA32
0
1
read-only
CLRENA33
CLRENA33
1
1
read-only
CLRENA34
CLRENA34
2
1
read-only
CLRENA35
CLRENA35
3
1
read-only
CLRENA36
CLRENA36
4
1
read-only
CLRENA37
CLRENA37
5
1
read-only
CLRENA38
CLRENA38
6
1
read-only
CLRENA39
CLRENA39
7
1
read-only
CLRENA40
CLRENA40
8
1
read-only
CLRENA41
CLRENA41
9
1
read-only
CLRENA42
CLRENA42
10
1
read-only
CLRENA43
CLRENA43
11
1
read-only
CLRENA44
CLRENA44
12
1
read-only
CLRENA45
CLRENA45
13
1
read-only
CLRENA46
CLRENA46
14
1
read-only
CLRENA47
CLRENA47
15
1
read-only
CLRENA48
CLRENA48
16
1
read-only
CLRENA49
CLRENA49
17
1
read-only
CLRENA50
CLRENA50
18
1
read-only
CLRENA51
CLRENA51
19
1
read-only
CLRENA52
CLRENA52
20
1
read-only
CLRENA53
CLRENA53
21
1
read-only
CLRENA54
CLRENA54
22
1
read-only
CLRENA55
CLRENA55
23
1
read-only
CLRENA56
CLRENA56
24
1
read-only
CLRENA57
CLRENA57
25
1
read-only
CLRENA58
CLRENA58
26
1
read-only
CLRENA59
CLRENA59
27
1
read-only
CLRENA60
CLRENA60
28
1
read-only
CLRENA61
CLRENA61
29
1
read-only
CLRENA62
CLRENA62
30
1
read-only
CLRENA63
CLRENA63
31
1
read-only
CLRPEND0
CLRPEND0
CLRPEND0
0x27C
read-write
n
0x0
0x0
CLRPEND0
CLRPEND0
0
1
read-only
CLRPEND1
CLRPEND1
1
1
read-only
CLRPEND10
CLRPEND10
10
1
read-only
CLRPEND11
CLRPEND11
11
1
read-only
CLRPEND12
CLRPEND12
12
1
read-only
CLRPEND13
CLRPEND13
13
1
read-only
CLRPEND14
CLRPEND14
14
1
read-only
CLRPEND15
CLRPEND15
15
1
read-only
CLRPEND16
CLRPEND16
16
1
read-only
CLRPEND17
CLRPEND17
17
1
read-only
CLRPEND18
CLRPEND18
18
1
read-only
CLRPEND19
CLRPEND19
19
1
read-only
CLRPEND2
CLRPEND2
2
1
read-only
CLRPEND20
CLRPEND20
20
1
read-only
CLRPEND21
CLRPEND21
21
1
read-only
CLRPEND22
CLRPEND22
22
1
read-only
CLRPEND23
CLRPEND23
23
1
read-only
CLRPEND24
CLRPEND24
24
1
read-only
CLRPEND25
CLRPEND25
25
1
read-only
CLRPEND26
CLRPEND26
26
1
read-only
CLRPEND27
CLRPEND27
27
1
read-only
CLRPEND28
CLRPEND28
28
1
read-only
CLRPEND29
CLRPEND29
29
1
read-only
CLRPEND3
CLRPEND3
3
1
read-only
CLRPEND30
CLRPEND30
30
1
read-only
CLRPEND31
CLRPEND31
31
1
read-only
CLRPEND4
CLRPEND4
4
1
read-only
CLRPEND5
CLRPEND5
5
1
read-only
CLRPEND6
CLRPEND6
6
1
read-only
CLRPEND7
CLRPEND7
7
1
read-only
CLRPEND8
CLRPEND8
8
1
read-only
CLRPEND9
CLRPEND9
9
1
read-only
CLRPEND1
CLRPEND1
CLRPEND1
0x280
read-write
n
0x0
0x0
CLRPEND32
CLRPEND32
0
1
read-only
CLRPEND33
CLRPEND33
1
1
read-only
CLRPEND34
CLRPEND34
2
1
read-only
CLRPEND35
CLRPEND35
3
1
read-only
CLRPEND36
CLRPEND36
4
1
read-only
CLRPEND37
CLRPEND37
5
1
read-only
CLRPEND38
CLRPEND38
6
1
read-only
CLRPEND39
CLRPEND39
7
1
read-only
CLRPEND40
CLRPEND40
8
1
read-only
CLRPEND41
CLRPEND41
9
1
read-only
CLRPEND42
CLRPEND42
10
1
read-only
CLRPEND43
CLRPEND43
11
1
read-only
CLRPEND44
CLRPEND44
12
1
read-only
CLRPEND45
CLRPEND45
13
1
read-only
CLRPEND46
CLRPEND46
14
1
read-only
CLRPEND47
CLRPEND47
15
1
read-only
CLRPEND48
CLRPEND48
16
1
read-only
CLRPEND49
CLRPEND49
17
1
read-only
CLRPEND50
CLRPEND50
18
1
read-only
CLRPEND51
CLRPEND51
19
1
read-only
CLRPEND52
CLRPEND52
20
1
read-only
CLRPEND53
CLRPEND53
21
1
read-only
CLRPEND54
CLRPEND54
22
1
read-only
CLRPEND55
CLRPEND55
23
1
read-only
CLRPEND56
CLRPEND56
24
1
read-only
CLRPEND57
CLRPEND57
25
1
read-only
CLRPEND58
CLRPEND58
26
1
read-only
CLRPEND59
CLRPEND59
27
1
read-only
CLRPEND60
CLRPEND60
28
1
read-only
CLRPEND61
CLRPEND61
29
1
read-only
CLRPEND62
CLRPEND62
30
1
read-only
CLRPEND63
CLRPEND63
31
1
read-only
CPUIDBR
CPUIDBR
CPUIDBR
0xCFC
-1
read-write
n
0x0
0x0
IMPLEMENTER
IMPLEMENTER
24
8
read-only
PARTNO
PARTNO
4
12
read-only
REVISION
REVISION
0
4
read-only
VARIANT
VARIANT
20
4
read-only
DFSR
DFSR
DFSR
0xD2C
read-write
n
0x0
0x0
BKPT
BKPT
1
1
read-only
DWTTRAP
DWTTRAP
2
1
read-only
EXTERNAL
EXTERNAL
4
1
read-only
HALTED
HALTED
0
1
read-only
VCATCH
VCATCH
3
1
read-only
HFSR
HFSR
HFSR
0xD28
-1
read-write
n
0x0
0x0
DEBUGEVT
DEBUGEVT
31
1
read-only
FORCED
FORCED
30
1
read-only
VECTTBL
VECTTBL
1
1
read-only
ICSR
ICSR
ICSR
0xD00
-1
read-write
n
0x0
0x0
ISRPENDING
ISRPENDING
22
1
read-only
ISRPREEMPT
ISRPREEMPT
23
1
read-only
NMIPENDSET
NMIPENDSET
31
1
read-only
PENDSTCLR
PENDSTCLR
25
1
read-only
PENDSTSET
PENDSTSET
26
1
read-only
PENDSVCLR
PENDSVCLR
27
1
read-only
PENDSVSET
PENDSVSET
28
1
read-write
RETTOBASE
RETTOBASE
11
1
read-only
VECTACTIVE
VECTACTIVE
0
10
read-only
VECTPENDING
VECTPENDING
12
10
read-only
IP0
IP0
IP0
0x3FC
read-write
n
0x0
0x0
PRI_0
PRI_0
0
8
read-only
PRI_1
PRI_1
8
8
read-only
PRI_2
PRI_2
16
8
read-only
PRI_3
PRI_3
24
8
read-only
IP1
IP1
IP1
0x400
read-write
n
0x0
0x0
PRI_4
PRI_4
0
8
read-only
PRI_5
PRI_5
8
8
read-only
PRI_6
PRI_6
16
8
read-only
PRI_7
PRI_7
24
8
read-only
IP10
IP10
IP10
0x424
read-write
n
0x0
0x0
PRI_40
PRI_40
0
8
read-only
PRI_41
PRI_41
8
8
read-only
PRI_42
PRI_42
16
8
read-only
PRI_43
PRI_43
24
8
read-only
IP11
IP11
IP11
0x428
read-write
n
0x0
0x0
PRI_44
PRI_44
0
8
read-only
PRI_45
PRI_45
8
8
read-only
PRI_46
PRI_46
16
8
read-only
PRI_47
PRI_47
24
8
read-only
IP12
IP12
IP12
0x42C
read-write
n
0x0
0x0
PRI_48
PRI_48
0
8
read-only
PRI_49
PRI_49
8
8
read-only
PRI_50
PRI_50
16
8
read-only
PRI_51
PRI_51
24
8
read-only
IP13
IP13
IP13
0x430
read-write
n
0x0
0x0
PRI_52
PRI_52
0
8
read-only
PRI_53
PRI_53
8
8
read-only
PRI_54
PRI_54
16
8
read-only
PRI_55
PRI_55
24
8
read-only
IP14
IP14
IP14
0x434
read-write
n
0x0
0x0
PRI_56
PRI_56
0
8
read-only
PRI_57
PRI_57
8
8
read-only
PRI_58
PRI_58
16
8
read-only
PRI_59
PRI_59
24
8
read-only
IP15
IP15
IP15
0x438
read-write
n
0x0
0x0
PRI_60
PRI_60
0
8
read-only
PRI_61
PRI_61
8
8
read-only
PRI_62
PRI_62
16
8
read-only
PRI_63
PRI_63
24
8
read-only
IP2
IP2
IP2
0x404
read-write
n
0x0
0x0
PRI_10
PRI_10
16
8
read-only
PRI_11
PRI_11
24
8
read-only
PRI_8
PRI_8
0
8
read-only
PRI_9
PRI_9
8
8
read-only
IP3
IP3
IP3
0x408
read-write
n
0x0
0x0
PRI_12
PRI_12
0
8
read-only
PRI_13
PRI_13
8
8
read-only
PRI_14
PRI_14
16
8
read-only
PRI_15
PRI_15
24
8
read-only
IP4
IP4
IP4
0x40C
read-write
n
0x0
0x0
PRI_16
PRI_16
0
8
read-only
PRI_17
PRI_17
8
8
read-only
PRI_18
PRI_18
16
8
read-only
PRI_19
PRI_19
24
8
read-only
IP5
IP5
IP5
0x410
read-write
n
0x0
0x0
PRI_20
PRI_20
0
8
read-only
PRI_21
PRI_21
8
8
read-only
PRI_22
PRI_22
16
8
read-only
PRI_23
PRI_23
24
8
read-only
IP6
IP6
IP6
0x414
read-write
n
0x0
0x0
PRI_24
PRI_24
0
8
read-only
PRI_25
PRI_25
8
8
read-only
PRI_26
PRI_26
16
8
read-only
PRI_27
PRI_27
24
8
read-only
IP7
IP7
IP7
0x418
read-write
n
0x0
0x0
PRI_28
PRI_28
0
8
read-only
PRI_29
PRI_29
8
8
read-only
PRI_30
PRI_30
16
8
read-only
PRI_31
PRI_31
24
8
read-only
IP8
IP8
IP8
0x41C
read-write
n
0x0
0x0
PRI_32
PRI_32
0
8
read-only
PRI_33
PRI_33
8
8
read-only
PRI_34
PRI_34
16
8
read-only
PRI_35
PRI_35
24
8
read-only
IP9
IP9
IP9
0x420
read-write
n
0x0
0x0
PRI_36
PRI_36
0
8
read-only
PRI_37
PRI_37
8
8
read-only
PRI_38
PRI_38
16
8
read-only
PRI_39
PRI_39
24
8
read-only
MMFAR
MMFAR
MMFAR
0xD30
-1
read-write
n
0x0
0x0
NVIC
NVIC
NVIC
0x0
-1
read-write
n
0x0
0x0
INTLINESNUM
INTLINESNUM
0
5
read-only
SCR
SCR
SCR
0xD0C
read-write
n
0x0
0x0
SEVONPEND
SEVONPEND
4
1
read-write
SLEEPDEEP
SLEEPDEEP
2
1
read-write
SLEEPONEXIT
SLEEPONEXIT
1
1
read-write
SETENA0
SETENA0
SETENA0
0xFC
read-write
n
0x0
0x0
SETENA0
SETENA0
0
1
read-write
SETENA1
SETENA1
1
1
read-write
SETENA10
SETENA10
10
1
read-write
SETENA11
SETENA11
11
1
read-write
SETENA12
SETENA12
12
1
read-write
SETENA13
SETENA13
13
1
read-write
SETENA14
SETENA14
14
1
read-write
SETENA15
SETENA15
15
1
read-write
SETENA16
SETENA16
16
1
read-write
SETENA17
SETENA17
17
1
read-write
SETENA18
SETENA18
18
1
read-write
SETENA19
SETENA19
19
1
read-write
SETENA2
SETENA2
2
1
read-write
SETENA20
SETENA20
20
1
read-write
SETENA21
SETENA21
21
1
read-write
SETENA22
SETENA22
22
1
read-write
SETENA23
SETENA23
23
1
read-write
SETENA24
SETENA24
24
1
read-write
SETENA25
SETENA25
25
1
read-write
SETENA26
SETENA26
26
1
read-write
SETENA27
SETENA27
27
1
read-write
SETENA28
SETENA28
28
1
read-write
SETENA29
SETENA29
29
1
read-write
SETENA3
SETENA3
3
1
read-write
SETENA30
SETENA30
30
1
read-write
SETENA31
SETENA31
31
1
read-write
SETENA4
SETENA4
4
1
read-write
SETENA5
SETENA5
5
1
read-write
SETENA6
SETENA6
6
1
read-write
SETENA7
SETENA7
7
1
read-write
SETENA8
SETENA8
8
1
read-write
SETENA9
SETENA9
9
1
read-write
SETENA1
SETENA1
SETENA1
0x100
read-write
n
0x0
0x0
SETENA32
SETENA32
0
1
read-write
SETENA33
SETENA33
1
1
read-write
SETENA34
SETENA34
2
1
read-write
SETENA35
SETENA35
3
1
read-write
SETENA36
SETENA36
4
1
read-write
SETENA37
SETENA37
5
1
read-write
SETENA38
SETENA38
6
1
read-write
SETENA39
SETENA39
7
1
read-write
SETENA40
SETENA40
8
1
read-write
SETENA41
SETENA41
9
1
read-write
SETENA42
SETENA42
10
1
read-write
SETENA43
SETENA43
11
1
read-write
SETENA44
SETENA44
12
1
read-write
SETENA45
SETENA45
13
1
read-only
SETENA46
SETENA46
14
1
read-only
SETENA47
SETENA47
15
1
read-only
SETENA48
SETENA48
16
1
read-only
SETENA49
SETENA49
17
1
read-only
SETENA50
SETENA50
18
1
read-only
SETENA51
SETENA51
19
1
read-only
SETENA52
SETENA52
20
1
read-only
SETENA53
SETENA53
21
1
read-only
SETENA54
SETENA54
22
1
read-only
SETENA55
SETENA55
23
1
read-only
SETENA56
SETENA56
24
1
read-only
SETENA57
SETENA57
25
1
read-only
SETENA58
SETENA58
26
1
read-only
SETENA59
SETENA59
27
1
read-only
SETENA60
SETENA60
28
1
read-only
SETENA61
SETENA61
29
1
read-only
SETENA62
SETENA62
30
1
read-only
SETENA63
SETENA63
31
1
read-only
SETPEND0
SETPEND0
SETPEND0
0x1FC
read-write
n
0x0
0x0
SETPEND0
SETPEND0
0
1
read-write
SETPEND1
SETPEND1
1
1
read-write
SETPEND10
SETPEND10
10
1
read-write
SETPEND11
SETPEND11
11
1
read-write
SETPEND12
SETPEND12
12
1
read-write
SETPEND13
SETPEND13
13
1
read-write
SETPEND14
SETPEND14
14
1
read-write
SETPEND15
SETPEND15
15
1
read-write
SETPEND16
SETPEND16
16
1
read-write
SETPEND17
SETPEND17
17
1
read-write
SETPEND18
SETPEND18
18
1
read-write
SETPEND19
SETPEND19
19
1
read-write
SETPEND2
SETPEND2
2
1
read-write
SETPEND20
SETPEND20
20
1
read-write
SETPEND21
SETPEND21
21
1
read-write
SETPEND22
SETPEND22
22
1
read-write
SETPEND23
SETPEND23
23
1
read-write
SETPEND24
SETPEND24
24
1
read-write
SETPEND25
SETPEND25
25
1
read-write
SETPEND26
SETPEND26
26
1
read-write
SETPEND27
SETPEND27
27
1
read-write
SETPEND28
SETPEND28
28
1
read-write
SETPEND29
SETPEND29
29
1
read-write
SETPEND3
SETPEND3
3
1
read-write
SETPEND30
SETPEND30
30
1
read-write
SETPEND31
SETPEND31
31
1
read-write
SETPEND4
SETPEND4
4
1
read-write
SETPEND5
SETPEND5
5
1
read-write
SETPEND6
SETPEND6
6
1
read-write
SETPEND7
SETPEND7
7
1
read-write
SETPEND8
SETPEND8
8
1
read-write
SETPEND9
SETPEND9
9
1
read-write
SETPEND1
SETPEND1
SETPEND1
0x200
read-write
n
0x0
0x0
SETPEND32
SETPEND32
0
1
read-write
SETPEND33
SETPEND33
1
1
read-write
SETPEND34
SETPEND34
2
1
read-write
SETPEND35
SETPEND35
3
1
read-write
SETPEND36
SETPEND36
4
1
read-write
SETPEND37
SETPEND37
5
1
read-write
SETPEND38
SETPEND38
6
1
read-write
SETPEND39
SETPEND39
7
1
read-write
SETPEND40
SETPEND40
8
1
read-write
SETPEND41
SETPEND41
9
1
read-write
SETPEND42
SETPEND42
10
1
read-write
SETPEND43
SETPEND43
11
1
read-write
SETPEND44
SETPEND44
12
1
read-write
SETPEND45
SETPEND45
13
1
read-only
SETPEND46
SETPEND46
14
1
read-only
SETPEND47
SETPEND47
15
1
read-only
SETPEND48
SETPEND48
16
1
read-only
SETPEND49
SETPEND49
17
1
read-only
SETPEND50
SETPEND50
18
1
read-only
SETPEND51
SETPEND51
19
1
read-only
SETPEND52
SETPEND52
20
1
read-only
SETPEND53
SETPEND53
21
1
read-only
SETPEND54
SETPEND54
22
1
read-only
SETPEND55
SETPEND55
23
1
read-only
SETPEND56
SETPEND56
24
1
read-only
SETPEND57
SETPEND57
25
1
read-only
SETPEND58
SETPEND58
26
1
read-only
SETPEND59
SETPEND59
27
1
read-only
SETPEND60
SETPEND60
28
1
read-only
SETPEND61
SETPEND61
29
1
read-only
SETPEND62
SETPEND62
30
1
read-only
SETPEND63
SETPEND63
31
1
read-only
SHCSR
SHCSR
SHCSR
0xD20
read-write
n
0x0
0x0
BUSFAULTACT
BUSFAULTACT
1
1
read-write
BUSFAULTENA
BUSFAULTENA
17
1
read-write
BUSFAULTPENDED
BUSFAULTPENDED
14
1
read-write
MEMFAULTACT
MEMFAULTACT
0
1
read-write
MEMFAULTENA
MEMFAULTENA
16
1
read-write
MEMFAULTPENDED
MEMFAULTPENDED
13
1
read-write
MONITORACT
MONITORACT
8
1
read-write
PENDSVACT
PENDSVACT
10
1
read-write
SVCALLACT
SVCALLACT
7
1
read-write
SVCALLPENDED
SVCALLPENDED
15
1
read-write
SYSTICKACT
SYSTICKACT
11
1
read-write
USGFAULTACT
USGFAULTACT
3
1
read-write
USGFAULTENA
USGFAULTENA
18
1
read-write
SHPR0
SHPR0
SHPR0
0xD14
read-write
n
0x0
0x0
PRI_4
PRI_4
0
8
read-only
PRI_5
PRI_5
8
8
read-only
PRI_6
PRI_6
16
8
read-only
PRI_7
PRI_7
24
8
read-only
SHPR1
SHPR1
SHPR1
0xD18
read-write
n
0x0
0x0
PRI_10
PRI_10
16
8
read-only
PRI_11
PRI_11
24
8
read-only
PRI_8
PRI_8
0
8
read-only
PRI_9
PRI_9
8
8
read-only
SHPR2
SHPR2
SHPR2
0xD1C
read-write
n
0x0
0x0
PRI_12
PRI_12
0
8
read-only
PRI_13
PRI_13
8
8
read-only
PRI_14
PRI_14
16
8
read-only
PRI_15
PRI_15
24
8
read-only
STIR
STIR
STIR
0xEFC
read-write
n
0x0
0x0
INTID
INTID
0
9
read-only
SYSTICKCALVR
SYSTICKCALVR
SYSTICKCALVR
0x18
-1
read-write
n
0x0
0x0
NOREF
NOREF
31
1
read-only
SKEW
SKEW
30
1
read-only
TENMS
TENMS
0
24
read-only
SYSTICKCSR
SYSTICKCSR
SYSTICKCSR
0xC
read-write
n
0x0
0x0
CLKSOURCE
CLKSOURCE
2
1
read-write
COUNTFLAG
COUNTFLAG
16
1
read-only
ENABLE
ENABLE
0
1
read-write
TICKINT
TICKINT
1
1
read-write
SYSTICKCVR
SYSTICKCVR
SYSTICKCVR
0x14
read-write
n
0x0
0x0
CURRENT
CURRENT
0
24
read-write
SYSTICKRVR
SYSTICKRVR
SYSTICKRVR
0x10
read-write
n
0x0
0x0
RELOAD
RELOAD
0
24
read-write
VTOR
VTOR
VTOR
0xD04
read-write
n
0x0
0x0
TBLBASE
TBLBASE
29
1
read-write
TBLOFF
TBLOFF
7
22
read-write
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
CR
CR
PWR power control register
0x0
-1
read-write
n
0x0
0x0
CSBF
CSBF
3
1
write-only
CWUF
CWUF
2
1
write-only
DBP
DBP
8
1
read-write
FWU
FWU
10
1
read-write
LPDS
LPDS
0
1
read-write
LPRUN
LPRUN
14
1
read-write
PDDS
PDDS
1
1
read-write
PLS
PLS
5
3
read-write
PVDE
PVDE
4
1
read-write
ULP
ULP
9
1
read-write
VOS
VOS
11
2
read-write
CSR
CSR
PWR power control/status register
0x4
-1
read-write
n
0x0
0x0
EWUP1
EWUP1
8
1
read-write
EWUP2
EWUP2
9
1
read-write
EWUP3
EWUP3
10
1
read-write
PVDO
PVDO
2
1
read-only
SBF
SBF
1
1
read-only
VOSF
VOSF
4
1
read-only
VREFINTRDYF
VREFINTRDYF
3
1
read-only
WUF
WUF
0
1
read-only
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
AHB1LPENR
AHB1LPENR
APB1 peripheral clock enable in low power mode register
0x30
-1
read-write
n
0x0
0x0
COMPLPEN
COMPLPEN
31
1
DACLPEN
DACLPEN
29
1
I2C1LPEN
I2C1LPEN
21
1
I2C2LPEN
I2C2LPEN
22
1
LCDLPEN
LCDLPEN
9
1
PWRLPEN
PWRLPEN
28
1
SPI2LPEN
SPI2LPEN
14
1
TIM2LPEN
TIM2LPEN
0
1
TIM3LPEN
TIM3LPEN
1
1
TIM4LPEN
TIM4LPEN
2
1
TIM6LPEN
TIM6LPEN
4
1
TIM7LPEN
TIM7LPEN
5
1
USART2LPEN
USART2LPEN
17
1
USART3LPEN
USART3LPEN
18
1
USBLPEN
USBLPEN
23
1
WWDLPEN
WWDLPEN
11
1
AHB2LPENR
AHB2LPENR
APB2 peripheral clock enable in low power mode register
0x2C
-1
read-write
n
0x0
0x0
ADC1EN
ADC1EN
9
1
SPI1EN
SPI1EN
12
1
SYSCFGEN
SYSCFGEN
0
1
TIM10EN
TIM10EN
3
1
TIM11EN
TIM11EN
4
1
TIM9EN
TIM9EN
2
1
USART1EN
USART1EN
14
1
AHBENR
AHBENR
AHB peripheral clock enable register
0x1C
-1
read-write
n
0x0
0x0
CRCEN
CRCEN
12
1
DMA1EN
DMA1EN
24
1
FLITFEN
FLITFEN
15
1
GPIOAEN
GPIOAEN
0
1
GPIOBEN
GPIOBEN
1
1
GPIOCEN
GPIOCEN
2
1
GPIODEN
GPIODEN
3
1
GPIOEEN
GPIOEEN
4
1
GPIOFEN
GPIOFEN
5
1
AHBLPENR
AHBLPENR
AHB peripheral clock enable in low power mode register
0x28
-1
read-write
n
0x0
0x0
CRCLPEN
CRCLPEN
12
1
DMA1LPEN
DMA1LPEN
24
1
FLITFLPEN
FLITFLPEN
15
1
GPIOALPEN
GPIOALPEN
0
1
GPIOBLPEN
GPIOBLPEN
1
1
GPIOCLPEN
GPIOCLPEN
2
1
GPIODLPEN
GPIODLPEN
3
1
GPIOELPEN
GPIOELPEN
4
1
GPIOFLPEN
GPIOFLPEN
5
1
SRAMLPEN
SRAMLPEN
16
1
APB1ENR
APB1ENR
APB1 peripheral clock enable register
0x24
read-write
n
0x0
0x0
COMPEN
COMPEN
31
1
DACEN
DACEN
29
1
I2C1EN
I2C1EN
21
1
I2C2EN
I2C2EN
22
1
LCDEN
LCDEN
9
1
PWREN
PWREN
28
1
SPI2EN
SPI2EN
14
1
TIM2EN
TIM2EN
0
1
TIM3EN
TIM3EN
1
1
TIM4EN
TIM4EN
2
1
TIM6EN
TIM6EN
4
1
TIM7EN
TIM7EN
5
1
USART2EN
USART2EN
17
1
USART3EN
USART3EN
18
1
USBEN
USBEN
23
1
WWDGEN
WWDGEN
11
1
APB1RSTR
APB1RSTR
APB1 peripheral reset register
0x18
read-write
n
0x0
0x0
COMPRST
COMPRST
31
1
DACRST
DACRST
29
1
I2C1RST
I2C1RST
21
1
I2C2RST
I2C2RST
22
1
LCDRST
LCDRST
9
1
PWRRST
PWRRST
28
1
SPI2RST
SPI2RST
14
1
TIM2RST
TIM2RST
0
1
TIM3RST
TIM3RST
1
1
TIM4RST
TIM4RST
2
1
TIM6RST
TIM6RST
4
1
TIM7RST
TIM7RST
5
1
USART2RST
USART2RST
17
1
USART3RST
USART3RST
18
1
USBRST
USBRST
23
1
WWDGRST
WWDGRST
11
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register
0x20
read-write
n
0x0
0x0
ADC1EN
ADC1EN
9
1
SPI1EN
SPI1EN
12
1
SYSCFGEN
SYSCFGEN
0
1
TIM10EN
TIM10EN
3
1
TIM11EN
TIM11EN
4
1
TIM9EN
TIM9EN
2
1
USART1EN
USART1EN
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x14
read-write
n
0x0
0x0
ADC1RST
ADC1RST
9
1
SPI1RST
SPI1RST
12
1
SYSCFGRST
SYSCFGRST
0
1
TIM10RST
TIM10RST
3
1
TIM11RST
TIM11RST
4
1
TIM9RST
TIM9RST
2
1
USART1RST
USART1RST
14
1
APBRSTR
APBRSTR
AHB peripheral reset register
0x10
read-write
n
0x0
0x0
CRCRST
CRCRST
12
1
read-write
DMA1RST
DMA1RST
24
1
read-write
FLITFRST
FLITFRST
15
1
read-write
GPIOARST
GPIOARST
0
1
read-write
GPIOBRST
GPIOBRST
1
1
read-write
GPIOCRST
GPIOCRST
2
1
read-write
GPIODRST
GPIODRST
3
1
read-write
GPIOERST
GPIOERST
4
1
read-write
GPIOFRST
GPIOFRST
5
1
read-write
CFGR
CFGR
Clock configuration register
0x8
read-write
n
0x0
0x0
HPRE
HPRE
4
4
read-write
MCOPRE
MCOPRE
28
3
read-write
MCOSEL
MCOSEL
24
3
read-write
PLLDIV
PLLDIV
22
2
read-write
PLLMUL
PLLMUL
18
4
read-write
PLLSRC
PLLSRC
16
1
read-write
PPRE1
PPRE1
8
3
read-write
PPRE2
PPRE2
11
3
read-write
SW
SW
0
2
read-write
SWS
SWS
2
2
read-only
CIR
CIR
Clock interrupt register
0xC
read-write
n
0x0
0x0
CSSC
CSSC
23
1
write-only
CSSF
CSSF
7
1
read-only
HSERDYC
HSERDYC
19
1
write-only
HSERDYF
HSERDYF
3
1
read-only
HSERDYIE
HSERDYIE
11
1
read-write
HSIRDYC
HSIRDYC
18
1
write-only
HSIRDYF
HSIRDYF
2
1
read-only
HSIRDYIE
HSIRDYIE
10
1
read-write
LSERDYC
LSERDYC
17
1
write-only
LSERDYF
LSERDYF
1
1
read-only
LSERDYIE
LSERDYIE
9
1
read-write
LSIRDYC
LSIRDYC
16
1
write-only
LSIRDYF
LSIRDYF
0
1
read-only
LSIRDYIE
LSIRDYIE
8
1
read-write
MSIRDYC
MSIRDYC
21
1
write-only
MSIRDYF
MSIRDYF
5
1
read-only
MSIRDYIE
MSIRDYIE
13
1
read-write
PLLRDYC
PLLRDYC
20
1
write-only
PLLRDYF
PLLRDYF
4
1
read-only
PLLRDYIE
PLLRDYIE
12
1
read-write
CR
CR
Clock control register
0x0
-1
read-write
n
0x0
0x0
CSSON
CSSON
28
1
read-write
HSEBYP
HSEBYP
18
1
read-write
HSEON
HSEON
16
1
read-write
HSERDY
HSERDY
17
1
read-only
HSION
HSION
0
1
read-write
HSIRDY
HSIRDY
1
1
read-only
MSION
MSION
8
1
read-write
MSIRDY
MSIRDY
9
1
read-only
PLLON
PLLON
24
1
read-write
PLLRDY
PLLRDY
25
1
read-only
RTCPRE
RTCPRE
29
2
read-write
CSR
CSR
Control/status register
0x34
-1
read-write
n
0x0
0x0
IWDGRSTF
IWDGRSTF
29
1
LPWRRSTF
LPWRRSTF
31
1
LSEBYP
LSEBYP
10
1
LSEON
LSEON
8
1
LSERDY
LSERDY
9
1
LSION
LSION
0
1
LSIRDY
LSIRDY
1
1
OBLRSTF
OBLRSTF
25
1
PINRSTF
PINRSTF
26
1
PORRSTF
PORRSTF
27
1
RMVF
RMVF
24
1
RTCEN
RTCEN
22
1
RTCRST
RTCRST
23
1
RTCSEL
RTCSEL
16
2
SFTRSTF
SFTRSTF
28
1
WWDGRSTF
WWDGRSTF
30
1
ICSCR
ICSCR
Internal clock sources calibration register
0x4
-1
read-write
n
0x0
0x0
HSICAL
HSICAL
0
8
read-only
HSITRIM
HSITRIM
8
5
read-write
MSICAL
MSICAL
16
8
read-only
MSIRANGE
MSIRANGE
13
3
read-write
MSITRIM
MSITRIM
24
8
read-write
RI
Routing interface (RI)
RI
0x0
0x0
0x400
registers
n
ASCR1
ASCR1
RI analog switches control register 1
0x4
read-write
n
0x0
0x0
CH0
CH0
0
1
CH1
CH1
1
1
CH10
CH10
10
1
CH11
CH11
11
1
CH12
CH12
12
1
CH13
CH13
13
1
CH14
CH14
14
1
CH15
CH15
15
1
CH18
CH18
18
1
CH19
CH19
19
1
CH2
CH2
2
1
CH20
CH20
20
1
CH21
CH21
21
1
CH22
CH22
22
1
CH23
CH23
23
1
CH24
CH24
24
1
CH25
CH25
25
1
CH3
CH3
3
1
CH6
CH6
6
1
CH7
CH7
7
1
CH8
CH8
8
1
CH9
CH9
9
1
ST
ST
31
1
VCOMP
VCOMP
26
1
ASCR2
ASCR2
RI analog switches control register 2
0x8
read-write
n
0x0
0x0
GR10_1
GR10_1
0
1
GR10_2
GR10_2
1
1
GR10_3
GR10_3
2
1
GR10_4
GR10_4
3
1
GR4_1
GR4_1
9
1
GR4_2
GR4_2
10
1
GR4_3
GR4_3
11
1
GR5_1
GR5_1
6
1
GR5_2
GR5_2
7
1
GR5_3
GR5_3
8
1
GR6_1
GR6_1
4
1
GR6_2
GR6_2
5
1
HYSCR1
HYSCR1
RI hysteresis control register 1
0xC
read-write
n
0x0
0x0
PA
PA
0
16
PB
PB
16
16
HYSCR2
HYSCR2
RI hysteresis control register 2
0x10
read-write
n
0x0
0x0
PC
PC
0
16
PD
PD
16
16
HYSCR3
HYSCR3
RI hysteresis control register 3
0x14
read-write
n
0x0
0x0
PE
PE
0
16
ICR
ICR
RI input capture register
0x0
read-write
n
0x0
0x0
IC1
IC1
18
1
IC1IOS
IC1IOS
0
4
IC2
IC2
19
1
IC2IOS
IC2IOS
4
4
IC3
IC3
20
1
IC3IOS
IC3IOS
8
4
IC4
IC4
21
1
IC4IOS
IC4IOS
12
4
TIM
TIM
16
2
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
ALRMAR
ALRMAR
RTC alarm A register
0x1C
read-write
n
0x0
0x0
DT
DT
28
2
DU
DU
24
4
HT
HT
20
2
HU
HU
16
4
MNT
MNT
12
3
MNU
MNU
8
4
MSK0
MSK0
7
1
MSK1
MSK1
15
1
MSK2
MSK2
23
1
MSK3
MSK3
31
1
PM
PM
22
1
ST
ST
4
3
SU
SU
0
4
WDSEL
WDSEL
30
1
ALRMBR
ALRMBR
RTC alarm B register
0x20
read-write
n
0x0
0x0
DT
DT
28
2
DU
DU
24
4
HT
HT
20
2
HU
HU
16
4
MNT
MNT
12
3
MNU
MNU
8
4
MSK0
MSK0
7
1
MSK1
MSK1
15
1
MSK2
MSK2
23
1
MSK3
MSK3
31
1
PM
PM
22
1
ST
ST
4
3
SU
SU
0
4
WDSEL
WDSEL
30
1
BK0R
BK0R
RTC backup register
0x50
read-write
n
0x0
0x0
BK0R
BK0R
0
32
BK10R
BK10R
RTC backup register
0x78
read-write
n
0x0
0x0
BK10R
BK10R
0
32
BK11R
BK11R
RTC backup register
0x7C
read-write
n
0x0
0x0
BK11R
BK11R
0
32
BK12R
BK12R
RTC backup register
0x80
read-write
n
0x0
0x0
BK12R
BK12R
0
32
BK13R
BK13R
RTC backup register
0x84
read-write
n
0x0
0x0
BK13R
BK13R
0
32
BK14R
BK14R
RTC backup register
0x88
read-write
n
0x0
0x0
BK14R
BK14R
0
32
BK15R
BK15R
RTC backup register
0x8C
read-write
n
0x0
0x0
BK15R
BK15R
0
32
BK16R
BK16R
RTC backup register
0x90
read-write
n
0x0
0x0
BK16R
BK16R
0
32
BK17R
BK17R
RTC backup register
0x94
read-write
n
0x0
0x0
BK17R
BK17R
0
32
BK18R
BK18R
RTC backup register
0x98
read-write
n
0x0
0x0
BK18R
BK18R
0
32
BK19R
BK19R
RTC backup register
0x9C
read-write
n
0x0
0x0
BK19R
BK19R
0
32
BK1R
BK1R
RTC backup register
0x54
read-write
n
0x0
0x0
BK1R
BK1R
0
32
BK2R
BK2R
RTC backup register
0x58
read-write
n
0x0
0x0
BK2R
BK2R
0
32
BK3R
BK3R
RTC backup register
0x5C
read-write
n
0x0
0x0
BK3R
BK3R
0
32
BK4R
BK4R
RTC backup register
0x60
read-write
n
0x0
0x0
BK4R
BK3R
0
32
BK5R
BK5R
RTC backup register
0x64
read-write
n
0x0
0x0
BK5R
BK5R
0
32
BK6R
BK6R
RTC backup register
0x68
read-write
n
0x0
0x0
BK6R
BK6R
0
32
BK7R
BK7R
RTC backup register
0x6C
read-write
n
0x0
0x0
BK7R
BK7R
0
32
BK8R
BK8R
RTC backup register
0x70
read-write
n
0x0
0x0
BK8R
BK8R
0
32
BK9R
BK9R
RTC backup register
0x74
read-write
n
0x0
0x0
BK9R
BK9R
0
32
CALIBR
CALIBR
RTC calibration register
0x18
read-write
n
0x0
0x0
DC
DC
0
5
DCS
DCS
7
1
CR
CR
RTC control register
0x8
read-write
n
0x0
0x0
ADD1H
ADD1H
16
1
ALRAE
ALRAE
8
1
ALRAIE
ALRAIE
12
1
ALRBE
ALRBE
9
1
ALRBIE
ALRBIE
13
1
BCK
BCK
18
1
COE
COE
23
1
DCE
DCE
7
1
FMT
FMT
6
1
OSEL
OSEL
21
2
POL
POL
20
1
REFCKON
REFCKON
4
1
SUB1H
SUB1H
17
1
TSE
TSE
11
1
TSEDGE
TSEDGE
3
1
TSIE
TSIE
15
1
WUCKSEL
WUCKSEL
0
3
WUTE
WUTE
10
1
WUTIE
WUTIE
14
1
DR
DR
RTC date register
0x4
-1
read-write
n
0x0
0x0
DT
DT
4
2
DU
DU
0
4
MT
MT
12
1
MU
MU
8
4
WDU
WDU
13
3
YT
YT
20
4
YU
YU
16
4
ISR
ISR
RTC initialization and status register
0xC
-1
read-write
n
0x0
0x0
ALRAF
ALRAF
8
1
read-only
ALRAWF
ALRAWF
0
1
read-only
ALRBF
ALRBF
9
1
read-only
ALRBWF
ALRBWF
1
1
read-only
INIT
INIT
7
1
read-write
INITF
INITF
6
1
read-only
INITS
INITS
4
1
read-only
RSF
RSF
5
1
read-only
TAMPF
TAMPF
13
1
read-only
TSF
TSF
11
1
read-only
TSOVF
TSOVF
12
1
read-only
WUTF
WUTF
10
1
read-only
WUTWF
WUTWF
2
1
read-only
PRER
PRER
RTC prescaler register
0x10
-1
read-only
n
0x0
0x0
PREDIV_A
PREDIV_A
16
7
PREDIV_S
PREDIV_S
0
13
TAFCR
TAFCR
RTC tamper and alternate function configuration register
0x40
read-only
n
0x0
0x0
ALARMOUTTYPE
ALARMOUTTYPE
18
1
TAMPE
TAMPE
0
1
TAMPEDGE
TAMPEDGE
1
1
TAMPIE
TAMPIE
2
1
TR
TR
RTC time register
0x0
read-write
n
0x0
0x0
HT
HT
20
2
HU
HU
16
4
MNT
MNT
12
3
MNU
MNU
8
4
PM
PM
22
1
ST
ST
4
3
SU
SU
0
4
TSDR
TSDR
RTC time stamp date register
0x34
read-only
n
0x0
0x0
DT
DT
4
2
DU
DU
0
4
MT
MT
12
1
MU
MU
8
4
WDU
WDU
13
3
TSTR
TSTR
RTC time stamp time register
0x30
read-only
n
0x0
0x0
HT
HT
20
2
HU
HU
16
4
MNT
MNT
12
3
MNU
MNU
8
4
PM
PM
22
1
ST
ST
4
3
SU
SU
0
4
WPR
WPR
RTC write protection register
0x24
write-only
n
0x0
0x0
KEY
KEY
0
8
WUTR
WUTR
RTC wakeup timer register
0x14
-1
read-write
n
0x0
0x0
WUARV
WUARV
0
16
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
CR1
CR1
SPI control register 1
0x0
read-write
n
0x0
0x0
BIDIMODE
BIDIMODE
15
1
BIDIOE
BIDIOE
14
1
BR
BR
3
3
CPHA
CPHA
0
1
CPOL
CPOL
1
1
CRCEN
CRCEN
13
1
CRCNEXT
CRCNEXT
12
1
DFF
DFF
11
1
LSBFIRST
LSBFIRST
7
1
MSTR
MSTR
2
1
RXONLY
RXONLY
10
1
SPE
SPE
6
1
SSI
SSI
8
1
SSM
SSM
9
1
CR2
CR2
SPI control register 2
0x4
read-write
n
0x0
0x0
ERRIE
ERRIE
5
1
RXDMAEN
RXDMAEN
0
1
RXNEIE
RXNEIE
6
1
SSOE
SSOE
2
1
TXDMAEN
TXDMAEN
1
1
TXEIE
TXEIE
7
1
CRCPR
CRCPR
SPI CRC polynomial register
0x10
read-write
n
0x0
0x0
CRCPOLY
CRCPOLY
0
16
DR
DR
SPI data register
0xC
read-write
n
0x0
0x0
DR
DR
0
16
RXCRCR
RXCRCR
SPI Rx CRC register
0x14
read-only
n
0x0
0x0
RxCRC
RxCRC
0
16
SR
SR
SPI status register
0x8
read-only
n
0x0
0x0
BSY
BSY
7
1
CRCERR
CRCERR
4
1
MODF
MODF
5
1
OVR
OVR
6
1
RXNE
RXNE
0
1
TXE
TXE
1
1
TXCRCR
TXCRCR
SPI Tx CRC register
0x18
read-only
n
0x0
0x0
TxCRC
TxCRC
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
CR1
CR1
SPI control register 1
0x0
read-write
n
0x0
0x0
BIDIMODE
BIDIMODE
15
1
BIDIOE
BIDIOE
14
1
BR
BR
3
3
CPHA
CPHA
0
1
CPOL
CPOL
1
1
CRCEN
CRCEN
13
1
CRCNEXT
CRCNEXT
12
1
DFF
DFF
11
1
LSBFIRST
LSBFIRST
7
1
MSTR
MSTR
2
1
RXONLY
RXONLY
10
1
SPE
SPE
6
1
SSI
SSI
8
1
SSM
SSM
9
1
CR2
CR2
SPI control register 2
0x4
read-write
n
0x0
0x0
ERRIE
ERRIE
5
1
RXDMAEN
RXDMAEN
0
1
RXNEIE
RXNEIE
6
1
SSOE
SSOE
2
1
TXDMAEN
TXDMAEN
1
1
TXEIE
TXEIE
7
1
CRCPR
CRCPR
SPI CRC polynomial register
0x10
read-write
n
0x0
0x0
CRCPOLY
CRCPOLY
0
16
DR
DR
SPI data register
0xC
read-write
n
0x0
0x0
DR
DR
0
16
RXCRCR
RXCRCR
SPI Rx CRC register
0x14
read-only
n
0x0
0x0
RxCRC
RxCRC
0
16
SR
SR
SPI status register
0x8
read-only
n
0x0
0x0
BSY
BSY
7
1
CRCERR
CRCERR
4
1
MODF
MODF
5
1
OVR
OVR
6
1
RXNE
RXNE
0
1
TXE
TXE
1
1
TXCRCR
TXCRCR
SPI Tx CRC register
0x18
read-only
n
0x0
0x0
TxCRC
TxCRC
0
16
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x400
registers
n
EXTICR1
EXTICR1
SYSCFG external interrupt configuration register 1
0x8
read-write
n
0x0
0x0
EXTI0
EXTI0
0
4
EXTI1
EXTI1
4
4
EXTI2
EXTI2
8
4
EXTI3
EXTI3
12
4
EXTICR2
EXTICR2
SYSCFG external interrupt configuration register 2
0xC
read-write
n
0x0
0x0
EXTI4
EXTI4
0
4
EXTI5
EXTI5
4
4
EXTI6
EXTI6
8
4
EXTI7
EXTI7
12
4
EXTICR3
EXTICR3
SYSCFG external interrupt configuration register 3
0x10
read-write
n
0x0
0x0
EXTI10
EXTI10
8
4
EXTI11
EXTI11
12
4
EXTI8
EXTI8
0
4
EXTI9
EXTI9
4
4
EXTICR4
EXTICR4
SYSCFG external interrupt configuration register 4
0x14
read-write
n
0x0
0x0
EXTI12
EXTI12
0
4
EXTI13
EXTI13
4
4
EXTI14
EXTI14
8
4
EXTI15
EXTI15
12
4
MEMRMP
MEMRMP
SYSCFG memory remap register
0x0
read-write
n
0x0
0x0
MEM_MODE
MEM_MODE
0
2
PMC
PMC
SYSCFG peripheral mode configuration register
0x4
read-write
n
0x0
0x0
DP_USB_PU_EN
DP_USB_PU_EN
0
1
TIM11
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM2
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM3
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM4
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM6
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM7
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
TIM9
General-purpose timers
TIM1
0x0
0x0
0x400
registers
n
ARR
ARR
TIMx auto-reload register
0x2C
read-write
n
0x0
0x0
ARR
ARR
0
16
CCER
CCER
TIMx capture/compare enable register
0x20
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CCMR1
CCMR1
TIMx capture/compare mode register 1
0x18
read-write
n
0x0
0x0
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
IC1S
IC1S
0
2
IC2F
IC2F
12
4
IC2PSC
IC2PSC
10
2
IC2S
IC2S
8
2
CCR1
CCR1
TIMx capture/compare register 1
0x34
read-write
n
0x0
0x0
CCR1
CCR1
0
16
CCR2
CCR2
TIMx capture/compare register 2
0x38
read-write
n
0x0
0x0
CCR2
CCR2
0
16
CNT
CNT
TIMx counter
0x24
read-write
n
0x0
0x0
CNT
CNT
0
16
CR1
CR1
TIMx control register 1
0x0
read-write
n
0x0
0x0
ARPE
ARPE
7
1
CEN
CEN
0
1
CKD
CKD
8
2
OPM
OPM
3
1
UDIS
UDIS
1
1
URS
URS
2
1
CR2
CR2
TIMx control register 2
0x4
read-write
n
0x0
0x0
MMS
MMS
4
3
read-only
DIER
DIER
TIMx Interrupt enable register
0xC
read-write
n
0x0
0x0
CC1IE
CC1IE
1
1
CC2IE
CC2IE
2
1
TIE
TIE
6
1
UIE
UIE
0
1
EGR
EGR
TIMx event generation register
0x14
write-only
n
0x0
0x0
CC1G
CC1G
1
1
CC2G
CC2G
2
1
TG
TG
6
1
UG
UG
0
1
OR
OR
option register
0x50
read-write
n
0x0
0x0
TI1_RMP
TI1_RMP
0
2
read-write
PSC
PSC
TIMx prescaler
0x28
read-write
n
0x0
0x0
PSC
PSC
0
16
SMCR
SMCR
TIMx slave mode control register
0x8
read-write
n
0x0
0x0
ECE
ECE
14
1
ETF
ETF
8
4
ETP
ETP
15
1
ETPS
ETPS
12
2
MSM
MSM
7
1
SMS
SMS
0
3
TS
TS
4
3
SR
SR
TIMx status register
0x10
read-only
n
0x0
0x0
CC1IF
CC1IF
1
1
CC1OF
CC1OF
9
1
CC2IF
CC2IF
2
1
CC2OF
CC2OF
10
1
TIF
TIF
6
1
UIF
UIF
0
1
USART1
Universal synchronous asynchronous receiver
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0xC
read-write
n
0x0
0x0
IDLEIE
IDLEIE
4
1
M
M
12
1
OVER8
OVER8
15
1
PCE
PCE
10
1
PEIE
PEIE
8
1
PS
PS
9
1
RE
RE
2
1
RWU
RWU
1
1
RXNEIE
RXNEIE
5
1
SBK
SBK
0
1
TCIE
TCIE
6
1
TE
TE
3
1
TXEIE
TXEIE
7
1
UE
UE
13
1
WAKE
WAKE
11
1
CR2
CR2
Control register 2
0x10
read-write
n
0x0
0x0
ADD
ADD
0
4
CLKEN
CLKEN
11
1
CPHA
CPHA
9
1
CPOL
CPOL
10
1
LBCL
LBCL
8
1
LBDIE
LBDIE
6
1
LBDL
LBDL
5
1
LINEN
LINEN
14
1
STOP
STOP
12
2
CR3
CR3
Control register 3
0x14
read-write
n
0x0
0x0
CTSE
CTSE
9
1
CTSIE
CTSIE
10
1
DMAR
DMAR
6
1
DMAT
DMAT
7
1
EIE
EIE
0
1
HDSEL
HDSEL
3
1
IREN
IREN
1
1
IRLP
IRLP
2
1
NACK
NACK
4
1
ONEBITE
ONEBITE
11
1
RTSE
RTSE
8
1
SCEN
SCEN
5
1
DR
DR
Data register
0x4
read-write
n
0x0
0x0
DR
DR
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
read-write
n
0x0
0x0
GT
GT
8
8
PSC
PSC
0
8
SR
SR
Status register
0x0
-1
read-write
n
0x0
0x0
CTS
CTS
9
1
write-only
FE
FE
1
1
read-only
IDLE
IDLE
4
1
read-only
LBD
LBD
8
1
write-only
NE
NE
2
1
read-only
ORE
ORE
3
1
read-only
PE
PE
0
1
read-only
RXNE
RXNE
5
1
write-only
TC
TC
6
1
write-only
TXE
TXE
7
1
read-only
USART2
Universal synchronous asynchronous receiver
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0xC
read-write
n
0x0
0x0
IDLEIE
IDLEIE
4
1
M
M
12
1
OVER8
OVER8
15
1
PCE
PCE
10
1
PEIE
PEIE
8
1
PS
PS
9
1
RE
RE
2
1
RWU
RWU
1
1
RXNEIE
RXNEIE
5
1
SBK
SBK
0
1
TCIE
TCIE
6
1
TE
TE
3
1
TXEIE
TXEIE
7
1
UE
UE
13
1
WAKE
WAKE
11
1
CR2
CR2
Control register 2
0x10
read-write
n
0x0
0x0
ADD
ADD
0
4
CLKEN
CLKEN
11
1
CPHA
CPHA
9
1
CPOL
CPOL
10
1
LBCL
LBCL
8
1
LBDIE
LBDIE
6
1
LBDL
LBDL
5
1
LINEN
LINEN
14
1
STOP
STOP
12
2
CR3
CR3
Control register 3
0x14
read-write
n
0x0
0x0
CTSE
CTSE
9
1
CTSIE
CTSIE
10
1
DMAR
DMAR
6
1
DMAT
DMAT
7
1
EIE
EIE
0
1
HDSEL
HDSEL
3
1
IREN
IREN
1
1
IRLP
IRLP
2
1
NACK
NACK
4
1
ONEBITE
ONEBITE
11
1
RTSE
RTSE
8
1
SCEN
SCEN
5
1
DR
DR
Data register
0x4
read-write
n
0x0
0x0
DR
DR
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
read-write
n
0x0
0x0
GT
GT
8
8
PSC
PSC
0
8
SR
SR
Status register
0x0
-1
read-write
n
0x0
0x0
CTS
CTS
9
1
write-only
FE
FE
1
1
read-only
IDLE
IDLE
4
1
read-only
LBD
LBD
8
1
write-only
NE
NE
2
1
read-only
ORE
ORE
3
1
read-only
PE
PE
0
1
read-only
RXNE
RXNE
5
1
write-only
TC
TC
6
1
write-only
TXE
TXE
7
1
read-only
USART3
Universal synchronous asynchronous receiver
USART
0x0
0x0
0x400
registers
n
BRR
BRR
Baud rate register
0x8
read-write
n
0x0
0x0
DIV_Fraction
DIV_Fraction
0
4
DIV_Mantissa
DIV_Mantissa
4
12
CR1
CR1
Control register 1
0xC
read-write
n
0x0
0x0
IDLEIE
IDLEIE
4
1
M
M
12
1
OVER8
OVER8
15
1
PCE
PCE
10
1
PEIE
PEIE
8
1
PS
PS
9
1
RE
RE
2
1
RWU
RWU
1
1
RXNEIE
RXNEIE
5
1
SBK
SBK
0
1
TCIE
TCIE
6
1
TE
TE
3
1
TXEIE
TXEIE
7
1
UE
UE
13
1
WAKE
WAKE
11
1
CR2
CR2
Control register 2
0x10
read-write
n
0x0
0x0
ADD
ADD
0
4
CLKEN
CLKEN
11
1
CPHA
CPHA
9
1
CPOL
CPOL
10
1
LBCL
LBCL
8
1
LBDIE
LBDIE
6
1
LBDL
LBDL
5
1
LINEN
LINEN
14
1
STOP
STOP
12
2
CR3
CR3
Control register 3
0x14
read-write
n
0x0
0x0
CTSE
CTSE
9
1
CTSIE
CTSIE
10
1
DMAR
DMAR
6
1
DMAT
DMAT
7
1
EIE
EIE
0
1
HDSEL
HDSEL
3
1
IREN
IREN
1
1
IRLP
IRLP
2
1
NACK
NACK
4
1
ONEBITE
ONEBITE
11
1
RTSE
RTSE
8
1
SCEN
SCEN
5
1
DR
DR
Data register
0x4
read-write
n
0x0
0x0
DR
DR
0
9
GTPR
GTPR
Guard time and prescaler register
0x18
read-write
n
0x0
0x0
GT
GT
8
8
PSC
PSC
0
8
SR
SR
Status register
0x0
-1
read-write
n
0x0
0x0
CTS
CTS
9
1
write-only
FE
FE
1
1
read-only
IDLE
IDLE
4
1
read-only
LBD
LBD
8
1
write-only
NE
NE
2
1
read-only
ORE
ORE
3
1
read-only
PE
PE
0
1
read-only
RXNE
RXNE
5
1
write-only
TC
TC
6
1
write-only
TXE
TXE
7
1
read-only
USB
USB
USB
0x0
0x0
0x400
registers
n
BTABLE
USB_BTABLE
USB_BTABLE
0x50
read-only
n
0x0
0x0
BTABLE
BTABLE
0
16
CNTR
USB_CNTR
USB_CNTR
0x40
-1
read-write
n
0x0
0x0
CTRM
CTRM
15
1
ERRM
ERRM
13
1
ESOFM
ESOFM
8
1
FRES
FRES
0
1
FSUSP
FSUSP
3
1
LP_MODE
LP_MODE
2
1
PDWN
PDWN
1
1
PMAOVRM
PMAOVRM
14
1
RESETM
RESETM
10
1
RESUME
RESUME
4
1
SOFM
SOFM
9
1
SUSPM
SUSPM
11
1
WKUPM
WKUPM
12
1
DADDR
USB_DADDR
USB_DADDR
0x4C
read-write
n
0x0
0x0
ADD
ADD
0
7
EF
EF
7
1
EP0R
USB_EP0R
USB_EP0R
0x0
read-write
n
0x0
0x0
CTR_RX
CTR_RX
15
1
write-only
CTR_TX
CTR_TX
7
1
write-only
DTOG_RX
DTOG_RX
14
1
write-only
DTOG_TX
DTOG_TX
6
1
write-only
EA
EA
0
4
read-write
EP_KIND
EP_KIND
8
1
read-write
EP_TYPE
EP_TYPE
9
2
read-write
SETUP
SETUP
11
1
read-only
STAT_RX
STAT_RX
12
2
write-only
STAT_TX
STAT_TX
4
2
write-only
EP1R
USB_EP1R
USB_EP1R
0x4
write-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP2R
USB_EP2R
USB_EP2R
0x8
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP3R
USB_EP3R
USB_EP3R
0xC
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP4R
USB_EP4R
USB_EP4R
0x10
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP5R
USB_EP5R
USB_EP5R
0x14
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP6R
USB_EP6R
USB_EP6R
0x18
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
EP7R
USB_EP7R
USB_EP7R
0x1C
read-only
n
0x0
0x0
CTR_RX
CTR_RX
15
1
CTR_TX
CTR_TX
7
1
DTOG_RX
DTOG_RX
14
1
DTOG_TX
DTOG_TX
6
1
EA
EA
0
4
EP_KIND
EP_KIND
8
1
EP_TYPE
EP_TYPE
9
2
SETUP
SETUP
11
1
STAT_RX
STAT_RX
12
2
STAT_TX
STAT_TX
4
2
FNR
USB_FNR
USB_FNR
0x48
read-only
n
0x0
0x0
FN
FN
0
11
LCK
LCK
13
1
LSOF
LSOF
11
2
RXDM
RXDM
14
1
RXDP
RXDP
15
1
ISTR
USB_ISTR
USB_ISTR
0x44
read-only
n
0x0
0x0
CTR
CTR
15
1
DIR
DIR
4
1
EP_ID
EP_ID
0
4
ERR
ERR
13
1
ESOF
ESOF
8
1
PMAOVR
PMAOVR
14
1
RESET
RESET
10
1
SOF
SOF
9
1
SUSP
SUSP
11
1
WKUP
WKUP
12
1
WWDG
Window watchdog
WWDG
0x0
0x0
0x400
registers
n
CFR
CFR
Configuration register
0x4
-1
read-write
n
0x0
0x0
EWI
EWI
9
1
W
W
0
7
WDGTB
WDGTB
7
2
CR
CR
Control register
0x0
-1
read-write
n
0x0
0x0
T
T
0
7
WDGA
WDGA
7
1
SR
SR
Status register
0x8
read-only
n
0x0
0x0
EWIF
EWIF
0
1