STMicroelectronics
STM32L4P5RETx
2024.09.21
STM32L4P5RETx
false
ADC
Analog-to-Digital Converter
ADC
0x50040000
0x0
0xB9
registers
n
ADC1_2
ADC1 and ADC2 global interrupt
18
AWD2CR
AWD2CR
Analog Watchdog 2 Configuration Register
0xA0
32
read-write
n
0x0
0xFFFFFFFF
AWD2CH
AWD2CH
0
18
AWD3CR
AWD3CR
Analog Watchdog 3 Configuration Register
0xA4
32
read-write
n
0x0
0xFFFFFFFF
AWD3CH
AWD3CH
0
18
CALFACT
CALFACT
Calibration Factors
0xB4
32
read-write
n
0x0
0xFFFFFFFF
CALFACT_D
CALFACT_D
16
7
CALFACT_S
CALFACT_S
0
7
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0xFFFFFFFF
ALIGN
ALIGN
5
1
AUTDLY
AUTDLY
14
1
AWD1EN
AWD1EN
23
1
AWD1SGL
AWD1SGL
22
1
AWDCH1CH
AWDCH1CH
26
5
CONT
CONT
13
1
DFSDMCFG
DFSDM mode configuration
2
1
DISCEN
DISCEN
16
1
DISCNUM
DISCNUM
17
3
DMACFG
DMACFG
1
1
DMAEN
DMAEN
0
1
EXTEN
EXTEN
10
2
EXTSEL0
EXTSEL0
6
1
EXTSEL1
EXTSEL1
7
1
EXTSEL2
EXTSEL2
8
1
EXTSEL3
EXTSEL3
9
1
JAUTO
JAUTO
25
1
JAWD1EN
JAWD1EN
24
1
JDISCEN
JDISCEN
20
1
JQDIS
Injected Queue disable
31
1
JQM
JQM
21
1
OVRMOD
OVRMOD
12
1
RES
RES
3
2
CFGR2
CFGR2
configuration register
0x10
32
read-write
n
0x0
0xFFFFFFFF
JOVSE
DMACFG
1
1
OVSR
RES
2
3
OVSS
ALIGN
5
4
ROVSE
DMAEN
0
1
ROVSM
Regular Oversampling mode
10
1
TROVS
Triggered Regular Oversampling
9
1
CR
CR
control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ADCAL
ADCAL
31
1
ADCALDIF
ADCALDIF
30
1
ADDIS
ADDIS
1
1
ADEN
ADEN
0
1
ADSTART
ADSTART
2
1
ADSTP
ADSTP
4
1
ADVREGEN
ADVREGEN
28
1
DEEPPWD
DEEPPWD
29
1
JADSTART
JADSTART
3
1
JADSTP
JADSTP
5
1
DIFSEL
DIFSEL
Differential Mode Selection Register 2
0xB0
32
read-write
n
0x0
0xFFFFFFFF
DIFSEL_16_18
Differential mode for channels 18 to 16
16
3
read-only
DIFSEL_1_15
Differential mode for channels 15 to 1
1
15
read-write
DR
DR
regular Data Register
0x40
32
read-only
n
0x0
0xFFFFFFFF
RDATA
Regular Data converted
0
16
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADRDYIE
ADRDYIE
0
1
AWD1IE
AWD1IE
7
1
AWD2IE
AWD2IE
8
1
AWD3IE
AWD3IE
9
1
EOCIE
EOCIE
2
1
EOSIE
EOSIE
3
1
EOSMPIE
EOSMPIE
1
1
JEOCIE
JEOCIE
5
1
JEOSIE
JEOSIE
6
1
JQOVFIE
JQOVFIE
10
1
OVRIE
OVRIE
4
1
ISR
ISR
interrupt and status register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADRDY
ADRDY
0
1
AWD1
AWD1
7
1
AWD2
AWD2
8
1
AWD3
AWD3
9
1
EOC
EOC
2
1
EOS
EOS
3
1
EOSMP
EOSMP
1
1
JEOC
JEOC
5
1
JEOS
JEOS
6
1
JQOVF
JQOVF
10
1
OVR
OVR
4
1
JDR1
JDR1
injected data register 1
0x80
32
read-only
n
0x0
0xFFFFFFFF
JDATA1
JDATA1
0
16
JDR2
JDR2
injected data register 2
0x84
32
read-only
n
0x0
0xFFFFFFFF
JDATA2
JDATA2
0
16
JDR3
JDR3
injected data register 3
0x88
32
read-only
n
0x0
0xFFFFFFFF
JDATA3
JDATA3
0
16
JDR4
JDR4
injected data register 4
0x8C
32
read-only
n
0x0
0xFFFFFFFF
JDATA4
JDATA4
0
16
JSQR
JSQR
injected sequence register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
JEXTEN
JEXTEN
6
2
JEXTSEL
JEXTSEL
2
4
JL
JL
0
2
JSQ1
JSQ1
8
5
JSQ2
JSQ2
14
5
JSQ3
JSQ3
20
5
JSQ4
JSQ4
26
5
OFR1
OFR1
offset register 1
0x60
32
read-write
n
0x0
0xFFFFFFFF
OFFSET1
OFFSET1
0
12
OFFSET1_CH
OFFSET1_CH
26
5
OFFSET1_EN
OFFSET1_EN
31
1
OFR2
OFR2
offset register 2
0x64
32
read-write
n
0x0
0xFFFFFFFF
OFFSET2
OFFSET2
0
12
OFFSET2_CH
OFFSET2_CH
26
5
OFFSET2_EN
OFFSET2_EN
31
1
OFR3
OFR3
offset register 3
0x68
32
read-write
n
0x0
0xFFFFFFFF
OFFSET3
OFFSET3
0
12
OFFSET3_CH
OFFSET3_CH
26
5
OFFSET3_EN
OFFSET3_EN
31
1
OFR4
OFR4
offset register 4
0x6C
32
read-write
n
0x0
0xFFFFFFFF
OFFSET4
OFFSET4
0
12
OFFSET4_CH
OFFSET4_CH
26
5
OFFSET4_EN
OFFSET4_EN
31
1
SMPR1
SMPR1
sample time register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
SMP0
SMP0
0
3
SMP1
SMP1
3
3
SMP2
SMP2
6
3
SMP3
SMP3
9
3
SMP4
SMP4
12
3
SMP5
SMP5
15
3
SMP6
SMP6
18
3
SMP7
SMP7
21
3
SMP8
SMP8
24
3
SMP9
SMP9
27
3
SMPPLUS
Addition of one clock cycle to the sampling time
31
1
SMPR2
SMPR2
sample time register 2
0x18
32
read-write
n
0x0
0xFFFFFFFF
SMP10
SMP10
0
3
SMP11
SMP11
3
3
SMP12
SMP12
6
3
SMP13
SMP13
9
3
SMP14
SMP14
12
3
SMP15
SMP15
15
3
SMP16
SMP16
18
3
SMP17
SMP17
21
3
SMP18
SMP18
24
3
SQR1
SQR1
regular sequence register 1
0x30
32
read-write
n
0x0
0xFFFFFFFF
L
Regular channel sequence length
0
4
SQ1
SQ1
6
5
SQ2
SQ2
12
5
SQ3
SQ3
18
5
SQ4
SQ4
24
5
SQR2
SQR2
regular sequence register 2
0x34
32
read-write
n
0x0
0xFFFFFFFF
SQ5
SQ5
0
5
SQ6
SQ6
6
5
SQ7
SQ7
12
5
SQ8
SQ8
18
5
SQ9
SQ9
24
5
SQR3
SQR3
regular sequence register 3
0x38
32
read-write
n
0x0
0xFFFFFFFF
SQ10
SQ10
0
5
SQ11
SQ11
6
5
SQ12
SQ12
12
5
SQ13
SQ13
18
5
SQ14
SQ14
24
5
SQR4
SQR4
regular sequence register 4
0x3C
32
read-write
n
0x0
0xFFFFFFFF
SQ15
SQ15
0
5
SQ16
SQ16
6
5
TR1
TR1
watchdog threshold register 1
0x20
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT1
HT1
16
12
LT1
LT1
0
12
TR2
TR2
watchdog threshold register
0x24
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT2
HT2
16
8
LT2
LT2
0
8
TR3
TR3
watchdog threshold register 3
0x28
32
read-write
n
0xFFF0000
0xFFFFFFFF
HT3
HT3
16
8
LT3
LT3
0
8
ADC_Common
Analog-to-Digital Converter
ADC
0x50040300
0x0
0x11
registers
n
CCR
CCR
ADC common control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CH17SEL
CH17 selection
23
1
CH18SEL
CH18 selection
24
1
CKMODE
ADC clock mode
16
2
DELAY
Delay between 2 sampling phases
8
4
DMACFG
DMA configuration (for multi-ADC mode)
13
1
DUAL
Dual ADC mode selection
0
5
MDMA
Direct memory access mode for multi ADC mode
14
2
PRESC
ADC prescaler
18
4
VREFEN
VREFINT enable
22
1
CDR
CDR
ADC common regular data register for dual and triple modes
0xC
32
read-only
n
0x0
0xFFFFFFFF
RDATA_MST
Regular data of the master ADC
0
16
RDATA_SLV
Regular data of the slave ADC
16
16
CSR
CSR
ADC Common status register
0x0
32
read-only
n
0x0
0xFFFFFFFF
ADDRDY_MST
ADDRDY_MST
0
1
ADRDY_SLV
ADRDY_SLV
16
1
AWD1_MST
AWD1_MST
7
1
AWD1_SLV
Analog watchdog 1 flag of the slave ADC
23
1
AWD2_MST
AWD2_MST
8
1
AWD2_SLV
Analog watchdog 2 flag of the slave ADC
24
1
AWD3_MST
AWD3_MST
9
1
AWD3_SLV
Analog watchdog 3 flag of the slave ADC
25
1
EOC_MST
EOC_MST
2
1
EOC_SLV
End of regular conversion of the slave ADC
18
1
EOSMP_MST
EOSMP_MST
1
1
EOSMP_SLV
EOSMP_SLV
17
1
EOS_MST
EOS_MST
3
1
EOS_SLV
End of regular sequence flag of the slave ADC
19
1
JEOC_MST
JEOC_MST
5
1
JEOC_SLV
End of injected conversion flag of the slave ADC
21
1
JEOS_MST
JEOS_MST
6
1
JEOS_SLV
End of injected sequence flag of the slave ADC
22
1
JQOVF_MST
JQOVF_MST
10
1
JQOVF_SLV
Injected Context Queue Overflow flag of the slave ADC
26
1
OVR_MST
OVR_MST
4
1
OVR_SLV
Overrun flag of the slave ADC
20
1
AES
Advanced encryption standard hardware accelerator
AES
0x50060000
0x0
0x400
registers
n
AES
AES global interrupt
79
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CCFC
Computation Complete Flag Clear
7
1
CCFIE
CCF flag interrupt enable
9
1
CHMOD
AES chaining mode
5
2
DATATYPE
Data type selection (for data in and data out to/from the cryptographic block)
1
2
DMAINEN
Enable DMA management of data input phase
11
1
DMAOUTEN
Enable DMA management of data output phase
12
1
EN
AES enable
0
1
ERRC
Error clear
8
1
ERRIE
Error interrupt enable
10
1
MODE
AES operating mode
3
2
DINR
DINR
data input register
0x8
32
read-write
n
0x0
0xFFFFFFFF
AES_DINR
Data Input Register
0
32
DOUTR
DOUTR
data output register
0xC
32
read-only
n
0x0
0xFFFFFFFF
AES_DOUTR
Data output register
0
32
IVR0
IVR0
initialization vector register 0
0x20
32
read-write
n
0x0
0xFFFFFFFF
AES_IVR0
initialization vector register (LSB IVR [31:0])
0
32
IVR1
IVR1
initialization vector register 1
0x24
32
read-write
n
0x0
0xFFFFFFFF
AES_IVR1
Initialization Vector Register (IVR [63:32])
0
32
IVR2
IVR2
initialization vector register 2
0x28
32
read-write
n
0x0
0xFFFFFFFF
AES_IVR2
Initialization Vector Register (IVR [95:64])
0
32
IVR3
IVR3
initialization vector register 3
0x2C
32
read-write
n
0x0
0xFFFFFFFF
AES_IVR3
Initialization Vector Register (MSB IVR [127:96])
0
32
KEYR0
KEYR0
key register 0
0x10
32
read-write
n
0x0
0xFFFFFFFF
AES_KEYR0
Data Output Register (LSB key [31:0])
0
32
KEYR1
KEYR1
key register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
AES_KEYR1
AES key register (key [63:32])
0
32
KEYR2
KEYR2
key register 2
0x18
32
read-write
n
0x0
0xFFFFFFFF
AES_KEYR2
AES key register (key [95:64])
0
32
KEYR3
KEYR3
key register 3
0x1C
32
read-write
n
0x0
0xFFFFFFFF
AES_KEYR3
AES key register (MSB key [127:96])
0
32
SR
SR
status register
0x4
32
read-only
n
0x0
0xFFFFFFFF
CCF
Computation complete flag
0
1
RDERR
Read error flag
1
1
WRERR
Write error flag
2
1
CAN1
Controller area network
CAN
0x40006400
0x0
0x400
registers
n
CAN1_TX
CAN1 TX interrupts
19
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_SCE
CAN1 SCE interrupt
22
BTR
BTR
bit timing register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
BRP
BRP
0
10
LBKM
LBKM
30
1
SILM
SILM
31
1
SJW
SJW
24
2
TS1
TS1
16
4
TS2
TS2
20
3
ESR
ESR
interrupt enable register
0x18
32
read-write
n
0x0
0xFFFFFFFF
BOFF
BOFF
2
1
read-only
EPVF
EPVF
1
1
read-only
EWGF
EWGF
0
1
read-only
LEC
LEC
4
3
read-write
REC
REC
24
8
read-only
TEC
TEC
16
8
read-only
F0R1
F0R1
Filter bank 0 register 1
0x240
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F0R2
F0R2
Filter bank 0 register 2
0x244
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R1
F10R1
Filter bank 10 register 1
0x290
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F10R2
F10R2
Filter bank 10 register 2
0x294
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R1
F11R1
Filter bank 11 register 1
0x298
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F11R2
F11R2
Filter bank 11 register 2
0x29C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R1
F12R1
Filter bank 4 register 1
0x2A0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F12R2
F12R2
Filter bank 12 register 2
0x2A4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R1
F13R1
Filter bank 13 register 1
0x2A8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F13R2
F13R2
Filter bank 13 register 2
0x2AC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R1
F14R1
Filter bank 14 register 1
0x2B0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F14R2
F14R2
Filter bank 14 register 2
0x2B4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R1
F15R1
Filter bank 15 register 1
0x2B8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F15R2
F15R2
Filter bank 15 register 2
0x2BC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R1
F16R1
Filter bank 16 register 1
0x2C0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F16R2
F16R2
Filter bank 16 register 2
0x2C4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R1
F17R1
Filter bank 17 register 1
0x2C8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F17R2
F17R2
Filter bank 17 register 2
0x2CC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R1
F18R1
Filter bank 18 register 1
0x2D0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F18R2
F18R2
Filter bank 18 register 2
0x2D4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R1
F19R1
Filter bank 19 register 1
0x2D8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F19R2
F19R2
Filter bank 19 register 2
0x2DC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R1
F1R1
Filter bank 1 register 1
0x248
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F1R2
F1R2
Filter bank 1 register 2
0x24C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R1
F20R1
Filter bank 20 register 1
0x2E0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F20R2
F20R2
Filter bank 20 register 2
0x2E4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R1
F21R1
Filter bank 21 register 1
0x2E8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F21R2
F21R2
Filter bank 21 register 2
0x2EC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R1
F22R1
Filter bank 22 register 1
0x2F0
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F22R2
F22R2
Filter bank 22 register 2
0x2F4
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R1
F23R1
Filter bank 23 register 1
0x2F8
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F23R2
F23R2
Filter bank 23 register 2
0x2FC
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R1
F24R1
Filter bank 24 register 1
0x300
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F24R2
F24R2
Filter bank 24 register 2
0x304
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R1
F25R1
Filter bank 25 register 1
0x308
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F25R2
F25R2
Filter bank 25 register 2
0x30C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R1
F26R1
Filter bank 26 register 1
0x310
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F26R2
F26R2
Filter bank 26 register 2
0x314
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R1
F27R1
Filter bank 27 register 1
0x318
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F27R2
F27R2
Filter bank 27 register 2
0x31C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R1
F2R1
Filter bank 2 register 1
0x250
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F2R2
F2R2
Filter bank 2 register 2
0x254
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R1
F3R1
Filter bank 3 register 1
0x258
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F3R2
F3R2
Filter bank 3 register 2
0x25C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R1
F4R1
Filter bank 4 register 1
0x260
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F4R2
F4R2
Filter bank 4 register 2
0x264
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R1
F5R1
Filter bank 5 register 1
0x268
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F5R2
F5R2
Filter bank 5 register 2
0x26C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R1
F6R1
Filter bank 6 register 1
0x270
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F6R2
F6R2
Filter bank 6 register 2
0x274
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R1
F7R1
Filter bank 7 register 1
0x278
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F7R2
F7R2
Filter bank 7 register 2
0x27C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R1
F8R1
Filter bank 8 register 1
0x280
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F8R2
F8R2
Filter bank 8 register 2
0x284
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R1
F9R1
Filter bank 9 register 1
0x288
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
F9R2
F9R2
Filter bank 9 register 2
0x28C
32
read-write
n
0x0
0xFFFFFFFF
FB0
Filter bits
0
1
FB1
Filter bits
1
1
FB10
Filter bits
10
1
FB11
Filter bits
11
1
FB12
Filter bits
12
1
FB13
Filter bits
13
1
FB14
Filter bits
14
1
FB15
Filter bits
15
1
FB16
Filter bits
16
1
FB17
Filter bits
17
1
FB18
Filter bits
18
1
FB19
Filter bits
19
1
FB2
Filter bits
2
1
FB20
Filter bits
20
1
FB21
Filter bits
21
1
FB22
Filter bits
22
1
FB23
Filter bits
23
1
FB24
Filter bits
24
1
FB25
Filter bits
25
1
FB26
Filter bits
26
1
FB27
Filter bits
27
1
FB28
Filter bits
28
1
FB29
Filter bits
29
1
FB3
Filter bits
3
1
FB30
Filter bits
30
1
FB31
Filter bits
31
1
FB4
Filter bits
4
1
FB5
Filter bits
5
1
FB6
Filter bits
6
1
FB7
Filter bits
7
1
FB8
Filter bits
8
1
FB9
Filter bits
9
1
FA1R
FA1R
filter activation register
0x21C
32
read-write
n
0x0
0xFFFFFFFF
FACT0
Filter active
0
1
FACT1
Filter active
1
1
FACT10
Filter active
10
1
FACT11
Filter active
11
1
FACT12
Filter active
12
1
FACT13
Filter active
13
1
FACT14
Filter active
14
1
FACT15
Filter active
15
1
FACT16
Filter active
16
1
FACT17
Filter active
17
1
FACT18
Filter active
18
1
FACT19
Filter active
19
1
FACT2
Filter active
2
1
FACT20
Filter active
20
1
FACT21
Filter active
21
1
FACT22
Filter active
22
1
FACT23
Filter active
23
1
FACT24
Filter active
24
1
FACT25
Filter active
25
1
FACT26
Filter active
26
1
FACT27
Filter active
27
1
FACT3
Filter active
3
1
FACT4
Filter active
4
1
FACT5
Filter active
5
1
FACT6
Filter active
6
1
FACT7
Filter active
7
1
FACT8
Filter active
8
1
FACT9
Filter active
9
1
FFA1R
FFA1R
filter FIFO assignment register
0x214
32
read-write
n
0x0
0xFFFFFFFF
FFA0
Filter FIFO assignment for filter 0
0
1
FFA1
Filter FIFO assignment for filter 1
1
1
FFA10
Filter FIFO assignment for filter 10
10
1
FFA11
Filter FIFO assignment for filter 11
11
1
FFA12
Filter FIFO assignment for filter 12
12
1
FFA13
Filter FIFO assignment for filter 13
13
1
FFA14
Filter FIFO assignment for filter
14
1
FFA15
Filter FIFO assignment for filter
15
1
FFA16
Filter FIFO assignment for filter
16
1
FFA17
Filter FIFO assignment for filter
17
1
FFA18
Filter FIFO assignment for filter
18
1
FFA19
Filter FIFO assignment for filter
19
1
FFA2
Filter FIFO assignment for filter 2
2
1
FFA20
Filter FIFO assignment for filter
20
1
FFA21
Filter FIFO assignment for filter
21
1
FFA22
Filter FIFO assignment for filter
22
1
FFA23
Filter FIFO assignment for filter
23
1
FFA24
Filter FIFO assignment for filter
24
1
FFA25
Filter FIFO assignment for filter
25
1
FFA26
Filter FIFO assignment for filter
26
1
FFA27
Filter FIFO assignment for filter
27
1
FFA3
Filter FIFO assignment for filter 3
3
1
FFA4
Filter FIFO assignment for filter 4
4
1
FFA5
Filter FIFO assignment for filter 5
5
1
FFA6
Filter FIFO assignment for filter 6
6
1
FFA7
Filter FIFO assignment for filter 7
7
1
FFA8
Filter FIFO assignment for filter 8
8
1
FFA9
Filter FIFO assignment for filter 9
9
1
FM1R
FM1R
filter mode register
0x204
32
read-write
n
0x0
0xFFFFFFFF
FBM0
Filter mode
0
1
FBM1
Filter mode
1
1
FBM10
Filter mode
10
1
FBM11
Filter mode
11
1
FBM12
Filter mode
12
1
FBM13
Filter mode
13
1
FBM14
Filter mode
14
1
FBM15
Filter mode
15
1
FBM16
Filter mode
16
1
FBM17
Filter mode
17
1
FBM18
Filter mode
18
1
FBM19
Filter mode
19
1
FBM2
Filter mode
2
1
FBM20
Filter mode
20
1
FBM21
Filter mode
21
1
FBM22
Filter mode
22
1
FBM23
Filter mode
23
1
FBM24
Filter mode
24
1
FBM25
Filter mode
25
1
FBM26
Filter mode
26
1
FBM27
Filter mode
27
1
FBM3
Filter mode
3
1
FBM4
Filter mode
4
1
FBM5
Filter mode
5
1
FBM6
Filter mode
6
1
FBM7
Filter mode
7
1
FBM8
Filter mode
8
1
FBM9
Filter mode
9
1
FMR
FMR
filter master register
0x200
32
read-write
n
0x2A1C0E01
0xFFFFFFFF
CANSB
CAN start bank
8
6
FINIT
Filter initialization mode
0
1
FS1R
FS1R
filter scale register
0x20C
32
read-write
n
0x0
0xFFFFFFFF
FSC0
Filter scale configuration
0
1
FSC1
Filter scale configuration
1
1
FSC10
Filter scale configuration
10
1
FSC11
Filter scale configuration
11
1
FSC12
Filter scale configuration
12
1
FSC13
Filter scale configuration
13
1
FSC14
Filter scale configuration
14
1
FSC15
Filter scale configuration
15
1
FSC16
Filter scale configuration
16
1
FSC17
Filter scale configuration
17
1
FSC18
Filter scale configuration
18
1
FSC19
Filter scale configuration
19
1
FSC2
Filter scale configuration
2
1
FSC20
Filter scale configuration
20
1
FSC21
Filter scale configuration
21
1
FSC22
Filter scale configuration
22
1
FSC23
Filter scale configuration
23
1
FSC24
Filter scale configuration
24
1
FSC25
Filter scale configuration
25
1
FSC26
Filter scale configuration
26
1
FSC27
Filter scale configuration
27
1
FSC3
Filter scale configuration
3
1
FSC4
Filter scale configuration
4
1
FSC5
Filter scale configuration
5
1
FSC6
Filter scale configuration
6
1
FSC7
Filter scale configuration
7
1
FSC8
Filter scale configuration
8
1
FSC9
Filter scale configuration
9
1
IER
IER
interrupt enable register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BOFIE
BOFIE
10
1
EPVIE
EPVIE
9
1
ERRIE
ERRIE
15
1
EWGIE
EWGIE
8
1
FFIE0
FFIE0
2
1
FFIE1
FFIE1
5
1
FMPIE0
FMPIE0
1
1
FMPIE1
FMPIE1
4
1
FOVIE0
FOVIE0
3
1
FOVIE1
FOVIE1
6
1
LECIE
LECIE
11
1
SLKIE
SLKIE
17
1
TMEIE
TMEIE
0
1
WKUIE
WKUIE
16
1
MCR
MCR
master control register
0x0
32
read-write
n
0x10002
0xFFFFFFFF
ABOM
ABOM
6
1
AWUM
AWUM
5
1
DBF
DBF
16
1
INRQ
INRQ
0
1
NART
NART
4
1
RESET
RESET
15
1
RFLM
RFLM
3
1
SLEEP
SLEEP
1
1
TTCM
TTCM
7
1
TXFP
TXFP
2
1
MSR
MSR
master status register
0x4
32
read-write
n
0xC02
0xFFFFFFFF
ERRI
ERRI
2
1
read-write
INAK
INAK
0
1
read-only
RX
RX
11
1
read-only
RXM
RXM
9
1
read-only
SAMP
SAMP
10
1
read-only
SLAK
SLAK
1
1
read-only
SLAKI
SLAKI
4
1
read-write
TXM
TXM
8
1
read-only
WKUI
WKUI
3
1
read-write
RDH0R
RDH0R
receive FIFO mailbox data high register
0x1BC
32
read-only
n
0x0
0xFFFFFFFF
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDH1R
RDH1R
mailbox data high register
0x1CC
32
read-only
n
0x0
0xFFFFFFFF
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
RDL0R
RDL0R
mailbox data high register
0x1B8
32
read-only
n
0x0
0xFFFFFFFF
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDL1R
RDL1R
mailbox data high register
0x1C8
32
read-only
n
0x0
0xFFFFFFFF
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
RDT0R
RDT0R
mailbox data high register
0x1B4
32
read-only
n
0x0
0xFFFFFFFF
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RDT1R
RDT1R
mailbox data high register
0x1C4
32
read-only
n
0x0
0xFFFFFFFF
DLC
DLC
0
4
FMI
FMI
8
8
TIME
TIME
16
16
RF0R
RF0R
receive FIFO 0 register
0xC
32
read-write
n
0x0
0xFFFFFFFF
FMP0
FMP0
0
2
read-only
FOVR0
FOVR0
4
1
read-write
FULL0
FULL0
3
1
read-write
RFOM0
RFOM0
5
1
read-write
RF1R
RF1R
receive FIFO 1 register
0x10
32
read-write
n
0x0
0xFFFFFFFF
FMP1
FMP1
0
2
read-only
FOVR1
FOVR1
4
1
read-write
FULL1
FULL1
3
1
read-write
RFOM1
RFOM1
5
1
read-write
RI0R
RI0R
receive FIFO mailbox identifier register
0x1B0
32
read-only
n
0x0
0xFFFFFFFF
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
RI1R
RI1R
mailbox data high register
0x1C0
32
read-only
n
0x0
0xFFFFFFFF
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TDH0R
TDH0R
mailbox data high register
0x18C
32
read-write
n
0x0
0xFFFFFFFF
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH1R
TDH1R
mailbox data high register
0x19C
32
read-write
n
0x0
0xFFFFFFFF
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDH2R
TDH2R
mailbox data high register
0x1AC
32
read-write
n
0x0
0xFFFFFFFF
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TDL0R
TDL0R
mailbox data low register
0x188
32
read-write
n
0x0
0xFFFFFFFF
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL1R
TDL1R
mailbox data low register
0x198
32
read-write
n
0x0
0xFFFFFFFF
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDL2R
TDL2R
mailbox data low register
0x1A8
32
read-write
n
0x0
0xFFFFFFFF
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TDT0R
TDT0R
mailbox data length control and time stamp register
0x184
32
read-write
n
0x0
0xFFFFFFFF
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT1R
TDT1R
mailbox data length control and time stamp register
0x194
32
read-write
n
0x0
0xFFFFFFFF
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TDT2R
TDT2R
mailbox data length control and time stamp register
0x1A4
32
read-write
n
0x0
0xFFFFFFFF
DLC
DLC
0
4
TGT
TGT
8
1
TIME
TIME
16
16
TI0R
TI0R
TX mailbox identifier register
0x180
32
read-write
n
0x0
0xFFFFFFFF
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI1R
TI1R
mailbox identifier register
0x190
32
read-write
n
0x0
0xFFFFFFFF
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TI2R
TI2R
mailbox identifier register
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
EXID
EXID
3
18
IDE
IDE
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TSR
TSR
transmit status register
0x8
32
read-write
n
0x1C000000
0xFFFFFFFF
ABRQ0
ABRQ0
7
1
read-write
ABRQ1
ABRQ1
15
1
read-write
ABRQ2
ABRQ2
23
1
read-write
ALST0
ALST0
2
1
read-write
ALST1
ALST1
10
1
read-write
ALST2
ALST2
18
1
read-write
CODE
CODE
24
2
read-only
LOW0
Lowest priority flag for mailbox 0
29
1
read-only
LOW1
Lowest priority flag for mailbox 1
30
1
read-only
LOW2
Lowest priority flag for mailbox 2
31
1
read-only
RQCP0
RQCP0
0
1
read-write
RQCP1
RQCP1
8
1
read-write
RQCP2
RQCP2
16
1
read-write
TERR0
TERR0
3
1
read-write
TERR1
TERR1
11
1
read-write
TERR2
TERR2
19
1
read-write
TME0
Lowest priority flag for mailbox 0
26
1
read-only
TME1
Lowest priority flag for mailbox 1
27
1
read-only
TME2
Lowest priority flag for mailbox 2
28
1
read-only
TXOK0
TXOK0
1
1
read-write
TXOK1
TXOK1
9
1
read-write
TXOK2
TXOK2
17
1
read-write
COMP
Comparator
COMP
0x40010200
0x0
0x200
registers
n
COMP
COMP1 and COMP2 interrupts
64
COMP1_CSR
COMP1_CSR
Comparator 1 control and status register
0x0
32
read-write
n
0x0
0xFFFFFFFF
COMP1_BLANKING
Comparator 1 blanking source selection bits
18
3
read-write
COMP1_BRGEN
Scaler bridge enable
22
1
read-write
COMP1_EN
Comparator 1 enable bit
0
1
read-write
COMP1_HYST
Comparator 1 hysteresis selection bits
16
2
read-write
COMP1_INMSEL
Comparator 1 Input Minus connection configuration bit
4
3
read-write
COMP1_INPSEL
Comparator1 input plus selection bit
7
1
read-write
COMP1_LOCK
COMP1_CSR register lock bit
31
1
write-only
COMP1_POLARITY
Comparator 1 polarity selection bit
15
1
read-write
COMP1_PWRMODE
Power Mode of the comparator 1
2
2
read-write
COMP1_SCALEN
Voltage scaler enable bit
23
1
read-write
COMP1_VALUE
Comparator 1 output status bit
30
1
read-only
COMP2_CSR
COMP2_CSR
Comparator 2 control and status register
0x4
32
read-write
n
0x0
0xFFFFFFFF
COMP2_BLANKING
Comparator 2 blanking source selection bits
18
3
read-write
COMP2_BRGEN
Scaler bridge enable
22
1
read-write
COMP2_EN
Comparator 2 enable bit
0
1
read-write
COMP2_HYST
Comparator 2 hysteresis selection bits
16
2
read-write
COMP2_INMSEL
Comparator 2 Input Minus connection configuration bit
4
3
read-write
COMP2_INPSEL
Comparator 2 Input Plus connection configuration bit
7
1
read-write
COMP2_LOCK
COMP2_CSR register lock bit
31
1
write-only
COMP2_POLARITY
Comparator 2 polarity selection bit
15
1
read-write
COMP2_PWRMODE
Power Mode of the comparator 2
2
2
read-write
COMP2_SCALEN
Voltage scaler enable bit
23
1
read-write
COMP2_VALUE
Comparator 2 output status bit
30
1
read-only
COMP2_WINMODE
Windows mode selection bit
9
1
read-write
CRC
Cyclic redundancy check calculation unit
CRC
0x40023000
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
POLYSIZE
Polynomial size
3
2
read-write
RESET
RESET bit
0
1
write-only
REV_IN
Reverse input data
5
2
read-write
REV_OUT
Reverse output data
7
1
read-write
DR
DR
Data register
0x0
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
DR
Data register bits
0
32
IDR
IDR
Independent data register
0x4
32
read-write
n
0x0
0xFFFFFFFF
IDR
General-purpose 8-bit data register bits
0
8
INIT
INIT
Initial CRC value
0x10
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
CRC_INIT
Programmable initial CRC value
0
32
POL
POL
polynomial
0x14
32
read-write
n
0x4C11DB7
0xFFFFFFFF
Polynomialcoefficients
Programmable polynomial
0
32
CRS
Clock recovery system
CRS
0x40006000
0x0
0x400
registers
n
CRS
CRS global interrupt
82
CFGR
CFGR
configuration register
0x4
32
read-write
n
0x2022BB7F
0xFFFFFFFF
FELIM
Frequency error limit
16
8
RELOAD
Counter reload value
0
16
SYNCDIV
SYNC divider
24
3
SYNCPOL
SYNC polarity selection
31
1
SYNCSRC
SYNC signal source selection
28
2
CR
CR
control register
0x0
32
read-write
n
0x2000
0xFFFFFFFF
AUTOTRIMEN
Automatic trimming enable
6
1
CEN
Frequency error counter enable
5
1
ERRIE
Synchronization or trimming error interrupt enable
2
1
ESYNCIE
Expected SYNC interrupt enable
3
1
SWSYNC
Generate software SYNC event
7
1
SYNCOKIE
SYNC event OK interrupt enable
0
1
SYNCWARNIE
SYNC warning interrupt enable
1
1
TRIM
HSI48 oscillator smooth trimming
8
6
ICR
ICR
interrupt flag clear register
0xC
32
read-write
n
0x0
0xFFFFFFFF
ERRC
Error clear flag
2
1
ESYNCC
Expected SYNC clear flag
3
1
SYNCOKC
SYNC event OK clear flag
0
1
SYNCWARNC
SYNC warning clear flag
1
1
ISR
ISR
interrupt and status register
0x8
32
read-only
n
0x0
0xFFFFFFFF
ERRF
Error flag
2
1
ESYNCF
Expected SYNC flag
3
1
FECAP
Frequency error capture
16
16
FEDIR
Frequency error direction
15
1
SYNCERR
SYNC error
8
1
SYNCMISS
SYNC missed
9
1
SYNCOKF
SYNC event OK flag
0
1
SYNCWARNF
SYNC warning flag
1
1
TRIMOVF
Trimming overflow or underflow
10
1
DAC
Digital-to-analog converter
DAC
0x40007400
0x0
0x400
registers
n
CCR
CCR
calibration control register
0x38
32
read-write
n
0x0
0xFFFFFFFF
OTRIM1
DAC Channel 1 offset trimming value
0
5
OTRIM2
DAC Channel 2 offset trimming value
16
5
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CEN1
DAC Channel 1 calibration enable
14
1
CEN2
DAC Channel 2 calibration enable
30
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAEN2
DAC channel2 DMA enable
28
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
DMAUDRIE2
DAC channel2 DMA underrun interrupt enable
29
1
EN1
DAC channel1 enable
0
1
EN2
DAC channel2 enable
16
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
MAMP2
DAC channel2 mask/amplitude selector
24
4
TEN1
DAC channel1 trigger enable
2
1
TEN2
DAC channel2 trigger enable
18
1
TSEL1
DAC channel1 trigger selection
3
3
TSEL2
DAC channel2 trigger selection
19
3
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
WAVE2
DAC channel2 noise/triangle wave generation enable
22
2
DHR12L1
DHR12L1
channel1 12-bit left-aligned data holding register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12L2
DHR12L2
channel2 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
DUAL DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DACC2DHR
DAC channel2 12-bit left-aligned data
20
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12R2
DHR12R2
channel2 12-bit right aligned data holding register
0x14
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DACC2DHR
DAC channel2 12-bit right-aligned data
16
12
DHR8R1
DHR8R1
channel1 8-bit right-aligned data holding register
0x10
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8R2
DHR8R2
channel2 8-bit right-aligned data holding register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
DACC2DHR
DAC channel2 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
DUAL DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0xFFFFFFFF
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DACC2DHR
DAC channel2 8-bit right-aligned data
8
8
DOR1
DOR1
channel1 data output register
0x2C
32
read-only
n
0x0
0xFFFFFFFF
DACC1DOR
DAC channel1 data output
0
12
DOR2
DOR2
channel2 data output register
0x30
32
read-only
n
0x0
0xFFFFFFFF
DACC2DOR
DAC channel2 data output
0
12
MCR
MCR
mode control register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
MODE1
DAC Channel 1 mode
0
3
MODE2
DAC Channel 2 mode
16
3
SHHR
SHHR
Sample and Hold hold time register
0x48
32
read-write
n
0x10001
0xFFFFFFFF
THOLD1
DAC Channel 1 hold Time
0
10
THOLD2
DAC Channel 2 hold time
16
10
SHRR
SHRR
Sample and Hold refresh time register
0x4C
32
read-write
n
0x1
0xFFFFFFFF
TREFRESH1
DAC Channel 1 refresh Time
0
8
TREFRESH2
DAC Channel 2 refresh Time
16
8
SHSR1
SHSR1
Sample and Hold sample time register 1
0x40
32
read-write
n
0x0
0xFFFFFFFF
TSAMPLE1
DAC Channel 1 sample Time
0
10
SHSR2
SHSR2
Sample and Hold sample time register 2
0x44
32
read-write
n
0x0
0xFFFFFFFF
TSAMPLE2
DAC Channel 2 sample Time
0
10
SR
SR
status register
0x34
32
read-write
n
0x0
0xFFFFFFFF
BWST1
DAC Channel 1 busy writing sample time flag
15
1
read-only
BWST2
DAC Channel 2 busy writing sample time flag
31
1
read-only
CAL_FLAG1
DAC Channel 1 calibration offset status
14
1
read-only
CAL_FLAG2
DAC Channel 2 calibration offset status
30
1
read-only
DMAUDR1
DAC channel1 DMA underrun flag
13
1
read-write
DMAUDR2
DAC channel2 DMA underrun flag
29
1
read-write
SWTRIGR
SWTRIGR
software trigger register
0x4
32
write-only
n
0x0
0xFFFFFFFF
SWTRIG1
DAC channel1 software trigger
0
1
SWTRIG2
DAC channel2 software trigger
1
1
DBGMCU
Debug support
DBGMCU
0xE0042000
0x0
0x400
registers
n
APB1_FZR1
APB1_FZR1
APB Low Freeze Register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
DBG_CAN_STOP
bxCAN stopped when core is halted
25
1
DBG_I2C1_STOP
I2C1 SMBUS timeout mode stopped when core is halted
21
1
DBG_I2C2_STOP
I2C2 SMBUS timeout mode stopped when core is halted
22
1
DBG_I2C3_STOP
I2C3 SMBUS timeout counter stopped when core is halted
23
1
DBG_IWDG_STOP
Debug Independent Wachdog stopped when Core is halted
12
1
DBG_LPTIMER_STOP
LPTIM1 counter stopped when core is halted
31
1
DBG_RTC_STOP
Debug RTC stopped when Core is halted
10
1
DBG_TIM3_STOP
TIM3 counter stopped when core is halted
1
1
DBG_TIM4_STOP
TIM4 counter stopped when core is halted
2
1
DBG_TIM5_STOP
TIM5 counter stopped when core is halted
3
1
DBG_TIM7_STOP
TIM7 counter stopped when core is halted
5
1
DBG_TIMER2_STOP
Debug Timer 2 stopped when Core is halted
0
1
DBG_TIMER6_STOP
Debug Timer 6 stopped when Core is halted
4
1
DBG_WWDG_STOP
Debug Window Wachdog stopped when Core is halted
11
1
APB1_FZR2
APB1_FZR2
APB Low Freeze Register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
DBG_LPTIM2_STOP
LPTIM2 counter stopped when core is halted
5
1
APB2_FZR
APB2_FZR
APB High Freeze Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
DBG_TIM15_STOP
TIM15 counter stopped when core is halted
16
1
DBG_TIM16_STOP
TIM16 counter stopped when core is halted
17
1
DBG_TIM17_STOP
TIM17 counter stopped when core is halted
18
1
DBG_TIM1_STOP
TIM1 counter stopped when core is halted
11
1
DBG_TIM8_STOP
TIM8 counter stopped when core is halted
13
1
CR
CR
Debug MCU Configuration Register
0x4
32
read-write
n
0x0
0xFFFFFFFF
DBG_SLEEP
Debug Sleep Mode
0
1
DBG_STANDBY
Debug Standby Mode
2
1
DBG_STOP
Debug Stop Mode
1
1
TRACE_IOEN
Trace pin assignment control
5
1
TRACE_MODE
Trace pin assignment control
6
2
IDCODE
IDCODE
MCU Device ID Code Register
0x0
32
read-only
n
0x0
0xFFFFFFFF
DEV_ID
Device Identifier
0
16
REV_ID
Revision Identifier
16
16
DCMI
Digital camera interface
DCMI
0x50050000
0x0
0x400
registers
n
DCMI
DCMI global interrupt
85
CR
CR
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
BSM
Byte Select mode
16
2
CAPTURE
Capture enable
0
1
CM
Capture mode
1
1
CROP
Crop feature
2
1
EDM
Extended data mode
10
2
ENABLE
DCMI enable
14
1
ESS
Embedded synchronization select
4
1
FCRC
Frame capture rate control
8
2
HSPOL
Horizontal synchronization polarity
6
1
JPEG
JPEG format
3
1
LSM
Line Select mode
19
1
OEBS
Odd/Even Byte Select (Byte Select Start)
18
1
OELS
Odd/Even Line Select (Line Select Start)
20
1
PCKPOL
Pixel clock polarity
5
1
VSPOL
Vertical synchronization polarity
7
1
CWSIZE
CWSIZE
crop window size
0x24
32
read-write
n
0x0
0xFFFFFFFF
CAPCNT
Capture count
0
14
VLINE
Vertical line count
16
14
CWSTRT
CWSTRT
crop window start
0x20
32
read-write
n
0x0
0xFFFFFFFF
HOFFCNT
Horizontal offset count
0
14
VST
Vertical start line count
16
13
DR
DR
data register
0x28
32
read-only
n
0x0
0xFFFFFFFF
Byte0
Data byte 0
0
8
Byte1
Data byte 1
8
8
Byte2
Data byte 2
16
8
Byte3
Data byte 3
24
8
ESCR
ESCR
embedded synchronization code register
0x18
32
read-write
n
0x0
0xFFFFFFFF
FEC
Frame end delimiter code
24
8
FSC
Frame start delimiter code
0
8
LEC
Line end delimiter code
16
8
LSC
Line start delimiter code
8
8
ESUR
ESUR
embedded synchronization unmask register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
FEU
Frame end delimiter unmask
24
8
FSU
Frame start delimiter unmask
0
8
LEU
Line end delimiter unmask
16
8
LSU
Line start delimiter unmask
8
8
ICR
ICR
interrupt clear register
0x14
32
write-only
n
0x0
0xFFFFFFFF
ERR_ISC
Synchronization error interrupt status clear
2
1
FRAME_ISC
Capture complete interrupt status clear
0
1
LINE_ISC
line interrupt status clear
4
1
OVR_ISC
Overrun interrupt status clear
1
1
VSYNC_ISC
Vertical synch interrupt status clear
3
1
IER
IER
interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
ERR_IE
Synchronization error interrupt enable
2
1
FRAME_IE
Capture complete interrupt enable
0
1
LINE_IE
Line interrupt enable
4
1
OVR_IE
Overrun interrupt enable
1
1
VSYNC_IE
VSYNC interrupt enable
3
1
MIS
MIS
masked interrupt status register
0x10
32
read-only
n
0x0
0xFFFFFFFF
ERR_MIS
Synchronization error masked interrupt status
2
1
FRAME_MIS
Capture complete masked interrupt status
0
1
LINE_MIS
Line masked interrupt status
4
1
OVR_MIS
Overrun masked interrupt status
1
1
VSYNC_MIS
VSYNC masked interrupt status
3
1
RIS
RIS
raw interrupt status register
0x8
32
read-only
n
0x0
0xFFFFFFFF
ERR_RIS
Synchronization error raw interrupt status
2
1
FRAME_RIS
Capture complete raw interrupt status
0
1
LINE_RIS
Line raw interrupt status
4
1
OVR_RIS
Overrun raw interrupt status
1
1
VSYNC_RIS
VSYNC raw interrupt status
3
1
SR
SR
status register
0x4
32
read-only
n
0x0
0xFFFFFFFF
FNE
FIFO not empty
2
1
HSYNC
HSYNC
0
1
VSYNC
VSYNC
1
1
DFSDM1
Digital filter for sigma delta modulators
DFSDM
0x40016000
0x0
0x500
registers
n
DFSDM1_FLT3
DFSDM1_FLT3 global interrupt
42
DFSDM1_FLT0
DFSDM1_FLT0 global interrupt
61
DFSDM1_FLT1
DFSDM1_FLT1 global interrupt
62
DFSDM1_FLT2
DFSDM1_FLT2 global interrupt
63
CH0AWSCDR
CH0AWSCDR
analog watchdog and short-circuit detector register
0x8
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH0CFGR1
CH0CFGR1
channel configuration y register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
CKOUTDIV
CKOUTDIV
16
8
CKOUTSRC
CKOUTSRC
30
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
DFSDMEN
DFSDMEN
31
1
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH0CFGR2
CH0CFGR2
channel configuration y register
0x4
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH0DATINR
CH0DATINR
channel data input register
0x10
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH0DLYR
CH0DLYR
channel y delay register
0x14
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH0WDATR
CH0WDATR
channel watchdog filter data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH1AWSCDR
CH1AWSCDR
CH1AWSCDR
0x28
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH1CFGR1
CH1CFGR1
CH1CFGR1
0x20
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH1CFGR2
CH1CFGR2
CH1CFGR2
0x24
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH1DATINR
CH1DATINR
CH1DATINR
0x30
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH1DLYR
CH1DLYR
channel y delay register
0x34
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH1WDATR
CH1WDATR
CH1WDATR
0x2C
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH2AWSCDR
CH2AWSCDR
CH2AWSCDR
0x48
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH2CFGR1
CH2CFGR1
CH2CFGR1
0x40
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH2CFGR2
CH2CFGR2
CH2CFGR2
0x44
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH2DATINR
CH2DATINR
CH2DATINR
0x50
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH2DLYR
CH2DLYR
channel y delay register
0x54
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH2WDATR
CH2WDATR
CH2WDATR
0x4C
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH3AWSCDR
CH3AWSCDR
CH3AWSCDR
0x68
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH3CFGR1
CH3CFGR1
CH3CFGR1
0x60
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH3CFGR2
CH3CFGR2
CH3CFGR2
0x64
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH3DATINR
CH3DATINR
CH3DATINR
0x70
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH3DLYR
CH3DLYR
channel y delay register
0x74
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH3WDATR
CH3WDATR
CH3WDATR
0x6C
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH4AWSCDR
CH4AWSCDR
CH4AWSCDR
0x88
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH4CFGR1
CH4CFGR1
CH4CFGR1
0x80
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH4CFGR2
CH4CFGR2
CH4CFGR2
0x84
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH4DATINR
CH4DATINR
CH4DATINR
0x90
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH4DLYR
CH4DLYR
channel y delay register
0x94
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH4WDATR
CH4WDATR
CH4WDATR
0x8C
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH5AWSCDR
CH5AWSCDR
CH5AWSCDR
0xA8
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH5CFGR1
CH5CFGR1
CH5CFGR1
0xA0
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH5CFGR2
CH5CFGR2
CH5CFGR2
0xA4
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH5DATINR
CH5DATINR
CH5DATINR
0xB0
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH5DLYR
CH5DLYR
channel y delay register
0xB4
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH5WDATR
CH5WDATR
CH5WDATR
0xAC
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH6AWSCDR
CH6AWSCDR
CH6AWSCDR
0xC8
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH6CFGR1
CH6CFGR1
CH6CFGR1
0xC0
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH6CFGR2
CH6CFGR2
CH6CFGR2
0xC4
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH6DATINR
CH6DATINR
CH6DATINR
0xD0
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH6DLYR
CH6DLYR
channel y delay register
0xD4
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH6WDATR
CH6WDATR
CH6WDATR
0xCC
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
CH7AWSCDR
CH7AWSCDR
CH7AWSCDR
0xE8
32
read-write
n
0x0
0xFFFFFFFF
AWFORD
AWFORD
22
2
AWFOSR
AWFOSR
16
5
BKSCD
BKSCD
12
4
SCDT
SCDT
0
8
CH7CFGR1
CH7CFGR1
CH7CFGR1
0xE0
32
read-write
n
0x0
0xFFFFFFFF
CHEN
CHEN
7
1
CHINSEL
CHINSEL
8
1
CKABEN
CKABEN
6
1
DATMPX
DATMPX
12
2
DATPACK
DATPACK
14
2
SCDEN
SCDEN
5
1
SITP
SITP
0
2
SPICKSEL
SPICKSEL
2
2
CH7CFGR2
CH7CFGR2
CH7CFGR2
0xE4
32
read-write
n
0x0
0xFFFFFFFF
DTRBS
DTRBS
3
5
OFFSET
OFFSET
8
24
CH7DATINR
CH7DATINR
CH7DATINR
0xF0
32
read-write
n
0x0
0xFFFFFFFF
INDAT0
INDAT0
0
16
INDAT1
INDAT1
16
16
CH7DLYR
CH7DLYR
channel y delay register
0xF4
32
read-write
n
0x0
0xFFFFFFFF
PLSSKP
PLSSKP
0
6
CH7WDATR
CH7WDATR
CH7WDATR
0xEC
32
read-write
n
0x0
0xFFFFFFFF
WDATA
WDATA
0
16
DFSDM_FLT0AWCFR
DFSDM_FLT0AWCFR
analog watchdog clear flag register
0x12C
32
read-write
n
0x0
0xFFFFFFFF
CLRAWHTF
Clear the analog watchdog high threshold flag
8
8
CLRAWLTF
Clear the analog watchdog low threshold flag
0
8
DFSDM_FLT0AWHTR
DFSDM_FLT0AWHTR
analog watchdog high threshold register
0x120
32
read-write
n
0x0
0xFFFFFFFF
AWHT
Analog watchdog high threshold
8
24
BKAWH
Break signal assignment to analog watchdog high threshold event
0
4
DFSDM_FLT0AWLTR
DFSDM_FLT0AWLTR
analog watchdog low threshold register
0x124
32
read-write
n
0x0
0xFFFFFFFF
AWLT
Analog watchdog low threshold
8
24
BKAWL
Break signal assignment to analog watchdog low threshold event
0
4
DFSDM_FLT0AWSR
DFSDM_FLT0AWSR
analog watchdog status register
0x128
32
read-only
n
0x0
0xFFFFFFFF
AWHTF
Analog watchdog high threshold flag
8
8
AWLTF
Analog watchdog low threshold flag
0
8
DFSDM_FLT0CNVTIMR
DFSDM_FLT0CNVTIMR
conversion timer register
0x138
32
read-only
n
0x0
0xFFFFFFFF
CNVCNT
28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
4
28
DFSDM_FLT0CR1
DFSDM_FLT0CR1
control register 1
0x100
32
read-write
n
0x0
0xFFFFFFFF
AWFSEL
Analog watchdog fast mode select
30
1
DFEN
DFSDM enable
0
1
FAST
Fast conversion mode selection for regular conversions
29
1
JDMAEN
DMA channel enabled to read data for the injected channel group
5
1
JEXTEN
Trigger enable and trigger edge selection for injected conversions
13
2
JEXTSEL
Trigger signal selection for launching injected conversions
8
3
JSCAN
Scanning conversion mode for injected conversions
4
1
JSWSTART
Start a conversion of the injected group of channels
1
1
JSYNC
Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
3
1
RCH
Regular channel selection
24
3
RCONT
Continuous mode selection for regular conversions
18
1
RDMAEN
DMA channel enabled to read data for the regular conversion
21
1
RSWSTART
Software start of a conversion on the regular channel
17
1
RSYNC
Launch regular conversion synchronously with DFSDM0
19
1
DFSDM_FLT0CR2
DFSDM_FLT0CR2
control register 2
0x104
32
read-write
n
0x0
0xFFFFFFFF
AWDCH
Analog watchdog channel selection
16
8
AWDIE
Analog watchdog interrupt enable
4
1
CKABIE
Clock absence interrupt enable
6
1
EXCH
Extremes detector channel selection
8
8
JEOCIE
Injected end of conversion interrupt enable
0
1
JOVRIE
Injected data overrun interrupt enable
2
1
REOCIE
Regular end of conversion interrupt enable
1
1
ROVRIE
Regular data overrun interrupt enable
3
1
SCDIE
Short-circuit detector interrupt enable
5
1
DFSDM_FLT0EXMAX
DFSDM_FLT0EXMAX
Extremes detector maximum register
0x130
32
read-only
n
0x80000000
0xFFFFFFFF
EXMAX
Extremes detector maximum value
8
24
EXMAXCH
Extremes detector maximum data channel
0
3
DFSDM_FLT0EXMIN
DFSDM_FLT0EXMIN
Extremes detector minimum register
0x134
32
read-only
n
0x7FFFFF00
0xFFFFFFFF
EXMIN
EXMIN
8
24
EXMINCH
Extremes detector minimum data channel
0
3
DFSDM_FLT0FCR
DFSDM_FLT0FCR
filter control register
0x114
32
read-write
n
0x0
0xFFFFFFFF
FORD
Sinc filter order
29
3
FOSR
Sinc filter oversampling ratio (decimation rate)
16
10
IOSR
Integrator oversampling ratio (averaging length)
0
8
DFSDM_FLT0ICR
DFSDM_FLT0ICR
interrupt flag clear register
0x10C
32
read-write
n
0x0
0xFFFFFFFF
CLRCKABF
Clear the clock absence flag
16
8
CLRJOVRF
Clear the injected conversion overrun flag
2
1
CLRROVRF
Clear the regular conversion overrun flag
3
1
CLRSCDF
Clear the short-circuit detector flag
24
8
DFSDM_FLT0ISR
DFSDM_FLT0ISR
interrupt and status register
0x108
32
read-only
n
0xFF0000
0xFFFFFFFF
AWDF
Analog watchdog
4
1
CKABF
Clock absence flag
16
8
JCIP
Injected conversion in progress status
13
1
JEOCF
End of injected conversion flag
0
1
JOVRF
Injected conversion overrun flag
2
1
RCIP
Regular conversion in progress status
14
1
REOCF
End of regular conversion flag
1
1
ROVRF
Regular conversion overrun flag
3
1
SCDF
short-circuit detector flag
24
8
DFSDM_FLT0JCHGR
DFSDM_FLT0JCHGR
injected channel group selection register
0x110
32
read-write
n
0x1
0xFFFFFFFF
JCHG
Injected channel group selection
0
8
DFSDM_FLT0JDATAR
DFSDM_FLT0JDATAR
data register for injected group
0x118
32
read-only
n
0x0
0xFFFFFFFF
JDATA
Injected group conversion data
8
24
JDATACH
Injected channel most recently converted
0
3
DFSDM_FLT0RDATAR
DFSDM_FLT0RDATAR
data register for the regular channel
0x11C
32
read-only
n
0x0
0xFFFFFFFF
RDATA
Regular channel conversion data
8
24
RDATACH
Regular channel most recently converted
0
3
RPEND
Regular channel pending data
4
1
DFSDM_FLT1AWCFR
DFSDM_FLT1AWCFR
analog watchdog clear flag register
0x1AC
32
read-write
n
0x0
0xFFFFFFFF
CLRAWHTF
Clear the analog watchdog high threshold flag
8
8
CLRAWLTF
Clear the analog watchdog low threshold flag
0
8
DFSDM_FLT1AWHTR
DFSDM_FLT1AWHTR
analog watchdog high threshold register
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
AWHT
Analog watchdog high threshold
8
24
BKAWH
Break signal assignment to analog watchdog high threshold event
0
4
DFSDM_FLT1AWLTR
DFSDM_FLT1AWLTR
analog watchdog low threshold register
0x1A4
32
read-write
n
0x0
0xFFFFFFFF
AWLT
Analog watchdog low threshold
8
24
BKAWL
Break signal assignment to analog watchdog low threshold event
0
4
DFSDM_FLT1AWSR
DFSDM_FLT1AWSR
analog watchdog status register
0x1A8
32
read-only
n
0x0
0xFFFFFFFF
AWHTF
Analog watchdog high threshold flag
8
8
AWLTF
Analog watchdog low threshold flag
0
8
DFSDM_FLT1CHGR
DFSDM_FLT1JCHGR
injected channel group selection register
0x190
32
read-write
n
0x1
0xFFFFFFFF
JCHG
Injected channel group selection
0
8
DFSDM_FLT1CNVTIMR
DFSDM_FLT1CNVTIMR
conversion timer register
0x1B8
32
read-only
n
0x0
0xFFFFFFFF
CNVCNT
28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
4
28
DFSDM_FLT1CR1
DFSDM_FLT1CR1
control register 1
0x180
32
read-write
n
0x0
0xFFFFFFFF
AWFSEL
Analog watchdog fast mode select
30
1
DFEN
DFSDM enable
0
1
FAST
Fast conversion mode selection for regular conversions
29
1
JDMAEN
DMA channel enabled to read data for the injected channel group
5
1
JEXTEN
Trigger enable and trigger edge selection for injected conversions
13
2
JEXTSEL
Trigger signal selection for launching injected conversions
8
3
JSCAN
Scanning conversion mode for injected conversions
4
1
JSWSTART
Start a conversion of the injected group of channels
1
1
JSYNC
Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
3
1
RCH
Regular channel selection
24
3
RCONT
Continuous mode selection for regular conversions
18
1
RDMAEN
DMA channel enabled to read data for the regular conversion
21
1
RSWSTART
Software start of a conversion on the regular channel
17
1
RSYNC
Launch regular conversion synchronously with DFSDM0
19
1
DFSDM_FLT1CR2
DFSDM_FLT1CR2
control register 2
0x184
32
read-write
n
0x0
0xFFFFFFFF
AWDCH
Analog watchdog channel selection
16
8
AWDIE
Analog watchdog interrupt enable
4
1
CKABIE
Clock absence interrupt enable
6
1
EXCH
Extremes detector channel selection
8
8
JEOCIE
Injected end of conversion interrupt enable
0
1
JOVRIE
Injected data overrun interrupt enable
2
1
REOCIE
Regular end of conversion interrupt enable
1
1
ROVRIE
Regular data overrun interrupt enable
3
1
SCDIE
Short-circuit detector interrupt enable
5
1
DFSDM_FLT1EXMAX
DFSDM_FLT1EXMAX
Extremes detector maximum register
0x1B0
32
read-only
n
0x80000000
0xFFFFFFFF
EXMAX
Extremes detector maximum value
8
24
EXMAXCH
Extremes detector maximum data channel
0
3
DFSDM_FLT1EXMIN
DFSDM_FLT1EXMIN
Extremes detector minimum register
0x1B4
32
read-only
n
0x7FFFFF00
0xFFFFFFFF
EXMIN
EXMIN
8
24
EXMINCH
Extremes detector minimum data channel
0
3
DFSDM_FLT1FCR
DFSDM1_FCR
filter control register
0x194
32
read-write
n
0x0
0xFFFFFFFF
FORD
Sinc filter order
29
3
FOSR
Sinc filter oversampling ratio (decimation rate)
16
10
IOSR
Integrator oversampling ratio (averaging length)
0
8
DFSDM_FLT1ICR
DFSDM1_ICR
interrupt flag clear register
0x18C
32
read-write
n
0x0
0xFFFFFFFF
CLRCKABF
Clear the clock absence flag
16
8
CLRJOVRF
Clear the injected conversion overrun flag
2
1
CLRROVRF
Clear the regular conversion overrun flag
3
1
CLRSCDF
Clear the short-circuit detector flag
24
8
DFSDM_FLT1ISR
DFSDM_FLT1ISR
interrupt and status register
0x188
32
read-only
n
0xFF0000
0xFFFFFFFF
AWDF
Analog watchdog
4
1
CKABF
Clock absence flag
16
8
JCIP
Injected conversion in progress status
13
1
JEOCF
End of injected conversion flag
0
1
JOVRF
Injected conversion overrun flag
2
1
RCIP
Regular conversion in progress status
14
1
REOCF
End of regular conversion flag
1
1
ROVRF
Regular conversion overrun flag
3
1
SCDF
short-circuit detector flag
24
8
DFSDM_FLT1JDATAR
DFSDM_FLT1JDATAR
data register for injected group
0x198
32
read-only
n
0x0
0xFFFFFFFF
JDATA
Injected group conversion data
8
24
JDATACH
Injected channel most recently converted
0
3
DFSDM_FLT1RDATAR
DFSDM_FLT1RDATAR
data register for the regular channel
0x19C
32
read-only
n
0x0
0xFFFFFFFF
RDATA
Regular channel conversion data
8
24
RDATACH
Regular channel most recently converted
0
3
RPEND
Regular channel pending data
4
1
DFSDM_FLT2AWCFR
DFSDM_FLT2AWCFR
analog watchdog clear flag register
0x22C
32
read-write
n
0x0
0xFFFFFFFF
CLRAWHTF
Clear the analog watchdog high threshold flag
8
8
CLRAWLTF
Clear the analog watchdog low threshold flag
0
8
DFSDM_FLT2AWHTR
DFSDM_FLT2AWHTR
analog watchdog high threshold register
0x220
32
read-write
n
0x0
0xFFFFFFFF
AWHT
Analog watchdog high threshold
8
24
BKAWH
Break signal assignment to analog watchdog high threshold event
0
4
DFSDM_FLT2AWLTR
DFSDM_FLT2AWLTR
analog watchdog low threshold register
0x224
32
read-write
n
0x0
0xFFFFFFFF
AWLT
Analog watchdog low threshold
8
24
BKAWL
Break signal assignment to analog watchdog low threshold event
0
4
DFSDM_FLT2AWSR
DFSDM_FLT2AWSR
analog watchdog status register
0x228
32
read-only
n
0x0
0xFFFFFFFF
AWHTF
Analog watchdog high threshold flag
8
8
AWLTF
Analog watchdog low threshold flag
0
8
DFSDM_FLT2CNVTIMR
DFSDM_FLT2CNVTIMR
conversion timer register
0x238
32
read-only
n
0x0
0xFFFFFFFF
CNVCNT
28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
4
28
DFSDM_FLT2CR1
DFSDM_FLT2CR1
control register 1
0x200
32
read-write
n
0x0
0xFFFFFFFF
AWFSEL
Analog watchdog fast mode select
30
1
DFEN
DFSDM enable
0
1
FAST
Fast conversion mode selection for regular conversions
29
1
JDMAEN
DMA channel enabled to read data for the injected channel group
5
1
JEXTEN
Trigger enable and trigger edge selection for injected conversions
13
2
JEXTSEL
Trigger signal selection for launching injected conversions
8
3
JSCAN
Scanning conversion mode for injected conversions
4
1
JSWSTART
Start a conversion of the injected group of channels
1
1
JSYNC
Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
3
1
RCH
Regular channel selection
24
3
RCONT
Continuous mode selection for regular conversions
18
1
RDMAEN
DMA channel enabled to read data for the regular conversion
21
1
RSWSTART
Software start of a conversion on the regular channel
17
1
RSYNC
Launch regular conversion synchronously with DFSDM0
19
1
DFSDM_FLT2CR2
DFSDM_FLT2CR2
control register 2
0x204
32
read-write
n
0x0
0xFFFFFFFF
AWDCH
Analog watchdog channel selection
16
8
AWDIE
Analog watchdog interrupt enable
4
1
CKABIE
Clock absence interrupt enable
6
1
EXCH
Extremes detector channel selection
8
8
JEOCIE
Injected end of conversion interrupt enable
0
1
JOVRIE
Injected data overrun interrupt enable
2
1
REOCIE
Regular end of conversion interrupt enable
1
1
ROVRIE
Regular data overrun interrupt enable
3
1
SCDIE
Short-circuit detector interrupt enable
5
1
DFSDM_FLT2EXMAX
DFSDM_FLT2EXMAX
Extremes detector maximum register
0x230
32
read-only
n
0x80000000
0xFFFFFFFF
EXMAX
Extremes detector maximum value
8
24
EXMAXCH
Extremes detector maximum data channel
0
3
DFSDM_FLT2EXMIN
DFSDM_FLT2EXMIN
Extremes detector minimum register
0x234
32
read-only
n
0x7FFFFF00
0xFFFFFFFF
EXMIN
EXMIN
8
24
EXMINCH
Extremes detector minimum data channel
0
3
DFSDM_FLT2FCR
DFSDM_FLT2FCR
filter control register
0x214
32
read-write
n
0x0
0xFFFFFFFF
FORD
Sinc filter order
29
3
FOSR
Sinc filter oversampling ratio (decimation rate)
16
10
IOSR
Integrator oversampling ratio (averaging length)
0
8
DFSDM_FLT2ICR
DFSDM_FLT2ICR
interrupt flag clear register
0x20C
32
read-write
n
0x0
0xFFFFFFFF
CLRCKABF
Clear the clock absence flag
16
8
CLRJOVRF
Clear the injected conversion overrun flag
2
1
CLRROVRF
Clear the regular conversion overrun flag
3
1
CLRSCDF
Clear the short-circuit detector flag
24
8
DFSDM_FLT2ISR
DFSDM_FLT2ISR
interrupt and status register
0x208
32
read-only
n
0xFF0000
0xFFFFFFFF
AWDF
Analog watchdog
4
1
CKABF
Clock absence flag
16
8
JCIP
Injected conversion in progress status
13
1
JEOCF
End of injected conversion flag
0
1
JOVRF
Injected conversion overrun flag
2
1
RCIP
Regular conversion in progress status
14
1
REOCF
End of regular conversion flag
1
1
ROVRF
Regular conversion overrun flag
3
1
SCDF
short-circuit detector flag
24
8
DFSDM_FLT2JCHGR
DFSDM_FLT2JCHGR
injected channel group selection register
0x210
32
read-write
n
0x1
0xFFFFFFFF
JCHG
Injected channel group selection
0
8
DFSDM_FLT2JDATAR
DFSDM_FLT2JDATAR
data register for injected group
0x218
32
read-only
n
0x0
0xFFFFFFFF
JDATA
Injected group conversion data
8
24
JDATACH
Injected channel most recently converted
0
3
DFSDM_FLT2RDATAR
DFSDM_FLT2RDATAR
data register for the regular channel
0x21C
32
read-only
n
0x0
0xFFFFFFFF
RDATA
Regular channel conversion data
8
24
RDATACH
Regular channel most recently converted
0
3
RPEND
Regular channel pending data
4
1
DFSDM_FLT3AWCFR
DFSDM_FLT3AWCFR
analog watchdog clear flag register
0x2AC
32
read-write
n
0x0
0xFFFFFFFF
CLRAWHTF
Clear the analog watchdog high threshold flag
8
8
CLRAWLTF
Clear the analog watchdog low threshold flag
0
8
DFSDM_FLT3AWHTR
DFSDM_FLT3AWHTR
analog watchdog high threshold register
0x2A0
32
read-write
n
0x0
0xFFFFFFFF
AWHT
Analog watchdog high threshold
8
24
BKAWH
Break signal assignment to analog watchdog high threshold event
0
4
DFSDM_FLT3AWLTR
DFSDM_FLT3AWLTR
analog watchdog low threshold register
0x2A4
32
read-write
n
0x0
0xFFFFFFFF
AWLT
Analog watchdog low threshold
8
24
BKAWL
Break signal assignment to analog watchdog low threshold event
0
4
DFSDM_FLT3AWSR
DFSDM_FLT3AWSR
analog watchdog status register
0x2A8
32
read-only
n
0x0
0xFFFFFFFF
AWHTF
Analog watchdog high threshold flag
8
8
AWLTF
Analog watchdog low threshold flag
0
8
DFSDM_FLT3CNVTIMR
DFSDM_FLT3CNVTIMR
conversion timer register
0x2B8
32
read-only
n
0x0
0xFFFFFFFF
CNVCNT
28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
4
28
DFSDM_FLT3CR1
DFSDM_FLT3CR1
control register 1
0x280
32
read-write
n
0x0
0xFFFFFFFF
AWFSEL
Analog watchdog fast mode select
30
1
DFEN
DFSDM enable
0
1
FAST
Fast conversion mode selection for regular conversions
29
1
JDMAEN
DMA channel enabled to read data for the injected channel group
5
1
JEXTEN
Trigger enable and trigger edge selection for injected conversions
13
2
JEXTSEL
Trigger signal selection for launching injected conversions
8
3
JSCAN
Scanning conversion mode for injected conversions
4
1
JSWSTART
Start a conversion of the injected group of channels
1
1
JSYNC
Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
3
1
RCH
Regular channel selection
24
3
RCONT
Continuous mode selection for regular conversions
18
1
RDMAEN
DMA channel enabled to read data for the regular conversion
21
1
RSWSTART
Software start of a conversion on the regular channel
17
1
RSYNC
Launch regular conversion synchronously with DFSDM0
19
1
DFSDM_FLT3CR2
DFSDM_FLT3CR2
control register 2
0x284
32
read-write
n
0x0
0xFFFFFFFF
AWDCH
Analog watchdog channel selection
16
8
AWDIE
Analog watchdog interrupt enable
4
1
CKABIE
Clock absence interrupt enable
6
1
EXCH
Extremes detector channel selection
8
8
JEOCIE
Injected end of conversion interrupt enable
0
1
JOVRIE
Injected data overrun interrupt enable
2
1
REOCIE
Regular end of conversion interrupt enable
1
1
ROVRIE
Regular data overrun interrupt enable
3
1
SCDIE
Short-circuit detector interrupt enable
5
1
DFSDM_FLT3EXMAX
DFSDM_FLT3EXMAX
Extremes detector maximum register
0x2B0
32
read-only
n
0x80000000
0xFFFFFFFF
EXMAX
Extremes detector maximum value
8
24
EXMAXCH
Extremes detector maximum data channel
0
3
DFSDM_FLT3EXMIN
DFSDM_FLT3EXMIN
Extremes detector minimum register
0x2B4
32
read-only
n
0x7FFFFF00
0xFFFFFFFF
EXMIN
EXMIN
8
24
EXMINCH
Extremes detector minimum data channel
0
3
DFSDM_FLT3FCR
DFSDM_FLT3FCR
filter control register
0x294
32
read-write
n
0x0
0xFFFFFFFF
FORD
Sinc filter order
29
3
FOSR
Sinc filter oversampling ratio (decimation rate)
16
10
IOSR
Integrator oversampling ratio (averaging length)
0
8
DFSDM_FLT3ICR
DFSDM_FLT3ICR
interrupt flag clear register
0x28C
32
read-write
n
0x0
0xFFFFFFFF
CLRCKABF
Clear the clock absence flag
16
8
CLRJOVRF
Clear the injected conversion overrun flag
2
1
CLRROVRF
Clear the regular conversion overrun flag
3
1
CLRSCDF
Clear the short-circuit detector flag
24
8
DFSDM_FLT3ISR
DFSDM_FLT3ISR
interrupt and status register
0x288
32
read-only
n
0xFF0000
0xFFFFFFFF
AWDF
Analog watchdog
4
1
CKABF
Clock absence flag
16
8
JCIP
Injected conversion in progress status
13
1
JEOCF
End of injected conversion flag
0
1
JOVRF
Injected conversion overrun flag
2
1
RCIP
Regular conversion in progress status
14
1
REOCF
End of regular conversion flag
1
1
ROVRF
Regular conversion overrun flag
3
1
SCDF
short-circuit detector flag
24
8
DFSDM_FLT3JCHGR
DFSDM_FLT3JCHGR
injected channel group selection register
0x290
32
read-write
n
0x1
0xFFFFFFFF
JCHG
Injected channel group selection
0
8
DFSDM_FLT3JDATAR
DFSDM_FLT3JDATAR
data register for injected group
0x298
32
read-only
n
0x0
0xFFFFFFFF
JDATA
Injected group conversion data
8
24
JDATACH
Injected channel most recently converted
0
3
DFSDM_FLT3RDATAR
DFSDM_FLT3RDATAR
data register for the regular channel
0x29C
32
read-only
n
0x0
0xFFFFFFFF
RDATA
Regular channel conversion data
8
24
RDATACH
Regular channel most recently converted
0
3
RPEND
Regular channel pending data
4
1
DMA1
Direct memory access controller
DMA
0x40020000
0x0
0x400
registers
n
DMA1_CH1
DMA1 Channel1 global interrupt
11
DMA1_CH2
DMA1 Channel2 global interrupt
12
DMA1_CH3
DMA1 Channel3 interrupt
13
DMA1_CH4
DMA1 Channel4 interrupt
14
DMA1_CH5
DMA1 Channel5 interrupt
15
DMA1_CH6
DMA1 Channel6 interrupt
16
DMA1_CH7
DMA1 Channel 7 interrupt
17
CCR1
CCR1
channel x configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
channel x configuration register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
channel x configuration register
0x30
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
channel x configuration register
0x44
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
channel x configuration register
0x58
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
channel x configuration register
0x6C
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
channel x configuration register
0x80
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
channel x memory address register
0x14
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR2
CMAR2
channel x memory address register
0x28
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR3
CMAR3
channel x memory address register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR4
CMAR4
channel x memory address register
0x50
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR5
CMAR5
channel x memory address register
0x64
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR6
CMAR6
channel x memory address register
0x78
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR7
CMAR7
channel x memory address register
0x8C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CNDTR1
CNDTR1
channel x number of data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
channel x number of data register
0x20
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
channel x number of data register
0x34
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
channel x number of data register
0x48
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
channel x number of data register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
channel x number of data register
0x70
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
channel x number of data register
0x84
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
channel x peripheral address register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR2
CPAR2
channel x peripheral address register
0x24
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR3
CPAR3
channel x peripheral address register
0x38
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR4
CPAR4
channel x peripheral address register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR5
CPAR5
channel x peripheral address register
0x60
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR6
CPAR6
channel x peripheral address register
0x74
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR7
CPAR7
channel x peripheral address register
0x88
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
IFCR
IFCR
interrupt flag clear register
0x4
32
write-only
n
0x0
0xFFFFFFFF
CGIF1
Channel x global interrupt clear (x = 1 ..7)
0
1
CGIF2
Channel x global interrupt clear (x = 1 ..7)
4
1
CGIF3
Channel x global interrupt clear (x = 1 ..7)
8
1
CGIF4
Channel x global interrupt clear (x = 1 ..7)
12
1
CGIF5
Channel x global interrupt clear (x = 1 ..7)
16
1
CGIF6
Channel x global interrupt clear (x = 1 ..7)
20
1
CGIF7
Channel x global interrupt clear (x = 1 ..7)
24
1
CHTIF1
Channel x half transfer clear (x = 1 ..7)
2
1
CHTIF2
Channel x half transfer clear (x = 1 ..7)
6
1
CHTIF3
Channel x half transfer clear (x = 1 ..7)
10
1
CHTIF4
Channel x half transfer clear (x = 1 ..7)
14
1
CHTIF5
Channel x half transfer clear (x = 1 ..7)
18
1
CHTIF6
Channel x half transfer clear (x = 1 ..7)
22
1
CHTIF7
Channel x half transfer clear (x = 1 ..7)
26
1
CTCIF1
Channel x transfer complete clear (x = 1 ..7)
1
1
CTCIF2
Channel x transfer complete clear (x = 1 ..7)
5
1
CTCIF3
Channel x transfer complete clear (x = 1 ..7)
9
1
CTCIF4
Channel x transfer complete clear (x = 1 ..7)
13
1
CTCIF5
Channel x transfer complete clear (x = 1 ..7)
17
1
CTCIF6
Channel x transfer complete clear (x = 1 ..7)
21
1
CTCIF7
Channel x transfer complete clear (x = 1 ..7)
25
1
CTEIF1
Channel x transfer error clear (x = 1 ..7)
3
1
CTEIF2
Channel x transfer error clear (x = 1 ..7)
7
1
CTEIF3
Channel x transfer error clear (x = 1 ..7)
11
1
CTEIF4
Channel x transfer error clear (x = 1 ..7)
15
1
CTEIF5
Channel x transfer error clear (x = 1 ..7)
19
1
CTEIF6
Channel x transfer error clear (x = 1 ..7)
23
1
CTEIF7
Channel x transfer error clear (x = 1 ..7)
27
1
ISR
ISR
interrupt status register
0x0
32
read-only
n
0x0
0xFFFFFFFF
GIF1
Channel x global interrupt flag (x = 1 ..7)
0
1
GIF2
Channel x global interrupt flag (x = 1 ..7)
4
1
GIF3
Channel x global interrupt flag (x = 1 ..7)
8
1
GIF4
Channel x global interrupt flag (x = 1 ..7)
12
1
GIF5
Channel x global interrupt flag (x = 1 ..7)
16
1
GIF6
Channel x global interrupt flag (x = 1 ..7)
20
1
GIF7
Channel x global interrupt flag (x = 1 ..7)
24
1
HTIF1
Channel x half transfer flag (x = 1 ..7)
2
1
HTIF2
Channel x half transfer flag (x = 1 ..7)
6
1
HTIF3
Channel x half transfer flag (x = 1 ..7)
10
1
HTIF4
Channel x half transfer flag (x = 1 ..7)
14
1
HTIF5
Channel x half transfer flag (x = 1 ..7)
18
1
HTIF6
Channel x half transfer flag (x = 1 ..7)
22
1
HTIF7
Channel x half transfer flag (x = 1 ..7)
26
1
TCIF1
Channel x transfer complete flag (x = 1 ..7)
1
1
TCIF2
Channel x transfer complete flag (x = 1 ..7)
5
1
TCIF3
Channel x transfer complete flag (x = 1 ..7)
9
1
TCIF4
Channel x transfer complete flag (x = 1 ..7)
13
1
TCIF5
Channel x transfer complete flag (x = 1 ..7)
17
1
TCIF6
Channel x transfer complete flag (x = 1 ..7)
21
1
TCIF7
Channel x transfer complete flag (x = 1 ..7)
25
1
TEIF1
Channel x transfer error flag (x = 1 ..7)
3
1
TEIF2
Channel x transfer error flag (x = 1 ..7)
7
1
TEIF3
Channel x transfer error flag (x = 1 ..7)
11
1
TEIF4
Channel x transfer error flag (x = 1 ..7)
15
1
TEIF5
Channel x transfer error flag (x = 1 ..7)
19
1
TEIF6
Channel x transfer error flag (x = 1 ..7)
23
1
TEIF7
Channel x transfer error flag (x = 1 ..7)
27
1
DMA2
Direct memory access controller
DMA
0x40020400
0x0
0x400
registers
n
DMA2_CH1
DMA2 Channel 1 global Interrupt
56
DMA2_CH2
DMA2 Channel 2 global Interrupt
57
DMA2_CH3
DMA2 Channel 3 global Interrupt
58
DMA2_CH4
DMA2 Channel 4 global Interrupt
59
DMA2_CH5
DMA2 Channel 5 global Interrupt
60
DMA2_CH6
DMA2 Channel 6 global Interrupt
68
DMA2_CH7
DMA2 Channel 7 global Interrupt
69
CCR1
CCR1
channel x configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR2
CCR2
channel x configuration register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR3
CCR3
channel x configuration register
0x30
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR4
CCR4
channel x configuration register
0x44
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR5
CCR5
channel x configuration register
0x58
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR6
CCR6
channel x configuration register
0x6C
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CCR7
CCR7
channel x configuration register
0x80
32
read-write
n
0x0
0xFFFFFFFF
CIRC
Circular mode
5
1
DIR
Data transfer direction
4
1
EN
Channel enable
0
1
HTIE
Half transfer interrupt enable
2
1
MEM2MEM
Memory to memory mode
14
1
MINC
Memory increment mode
7
1
MSIZE
Memory size
10
2
PINC
Peripheral increment mode
6
1
PL
Channel priority level
12
2
PSIZE
Peripheral size
8
2
TCIE
Transfer complete interrupt enable
1
1
TEIE
Transfer error interrupt enable
3
1
CMAR1
CMAR1
channel x memory address register
0x14
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR2
CMAR2
channel x memory address register
0x28
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR3
CMAR3
channel x memory address register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR4
CMAR4
channel x memory address register
0x50
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR5
CMAR5
channel x memory address register
0x64
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR6
CMAR6
channel x memory address register
0x78
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CMAR7
CMAR7
channel x memory address register
0x8C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
CNDTR1
CNDTR1
channel x number of data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR2
CNDTR2
channel x number of data register
0x20
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR3
CNDTR3
channel x number of data register
0x34
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR4
CNDTR4
channel x number of data register
0x48
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR5
CNDTR5
channel x number of data register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR6
CNDTR6
channel x number of data register
0x70
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CNDTR7
CNDTR7
channel x number of data register
0x84
32
read-write
n
0x0
0xFFFFFFFF
NDT
Number of data to transfer
0
16
CPAR1
CPAR1
channel x peripheral address register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR2
CPAR2
channel x peripheral address register
0x24
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR3
CPAR3
channel x peripheral address register
0x38
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR4
CPAR4
channel x peripheral address register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR5
CPAR5
channel x peripheral address register
0x60
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR6
CPAR6
channel x peripheral address register
0x74
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
CPAR7
CPAR7
channel x peripheral address register
0x88
32
read-write
n
0x0
0xFFFFFFFF
PA
Peripheral address
0
32
IFCR
IFCR
interrupt flag clear register
0x4
32
write-only
n
0x0
0xFFFFFFFF
CGIF1
Channel x global interrupt clear (x = 1 ..7)
0
1
CGIF2
Channel x global interrupt clear (x = 1 ..7)
4
1
CGIF3
Channel x global interrupt clear (x = 1 ..7)
8
1
CGIF4
Channel x global interrupt clear (x = 1 ..7)
12
1
CGIF5
Channel x global interrupt clear (x = 1 ..7)
16
1
CGIF6
Channel x global interrupt clear (x = 1 ..7)
20
1
CGIF7
Channel x global interrupt clear (x = 1 ..7)
24
1
CHTIF1
Channel x half transfer clear (x = 1 ..7)
2
1
CHTIF2
Channel x half transfer clear (x = 1 ..7)
6
1
CHTIF3
Channel x half transfer clear (x = 1 ..7)
10
1
CHTIF4
Channel x half transfer clear (x = 1 ..7)
14
1
CHTIF5
Channel x half transfer clear (x = 1 ..7)
18
1
CHTIF6
Channel x half transfer clear (x = 1 ..7)
22
1
CHTIF7
Channel x half transfer clear (x = 1 ..7)
26
1
CTCIF1
Channel x transfer complete clear (x = 1 ..7)
1
1
CTCIF2
Channel x transfer complete clear (x = 1 ..7)
5
1
CTCIF3
Channel x transfer complete clear (x = 1 ..7)
9
1
CTCIF4
Channel x transfer complete clear (x = 1 ..7)
13
1
CTCIF5
Channel x transfer complete clear (x = 1 ..7)
17
1
CTCIF6
Channel x transfer complete clear (x = 1 ..7)
21
1
CTCIF7
Channel x transfer complete clear (x = 1 ..7)
25
1
CTEIF1
Channel x transfer error clear (x = 1 ..7)
3
1
CTEIF2
Channel x transfer error clear (x = 1 ..7)
7
1
CTEIF3
Channel x transfer error clear (x = 1 ..7)
11
1
CTEIF4
Channel x transfer error clear (x = 1 ..7)
15
1
CTEIF5
Channel x transfer error clear (x = 1 ..7)
19
1
CTEIF6
Channel x transfer error clear (x = 1 ..7)
23
1
CTEIF7
Channel x transfer error clear (x = 1 ..7)
27
1
ISR
ISR
interrupt status register
0x0
32
read-only
n
0x0
0xFFFFFFFF
GIF1
Channel x global interrupt flag (x = 1 ..7)
0
1
GIF2
Channel x global interrupt flag (x = 1 ..7)
4
1
GIF3
Channel x global interrupt flag (x = 1 ..7)
8
1
GIF4
Channel x global interrupt flag (x = 1 ..7)
12
1
GIF5
Channel x global interrupt flag (x = 1 ..7)
16
1
GIF6
Channel x global interrupt flag (x = 1 ..7)
20
1
GIF7
Channel x global interrupt flag (x = 1 ..7)
24
1
HTIF1
Channel x half transfer flag (x = 1 ..7)
2
1
HTIF2
Channel x half transfer flag (x = 1 ..7)
6
1
HTIF3
Channel x half transfer flag (x = 1 ..7)
10
1
HTIF4
Channel x half transfer flag (x = 1 ..7)
14
1
HTIF5
Channel x half transfer flag (x = 1 ..7)
18
1
HTIF6
Channel x half transfer flag (x = 1 ..7)
22
1
HTIF7
Channel x half transfer flag (x = 1 ..7)
26
1
TCIF1
Channel x transfer complete flag (x = 1 ..7)
1
1
TCIF2
Channel x transfer complete flag (x = 1 ..7)
5
1
TCIF3
Channel x transfer complete flag (x = 1 ..7)
9
1
TCIF4
Channel x transfer complete flag (x = 1 ..7)
13
1
TCIF5
Channel x transfer complete flag (x = 1 ..7)
17
1
TCIF6
Channel x transfer complete flag (x = 1 ..7)
21
1
TCIF7
Channel x transfer complete flag (x = 1 ..7)
25
1
TEIF1
Channel x transfer error flag (x = 1 ..7)
3
1
TEIF2
Channel x transfer error flag (x = 1 ..7)
7
1
TEIF3
Channel x transfer error flag (x = 1 ..7)
11
1
TEIF4
Channel x transfer error flag (x = 1 ..7)
15
1
TEIF5
Channel x transfer error flag (x = 1 ..7)
19
1
TEIF6
Channel x transfer error flag (x = 1 ..7)
23
1
TEIF7
Channel x transfer error flag (x = 1 ..7)
27
1
DMA2D
DMA2D controller
DMA2D
0x4002B000
0x0
0xC00
registers
n
DMA2D
DMA2D global interrupt
90
AMTCR
AMTCR
AHB master timer configuration register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DT
Dead Time
8
8
EN
Enable
0
1
BGCLUT
BGCLUT
BGCLUT
0x800
32
read-write
n
0x0
0xFFFFFFFF
APLHA
APLHA
24
8
BLUE
BLUE
0
8
GREEN
GREEN
8
8
RED
RED
16
8
BGCMAR
BGCMAR
background CLUT memory address register
0x30
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
BGCOLR
BGCOLR
background color register
0x28
32
read-write
n
0x0
0xFFFFFFFF
BLUE
Blue Value
0
8
GREEN
Green Value
8
8
RED
Red Value
16
8
BGMAR
BGMAR
background memory address register
0x14
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
BGOR
BGOR
background offset register
0x18
32
read-write
n
0x0
0xFFFFFFFF
LO
Line offset
0
14
BGPFCCR
BGPFCCR
background PFC control register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AI
Alpha Inverted
20
1
ALPHA
Alpha value
24
8
AM
Alpha mode
16
2
CCM
CLUT Color mode
4
1
CM
Color mode
0
4
CS
CLUT size
8
8
RBS
Red Blue Swap
21
1
START
Start
5
1
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ABORT
Abort
2
1
CAEIE
CLUT access error interrupt enable
11
1
CEIE
Configuration Error Interrupt Enable
13
1
CTCIE
CLUT transfer complete interrupt enable
12
1
MODE
DMA2D mode
16
2
START
Start
0
1
SUSP
Suspend
1
1
TCIE
Transfer complete interrupt enable
9
1
TEIE
Transfer error interrupt enable
8
1
TWIE
Transfer watermark interrupt enable
10
1
FGCLUT
FGCLUT
FGCLUT
0x400
32
read-write
n
0x0
0xFFFFFFFF
APLHA
APLHA
24
8
BLUE
BLUE
0
8
GREEN
GREEN
8
8
RED
RED
16
8
FGCMAR
FGCMAR
foreground CLUT memory address register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory Address
0
32
FGCOLR
FGCOLR
foreground color register
0x20
32
read-write
n
0x0
0xFFFFFFFF
BLUE
Blue Value
0
8
GREEN
Green Value
8
8
RED
Red Value
16
8
FGMAR
FGMAR
foreground memory address register
0xC
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory address
0
32
FGOR
FGOR
foreground offset register
0x10
32
read-write
n
0x0
0xFFFFFFFF
LO
Line offset
0
14
FGPFCCR
FGPFCCR
foreground PFC control register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
AI
Alpha Inverted
20
1
ALPHA
Alpha value
24
8
AM
Alpha mode
16
2
CCM
CLUT color mode
4
1
CM
Color mode
0
4
CS
CLUT size
8
8
RBS
Red Blue Swap
21
1
START
Start
5
1
IFCR
IFCR
interrupt flag clear register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CAECIF
Clear CLUT access error interrupt flag
3
1
CCEIF
Clear configuration error interrupt flag
5
1
CCTCIF
Clear CLUT transfer complete interrupt flag
4
1
CTCIF
Clear transfer complete interrupt flag
1
1
CTEIF
Clear Transfer error interrupt flag
0
1
CTWIF
Clear transfer watermark interrupt flag
2
1
ISR
ISR
Interrupt Status Register
0x4
32
read-only
n
0x0
0xFFFFFFFF
CAEIF
CLUT access error interrupt flag
3
1
CEIF
Configuration error interrupt flag
5
1
CTCIF
CLUT transfer complete interrupt flag
4
1
TCIF
Transfer complete interrupt flag
1
1
TEIF
Transfer error interrupt flag
0
1
TWIF
Transfer watermark interrupt flag
2
1
LWR
LWR
line watermark register
0x48
32
read-write
n
0x0
0xFFFFFFFF
LW
Line watermark
0
16
NLR
NLR
number of line register
0x44
32
read-write
n
0x0
0xFFFFFFFF
NL
Number of lines
0
16
PL
Pixel per lines
16
14
OCOLR
OCOLR
output color register
0x38
32
read-write
n
0x0
0xFFFFFFFF
APLHA
Alpha Channel Value
24
8
BLUE
Blue Value
0
8
GREEN
Green Value
8
8
RED
Red Value
16
8
OMAR
OMAR
output memory address register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
MA
Memory Address
0
32
OOR
OOR
output offset register
0x40
32
read-write
n
0x0
0xFFFFFFFF
LO
Line Offset
0
14
OPFCCR
OPFCCR
output PFC control register
0x34
32
read-write
n
0x0
0xFFFFFFFF
AI
Alpha Inverted
20
1
CM
Color mode
0
3
RBS
Red Blue Swap
21
1
DMAMUX1
DMA request multiplexer
DMAMUX
0x40020800
0x0
0x400
registers
n
DMAMUX1_OVR
DMAMUX Overrun interrupt
94
C0CR
C0CR
channel 0 configuration register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C10CR
C10CR
channel 10 configuration register
0x28
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C11CR
C11CR
channel 11 configuration register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C12CR
C12CR
channel 12 configuration register
0x30
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C13CR
C13CR
channel 13 configuration register
0x34
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C1CR
C1CR
channel 1 configuration register
0x4
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C2CR
C2CR
channel 2 configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C3CR
C3CR
channel 3 configuration register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C4CR
C4CR
channel 4 configuration register
0x10
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C5CR
C5CR
channel 5 configuration register
0x14
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C6CR
C6CR
channel 6 configuration register
0x18
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C7CR
C7CR
channel 7 configuration register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C8CR
C8CR
channel 8 configuration register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C9CR
C9CR
channel 9 configuration register
0x24
32
read-write
n
0x0
0xFFFFFFFF
DMAREQ_ID
DMA request identification
0
7
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
CFR
CFR
clear flag register
0x84
32
write-only
n
0x0
0xFFFFFFFF
CSOF0
Clear synchronization overrun event flag
0
1
CSOF1
Clear synchronization overrun event flag
1
1
CSOF10
Clear synchronization overrun event flag
10
1
CSOF11
Clear synchronization overrun event flag
11
1
CSOF12
Clear synchronization overrun event flag
12
1
CSOF13
Clear synchronization overrun event flag
13
1
CSOF2
Clear synchronization overrun event flag
2
1
CSOF3
Clear synchronization overrun event flag
3
1
CSOF4
Clear synchronization overrun event flag
4
1
CSOF5
Clear synchronization overrun event flag
5
1
CSOF6
Clear synchronization overrun event flag
6
1
CSOF7
Clear synchronization overrun event flag
7
1
CSOF8
Clear synchronization overrun event flag
8
1
CSOF9
Clear synchronization overrun event flag
9
1
CSR
CSR
channel status register
0x80
32
read-only
n
0x0
0xFFFFFFFF
SOF0
Synchronization overrun event flag
0
1
SOF1
Synchronization overrun event flag
1
1
SOF10
Synchronization overrun event flag
10
1
SOF11
Synchronization overrun event flag
11
1
SOF12
Synchronization overrun event flag
12
1
SOF13
Synchronization overrun event flag
13
1
SOF2
Synchronization overrun event flag
2
1
SOF3
Synchronization overrun event flag
3
1
SOF4
Synchronization overrun event flag
4
1
SOF5
Synchronization overrun event flag
5
1
SOF6
Synchronization overrun event flag
6
1
SOF7
Synchronization overrun event flag
7
1
SOF8
Synchronization overrun event flag
8
1
SOF9
Synchronization overrun event flag
9
1
RG0CR
RG0CR
request generator channel 0 configuration register
0x100
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel 0 enable
16
1
GNBREQ
Number of DMA requests to be generated minus 1
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG1CR
RG1CR
request generator channel 1 configuration register
0x104
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel 1 enable
16
1
GNBREQ
Number of DMA requests to be generated minus 1
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG2CR
RG2CR
request generator channel 2 configuration register
0x108
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel 2 enable
16
1
GNBREQ
Number of DMA requests to be generated minus 1
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG3CR
RG3CR
request generator channel 3 configuration register
0x10C
32
read-write
n
0x0
0xFFFFFFFF
GE
DMA request generator channel 3 enable
16
1
GNBREQ
Number of DMA requests to be generated minus 1
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RGCFR
RGCFR
request generator interrupt clear flag register
0x144
32
write-only
n
0x0
0xFFFFFFFF
COF0
Clear trigger overrun event flag
0
1
COF1
Clear trigger overrun event flag
1
1
COF2
Clear trigger overrun event flag
2
1
COF3
Clear trigger overrun event flag
3
1
RGSR
RGSR
request generator interrupt status register
0x140
32
read-only
n
0x0
0xFFFFFFFF
OF0
Trigger overrun event flag
0
1
OF1
Trigger overrun event flag
1
1
OF2
Trigger overrun event flag
2
1
OF3
Trigger overrun event flag
3
1
EXTI
External interrupt/event controller
EXTI
0x40010400
0x0
0x400
registers
n
PVD_PVM
PVD through EXTI line detection
1
EXTI0
EXTI Line 0 interrupt
6
EXTI1
EXTI Line 1 interrupt
7
EXTI2
EXTI Line 2 interrupt
8
EXTI3
EXTI Line 3 interrupt
9
EXTI4
EXTI Line 4 interrupt
10
EXTI9_5
EXTI Line5 to Line9 interrupts
23
EXTI15_10
EXTI Lines 10 to 15 interrupts
40
EMR1
EMR1
Event mask register
0x4
32
read-write
n
0x0
0xFFFFFFFF
MR0
Event Mask on line 0
0
1
MR1
Event Mask on line 1
1
1
MR10
Event Mask on line 10
10
1
MR11
Event Mask on line 11
11
1
MR12
Event Mask on line 12
12
1
MR13
Event Mask on line 13
13
1
MR14
Event Mask on line 14
14
1
MR15
Event Mask on line 15
15
1
MR16
Event Mask on line 16
16
1
MR17
Event Mask on line 17
17
1
MR18
Event Mask on line 18
18
1
MR19
Event Mask on line 19
19
1
MR2
Event Mask on line 2
2
1
MR20
Event Mask on line 20
20
1
MR21
Event Mask on line 21
21
1
MR22
Event Mask on line 22
22
1
MR23
Event Mask on line 23
23
1
MR24
Event Mask on line 24
24
1
MR25
Event Mask on line 25
25
1
MR26
Event Mask on line 26
26
1
MR27
Event Mask on line 27
27
1
MR28
Event Mask on line 28
28
1
MR29
Event Mask on line 29
29
1
MR3
Event Mask on line 3
3
1
MR30
Event Mask on line 30
30
1
MR31
Event Mask on line 31
31
1
MR4
Event Mask on line 4
4
1
MR5
Event Mask on line 5
5
1
MR6
Event Mask on line 6
6
1
MR7
Event Mask on line 7
7
1
MR8
Event Mask on line 8
8
1
MR9
Event Mask on line 9
9
1
EMR2
EMR2
Event mask register
0x24
32
read-write
n
0x0
0xFFFFFFFF
MR32
Event mask on external/internal line 32
0
1
MR33
Event mask on external/internal line 33
1
1
MR34
Event mask on external/internal line 34
2
1
MR35
Event mask on external/internal line 35
3
1
MR36
Event mask on external/internal line 36
4
1
MR37
Event mask on external/internal line 37
5
1
MR38
Event mask on external/internal line 38
6
1
MR39
Event mask on external/internal line 39
7
1
FTSR1
FTSR1
Falling Trigger selection register
0xC
32
read-write
n
0x0
0xFFFFFFFF
TR0
Falling trigger event configuration of line 0
0
1
TR1
Falling trigger event configuration of line 1
1
1
TR10
Falling trigger event configuration of line 10
10
1
TR11
Falling trigger event configuration of line 11
11
1
TR12
Falling trigger event configuration of line 12
12
1
TR13
Falling trigger event configuration of line 13
13
1
TR14
Falling trigger event configuration of line 14
14
1
TR15
Falling trigger event configuration of line 15
15
1
TR16
Falling trigger event configuration of line 16
16
1
TR18
Falling trigger event configuration of line 18
18
1
TR19
Falling trigger event configuration of line 19
19
1
TR2
Falling trigger event configuration of line 2
2
1
TR20
Falling trigger event configuration of line 20
20
1
TR21
Falling trigger event configuration of line 21
21
1
TR22
Falling trigger event configuration of line 22
22
1
TR3
Falling trigger event configuration of line 3
3
1
TR4
Falling trigger event configuration of line 4
4
1
TR5
Falling trigger event configuration of line 5
5
1
TR6
Falling trigger event configuration of line 6
6
1
TR7
Falling trigger event configuration of line 7
7
1
TR8
Falling trigger event configuration of line 8
8
1
TR9
Falling trigger event configuration of line 9
9
1
FTSR2
FTSR2
Falling Trigger selection register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
FT35
Falling trigger event configuration bit of line 35
3
1
FT36
Falling trigger event configuration bit of line 36
4
1
FT37
Falling trigger event configuration bit of line 37
5
1
FT38
Falling trigger event configuration bit of line 38
6
1
IMR1
IMR1
Interrupt mask register
0x0
32
read-write
n
0xFF820000
0xFFFFFFFF
MR0
Interrupt Mask on line 0
0
1
MR1
Interrupt Mask on line 1
1
1
MR10
Interrupt Mask on line 10
10
1
MR11
Interrupt Mask on line 11
11
1
MR12
Interrupt Mask on line 12
12
1
MR13
Interrupt Mask on line 13
13
1
MR14
Interrupt Mask on line 14
14
1
MR15
Interrupt Mask on line 15
15
1
MR16
Interrupt Mask on line 16
16
1
MR17
Interrupt Mask on line 17
17
1
MR18
Interrupt Mask on line 18
18
1
MR19
Interrupt Mask on line 19
19
1
MR2
Interrupt Mask on line 2
2
1
MR20
Interrupt Mask on line 20
20
1
MR21
Interrupt Mask on line 21
21
1
MR22
Interrupt Mask on line 22
22
1
MR23
Interrupt Mask on line 23
23
1
MR24
Interrupt Mask on line 24
24
1
MR25
Interrupt Mask on line 25
25
1
MR26
Interrupt Mask on line 26
26
1
MR27
Interrupt Mask on line 27
27
1
MR28
Interrupt Mask on line 28
28
1
MR29
Interrupt Mask on line 29
29
1
MR3
Interrupt Mask on line 3
3
1
MR30
Interrupt Mask on line 30
30
1
MR31
Interrupt Mask on line 31
31
1
MR4
Interrupt Mask on line 4
4
1
MR5
Interrupt Mask on line 5
5
1
MR6
Interrupt Mask on line 6
6
1
MR7
Interrupt Mask on line 7
7
1
MR8
Interrupt Mask on line 8
8
1
MR9
Interrupt Mask on line 9
9
1
IMR2
IMR2
Interrupt mask register
0x20
32
read-write
n
0xFFFFFF87
0xFFFFFFFF
MR32
Interrupt Mask on external/internal line 32
0
1
MR33
Interrupt Mask on external/internal line 33
1
1
MR34
Interrupt Mask on external/internal line 34
2
1
MR35
Interrupt Mask on external/internal line 35
3
1
MR36
Interrupt Mask on external/internal line 36
4
1
MR37
Interrupt Mask on external/internal line 37
5
1
MR38
Interrupt Mask on external/internal line 38
6
1
MR39
Interrupt Mask on external/internal line 39
7
1
PR1
PR1
Pending register
0x14
32
read-write
n
0x0
0xFFFFFFFF
PR0
Pending bit 0
0
1
PR1
Pending bit 1
1
1
PR10
Pending bit 10
10
1
PR11
Pending bit 11
11
1
PR12
Pending bit 12
12
1
PR13
Pending bit 13
13
1
PR14
Pending bit 14
14
1
PR15
Pending bit 15
15
1
PR16
Pending bit 16
16
1
PR18
Pending bit 18
18
1
PR19
Pending bit 19
19
1
PR2
Pending bit 2
2
1
PR20
Pending bit 20
20
1
PR21
Pending bit 21
21
1
PR22
Pending bit 22
22
1
PR3
Pending bit 3
3
1
PR4
Pending bit 4
4
1
PR5
Pending bit 5
5
1
PR6
Pending bit 6
6
1
PR7
Pending bit 7
7
1
PR8
Pending bit 8
8
1
PR9
Pending bit 9
9
1
PR2
PR2
Pending register
0x34
32
read-write
n
0x0
0xFFFFFFFF
PIF35
Pending interrupt flag on line 35
3
1
PIF36
Pending interrupt flag on line 36
4
1
PIF37
Pending interrupt flag on line 37
5
1
PIF38
Pending interrupt flag on line 38
6
1
RTSR1
RTSR1
Rising Trigger selection register
0x8
32
read-write
n
0x0
0xFFFFFFFF
TR0
Rising trigger event configuration of line 0
0
1
TR1
Rising trigger event configuration of line 1
1
1
TR10
Rising trigger event configuration of line 10
10
1
TR11
Rising trigger event configuration of line 11
11
1
TR12
Rising trigger event configuration of line 12
12
1
TR13
Rising trigger event configuration of line 13
13
1
TR14
Rising trigger event configuration of line 14
14
1
TR15
Rising trigger event configuration of line 15
15
1
TR16
Rising trigger event configuration of line 16
16
1
TR18
Rising trigger event configuration of line 18
18
1
TR19
Rising trigger event configuration of line 19
19
1
TR2
Rising trigger event configuration of line 2
2
1
TR20
Rising trigger event configuration of line 20
20
1
TR21
Rising trigger event configuration of line 21
21
1
TR22
Rising trigger event configuration of line 22
22
1
TR3
Rising trigger event configuration of line 3
3
1
TR4
Rising trigger event configuration of line 4
4
1
TR5
Rising trigger event configuration of line 5
5
1
TR6
Rising trigger event configuration of line 6
6
1
TR7
Rising trigger event configuration of line 7
7
1
TR8
Rising trigger event configuration of line 8
8
1
TR9
Rising trigger event configuration of line 9
9
1
RTSR2
RTSR2
Rising Trigger selection register
0x28
32
read-write
n
0x0
0xFFFFFFFF
RT35
Rising trigger event configuration bit of line 35
3
1
RT36
Rising trigger event configuration bit of line 36
4
1
RT37
Rising trigger event configuration bit of line 37
5
1
RT38
Rising trigger event configuration bit of line 38
6
1
SWIER1
SWIER1
Software interrupt event register
0x10
32
read-write
n
0x0
0xFFFFFFFF
SWIER0
Software Interrupt on line 0
0
1
SWIER1
Software Interrupt on line 1
1
1
SWIER10
Software Interrupt on line 10
10
1
SWIER11
Software Interrupt on line 11
11
1
SWIER12
Software Interrupt on line 12
12
1
SWIER13
Software Interrupt on line 13
13
1
SWIER14
Software Interrupt on line 14
14
1
SWIER15
Software Interrupt on line 15
15
1
SWIER16
Software Interrupt on line 16
16
1
SWIER18
Software Interrupt on line 18
18
1
SWIER19
Software Interrupt on line 19
19
1
SWIER2
Software Interrupt on line 2
2
1
SWIER20
Software Interrupt on line 20
20
1
SWIER21
Software Interrupt on line 21
21
1
SWIER22
Software Interrupt on line 22
22
1
SWIER3
Software Interrupt on line 3
3
1
SWIER4
Software Interrupt on line 4
4
1
SWIER5
Software Interrupt on line 5
5
1
SWIER6
Software Interrupt on line 6
6
1
SWIER7
Software Interrupt on line 7
7
1
SWIER8
Software Interrupt on line 8
8
1
SWIER9
Software Interrupt on line 9
9
1
SWIER2
SWIER2
Software interrupt event register
0x30
32
read-write
n
0x0
0xFFFFFFFF
SWI35
Software interrupt on line 35
3
1
SWI36
Software interrupt on line 36
4
1
SWI37
Software interrupt on line 37
5
1
SWI38
Software interrupt on line 38
6
1
FIREWALL
Firewall
Firewall
0x40011C00
0x0
0x400
registers
n
CR
CR
Configuration register
0x20
32
read-write
n
0x0
0xFFFFFFFF
FPA
Firewall pre alarm
0
1
VDE
Volatile data execution
2
1
VDS
Volatile data shared
1
1
CSL
CSL
Code segment length
0x4
32
read-write
n
0x0
0xFFFFFFFF
LENG
code segment length
8
14
CSSA
CSSA
Code segment start address
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADD
code segment start address
8
16
NVDSL
NVDSL
Non-volatile data segment length
0xC
32
read-write
n
0x0
0xFFFFFFFF
LENG
Non-volatile data segment length
8
14
NVDSSA
NVDSSA
Non-volatile data segment start address
0x8
32
read-write
n
0x0
0xFFFFFFFF
ADD
Non-volatile data segment start address
8
16
VDSL
VDSL
Volatile data segment length
0x14
32
read-write
n
0x0
0xFFFFFFFF
LENG
Non-volatile data segment length
6
10
VDSSA
VDSSA
Volatile data segment start address
0x10
32
read-write
n
0x0
0xFFFFFFFF
ADD
Volatile data segment start address
6
10
FLASH
Flash
Flash
0x40022000
0x0
0x400
registers
n
FLASH
Flash global interrupt
4
ACR
ACR
Access control register
0x0
32
read-write
n
0x600
0xFFFFFFFF
DCEN
Data cache enable
10
1
DCRST
Data cache reset
12
1
ICEN
Instruction cache enable
9
1
ICRST
Instruction cache reset
11
1
LATENCY
Latency
0
3
PRFTEN
Prefetch enable
8
1
RUN_PD
Flash Power-down mode during Low-power run mode
13
1
SLEEP_PD
Flash Power-down mode during Low-power sleep mode
14
1
CR
CR
Flash control register
0x14
32
read-write
n
0xC0000000
0xFFFFFFFF
BKER
Bank erase
11
1
EOPIE
End of operation interrupt enable
24
1
ERRIE
Error interrupt enable
25
1
FSTPG
Fast programming
18
1
LOCK
FLASH_CR Lock
31
1
MER1
Bank 1 Mass erase
2
1
MER2
Bank 2 Mass erase
15
1
OBL_LAUNCH
Force the option byte loading
27
1
OPTLOCK
Options Lock
30
1
OPTSTRT
Options modification start
17
1
PER
Page erase
1
1
PG
Programming
0
1
PNB
Page number
3
8
RDERRIE
PCROP read error interrupt enable
26
1
START
Start
16
1
ECCR
ECCR
Flash ECC register
0x18
32
read-write
n
0x0
0xFFFFFFFF
ADDR_ECC
ECC fail address
0
19
read-only
BK_ECC
ECC fail bank
19
1
read-only
ECCC
ECC correction
30
1
read-write
ECCD
ECC detection
31
1
read-write
ECCIE
ECC correction interrupt enable
24
1
read-write
SYSF_ECC
System Flash ECC fail
20
1
read-only
KEYR
KEYR
Flash key register
0x8
32
write-only
n
0x0
0xFFFFFFFF
KEYR
KEYR
0
32
OPTKEYR
OPTKEYR
Option byte key register
0xC
32
write-only
n
0x0
0xFFFFFFFF
OPTKEYR
Option byte key
0
32
OPTR
OPTR
Flash option register
0x20
32
read-write
n
0xF0000000
0xFFFFFFFF
BFB2
Dual-bank boot
20
1
BOR_LEV
BOR reset Level
8
3
DUALBANK
Dual-Bank on 512 KB or 256 KB Flash memory devices
21
1
IDWG_SW
Independent watchdog selection
16
1
IWDG_STDBY
Independent watchdog counter freeze in Standby mode
18
1
IWDG_STOP
Independent watchdog counter freeze in Stop mode
17
1
nBOOT1
Boot configuration
23
1
nRST_STDBY
nRST_STDBY
13
1
nRST_STOP
nRST_STOP
12
1
RDP
Read protection level
0
8
SRAM2_PE
SRAM2 parity check enable
24
1
SRAM2_RST
SRAM2 Erase when system reset
25
1
WWDG_SW
Window watchdog selection
19
1
PCROP1ER
PCROP1ER
Flash Bank 1 PCROP End address register
0x28
32
read-write
n
0xFFF0000
0xFFFFFFFF
PCROP1_END
Bank 1 PCROP area end offset
0
16
PCROP_RDP
PCROP area preserved when RDP level decreased
31
1
PCROP1SR
PCROP1SR
Flash Bank 1 PCROP Start address register
0x24
32
read-write
n
0xFFFF0000
0xFFFFFFFF
PCROP1_STRT
Bank 1 PCROP area start offset
0
16
PCROP2ER
PCROP2ER
Flash Bank 2 PCROP End address register
0x48
32
read-write
n
0xFFFF0000
0xFFFFFFFF
PCROP2_END
Bank 2 PCROP area end offset
0
16
PCROP2SR
PCROP2SR
Flash Bank 2 PCROP Start address register
0x44
32
read-write
n
0xFFFF0000
0xFFFFFFFF
PCROP2_STRT
Bank 2 PCROP area start offset
0
16
PDKEYR
PDKEYR
Power down key register
0x4
32
write-only
n
0x0
0xFFFFFFFF
PDKEYR
RUN_PD in FLASH_ACR key
0
32
SR
SR
Status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BSY
Busy
16
1
read-only
EOP
End of operation
0
1
read-write
FASTERR
Fast programming error
9
1
read-write
MISERR
Fast programming data miss error
8
1
read-write
OPERR
Operation error
1
1
read-write
OPTVERR
Option validity error
15
1
read-write
PGAERR
Programming alignment error
5
1
read-write
PGSERR
Programming sequence error
7
1
read-write
PROGERR
Programming error
3
1
read-write
RDERR
PCROP read error
14
1
read-write
SIZERR
Size error
6
1
read-write
WRPERR
Write protected error
4
1
read-write
WRP1AR
WRP1AR
Flash Bank 1 WRP area A address register
0x2C
32
read-write
n
0xFF00FF00
0xFFFFFFFF
WRP1A_END
Bank 1 WRP first area A end offset
16
8
WRP1A_STRT
Bank 1 WRP first area start offset
0
8
WRP1BR
WRP1BR
Flash Bank 1 WRP area B address register
0x30
32
read-write
n
0xFF00FF00
0xFFFFFFFF
WRP1B_END
Bank 1 WRP second area B end offset
16
8
WRP1B_STRT
Bank 1 WRP second area B start offset
0
8
WRP2AR
WRP2AR
Flash Bank 2 WRP area A address register
0x4C
32
read-write
n
0xFF00FF00
0xFFFFFFFF
WRP2A_END
Bank 2 WRP first area A end offset
16
8
WRP2A_STRT
Bank 2 WRP first area A start offset
0
8
WRP2BR
WRP2BR
Flash Bank 2 WRP area B address register
0x50
32
read-write
n
0xFF00FF00
0xFFFFFFFF
WRP2B_END
Bank 2 WRP second area B end offset
16
8
WRP2B_STRT
Bank 2 WRP second area B start offset
0
8
FMC
Flexible memory controller
FMC
0xA0000000
0x0
0x400
registers
n
FMC
FMC global Interrupt
48
FPU
Floating point interrupt
81
BCR1
BCR1
SRAM/NOR-Flash chip-select control register 1
0x0
32
read-write
n
0x30D0
0xFFFFFFFF
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
CCLKEN
CCLKEN
20
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WFDIS
Write FIFO Disable
21
1
WREN
WREN
12
1
BCR2
BCR2
SRAM/NOR-Flash chip-select control register 2
0x8
32
read-write
n
0x30D0
0xFFFFFFFF
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR3
BCR3
SRAM/NOR-Flash chip-select control register 3
0x10
32
read-write
n
0x30D0
0xFFFFFFFF
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BCR4
BCR4
SRAM/NOR-Flash chip-select control register 4
0x18
32
read-write
n
0x30D0
0xFFFFFFFF
ASYNCWAIT
ASYNCWAIT
15
1
BURSTEN
BURSTEN
8
1
CBURSTRW
CBURSTRW
19
1
EXTMOD
EXTMOD
14
1
FACCEN
FACCEN
6
1
MBKEN
MBKEN
0
1
MTYP
MTYP
2
2
MUXEN
MUXEN
1
1
MWID
MWID
4
2
WAITCFG
WAITCFG
11
1
WAITEN
WAITEN
13
1
WAITPOL
WAITPOL
9
1
WRAPMOD
WRAPMOD
10
1
WREN
WREN
12
1
BTR1
BTR1
SRAM/NOR-Flash chip-select timing register 1
0x4
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR2
BTR2
SRAM/NOR-Flash chip-select timing register 2
0xC
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR3
BTR3
SRAM/NOR-Flash chip-select timing register 3
0x14
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BTR4
BTR4
SRAM/NOR-Flash chip-select timing register 4
0x1C
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
BUSTURN
BUSTURN
16
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR1
BWTR1
SRAM/NOR-Flash write timing registers 1
0x104
32
read-write
n
0xFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR2
BWTR2
SRAM/NOR-Flash write timing registers 2
0x10C
32
read-write
n
0xFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR3
BWTR3
SRAM/NOR-Flash write timing registers 3
0x114
32
read-write
n
0xFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
BWTR4
BWTR4
SRAM/NOR-Flash write timing registers 4
0x11C
32
read-write
n
0xFFFFFFF
0xFFFFFFFF
ACCMOD
ACCMOD
28
2
ADDHLD
ADDHLD
4
4
ADDSET
ADDSET
0
4
CLKDIV
CLKDIV
20
4
DATAST
DATAST
8
8
DATLAT
DATLAT
24
4
ECCR
ECCR
ECC result register 3
0x94
32
read-only
n
0x0
0xFFFFFFFF
ECCx
ECCx
0
32
PATT
PATT
Attribute memory space timing register 3
0x8C
32
read-write
n
0xFCFCFCFC
0xFFFFFFFF
ATTHIZx
ATTHIZx
24
8
ATTHOLDx
ATTHOLDx
16
8
ATTSETx
ATTSETx
0
8
ATTWAITx
ATTWAITx
8
8
PCR
PCR
PC Card/NAND Flash control register 3
0x80
32
read-write
n
0x18
0xFFFFFFFF
ECCEN
ECCEN
6
1
ECCPS
ECCPS
17
3
PBKEN
PBKEN
2
1
PTYP
PTYP
3
1
PWAITEN
PWAITEN
1
1
PWID
PWID
4
2
TAR
TAR
13
4
TCLR
TCLR
9
4
PMEM
PMEM
Common memory space timing register 3
0x88
32
read-write
n
0xFCFCFCFC
0xFFFFFFFF
MEMHIZx
MEMHIZx
24
8
MEMHOLDx
MEMHOLDx
16
8
MEMSETx
MEMSETx
0
8
MEMWAITx
MEMWAITx
8
8
SR
SR
FIFO status and interrupt register 3
0x84
32
read-write
n
0x40
0xFFFFFFFF
FEMPT
FEMPT
6
1
read-only
IFEN
IFEN
5
1
read-write
IFS
IFS
2
1
read-write
ILEN
ILEN
4
1
read-write
ILS
ILS
1
1
read-write
IREN
IREN
3
1
read-write
IRS
IRS
0
1
read-write
FPU
Floting point unit
FPU
0xE000EF34
0x0
0xD
registers
n
FPU
Floating point interrupt
81
FPU
Floating point interrupt
81
FPCAR
FPCAR
Floating-point context address register
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADDRESS
Location of unpopulated floating-point
3
29
FPCCR
FPCCR
Floating-point context control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ASPEN
ASPEN
31
1
BFRDY
BFRDY
6
1
HFRDY
HFRDY
4
1
LSPACT
LSPACT
0
1
LSPEN
LSPEN
30
1
MMRDY
MMRDY
5
1
MONRDY
MONRDY
8
1
THREAD
THREAD
3
1
USER
USER
1
1
FPSCR
FPSCR
Floating-point status control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
AHP
Alternative half-precision control bit
26
1
C
Carry condition code flag
29
1
DN
Default NaN mode control bit
25
1
DZC
Division by zero cumulative exception bit.
1
1
FZ
Flush-to-zero mode control bit:
24
1
IDC
Input denormal cumulative exception bit.
7
1
IOC
Invalid operation cumulative exception bit
0
1
IXC
Inexact cumulative exception bit
4
1
N
Negative condition code flag
31
1
OFC
Overflow cumulative exception bit
2
1
RMode
Rounding Mode control field
22
2
UFC
Underflow cumulative exception bit
3
1
V
Overflow condition code flag
28
1
Z
Zero condition code flag
30
1
FPU_CPACR
Floating point unit CPACR
FPU
0xE000ED88
0x0
0x5
registers
n
CPACR
CPACR
Coprocessor access control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CP
CP
20
4
GPIOA
General-purpose I/Os
GPIO
0x48000000
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0xA8000000
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x64000000
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x48000400
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x280
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0xC0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x100
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x48000800
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOD
General-purpose I/Os
GPIO
0x48000C00
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOE
General-purpose I/Os
GPIO
0x48001000
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOF
General-purpose I/Os
GPIO
0x48001400
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOG
General-purpose I/Os
GPIO
0x48001800
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOH
General-purpose I/Os
GPIO
0x48001C00
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
ASCR
ASCR
GPIO port analog switch control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ASC0
Port analog switch control
0
1
ASC1
Port analog switch control
1
1
ASC10
Port analog switch control
10
1
ASC11
Port analog switch control
11
1
ASC12
Port analog switch control
12
1
ASC13
Port analog switch control
13
1
ASC14
Port analog switch control
14
1
ASC15
Port analog switch control
15
1
ASC2
Port analog switch control
2
1
ASC3
Port analog switch control
3
1
ASC4
Port analog switch control
4
1
ASC5
Port analog switch control
5
1
ASC6
Port analog switch control
6
1
ASC7
Port analog switch control
7
1
ASC8
Port analog switch control
8
1
ASC9
Port analog switch control
9
1
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOI
General-purpose I/Os
GPIO
0x48002000
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0xFFFFFFFF
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0xFFFFFFFF
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0xFFFFFFFF
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0xFFFFFFFF
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0xFFFFFFFF
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0xFFFFFFFF
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0xFFFFFFFF
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0xFFFFFFFF
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0xFFFFFFFF
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
HASH
Hash processor
HASH
0x50060400
0x0
0x400
registers
n
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ALGO0
Algorithm selection
7
1
read-write
ALGO1
ALGO
18
1
read-write
DATATYPE
Data type selection
4
2
read-write
DINNE
DIN not empty
12
1
read-only
DMAE
DMA enable
3
1
read-write
INIT
Initialize message digest calculation
2
1
write-only
LKEY
Long key selection
16
1
read-write
MDMAT
Multiple DMA Transfers
13
1
read-write
MODE
Mode selection
6
1
read-write
NBW
Number of words already pushed
8
4
read-only
CSR0
CSR0
context swap registers
0xF8
32
read-write
n
0x0
0xFFFFFFFF
CSR0
CSR0
0
32
CSR1
CSR1
context swap registers
0xFC
32
read-write
n
0x0
0xFFFFFFFF
CSR1
CSR1
0
32
CSR10
CSR10
context swap registers
0x120
32
read-write
n
0x0
0xFFFFFFFF
CSR10
CSR10
0
32
CSR11
CSR11
context swap registers
0x124
32
read-write
n
0x0
0xFFFFFFFF
CSR11
CSR11
0
32
CSR12
CSR12
context swap registers
0x128
32
read-write
n
0x0
0xFFFFFFFF
CSR12
CSR12
0
32
CSR13
CSR13
context swap registers
0x12C
32
read-write
n
0x0
0xFFFFFFFF
CSR13
CSR13
0
32
CSR14
CSR14
context swap registers
0x130
32
read-write
n
0x0
0xFFFFFFFF
CSR14
CSR14
0
32
CSR15
CSR15
context swap registers
0x134
32
read-write
n
0x0
0xFFFFFFFF
CSR15
CSR15
0
32
CSR16
CSR16
context swap registers
0x138
32
read-write
n
0x0
0xFFFFFFFF
CSR16
CSR16
0
32
CSR17
CSR17
context swap registers
0x13C
32
read-write
n
0x0
0xFFFFFFFF
CSR17
CSR17
0
32
CSR18
CSR18
context swap registers
0x140
32
read-write
n
0x0
0xFFFFFFFF
CSR18
CSR18
0
32
CSR19
CSR19
context swap registers
0x144
32
read-write
n
0x0
0xFFFFFFFF
CSR19
CSR19
0
32
CSR2
CSR2
context swap registers
0x100
32
read-write
n
0x0
0xFFFFFFFF
CSR2
CSR2
0
32
CSR20
CSR20
context swap registers
0x148
32
read-write
n
0x0
0xFFFFFFFF
CSR20
CSR20
0
32
CSR21
CSR21
context swap registers
0x14C
32
read-write
n
0x0
0xFFFFFFFF
CSR21
CSR21
0
32
CSR22
CSR22
context swap registers
0x150
32
read-write
n
0x0
0xFFFFFFFF
CSR22
CSR22
0
32
CSR23
CSR23
context swap registers
0x154
32
read-write
n
0x0
0xFFFFFFFF
CSR23
CSR23
0
32
CSR24
CSR24
context swap registers
0x158
32
read-write
n
0x0
0xFFFFFFFF
CSR24
CSR24
0
32
CSR25
CSR25
context swap registers
0x15C
32
read-write
n
0x0
0xFFFFFFFF
CSR25
CSR25
0
32
CSR26
CSR26
context swap registers
0x160
32
read-write
n
0x0
0xFFFFFFFF
CSR26
CSR26
0
32
CSR27
CSR27
context swap registers
0x164
32
read-write
n
0x0
0xFFFFFFFF
CSR27
CSR27
0
32
CSR28
CSR28
context swap registers
0x168
32
read-write
n
0x0
0xFFFFFFFF
CSR28
CSR28
0
32
CSR29
CSR29
context swap registers
0x16C
32
read-write
n
0x0
0xFFFFFFFF
CSR29
CSR29
0
32
CSR3
CSR3
context swap registers
0x104
32
read-write
n
0x0
0xFFFFFFFF
CSR3
CSR3
0
32
CSR30
CSR30
context swap registers
0x170
32
read-write
n
0x0
0xFFFFFFFF
CSR30
CSR30
0
32
CSR31
CSR31
context swap registers
0x174
32
read-write
n
0x0
0xFFFFFFFF
CSR31
CSR31
0
32
CSR32
CSR32
context swap registers
0x178
32
read-write
n
0x0
0xFFFFFFFF
CSR32
CSR32
0
32
CSR33
CSR33
context swap registers
0x17C
32
read-write
n
0x0
0xFFFFFFFF
CSR33
CSR33
0
32
CSR34
CSR34
context swap registers
0x180
32
read-write
n
0x0
0xFFFFFFFF
CSR34
CSR34
0
32
CSR35
CSR35
context swap registers
0x184
32
read-write
n
0x0
0xFFFFFFFF
CSR35
CSR35
0
32
CSR36
CSR36
context swap registers
0x188
32
read-write
n
0x0
0xFFFFFFFF
CSR36
CSR36
0
32
CSR37
CSR37
context swap registers
0x18C
32
read-write
n
0x0
0xFFFFFFFF
CSR37
CSR37
0
32
CSR38
CSR38
context swap registers
0x190
32
read-write
n
0x0
0xFFFFFFFF
CSR38
CSR38
0
32
CSR39
CSR39
context swap registers
0x194
32
read-write
n
0x0
0xFFFFFFFF
CSR39
CSR39
0
32
CSR4
CSR4
context swap registers
0x108
32
read-write
n
0x0
0xFFFFFFFF
CSR4
CSR4
0
32
CSR40
CSR40
context swap registers
0x198
32
read-write
n
0x0
0xFFFFFFFF
CSR40
CSR40
0
32
CSR41
CSR41
context swap registers
0x19C
32
read-write
n
0x0
0xFFFFFFFF
CSR41
CSR41
0
32
CSR42
CSR42
context swap registers
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
CSR42
CSR42
0
32
CSR43
CSR43
context swap registers
0x1A4
32
read-write
n
0x0
0xFFFFFFFF
CSR43
CSR43
0
32
CSR44
CSR44
context swap registers
0x1A8
32
read-write
n
0x0
0xFFFFFFFF
CSR44
CSR44
0
32
CSR45
CSR45
context swap registers
0x1AC
32
read-write
n
0x0
0xFFFFFFFF
CSR45
CSR45
0
32
CSR46
CSR46
context swap registers
0x1B0
32
read-write
n
0x0
0xFFFFFFFF
CSR46
CSR46
0
32
CSR47
CSR47
context swap registers
0x1B4
32
read-write
n
0x0
0xFFFFFFFF
CSR47
CSR47
0
32
CSR48
CSR48
context swap registers
0x1B8
32
read-write
n
0x0
0xFFFFFFFF
CSR48
CSR48
0
32
CSR49
CSR49
context swap registers
0x1BC
32
read-write
n
0x0
0xFFFFFFFF
CSR49
CSR49
0
32
CSR5
CSR5
context swap registers
0x10C
32
read-write
n
0x0
0xFFFFFFFF
CSR5
CSR5
0
32
CSR50
CSR50
context swap registers
0x1C0
32
read-write
n
0x0
0xFFFFFFFF
CSR50
CSR50
0
32
CSR51
CSR51
context swap registers
0x1C4
32
read-write
n
0x0
0xFFFFFFFF
CSR51
CSR51
0
32
CSR52
CSR52
context swap registers
0x1C8
32
read-write
n
0x0
0xFFFFFFFF
CSR52
CSR52
0
32
CSR53
CSR53
context swap registers
0x1CC
32
read-write
n
0x0
0xFFFFFFFF
CSR53
CSR53
0
32
CSR6
CSR6
context swap registers
0x110
32
read-write
n
0x0
0xFFFFFFFF
CSR6
CSR6
0
32
CSR7
CSR7
context swap registers
0x114
32
read-write
n
0x0
0xFFFFFFFF
CSR7
CSR7
0
32
CSR8
CSR8
context swap registers
0x118
32
read-write
n
0x0
0xFFFFFFFF
CSR8
CSR8
0
32
CSR9
CSR9
context swap registers
0x11C
32
read-write
n
0x0
0xFFFFFFFF
CSR9
CSR9
0
32
DIN
DIN
data input register
0x4
32
read-write
n
0x0
0xFFFFFFFF
DATAIN
Data input
0
32
HR0
HR0
digest registers
0xC
32
read-only
n
0x0
0xFFFFFFFF
H0
H0
0
32
HR1
HASH_HR1
read-only
0x314
32
read-only
n
0x0
0xFFFFFFFF
H1
H1
0
32
HR2
HASH_HR2
read-only
0x318
32
read-only
n
0x0
0xFFFFFFFF
H2
H2
0
32
HR3
HASH_HR3
read-only
0x31C
32
read-only
n
0x0
0xFFFFFFFF
H3
H3
0
32
HR4
HASH_HR4
read-only
0x320
32
read-only
n
0x0
0xFFFFFFFF
H4
H4
0
32
HR5
HASH_HR5
read-only
0x324
32
read-only
n
0x0
0xFFFFFFFF
H5
H5
0
32
HR6
HASH_HR6
read-only
0x328
32
read-only
n
0x0
0xFFFFFFFF
H6
H6
0
32
HR7
HASH_HR7
read-only
0x32C
32
read-only
n
0x0
0xFFFFFFFF
H7
H7
0
32
IMR
IMR
interrupt enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DCIE
Digest calculation completion interrupt enable
1
1
DINIE
Data input interrupt enable
0
1
SR
SR
status register
0x24
32
read-write
n
0x1
0xFFFFFFFF
BUSY
Busy bit
3
1
read-only
DCIS
Digest calculation completion interrupt status
1
1
read-write
DINIS
Data input interrupt status
0
1
read-write
DMAS
DMA Status
2
1
read-only
STR
STR
start register
0x8
32
read-write
n
0x0
0xFFFFFFFF
DCAL
Digest calculation
8
1
write-only
NBLW
Number of valid bits in the last word of the message
0
5
read-write
I2C1
Inter-integrated circuit
I2C
0x40005400
0x0
0x400
registers
n
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
I2C2
Inter-integrated circuit
I2C
0x40005800
0x0
0x400
registers
n
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
I2C3
Inter-integrated circuit
I2C
0x40005C00
0x0
0x400
registers
n
I2C3_EV
I2C3 event interrupt
72
I2C3_ER
I2C3 error interrupt
73
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
I2C4
Inter-integrated circuit
I2C
0x40008400
0x0
0x400
registers
n
I2C4_ER
I2C4 error interrupt
83
I2C4_EV
I2C4 event interrupt
84
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0xFFFFFFFF
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0xFFFFFFFF
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0xFFFFFFFF
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TXDATA
8-bit transmit data
0
8
IWDG
Independent watchdog
IWDG
0x40003000
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0xFFFFFFFF
KEY
Key value (write only, read 0x0000)
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0xFFFFFFFF
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0xFFF
0xFFFFFFFF
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0xFFFFFFFF
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
WVU
Watchdog counter window value update
2
1
WINR
WINR
Window register
0x10
32
read-write
n
0xFFF
0xFFFFFFFF
WIN
Watchdog counter window value
0
12
LPTIM1
Low power timer
LPTIM
0x40007C00
0x0
0x400
registers
n
LPTIM1
LP TIM1 interrupt
65
ARR
ARR
Autoreload Register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ARR
Auto reload value
0
16
CFGR
CFGR
Configuration Register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CKFLT
Configurable digital filter for external clock
3
2
CKPOL
Clock Polarity
1
2
CKSEL
Clock selector
0
1
COUNTMODE
counter mode enabled
23
1
ENC
Encoder mode enable
24
1
PRELOAD
Registers update mode
22
1
PRESC
Clock prescaler
9
3
TIMOUT
Timeout enable
19
1
TRGFLT
Configurable digital filter for trigger
6
2
TRIGEN
Trigger enable and polarity
17
2
TRIGSEL
Trigger selector
13
3
WAVE
Waveform shape
20
1
WAVPOL
Waveform shape polarity
21
1
CMP
CMP
Compare Register
0x14
32
read-write
n
0x0
0xFFFFFFFF
CMP
Compare value
0
16
CNT
CNT
Counter Register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
CR
CR
Control Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CNTSTRT
Timer start in continuous mode
2
1
ENABLE
LPTIM Enable
0
1
SNGSTRT
LPTIM start in single mode
1
1
ICR
ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0xFFFFFFFF
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0xFFFFFFFF
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
UP
Counter direction change down to up
5
1
LPTIM2
Low power timer
LPTIM
0x40009400
0x0
0x400
registers
n
LPTIM2
LP TIM2 interrupt
66
ARR
ARR
Autoreload Register
0x18
32
read-write
n
0x1
0xFFFFFFFF
ARR
Auto reload value
0
16
CFGR
CFGR
Configuration Register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CKFLT
Configurable digital filter for external clock
3
2
CKPOL
Clock Polarity
1
2
CKSEL
Clock selector
0
1
COUNTMODE
counter mode enabled
23
1
ENC
Encoder mode enable
24
1
PRELOAD
Registers update mode
22
1
PRESC
Clock prescaler
9
3
TIMOUT
Timeout enable
19
1
TRGFLT
Configurable digital filter for trigger
6
2
TRIGEN
Trigger enable and polarity
17
2
TRIGSEL
Trigger selector
13
3
WAVE
Waveform shape
20
1
WAVPOL
Waveform shape polarity
21
1
CMP
CMP
Compare Register
0x14
32
read-write
n
0x0
0xFFFFFFFF
CMP
Compare value
0
16
CNT
CNT
Counter Register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
16
CR
CR
Control Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CNTSTRT
Timer start in continuous mode
2
1
ENABLE
LPTIM Enable
0
1
SNGSTRT
LPTIM start in single mode
1
1
ICR
ICR
Interrupt Clear Register
0x4
32
write-only
n
0x0
0xFFFFFFFF
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
Interrupt Enable Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
Interrupt and Status Register
0x0
32
read-only
n
0x0
0xFFFFFFFF
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
UP
Counter direction change down to up
5
1
LPUART1
Universal synchronous asynchronous receiver transmitter
USART
0x40008000
0x0
0x400
registers
n
LPUART1
LPUART1 global interrupt
70
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR
BRR
0
20
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
MSBFIRST
Most significant bit first
19
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt and status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
FE
FE
1
1
IDLE
IDLE
4
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RWU
RWU
19
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
LTCD
Liquid crystal display controller
LCD
0x40016800
0x0
0x400
registers
n
LCD_TFT
LTDC global interrupt
91
LCD_TFT_ER
LTDC global error interrupt
92
AWCR
AWCR
LTDC Active Width Configuration Register
0x10
32
read-write
n
0x0
0xFFFFFFFF
AAH
Accumulated Active Height (in units of horizontal scan line)
0
11
AAW
Accumulated Active Width (in units of pixel clock period)
16
12
BCCR
BCCR
LTDC Background Color Configuration Register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
BCBLUE
Background Color Blue value
0
8
BCGREEN
Background Color Green value
8
8
BCRED
Background Color Red value
16
8
BPCR
BPCR
LTDC Back Porch Configuration Register
0xC
32
read-write
n
0x0
0xFFFFFFFF
AHBP
Accumulated Horizontal back porch (in units of pixel clock period)
16
12
AVBP
Accumulated Vertical back porch (in units of horizontal scan line)
0
11
CDSR
CDSR
LTDC Current Display Status Register
0x48
32
read-only
n
0xF
0xFFFFFFFF
HDES
Horizontal Data Enable display Status
1
1
HSYNCS
Horizontal Synchronization display Status
3
1
VDES
Vertical Data Enable display Status
0
1
VSYNCS
Vertical Synchronization display Status
2
1
CPSR
CPSR
LTDC Current Position Status Register
0x44
32
read-only
n
0x0
0xFFFFFFFF
CXPOS
Current X Position
16
16
CYPOS
Current Y Position
0
16
GCR
GCR
LTDC Global Control Register
0x18
32
read-write
n
0x2220
0xFFFFFFFF
DBW
Dither Blue Width
4
3
read-only
DEN
Dither Enable
16
1
read-write
DEPOL
Not Data Enable Polarity
29
1
read-write
DGW
Dither Green Width
8
3
read-only
DRW
Dither Red Width
12
3
read-only
HSPOL
Horizontal Synchronization Polarity
31
1
read-write
LTDCEN
LCD-TFT controller enable bit
0
1
read-write
PCPOL
Pixel Clock Polarity
28
1
read-write
VSPOL
Vertical Synchronization Polarity
30
1
read-write
ICR
ICR
LTDC Interrupt Clear Register
0x3C
32
write-only
n
0x0
0xFFFFFFFF
CFUIF
Clears the FIFO Underrun Interrupt flag
1
1
CLIF
Clears the Line Interrupt Flag
0
1
CRRIF
Clears Register Reload Interrupt Flag
3
1
CTERRIF
Clears the Transfer Error Interrupt Flag
2
1
IER
IER
LTDC Interrupt Enable Register
0x34
32
read-write
n
0x0
0xFFFFFFFF
FUIE
FIFO Underrun Interrupt Enable
1
1
LIE
Line Interrupt Enable
0
1
RRIE
Register Reload interrupt enable
3
1
TERRIE
Transfer Error Interrupt Enable
2
1
ISR
ISR
LTDC Interrupt Status Register
0x38
32
read-only
n
0x0
0xFFFFFFFF
FUIF
FIFO Underrun Interrupt flag
1
1
LIF
Line Interrupt flag
0
1
RRIF
Register Reload Interrupt Flag
3
1
TERRIF
Transfer Error interrupt flag
2
1
L1BFCR
L1BFCR
LTDC Layer Blending Factors Configuration Register
0xA0
32
read-write
n
0x0
0xFFFFFFFF
BF1
Blending Factor 1
8
3
BF2
Blending Factor 2
0
3
L1CACR
L1CACR
LTDC Layer Constant Alpha Configuration Register
0x98
32
read-write
n
0x0
0xFFFFFFFF
CONSTA
Constant Alpha
0
8
L1CFBAR
L1CFBAR
LTDC Layer Color Frame Buffer Address Register
0xAC
32
read-write
n
0x0
0xFFFFFFFF
CFBADD
Color Frame Buffer Start Address
0
32
L1CFBLNR
L1CFBLNR
LTDC Layer ColorFrame Buffer Line Number Register
0xB4
32
read-write
n
0x0
0xFFFFFFFF
CFBLNBR
Frame Buffer Line Number
0
11
L1CFBLR
L1CFBLR
LTDC Layer Color Frame Buffer Length Register
0xB0
32
read-write
n
0x0
0xFFFFFFFF
CFBLL
Color Frame Buffer Line Length
0
13
CFBP
Color Frame Buffer Pitch in bytes
16
13
L1CKCR
L1CKCR
LTDC Layer Color Keying Configuration Register
0x90
32
read-write
n
0x0
0xFFFFFFFF
CKBLUE
Color Key Blue value
0
8
CKGREEN
Color Key Green value
8
8
CKRED
Color Key Red value
16
8
L1CLUTWR
L1CLUTWR
LTDC Layerx CLUT Write Register
0xC4
32
write-only
n
0x0
0xFFFFFFFF
BLUE
Blue value
0
8
CLUTADD
CLUT Address
24
8
GREEN
Green value
8
8
RED
Red value
16
8
L1CR
L1CR
LTDC Layer Control Register
0x84
32
read-write
n
0x0
0xFFFFFFFF
CLUTEN
Color Look-Up Table Enable
4
1
COLKEN
Color Keying Enable
1
1
LEN
Layer Enable
0
1
L1DCCR
L1DCCR
LTDC Layer Default Color Configuration Register
0x9C
32
read-write
n
0x0
0xFFFFFFFF
DCALPHA
Default Color Alpha
24
8
DCBLUE
Default Color Blue
0
8
DCGREEN
Default Color Green
8
8
DCRED
Default Color Red
16
8
L1PFCR
L1PFCR
LTDC Layer Pixel Format Configuration Register
0x94
32
read-write
n
0x0
0xFFFFFFFF
PF
Pixel Format
0
3
L1WHPCR
L1WHPCR
LTDC Layer Window Horizontal Position Configuration Register
0x88
32
read-write
n
0x0
0xFFFFFFFF
WHSPPOS
Window Horizontal Stop Position
16
12
WHSTPOS
Window Horizontal Start Position
0
12
L1WVPCR
L1WVPCR
LTDC Layer Window Vertical Position Configuration Register
0x8C
32
read-write
n
0x0
0xFFFFFFFF
WVSPPOS
Window Vertical Stop Position
16
11
WVSTPOS
Window Vertical Start Position
0
11
L2BFCR
L2BFCR
LTDC Layer Blending Factors Configuration Register
0x124
32
read-write
n
0x0
0xFFFFFFFF
BF1
Blending Factor 1
8
3
BF2
Blending Factor 2
0
3
L2CACR
L2CACR
LTDC Layer Constant Alpha Configuration Register
0x118
32
read-write
n
0x0
0xFFFFFFFF
CONSTA
Constant Alpha
0
8
L2CFBAR
L2CFBAR
LTDC Layer Color Frame Buffer Address Register
0x12C
32
read-write
n
0x0
0xFFFFFFFF
CFBADD
Color Frame Buffer Start Address
0
32
L2CFBLNR
L2CFBLNR
LTDC Layer ColorFrame Buffer Line Number Register
0x134
32
read-write
n
0x0
0xFFFFFFFF
CFBLNBR
Frame Buffer Line Number
0
11
L2CFBLR
L2CFBLR
LTDC Layer Color Frame Buffer Length Register
0x130
32
read-write
n
0x0
0xFFFFFFFF
CFBLL
Color Frame Buffer Line Length
0
13
CFBP
Color Frame Buffer Pitch in bytes
16
13
L2CKCR
L2CKCR
LTDC Layer Color Keying Configuration Register
0x110
32
read-write
n
0x0
0xFFFFFFFF
CKBLUE
Color Key Blue value
0
8
CKGREEN
Color Key Green value
8
8
CKRED
Color Key Red value
16
8
L2CLUTWR
L2CLUTWR
LTDC Layerx CLUT Write Register
0x144
32
write-only
n
0x0
0xFFFFFFFF
BLUE
Blue value
0
8
CLUTADD
CLUT Address
24
8
GREEN
Green value
8
8
RED
Red value
16
8
L2CR
L2CR
LTDC Layer Control Register
0x104
32
read-write
n
0x0
0xFFFFFFFF
CLUTEN
Color Look-Up Table Enable
4
1
COLKEN
Color Keying Enable
1
1
LEN
Layer Enable
0
1
L2DCCR
L2DCCR
LTDC Layer Default Color Configuration Register
0x11C
32
read-write
n
0x0
0xFFFFFFFF
DCALPHA
Default Color Alpha
24
8
DCBLUE
Default Color Blue
0
8
DCGREEN
Default Color Green
8
8
DCRED
Default Color Red
16
8
L2PFCR
L2PFCR
LTDC Layer Pixel Format Configuration Register
0x114
32
read-write
n
0x0
0xFFFFFFFF
PF
Pixel Format
0
3
L2WHPCR
L2WHPCR
LTDC Layerx Window Horizontal Position Configuration Register
0x108
32
read-write
n
0x0
0xFFFFFFFF
WHSPPOS
Window Horizontal Stop Position
16
12
WHSTPOS
Window Horizontal Start Position
0
12
L2WVPCR
L2WVPCR
LTDC Layer Window Vertical Position Configuration Register
0x10C
32
read-write
n
0x0
0xFFFFFFFF
WVSPPOS
Window Vertical Stop Position
16
11
WVSTPOS
Window Vertical Start Position
0
11
LIPCR
LIPCR
LTDC Line Interrupt Position Configuration Register
0x40
32
read-write
n
0x0
0xFFFFFFFF
LIPOS
Line Interrupt Position
0
11
SRCR
SRCR
LTDC Shadow Reload Configuration Register
0x24
32
read-write
n
0x0
0xFFFFFFFF
IMR
Immediate Reload
0
1
VBR
Vertical Blanking Reload
1
1
SSCR
SSCR
LTDC Synchronization Size Configuration Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
HSW
Horizontal Synchronization Width (in units of pixel clock period)
16
12
VSH
Vertical Synchronization Height (in units of horizontal scan line)
0
11
TWCR
TWCR
LTDC Total Width Configuration Register
0x14
32
read-write
n
0x0
0xFFFFFFFF
TOTALH
Total Height (in units of horizontal scan line)
0
11
TOTALW
Total Width (in units of pixel clock period)
16
12
MPU
Memory protection unit
MPU
0xE000ED90
0x0
0x15
registers
n
CTRL
MPU_CTRL
MPU control register
0x4
32
read-write
n
0x0
0xFFFFFFFF
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault
1
1
PRIVDEFENA
Enable priviliged software access to default memory map
2
1
RASR
MPU_RASR
MPU region attribute and size register
0x10
32
read-write
n
0x0
0xFFFFFFFF
AP
Access permission
24
3
B
memory attribute
16
1
C
memory attribute
17
1
ENABLE
Region enable bit.
0
1
S
Shareable memory attribute
18
1
SIZE
Size of the MPU protection region
1
5
SRD
Subregion disable bits
8
8
TEX
memory attribute
19
3
XN
Instruction access disable bit
28
1
RBAR
MPU_RBAR
MPU region base address register
0xC
32
read-write
n
0x0
0xFFFFFFFF
ADDR
Region base address field
5
27
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
RNR
MPU_RNR
MPU region number register
0x8
32
read-write
n
0x0
0xFFFFFFFF
REGION
MPU region
0
8
TYPER
MPU_TYPER
MPU type register
0x0
32
read-only
n
0x800
0xFFFFFFFF
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction regions
16
8
SEPARATE
Separate flag
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0xE000E100
0x0
0x368
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x200
32
read-only
n
0x0
0xFFFFFFFF
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
32
read-only
n
0x0
0xFFFFFFFF
ACTIVE
ACTIVE
0
32
IABR2
IABR2
Interrupt Active Bit Register
0x208
32
read-only
n
0x0
0xFFFFFFFF
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x80
32
read-write
n
0x0
0xFFFFFFFF
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x84
32
read-write
n
0x0
0xFFFFFFFF
CLRENA
CLRENA
0
32
ICER2
ICER2
Interrupt Clear-Enable Register
0x88
32
read-write
n
0x0
0xFFFFFFFF
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0xFFFFFFFF
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x184
32
read-write
n
0x0
0xFFFFFFFF
CLRPEND
CLRPEND
0
32
ICPR2
ICPR2
Interrupt Clear-Pending Register
0x188
32
read-write
n
0x0
0xFFFFFFFF
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x328
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x32C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x330
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x334
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x338
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR15
IPR15
Interrupt Priority Register
0x33C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR16
IPR16
Interrupt Priority Register
0x340
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR17
IPR17
Interrupt Priority Register
0x344
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR18
IPR18
Interrupt Priority Register
0x348
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR19
IPR19
Interrupt Priority Register
0x34C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR20
IPR20
Interrupt Priority Register
0x350
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR21
IPR21
Interrupt Priority Register
0x354
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR22
IPR22
Interrupt Priority Register
0x358
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR23
IPR23
Interrupt Priority Register
0x35C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR24
IPR24
Interrupt Priority Register
0x360
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR25
IPR25
Interrupt Priority Register
0x364
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x324
32
read-write
n
0x0
0xFFFFFFFF
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x0
32
read-write
n
0x0
0xFFFFFFFF
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x4
32
read-write
n
0x0
0xFFFFFFFF
SETENA
SETENA
0
32
ISER2
ISER2
Interrupt Set-Enable Register
0x8
32
read-write
n
0x0
0xFFFFFFFF
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0xFFFFFFFF
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x104
32
read-write
n
0x0
0xFFFFFFFF
SETPEND
SETPEND
0
32
ISPR2
ISPR2
Interrupt Set-Pending Register
0x108
32
read-write
n
0x0
0xFFFFFFFF
SETPEND
SETPEND
0
32
NVIC_STIR
Nested vectored interrupt controller
NVIC
0xE000EF00
0x0
0x5
registers
n
STIR
STIR
Software trigger interrupt register
0x0
32
read-write
n
0x0
0xFFFFFFFF
INTID
Software generated interrupt ID
0
9
OCTOSPI1
OctoSPI
OctoSPI
0xA0001000
0x0
0x400
registers
n
OCTOSPI1
OCTOSPI1 global interrupt
71
ABR
ABR
alternate bytes register
0x120
32
read-write
n
0x0
0xFFFFFFFF
ALTERNATE
Alternate bytes
0
32
AR
AR
address register
0x48
32
read-write
n
0x0
0xFFFFFFFF
ADDRESS
ADDRESS
0
32
CCR
CCR
communication configuration register
0x100
32
read-write
n
0x0
0xFFFFFFFF
ABDTR
Alternate bytes double transfer rate
19
1
ABMODE
Alternate byte mode
16
3
ABSIZE
Alternate bytes size
20
2
ADDTR
Address double transfer rate
11
1
ADMODE
Address mode
8
3
ADSIZE
Address size
12
2
DDTR
Alternate bytes double transfer rate
27
1
DMODE
Data mode
24
3
DQSE
DQS enable
29
1
IDTR
Instruction double transfer rate
3
1
IMODE
Instruction mode
0
3
ISIZE
Instruction size
4
2
SIOO
Send instruction only once mode
31
1
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ABORT
Abort request
1
1
APMS
Automatic poll mode stop
22
1
DMAEN
DMA enable
2
1
DQM
Dual-quad mode
6
1
EN
Enable
0
1
FMODE
Functional mode
28
2
FSEL
FLASH memory selection
7
1
FTHRES
IFO threshold level
8
5
FTIE
FIFO threshold interrupt enable
18
1
PMM
Polling match mode
23
1
SMIE
Status match interrupt enable
19
1
TCEN
Timeout counter enable
3
1
TCIE
Transfer complete interrupt enable
17
1
TEIE
Transfer error interrupt enable
16
1
TOIE
TimeOut interrupt enable
20
1
DCR1
DCR1
device configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CKMODE
Mode 0 / mode 3
0
1
CSHT
Chip-select high time
8
3
DEVSIZE
Device size
16
5
FRCK
Free running clock
1
1
MTYP
Memory type
24
2
DCR2
DCR2
device configuration register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
8
WRAPSIZE
Wrap size
16
3
DCR3
DCR3
device configuration register 3
0x10
32
read-write
n
0x0
0xFFFFFFFF
CSBOUND
CS boundary
16
5
DLR
DLR
data length register
0x40
32
read-write
n
0x0
0xFFFFFFFF
DL
Data length
0
32
DR
DR
data register
0x50
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
FCR
FCR
flag clear register
0x24
32
write-only
n
0x0
0xFFFFFFFF
CSMF
Clear status match flag
3
1
CTCF
Clear transfer complete flag
1
1
CTEF
Clear transfer error flag
0
1
CTOF
Clear timeout flag
4
1
HLCR
HLCR
HyperBusTM latency configuration register
0x200
32
read-write
n
0x0
0xFFFFFFFF
LM
Latency mode
0
1
TACC
Access time
8
8
TRWR
Read write recovery time
16
8
WZL
Write zero latency
1
1
HWCFGR
HWCFGR
HW configuration register
0x3F0
32
read-only
n
0x11300080
0xFFFFFFFF
AXI
AXI interface
0
4
FIFO
FIFO depth
4
8
IDL
ID Length
20
4
MMW
Memory map write
24
4
MST
Master
28
4
PRES
Prescaler
12
8
ID
ID
identification
0x3F8
32
read-only
n
0x140041
0xFFFFFFFF
ID
Identification
0
32
IR
IR
instruction register
0x110
32
read-write
n
0x0
0xFFFFFFFF
INSTRUCTION
INSTRUCTION
0
32
LPTR
LPTR
low-power timeout register
0x130
32
read-write
n
0x0
0xFFFFFFFF
TIMEOUT
Timeout period
0
16
MID
MID
magic ID
0x3FC
32
read-only
n
0xA3C5DD01
0xFFFFFFFF
MID
Magic ID
0
32
PIR
PIR
polling interval register
0x90
32
read-write
n
0x0
0xFFFFFFFF
INTERVAL
Polling interval
0
16
PSMAR
PSMAR
polling status match register
0x88
32
read-write
n
0x0
0xFFFFFFFF
MATCH
Status match
0
32
PSMKR
PSMKR
polling status mask register
0x80
32
read-write
n
0x0
0xFFFFFFFF
MASK
Status mask
0
32
SR
SR
status register
0x20
32
read-write
n
0x0
0xFFFFFFFF
BUSY
BUSY
5
1
FLEVEL
FIFO level
8
6
FTF
FIFO threshold flag
2
1
SMF
Status match flag
3
1
TCF
Transfer complete flag
1
1
TEF
Transfer error flag
0
1
TOF
Timeout flag
4
1
TCR
TCR
timing configuration register
0x108
32
read-write
n
0x0
0xFFFFFFFF
DCYC
Number of dummy cycles
0
5
DHQC
Delay hold quarter cycle
28
1
SSHIFT
Sample shift
30
1
VER
VER
version register
0x3F4
32
read-only
n
0x10
0xFFFFFFFF
VER
Version
0
8
WABR
WABR
write alternate bytes register
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
ALTERNATE
Alternate bytes
0
32
WCCR
WCCR
write communication configuration register
0x180
32
read-write
n
0x0
0xFFFFFFFF
ABDTR
Alternate bytes double transfer rate
19
1
ABMODE
Alternate byte mode
16
3
ABSIZE
Alternate bytes size
20
2
ADDTR
Address double transfer rate
11
1
ADMODE
Address mode
8
3
ADSIZE
Address size
12
2
DDTR
alternate bytes double transfer rate
27
1
DMODE
Data mode
24
3
DQSE
DQS enable
29
1
IDTR
Instruction double transfer rate
3
1
IMODE
Instruction mode
0
3
ISIZE
Instruction size
4
2
SIOO
Send instruction only once mode
31
1
WIR
WIR
write instruction register
0x190
32
read-write
n
0x0
0xFFFFFFFF
INSTRUCTION
INSTRUCTION
0
32
WTCR
WTCR
write timing configuration register
0x188
32
read-write
n
0x0
0xFFFFFFFF
DCYC
Number of dummy cycles
0
5
OCTOSPI2
OctoSPI
OctoSPI
0xA0001400
0x0
0x400
registers
n
OCTOSPI2
OCTOSPI2 global interrupt
76
ABR
ABR
alternate bytes register
0x120
32
read-write
n
0x0
0xFFFFFFFF
ALTERNATE
Alternate bytes
0
32
AR
AR
address register
0x48
32
read-write
n
0x0
0xFFFFFFFF
ADDRESS
ADDRESS
0
32
CCR
CCR
communication configuration register
0x100
32
read-write
n
0x0
0xFFFFFFFF
ABDTR
Alternate bytes double transfer rate
19
1
ABMODE
Alternate byte mode
16
3
ABSIZE
Alternate bytes size
20
2
ADDTR
Address double transfer rate
11
1
ADMODE
Address mode
8
3
ADSIZE
Address size
12
2
DDTR
Alternate bytes double transfer rate
27
1
DMODE
Data mode
24
3
DQSE
DQS enable
29
1
IDTR
Instruction double transfer rate
3
1
IMODE
Instruction mode
0
3
ISIZE
Instruction size
4
2
SIOO
Send instruction only once mode
31
1
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
ABORT
Abort request
1
1
APMS
Automatic poll mode stop
22
1
DMAEN
DMA enable
2
1
DQM
Dual-quad mode
6
1
EN
Enable
0
1
FMODE
Functional mode
28
2
FSEL
FLASH memory selection
7
1
FTHRES
IFO threshold level
8
5
FTIE
FIFO threshold interrupt enable
18
1
PMM
Polling match mode
23
1
SMIE
Status match interrupt enable
19
1
TCEN
Timeout counter enable
3
1
TCIE
Transfer complete interrupt enable
17
1
TEIE
Transfer error interrupt enable
16
1
TOIE
TimeOut interrupt enable
20
1
DCR1
DCR1
device configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CKMODE
Mode 0 / mode 3
0
1
CSHT
Chip-select high time
8
3
DEVSIZE
Device size
16
5
FRCK
Free running clock
1
1
MTYP
Memory type
24
2
DCR2
DCR2
device configuration register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
8
WRAPSIZE
Wrap size
16
3
DCR3
DCR3
device configuration register 3
0x10
32
read-write
n
0x0
0xFFFFFFFF
CSBOUND
CS boundary
16
5
DLR
DLR
data length register
0x40
32
read-write
n
0x0
0xFFFFFFFF
DL
Data length
0
32
DR
DR
data register
0x50
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
FCR
FCR
flag clear register
0x24
32
write-only
n
0x0
0xFFFFFFFF
CSMF
Clear status match flag
3
1
CTCF
Clear transfer complete flag
1
1
CTEF
Clear transfer error flag
0
1
CTOF
Clear timeout flag
4
1
HLCR
HLCR
HyperBusTM latency configuration register
0x200
32
read-write
n
0x0
0xFFFFFFFF
LM
Latency mode
0
1
TACC
Access time
8
8
TRWR
Read write recovery time
16
8
WZL
Write zero latency
1
1
HWCFGR
HWCFGR
HW configuration register
0x3F0
32
read-only
n
0x11300080
0xFFFFFFFF
AXI
AXI interface
0
4
FIFO
FIFO depth
4
8
IDL
ID Length
20
4
MMW
Memory map write
24
4
MST
Master
28
4
PRES
Prescaler
12
8
ID
ID
identification
0x3F8
32
read-only
n
0x140041
0xFFFFFFFF
ID
Identification
0
32
IR
IR
instruction register
0x110
32
read-write
n
0x0
0xFFFFFFFF
INSTRUCTION
INSTRUCTION
0
32
LPTR
LPTR
low-power timeout register
0x130
32
read-write
n
0x0
0xFFFFFFFF
TIMEOUT
Timeout period
0
16
MID
MID
magic ID
0x3FC
32
read-only
n
0xA3C5DD01
0xFFFFFFFF
MID
Magic ID
0
32
PIR
PIR
polling interval register
0x90
32
read-write
n
0x0
0xFFFFFFFF
INTERVAL
Polling interval
0
16
PSMAR
PSMAR
polling status match register
0x88
32
read-write
n
0x0
0xFFFFFFFF
MATCH
Status match
0
32
PSMKR
PSMKR
polling status mask register
0x80
32
read-write
n
0x0
0xFFFFFFFF
MASK
Status mask
0
32
SR
SR
status register
0x20
32
read-write
n
0x0
0xFFFFFFFF
BUSY
BUSY
5
1
FLEVEL
FIFO level
8
6
FTF
FIFO threshold flag
2
1
SMF
Status match flag
3
1
TCF
Transfer complete flag
1
1
TEF
Transfer error flag
0
1
TOF
Timeout flag
4
1
TCR
TCR
timing configuration register
0x108
32
read-write
n
0x0
0xFFFFFFFF
DCYC
Number of dummy cycles
0
5
DHQC
Delay hold quarter cycle
28
1
SSHIFT
Sample shift
30
1
VER
VER
version register
0x3F4
32
read-only
n
0x10
0xFFFFFFFF
VER
Version
0
8
WABR
WABR
write alternate bytes register
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
ALTERNATE
Alternate bytes
0
32
WCCR
WCCR
write communication configuration register
0x180
32
read-write
n
0x0
0xFFFFFFFF
ABDTR
Alternate bytes double transfer rate
19
1
ABMODE
Alternate byte mode
16
3
ABSIZE
Alternate bytes size
20
2
ADDTR
Address double transfer rate
11
1
ADMODE
Address mode
8
3
ADSIZE
Address size
12
2
DDTR
alternate bytes double transfer rate
27
1
DMODE
Data mode
24
3
DQSE
DQS enable
29
1
IDTR
Instruction double transfer rate
3
1
IMODE
Instruction mode
0
3
ISIZE
Instruction size
4
2
SIOO
Send instruction only once mode
31
1
WIR
WIR
write instruction register
0x190
32
read-write
n
0x0
0xFFFFFFFF
INSTRUCTION
INSTRUCTION
0
32
WTCR
WTCR
write timing configuration register
0x188
32
read-write
n
0x0
0xFFFFFFFF
DCYC
Number of dummy cycles
0
5
OCTOSPIM
OctoSPI IO Manager
OCTOSPIM
0x50061C00
0x0
0x400
registers
n
P1CR
P1CR
OctoSPI IO Manager Port 1 Configuration Register
0x4
32
read-write
n
0x3010111
0xFFFFFFFF
CLKEN
CLK/CLK Enable for Port
0
1
CLKSRC
CLK/CLK Source for Port
1
1
DQSEN
DQS Enable for Port
4
1
DQSSRC
DQS Source for Port
5
1
IOHEN
Enable for Port n
24
1
IOHSRC
Source for Port
25
2
IOLEN
Enable for Port
16
1
IOLSRC
Source for Port
17
2
NCSEN
CS Enable for Port
8
1
NCSSRC
CS Source for Port
9
1
P2CR
P2CR
OctoSPI IO Manager Port 2 Configuration Register
0x8
32
read-write
n
0x7050333
0xFFFFFFFF
CLKEN
CLK/CLK Enable for Port
0
1
CLKSRC
CLK/CLK Source for Port
1
1
DQSEN
DQS Enable for Port
4
1
DQSSRC
DQS Source for Port
5
1
IOHEN
Enable for Port n
24
1
IOHSRC
Source for Port
25
2
IOLEN
Enable for Port
16
1
IOLSRC
Source for Port
17
2
NCSEN
CS Enable for Port
8
1
NCSSRC
CS Source for Port
9
1
OPAMP
Operational amplifiers
OPAMP
0x40007800
0x0
0x400
registers
n
OPAMP1_CSR
OPAMP1_CSR
OPAMP1 control/status register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CALON
Calibration mode enabled
12
1
CALOUT
Operational amplifier calibration output
15
1
CALSEL
Calibration selection
13
1
OPAEN
Operational amplifier Enable
0
1
OPALPM
Operational amplifier Low Power Mode
1
1
OPAMODE
Operational amplifier PGA mode
2
2
OPA_RANGE
Operational amplifier power supply range for stability
31
1
PGA_GAIN
Operational amplifier Programmable amplifier gain value
4
2
USERTRIM
allows to switch from AOP offset trimmed values to AOP offset
14
1
VM_SEL
Inverting input selection
8
2
VP_SEL
Non inverted input selection
10
1
OPAMP1_LPOTR
OPAMP1_LPOTR
OPAMP1 offset trimming register in low-power mode
0x8
32
read-write
n
0x0
0xFFFFFFFF
TRIMLPOFFSETN
Trim for NMOS differential pairs
0
5
TRIMLPOFFSETP
Trim for PMOS differential pairs
8
5
OPAMP1_OTR
OPAMP1_OTR
OPAMP1 offset trimming register in normal mode
0x4
32
read-write
n
0x0
0xFFFFFFFF
TRIMOFFSETN
Trim for NMOS differential pairs
0
5
TRIMOFFSETP
Trim for PMOS differential pairs
8
5
OPAMP2_CSR
OPAMP2_CSR
OPAMP2 control/status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CALON
Calibration mode enabled
12
1
CALOUT
Operational amplifier calibration output
15
1
CALSEL
Calibration selection
13
1
OPAEN
Operational amplifier Enable
0
1
OPALPM
Operational amplifier Low Power Mode
1
1
OPAMODE
Operational amplifier PGA mode
2
2
PGA_GAIN
Operational amplifier Programmable amplifier gain value
4
2
USERTRIM
allows to switch from AOP offset trimmed values to AOP offset
14
1
VM_SEL
Inverting input selection
8
2
VP_SEL
Non inverted input selection
10
1
OPAMP2_LPOTR
OPAMP2_LPOTR
OPAMP2 offset trimming register in low-power mode
0x18
32
read-write
n
0x0
0xFFFFFFFF
TRIMLPOFFSETN
Trim for NMOS differential pairs
0
5
TRIMLPOFFSETP
Trim for PMOS differential pairs
8
5
OPAMP2_OTR
OPAMP2_OTR
OPAMP2 offset trimming register in normal mode
0x14
32
read-write
n
0x0
0xFFFFFFFF
TRIMOFFSETN
Trim for NMOS differential pairs
0
5
TRIMOFFSETP
Trim for PMOS differential pairs
8
5
OTG_FS_DEVICE
USB on the go full speed
USB_OTG_FS
0x50000800
0x0
0x400
registers
n
DIEPCTL1
DIEPCTL1
OTG device endpoint-1 control register
0x120
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM_SD1PID
SODDFRM/SD1PID
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPCTL2
DIEPCTL2
OTG device endpoint-2 control register
0x140
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPCTL3
DIEPCTL3
OTG device endpoint-3 control register
0x160
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
TXFNUM
TXFNUM
22
4
read-write
USBAEP
USBAEP
15
1
read-write
DIEPEMPMSK
DIEPEMPMSK
OTG_FS device IN endpoint FIFO empty interrupt mask register
0x34
32
read-write
n
0x0
0xFFFFFFFF
INEPTXFEM
IN EP Tx FIFO empty interrupt mask bits
0
16
DIEPINT0
DIEPINT0
device endpoint-x interrupt register
0x108
32
read-write
n
0x80
0xFFFFFFFF
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT1
DIEPINT1
device endpoint-1 interrupt register
0x128
32
read-write
n
0x80
0xFFFFFFFF
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT2
DIEPINT2
device endpoint-2 interrupt register
0x148
32
read-write
n
0x80
0xFFFFFFFF
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPINT3
DIEPINT3
device endpoint-3 interrupt register
0x168
32
read-write
n
0x80
0xFFFFFFFF
EPDISD
EPDISD
1
1
read-write
INEPNE
INEPNE
6
1
read-write
ITTXFE
ITTXFE
4
1
read-write
TOC
TOC
3
1
read-write
TXFE
TXFE
7
1
read-only
XFRC
XFRC
0
1
read-write
DIEPTSIZ0
DIEPTSIZ0
device endpoint-0 transfer size register
0x110
32
read-write
n
0x0
0xFFFFFFFF
PKTCNT
Packet count
19
2
XFRSIZ
Transfer size
0
7
DIEPTSIZ1
DIEPTSIZ1
device endpoint-1 transfer size register
0x130
32
read-write
n
0x0
0xFFFFFFFF
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DIEPTSIZ2
DIEPTSIZ2
device endpoint-2 transfer size register
0x150
32
read-write
n
0x0
0xFFFFFFFF
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DIEPTSIZ3
DIEPTSIZ3
device endpoint-3 transfer size register
0x170
32
read-write
n
0x0
0xFFFFFFFF
MCNT
Multi count
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
DOEPCTL0
DOEPCTL0
device endpoint-0 control register
0x300
32
read-write
n
0x8000
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EPDIS
EPDIS
30
1
read-only
EPENA
EPENA
31
1
write-only
EPTYP
EPTYP
18
2
read-only
MPSIZ
MPSIZ
0
2
read-only
NAKSTS
NAKSTS
17
1
read-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-only
DOEPCTL1
DOEPCTL1
device endpoint-1 control register
0x320
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPCTL2
DOEPCTL2
device endpoint-2 control register
0x340
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPCTL3
DOEPCTL3
device endpoint-3 control register
0x360
32
read-write
n
0x0
0xFFFFFFFF
CNAK
CNAK
26
1
write-only
EONUM_DPID
EONUM/DPID
16
1
read-only
EPDIS
EPDIS
30
1
read-write
EPENA
EPENA
31
1
read-write
EPTYP
EPTYP
18
2
read-write
MPSIZ
MPSIZ
0
11
read-write
NAKSTS
NAKSTS
17
1
read-only
SD0PID_SEVNFRM
SD0PID/SEVNFRM
28
1
write-only
SNAK
SNAK
27
1
write-only
SNPM
SNPM
20
1
read-write
SODDFRM
SODDFRM
29
1
write-only
Stall
Stall
21
1
read-write
USBAEP
USBAEP
15
1
read-write
DOEPINT0
DOEPINT0
device endpoint-0 interrupt register
0x308
32
read-write
n
0x80
0xFFFFFFFF
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT1
DOEPINT1
device endpoint-1 interrupt register
0x328
32
read-write
n
0x80
0xFFFFFFFF
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT2
DOEPINT2
device endpoint-2 interrupt register
0x348
32
read-write
n
0x80
0xFFFFFFFF
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPINT3
DOEPINT3
device endpoint-3 interrupt register
0x368
32
read-write
n
0x80
0xFFFFFFFF
B2BSTUP
B2BSTUP
6
1
EPDISD
EPDISD
1
1
OTEPDIS
OTEPDIS
4
1
STUP
STUP
3
1
XFRC
XFRC
0
1
DOEPTSIZ0
DOEPTSIZ0
device OUT endpoint-0 transfer size register
0x310
32
read-write
n
0x0
0xFFFFFFFF
PKTCNT
Packet count
19
1
STUPCNT
SETUP packet count
29
2
XFRSIZ
Transfer size
0
7
DOEPTSIZ1
DOEPTSIZ1
device OUT endpoint-1 transfer size register
0x330
32
read-write
n
0x0
0xFFFFFFFF
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DOEPTSIZ2
DOEPTSIZ2
device OUT endpoint-2 transfer size register
0x350
32
read-write
n
0x0
0xFFFFFFFF
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DOEPTSIZ3
DOEPTSIZ3
device OUT endpoint-3 transfer size register
0x370
32
read-write
n
0x0
0xFFFFFFFF
PKTCNT
Packet count
19
10
RXDPID_STUPCNT
Received data PID/SETUP packet count
29
2
XFRSIZ
Transfer size
0
19
DTXFSTS0
DTXFSTS0
OTG_FS device IN endpoint transmit FIFO status register
0x118
32
read-only
n
0x0
0xFFFFFFFF
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS1
DTXFSTS1
OTG_FS device IN endpoint transmit FIFO status register
0x138
32
read-only
n
0x0
0xFFFFFFFF
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS2
DTXFSTS2
OTG_FS device IN endpoint transmit FIFO status register
0x158
32
read-only
n
0x0
0xFFFFFFFF
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DTXFSTS3
DTXFSTS3
OTG_FS device IN endpoint transmit FIFO status register
0x178
32
read-only
n
0x0
0xFFFFFFFF
INEPTFSAV
IN endpoint TxFIFO space available
0
16
DVBUSDIS
DVBUSDIS
OTG_FS device VBUS discharge time register
0x28
32
read-write
n
0x17D7
0xFFFFFFFF
VBUSDT
Device VBUS discharge time
0
16
DVBUSPULSE
DVBUSPULSE
OTG_FS device VBUS pulsing time register
0x2C
32
read-write
n
0x5B8
0xFFFFFFFF
DVBUSP
Device VBUS pulsing time
0
12
FS_DAINT
FS_DAINT
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
0x18
32
read-only
n
0x0
0xFFFFFFFF
IEPINT
IN endpoint interrupt bits
0
16
OEPINT
OUT endpoint interrupt bits
16
16
FS_DAINTMSK
FS_DAINTMSK
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
IEPM
IN EP interrupt mask bits
0
16
OEPINT
OUT endpoint interrupt bits
16
16
FS_DCFG
FS_DCFG
OTG_FS device configuration register (OTG_FS_DCFG)
0x0
32
read-write
n
0x2200000
0xFFFFFFFF
DAD
Device address
4
7
DSPD
Device speed
0
2
NZLSOHSK
Non-zero-length status OUT handshake
2
1
PFIVL
Periodic frame interval
11
2
FS_DCTL
FS_DCTL
OTG_FS device control register (OTG_FS_DCTL)
0x4
32
read-write
n
0x0
0xFFFFFFFF
CGINAK
Clear global IN NAK
8
1
read-write
CGONAK
Clear global OUT NAK
10
1
read-write
GINSTS
Global IN NAK status
2
1
read-only
GONSTS
Global OUT NAK status
3
1
read-only
POPRGDNE
Power-on programming done
11
1
read-write
RWUSIG
Remote wakeup signaling
0
1
read-write
SDIS
Soft disconnect
1
1
read-write
SGINAK
Set global IN NAK
7
1
read-write
SGONAK
Set global OUT NAK
9
1
read-write
TCTL
Test control
4
3
read-write
FS_DIEPCTL0
FS_DIEPCTL0
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
0x100
32
read-write
n
0x0
0xFFFFFFFF
CNAK
Clear NAK
26
1
write-only
EPDIS
Endpoint disable
30
1
read-only
EPENA
Endpoint enable
31
1
read-only
EPTYP
Endpoint type
18
2
read-only
MPSIZ
Maximum packet size
0
2
read-write
NAKSTS
NAK status
17
1
read-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
USBAEP
USB active endpoint
15
1
read-only
FS_DIEPMSK
FS_DIEPMSK
OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
0x10
32
read-write
n
0x0
0xFFFFFFFF
EPDM
Endpoint disabled interrupt mask
1
1
INEPNEM
IN endpoint NAK effective mask
6
1
INEPNMM
IN token received with EP mismatch mask
5
1
ITTXFEMSK
IN token received when TxFIFO empty mask
4
1
TOM
Timeout condition mask (Non-isochronous endpoints)
3
1
XFRCM
Transfer completed interrupt mask
0
1
FS_DOEPMSK
FS_DOEPMSK
OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
0x14
32
read-write
n
0x0
0xFFFFFFFF
EPDM
Endpoint disabled interrupt mask
1
1
OTEPDM
OUT token received when endpoint disabled mask
4
1
STUPM
SETUP phase done mask
3
1
XFRCM
Transfer completed interrupt mask
0
1
FS_DSTS
FS_DSTS
OTG_FS device status register (OTG_FS_DSTS)
0x8
32
read-only
n
0x10
0xFFFFFFFF
EERR
Erratic error
3
1
ENUMSPD
Enumerated speed
1
2
FNSOF
Frame number of the received SOF
8
14
SUSPSTS
Suspend status
0
1
OTG_FS_GLOBAL
USB on the go full speed
USB_OTG_FS
0x50000000
0x0
0x400
registers
n
OTG_FS
USB OTG FS global Interrupt
67
FS_CID
FS_CID
core ID register
0x3C
32
read-write
n
0x1000
0xFFFFFFFF
PRODUCT_ID
Product ID field
0
32
FS_DIEPTXF1
FS_DIEPTXF1
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
0x104
32
read-write
n
0x2000400
0xFFFFFFFF
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO2 transmit RAM start address
0
16
FS_DIEPTXF2
FS_DIEPTXF2
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
0x108
32
read-write
n
0x2000400
0xFFFFFFFF
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO3 transmit RAM start address
0
16
FS_DIEPTXF3
FS_DIEPTXF3
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
0x10C
32
read-write
n
0x2000400
0xFFFFFFFF
INEPTXFD
IN endpoint TxFIFO depth
16
16
INEPTXSA
IN endpoint FIFO4 transmit RAM start address
0
16
FS_GAHBCFG
FS_GAHBCFG
OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
0x8
32
read-write
n
0x0
0xFFFFFFFF
GINT
Global interrupt mask
0
1
PTXFELVL
Periodic TxFIFO empty level
8
1
TXFELVL
TxFIFO empty level
7
1
FS_GCCFG
FS_GCCFG
OTG_FS general core configuration register (OTG_FS_GCCFG)
0x38
32
read-write
n
0x0
0xFFFFFFFF
PWRDWN
Power down
16
1
SOFOUTEN
SOF output enable
20
1
VBUSASEN
Enable the VBUS sensing device
18
1
VBUSBSEN
Enable the VBUS sensing device
19
1
FS_GINTMSK
FS_GINTMSK
OTG_FS interrupt mask register (OTG_FS_GINTMSK)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CIDSCHGM
Connector ID status change mask
28
1
read-write
DISCINT
Disconnect detected interrupt mask
29
1
read-write
ENUMDNEM
Enumeration done mask
13
1
read-write
EOPFM
End of periodic frame interrupt mask
15
1
read-write
EPMISM
Endpoint mismatch interrupt mask
17
1
read-write
ESUSPM
Early suspend mask
10
1
read-write
GINAKEFFM
Global non-periodic IN NAK effective mask
6
1
read-write
GONAKEFFM
Global OUT NAK effective mask
7
1
read-write
HCIM
Host channels interrupt mask
25
1
read-write
IEPINT
IN endpoints interrupt mask
18
1
read-write
IISOIXFRM
Incomplete isochronous IN transfer mask
20
1
read-write
IPXFRM_IISOOXFRM
Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
21
1
read-write
ISOODRPM
Isochronous OUT packet dropped interrupt mask
14
1
read-write
MMISM
Mode mismatch interrupt mask
1
1
read-write
NPTXFEM
Non-periodic TxFIFO empty mask
5
1
read-write
OEPINT
OUT endpoints interrupt mask
19
1
read-write
OTGINT
OTG interrupt mask
2
1
read-write
PRTIM
Host port interrupt mask
24
1
read-only
PTXFEM
Periodic TxFIFO empty mask
26
1
read-write
RXFLVLM
Receive FIFO non-empty mask
4
1
read-write
SOFM
Start of frame mask
3
1
read-write
SRQIM
Session request/new session detected interrupt mask
30
1
read-write
USBRST
USB reset mask
12
1
read-write
USBSUSPM
USB suspend mask
11
1
read-write
WUIM
Resume/remote wakeup detected interrupt mask
31
1
read-write
FS_GINTSTS
FS_GINTSTS
OTG_FS core interrupt register (OTG_FS_GINTSTS)
0x14
32
read-write
n
0x4000020
0xFFFFFFFF
CIDSCHG
Connector ID status change
28
1
read-write
CMOD
Current mode of operation
0
1
read-only
DISCINT
Disconnect detected interrupt
29
1
read-write
ENUMDNE
Enumeration done
13
1
read-write
EOPF
End of periodic frame interrupt
15
1
read-write
ESUSP
Early suspend
10
1
read-write
GINAKEFF
Global IN non-periodic NAK effective
6
1
read-only
GOUTNAKEFF
Global OUT NAK effective
7
1
read-only
HCINT
Host channels interrupt
25
1
read-only
HPRTINT
Host port interrupt
24
1
read-only
IEPINT
IN endpoint interrupt
18
1
read-only
IISOIXFR
Incomplete isochronous IN transfer
20
1
read-write
IPXFR_INCOMPISOOUT
Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
21
1
read-write
ISOODRP
Isochronous OUT packet dropped interrupt
14
1
read-write
MMIS
Mode mismatch interrupt
1
1
read-write
NPTXFE
Non-periodic TxFIFO empty
5
1
read-only
OEPINT
OUT endpoint interrupt
19
1
read-only
OTGINT
OTG interrupt
2
1
read-only
PTXFE
Periodic TxFIFO empty
26
1
read-only
RXFLVL
RxFIFO non-empty
4
1
read-only
SOF
Start of frame
3
1
read-write
SRQINT
Session request/new session detected interrupt
30
1
read-write
USBRST
USB reset
12
1
read-write
USBSUSP
USB suspend
11
1
read-write
WKUPINT
Resume/remote wakeup detected interrupt
31
1
read-write
FS_GNPTXFSIZ_Device
FS_GNPTXFSIZ_Device
OTG_FS non-periodic transmit FIFO size register (Device mode)
0x28
32
read-write
n
0x200
0xFFFFFFFF
TX0FD
Endpoint 0 TxFIFO depth
16
16
TX0FSA
Endpoint 0 transmit RAM start address
0
16
FS_GNPTXFSIZ_Host
FS_GNPTXFSIZ_Host
OTG_FS non-periodic transmit FIFO size register (Host mode)
FS_GNPTXFSIZ_Device
0x28
32
read-write
n
0x200
0xFFFFFFFF
NPTXFD
Non-periodic TxFIFO depth
16
16
NPTXFSA
Non-periodic transmit RAM start address
0
16
FS_GNPTXSTS
FS_GNPTXSTS
OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
0x2C
32
read-only
n
0x80200
0xFFFFFFFF
NPTQXSAV
Non-periodic transmit request queue space available
16
8
NPTXFSAV
Non-periodic TxFIFO space available
0
16
NPTXQTOP
Top of the non-periodic transmit request queue
24
7
FS_GOTGCTL
FS_GOTGCTL
OTG_FS control and status register (OTG_FS_GOTGCTL)
0x0
32
read-write
n
0x800
0xFFFFFFFF
ASVLD
A-session valid
18
1
read-only
BSVLD
B-session valid
19
1
read-only
CIDSTS
Connector ID status
16
1
read-only
DBCT
Long/short debounce time
17
1
read-only
DHNPEN
Device HNP enabled
11
1
read-write
HNGSCS
Host negotiation success
8
1
read-only
HNPRQ
HNP request
9
1
read-write
HSHNPEN
Host set HNP enable
10
1
read-write
SRQ
Session request
1
1
read-write
SRQSCS
Session request success
0
1
read-only
FS_GOTGINT
FS_GOTGINT
OTG_FS interrupt register (OTG_FS_GOTGINT)
0x4
32
read-write
n
0x0
0xFFFFFFFF
ADTOCHG
A-device timeout change
18
1
DBCDNE
Debounce done
19
1
HNGDET
Host negotiation detected
17
1
HNSSCHG
Host negotiation success status change
9
1
SEDET
Session end detected
2
1
SRSSCHG
Session request success status change
8
1
FS_GRSTCTL
FS_GRSTCTL
OTG_FS reset register (OTG_FS_GRSTCTL)
0x10
32
read-write
n
0x20000000
0xFFFFFFFF
AHBIDL
AHB master idle
31
1
read-only
CSRST
Core soft reset
0
1
read-write
FCRST
Host frame counter reset
2
1
read-write
HSRST
HCLK soft reset
1
1
read-write
RXFFLSH
RxFIFO flush
4
1
read-write
TXFFLSH
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
FS_GRXFSIZ
FS_GRXFSIZ
OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
0x24
32
read-write
n
0x200
0xFFFFFFFF
RXFD
RxFIFO depth
0
16
FS_GRXSTSR_Device
FS_GRXSTSR_Device
OTG_FS Receive status debug read(Device mode)
0x1C
32
read-only
n
0x0
0xFFFFFFFF
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
FS_GRXSTSR_Host
FS_GRXSTSR_Host
OTG_FS Receive status debug read(Host mode)
FS_GRXSTSR_Device
0x1C
32
read-only
n
0x0
0xFFFFFFFF
BCNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
FRMNUM
Frame number
21
4
PKTSTS
Packet status
17
4
FS_GUSBCFG
FS_GUSBCFG
OTG_FS USB configuration register (OTG_FS_GUSBCFG)
0xC
32
read-write
n
0xA00
0xFFFFFFFF
CTXPKT
Corrupt Tx packet
31
1
read-write
FDMOD
Force device mode
30
1
read-write
FHMOD
Force host mode
29
1
read-write
HNPCAP
HNP-capable
9
1
read-write
PHYSEL
Full Speed serial transceiver select
6
1
write-only
SRPCAP
SRP-capable
8
1
read-write
TOCAL
FS timeout calibration
0
3
read-write
TRDT
USB turnaround time
10
4
read-write
FS_HPTXFSIZ
FS_HPTXFSIZ
OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
0x100
32
read-write
n
0x2000600
0xFFFFFFFF
PTXFSIZ
Host periodic TxFIFO depth
16
16
PTXSA
Host periodic TxFIFO start address
0
16
OTG_FS_HOST
USB on the go full speed
USB_OTG_FS
0x50000400
0x0
0x400
registers
n
FS_HCCHAR0
FS_HCCHAR0
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
0x100
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR1
FS_HCCHAR1
OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
0x120
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR2
FS_HCCHAR2
OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
0x140
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR3
FS_HCCHAR3
OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
0x160
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR4
FS_HCCHAR4
OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
0x180
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR5
FS_HCCHAR5
OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
0x1A0
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR6
FS_HCCHAR6
OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
0x1C0
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCCHAR7
FS_HCCHAR7
OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
0x1E0
32
read-write
n
0x0
0xFFFFFFFF
CHDIS
Channel disable
30
1
CHENA
Channel enable
31
1
DAD
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYP
Endpoint type
18
2
LSDEV
Low-speed device
17
1
MCNT
Multicount
20
2
MPSIZ
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
FS_HCFG
FS_HCFG
OTG_FS host configuration register (OTG_FS_HCFG)
0x0
32
read-write
n
0x0
0xFFFFFFFF
FSLSPCS
FS/LS PHY clock select
0
2
read-write
FSLSS
FS- and LS-only support
2
1
read-only
FS_HCINT0
FS_HCINT0
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
0x108
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT1
FS_HCINT1
OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
0x128
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT2
FS_HCINT2
OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
0x148
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT3
FS_HCINT3
OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
0x168
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT4
FS_HCINT4
OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
0x188
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT5
FS_HCINT5
OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
0x1A8
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT6
FS_HCINT6
OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
0x1C8
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINT7
FS_HCINT7
OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
0x1E8
32
read-write
n
0x0
0xFFFFFFFF
ACK
ACK response received/transmitted interrupt
5
1
BBERR
Babble error
8
1
CHH
Channel halted
1
1
DTERR
Data toggle error
10
1
FRMOR
Frame overrun
9
1
NAK
NAK response received interrupt
4
1
STALL
STALL response received interrupt
3
1
TXERR
Transaction error
7
1
XFRC
Transfer completed
0
1
FS_HCINTMSK0
FS_HCINTMSK0
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
0x10C
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK1
FS_HCINTMSK1
OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
0x12C
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK2
FS_HCINTMSK2
OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
0x14C
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK3
FS_HCINTMSK3
OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
0x16C
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK4
FS_HCINTMSK4
OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
0x18C
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK5
FS_HCINTMSK5
OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
0x1AC
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK6
FS_HCINTMSK6
OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
0x1CC
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCINTMSK7
FS_HCINTMSK7
OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
0x1EC
32
read-write
n
0x0
0xFFFFFFFF
ACKM
ACK response received/transmitted interrupt mask
5
1
BBERRM
Babble error mask
8
1
CHHM
Channel halted mask
1
1
DTERRM
Data toggle error mask
10
1
FRMORM
Frame overrun mask
9
1
NAKM
NAK response received interrupt mask
4
1
NYET
response received interrupt mask
6
1
STALLM
STALL response received interrupt mask
3
1
TXERRM
Transaction error mask
7
1
XFRCM
Transfer completed mask
0
1
FS_HCTSIZ0
FS_HCTSIZ0
OTG_FS host channel-0 transfer size register
0x110
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ1
FS_HCTSIZ1
OTG_FS host channel-1 transfer size register
0x130
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ2
FS_HCTSIZ2
OTG_FS host channel-2 transfer size register
0x150
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ3
FS_HCTSIZ3
OTG_FS host channel-3 transfer size register
0x170
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ4
FS_HCTSIZ4
OTG_FS host channel-x transfer size register
0x190
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ5
FS_HCTSIZ5
OTG_FS host channel-5 transfer size register
0x1B0
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ6
FS_HCTSIZ6
OTG_FS host channel-6 transfer size register
0x1D0
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HCTSIZ7
FS_HCTSIZ7
OTG_FS host channel-7 transfer size register
0x1F0
32
read-write
n
0x0
0xFFFFFFFF
DPID
Data PID
29
2
PKTCNT
Packet count
19
10
XFRSIZ
Transfer size
0
19
FS_HFNUM
FS_HFNUM
OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
0x8
32
read-only
n
0x3FFF
0xFFFFFFFF
FRNUM
Frame number
0
16
FTREM
Frame time remaining
16
16
FS_HPRT
FS_HPRT
OTG_FS host port control and status register (OTG_FS_HPRT)
0x40
32
read-write
n
0x0
0xFFFFFFFF
PCDET
Port connect detected
1
1
read-write
PCSTS
Port connect status
0
1
read-only
PENA
Port enable
2
1
read-write
PENCHNG
Port enable/disable change
3
1
read-write
PLSTS
Port line status
10
2
read-only
POCA
Port overcurrent active
4
1
read-only
POCCHNG
Port overcurrent change
5
1
read-write
PPWR
Port power
12
1
read-write
PRES
Port resume
6
1
read-write
PRST
Port reset
8
1
read-write
PSPD
Port speed
17
2
read-only
PSUSP
Port suspend
7
1
read-write
PTCTL
Port test control
13
4
read-write
FS_HPTXSTS
FS_HPTXSTS
OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
0x10
32
read-write
n
0x80100
0xFFFFFFFF
PTXFSAVL
Periodic transmit data FIFO space available
0
16
read-write
PTXQSAV
Periodic transmit request queue space available
16
8
read-only
PTXQTOP
Top of the periodic transmit request queue
24
8
read-only
HAINT
HAINT
OTG_FS Host all channels interrupt register
0x14
32
read-only
n
0x0
0xFFFFFFFF
HAINT
Channel interrupts
0
16
HAINTMSK
HAINTMSK
OTG_FS host all channels interrupt mask register
0x18
32
read-write
n
0x0
0xFFFFFFFF
HAINTM
Channel interrupt mask
0
16
HFIR
HFIR
OTG_FS Host frame interval register
0x4
32
read-write
n
0xEA60
0xFFFFFFFF
FRIVL
Frame interval
0
16
OTG_FS_PWRCLK
USB on the go full speed
USB_OTG_FS
0x50000E00
0x0
0x400
registers
n
FS_PCGCCTL
FS_PCGCCTL
OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
0x0
32
read-write
n
0x0
0xFFFFFFFF
GATEHCLK
Gate HCLK
1
1
PHYSUSP
PHY Suspended
4
1
STPPCLK
Stop PHY clock
0
1
PWR
Power control
PWR
0x40007000
0x0
0x400
registers
n
CR1
CR1
Power control register 1
0x0
32
read-write
n
0x200
0xFFFFFFFF
DBP
Disable backup domain write protection
8
1
LPMS
Low-power mode selection
0
3
LPR
Low-power run
14
1
VOS
Voltage scaling range selection
9
2
CR2
CR2
Power control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
IOSV
VDDIO2 Independent I/Os supply valid
9
1
PLS
Power voltage detector level selection
1
3
PVDE
Power voltage detector enable
0
1
PVME1
Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
4
1
PVME2
Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
5
1
PVME3
Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
6
1
PVME4
Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V
7
1
USV
VDDUSB USB supply valid
10
1
CR3
CR3
Power control register 3
0x8
32
read-write
n
0x8000
0xFFFFFFFF
APC
Apply pull-up and pull-down configuration
10
1
EWF
Enable internal wakeup line
15
1
EWUP1
Enable Wakeup pin WKUP1
0
1
EWUP2
Enable Wakeup pin WKUP2
1
1
EWUP3
Enable Wakeup pin WKUP3
2
1
EWUP4
Enable Wakeup pin WKUP4
3
1
EWUP5
Enable Wakeup pin WKUP5
4
1
RRS
SRAM2 retention in Standby mode
8
1
CR4
CR4
Power control register 4
0xC
32
read-write
n
0x0
0xFFFFFFFF
VBE
VBAT battery charging enable
8
1
VBRS
VBAT battery charging resistor selection
9
1
WP1
Wakeup pin WKUP1 polarity
0
1
WP2
Wakeup pin WKUP2 polarity
1
1
WP3
Wakeup pin WKUP3 polarity
2
1
WP4
Wakeup pin WKUP4 polarity
3
1
WP5
Wakeup pin WKUP5 polarity
4
1
PDCRA
PDCRA
Power Port A pull-down control register
0x24
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port A pull-down bit y (y=0..15)
0
1
PD1
Port A pull-down bit y (y=0..15)
1
1
PD10
Port A pull-down bit y (y=0..15)
10
1
PD11
Port A pull-down bit y (y=0..15)
11
1
PD12
Port A pull-down bit y (y=0..15)
12
1
PD13
Port A pull-down bit y (y=0..15)
13
1
PD14
Port A pull-down bit y (y=0..15)
14
1
PD15
Port A pull-down bit y (y=0..15)
15
1
PD2
Port A pull-down bit y (y=0..15)
2
1
PD3
Port A pull-down bit y (y=0..15)
3
1
PD4
Port A pull-down bit y (y=0..15)
4
1
PD5
Port A pull-down bit y (y=0..15)
5
1
PD6
Port A pull-down bit y (y=0..15)
6
1
PD7
Port A pull-down bit y (y=0..15)
7
1
PD8
Port A pull-down bit y (y=0..15)
8
1
PD9
Port A pull-down bit y (y=0..15)
9
1
PDCRB
PDCRB
Power Port B pull-down control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port B pull-down bit y (y=0..15)
0
1
PD1
Port B pull-down bit y (y=0..15)
1
1
PD10
Port B pull-down bit y (y=0..15)
10
1
PD11
Port B pull-down bit y (y=0..15)
11
1
PD12
Port B pull-down bit y (y=0..15)
12
1
PD13
Port B pull-down bit y (y=0..15)
13
1
PD14
Port B pull-down bit y (y=0..15)
14
1
PD15
Port B pull-down bit y (y=0..15)
15
1
PD2
Port B pull-down bit y (y=0..15)
2
1
PD3
Port B pull-down bit y (y=0..15)
3
1
PD4
Port B pull-down bit y (y=0..15)
4
1
PD5
Port B pull-down bit y (y=0..15)
5
1
PD6
Port B pull-down bit y (y=0..15)
6
1
PD7
Port B pull-down bit y (y=0..15)
7
1
PD8
Port B pull-down bit y (y=0..15)
8
1
PD9
Port B pull-down bit y (y=0..15)
9
1
PDCRC
PDCRC
Power Port C pull-down control register
0x34
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port C pull-down bit y (y=0..15)
0
1
PD1
Port C pull-down bit y (y=0..15)
1
1
PD10
Port C pull-down bit y (y=0..15)
10
1
PD11
Port C pull-down bit y (y=0..15)
11
1
PD12
Port C pull-down bit y (y=0..15)
12
1
PD13
Port C pull-down bit y (y=0..15)
13
1
PD14
Port C pull-down bit y (y=0..15)
14
1
PD15
Port C pull-down bit y (y=0..15)
15
1
PD2
Port C pull-down bit y (y=0..15)
2
1
PD3
Port C pull-down bit y (y=0..15)
3
1
PD4
Port C pull-down bit y (y=0..15)
4
1
PD5
Port C pull-down bit y (y=0..15)
5
1
PD6
Port C pull-down bit y (y=0..15)
6
1
PD7
Port C pull-down bit y (y=0..15)
7
1
PD8
Port C pull-down bit y (y=0..15)
8
1
PD9
Port C pull-down bit y (y=0..15)
9
1
PDCRD
PDCRD
Power Port D pull-down control register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port D pull-down bit y (y=0..15)
0
1
PD1
Port D pull-down bit y (y=0..15)
1
1
PD10
Port D pull-down bit y (y=0..15)
10
1
PD11
Port D pull-down bit y (y=0..15)
11
1
PD12
Port D pull-down bit y (y=0..15)
12
1
PD13
Port D pull-down bit y (y=0..15)
13
1
PD14
Port D pull-down bit y (y=0..15)
14
1
PD15
Port D pull-down bit y (y=0..15)
15
1
PD2
Port D pull-down bit y (y=0..15)
2
1
PD3
Port D pull-down bit y (y=0..15)
3
1
PD4
Port D pull-down bit y (y=0..15)
4
1
PD5
Port D pull-down bit y (y=0..15)
5
1
PD6
Port D pull-down bit y (y=0..15)
6
1
PD7
Port D pull-down bit y (y=0..15)
7
1
PD8
Port D pull-down bit y (y=0..15)
8
1
PD9
Port D pull-down bit y (y=0..15)
9
1
PDCRE
PDCRE
Power Port E pull-down control register
0x44
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port E pull-down bit y (y=0..15)
0
1
PD1
Port E pull-down bit y (y=0..15)
1
1
PD10
Port E pull-down bit y (y=0..15)
10
1
PD11
Port E pull-down bit y (y=0..15)
11
1
PD12
Port E pull-down bit y (y=0..15)
12
1
PD13
Port E pull-down bit y (y=0..15)
13
1
PD14
Port E pull-down bit y (y=0..15)
14
1
PD15
Port E pull-down bit y (y=0..15)
15
1
PD2
Port E pull-down bit y (y=0..15)
2
1
PD3
Port E pull-down bit y (y=0..15)
3
1
PD4
Port E pull-down bit y (y=0..15)
4
1
PD5
Port E pull-down bit y (y=0..15)
5
1
PD6
Port E pull-down bit y (y=0..15)
6
1
PD7
Port E pull-down bit y (y=0..15)
7
1
PD8
Port E pull-down bit y (y=0..15)
8
1
PD9
Port E pull-down bit y (y=0..15)
9
1
PDCRF
PDCRF
Power Port F pull-down control register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port F pull-down bit y (y=0..15)
0
1
PD1
Port F pull-down bit y (y=0..15)
1
1
PD10
Port F pull-down bit y (y=0..15)
10
1
PD11
Port F pull-down bit y (y=0..15)
11
1
PD12
Port F pull-down bit y (y=0..15)
12
1
PD13
Port F pull-down bit y (y=0..15)
13
1
PD14
Port F pull-down bit y (y=0..15)
14
1
PD15
Port F pull-down bit y (y=0..15)
15
1
PD2
Port F pull-down bit y (y=0..15)
2
1
PD3
Port F pull-down bit y (y=0..15)
3
1
PD4
Port F pull-down bit y (y=0..15)
4
1
PD5
Port F pull-down bit y (y=0..15)
5
1
PD6
Port F pull-down bit y (y=0..15)
6
1
PD7
Port F pull-down bit y (y=0..15)
7
1
PD8
Port F pull-down bit y (y=0..15)
8
1
PD9
Port F pull-down bit y (y=0..15)
9
1
PDCRG
PDCRG
Power Port G pull-down control register
0x54
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port G pull-down bit y (y=0..15)
0
1
PD1
Port G pull-down bit y (y=0..15)
1
1
PD10
Port G pull-down bit y (y=0..15)
10
1
PD11
Port G pull-down bit y (y=0..15)
11
1
PD12
Port G pull-down bit y (y=0..15)
12
1
PD13
Port G pull-down bit y (y=0..15)
13
1
PD14
Port G pull-down bit y (y=0..15)
14
1
PD15
Port G pull-down bit y (y=0..15)
15
1
PD2
Port G pull-down bit y (y=0..15)
2
1
PD3
Port G pull-down bit y (y=0..15)
3
1
PD4
Port G pull-down bit y (y=0..15)
4
1
PD5
Port G pull-down bit y (y=0..15)
5
1
PD6
Port G pull-down bit y (y=0..15)
6
1
PD7
Port G pull-down bit y (y=0..15)
7
1
PD8
Port G pull-down bit y (y=0..15)
8
1
PD9
Port G pull-down bit y (y=0..15)
9
1
PDCRH
PDCRH
Power Port H pull-down control register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
PD0
Port H pull-down bit y (y=0..1)
0
1
PD1
Port H pull-down bit y (y=0..1)
1
1
PUCRA
PUCRA
Power Port A pull-up control register
0x20
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port A pull-up bit y (y=0..15)
0
1
PU1
Port A pull-up bit y (y=0..15)
1
1
PU10
Port A pull-up bit y (y=0..15)
10
1
PU11
Port A pull-up bit y (y=0..15)
11
1
PU12
Port A pull-up bit y (y=0..15)
12
1
PU13
Port A pull-up bit y (y=0..15)
13
1
PU14
Port A pull-up bit y (y=0..15)
14
1
PU15
Port A pull-up bit y (y=0..15)
15
1
PU2
Port A pull-up bit y (y=0..15)
2
1
PU3
Port A pull-up bit y (y=0..15)
3
1
PU4
Port A pull-up bit y (y=0..15)
4
1
PU5
Port A pull-up bit y (y=0..15)
5
1
PU6
Port A pull-up bit y (y=0..15)
6
1
PU7
Port A pull-up bit y (y=0..15)
7
1
PU8
Port A pull-up bit y (y=0..15)
8
1
PU9
Port A pull-up bit y (y=0..15)
9
1
PUCRB
PUCRB
Power Port B pull-up control register
0x28
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port B pull-up bit y (y=0..15)
0
1
PU1
Port B pull-up bit y (y=0..15)
1
1
PU10
Port B pull-up bit y (y=0..15)
10
1
PU11
Port B pull-up bit y (y=0..15)
11
1
PU12
Port B pull-up bit y (y=0..15)
12
1
PU13
Port B pull-up bit y (y=0..15)
13
1
PU14
Port B pull-up bit y (y=0..15)
14
1
PU15
Port B pull-up bit y (y=0..15)
15
1
PU2
Port B pull-up bit y (y=0..15)
2
1
PU3
Port B pull-up bit y (y=0..15)
3
1
PU4
Port B pull-up bit y (y=0..15)
4
1
PU5
Port B pull-up bit y (y=0..15)
5
1
PU6
Port B pull-up bit y (y=0..15)
6
1
PU7
Port B pull-up bit y (y=0..15)
7
1
PU8
Port B pull-up bit y (y=0..15)
8
1
PU9
Port B pull-up bit y (y=0..15)
9
1
PUCRC
PUCRC
Power Port C pull-up control register
0x30
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port C pull-up bit y (y=0..15)
0
1
PU1
Port C pull-up bit y (y=0..15)
1
1
PU10
Port C pull-up bit y (y=0..15)
10
1
PU11
Port C pull-up bit y (y=0..15)
11
1
PU12
Port C pull-up bit y (y=0..15)
12
1
PU13
Port C pull-up bit y (y=0..15)
13
1
PU14
Port C pull-up bit y (y=0..15)
14
1
PU15
Port C pull-up bit y (y=0..15)
15
1
PU2
Port C pull-up bit y (y=0..15)
2
1
PU3
Port C pull-up bit y (y=0..15)
3
1
PU4
Port C pull-up bit y (y=0..15)
4
1
PU5
Port C pull-up bit y (y=0..15)
5
1
PU6
Port C pull-up bit y (y=0..15)
6
1
PU7
Port C pull-up bit y (y=0..15)
7
1
PU8
Port C pull-up bit y (y=0..15)
8
1
PU9
Port C pull-up bit y (y=0..15)
9
1
PUCRD
PUCRD
Power Port D pull-up control register
0x38
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port D pull-up bit y (y=0..15)
0
1
PU1
Port D pull-up bit y (y=0..15)
1
1
PU10
Port D pull-up bit y (y=0..15)
10
1
PU11
Port D pull-up bit y (y=0..15)
11
1
PU12
Port D pull-up bit y (y=0..15)
12
1
PU13
Port D pull-up bit y (y=0..15)
13
1
PU14
Port D pull-up bit y (y=0..15)
14
1
PU15
Port D pull-up bit y (y=0..15)
15
1
PU2
Port D pull-up bit y (y=0..15)
2
1
PU3
Port D pull-up bit y (y=0..15)
3
1
PU4
Port D pull-up bit y (y=0..15)
4
1
PU5
Port D pull-up bit y (y=0..15)
5
1
PU6
Port D pull-up bit y (y=0..15)
6
1
PU7
Port D pull-up bit y (y=0..15)
7
1
PU8
Port D pull-up bit y (y=0..15)
8
1
PU9
Port D pull-up bit y (y=0..15)
9
1
PUCRE
PUCRE
Power Port E pull-up control register
0x40
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port E pull-up bit y (y=0..15)
0
1
PU1
Port E pull-up bit y (y=0..15)
1
1
PU10
Port E pull-up bit y (y=0..15)
10
1
PU11
Port E pull-up bit y (y=0..15)
11
1
PU12
Port E pull-up bit y (y=0..15)
12
1
PU13
Port E pull-up bit y (y=0..15)
13
1
PU14
Port E pull-up bit y (y=0..15)
14
1
PU15
Port E pull-up bit y (y=0..15)
15
1
PU2
Port E pull-up bit y (y=0..15)
2
1
PU3
Port E pull-up bit y (y=0..15)
3
1
PU4
Port E pull-up bit y (y=0..15)
4
1
PU5
Port E pull-up bit y (y=0..15)
5
1
PU6
Port E pull-up bit y (y=0..15)
6
1
PU7
Port E pull-up bit y (y=0..15)
7
1
PU8
Port E pull-up bit y (y=0..15)
8
1
PU9
Port E pull-up bit y (y=0..15)
9
1
PUCRF
PUCRF
Power Port F pull-up control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port F pull-up bit y (y=0..15)
0
1
PU1
Port F pull-up bit y (y=0..15)
1
1
PU10
Port F pull-up bit y (y=0..15)
10
1
PU11
Port F pull-up bit y (y=0..15)
11
1
PU12
Port F pull-up bit y (y=0..15)
12
1
PU13
Port F pull-up bit y (y=0..15)
13
1
PU14
Port F pull-up bit y (y=0..15)
14
1
PU15
Port F pull-up bit y (y=0..15)
15
1
PU2
Port F pull-up bit y (y=0..15)
2
1
PU3
Port F pull-up bit y (y=0..15)
3
1
PU4
Port F pull-up bit y (y=0..15)
4
1
PU5
Port F pull-up bit y (y=0..15)
5
1
PU6
Port F pull-up bit y (y=0..15)
6
1
PU7
Port F pull-up bit y (y=0..15)
7
1
PU8
Port F pull-up bit y (y=0..15)
8
1
PU9
Port F pull-up bit y (y=0..15)
9
1
PUCRG
PUCRG
Power Port G pull-up control register
0x50
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port G pull-up bit y (y=0..15)
0
1
PU1
Port G pull-up bit y (y=0..15)
1
1
PU10
Port G pull-up bit y (y=0..15)
10
1
PU11
Port G pull-up bit y (y=0..15)
11
1
PU12
Port G pull-up bit y (y=0..15)
12
1
PU13
Port G pull-up bit y (y=0..15)
13
1
PU14
Port G pull-up bit y (y=0..15)
14
1
PU15
Port G pull-up bit y (y=0..15)
15
1
PU2
Port G pull-up bit y (y=0..15)
2
1
PU3
Port G pull-up bit y (y=0..15)
3
1
PU4
Port G pull-up bit y (y=0..15)
4
1
PU5
Port G pull-up bit y (y=0..15)
5
1
PU6
Port G pull-up bit y (y=0..15)
6
1
PU7
Port G pull-up bit y (y=0..15)
7
1
PU8
Port G pull-up bit y (y=0..15)
8
1
PU9
Port G pull-up bit y (y=0..15)
9
1
PUCRH
PUCRH
Power Port H pull-up control register
0x58
32
read-write
n
0x0
0xFFFFFFFF
PU0
Port H pull-up bit y (y=0..1)
0
1
PU1
Port H pull-up bit y (y=0..1)
1
1
SCR
SCR
Power status clear register
0x18
32
write-only
n
0x0
0xFFFFFFFF
SBF
Clear standby flag
8
1
WUF1
Clear wakeup flag 1
0
1
WUF2
Clear wakeup flag 2
1
1
WUF3
Clear wakeup flag 3
2
1
WUF4
Clear wakeup flag 4
3
1
WUF5
Clear wakeup flag 5
4
1
SR1
SR1
Power status register 1
0x10
32
read-only
n
0x0
0xFFFFFFFF
CSBF
Standby flag
8
1
CWUF1
Wakeup flag 1
0
1
CWUF2
Wakeup flag 2
1
1
CWUF3
Wakeup flag 3
2
1
CWUF4
Wakeup flag 4
3
1
CWUF5
Wakeup flag 5
4
1
WUFI
Wakeup flag internal
15
1
SR2
SR2
Power status register 2
0x14
32
read-only
n
0x0
0xFFFFFFFF
PVDO
Power voltage detector output
11
1
PVMO1
Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
12
1
PVMO2
Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V
13
1
PVMO3
Peripheral voltage monitoring output: VDDA vs. 1.62 V
14
1
PVMO4
Peripheral voltage monitoring output: VDDA vs. 2.2 V
15
1
REGLPF
Low-power regulator flag
9
1
REGLPS
Low-power regulator started
8
1
VOSF
Voltage scaling flag
10
1
RCC
Reset and clock control
RCC
0x40021000
0x0
0x400
registers
n
RCC
RCC global interrupt
5
AHB1ENR
AHB1ENR
AHB1 peripheral clock enable register
0x48
32
read-write
n
0x100
0xFFFFFFFF
CRCEN
CRC clock enable
12
1
DMA1EN
DMA1 clock enable
0
1
DMA2DEN
DMA2D clock enable
17
1
DMA2EN
DMA2 clock enable
1
1
DMAMUX1EN
DMAMUX clock enable
2
1
FLASHEN
Flash memory interface clock enable
8
1
TSCEN
Touch Sensing Controller clock enable
16
1
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x28
32
read-write
n
0x0
0xFFFFFFFF
CRCRST
CRC reset
12
1
DMA1RST
DMA1 reset
0
1
DMA2DRST
DMA2D reset
17
1
DMA2RST
DMA2 reset
1
1
DMAMUX1RST
DMAMUXRST
2
1
FLASHRST
Flash memory interface reset
8
1
TSCRST
Touch Sensing Controller reset
16
1
AHB1SMENR
AHB1SMENR
AHB1 peripheral clocks enable in Sleep and Stop modes register
0x68
32
read-write
n
0x11303
0xFFFFFFFF
CRCSMEN
CRCSMEN
12
1
DMA1SMEN
DMA1 clocks enable during Sleep and Stop modes
0
1
DMA2DSMEN
DMA2D clock enable during Sleep and Stop modes
17
1
DMA2SMEN
DMA2 clocks enable during Sleep and Stop modes
1
1
DMAMUX1SMEN
DMAMUX clock enable during Sleep and Stop modes
2
1
FLASHSMEN
Flash memory interface clocks enable during Sleep and Stop modes
8
1
SRAM1SMEN
SRAM1 interface clocks enable during Sleep and Stop modes
9
1
TSCSMEN
Touch Sensing Controller clocks enable during Sleep and Stop modes
16
1
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
ADCEN
ADC clock enable
13
1
AESEN
AES accelerator clock enable
16
1
DCMIEN
DCMI clock enable
14
1
GPIOAEN
IO port A clock enable
0
1
GPIOBEN
IO port B clock enable
1
1
GPIOCEN
IO port C clock enable
2
1
GPIODEN
IO port D clock enable
3
1
GPIOEEN
IO port E clock enable
4
1
GPIOFEN
IO port F clock enable
5
1
GPIOGEN
IO port G clock enable
6
1
GPIOHEN
IO port H clock enable
7
1
GPIOIEN
IO port I clock enable
8
1
HASHEN
HASH clock enable
17
1
OSPIMEN
OctoSPI IO manager clock enable
20
1
OTGFSEN
OTG full speed clock enable
12
1
RNGEN
Random Number Generator clock enable
18
1
SDMMC1EN
SDMMC1 clock enable
22
1
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ADCRST
ADC reset
13
1
AESRST
AES hardware accelerator reset
16
1
DCMIRST
Digital Camera Interface reset
14
1
GPIOARST
IO port A reset
0
1
GPIOBRST
IO port B reset
1
1
GPIOCRST
IO port C reset
2
1
GPIODRST
IO port D reset
3
1
GPIOERST
IO port E reset
4
1
GPIOFRST
IO port F reset
5
1
GPIOGRST
IO port G reset
6
1
GPIOHRST
IO port H reset
7
1
GPIOIRST
IO port I reset
8
1
HASHRST
Hash reset
17
1
OSPIMRST
OCTOSPI IO manager reset
20
1
OTGFSRST
USB OTG FS reset
12
1
RNGRST
Random number generator reset
18
1
SDMMC1RST
SDMMC1 reset
22
1
AHB2SMENR
AHB2SMENR
AHB2 peripheral clocks enable in Sleep and Stop modes register
0x6C
32
read-write
n
0x532FF
0xFFFFFFFF
ADCFSSMEN
ADC clocks enable during Sleep and Stop modes
13
1
AESSMEN
AES accelerator clocks enable during Sleep and Stop modes
16
1
DCMISMEN
DCMI clock enable during Sleep and Stop modes
14
1
GPIOASMEN
IO port A clocks enable during Sleep and Stop modes
0
1
GPIOBSMEN
IO port B clocks enable during Sleep and Stop modes
1
1
GPIOCSMEN
IO port C clocks enable during Sleep and Stop modes
2
1
GPIODSMEN
IO port D clocks enable during Sleep and Stop modes
3
1
GPIOESMEN
IO port E clocks enable during Sleep and Stop modes
4
1
GPIOFSMEN
IO port F clocks enable during Sleep and Stop modes
5
1
GPIOGSMEN
IO port G clocks enable during Sleep and Stop modes
6
1
GPIOHSMEN
IO port H clocks enable during Sleep and Stop modes
7
1
GPIOISMEN
IO port I clocks enable during Sleep and Stop modes
8
1
HASHSMEN
HASH clock enable during Sleep and Stop modes
17
1
OSPIMSMEN
OctoSPI IO manager clocks enable during Sleep and Stop modes
20
1
OTGFSSMEN
OTG full speed clocks enable during Sleep and Stop modes
12
1
RNGSMEN
Random Number Generator clocks enable during Sleep and Stop modes
18
1
SDMMC1SMEN
SDMMC1 clocks enable during Sleep and Stop modes
22
1
SRAM2SMEN
SRAM2 interface clocks enable during Sleep and Stop modes
9
1
SRAM3SMEN
SRAM2 interface clocks enable during Sleep and Stop modes
10
1
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable register
0x50
32
read-write
n
0x0
0xFFFFFFFF
FMCEN
Flexible memory controller clock enable
0
1
OSPI2EN
OSPI2EN memory interface clock enable
9
1
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x30
32
read-write
n
0x0
0xFFFFFFFF
FMCRST
Flexible memory controller reset
0
1
OSPI2RST
OctOSPI2 memory interface reset
9
1
AHB3SMENR
AHB3SMENR
AHB3 peripheral clocks enable in Sleep and Stop modes register
0x70
32
read-write
n
0x101
0xFFFFFFFF
FMCSMEN
Flexible memory controller clocks enable during Sleep and Stop modes
0
1
OCTOSPI2
OctoSPI2 memory interface clocks enable during Sleep and Stop modes
9
1
APB1ENR1
APB1ENR1
APB1ENR1
0x58
32
read-write
n
0x0
0xFFFFFFFF
CAN1EN
CAN1 clock enable
25
1
CRSEN
Clock Recovery System clock enable
24
1
DAC1EN
DAC1 interface clock enable
29
1
I2C1EN
I2C1 clock enable
21
1
I2C2EN
I2C2 clock enable
22
1
I2C3EN
I2C3 clock enable
23
1
LPTIM1EN
Low power timer 1 clock enable
31
1
OPAMPEN
OPAMP interface clock enable
30
1
PWREN
Power interface clock enable
28
1
RTCAPBEN
RTC APB clock enable
10
1
SP3EN
SPI3 clock enable
15
1
SPI2EN
SPI2 clock enable
14
1
TIM2EN
TIM2 timer clock enable
0
1
TIM3EN
TIM3 timer clock enable
1
1
TIM4EN
TIM4 timer clock enable
2
1
TIM5EN
TIM5 timer clock enable
3
1
TIM6EN
TIM6 timer clock enable
4
1
TIM7EN
TIM7 timer clock enable
5
1
UART4EN
UART4 clock enable
19
1
UART5EN
UART5 clock enable
20
1
USART2EN
USART2 clock enable
17
1
USART3EN
USART3 clock enable
18
1
WWDGEN
Window watchdog clock enable
11
1
APB1ENR2
APB1ENR2
APB1 peripheral clock enable register 2
0x5C
32
read-write
n
0x0
0xFFFFFFFF
I2C4EN
I2C4 clock enable
1
1
LPTIM2EN
LPTIM2EN
5
1
LPUART1EN
Low power UART 1 clock enable
0
1
APB1RSTR1
APB1RSTR1
APB1 peripheral reset register 1
0x38
32
read-write
n
0x0
0xFFFFFFFF
CAN1RST
CAN1 reset
25
1
CRSRST
CRS reset
24
1
DAC1RST
DAC1 interface reset
29
1
I2C1RST
I2C1 reset
21
1
I2C2RST
I2C2 reset
22
1
I2C3RST
I2C3 reset
23
1
LPTIM1RST
Low Power Timer 1 reset
31
1
OPAMPRST
OPAMP interface reset
30
1
PWRRST
Power interface reset
28
1
SPI2RST
SPI2 reset
14
1
SPI3RST
SPI3 reset
15
1
TIM2RST
TIM2 timer reset
0
1
TIM3RST
TIM3 timer reset
1
1
TIM4RST
TIM3 timer reset
2
1
TIM5RST
TIM5 timer reset
3
1
TIM6RST
TIM6 timer reset
4
1
TIM7RST
TIM7 timer reset
5
1
UART4RST
UART4 reset
19
1
UART5RST
UART5 reset
20
1
USART2RST
USART2 reset
17
1
USART3RST
USART3 reset
18
1
APB1RSTR2
APB1RSTR2
APB1 peripheral reset register 2
0x3C
32
read-write
n
0x0
0xFFFFFFFF
I2C4RST
I2C4 reset
1
1
LPTIM2RST
Low-power timer 2 reset
5
1
LPUART1RST
Low-power UART 1 reset
0
1
APB1SMENR1
APB1SMENR1
APB1SMENR1
0x78
32
read-write
n
0xF2FECA3F
0xFFFFFFFF
CAN1SMEN
CAN1 clocks enable during Sleep and Stop modes
25
1
CRSSMEN
CRS clock enable during Sleep and Stop modes
24
1
DAC1SMEN
DAC1 interface clocks enable during Sleep and Stop modes
29
1
I2C1SMEN
I2C1 clocks enable during Sleep and Stop modes
21
1
I2C2SMEN
I2C2 clocks enable during Sleep and Stop modes
22
1
I2C3SMEN
I2C3 clocks enable during Sleep and Stop modes
23
1
LPTIM1SMEN
Low power timer 1 clocks enable during Sleep and Stop modes
31
1
OPAMPSMEN
OPAMP interface clocks enable during Sleep and Stop modes
30
1
PWRSMEN
Power interface clocks enable during Sleep and Stop modes
28
1
RTCAPBSMEN
RTC APB clock enable during Sleep and Stop modes
10
1
SP3SMEN
SPI3 clocks enable during Sleep and Stop modes
15
1
SPI2SMEN
SPI2 clocks enable during Sleep and Stop modes
14
1
TIM2SMEN
TIM2 timer clocks enable during Sleep and Stop modes
0
1
TIM3SMEN
TIM3 timer clocks enable during Sleep and Stop modes
1
1
TIM4SMEN
TIM4 timer clocks enable during Sleep and Stop modes
2
1
TIM5SMEN
TIM5 timer clocks enable during Sleep and Stop modes
3
1
TIM6SMEN
TIM6 timer clocks enable during Sleep and Stop modes
4
1
TIM7SMEN
TIM7 timer clocks enable during Sleep and Stop modes
5
1
UART4SMEN
UART4 clocks enable during Sleep and Stop modes
19
1
UART5SMEN
UART5 clocks enable during Sleep and Stop modes
20
1
USART2SMEN
USART2 clocks enable during Sleep and Stop modes
17
1
USART3SMEN
USART3 clocks enable during Sleep and Stop modes
18
1
WWDGSMEN
Window watchdog clocks enable during Sleep and Stop modes
11
1
APB1SMENR2
APB1SMENR2
APB1 peripheral clocks enable in Sleep and Stop modes register 2
0x7C
32
read-write
n
0x25
0xFFFFFFFF
I2C4SMEN
I2C4 clocks enable during Sleep and Stop modes
1
1
LPTIM2SMEN
LPTIM2SMEN
5
1
LPUART1SMEN
Low power UART 1 clocks enable during Sleep and Stop modes
0
1
APB2ENR
APB2ENR
APB2ENR
0x60
32
read-write
n
0x0
0xFFFFFFFF
DFSDM1EN
DFSDM timer clock enable
24
1
DSIEN
DSI clock enable
27
1
FWEN
Firewall clock enable
7
1
LTDCEN
LCD-TFT clock enable
26
1
SAI1EN
SAI1 clock enable
21
1
SAI2EN
SAI2 clock enable
22
1
SPI1EN
SPI1 clock enable
12
1
SYSCFGEN
SYSCFG clock enable
0
1
TIM15EN
TIM15 timer clock enable
16
1
TIM16EN
TIM16 timer clock enable
17
1
TIM17EN
TIM17 timer clock enable
18
1
TIM1EN
TIM1 timer clock enable
11
1
TIM8EN
TIM8 timer clock enable
13
1
USART1EN
USART1clock enable
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x40
32
read-write
n
0x0
0xFFFFFFFF
DFSDM1RST
Digital filters for sigma-delata modulators (DFSDM) reset
24
1
DSIRST
DSI reset
27
1
LTDCRST
LCD-TFT reset
26
1
SAI1RST
Serial audio interface 1 (SAI1) reset
21
1
SAI2RST
Serial audio interface 2 (SAI2) reset
22
1
SPI1RST
SPI1 reset
12
1
SYSCFGRST
System configuration (SYSCFG) reset
0
1
TIM15RST
TIM15 timer reset
16
1
TIM16RST
TIM16 timer reset
17
1
TIM17RST
TIM17 timer reset
18
1
TIM1RST
TIM1 timer reset
11
1
TIM8RST
TIM8 timer reset
13
1
USART1RST
USART1 reset
14
1
APB2SMENR
APB2SMENR
APB2SMENR
0x80
32
read-write
n
0x1677C01
0xFFFFFFFF
DFSDM1SMEN
DFSDM timer clocks enable during Sleep and Stop modes
24
1
DSISMEN
DSI clocks enable during Sleep and Stop modes
27
1
LTDCSMEN
LCD-TFT timer clocks enable during Sleep and Stop modes
26
1
SAI1SMEN
SAI1 clocks enable during Sleep and Stop modes
21
1
SAI2SMEN
SAI2 clocks enable during Sleep and Stop modes
22
1
SPI1SMEN
SPI1 clocks enable during Sleep and Stop modes
12
1
SYSCFGSMEN
SYSCFG clocks enable during Sleep and Stop modes
0
1
TIM15SMEN
TIM15 timer clocks enable during Sleep and Stop modes
16
1
TIM16SMEN
TIM16 timer clocks enable during Sleep and Stop modes
17
1
TIM17SMEN
TIM17 timer clocks enable during Sleep and Stop modes
18
1
TIM1SMEN
TIM1 timer clocks enable during Sleep and Stop modes
11
1
TIM8SMEN
TIM8 timer clocks enable during Sleep and Stop modes
13
1
USART1SMEN
USART1clocks enable during Sleep and Stop modes
14
1
BDCR
BDCR
BDCR
0x90
32
read-write
n
0x0
0xFFFFFFFF
BDRST
Backup domain software reset
16
1
read-write
LSCOEN
Low speed clock output enable
24
1
read-write
LSCOSEL
Low speed clock output selection
25
1
read-write
LSEBYP
LSE oscillator bypass
2
1
read-write
LSECSSD
LSECSSD
6
1
read-only
LSECSSON
LSECSSON
5
1
read-write
LSEDRV
SE oscillator drive capability
3
2
read-write
LSEON
LSE oscillator enable
0
1
read-write
LSERDY
LSE oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL
RTC clock source selection
8
2
read-write
CCIPR
CCIPR
CCIPR
0x88
32
read-write
n
0x0
0xFFFFFFFF
ADCSEL
ADCs clock source selection
28
2
CLK48SEL
48 MHz clock source selection
26
2
I2C1SEL
I2C1 clock source selection
12
2
I2C2SEL
I2C2 clock source selection
14
2
I2C3SEL
I2C3 clock source selection
16
2
LPTIM1SEL
Low power timer 1 clock source selection
18
2
LPTIM2SEL
Low power timer 2 clock source selection
20
2
LPUART1SEL
LPUART1 clock source selection
10
2
SAI1SEL
SAI1 clock source selection
22
2
SAI2SEL
SAI2 clock source selection
24
2
UART4SEL
UART4 clock source selection
6
2
UART5SEL
UART5 clock source selection
8
2
USART1SEL
USART1 clock source selection
0
2
USART2SEL
USART2 clock source selection
2
2
USART3SEL
USART3 clock source selection
4
2
CCIPR2
CCIPR2
Peripherals independent clock configuration register
0x9C
32
read-write
n
0x0
0xFFFFFFFF
ADFSDMSEL
Digital filter for sigma delta modulator audio clock source selection
3
2
DFSDMSEL
Digital filter for sigma delta modulator kernel clock source selection
2
1
DSISEL
clock selection
12
1
I2C4SEL
I2C4 clock source selection
0
2
OSPISEL
Octospi clock source selection
20
2
PLLSAI2DIVR
division factor for LTDC clock
16
2
SAI1SEL
SAI1 clock source selection
5
3
SAI2SEL
SAI2 clock source selection
8
3
SDMMCSEL
SDMMC clock selection
14
1
CFGR
CFGR
Clock configuration register
0x8
32
read-write
n
0x0
0xFFFFFFFF
HPRE
AHB prescaler
4
4
read-write
MCOPRE
Microcontroller clock output prescaler
28
3
read-only
MCOSEL
Microcontroller clock output
24
3
read-write
PPRE1
PB low-speed prescaler (APB1)
8
3
read-write
PPRE2
APB high-speed prescaler (APB2)
11
3
read-write
STOPWUCK
Wakeup from Stop and CSS backup clock selection
15
1
read-write
SW
System clock switch
0
2
read-write
SWS
System clock switch status
2
2
read-only
CICR
CICR
Clock interrupt clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CSSC
Clock security system interrupt clear
8
1
HSERDYC
HSE ready interrupt clear
4
1
HSI48RDYC
HSI48 oscillator ready interrupt clear
10
1
HSIRDYC
HSI ready interrupt clear
3
1
LSECSSC
LSE Clock security system interrupt clear
9
1
LSERDYC
LSE ready interrupt clear
1
1
LSIRDYC
LSI ready interrupt clear
0
1
MSIRDYC
MSI ready interrupt clear
2
1
PLLRDYC
PLL ready interrupt clear
5
1
PLLSAI1RDYC
PLLSAI1 ready interrupt clear
6
1
PLLSAI2RDYC
PLLSAI2 ready interrupt clear
7
1
CIER
CIER
Clock interrupt enable register
0x18
32
read-write
n
0x0
0xFFFFFFFF
HSERDYIE
HSE ready interrupt enable
4
1
HSI48RDYIE
HSI48 ready interrupt enable
10
1
HSIRDYIE
HSI ready interrupt enable
3
1
LSECSSIE
LSE clock security system interrupt enable
9
1
LSERDYIE
LSE ready interrupt enable
1
1
LSIRDYIE
LSI ready interrupt enable
0
1
MSIRDYIE
MSI ready interrupt enable
2
1
PLLRDYIE
PLL ready interrupt enable
5
1
PLLSAI1RDYIE
PLLSAI1 ready interrupt enable
6
1
PLLSAI2RDYIE
PLLSAI2 ready interrupt enable
7
1
CIFR
CIFR
Clock interrupt flag register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CSSF
Clock security system interrupt flag
8
1
HSERDYF
HSE ready interrupt flag
4
1
HSI48RDYF
HSI48 ready interrupt flag
10
1
HSIRDYF
HSI ready interrupt flag
3
1
LSECSSF
LSE Clock security system interrupt flag
9
1
LSERDYF
LSE ready interrupt flag
1
1
LSIRDYF
LSI ready interrupt flag
0
1
MSIRDYF
MSI ready interrupt flag
2
1
PLLRDYF
PLL ready interrupt flag
5
1
PLLSAI1RDYF
PLLSAI1 ready interrupt flag
6
1
PLLSAI2RDYF
PLLSAI2 ready interrupt flag
7
1
CR
CR
Clock control register
0x0
32
read-write
n
0x63
0xFFFFFFFF
CSSON
Clock security system enable
19
1
write-only
HSEBYP
HSE crystal oscillator bypass
18
1
read-write
HSEON
HSE clock enable
16
1
read-write
HSERDY
HSE clock ready flag
17
1
read-only
HSIASFS
HSI automatic start from Stop
11
1
read-write
HSIKERON
HSI always enable for peripheral kernels
9
1
read-write
HSION
HSI clock enable
8
1
read-write
HSIRDY
HSI clock ready flag
10
1
read-only
MSION
MSI clock enable
0
1
read-write
MSIPLLEN
MSI clock PLL enable
2
1
read-write
MSIRANGE
MSI clock ranges
4
4
read-write
MSIRDY
MSI clock ready flag
1
1
read-only
MSIRGSEL
MSI clock range selection
3
1
write-only
PLLON
Main PLL enable
24
1
read-write
PLLRDY
Main PLL clock ready flag
25
1
read-only
PLLSAI1ON
SAI1 PLL enable
26
1
read-write
PLLSAI1RDY
SAI1 PLL clock ready flag
27
1
read-only
PLLSAI2ON
SAI2 PLL enable
28
1
read-write
PLLSAI2RDY
SAI2 PLL clock ready flag
29
1
read-only
CRRCR
CRRCR
Clock recovery RC register
0x98
32
read-write
n
0x0
0xFFFFFFFF
HSI48CAL
HSI48 clock calibration
7
9
read-only
HSI48ON
HSI48 clock enable
0
1
read-write
HSI48RDY
HSI48 clock ready flag
1
1
read-only
CSR
CSR
CSR
0x94
32
read-write
n
0xC000600
0xFFFFFFFF
BORRSTF
BOR flag
27
1
read-only
FWRSTF
Firewall reset flag
24
1
read-only
IWDGRSTF
Independent window watchdog reset flag
29
1
read-only
LPWRSTF
Low-power reset flag
31
1
read-only
LSION
LSI oscillator enable
0
1
read-write
LSIRDY
LSI oscillator ready
1
1
read-only
MSISRANGE
SI range after Standby mode
8
4
read-write
OBLRSTF
Option byte loader reset flag
25
1
read-only
PINRSTF
Pin reset flag
26
1
read-only
RMVF
Remove reset flag
23
1
read-write
SFTRSTF
Software reset flag
28
1
read-only
WWDGRSTF
Window watchdog reset flag
30
1
read-only
ICSCR
ICSCR
Internal clock sources calibration register
0x4
32
read-write
n
0x10000000
0xFFFFFFFF
HSICAL
HSI clock calibration
16
8
read-only
HSITRIM
HSI clock trimming
24
7
read-write
MSICAL
MSI clock calibration
0
8
read-only
MSITRIM
MSI clock trimming
8
8
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0xC
32
read-write
n
0x1000
0xFFFFFFFF
PLLM
Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
4
4
PLLN
Main PLL multiplication factor for VCO
8
7
PLLP
Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
17
1
PLLPDIV
Main PLL division factor for PLLSAI2CLK
27
5
PLLPEN
Main PLL PLLSAI3CLK output enable
16
1
PLLQ
Main PLL division factor for PLLUSB1CLK(48 MHz clock)
21
2
PLLQEN
Main PLL PLLUSB1CLK output enable
20
1
PLLR
Main PLL division factor for PLLCLK (system clock)
25
2
PLLREN
Main PLL PLLCLK output enable
24
1
PLLSRC
Main PLL, PLLSAI1 and PLLSAI2 entry clock source
0
2
PLLSAI1CFGR
PLLSAI1CFGR
PLLSAI1 configuration register
0x10
32
read-write
n
0x1000
0xFFFFFFFF
PLLSAI1M
Division factor for PLLSAI1 input clock
4
4
PLLSAI1N
SAI1PLL multiplication factor for VCO
8
7
PLLSAI1P
SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
17
1
PLLSAI1PDIV
PLLSAI1 division factor for PLLSAI1CLK
27
5
PLLSAI1PEN
SAI1PLL PLLSAI1CLK output enable
16
1
PLLSAI1Q
SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
21
2
PLLSAI1QEN
SAI1PLL PLLUSB2CLK output enable
20
1
PLLSAI1R
PLLSAI1 division factor for PLLADC1CLK (ADC clock)
25
2
PLLSAI1REN
PLLSAI1 PLLADC1CLK output enable
24
1
PLLSAI2CFGR
PLLSAI2CFGR
PLLSAI2 configuration register
0x14
32
read-write
n
0x1000
0xFFFFFFFF
PLLSAI2M
Division factor for PLLSAI2 input clock
4
4
PLLSAI2N
SAI2PLL multiplication factor for VCO
8
7
PLLSAI2P
SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
17
1
PLLSAI2PDIV
PLLSAI2 division factor for PLLSAI2CLK
27
5
PLLSAI2PEN
SAI2PLL PLLSAI2CLK output enable
16
1
PLLSAI2Q
SAI2PLL PLLSAI2CLK output enable
21
2
PLLSAI2QEN
PLLSAI2 division factor for PLLDISCLK
20
1
PLLSAI2R
PLLSAI2 division factor for PLLADC2CLK (ADC clock)
25
2
PLLSAI2REN
PLLSAI2 PLLADC2CLK output enable
24
1
RNG
Random number generator
RNG
0x50060800
0x0
0x400
registers
n
RNG_HASH
RNG and HASH global interrupt
80
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
IE
Interrupt enable
3
1
RNGEN
Random number generator enable
2
1
DR
DR
data register
0x8
32
read-only
n
0x0
0xFFFFFFFF
RNDATA
Random data
0
32
SR
SR
status register
0x4
32
read-write
n
0x0
0xFFFFFFFF
CECS
Clock error current status
1
1
read-only
CEIS
Clock error interrupt status
5
1
read-write
DRDY
Data ready
0
1
read-only
SECS
Seed error current status
2
1
read-only
SEIS
Seed error interrupt status
6
1
read-write
RTC
Real-time clock
RTC
0x40002800
0x0
0x400
registers
n
TAMP_STAMP
Tamper and TimeStamp interrupts
2
RTC_WKUP
RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts
3
RTC_ALARM
RTC alarms through EXTI line 18 interrupts
41
ALRMAR
ALRMAR
alarm A register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
alarm A sub second register
0x44
32
read-write
n
0x0
0xFFFFFFFF
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
ALRMBR
ALRMBR
alarm B register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
alarm B sub second register
0x48
32
read-write
n
0x0
0xFFFFFFFF
MASKSS
Mask the most-significant bits starting at this bit
24
4
SS
Sub seconds value
0
15
BKP0R
BKP0R
backup register
0x50
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP10R
BKP10R
backup register
0x78
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP11R
BKP11R
backup register
0x7C
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP12R
BKP12R
backup register
0x80
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP13R
BKP13R
backup register
0x84
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP14R
BKP14R
backup register
0x88
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP15R
BKP15R
backup register
0x8C
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP16R
BKP16R
backup register
0x90
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP17R
BKP17R
backup register
0x94
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP18R
BKP18R
backup register
0x98
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP19R
BKP19R
backup register
0x9C
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP1R
BKP1R
backup register
0x54
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP20R
BKP20R
backup register
0xA0
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP21R
BKP21R
backup register
0xA4
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP22R
BKP22R
backup register
0xA8
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP23R
BKP23R
backup register
0xAC
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP24R
BKP24R
backup register
0xB0
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP25R
BKP25R
backup register
0xB4
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP26R
BKP26R
backup register
0xB8
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP27R
BKP27R
backup register
0xBC
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP28R
BKP28R
backup register
0xC0
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP29R
BKP29R
backup register
0xC4
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP2R
BKP2R
backup register
0x58
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP30R
BKP30R
backup register
0xC8
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP31R
BKP31R
backup register
0xCC
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP3R
BKP3R
backup register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP4R
BKP4R
backup register
0x60
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP5R
BKP5R
backup register
0x64
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP6R
BKP6R
backup register
0x68
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP7R
BKP7R
backup register
0x6C
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP8R
BKP8R
backup register
0x70
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
BKP9R
BKP9R
backup register
0x74
32
read-write
n
0x0
0xFFFFFFFF
BKP
BKP
0
32
CALR
CALR
calibration register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CALM
Calibration minus
0
9
CALP
Increase frequency of RTC by 488.5 ppm
15
1
CALW16
Use a 16-second calibration cycle period
13
1
CALW8
Use an 8-second calibration cycle period
14
1
CR
CR
control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ADD1H
Add 1 hour (summer time change)
16
1
ALRAE
Alarm A enable
8
1
ALRAIE
Alarm A interrupt enable
12
1
ALRBE
Alarm B enable
9
1
ALRBIE
Alarm B interrupt enable
13
1
BKP
Backup
18
1
BYPSHAD
Bypass the shadow registers
5
1
COE
Calibration output enable
23
1
COSEL
Calibration output selection
19
1
FMT
Hour format
6
1
ITSE
timestamp on internal event enable
24
1
OSEL
Output selection
21
2
POL
Output polarity
20
1
REFCKON
Reference clock detection enable (50 or 60 Hz)
4
1
SUB1H
Subtract 1 hour (winter time change)
17
1
TSE
Time stamp enable
11
1
TSEDGE
Time-stamp event active edge
3
1
TSIE
Time-stamp interrupt enable
15
1
WCKSEL
Wakeup clock selection
0
3
WUTE
Wakeup timer enable
10
1
WUTIE
Wakeup timer interrupt enable
14
1
DR
DR
date register
0x4
32
read-write
n
0x2101
0xFFFFFFFF
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ISR
ISR
initialization and status register
0xC
32
read-write
n
0x7
0xFFFFFFFF
ALRAF
Alarm A flag
8
1
read-write
ALRAWF
Alarm A write flag
0
1
read-only
ALRBF
Alarm B flag
9
1
read-write
ALRBWF
Alarm B write flag
1
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RECALPF
Recalibration pending Flag
16
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-write
TAMP1F
Tamper detection flag
13
1
read-write
TAMP2F
RTC_TAMP2 detection flag
14
1
read-write
TAMP3F
RTC_TAMP3 detection flag
15
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
WUTF
Wakeup timer flag
10
1
read-write
WUTWF
Wakeup timer write flag
2
1
read-only
OR
OR
option register
0x4C
32
read-write
n
0x0
0xFFFFFFFF
RTC_ALARM_TYPE
RTC_ALARM on PC13 output type
0
1
RTC_OUT_RMP
RTC_OUT remap
1
1
PRER
PRER
prescaler register
0x10
32
read-write
n
0x7F00FF
0xFFFFFFFF
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
15
SHIFTR
SHIFTR
shift control register
0x2C
32
write-only
n
0x0
0xFFFFFFFF
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SSR
SSR
sub second register
0x28
32
read-only
n
0x0
0xFFFFFFFF
SS
Sub second value
0
16
TAMPCR
TAMPCR
tamper configuration register
0x40
32
read-write
n
0x0
0xFFFFFFFF
TAMP1E
Tamper 1 detection enable
0
1
TAMP1IE
Tamper 1 interrupt enable
16
1
TAMP1MF
Tamper 1 mask flag
18
1
TAMP1NOERASE
Tamper 1 no erase
17
1
TAMP1TRG
Active level for tamper 1
1
1
TAMP2E
Tamper 2 detection enable
3
1
TAMP2IE
Tamper 2 interrupt enable
19
1
TAMP2MF
Tamper 2 mask flag
21
1
TAMP2NOERASE
Tamper 2 no erase
20
1
TAMP2TRG
Active level for tamper 2
4
1
TAMP3E
Tamper 3 detection enable
5
1
TAMP3IE
Tamper 3 interrupt enable
22
1
TAMP3MF
Tamper 3 mask flag
24
1
TAMP3NOERASE
Tamper 3 no erase
23
1
TAMP3TRG
Active level for tamper 3
6
1
TAMPFLT
Tamper filter count
11
2
TAMPFREQ
Tamper sampling frequency
8
3
TAMPIE
Tamper interrupt enable
2
1
TAMPPRCH
Tamper precharge duration
13
2
TAMPPUDIS
TAMPER pull-up disable
15
1
TAMPTS
Activate timestamp on tamper detection event
7
1
TR
TR
time register
0x0
32
read-write
n
0x0
0xFFFFFFFF
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
time stamp date register
0x34
32
read-only
n
0x0
0xFFFFFFFF
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
timestamp sub second register
0x38
32
read-only
n
0x0
0xFFFFFFFF
SS
Sub second value
0
16
TSTR
TSTR
time stamp time register
0x30
32
read-only
n
0x0
0xFFFFFFFF
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0xFFFFFFFF
KEY
Write protection key
0
8
WUTR
WUTR
wakeup timer register
0x14
32
read-write
n
0xFFFF
0xFFFFFFFF
WUT
Wakeup auto-reload value bits
0
16
SAI1
Serial audio interface
SAI
0x40015400
0x0
0x400
registers
n
SAI1
SAI1 global interrupt
74
ACLRFR
ACLRFR
AClear flag register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CAFSDET
Clear anticipated frame synchronization detection flag
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
ACR1
ACR1
AConfiguration register 1
0x4
32
read-write
n
0x40
0xFFFFFFFF
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIAEN
Audio block A enable
16
1
SYNCEN
Synchronization enable
10
2
ACR2
ACR2
AConfiguration register 2
0x8
32
read-write
n
0x0
0xFFFFFFFF
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
ADR
ADR
AData register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
AFRCR
AFRCR
AFRCR
0xC
32
read-write
n
0x7
0xFFFFFFFF
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
AIM
AIM
AInterrupt mask register2
0x14
32
read-write
n
0x0
0xFFFFFFFF
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDET
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
ASLOTR
ASLOTR
ASlot register
0x10
32
read-write
n
0x0
0xFFFFFFFF
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
ASR
ASR
AStatus register
0x18
32
read-write
n
0x0
0xFFFFFFFF
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag. This bit is read only
2
1
BCLRFR
BCLRFR
BClear flag register
0x3C
32
write-only
n
0x0
0xFFFFFFFF
CAFSDET
Clear anticipated frame synchronization detection flag
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
BCR1
BCR1
BConfiguration register 1
0x24
32
read-write
n
0x40
0xFFFFFFFF
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIBEN
Audio block B enable
16
1
SYNCEN
Synchronization enable
10
2
BCR2
BCR2
BConfiguration register 2
0x28
32
read-write
n
0x0
0xFFFFFFFF
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
BDR
BDR
BData register
0x40
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
BFRCR
BFRCR
BFRCR
0x2C
32
read-write
n
0x7
0xFFFFFFFF
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
BIM
BIM
BInterrupt mask register2
0x34
32
read-write
n
0x0
0xFFFFFFFF
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDETIE
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
BSLOTR
BSLOTR
BSlot register
0x30
32
read-write
n
0x0
0xFFFFFFFF
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
BSR
BSR
BStatus register
0x38
32
read-only
n
0x0
0xFFFFFFFF
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag
2
1
SAI2
Serial audio interface
SAI
0x40015800
0x0
0x400
registers
n
SAI2
SAI2 global interrupt
75
ACLRFR
ACLRFR
AClear flag register
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CAFSDET
Clear anticipated frame synchronization detection flag
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
ACR1
ACR1
AConfiguration register 1
0x4
32
read-write
n
0x40
0xFFFFFFFF
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIAEN
Audio block A enable
16
1
SYNCEN
Synchronization enable
10
2
ACR2
ACR2
AConfiguration register 2
0x8
32
read-write
n
0x0
0xFFFFFFFF
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
ADR
ADR
AData register
0x20
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
AFRCR
AFRCR
AFRCR
0xC
32
read-write
n
0x7
0xFFFFFFFF
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
AIM
AIM
AInterrupt mask register2
0x14
32
read-write
n
0x0
0xFFFFFFFF
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDET
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
ASLOTR
ASLOTR
ASlot register
0x10
32
read-write
n
0x0
0xFFFFFFFF
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
ASR
ASR
AStatus register
0x18
32
read-write
n
0x0
0xFFFFFFFF
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag. This bit is read only
2
1
BCLRFR
BCLRFR
BClear flag register
0x3C
32
write-only
n
0x0
0xFFFFFFFF
CAFSDET
Clear anticipated frame synchronization detection flag
5
1
CNRDY
Clear codec not ready flag
4
1
LFSDET
Clear late frame synchronization detection flag
6
1
MUTEDET
Mute detection flag
1
1
OVRUDR
Clear overrun / underrun
0
1
WCKCFG
Clear wrong clock configuration flag
2
1
BCR1
BCR1
BConfiguration register 1
0x24
32
read-write
n
0x40
0xFFFFFFFF
CKSTR
Clock strobing edge
9
1
DMAEN
DMA enable
17
1
DS
Data size
5
3
LSBFIRST
Least significant bit first
8
1
MCJDIV
Master clock divider
20
4
MODE
Audio block mode
0
2
MONO
Mono mode
12
1
NODIV
No divider
19
1
OutDri
Output drive
13
1
PRTCFG
Protocol configuration
2
2
SAIBEN
Audio block B enable
16
1
SYNCEN
Synchronization enable
10
2
BCR2
BCR2
BConfiguration register 2
0x28
32
read-write
n
0x0
0xFFFFFFFF
COMP
Companding mode
14
2
CPL
Complement bit
13
1
FFLUS
FIFO flush
3
1
FTH
FIFO threshold
0
3
MUTE
Mute
5
1
MUTECN
Mute counter
7
6
MUTEVAL
Mute value
6
1
TRIS
Tristate management on data line
4
1
BDR
BDR
BData register
0x40
32
read-write
n
0x0
0xFFFFFFFF
DATA
Data
0
32
BFRCR
BFRCR
BFRCR
0x2C
32
read-write
n
0x7
0xFFFFFFFF
FRL
Frame length
0
8
FSALL
Frame synchronization active level length
8
7
FSDEF
Frame synchronization definition
16
1
FSOFF
Frame synchronization offset
18
1
FSPOL
Frame synchronization polarity
17
1
BIM
BIM
BInterrupt mask register2
0x34
32
read-write
n
0x0
0xFFFFFFFF
AFSDETIE
Anticipated frame synchronization detection interrupt enable
5
1
CNRDYIE
Codec not ready interrupt enable
4
1
FREQIE
FIFO request interrupt enable
3
1
LFSDETIE
Late frame synchronization detection interrupt enable
6
1
MUTEDET
Mute detection interrupt enable
1
1
OVRUDRIE
Overrun/underrun interrupt enable
0
1
WCKCFG
Wrong clock configuration interrupt enable
2
1
BSLOTR
BSLOTR
BSlot register
0x30
32
read-write
n
0x0
0xFFFFFFFF
FBOFF
First bit offset
0
5
NBSLOT
Number of slots in an audio frame
8
4
SLOTEN
Slot enable
16
16
SLOTSZ
Slot size
6
2
BSR
BSR
BStatus register
0x38
32
read-only
n
0x0
0xFFFFFFFF
AFSDET
Anticipated frame synchronization detection
5
1
CNRDY
Codec not ready
4
1
FLVL
FIFO level threshold
16
3
FREQ
FIFO request
3
1
LFSDET
Late frame synchronization detection
6
1
MUTEDET
Mute detection
1
1
OVRUDR
Overrun / underrun
0
1
WCKCFG
Wrong clock configuration flag
2
1
SCB
System control block
SCB
0xE000ED00
0x0
0x41
registers
n
AFSR
AFSR
Auxiliary fault status register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
IMPDEF
Implementation defined
0
32
AIRCR
AIRCR
Application interrupt and reset control register
0xC
32
read-write
n
0x0
0xFFFFFFFF
ENDIANESS
ENDIANESS
15
1
PRIGROUP
PRIGROUP
8
3
SYSRESETREQ
SYSRESETREQ
2
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
VECTKEYSTAT
Register key
16
16
VECTRESET
VECTRESET
0
1
BFAR
BFAR
Bus fault address register
0x38
32
read-write
n
0x0
0xFFFFFFFF
BFAR
Bus fault address
0
32
CCR
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BFHFNMIGN
BFHFNMIGN
8
1
DIV_0_TRP
DIV_0_TRP
4
1
NONBASETHRDENA
Configures how the processor enters Thread mode
0
1
STKALIGN
STKALIGN
9
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
USERSETMPEND
USERSETMPEND
1
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status register
0x28
32
read-write
n
0x0
0xFFFFFFFF
BFARVALID
Bus Fault Address Register (BFAR) valid flag
15
1
DIVBYZERO
Divide by zero usage fault
25
1
IACCVIOL
Instruction access violation flag
1
1
IBUSERR
Instruction bus error
8
1
IMPRECISERR
Imprecise data bus error
10
1
INVPC
Invalid PC load usage fault
18
1
INVSTATE
Invalid state usage fault
17
1
LSPERR
Bus fault on floating-point lazy state preservation
13
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register (MMAR) valid flag
7
1
MSTKERR
Memory manager fault on stacking for exception entry.
4
1
MUNSTKERR
Memory manager fault on unstacking for a return from exception
3
1
NOCP
No coprocessor usage fault.
19
1
PRECISERR
Precise data bus error
9
1
STKERR
Bus fault on stacking for exception entry
12
1
UNALIGNED
Unaligned access usage fault
24
1
UNDEFINSTR
Undefined instruction usage fault
16
1
UNSTKERR
Bus fault on unstacking for a return from exception
11
1
CPUID
CPUID
CPUID base register
0x0
32
read-only
n
0x410FC241
0xFFFFFFFF
Constant
Reads as 0xF
16
4
Implementer
Implementer code
24
8
PartNo
Part number of the processor
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
HFSR
HFSR
Hard fault status register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
DEBUG_VT
Reserved for Debug use
31
1
FORCED
Forced hard fault
30
1
VECTTBL
Vector table hard fault
1
1
ICSR
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0xFFFFFFFF
ISRPENDING
Interrupt pending flag
22
1
NMIPENDSET
NMI set-pending bit.
31
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
RETTOBASE
Return to base level
11
1
VECTACTIVE
Active vector
0
9
VECTPENDING
Pending vector
12
7
MMFAR
MMFAR
Memory management fault address register
0x34
32
read-write
n
0x0
0xFFFFFFFF
MMFAR
Memory management fault address
0
32
SCR
SCR
System control register
0x10
32
read-write
n
0x0
0xFFFFFFFF
SEVEONPEND
Send Event on Pending bit
4
1
SLEEPDEEP
SLEEPDEEP
2
1
SLEEPONEXIT
SLEEPONEXIT
1
1
SHCSR
SHCSR
System handler control and state register
0x24
32
read-write
n
0x0
0xFFFFFFFF
BUSFAULTACT
Bus fault exception active bit
1
1
BUSFAULTENA
Bus fault enable bit
17
1
BUSFAULTPENDED
Bus fault exception pending bit
14
1
MEMFAULTACT
Memory management fault exception active bit
0
1
MEMFAULTENA
Memory management fault enable bit
16
1
MEMFAULTPENDED
Memory management fault exception pending bit
13
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active bit
10
1
SVCALLACT
SVC call active bit
7
1
SVCALLPENDED
SVC call pending bit
15
1
SYSTICKACT
SysTick exception active bit
11
1
USGFAULTACT
Usage fault exception active bit
3
1
USGFAULTENA
Usage fault enable bit
18
1
USGFAULTPENDED
Usage fault exception pending bit
12
1
SHPR1
SHPR1
System handler priority registers
0x18
32
read-write
n
0x0
0xFFFFFFFF
PRI_4
Priority of system handler 4
0
8
PRI_5
Priority of system handler 5
8
8
PRI_6
Priority of system handler 6
16
8
SHPR2
SHPR2
System handler priority registers
0x1C
32
read-write
n
0x0
0xFFFFFFFF
PRI_11
Priority of system handler 11
24
8
SHPR3
SHPR3
System handler priority registers
0x20
32
read-write
n
0x0
0xFFFFFFFF
PRI_14
Priority of system handler 14
16
8
PRI_15
Priority of system handler 15
24
8
VTOR
VTOR
Vector table offset register
0x8
32
read-write
n
0x0
0xFFFFFFFF
TBLOFF
Vector table base offset field
9
21
SCB_ACTRL
System control block ACTLR
SCB
0xE000E008
0x0
0x5
registers
n
ACTRL
ACTRL
Auxiliary control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISMCYCINT
DISMCYCINT
0
1
DISOOFP
DISOOFP
9
1
SDMMC1
Secure digital input/output interface 1
SDIO
0x50062400
0x0
0x400
registers
n
SDMMC1
SDMMC1 global Interrupt
49
ACKTIMER
ACKTIMER
acknowledgment timer register
0x40
32
read-write
n
0x0
0xFFFFFFFF
ACKTIME
Boot acknowledgment timeout period
0
25
ARGR
ARGR
argument register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CMDARG
Command argument
0
32
CLKCR
CLKCR
SDI clock control register
0x4
32
read-write
n
0x0
0xFFFFFFFF
BUSSPEED
Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50
19
1
CLKDIV
Clock divide factor
0
10
DDR
Data rate signaling selection
18
1
HWFC_EN
Hardware flow control enable
17
1
NEGEDGE
SDMMC_CK dephasing selection bit for data and command
16
1
PWRSAV
Power saving configuration bit
12
1
SELCLKRX
Receive clock selection
20
2
WIDBUS
Wide bus mode enable bit
14
2
CMDR
CMDR
command register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BOOTEN
Enable boot mode procedure
15
1
BOOTMODE
Select the boot mode procedure to be used
14
1
CMDINDEX
Command index
0
6
CMDSTOP
The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
7
1
CMDSUSPEND
The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
16
1
CMDTRANS
The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM
6
1
CPSMEN
Command path state machine (CPSM) Enable bit
12
1
DTHOLD
Hold new data block transmission and reception in the DPSM
13
1
WAITINT
CPSM waits for interrupt request
10
1
WAITPEND
CPSM Waits for ends of data transfer (CmdPend internal signal)
11
1
WAITRESP
Wait for response bits
8
2
DCNTR
DCNTR
data counter register
0x30
32
read-only
n
0x0
0xFFFFFFFF
DATACOUNT
Data count value
0
25
DCTRL
DCTRL
data control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
BOOTACKEN
Enable the reception of the boot acknowledgment
12
1
DBLOCKSIZE
Data block size
4
4
DTDIR
Data transfer direction selection
1
1
DTEN
DTEN
0
1
DTMODE
Data transfer mode selection 1: Stream or SDIO multibyte data transfer
2
2
FIFORST
FIFO reset, will flush any remaining data
13
1
RWMOD
Read wait mode
10
1
RWSTART
Read wait start
8
1
RWSTOP
Read wait stop
9
1
SDIOEN
SD I/O enable functions
11
1
DLENR
DLENR
data length register
0x28
32
read-write
n
0x0
0xFFFFFFFF
DATALENGTH
Data length value
0
25
DTIMER
DTIMER
data timer register
0x24
32
read-write
n
0x0
0xFFFFFFFF
DATATIME
Data timeout period
0
32
FIFOR0
FIFOR0
data FIFO register 0
0x80
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR1
FIFOR1
data FIFO register 1
0x84
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR10
FIFOR10
data FIFO register 10
0xA8
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR11
FIFOR11
data FIFO register 11
0xAC
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR12
FIFOR12
data FIFO register 12
0xB0
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR13
FIFOR13
data FIFO register 13
0xB4
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR14
FIFOR14
data FIFO register 14
0xB8
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR15
FIFOR15
data FIFO register 15
0xBC
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR2
FIFOR2
data FIFO register 2
0x88
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR3
FIFOR3
data FIFO register 3
0x8C
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR4
FIFOR4
data FIFO register 4
0x90
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR5
FIFOR5
data FIFO register 5
0x94
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR6
FIFOR6
data FIFO register 6
0x98
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR7
FIFOR7
data FIFO register 7
0x9C
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR8
FIFOR8
data FIFO register 8
0xA0
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR9
FIFOR9
data FIFO register 9
0xA4
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
ICR
ICR
interrupt clear register
0x38
32
read-write
n
0x0
0xFFFFFFFF
ACKFAILC
ACKFAIL flag clear bit
23
1
ACKTIMEOUTC
ACKTIMEOUT flag clear bit
24
1
BUSYD0ENDC
BUSYD0END flag clear bit
21
1
CCRCFAILC
CCRCFAIL flag clear bit
0
1
CKSTOPC
CKSTOP flag clear bit
26
1
CMDRENDC
CMDREND flag clear bit
6
1
CMDSENTC
CMDSENT flag clear bit
7
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DABORTC
DABORT flag clear bit
11
1
DATAENDC
DATAEND flag clear bit
8
1
DBCKENDC
DBCKEND flag clear bit
10
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
DHOLDC
DHOLD flag clear bit
9
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
IDMABTCC
IDMA buffer transfer complete clear bit
28
1
IDMATEC
IDMA transfer error clear bit
27
1
RXOVERRC
RXOVERR flag clear bit
5
1
SDIOITC
SDIOIT flag clear bit
22
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
VSWENDC
VSWEND flag clear bit
25
1
IDMABASE0R
IDMABASE0R
IDMA buffer 0 base address register
0x58
32
read-write
n
0x0
0xFFFFFFFF
IDMABASE0
Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only)
0
32
IDMABASE1R
IDMABASE1R
IDMA buffer 0 base address register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
IDMABASE1
Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only)
0
32
IDMABSIZER
IDMABSIZER
IDMA buffer size register
0x54
32
read-write
n
0x0
0xFFFFFFFF
IDMABNDT
Number of bytes per buffer
5
8
IDMACTRLR
IDMACTRLR
DMA control register
0x50
32
read-write
n
0x0
0xFFFFFFFF
IDMABACT
Double buffer mode active buffer indication
2
1
IDMABMODE
Buffer mode selection
1
1
IDMAEN
IDMA enable
0
1
MASKR
MASKR
mask register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
ACKFAILIE
Acknowledgment Fail interrupt enable
23
1
ACKTIMEOUTIE
Acknowledgment timeout interrupt enable
24
1
BUSYD0ENDIE
BUSYD0END interrupt enable
21
1
CCRCFAILIE
Command CRC fail interrupt enable
0
1
CKSTOPIE
CKSTOPIE
26
1
CMDRENDIE
Command response received interrupt enable
6
1
CMDSENTIE
Command sent interrupt enable
7
1
CTIMEOUTIE
Command timeout interrupt enable
2
1
DABORTIE
Data transfer aborted interrupt enable
11
1
DATAENDIE
Data end interrupt enable
8
1
DBCKENDIE
Data block end interrupt enable
10
1
DCRCFAILIE
Data CRC fail interrupt enable
1
1
DHOLDIE
Data hold interrupt enable
9
1
DTIMEOUTIE
Data timeout interrupt enable
3
1
IDMABTCIE
IDMABTCIE
28
1
RXFIFOFIE
Rx FIFO full interrupt enable
17
1
RXFIFOHFIE
Rx FIFO half full interrupt enable
15
1
RXOVERRIE
Rx FIFO overrun error interrupt enable
5
1
SDIOITIE
SDIO mode interrupt received interrupt enable
22
1
TXFIFOEIE
Tx FIFO empty interrupt enable
18
1
TXFIFOHEIE
Tx FIFO half empty interrupt enable
14
1
TXUNDERRIE
Tx FIFO underrun error interrupt enable
4
1
VSWENDIE
Voltage switch critical timing section completion interrupt enable
25
1
POWER
POWER
power control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DIRPOL
Data and command direction signals polarity selection
4
1
PWRCTRL
SDMMC state control bits
0
2
VSWITCH
Voltage switch sequence start
2
1
VSWITCHEN
Voltage switch procedure enable
3
1
RESP1R
RESP1R
response 1..4 register
0x14
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS1
see Table 347
0
32
RESP2R
RESP2R
response 1..4 register
0x18
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS2
see Table 347
0
32
RESP3R
RESP3R
response 1..4 register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS3
see Table 347
0
32
RESP4R
RESP4R
response 1..4 register
0x20
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS4
see Table 347
0
32
RESPCMDR
RESPCMDR
command response register
0x10
32
read-only
n
0x0
0xFFFFFFFF
RESPCMD
Response command index
0
6
STAR
STAR
status register
0x34
32
read-only
n
0x0
0xFFFFFFFF
ACKFAIL
Boot acknowledgment received (boot acknowledgment check fail)
23
1
ACKTIMEOUT
Boot acknowledgment timeout
24
1
BUSYD0
Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response
20
1
BUSYD0END
end of SDMMC_D0 Busy following a CMD response detected
21
1
CCRCFAIL
Command response received (CRC check failed)
0
1
CKSTOP
SDMMC_CK stopped in Voltage switch procedure
26
1
CMDREND
Command response received (CRC check passed)
6
1
CMDSENT
Command sent (no response required)
7
1
CPSMACT
Command path state machine active, i.e. not in Idle state
13
1
CTIMEOUT
Command response timeout
2
1
DABORT
Data transfer aborted by CMD12
11
1
DATAEND
Data end (data counter, SDIDCOUNT, is zero)
8
1
DBCKEND
Data block sent/received
10
1
DCRCFAIL
Data block sent/received (CRC check failed)
1
1
DHOLD
Data transfer Hold
9
1
DPSMACT
Data path state machine active, i.e. not in Idle state
12
1
DTIMEOUT
Data timeout
3
1
IDMABTC
IDMA buffer transfer complete
28
1
IDMATE
IDMA transfer error
27
1
RXFIFOE
Receive FIFO empty
19
1
RXFIFOF
Receive FIFO full
17
1
RXFIFOHF
Receive FIFO half full: there are at least 8 words in the FIFO
15
1
RXOVERR
Received FIFO overrun error
5
1
SDIOIT
SDIO interrupt received
22
1
TXFIFOE
Transmit FIFO empty
18
1
TXFIFOF
Transmit FIFO full
16
1
TXFIFOHE
Transmit FIFO half empty: at least 8 words can be written into the FIFO
14
1
TXUNDERR
Transmit FIFO underrun error
4
1
VSWEND
Voltage switch critical timing section completion
25
1
SDMMC2
Secure digital input/output interface 2
SDIO
0x50062800
0x0
0x400
registers
n
SDMMC2
SDMMC2 global Interrupt
47
ACKTIMER
ACKTIMER
acknowledgment timer register
0x40
32
read-write
n
0x0
0xFFFFFFFF
ACKTIME
Boot acknowledgment timeout period
0
25
ARGR
ARGR
argument register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CMDARG
Command argument
0
32
CLKCR
CLKCR
SDI clock control register
0x4
32
read-write
n
0x0
0xFFFFFFFF
BUSSPEED
Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50
19
1
CLKDIV
Clock divide factor
0
10
DDR
Data rate signaling selection
18
1
HWFC_EN
Hardware flow control enable
17
1
NEGEDGE
SDMMC_CK dephasing selection bit for data and command
16
1
PWRSAV
Power saving configuration bit
12
1
SELCLKRX
Receive clock selection
20
2
WIDBUS
Wide bus mode enable bit
14
2
CMDR
CMDR
command register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BOOTEN
Enable boot mode procedure
15
1
BOOTMODE
Select the boot mode procedure to be used
14
1
CMDINDEX
Command index
0
6
CMDSTOP
The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM
7
1
CMDSUSPEND
The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end
16
1
CMDTRANS
The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM
6
1
CPSMEN
Command path state machine (CPSM) Enable bit
12
1
DTHOLD
Hold new data block transmission and reception in the DPSM
13
1
WAITINT
CPSM waits for interrupt request
10
1
WAITPEND
CPSM Waits for ends of data transfer (CmdPend internal signal)
11
1
WAITRESP
Wait for response bits
8
2
DCNTR
DCNTR
data counter register
0x30
32
read-only
n
0x0
0xFFFFFFFF
DATACOUNT
Data count value
0
25
DCTRL
DCTRL
data control register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
BOOTACKEN
Enable the reception of the boot acknowledgment
12
1
DBLOCKSIZE
Data block size
4
4
DTDIR
Data transfer direction selection
1
1
DTEN
DTEN
0
1
DTMODE
Data transfer mode selection 1: Stream or SDIO multibyte data transfer
2
2
FIFORST
FIFO reset, will flush any remaining data
13
1
RWMOD
Read wait mode
10
1
RWSTART
Read wait start
8
1
RWSTOP
Read wait stop
9
1
SDIOEN
SD I/O enable functions
11
1
DLENR
DLENR
data length register
0x28
32
read-write
n
0x0
0xFFFFFFFF
DATALENGTH
Data length value
0
25
DTIMER
DTIMER
data timer register
0x24
32
read-write
n
0x0
0xFFFFFFFF
DATATIME
Data timeout period
0
32
FIFOR0
FIFOR0
data FIFO register 0
0x80
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR1
FIFOR1
data FIFO register 1
0x84
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR10
FIFOR10
data FIFO register 10
0xA8
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR11
FIFOR11
data FIFO register 11
0xAC
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR12
FIFOR12
data FIFO register 12
0xB0
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR13
FIFOR13
data FIFO register 13
0xB4
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR14
FIFOR14
data FIFO register 14
0xB8
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR15
FIFOR15
data FIFO register 15
0xBC
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR2
FIFOR2
data FIFO register 2
0x88
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR3
FIFOR3
data FIFO register 3
0x8C
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR4
FIFOR4
data FIFO register 4
0x90
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR5
FIFOR5
data FIFO register 5
0x94
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR6
FIFOR6
data FIFO register 6
0x98
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR7
FIFOR7
data FIFO register 7
0x9C
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR8
FIFOR8
data FIFO register 8
0xA0
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
FIFOR9
FIFOR9
data FIFO register 9
0xA4
32
read-write
n
0x0
0xFFFFFFFF
FIFODATA
Receive and transmit FIFO data
0
32
ICR
ICR
interrupt clear register
0x38
32
read-write
n
0x0
0xFFFFFFFF
ACKFAILC
ACKFAIL flag clear bit
23
1
ACKTIMEOUTC
ACKTIMEOUT flag clear bit
24
1
BUSYD0ENDC
BUSYD0END flag clear bit
21
1
CCRCFAILC
CCRCFAIL flag clear bit
0
1
CKSTOPC
CKSTOP flag clear bit
26
1
CMDRENDC
CMDREND flag clear bit
6
1
CMDSENTC
CMDSENT flag clear bit
7
1
CTIMEOUTC
CTIMEOUT flag clear bit
2
1
DABORTC
DABORT flag clear bit
11
1
DATAENDC
DATAEND flag clear bit
8
1
DBCKENDC
DBCKEND flag clear bit
10
1
DCRCFAILC
DCRCFAIL flag clear bit
1
1
DHOLDC
DHOLD flag clear bit
9
1
DTIMEOUTC
DTIMEOUT flag clear bit
3
1
IDMABTCC
IDMA buffer transfer complete clear bit
28
1
IDMATEC
IDMA transfer error clear bit
27
1
RXOVERRC
RXOVERR flag clear bit
5
1
SDIOITC
SDIOIT flag clear bit
22
1
TXUNDERRC
TXUNDERR flag clear bit
4
1
VSWENDC
VSWEND flag clear bit
25
1
IDMABASE0R
IDMABASE0R
IDMA buffer 0 base address register
0x58
32
read-write
n
0x0
0xFFFFFFFF
IDMABASE0
Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only)
0
32
IDMABASE1R
IDMABASE1R
IDMA buffer 0 base address register
0x5C
32
read-write
n
0x0
0xFFFFFFFF
IDMABASE1
Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only)
0
32
IDMABSIZER
IDMABSIZER
IDMA buffer size register
0x54
32
read-write
n
0x0
0xFFFFFFFF
IDMABNDT
Number of bytes per buffer
5
8
IDMACTRLR
IDMACTRLR
DMA control register
0x50
32
read-write
n
0x0
0xFFFFFFFF
IDMABACT
Double buffer mode active buffer indication
2
1
IDMABMODE
Buffer mode selection
1
1
IDMAEN
IDMA enable
0
1
MASKR
MASKR
mask register
0x3C
32
read-write
n
0x0
0xFFFFFFFF
ACKFAILIE
Acknowledgment Fail interrupt enable
23
1
ACKTIMEOUTIE
Acknowledgment timeout interrupt enable
24
1
BUSYD0ENDIE
BUSYD0END interrupt enable
21
1
CCRCFAILIE
Command CRC fail interrupt enable
0
1
CKSTOPIE
CKSTOPIE
26
1
CMDRENDIE
Command response received interrupt enable
6
1
CMDSENTIE
Command sent interrupt enable
7
1
CTIMEOUTIE
Command timeout interrupt enable
2
1
DABORTIE
Data transfer aborted interrupt enable
11
1
DATAENDIE
Data end interrupt enable
8
1
DBCKENDIE
Data block end interrupt enable
10
1
DCRCFAILIE
Data CRC fail interrupt enable
1
1
DHOLDIE
Data hold interrupt enable
9
1
DTIMEOUTIE
Data timeout interrupt enable
3
1
IDMABTCIE
IDMABTCIE
28
1
RXFIFOFIE
Rx FIFO full interrupt enable
17
1
RXFIFOHFIE
Rx FIFO half full interrupt enable
15
1
RXOVERRIE
Rx FIFO overrun error interrupt enable
5
1
SDIOITIE
SDIO mode interrupt received interrupt enable
22
1
TXFIFOEIE
Tx FIFO empty interrupt enable
18
1
TXFIFOHEIE
Tx FIFO half empty interrupt enable
14
1
TXUNDERRIE
Tx FIFO underrun error interrupt enable
4
1
VSWENDIE
Voltage switch critical timing section completion interrupt enable
25
1
POWER
POWER
power control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DIRPOL
Data and command direction signals polarity selection
4
1
PWRCTRL
SDMMC state control bits
0
2
VSWITCH
Voltage switch sequence start
2
1
VSWITCHEN
Voltage switch procedure enable
3
1
RESP1R
RESP1R
response 1..4 register
0x14
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS1
see Table 347
0
32
RESP2R
RESP2R
response 1..4 register
0x18
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS2
see Table 347
0
32
RESP3R
RESP3R
response 1..4 register
0x1C
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS3
see Table 347
0
32
RESP4R
RESP4R
response 1..4 register
0x20
32
read-only
n
0x0
0xFFFFFFFF
CARDSTATUS4
see Table 347
0
32
RESPCMDR
RESPCMDR
command response register
0x10
32
read-only
n
0x0
0xFFFFFFFF
RESPCMD
Response command index
0
6
STAR
STAR
status register
0x34
32
read-only
n
0x0
0xFFFFFFFF
ACKFAIL
Boot acknowledgment received (boot acknowledgment check fail)
23
1
ACKTIMEOUT
Boot acknowledgment timeout
24
1
BUSYD0
Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response
20
1
BUSYD0END
end of SDMMC_D0 Busy following a CMD response detected
21
1
CCRCFAIL
Command response received (CRC check failed)
0
1
CKSTOP
SDMMC_CK stopped in Voltage switch procedure
26
1
CMDREND
Command response received (CRC check passed)
6
1
CMDSENT
Command sent (no response required)
7
1
CPSMACT
Command path state machine active, i.e. not in Idle state
13
1
CTIMEOUT
Command response timeout
2
1
DABORT
Data transfer aborted by CMD12
11
1
DATAEND
Data end (data counter, SDIDCOUNT, is zero)
8
1
DBCKEND
Data block sent/received
10
1
DCRCFAIL
Data block sent/received (CRC check failed)
1
1
DHOLD
Data transfer Hold
9
1
DPSMACT
Data path state machine active, i.e. not in Idle state
12
1
DTIMEOUT
Data timeout
3
1
IDMABTC
IDMA buffer transfer complete
28
1
IDMATE
IDMA transfer error
27
1
RXFIFOE
Receive FIFO empty
19
1
RXFIFOF
Receive FIFO full
17
1
RXFIFOHF
Receive FIFO half full: there are at least 8 words in the FIFO
15
1
RXOVERR
Received FIFO overrun error
5
1
SDIOIT
SDIO interrupt received
22
1
TXFIFOE
Transmit FIFO empty
18
1
TXFIFOF
Transmit FIFO full
16
1
TXFIFOHE
Transmit FIFO half empty: at least 8 words can be written into the FIFO
14
1
TXUNDERR
Transmit FIFO underrun error
4
1
VSWEND
Voltage switch critical timing section completion
25
1
SPI1
Serial peripheral interface/Inter-IC sound
SPI
0x40013000
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x7
0xFFFFFFFF
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0xFFFFFFFF
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x2
0xFFFFFFFF
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0xFFFFFFFF
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface/Inter-IC sound
SPI
0x40003800
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
36
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x7
0xFFFFFFFF
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0xFFFFFFFF
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x2
0xFFFFFFFF
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0xFFFFFFFF
TxCRC
Tx CRC register
0
16
SPI3
Serial peripheral interface/Inter-IC sound
SPI
0x40003C00
0x0
0x400
registers
n
SPI3
SPI3 global Interrupt
51
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x7
0xFFFFFFFF
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0xFFFFFFFF
DR
Data register
0
16
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0xFFFFFFFF
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x2
0xFFFFFFFF
BSY
Busy flag
7
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0xFFFFFFFF
TxCRC
Tx CRC register
0
16
STK
SysTick timer
STK
0xE000E010
0x0
0x11
registers
n
CALIB
CALIB
SysTick calibration value register
0xC
32
read-write
n
0x0
0xFFFFFFFF
NOREF
NOREF flag. Reads as zero
31
1
SKEW
SKEW flag: Indicates whether the TENMS value is exact
30
1
TENMS
Calibration value
0
24
CTRL
CTRL
SysTick control and status register
0x0
32
read-write
n
0x0
0xFFFFFFFF
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request enable
1
1
LOAD
LOAD
SysTick reload value register
0x4
32
read-write
n
0x0
0xFFFFFFFF
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
32
read-write
n
0x0
0xFFFFFFFF
CURRENT
Current counter value
0
24
SWPMI1
Single Wire Protocol Master Interface
SWPMI
0x40008800
0x0
0x400
registers
n
BRR
BRR
SWPMI Bitrate register
0x4
32
read-write
n
0x1
0xFFFFFFFF
BR
Bitrate prescaler
0
6
CR
CR
SWPMI Configuration/Control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
DEACT
Single wire protocol master interface deactivate
10
1
LPBK
Loopback mode enable
4
1
RXDMA
Reception DMA enable
0
1
RXMODE
Reception buffering mode
2
1
SWPME
Single wire protocol master interface enable
5
1
TXDMA
Transmission DMA enable
1
1
TXMODE
Transmission buffering mode
3
1
ICR
ICR
SWPMI Interrupt Flag Clear register
0x10
32
write-only
n
0x0
0xFFFFFFFF
CRXBERF
Clear receive CRC error flag
2
1
CRXBFF
Clear receive buffer full flag
0
1
CRXOVRF
Clear receive overrun error flag
3
1
CSRF
Clear slave resume flag
8
1
CTCF
Clear transfer complete flag
7
1
CTXBEF
Clear transmit buffer empty flag
1
1
CTXUNRF
Clear transmit underrun error flag
4
1
IER
IER
SWPMI Interrupt Enable register
0x14
32
read-write
n
0x0
0xFFFFFFFF
RIE
Receive interrupt enable
5
1
RXBERIE
Receive CRC error interrupt enable
2
1
RXBFIE
Receive buffer full interrupt enable
0
1
RXOVRIE
Receive overrun error interrupt enable
3
1
SRIE
Slave resume interrupt enable
8
1
TCIE
Transmit complete interrupt enable
7
1
TIE
Transmit interrupt enable
6
1
TXBEIE
Transmit buffer empty interrupt enable
1
1
TXUNRIE
Transmit underrun error interrupt enable
4
1
ISR
ISR
SWPMI Interrupt and Status register
0xC
32
read-only
n
0x2C2
0xFFFFFFFF
DEACTF
DEACTIVATED flag
10
1
RXBERF
Receive CRC error flag
2
1
RXBFF
Receive buffer full flag
0
1
RXNE
Receive data register not empty
5
1
RXOVRF
Receive overrun error flag
3
1
SRF
Slave resume flag
8
1
SUSP
SUSPEND flag
9
1
TCF
Transfer complete flag
7
1
TXBEF
Transmit buffer empty flag
1
1
TXE
Transmit data register empty
6
1
TXUNRF
Transmit underrun error flag
4
1
RDR
RDR
SWPMI Receive data register
0x20
32
read-only
n
0x0
0xFFFFFFFF
RD
received data
0
32
RFL
RFL
SWPMI Receive Frame Length register
0x18
32
read-only
n
0x0
0xFFFFFFFF
RFL
Receive frame length
0
5
TDR
TDR
SWPMI Transmit data register
0x1C
32
write-only
n
0x0
0xFFFFFFFF
TD
Transmit data
0
32
SYSCFG
System configuration controller
SYSCFG
0x40010000
0x0
0x30
registers
n
CFGR1
CFGR1
configuration register 1
0x4
32
read-write
n
0x7C000001
0xFFFFFFFF
BOOSTEN
I/O analog switch voltage booster enable
8
1
FPU_IE
Floating Point Unit interrupts enable bits
26
6
FWDIS
Firewall disable
0
1
I2C1_FMP
I2C1 Fast-mode Plus driving capability activation
20
1
I2C2_FMP
I2C2 Fast-mode Plus driving capability activation
21
1
I2C3_FMP
I2C3 Fast-mode Plus driving capability activation
22
1
I2C_PB6_FMP
Fast-mode Plus (Fm+) driving capability activation on PB6
16
1
I2C_PB7_FMP
Fast-mode Plus (Fm+) driving capability activation on PB7
17
1
I2C_PB8_FMP
Fast-mode Plus (Fm+) driving capability activation on PB8
18
1
I2C_PB9_FMP
Fast-mode Plus (Fm+) driving capability activation on PB9
19
1
CFGR2
CFGR2
CFGR2
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CLL
Cortex-M4 LOCKUP (Hardfault) output enable bit
0
1
write-only
ECCL
ECC Lock
3
1
write-only
PVDL
PVD lock enable bit
2
1
write-only
SPF
SRAM2 parity error flag
8
1
read-write
SPL
SRAM2 parity lock bit
1
1
write-only
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0xFFFFFFFF
EXTI0
EXTI 0 configuration bits
0
3
EXTI1
EXTI 1 configuration bits
4
3
EXTI2
EXTI 2 configuration bits
8
3
EXTI3
EXTI 3 configuration bits
12
3
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0xFFFFFFFF
EXTI4
EXTI 4 configuration bits
0
3
EXTI5
EXTI 5 configuration bits
4
3
EXTI6
EXTI 6 configuration bits
8
3
EXTI7
EXTI 7 configuration bits
12
3
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0xFFFFFFFF
EXTI10
EXTI 10 configuration bits
8
3
EXTI11
EXTI 11 configuration bits
12
3
EXTI8
EXTI 8 configuration bits
0
3
EXTI9
EXTI 9 configuration bits
4
3
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0xFFFFFFFF
EXTI12
EXTI12 configuration bits
0
3
EXTI13
EXTI13 configuration bits
4
3
EXTI14
EXTI14 configuration bits
8
3
EXTI15
EXTI15 configuration bits
12
3
MEMRMP
MEMRMP
memory remap register
0x0
32
read-write
n
0x0
0xFFFFFFFF
FB_MODE
Flash Bank mode selection
8
1
MEM_MODE
Memory mapping selection
0
3
QFS
QUADSPI memory mapping swap
3
1
SCSR
SCSR
SCSR
0x18
32
read-write
n
0x0
0xFFFFFFFF
SRAM2BSY
SRAM2 busy by erase operation
1
1
read-only
SRAM2ER
SRAM2 Erase
0
1
read-write
SKR
SKR
SKR
0x24
32
write-only
n
0x0
0xFFFFFFFF
KEY
SRAM2 write protection key for software erase
0
8
SWPR
SWPR
SWPR
0x20
32
write-only
n
0x0
0xFFFFFFFF
P0WP
P0WP
0
1
P10WP
P10WP
10
1
P11WP
P11WP
11
1
P12WP
P12WP
12
1
P13WP
P13WP
13
1
P14WP
P14WP
14
1
P15WP
P15WP
15
1
P16WP
P16WP
16
1
P17WP
P17WP
17
1
P18WP
P18WP
18
1
P19WP
P19WP
19
1
P1WP
P1WP
1
1
P20WP
P20WP
20
1
P21WP
P21WP
21
1
P22WP
P22WP
22
1
P23WP
P23WP
23
1
P24WP
P24WP
24
1
P25WP
P25WP
25
1
P26WP
P26WP
26
1
P27WP
P27WP
27
1
P28WP
P28WP
28
1
P29WP
P29WP
29
1
P2WP
P2WP
2
1
P30WP
P30WP
30
1
P31WP
SRAM2 page 31 write protection
31
1
P3WP
P3WP
3
1
P4WP
P4WP
4
1
P5WP
P5WP
5
1
P6WP
P6WP
6
1
P7WP
P7WP
7
1
P8WP
P8WP
8
1
P9WP
P9WP
9
1
TIM1
Advanced-timers
TIM
0x40012C00
0x0
0x400
registers
n
TIM1_BRK_TIM15
TIM1 Break/TIM15 global interrupts
24
TIM1_UP_TIM16
TIM1 Update/TIM16 global interrupts
25
TIM1_TRG_COM_TIM17
TIM1 Trigger and Commutation interrupts and TIM17 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCMR3_Output
CCMR3_Output
capture/compare mode register 2 (output mode)
0x54
32
read-write
n
0x0
0xFFFFFFFF
OC5CE
Output compare 5 clear enable
7
1
OC5FE
Output compare 5 fast enable
2
1
OC5M
Output compare 5 mode
4
3
OC5M_bit3
Output Compare 5 mode bit 3
16
3
OC5PE
Output compare 5 preload enable
3
1
OC6CE
Output compare 6 clear enable
15
1
OC6FE
Output compare 6 fast enable
10
1
OC6M
Output compare 6 mode
12
3
OC6M_bit3
Output Compare 6 mode bit 3
24
1
OC6PE
Output compare 6 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4
Capture/Compare value
0
16
CCR5
CCR5
capture/compare register 4
0x58
32
read-write
n
0x0
0xFFFFFFFF
CCR5
Capture/Compare value
0
16
GC5C1
Group Channel 5 and Channel 1
29
1
GC5C2
Group Channel 5 and Channel 2
30
1
GC5C3
Group Channel 5 and Channel 3
31
1
CCR6
CCR6
capture/compare register 4
0x5C
32
read-write
n
0x0
0xFFFFFFFF
CCR6
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
OR1
DMA address for full transfer
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_ADC1_RMP
External trigger remap on ADC1 analog watchdog
0
2
ETR_ADC3_RMP
External trigger remap on ADC3 analog watchdog
2
2
TI1_RMP
Input Capture 1 remap
4
1
OR2
OR2
DMA address for full transfer
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarity
11
1
BKDFBK0E
BRK DFSDM_BREAK0 enable
8
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
ETRSEL
ETR source selection
14
3
OR3
OR3
DMA address for full transfer
0x64
32
read-write
n
0x1
0xFFFFFFFF
BK2CMP1E
BRK2 COMP1 enable
1
1
BK2CMP1P
BRK2 COMP1 input polarity
10
1
BK2CMP2E
BRK2 COMP2 enable
2
1
BK2CMP2P
BRK2 COMP2 input polarity
11
1
BK2DFBK0E
BRK2 DFSDM_BREAK0 enable
8
1
BK2INE
BRK2 BKIN input enable
0
1
BK2INP
BRK2 BKIN input polarity
9
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM15
General purpose timers
TIM
0x40014000
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_2
Output Compare 1 mode
16
1
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM16
General purpose timers
TIM
0x40014400
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_2
Output Compare 1 mode
16
1
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
OR1
TIM16 option register 1
0x50
32
read-write
n
0x0
0xFFFFFFFF
TI1_RMP
Input capture 1 remap
0
2
OR2
OR2
TIM17 option register 1
0x60
32
read-write
n
0x0
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarit
11
1
BKDFBK1E
BRK DFSDM_BREAK1 enable
8
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM17
General purpose timers
TIM
0x40014800
0x0
0x400
registers
n
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1M_2
Output Compare 1 mode
16
1
OC1PE
Output Compare 1 preload enable
3
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
read-write
UIFCPY
UIF Copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
OR1
TIM16 option register 1
0x50
32
read-write
n
0x0
0xFFFFFFFF
TI1_RMP
Input capture 1 remap
0
2
OR2
OR2
TIM17 option register 1
0x60
32
read-write
n
0x0
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarit
11
1
BKDFBK1E
BRK DFSDM_BREAK1 enable
8
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM2
General-purpose-timers
TIM
0x40000000
0x0
0x400
registers
n
TIM2
TIM2 global interrupt
28
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM3
General-purpose-timers
TIM
0x40000400
0x0
0x400
registers
n
TIM3
TIM3 global interrupt
29
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM4
General-purpose-timers
TIM
0x40000800
0x0
0x400
registers
n
TIM4
TIM4 global interrupt
30
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM5
General-purpose-timers
TIM
0x40000C00
0x0
0x400
registers
n
TIM5
TIM5 global Interrupt
50
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR
OR
TIM2 option register
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_RMP
Timer2 ETR remap
0
3
TI4_RMP
Internal trigger
3
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TIM6
Basic-timers
TIM
0x40001000
0x0
0x400
registers
n
TIM6_DACUNDER
TIM6 global and DAC1 and 2 underrun error interrupts
54
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
UIF
Update interrupt flag
0
1
TIM7
Basic-timers
TIM
0x40001400
0x0
0x400
registers
n
TIM7
TIM7 global interrupt
55
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
MMS
Master mode selection
4
3
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
UG
Update generation
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
UIF
Update interrupt flag
0
1
TIM8
Advanced-timers
TIM
0x40013400
0x0
0x400
registers
n
TIM8_BRK
TIM8 Break Interrupt
43
TIM8_UP
TIM8 Update Interrupt
44
TIM8_TRG_COM
TIM8 Trigger and Commutation Interrupt
45
TIM8_CC
TIM8 Capture Compare Interrupt
46
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0xFFFFFFFF
AOE
Automatic output enable
14
1
BKE
Break enable
12
1
BKP
Break polarity
13
1
DTG
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0xFFFFFFFF
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NE
Capture/Compare 2 complementary output enable
6
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NE
Capture/Compare 3 complementary output enable
10
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC2F
Input capture 2 filter
12
4
IC2PCS
Input capture 2 prescaler
10
2
ICPCS
Input capture 1 prescaler
2
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0xFFFFFFFF
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output Compare 1 clear enable
7
1
OC1FE
Output Compare 1 fast enable
2
1
OC1M
Output Compare 1 mode
4
3
OC1PE
Output Compare 1 preload enable
3
1
OC2CE
Output Compare 2 clear enable
15
1
OC2FE
Output Compare 2 fast enable
10
1
OC2M
Output Compare 2 mode
12
3
OC2PE
Output Compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0xFFFFFFFF
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4PE
Output compare 4 preload enable
11
1
CCMR3_Output
CCMR3_Output
capture/compare mode register 2 (output mode)
0x54
32
read-write
n
0x0
0xFFFFFFFF
OC5CE
Output compare 5 clear enable
7
1
OC5FE
Output compare 5 fast enable
2
1
OC5M
Output compare 5 mode
4
3
OC5M_bit3
Output Compare 5 mode bit 3
16
3
OC5PE
Output compare 5 preload enable
3
1
OC6CE
Output compare 6 clear enable
15
1
OC6FE
Output compare 6 fast enable
10
1
OC6M
Output compare 6 mode
12
3
OC6M_bit3
Output Compare 6 mode bit 3
24
1
OC6PE
Output compare 6 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0xFFFFFFFF
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0xFFFFFFFF
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0xFFFFFFFF
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0xFFFFFFFF
CCR4
Capture/Compare value
0
16
CCR5
CCR5
capture/compare register 4
0x58
32
read-write
n
0x0
0xFFFFFFFF
CCR5
Capture/Compare value
0
16
GC5C1
Group Channel 5 and Channel 1
29
1
GC5C2
Group Channel 5 and Channel 2
30
1
GC5C3
Group Channel 5 and Channel 3
31
1
CCR6
CCR6
capture/compare register 4
0x5C
32
read-write
n
0x0
0xFFFFFFFF
CCR6
Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0xFFFFFFFF
CNT
counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
OIS1
Output Idle state 1
8
1
OIS1N
Output Idle state 1
9
1
OIS2
Output Idle state 2
10
1
OIS2N
Output Idle state 2
11
1
OIS3
Output Idle state 3
12
1
OIS3N
Output Idle state 3
13
1
OIS4
Output Idle state 4
14
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0xFFFFFFFF
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0xFFFFFFFF
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0xFFFFFFFF
BG
Break generation
7
1
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
COMG
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
OR1
DMA address for full transfer
0x50
32
read-write
n
0x0
0xFFFFFFFF
ETR_ADC2_RMP
External trigger remap on ADC2 analog watchdog
0
2
ETR_ADC3_RMP
External trigger remap on ADC3 analog watchdog
2
2
TI1_RMP
Input Capture 1 remap
4
1
OR2
OR2
DMA address for full transfer
0x60
32
read-write
n
0x1
0xFFFFFFFF
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarity
11
1
BKDFBK2E
BRK DFSDM_BREAK2 enable
8
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
ETRSEL
ETR source selection
14
3
OR3
OR3
DMA address for full transfer
0x64
32
read-write
n
0x1
0xFFFFFFFF
BK2CMP1E
BRK2 COMP1 enable
1
1
BK2CMP1P
BRK2 COMP1 input polarity
10
1
BK2CMP2E
BRK2 COMP2 enable
2
1
BK2CMP2P
BRK2 COMP2 input polarity
11
1
BK2DFBK3E
BRK2 DFSDM_BREAK3 enable
8
1
BK2INE
BRK2 BKIN input enable
0
1
BK2INP
BRK2 BKIN input polarity
9
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0xFFFFFFFF
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0xFFFFFFFF
REP
Repetition counter value
0
8
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0xFFFFFFFF
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMS
Slave mode selection
0
3
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0xFFFFFFFF
BIF
Break interrupt flag
7
1
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
COMIF
COM interrupt flag
5
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TSC
Touch sensing controller
TSC
0x40024000
0x0
0x400
registers
n
TSC
TSC global interrupt
77
CR
CR
control register
0x0
32
read-write
n
0x0
0xFFFFFFFF
AM
Acquisition mode
2
1
CTPH
Charge transfer pulse high
28
4
CTPL
Charge transfer pulse low
24
4
IODEF
I/O Default mode
4
1
MCV
Max count value
5
3
PGPSC
pulse generator prescaler
12
3
SSD
Spread spectrum deviation
17
7
SSE
Spread spectrum enable
16
1
SSPSC
Spread spectrum prescaler
15
1
START
Start a new acquisition
1
1
SYNCPOL
Synchronization pin polarity
3
1
TSCE
Touch sensing controller enable
0
1
ICR
ICR
interrupt clear register
0x8
32
read-write
n
0x0
0xFFFFFFFF
EOAIC
End of acquisition interrupt clear
0
1
MCEIC
Max count error interrupt clear
1
1
IER
IER
interrupt enable register
0x4
32
read-write
n
0x0
0xFFFFFFFF
EOAIE
End of acquisition interrupt enable
0
1
MCEIE
Max count error interrupt enable
1
1
IOASCR
IOASCR
I/O analog switch control register
0x18
32
read-write
n
0x0
0xFFFFFFFF
G1_IO1
G1_IO1
0
1
G1_IO2
G1_IO2
1
1
G1_IO3
G1_IO3
2
1
G1_IO4
G1_IO4
3
1
G2_IO1
G2_IO1
4
1
G2_IO2
G2_IO2
5
1
G2_IO3
G2_IO3
6
1
G2_IO4
G2_IO4
7
1
G3_IO1
G3_IO1
8
1
G3_IO2
G3_IO2
9
1
G3_IO3
G3_IO3
10
1
G3_IO4
G3_IO4
11
1
G4_IO1
G4_IO1
12
1
G4_IO2
G4_IO2
13
1
G4_IO3
G4_IO3
14
1
G4_IO4
G4_IO4
15
1
G5_IO1
G5_IO1
16
1
G5_IO2
G5_IO2
17
1
G5_IO3
G5_IO3
18
1
G5_IO4
G5_IO4
19
1
G6_IO1
G6_IO1
20
1
G6_IO2
G6_IO2
21
1
G6_IO3
G6_IO3
22
1
G6_IO4
G6_IO4
23
1
G7_IO1
G7_IO1
24
1
G7_IO2
G7_IO2
25
1
G7_IO3
G7_IO3
26
1
G7_IO4
G7_IO4
27
1
G8_IO1
G8_IO1
28
1
G8_IO2
G8_IO2
29
1
G8_IO3
G8_IO3
30
1
G8_IO4
G8_IO4
31
1
IOCCR
IOCCR
I/O channel control register
0x28
32
read-write
n
0x0
0xFFFFFFFF
G1_IO1
G1_IO1
0
1
G1_IO2
G1_IO2
1
1
G1_IO3
G1_IO3
2
1
G1_IO4
G1_IO4
3
1
G2_IO1
G2_IO1
4
1
G2_IO2
G2_IO2
5
1
G2_IO3
G2_IO3
6
1
G2_IO4
G2_IO4
7
1
G3_IO1
G3_IO1
8
1
G3_IO2
G3_IO2
9
1
G3_IO3
G3_IO3
10
1
G3_IO4
G3_IO4
11
1
G4_IO1
G4_IO1
12
1
G4_IO2
G4_IO2
13
1
G4_IO3
G4_IO3
14
1
G4_IO4
G4_IO4
15
1
G5_IO1
G5_IO1
16
1
G5_IO2
G5_IO2
17
1
G5_IO3
G5_IO3
18
1
G5_IO4
G5_IO4
19
1
G6_IO1
G6_IO1
20
1
G6_IO2
G6_IO2
21
1
G6_IO3
G6_IO3
22
1
G6_IO4
G6_IO4
23
1
G7_IO1
G7_IO1
24
1
G7_IO2
G7_IO2
25
1
G7_IO3
G7_IO3
26
1
G7_IO4
G7_IO4
27
1
G8_IO1
G8_IO1
28
1
G8_IO2
G8_IO2
29
1
G8_IO3
G8_IO3
30
1
G8_IO4
G8_IO4
31
1
IOG1CR
IOG1CR
I/O group x counter register
0x34
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG2CR
IOG2CR
I/O group x counter register
0x38
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG3CR
IOG3CR
I/O group x counter register
0x3C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG4CR
IOG4CR
I/O group x counter register
0x40
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG5CR
IOG5CR
I/O group x counter register
0x44
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG6CR
IOG6CR
I/O group x counter register
0x48
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG7CR
IOG7CR
I/O group x counter register
0x4C
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOG8CR
IOG8CR
I/O group x counter register
0x50
32
read-only
n
0x0
0xFFFFFFFF
CNT
Counter value
0
14
IOGCSR
IOGCSR
I/O group control status register
0x30
32
read-write
n
0x0
0xFFFFFFFF
G1E
Analog I/O group x enable
0
1
read-write
G1S
Analog I/O group x status
16
1
read-only
G2E
Analog I/O group x enable
1
1
read-write
G2S
Analog I/O group x status
17
1
read-only
G3E
Analog I/O group x enable
2
1
read-write
G3S
Analog I/O group x status
18
1
read-only
G4E
Analog I/O group x enable
3
1
read-write
G4S
Analog I/O group x status
19
1
read-only
G5E
Analog I/O group x enable
4
1
read-write
G5S
Analog I/O group x status
20
1
read-only
G6E
Analog I/O group x enable
5
1
read-write
G6S
Analog I/O group x status
21
1
read-only
G7E
Analog I/O group x enable
6
1
read-write
G7S
Analog I/O group x status
22
1
read-only
G8E
Analog I/O group x enable
7
1
read-write
G8S
Analog I/O group x status
23
1
read-only
IOHCR
IOHCR
I/O hysteresis control register
0x10
32
read-write
n
0xFFFFFFFF
0xFFFFFFFF
G1_IO1
G1_IO1
0
1
G1_IO2
G1_IO2
1
1
G1_IO3
G1_IO3
2
1
G1_IO4
G1_IO4
3
1
G2_IO1
G2_IO1
4
1
G2_IO2
G2_IO2
5
1
G2_IO3
G2_IO3
6
1
G2_IO4
G2_IO4
7
1
G3_IO1
G3_IO1
8
1
G3_IO2
G3_IO2
9
1
G3_IO3
G3_IO3
10
1
G3_IO4
G3_IO4
11
1
G4_IO1
G4_IO1
12
1
G4_IO2
G4_IO2
13
1
G4_IO3
G4_IO3
14
1
G4_IO4
G4_IO4
15
1
G5_IO1
G5_IO1
16
1
G5_IO2
G5_IO2
17
1
G5_IO3
G5_IO3
18
1
G5_IO4
G5_IO4
19
1
G6_IO1
G6_IO1
20
1
G6_IO2
G6_IO2
21
1
G6_IO3
G6_IO3
22
1
G6_IO4
G6_IO4
23
1
G7_IO1
G7_IO1
24
1
G7_IO2
G7_IO2
25
1
G7_IO3
G7_IO3
26
1
G7_IO4
G7_IO4
27
1
G8_IO1
G8_IO1
28
1
G8_IO2
G8_IO2
29
1
G8_IO3
G8_IO3
30
1
G8_IO4
G8_IO4
31
1
IOSCR
IOSCR
I/O sampling control register
0x20
32
read-write
n
0x0
0xFFFFFFFF
G1_IO1
G1_IO1
0
1
G1_IO2
G1_IO2
1
1
G1_IO3
G1_IO3
2
1
G1_IO4
G1_IO4
3
1
G2_IO1
G2_IO1
4
1
G2_IO2
G2_IO2
5
1
G2_IO3
G2_IO3
6
1
G2_IO4
G2_IO4
7
1
G3_IO1
G3_IO1
8
1
G3_IO2
G3_IO2
9
1
G3_IO3
G3_IO3
10
1
G3_IO4
G3_IO4
11
1
G4_IO1
G4_IO1
12
1
G4_IO2
G4_IO2
13
1
G4_IO3
G4_IO3
14
1
G4_IO4
G4_IO4
15
1
G5_IO1
G5_IO1
16
1
G5_IO2
G5_IO2
17
1
G5_IO3
G5_IO3
18
1
G5_IO4
G5_IO4
19
1
G6_IO1
G6_IO1
20
1
G6_IO2
G6_IO2
21
1
G6_IO3
G6_IO3
22
1
G6_IO4
G6_IO4
23
1
G7_IO1
G7_IO1
24
1
G7_IO2
G7_IO2
25
1
G7_IO3
G7_IO3
26
1
G7_IO4
G7_IO4
27
1
G8_IO1
G8_IO1
28
1
G8_IO2
G8_IO2
29
1
G8_IO3
G8_IO3
30
1
G8_IO4
G8_IO4
31
1
ISR
ISR
interrupt status register
0xC
32
read-write
n
0x0
0xFFFFFFFF
EOAF
End of acquisition flag
0
1
MCEF
Max count error flag
1
1
UART4
Universal synchronous asynchronous receiver transmitter
USART
0x40004C00
0x0
0x400
registers
n
UART4
UART4 global Interrupt
52
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR0_3
BRR
0
4
BRR4_15
USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
UDRCF
UDRCF
13
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
WUF
WUF
20
1
PRESC
PRESC
USART prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
UART5
Universal synchronous asynchronous receiver transmitter
USART
0x40005000
0x0
0x400
registers
n
UART5
UART5 global Interrupt
53
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR0_3
BRR
0
4
BRR4_15
USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
UDRCF
UDRCF
13
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
WUF
WUF
20
1
PRESC
PRESC
USART prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x40013800
0x0
0x400
registers
n
USART1
USART1 global interrupt
37
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR0_3
BRR
0
4
BRR4_15
USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
UDRCF
UDRCF
13
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
WUF
WUF
20
1
PRESC
PRESC
USART prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x40004400
0x0
0x400
registers
n
USART2
USART2 global interrupt
38
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR0_3
BRR
0
4
BRR4_15
USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
UDRCF
UDRCF
13
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
WUF
WUF
20
1
PRESC
PRESC
USART prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
USART3
Universal synchronous asynchronous receiver transmitter
USART
0x40004800
0x0
0x400
registers
n
USART3
USART3 global interrupt
39
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0xFFFFFFFF
BRR0_3
BRR
0
4
BRR4_15
USARTDIV
4
12
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0xFFFFFFFF
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable de-assertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0xFFFFFFFF
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD0_3
Address of the USART node
24
4
ADD4_7
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TAINV
Binary data inversion
18
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0xFFFFFFFF
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
Ir mode enable
1
1
IRLP
Ir low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
GTPR
GTPR
Guard time and prescaler register
0x10
32
read-write
n
0x0
0xFFFFFFFF
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0xFFFFFFFF
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NCF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCCF
Transmission complete clear flag
6
1
UDRCF
UDRCF
13
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR
ISR
Interrupt status register
0x1C
32
read-only
n
0xC0
0xFFFFFFFF
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NF
NF
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
WUF
WUF
20
1
PRESC
PRESC
USART prescaler register
0x2C
32
read-write
n
0x0
0xFFFFFFFF
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0xFFFFFFFF
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0xFFFFFFFF
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
Receiver timeout register
0x14
32
read-write
n
0x0
0xFFFFFFFF
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0xFFFFFFFF
TDR
Transmit data value
0
9
VREFBUF
Voltage reference buffer
VREF
0x40010030
0x0
0x1D0
registers
n
CCR
CCR
calibration control register
0x4
32
read-write
n
0x0
0xFFFFFFFF
TRIM
Trimming code
0
6
CSR
CSR
VREF control and status register
0x0
32
read-write
n
0x2
0xFFFFFFFF
ENVR
Voltage reference buffer enable
0
1
read-write
HIZ
High impedance mode
1
1
read-write
VRR
Voltage reference buffer ready
3
1
read-only
VRS
Voltage reference scale
2
1
read-write
WWDG
System window watchdog
WWDG
0x40002C00
0x0
0x400
registers
n
WWDG
Window Watchdog interrupt
0
CFR
CFR
Configuration register
0x4
32
read-write
n
0x7F
0xFFFFFFFF
EWI
Early wakeup interrupt
9
1
W
7-bit window value
0
7
WDGTB
Timer base
7
2
CR
CR
Control register
0x0
32
read-write
n
0x7F
0xFFFFFFFF
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0xFFFFFFFF
EWIF
Early wakeup interrupt flag
0
1