STMicroelectronics STM32L4R7AIIx 2024.04.27 STM32L4R7AIIx false ADC Analog-to-Digital Converter ADC 0x0 0x0 0xB9 registers n ADC1 ADC1 and ADC2 global interrupt 18 ADC3 ADC3 global interrupt 47 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 18 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 18 CALFACT CALFACT Calibration Factors 0xB4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 CFGR CFGR configuration register 0xC 32 read-write n 0x0 0x0 ALIGN ALIGN 5 1 AUTDLY AUTDLY 14 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 AWDCH1CH AWDCH1CH 26 5 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS Injected Queue disable 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 3 2 CFGR2 CFGR2 configuration register 0x10 32 read-write n 0x0 0x0 JOVSE DMACFG 1 1 OVSR RES 2 3 OVSS ALIGN 5 4 ROVSE DMAEN 0 1 ROVSM EXTEN 10 1 TROVS Triggered Regular Oversampling 9 1 CR CR control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 32 read-write n 0x0 0x0 DIFSEL_16_18 Differential mode for channels 18 to 16 16 3 read-only DIFSEL_1_15 Differential mode for channels 15 to 1 1 15 read-write DR DR regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA Regular Data converted 0 16 IER IER interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ISR ISR interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 JDR1 JDR1 injected data register 1 0x80 32 read-only n 0x0 0x0 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 32 read-only n 0x0 0x0 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 32 read-only n 0x0 0x0 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 32 read-only n 0x0 0x0 JDATA4 JDATA4 0 16 JSQR JSQR injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 6 2 JEXTSEL JEXTSEL 2 4 JL JL 0 2 JSQ1 JSQ1 8 5 JSQ2 JSQ2 14 5 JSQ3 JSQ3 20 5 JSQ4 JSQ4 26 5 OFR1 OFR1 offset register 1 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFR2 OFR2 offset register 2 0x64 32 read-write n 0x0 0x0 OFFSET2 OFFSET2 0 12 OFFSET2_CH OFFSET2_CH 26 5 OFFSET2_EN OFFSET2_EN 31 1 OFR3 OFR3 offset register 3 0x68 32 read-write n 0x0 0x0 OFFSET3 OFFSET3 0 12 OFFSET3_CH OFFSET3_CH 26 5 OFFSET3_EN OFFSET3_EN 31 1 OFR4 OFR4 offset register 4 0x6C 32 read-write n 0x0 0x0 OFFSET4 OFFSET4 0 12 OFFSET4_CH OFFSET4_CH 26 5 OFFSET4_EN OFFSET4_EN 31 1 SMPR1 SMPR1 sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPR2 SMPR2 sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SQR1 SQR1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 L Regular channel sequence length 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 TR1 TR1 watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 32 read-write n 0x0 0x0 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 32 read-write n 0x0 0x0 HT3 HT3 16 8 LT3 LT3 0 8 ADC_Common Analog-to-Digital Converter ADC 0x0 0x0 0x11 registers n CCR CCR ADC common control register 0x8 32 read-write n 0x0 0x0 CH17SEL CH17 selection 23 1 CH18SEL CH18 selection 24 1 CKMODE ADC clock mode 16 2 DELAY Delay between 2 sampling phases 8 4 DMACFG DMA configuration (for multi-ADC mode) 13 1 DUAL Dual ADC mode selection 0 5 MDMA Direct memory access mode for multi ADC mode 14 2 PRESC ADC prescaler 18 4 VREFEN VREFINT enable 22 1 CDR CDR ADC common regular data register for dual and triple modes 0xC 32 read-only n 0x0 0x0 RDATA_MST Regular data of the master ADC 0 16 RDATA_SLV Regular data of the slave ADC 16 16 CSR CSR ADC Common status register 0x0 32 read-only n 0x0 0x0 ADDRDY_MST ADDRDY_MST 0 1 ADRDY_SLV ADRDY_SLV 16 1 AWD1_MST AWD1_MST 7 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_MST AWD2_MST 8 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_MST AWD3_MST 9 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 EOC_MST EOC_MST 2 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_SLV EOSMP_SLV 17 1 EOS_MST EOS_MST 3 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 JEOC_MST JEOC_MST 5 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_MST JEOS_MST 6 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 OVR_MST OVR_MST 4 1 OVR_SLV Overrun flag of the slave ADC 20 1 AES Advanced encryption standard hardware accelerator AES 0x0 0x0 0x400 registers n AES AES global interrupt 79 CR CR control register 0x0 32 read-write n 0x0 0x0 CCFC Computation Complete Flag Clear 7 1 CCFIE CCF flag interrupt enable 9 1 CHMOD AES chaining mode 5 2 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DMAINEN Enable DMA management of data input phase 11 1 DMAOUTEN Enable DMA management of data output phase 12 1 EN AES enable 0 1 ERRC Error clear 8 1 ERRIE Error interrupt enable 10 1 MODE AES operating mode 3 2 DINR DINR data input register 0x8 32 read-write n 0x0 0x0 AES_DINR Data Input Register 0 32 DOUTR DOUTR data output register 0xC 32 read-only n 0x0 0x0 AES_DOUTR Data output register 0 32 IVR0 IVR0 initialization vector register 0 0x20 32 read-write n 0x0 0x0 AES_IVR0 initialization vector register (LSB IVR [31:0]) 0 32 IVR1 IVR1 initialization vector register 1 0x24 32 read-write n 0x0 0x0 AES_IVR1 Initialization Vector Register (IVR [63:32]) 0 32 IVR2 IVR2 initialization vector register 2 0x28 32 read-write n 0x0 0x0 AES_IVR2 Initialization Vector Register (IVR [95:64]) 0 32 IVR3 IVR3 initialization vector register 3 0x2C 32 read-write n 0x0 0x0 AES_IVR3 Initialization Vector Register (MSB IVR [127:96]) 0 32 KEYR0 KEYR0 key register 0 0x10 32 read-write n 0x0 0x0 AES_KEYR0 Data Output Register (LSB key [31:0]) 0 32 KEYR1 KEYR1 key register 1 0x14 32 read-write n 0x0 0x0 AES_KEYR1 AES key register (key [63:32]) 0 32 KEYR2 KEYR2 key register 2 0x18 32 read-write n 0x0 0x0 AES_KEYR2 AES key register (key [95:64]) 0 32 KEYR3 KEYR3 key register 3 0x1C 32 read-write n 0x0 0x0 AES_KEYR3 AES key register (MSB key [127:96]) 0 32 SR SR status register 0x4 32 read-only n 0x0 0x0 CCF Computation complete flag 0 1 RDERR Read error flag 1 1 WRERR Write error flag 2 1 CAN1 Controller area network CAN 0x0 0x0 0x400 registers n CAN1_TX CAN1 TX interrupts 19 CAN1_RX0 CAN1 RX0 interrupts 20 CAN1_RX1 CAN1 RX1 interrupts 21 CAN1_SCE CAN1 SCE interrupt 22 BTR BTR bit timing register 0x1C 32 read-write n 0x0 0x0 BRP BRP 0 10 LBKM LBKM 30 1 SILM SILM 31 1 SJW SJW 24 2 TS1 TS1 16 4 TS2 TS2 20 3 ESR ESR interrupt enable register 0x18 32 read-write n 0x0 0x0 BOFF BOFF 2 1 read-only EPVF EPVF 1 1 read-only EWGF EWGF 0 1 read-only LEC LEC 4 3 read-write REC REC 24 8 read-only TEC TEC 16 8 read-only F0R1 F0R1 Filter bank 0 register 1 0x240 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F0R2 F0R2 Filter bank 0 register 2 0x244 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R1 F10R1 Filter bank 10 register 1 0x290 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R2 F10R2 Filter bank 10 register 2 0x294 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R1 F11R1 Filter bank 11 register 1 0x298 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R2 F11R2 Filter bank 11 register 2 0x29C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R1 F12R1 Filter bank 4 register 1 0x2A0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R2 F12R2 Filter bank 12 register 2 0x2A4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R1 F13R1 Filter bank 13 register 1 0x2A8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R2 F13R2 Filter bank 13 register 2 0x2AC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R1 F14R1 Filter bank 14 register 1 0x2B0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R2 F14R2 Filter bank 14 register 2 0x2B4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R1 F15R1 Filter bank 15 register 1 0x2B8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R2 F15R2 Filter bank 15 register 2 0x2BC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R1 F16R1 Filter bank 16 register 1 0x2C0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R2 F16R2 Filter bank 16 register 2 0x2C4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R1 F17R1 Filter bank 17 register 1 0x2C8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R2 F17R2 Filter bank 17 register 2 0x2CC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R1 F18R1 Filter bank 18 register 1 0x2D0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R2 F18R2 Filter bank 18 register 2 0x2D4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R1 F19R1 Filter bank 19 register 1 0x2D8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R2 F19R2 Filter bank 19 register 2 0x2DC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R1 F1R1 Filter bank 1 register 1 0x248 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R2 F1R2 Filter bank 1 register 2 0x24C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R1 F20R1 Filter bank 20 register 1 0x2E0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R2 F20R2 Filter bank 20 register 2 0x2E4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R1 F21R1 Filter bank 21 register 1 0x2E8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R2 F21R2 Filter bank 21 register 2 0x2EC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R1 F22R1 Filter bank 22 register 1 0x2F0 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R2 F22R2 Filter bank 22 register 2 0x2F4 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R1 F23R1 Filter bank 23 register 1 0x2F8 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R2 F23R2 Filter bank 23 register 2 0x2FC 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R1 F24R1 Filter bank 24 register 1 0x300 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R2 F24R2 Filter bank 24 register 2 0x304 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R1 F25R1 Filter bank 25 register 1 0x308 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R2 F25R2 Filter bank 25 register 2 0x30C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R1 F26R1 Filter bank 26 register 1 0x310 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R2 F26R2 Filter bank 26 register 2 0x314 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R1 F27R1 Filter bank 27 register 1 0x318 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R2 F27R2 Filter bank 27 register 2 0x31C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R1 F2R1 Filter bank 2 register 1 0x250 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R2 F2R2 Filter bank 2 register 2 0x254 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R1 F3R1 Filter bank 3 register 1 0x258 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R2 F3R2 Filter bank 3 register 2 0x25C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R1 F4R1 Filter bank 4 register 1 0x260 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R2 F4R2 Filter bank 4 register 2 0x264 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R1 F5R1 Filter bank 5 register 1 0x268 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R2 F5R2 Filter bank 5 register 2 0x26C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R1 F6R1 Filter bank 6 register 1 0x270 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R2 F6R2 Filter bank 6 register 2 0x274 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R1 F7R1 Filter bank 7 register 1 0x278 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R2 F7R2 Filter bank 7 register 2 0x27C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R1 F8R1 Filter bank 8 register 1 0x280 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R2 F8R2 Filter bank 8 register 2 0x284 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R1 F9R1 Filter bank 9 register 1 0x288 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R2 F9R2 Filter bank 9 register 2 0x28C 32 read-write n 0x0 0x0 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FA1R FA1R filter activation register 0x21C 32 read-write n 0x0 0x0 FACT0 Filter active 0 1 FACT1 Filter active 1 1 FACT10 Filter active 10 1 FACT11 Filter active 11 1 FACT12 Filter active 12 1 FACT13 Filter active 13 1 FACT14 Filter active 14 1 FACT15 Filter active 15 1 FACT16 Filter active 16 1 FACT17 Filter active 17 1 FACT18 Filter active 18 1 FACT19 Filter active 19 1 FACT2 Filter active 2 1 FACT20 Filter active 20 1 FACT21 Filter active 21 1 FACT22 Filter active 22 1 FACT23 Filter active 23 1 FACT24 Filter active 24 1 FACT25 Filter active 25 1 FACT26 Filter active 26 1 FACT27 Filter active 27 1 FACT3 Filter active 3 1 FACT4 Filter active 4 1 FACT5 Filter active 5 1 FACT6 Filter active 6 1 FACT7 Filter active 7 1 FACT8 Filter active 8 1 FACT9 Filter active 9 1 FFA1R FFA1R filter FIFO assignment register 0x214 32 read-write n 0x0 0x0 FFA0 Filter FIFO assignment for filter 0 0 1 FFA1 Filter FIFO assignment for filter 1 1 1 FFA10 Filter FIFO assignment for filter 10 10 1 FFA11 Filter FIFO assignment for filter 11 11 1 FFA12 Filter FIFO assignment for filter 12 12 1 FFA13 Filter FIFO assignment for filter 13 13 1 FFA14 Filter FIFO assignment for filter 14 1 FFA15 Filter FIFO assignment for filter 15 1 FFA16 Filter FIFO assignment for filter 16 1 FFA17 Filter FIFO assignment for filter 17 1 FFA18 Filter FIFO assignment for filter 18 1 FFA19 Filter FIFO assignment for filter 19 1 FFA2 Filter FIFO assignment for filter 2 2 1 FFA20 Filter FIFO assignment for filter 20 1 FFA21 Filter FIFO assignment for filter 21 1 FFA22 Filter FIFO assignment for filter 22 1 FFA23 Filter FIFO assignment for filter 23 1 FFA24 Filter FIFO assignment for filter 24 1 FFA25 Filter FIFO assignment for filter 25 1 FFA26 Filter FIFO assignment for filter 26 1 FFA27 Filter FIFO assignment for filter 27 1 FFA3 Filter FIFO assignment for filter 3 3 1 FFA4 Filter FIFO assignment for filter 4 4 1 FFA5 Filter FIFO assignment for filter 5 5 1 FFA6 Filter FIFO assignment for filter 6 6 1 FFA7 Filter FIFO assignment for filter 7 7 1 FFA8 Filter FIFO assignment for filter 8 8 1 FFA9 Filter FIFO assignment for filter 9 9 1 FM1R FM1R filter mode register 0x204 32 read-write n 0x0 0x0 FBM0 Filter mode 0 1 FBM1 Filter mode 1 1 FBM10 Filter mode 10 1 FBM11 Filter mode 11 1 FBM12 Filter mode 12 1 FBM13 Filter mode 13 1 FBM14 Filter mode 14 1 FBM15 Filter mode 15 1 FBM16 Filter mode 16 1 FBM17 Filter mode 17 1 FBM18 Filter mode 18 1 FBM19 Filter mode 19 1 FBM2 Filter mode 2 1 FBM20 Filter mode 20 1 FBM21 Filter mode 21 1 FBM22 Filter mode 22 1 FBM23 Filter mode 23 1 FBM24 Filter mode 24 1 FBM25 Filter mode 25 1 FBM26 Filter mode 26 1 FBM27 Filter mode 27 1 FBM3 Filter mode 3 1 FBM4 Filter mode 4 1 FBM5 Filter mode 5 1 FBM6 Filter mode 6 1 FBM7 Filter mode 7 1 FBM8 Filter mode 8 1 FBM9 Filter mode 9 1 FMR FMR filter master register 0x200 32 read-write n 0x0 0x0 CANSB CAN start bank 8 6 FINIT Filter initialization mode 0 1 FS1R FS1R filter scale register 0x20C 32 read-write n 0x0 0x0 FSC0 Filter scale configuration 0 1 FSC1 Filter scale configuration 1 1 FSC10 Filter scale configuration 10 1 FSC11 Filter scale configuration 11 1 FSC12 Filter scale configuration 12 1 FSC13 Filter scale configuration 13 1 FSC14 Filter scale configuration 14 1 FSC15 Filter scale configuration 15 1 FSC16 Filter scale configuration 16 1 FSC17 Filter scale configuration 17 1 FSC18 Filter scale configuration 18 1 FSC19 Filter scale configuration 19 1 FSC2 Filter scale configuration 2 1 FSC20 Filter scale configuration 20 1 FSC21 Filter scale configuration 21 1 FSC22 Filter scale configuration 22 1 FSC23 Filter scale configuration 23 1 FSC24 Filter scale configuration 24 1 FSC25 Filter scale configuration 25 1 FSC26 Filter scale configuration 26 1 FSC27 Filter scale configuration 27 1 FSC3 Filter scale configuration 3 1 FSC4 Filter scale configuration 4 1 FSC5 Filter scale configuration 5 1 FSC6 Filter scale configuration 6 1 FSC7 Filter scale configuration 7 1 FSC8 Filter scale configuration 8 1 FSC9 Filter scale configuration 9 1 IER IER interrupt enable register 0x14 32 read-write n 0x0 0x0 BOFIE BOFIE 10 1 EPVIE EPVIE 9 1 ERRIE ERRIE 15 1 EWGIE EWGIE 8 1 FFIE0 FFIE0 2 1 FFIE1 FFIE1 5 1 FMPIE0 FMPIE0 1 1 FMPIE1 FMPIE1 4 1 FOVIE0 FOVIE0 3 1 FOVIE1 FOVIE1 6 1 LECIE LECIE 11 1 SLKIE SLKIE 17 1 TMEIE TMEIE 0 1 WKUIE WKUIE 16 1 MCR MCR master control register 0x0 32 read-write n 0x0 0x0 ABOM ABOM 6 1 AWUM AWUM 5 1 DBF DBF 16 1 INRQ INRQ 0 1 NART NART 4 1 RESET RESET 15 1 RFLM RFLM 3 1 SLEEP SLEEP 1 1 TTCM TTCM 7 1 TXFP TXFP 2 1 MSR MSR master status register 0x4 32 read-write n 0x0 0x0 ERRI ERRI 2 1 read-write INAK INAK 0 1 read-only RX RX 11 1 read-only RXM RXM 9 1 read-only SAMP SAMP 10 1 read-only SLAK SLAK 1 1 read-only SLAKI SLAKI 4 1 read-write TXM TXM 8 1 read-only WKUI WKUI 3 1 read-write RDH0R RDH0R receive FIFO mailbox data high register 0x1BC 32 read-only n 0x0 0x0 DATA4 DATA4 0 8 DATA5 DATA5 8 8 DATA6 DATA6 16 8 DATA7 DATA7 24 8 RDH1R RDH1R mailbox data high register 0x1CC 32 read-only n 0x0 0x0 DATA4 DATA4 0 8 DATA5 DATA5 8 8 DATA6 DATA6 16 8 DATA7 DATA7 24 8 RDL0R RDL0R mailbox data high register 0x1B8 32 read-only n 0x0 0x0 DATA0 DATA0 0 8 DATA1 DATA1 8 8 DATA2 DATA2 16 8 DATA3 DATA3 24 8 RDL1R RDL1R mailbox data high register 0x1C8 32 read-only n 0x0 0x0 DATA0 DATA0 0 8 DATA1 DATA1 8 8 DATA2 DATA2 16 8 DATA3 DATA3 24 8 RDT0R RDT0R mailbox data high register 0x1B4 32 read-only n 0x0 0x0 DLC DLC 0 4 FMI FMI 8 8 TIME TIME 16 16 RDT1R RDT1R mailbox data high register 0x1C4 32 read-only n 0x0 0x0 DLC DLC 0 4 FMI FMI 8 8 TIME TIME 16 16 RF0R RF0R receive FIFO 0 register 0xC 32 read-write n 0x0 0x0 FMP0 FMP0 0 2 read-only FOVR0 FOVR0 4 1 read-write FULL0 FULL0 3 1 read-write RFOM0 RFOM0 5 1 read-write RF1R RF1R receive FIFO 1 register 0x10 32 read-write n 0x0 0x0 FMP1 FMP1 0 2 read-only FOVR1 FOVR1 4 1 read-write FULL1 FULL1 3 1 read-write RFOM1 RFOM1 5 1 read-write RI0R RI0R receive FIFO mailbox identifier register 0x1B0 32 read-only n 0x0 0x0 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 STID STID 21 11 RI1R RI1R mailbox data high register 0x1C0 32 read-only n 0x0 0x0 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 STID STID 21 11 TDH0R TDH0R mailbox data high register 0x18C 32 read-write n 0x0 0x0 DATA4 DATA4 0 8 DATA5 DATA5 8 8 DATA6 DATA6 16 8 DATA7 DATA7 24 8 TDH1R TDH1R mailbox data high register 0x19C 32 read-write n 0x0 0x0 DATA4 DATA4 0 8 DATA5 DATA5 8 8 DATA6 DATA6 16 8 DATA7 DATA7 24 8 TDH2R TDH2R mailbox data high register 0x1AC 32 read-write n 0x0 0x0 DATA4 DATA4 0 8 DATA5 DATA5 8 8 DATA6 DATA6 16 8 DATA7 DATA7 24 8 TDL0R TDL0R mailbox data low register 0x188 32 read-write n 0x0 0x0 DATA0 DATA0 0 8 DATA1 DATA1 8 8 DATA2 DATA2 16 8 DATA3 DATA3 24 8 TDL1R TDL1R mailbox data low register 0x198 32 read-write n 0x0 0x0 DATA0 DATA0 0 8 DATA1 DATA1 8 8 DATA2 DATA2 16 8 DATA3 DATA3 24 8 TDL2R TDL2R mailbox data low register 0x1A8 32 read-write n 0x0 0x0 DATA0 DATA0 0 8 DATA1 DATA1 8 8 DATA2 DATA2 16 8 DATA3 DATA3 24 8 TDT0R TDT0R mailbox data length control and time stamp register 0x184 32 read-write n 0x0 0x0 DLC DLC 0 4 TGT TGT 8 1 TIME TIME 16 16 TDT1R TDT1R mailbox data length control and time stamp register 0x194 32 read-write n 0x0 0x0 DLC DLC 0 4 TGT TGT 8 1 TIME TIME 16 16 TDT2R TDT2R mailbox data length control and time stamp register 0x1A4 32 read-write n 0x0 0x0 DLC DLC 0 4 TGT TGT 8 1 TIME TIME 16 16 TI0R TI0R TX mailbox identifier register 0x180 32 read-write n 0x0 0x0 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 STID STID 21 11 TXRQ TXRQ 0 1 TI1R TI1R mailbox identifier register 0x190 32 read-write n 0x0 0x0 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 STID STID 21 11 TXRQ TXRQ 0 1 TI2R TI2R mailbox identifier register 0x1A0 32 read-write n 0x0 0x0 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 STID STID 21 11 TXRQ TXRQ 0 1 TSR TSR transmit status register 0x8 32 read-write n 0x0 0x0 ABRQ0 ABRQ0 7 1 read-write ABRQ1 ABRQ1 15 1 read-write ABRQ2 ABRQ2 23 1 read-write ALST0 ALST0 2 1 read-write ALST1 ALST1 10 1 read-write ALST2 ALST2 18 1 read-write CODE CODE 24 2 read-only LOW0 Lowest priority flag for mailbox 0 29 1 read-only LOW1 Lowest priority flag for mailbox 1 30 1 read-only LOW2 Lowest priority flag for mailbox 2 31 1 read-only RQCP0 RQCP0 0 1 read-write RQCP1 RQCP1 8 1 read-write RQCP2 RQCP2 16 1 read-write TERR0 TERR0 3 1 read-write TERR1 TERR1 11 1 read-write TERR2 TERR2 19 1 read-write TME0 Lowest priority flag for mailbox 0 26 1 read-only TME1 Lowest priority flag for mailbox 1 27 1 read-only TME2 Lowest priority flag for mailbox 2 28 1 read-only TXOK0 TXOK0 1 1 read-write TXOK1 TXOK1 9 1 read-write TXOK2 TXOK2 17 1 read-write COMP Comparator COMP 0x0 0x0 0x200 registers n COMP COMP1 and COMP2 interrupts 64 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 32 read-write n 0x0 0x0 COMP1_BLANKING Comparator 1 blanking source selection bits 18 3 read-write COMP1_BRGEN Scaler bridge enable 22 1 read-write COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 3 read-write COMP1_INPSEL Comparator1 input plus selection bit 7 1 read-write COMP1_LOCK COMP1_CSR register lock bit 31 1 write-only COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_PWRMODE Power Mode of the comparator 1 2 2 read-write COMP1_SCALEN Voltage scaler enable bit 23 1 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 32 read-write n 0x0 0x0 COMP2_BLANKING Comparator 2 blanking source selection bits 18 3 read-write COMP2_BRGEN Scaler bridge enable 22 1 read-write COMP2_EN Comparator 2 enable bit 0 1 read-write COMP2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COMP2_INMSEL Comparator 2 Input Minus connection configuration bit 4 3 read-write COMP2_INPSEL Comparator 2 Input Plus connection configuration bit 7 1 read-write COMP2_LOCK COMP2_CSR register lock bit 31 1 write-only COMP2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COMP2_PWRMODE Power Mode of the comparator 2 2 2 read-write COMP2_SCALEN Voltage scaler enable bit 23 1 read-write COMP2_VALUE Comparator 2 output status bit 30 1 read-only COMP2_WINMODE Windows mode selection bit 9 1 read-write CRC Cyclic redundancy check calculation unit CRC 0x0 0x0 0x400 registers n CR CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only REV_IN Reverse input data 5 2 read-write REV_OUT Reverse output data 7 1 read-write DR DR Data register 0x0 32 read-write n 0x0 0x0 DR Data register bits 0 32 IDR IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR General-purpose 8-bit data register bits 0 8 INIT INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 32 read-write n 0x0 0x0 Polynomialcoefficients Programmable polynomial 0 32 CRS Clock recovery system CRS 0x0 0x0 0x400 registers n CRS CRS global interrupt 82 CFGR CFGR configuration register 0x4 32 read-write n 0x0 0x0 FELIM Frequency error limit 16 8 RELOAD Counter reload value 0 16 SYNCDIV SYNC divider 24 3 SYNCPOL SYNC polarity selection 31 1 SYNCSRC SYNC signal source selection 28 2 CR CR control register 0x0 32 read-write n 0x0 0x0 AUTOTRIMEN Automatic trimming enable 6 1 CEN Frequency error counter enable 5 1 ERRIE Synchronization or trimming error interrupt enable 2 1 ESYNCIE Expected SYNC interrupt enable 3 1 SWSYNC Generate software SYNC event 7 1 SYNCOKIE SYNC event OK interrupt enable 0 1 SYNCWARNIE SYNC warning interrupt enable 1 1 TRIM HSI48 oscillator smooth trimming 8 6 ICR ICR interrupt flag clear register 0xC 32 read-write n 0x0 0x0 ERRC Error clear flag 2 1 ESYNCC Expected SYNC clear flag 3 1 SYNCOKC SYNC event OK clear flag 0 1 SYNCWARNC SYNC warning clear flag 1 1 ISR ISR interrupt and status register 0x8 32 read-only n 0x0 0x0 ERRF Error flag 2 1 ESYNCF Expected SYNC flag 3 1 FECAP Frequency error capture 16 16 FEDIR Frequency error direction 15 1 SYNCERR SYNC error 8 1 SYNCMISS SYNC missed 9 1 SYNCOKF SYNC event OK flag 0 1 SYNCWARNF SYNC warning flag 1 1 TRIMOVF Trimming overflow or underflow 10 1 DAC Digital-to-analog converter DAC 0x0 0x0 0x400 registers n CCR CCR calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 CR CR control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable 14 1 CEN2 DAC Channel 2 calibration enable 30 1 DMAEN1 DAC channel1 DMA enable 12 1 DMAEN2 DAC channel2 DMA enable 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable 29 1 EN1 DAC channel1 enable 0 1 EN2 DAC channel2 enable 16 1 MAMP1 DAC channel1 mask/amplitude selector 8 4 MAMP2 DAC channel2 mask/amplitude selector 24 4 TEN1 DAC channel1 trigger enable 2 1 TEN2 DAC channel2 trigger enable 18 1 TSEL1 DAC channel1 trigger selection 3 3 TSEL2 DAC channel2 trigger selection 19 3 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 DHR12L1 DHR12L1 channel1 12-bit left-aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DHR12L2 DHR12L2 channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DACC2DHR DAC channel2 12-bit left-aligned data 20 12 DHR12R1 DHR12R1 channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DHR12R2 DHR12R2 channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 DHR8R1 DHR8R1 channel1 8-bit right-aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DHR8R2 DHR8R2 channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data 0 8 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 DOR1 DOR1 channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output 0 12 MCR MCR mode control register 0x3C 32 read-write n 0x0 0x0 MODE1 DAC Channel 1 mode 0 3 MODE2 DAC Channel 2 mode 16 3 SHHR SHHR Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time 0 10 THOLD2 DAC Channel 2 hold time 16 10 SHRR SHRR Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time 0 8 TREFRESH2 DAC Channel 2 refresh Time 16 8 SHSR1 SHSR1 Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time 0 10 SHSR2 SHSR2 Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time 0 10 SR SR status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status 30 1 read-only DMAUDR1 DAC channel1 DMA underrun flag 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag 29 1 read-write SWTRIGR SWTRIGR software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG2 DAC channel2 software trigger 1 1 DBGMCU Debug support DBGMCU 0x0 0x0 0x400 registers n APB1_FZR1 APB1_FZR1 APB Low Freeze Register 1 0x8 32 read-write n 0x0 0x0 DBG_CAN_STOP bxCAN stopped when core is halted 25 1 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted 23 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_LPTIMER_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 APB1_FZR2 APB1_FZR2 APB Low Freeze Register 2 0xC 32 read-write n 0x0 0x0 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 APB2_FZR APB2_FZR APB High Freeze Register 0x10 32 read-write n 0x0 0x0 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 13 1 CR CR Debug MCU Configuration Register 0x4 32 read-write n 0x0 0x0 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STANDBY Debug Standby Mode 2 1 DBG_STOP Debug Stop Mode 1 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 IDCODE IDCODE MCU Device ID Code Register 0x0 32 read-only n 0x0 0x0 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 DCMI Digital camera interface DCMI 0x0 0x0 0x400 registers n DCMI DCMI global interrupt 85 CR CR control register 1 0x0 32 read-write n 0x0 0x0 BSM Byte Select mode 16 2 CAPTURE Capture enable 0 1 CM Capture mode 1 1 CROP Crop feature 2 1 EDM Extended data mode 10 2 ENABLE DCMI enable 14 1 ESS Embedded synchronization select 4 1 FCRC Frame capture rate control 8 2 HSPOL Horizontal synchronization polarity 6 1 JPEG JPEG format 3 1 LSM Line Select mode 19 1 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 OELS Odd/Even Line Select (Line Select Start) 20 1 PCKPOL Pixel clock polarity 5 1 VSPOL Vertical synchronization polarity 7 1 CWSIZE CWSIZE crop window size 0x24 32 read-write n 0x0 0x0 CAPCNT Capture count 0 14 VLINE Vertical line count 16 14 CWSTRT CWSTRT crop window start 0x20 32 read-write n 0x0 0x0 HOFFCNT Horizontal offset count 0 14 VST Vertical start line count 16 13 DR DR data register 0x28 32 read-only n 0x0 0x0 Byte0 Data byte 0 0 8 Byte1 Data byte 1 8 8 Byte2 Data byte 2 16 8 Byte3 Data byte 3 24 8 ESCR ESCR embedded synchronization code register 0x18 32 read-write n 0x0 0x0 FEC Frame end delimiter code 24 8 FSC Frame start delimiter code 0 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 ESUR ESUR embedded synchronization unmask register 0x1C 32 read-write n 0x0 0x0 FEU Frame end delimiter unmask 24 8 FSU Frame start delimiter unmask 0 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 ICR ICR interrupt clear register 0x14 32 write-only n 0x0 0x0 ERR_ISC Synchronization error interrupt status clear 2 1 FRAME_ISC Capture complete interrupt status clear 0 1 LINE_ISC line interrupt status clear 4 1 OVR_ISC Overrun interrupt status clear 1 1 VSYNC_ISC Vertical synch interrupt status clear 3 1 IER IER interrupt enable register 0xC 32 read-write n 0x0 0x0 ERR_IE Synchronization error interrupt enable 2 1 FRAME_IE Capture complete interrupt enable 0 1 LINE_IE Line interrupt enable 4 1 OVR_IE Overrun interrupt enable 1 1 VSYNC_IE VSYNC interrupt enable 3 1 MIS MIS masked interrupt status register 0x10 32 read-only n 0x0 0x0 ERR_MIS Synchronization error masked interrupt status 2 1 FRAME_MIS Capture complete masked interrupt status 0 1 LINE_MIS Line masked interrupt status 4 1 OVR_MIS Overrun masked interrupt status 1 1 VSYNC_MIS VSYNC masked interrupt status 3 1 RIS RIS raw interrupt status register 0x8 32 read-only n 0x0 0x0 ERR_RIS Synchronization error raw interrupt status 2 1 FRAME_RIS Capture complete raw interrupt status 0 1 LINE_RIS Line raw interrupt status 4 1 OVR_RIS Overrun raw interrupt status 1 1 VSYNC_RIS VSYNC raw interrupt status 3 1 SR SR status register 0x4 32 read-only n 0x0 0x0 FNE FIFO not empty 2 1 HSYNC HSYNC 0 1 VSYNC VSYNC 1 1 DFSDM1 Digital filter for sigma delta modulators DFSDM 0x0 0x0 0x500 registers n DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 42 DFSDM1_FLT0 DFSDM1_FLT0 global interrupt 61 DFSDM1_FLT1 DFSDM1_FLT1 global interrupt 62 DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 63 AWCFR DFSDM1_AWCFR analog watchdog clear flag register 0x22C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 AWHTR DFSDM1_AWHTR analog watchdog high threshold register 0x220 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 AWLTR DFSDM1_AWLTR analog watchdog low threshold register 0x224 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 AWSCD0R AWSCD0R analog watchdog and short-circuit detector register 0x8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD1R AWSCD1R AWSCD1R 0x28 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD2R AWSCD2R AWSCD2R 0x48 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD3R AWSCD3R AWSCD3R 0x68 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD4R AWSCD4R AWSCD4R 0x88 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD5R AWSCD5R AWSCD5R 0xA8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD6R AWSCD6R AWSCD6R 0xC8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSCD7R AWSCD7R AWSCD7R 0xE8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 AWSR DFSDM1_AWSR analog watchdog status register 0x228 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 CH0AWSCDR CH0AWSCDR analog watchdog and short-circuit detector register 0x8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH0CFGR1 CH0CFGR1 channel configuration y register 0x0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH0CFGR2 CH0CFGR2 channel configuration y register 0x4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH0DATINR CH0DATINR channel data input register 0x10 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH0DLYR CH0DLYR channel y delay register 0x14 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH0WDATR CH0WDATR channel watchdog filter data register 0xC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH1AWSCDR CH1AWSCDR CH1AWSCDR 0x28 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH1CFGR1 CH1CFGR1 CH1CFGR1 0x20 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH1CFGR2 CH1CFGR2 CH1CFGR2 0x24 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH1DATINR CH1DATINR CH1DATINR 0x30 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH1DLYR CH1DLYR channel y delay register 0x34 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH1WDATR CH1WDATR CH1WDATR 0x2C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH2AWSCDR CH2AWSCDR CH2AWSCDR 0x48 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH2CFGR1 CH2CFGR1 CH2CFGR1 0x40 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH2CFGR2 CH2CFGR2 CH2CFGR2 0x44 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH2DATINR CH2DATINR CH2DATINR 0x50 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH2DLYR CH2DLYR channel y delay register 0x54 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH2WDATR CH2WDATR CH2WDATR 0x4C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH3AWSCDR CH3AWSCDR CH3AWSCDR 0x68 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH3CFGR1 CH3CFGR1 CH3CFGR1 0x60 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH3CFGR2 CH3CFGR2 CH3CFGR2 0x64 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH3DATINR CH3DATINR CH3DATINR 0x70 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH3DLYR CH3DLYR channel y delay register 0x74 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH3WDATR CH3WDATR CH3WDATR 0x6C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH4AWSCDR CH4AWSCDR CH4AWSCDR 0x88 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH4CFGR1 CH4CFGR1 CH4CFGR1 0x80 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH4CFGR2 CH4CFGR2 CH4CFGR2 0x84 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH4DATINR CH4DATINR CH4DATINR 0x90 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH4DLYR CH4DLYR channel y delay register 0x94 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH4WDATR CH4WDATR CH4WDATR 0x8C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH5AWSCDR CH5AWSCDR CH5AWSCDR 0xA8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH5CFGR1 CH5CFGR1 CH5CFGR1 0xA0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH5CFGR2 CH5CFGR2 CH5CFGR2 0xA4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH5DATINR CH5DATINR CH5DATINR 0xB0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH5DLYR CH5DLYR channel y delay register 0xB4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH5WDATR CH5WDATR CH5WDATR 0xAC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH6AWSCDR CH6AWSCDR CH6AWSCDR 0xC8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH6CFGR1 CH6CFGR1 CH6CFGR1 0xC0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH6CFGR2 CH6CFGR2 CH6CFGR2 0xC4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH6DATINR CH6DATINR CH6DATINR 0xD0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH6DLYR CH6DLYR channel y delay register 0xD4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH6WDATR CH6WDATR CH6WDATR 0xCC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CH7AWSCDR CH7AWSCDR CH7AWSCDR 0xE8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CH7CFGR1 CH7CFGR1 CH7CFGR1 0xE0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CH7CFGR2 CH7CFGR2 CH7CFGR2 0xE4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CH7DATINR CH7DATINR CH7DATINR 0xF0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CH7DLYR CH7DLYR channel y delay register 0xF4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 CH7WDATR CH7WDATR CH7WDATR 0xEC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHCFG0R1 CHCFG0R1 channel configuration y register 0x0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG0R2 CHCFG0R2 channel configuration y register 0x4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG1R1 CHCFG1R1 CHCFG1R1 0x20 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG1R2 CHCFG1R2 CHCFG1R2 0x24 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG2R1 CHCFG2R1 CHCFG2R1 0x40 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG2R2 CHCFG2R2 CHCFG2R2 0x44 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG3R1 CHCFG3R1 CHCFG3R1 0x60 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG3R2 CHCFG3R2 CHCFG3R2 0x64 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG4R1 CHCFG4R1 CHCFG4R1 0x80 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG4R2 CHCFG4R2 CHCFG4R2 0x84 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG5R1 CHCFG5R1 CHCFG5R1 0xA0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG5R2 CHCFG5R2 CHCFG5R2 0xA4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG6R1 CHCFG6R1 CHCFG6R1 0xC0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG6R2 CHCFG6R2 CHCFG6R2 0xC4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHCFG7R1 CHCFG7R1 CHCFG7R1 0xE0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 CHCFG7R2 CHCFG7R2 CHCFG7R2 0xE4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 CHDATIN0R CHDATIN0R channel data input register 0x10 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN1R CHDATIN1R CHDATIN1R 0x30 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN2R CHDATIN2R CHDATIN2R 0x50 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN3R CHDATIN3R CHDATIN3R 0x70 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN4R CHDATIN4R CHDATIN4R 0x90 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN5R CHDATIN5R CHDATIN5R 0xB0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN6R CHDATIN6R CHDATIN6R 0xD0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHDATIN7R CHDATIN7R CHDATIN7R 0xF0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 CHWDAT0R CHWDAT0R channel watchdog filter data register 0xC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT1R CHWDAT1R CHWDAT1R 0x2C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT2R CHWDAT2R CHWDAT2R 0x4C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT3R CHWDAT3R CHWDAT3R 0x6C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT4R CHWDAT4R CHWDAT4R 0x8C 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT5R CHWDAT5R CHWDAT5R 0xAC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT6R CHWDAT6R CHWDAT6R 0xCC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CHWDAT7R CHWDAT7R CHWDAT7R 0xEC 32 read-write n 0x0 0x0 WDATA WDATA 0 16 CNVTIMR DFSDM1_CNVTIMR conversion timer register 0x238 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 CR1 DFSDM1_CR1 control register 1 0x200 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 CR2 DFSDM1_CR2 control register 2 0x204 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM0_AWCFR DFSDM0_AWCFR analog watchdog clear flag register 0x12C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM0_AWHTR DFSDM0_AWHTR analog watchdog high threshold register 0x120 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM0_AWLTR DFSDM0_AWLTR analog watchdog low threshold register 0x124 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM0_AWSR DFSDM0_AWSR analog watchdog status register 0x128 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM0_CNVTIMR DFSDM0_CNVTIMR conversion timer register 0x138 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM0_CR1 DFSDM0_CR1 control register 1 0x100 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM0_CR2 DFSDM0_CR2 control register 2 0x104 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM0_EXMAX DFSDM0_EXMAX Extremes detector maximum register 0x130 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM0_EXMIN DFSDM0_EXMIN Extremes detector minimum register 0x134 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM0_FCR DFSDM0_FCR filter control register 0x114 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM0_ICR DFSDM0_ICR interrupt flag clear register 0x10C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM0_ISR DFSDM0_ISR interrupt and status register 0x108 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM0_JCHGR DFSDM0_JCHGR injected channel group selection register 0x110 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM0_JDATAR DFSDM0_JDATAR data register for injected group 0x118 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM0_RDATAR DFSDM0_RDATAR data register for the regular channel 0x11C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM2_AWCFR DFSDM2_AWCFR analog watchdog clear flag register 0x32C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM2_AWHTR DFSDM2_AWHTR analog watchdog high threshold register 0x320 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM2_AWLTR DFSDM2_AWLTR analog watchdog low threshold register 0x324 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM2_AWSR DFSDM2_AWSR analog watchdog status register 0x328 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM2_CNVTIMR DFSDM2_CNVTIMR conversion timer register 0x338 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM2_CR1 DFSDM2_CR1 control register 1 0x300 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM2_CR2 DFSDM2_CR2 control register 2 0x304 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM2_EXMAX DFSDM2_EXMAX Extremes detector maximum register 0x330 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM2_EXMIN DFSDM2_EXMIN Extremes detector minimum register 0x334 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM2_FCR DFSDM2_FCR filter control register 0x314 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM2_ICR DFSDM2_ICR interrupt flag clear register 0x30C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM2_ISR DFSDM2_ISR interrupt and status register 0x308 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM2_JCHGR DFSDM2_JCHGR injected channel group selection register 0x310 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM2_JDATAR DFSDM2_JDATAR data register for injected group 0x318 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM2_RDATAR DFSDM2_RDATAR data register for the regular channel 0x31C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM3_AWCFR DFSDM3_AWCFR analog watchdog clear flag register 0x42C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM3_AWHTR DFSDM3_AWHTR analog watchdog high threshold register 0x420 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM3_AWLTR DFSDM3_AWLTR analog watchdog low threshold register 0x424 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM3_AWSR DFSDM3_AWSR analog watchdog status register 0x428 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM3_CNVTIMR DFSDM3_CNVTIMR conversion timer register 0x438 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM3_CR1 DFSDM3_CR1 control register 1 0x400 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM3_CR2 DFSDM3_CR2 control register 2 0x404 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM3_EXMAX DFSDM3_EXMAX Extremes detector maximum register 0x430 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM3_EXMIN DFSDM3_EXMIN Extremes detector minimum register 0x434 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM3_FCR DFSDM3_FCR filter control register 0x414 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM3_ICR DFSDM3_ICR interrupt flag clear register 0x40C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM3_ISR DFSDM3_ISR interrupt and status register 0x408 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM3_JCHGR DFSDM3_JCHGR injected channel group selection register 0x410 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM3_JDATAR DFSDM3_JDATAR data register for injected group 0x418 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM3_RDATAR DFSDM3_RDATAR data register for the regular channel 0x41C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR analog watchdog clear flag register 0x12C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR analog watchdog high threshold register 0x120 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR analog watchdog low threshold register 0x124 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM_FLT0AWSR DFSDM_FLT0AWSR analog watchdog status register 0x128 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR conversion timer register 0x138 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM_FLT0CR1 DFSDM_FLT0CR1 control register 1 0x100 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM_FLT0CR2 DFSDM_FLT0CR2 control register 2 0x104 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX Extremes detector maximum register 0x130 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN Extremes detector minimum register 0x134 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM_FLT0FCR DFSDM_FLT0FCR filter control register 0x114 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM_FLT0ICR DFSDM_FLT0ICR interrupt flag clear register 0x10C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM_FLT0ISR DFSDM_FLT0ISR interrupt and status register 0x108 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR injected channel group selection register 0x110 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR data register for injected group 0x118 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR data register for the regular channel 0x11C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR analog watchdog clear flag register 0x1AC 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR analog watchdog high threshold register 0x1A0 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR analog watchdog low threshold register 0x1A4 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM_FLT1AWSR DFSDM_FLT1AWSR analog watchdog status register 0x1A8 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM_FLT1CHGR DFSDM_FLT1JCHGR injected channel group selection register 0x190 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR conversion timer register 0x1B8 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM_FLT1CR1 DFSDM_FLT1CR1 control register 1 0x180 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM_FLT1CR2 DFSDM_FLT1CR2 control register 2 0x184 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX Extremes detector maximum register 0x1B0 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN Extremes detector minimum register 0x1B4 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM_FLT1FCR DFSDM1_FCR filter control register 0x194 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM_FLT1ICR DFSDM1_ICR interrupt flag clear register 0x18C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM_FLT1ISR DFSDM_FLT1ISR interrupt and status register 0x188 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR data register for injected group 0x198 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR data register for the regular channel 0x19C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR analog watchdog clear flag register 0x22C 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR analog watchdog high threshold register 0x220 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR analog watchdog low threshold register 0x224 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM_FLT2AWSR DFSDM_FLT2AWSR analog watchdog status register 0x228 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR conversion timer register 0x238 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM_FLT2CR1 DFSDM_FLT2CR1 control register 1 0x200 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM_FLT2CR2 DFSDM_FLT2CR2 control register 2 0x204 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX Extremes detector maximum register 0x230 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN Extremes detector minimum register 0x234 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM_FLT2FCR DFSDM_FLT2FCR filter control register 0x214 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM_FLT2ICR DFSDM_FLT2ICR interrupt flag clear register 0x20C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM_FLT2ISR DFSDM_FLT2ISR interrupt and status register 0x208 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR injected channel group selection register 0x210 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR data register for injected group 0x218 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR data register for the regular channel 0x21C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR analog watchdog clear flag register 0x2AC 32 read-write n 0x0 0x0 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR analog watchdog high threshold register 0x2A0 32 read-write n 0x0 0x0 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR analog watchdog low threshold register 0x2A4 32 read-write n 0x0 0x0 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM_FLT3AWSR DFSDM_FLT3AWSR analog watchdog status register 0x2A8 32 read-only n 0x0 0x0 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR conversion timer register 0x2B8 32 read-only n 0x0 0x0 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM_FLT3CR1 DFSDM_FLT3CR1 control register 1 0x280 32 read-write n 0x0 0x0 AWFSEL Analog watchdog fast mode select 30 1 DFEN DFSDM enable 0 1 FAST Fast conversion mode selection for regular conversions 29 1 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JSCAN Scanning conversion mode for injected conversions 4 1 JSWSTART Start a conversion of the injected group of channels 1 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 RCH Regular channel selection 24 3 RCONT Continuous mode selection for regular conversions 18 1 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSWSTART Software start of a conversion on the regular channel 17 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 DFSDM_FLT3CR2 DFSDM_FLT3CR2 control register 2 0x284 32 read-write n 0x0 0x0 AWDCH Analog watchdog channel selection 16 8 AWDIE Analog watchdog interrupt enable 4 1 CKABIE Clock absence interrupt enable 6 1 EXCH Extremes detector channel selection 8 8 JEOCIE Injected end of conversion interrupt enable 0 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 ROVRIE Regular data overrun interrupt enable 3 1 SCDIE Short-circuit detector interrupt enable 5 1 DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX Extremes detector maximum register 0x2B0 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN Extremes detector minimum register 0x2B4 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM_FLT3FCR DFSDM_FLT3FCR filter control register 0x294 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM_FLT3ICR DFSDM_FLT3ICR interrupt flag clear register 0x28C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 DFSDM_FLT3ISR DFSDM_FLT3ISR interrupt and status register 0x288 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR injected channel group selection register 0x290 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR data register for injected group 0x298 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR data register for the regular channel 0x29C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 EXMAX DFSDM1_EXMAX Extremes detector maximum register 0x230 32 read-only n 0x0 0x0 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 EXMIN DFSDM1_EXMIN Extremes detector minimum register 0x234 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 FCR DFSDM1_FCR filter control register 0x214 32 read-write n 0x0 0x0 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 ICR DFSDM1_ICR interrupt flag clear register 0x20C 32 read-write n 0x0 0x0 CLRCKABF Clear the clock absence flag 16 8 CLRJOVRF Clear the injected conversion overrun flag 2 1 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRSCDF Clear the short-circuit detector flag 24 8 ISR DFSDM1_ISR interrupt and status register 0x208 32 read-only n 0x0 0x0 AWDF Analog watchdog 4 1 CKABF Clock absence flag 16 8 JCIP Injected conversion in progress status 13 1 JEOCF End of injected conversion flag 0 1 JOVRF Injected conversion overrun flag 2 1 RCIP Regular conversion in progress status 14 1 REOCF End of regular conversion flag 1 1 ROVRF Regular conversion overrun flag 3 1 SCDF short-circuit detector flag 24 8 JCHGR DFSDM1_JCHGR injected channel group selection register 0x210 32 read-write n 0x0 0x0 JCHG Injected channel group selection 0 8 JDATAR DFSDM1_JDATAR data register for injected group 0x218 32 read-only n 0x0 0x0 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 RDATAR DFSDM1_RDATAR data register for the regular channel 0x21C 32 read-only n 0x0 0x0 RDATA Regular channel conversion data 8 24 RDATACH Regular channel most recently converted 0 3 RPEND Regular channel pending data 4 1 DMA1 Direct memory access controller DMA 0x0 0x0 0x400 registers n DMA1_CH1 DMA1 Channel1 global interrupt 11 DMA1_CH2 DMA1 Channel2 global interrupt 12 DMA1_CH3 DMA1 Channel3 interrupt 13 DMA1_CH4 DMA1 Channel4 interrupt 14 DMA1_CH5 DMA1 Channel5 interrupt 15 DMA1_CH6 DMA1 Channel6 interrupt 16 DMA1_CH7 DMA1 Channel 7 interrupt 17 DMAMUX_OVR DMAMUX Overrun interrupt 94 CCR1 CCR1 channel x configuration register 0x8 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR2 CCR2 channel x configuration register 0x1C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR3 CCR3 channel x configuration register 0x30 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR4 CCR4 channel x configuration register 0x44 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR5 CCR5 channel x configuration register 0x58 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR6 CCR6 channel x configuration register 0x6C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR7 CCR7 channel x configuration register 0x80 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CMAR1 CMAR1 channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR2 CMAR2 channel x memory address register 0x28 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR3 CMAR3 channel x memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR4 CMAR4 channel x memory address register 0x50 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR5 CMAR5 channel x memory address register 0x64 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR6 CMAR6 channel x memory address register 0x78 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR7 CMAR7 channel x memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory address 0 32 CNDTR1 CNDTR1 channel x number of data register 0xC 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR2 CNDTR2 channel x number of data register 0x20 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR3 CNDTR3 channel x number of data register 0x34 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR4 CNDTR4 channel x number of data register 0x48 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR5 CNDTR5 channel x number of data register 0x5C 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR6 CNDTR6 channel x number of data register 0x70 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR7 CNDTR7 channel x number of data register 0x84 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CPAR1 CPAR1 channel x peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 channel x peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR3 channel x peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 channel x peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 channel x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 channel x peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 channel x peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CSELR CSELR channel selection register 0xA8 32 read-write n 0x0 0x0 C1S DMA channel 1 selection 0 4 C2S DMA channel 2 selection 4 4 C3S DMA channel 3 selection 8 4 C4S DMA channel 4 selection 12 4 C5S DMA channel 5 selection 16 4 C6S DMA channel 6 selection 20 4 C7S DMA channel 7 selection 24 4 IFCR IFCR interrupt flag clear register 0x4 32 write-only n 0x0 0x0 CGIF1 Channel x global interrupt clear (x = 1 ..7) 0 1 CGIF2 Channel x global interrupt clear (x = 1 ..7) 4 1 CGIF3 Channel x global interrupt clear (x = 1 ..7) 8 1 CGIF4 Channel x global interrupt clear (x = 1 ..7) 12 1 CGIF5 Channel x global interrupt clear (x = 1 ..7) 16 1 CGIF6 Channel x global interrupt clear (x = 1 ..7) 20 1 CGIF7 Channel x global interrupt clear (x = 1 ..7) 24 1 CHTIF1 Channel x half transfer clear (x = 1 ..7) 2 1 CHTIF2 Channel x half transfer clear (x = 1 ..7) 6 1 CHTIF3 Channel x half transfer clear (x = 1 ..7) 10 1 CHTIF4 Channel x half transfer clear (x = 1 ..7) 14 1 CHTIF5 Channel x half transfer clear (x = 1 ..7) 18 1 CHTIF6 Channel x half transfer clear (x = 1 ..7) 22 1 CHTIF7 Channel x half transfer clear (x = 1 ..7) 26 1 CTCIF1 Channel x transfer complete clear (x = 1 ..7) 1 1 CTCIF2 Channel x transfer complete clear (x = 1 ..7) 5 1 CTCIF3 Channel x transfer complete clear (x = 1 ..7) 9 1 CTCIF4 Channel x transfer complete clear (x = 1 ..7) 13 1 CTCIF5 Channel x transfer complete clear (x = 1 ..7) 17 1 CTCIF6 Channel x transfer complete clear (x = 1 ..7) 21 1 CTCIF7 Channel x transfer complete clear (x = 1 ..7) 25 1 CTEIF1 Channel x transfer error clear (x = 1 ..7) 3 1 CTEIF2 Channel x transfer error clear (x = 1 ..7) 7 1 CTEIF3 Channel x transfer error clear (x = 1 ..7) 11 1 CTEIF4 Channel x transfer error clear (x = 1 ..7) 15 1 CTEIF5 Channel x transfer error clear (x = 1 ..7) 19 1 CTEIF6 Channel x transfer error clear (x = 1 ..7) 23 1 CTEIF7 Channel x transfer error clear (x = 1 ..7) 27 1 ISR ISR interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 Channel x global interrupt flag (x = 1 ..7) 0 1 GIF2 Channel x global interrupt flag (x = 1 ..7) 4 1 GIF3 Channel x global interrupt flag (x = 1 ..7) 8 1 GIF4 Channel x global interrupt flag (x = 1 ..7) 12 1 GIF5 Channel x global interrupt flag (x = 1 ..7) 16 1 GIF6 Channel x global interrupt flag (x = 1 ..7) 20 1 GIF7 Channel x global interrupt flag (x = 1 ..7) 24 1 HTIF1 Channel x half transfer flag (x = 1 ..7) 2 1 HTIF2 Channel x half transfer flag (x = 1 ..7) 6 1 HTIF3 Channel x half transfer flag (x = 1 ..7) 10 1 HTIF4 Channel x half transfer flag (x = 1 ..7) 14 1 HTIF5 Channel x half transfer flag (x = 1 ..7) 18 1 HTIF6 Channel x half transfer flag (x = 1 ..7) 22 1 HTIF7 Channel x half transfer flag (x = 1 ..7) 26 1 TCIF1 Channel x transfer complete flag (x = 1 ..7) 1 1 TCIF2 Channel x transfer complete flag (x = 1 ..7) 5 1 TCIF3 Channel x transfer complete flag (x = 1 ..7) 9 1 TCIF4 Channel x transfer complete flag (x = 1 ..7) 13 1 TCIF5 Channel x transfer complete flag (x = 1 ..7) 17 1 TCIF6 Channel x transfer complete flag (x = 1 ..7) 21 1 TCIF7 Channel x transfer complete flag (x = 1 ..7) 25 1 TEIF1 Channel x transfer error flag (x = 1 ..7) 3 1 TEIF2 Channel x transfer error flag (x = 1 ..7) 7 1 TEIF3 Channel x transfer error flag (x = 1 ..7) 11 1 TEIF4 Channel x transfer error flag (x = 1 ..7) 15 1 TEIF5 Channel x transfer error flag (x = 1 ..7) 19 1 TEIF6 Channel x transfer error flag (x = 1 ..7) 23 1 TEIF7 Channel x transfer error flag (x = 1 ..7) 27 1 DMA2 Direct memory access controller DMA 0x0 0x0 0x400 registers n DMA2_CH1 DMA2 Channel 1 global Interrupt 56 DMA2_CH2 DMA2 Channel 2 global Interrupt 57 DMA2_CH3 DMA2 Channel 3 global Interrupt 58 DMA2_CH4 DMA2 Channel 4 global Interrupt 59 DMA2_CH5 DMA2 Channel 5 global Interrupt 60 DMA2_CH6 DMA2 Channel 6 global Interrupt 68 DMA2_CH7 DMA2 Channel 7 global Interrupt 69 CCR1 CCR1 channel x configuration register 0x8 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR2 CCR2 channel x configuration register 0x1C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR3 CCR3 channel x configuration register 0x30 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR4 CCR4 channel x configuration register 0x44 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR5 CCR5 channel x configuration register 0x58 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR6 CCR6 channel x configuration register 0x6C 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CCR7 CCR7 channel x configuration register 0x80 32 read-write n 0x0 0x0 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CMAR1 CMAR1 channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR2 CMAR2 channel x memory address register 0x28 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR3 CMAR3 channel x memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR4 CMAR4 channel x memory address register 0x50 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR5 CMAR5 channel x memory address register 0x64 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR6 CMAR6 channel x memory address register 0x78 32 read-write n 0x0 0x0 MA Memory address 0 32 CMAR7 CMAR7 channel x memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory address 0 32 CNDTR1 CNDTR1 channel x number of data register 0xC 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR2 CNDTR2 channel x number of data register 0x20 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR3 CNDTR3 channel x number of data register 0x34 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR4 CNDTR4 channel x number of data register 0x48 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR5 CNDTR5 channel x number of data register 0x5C 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR6 CNDTR6 channel x number of data register 0x70 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CNDTR7 CNDTR7 channel x number of data register 0x84 32 read-write n 0x0 0x0 NDT Number of data to transfer 0 16 CPAR1 CPAR1 channel x peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 channel x peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR3 channel x peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 channel x peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 channel x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 channel x peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 channel x peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CSELR CSELR channel selection register 0xA8 32 read-write n 0x0 0x0 C1S DMA channel 1 selection 0 4 C2S DMA channel 2 selection 4 4 C3S DMA channel 3 selection 8 4 C4S DMA channel 4 selection 12 4 C5S DMA channel 5 selection 16 4 C6S DMA channel 6 selection 20 4 C7S DMA channel 7 selection 24 4 IFCR IFCR interrupt flag clear register 0x4 32 write-only n 0x0 0x0 CGIF1 Channel x global interrupt clear (x = 1 ..7) 0 1 CGIF2 Channel x global interrupt clear (x = 1 ..7) 4 1 CGIF3 Channel x global interrupt clear (x = 1 ..7) 8 1 CGIF4 Channel x global interrupt clear (x = 1 ..7) 12 1 CGIF5 Channel x global interrupt clear (x = 1 ..7) 16 1 CGIF6 Channel x global interrupt clear (x = 1 ..7) 20 1 CGIF7 Channel x global interrupt clear (x = 1 ..7) 24 1 CHTIF1 Channel x half transfer clear (x = 1 ..7) 2 1 CHTIF2 Channel x half transfer clear (x = 1 ..7) 6 1 CHTIF3 Channel x half transfer clear (x = 1 ..7) 10 1 CHTIF4 Channel x half transfer clear (x = 1 ..7) 14 1 CHTIF5 Channel x half transfer clear (x = 1 ..7) 18 1 CHTIF6 Channel x half transfer clear (x = 1 ..7) 22 1 CHTIF7 Channel x half transfer clear (x = 1 ..7) 26 1 CTCIF1 Channel x transfer complete clear (x = 1 ..7) 1 1 CTCIF2 Channel x transfer complete clear (x = 1 ..7) 5 1 CTCIF3 Channel x transfer complete clear (x = 1 ..7) 9 1 CTCIF4 Channel x transfer complete clear (x = 1 ..7) 13 1 CTCIF5 Channel x transfer complete clear (x = 1 ..7) 17 1 CTCIF6 Channel x transfer complete clear (x = 1 ..7) 21 1 CTCIF7 Channel x transfer complete clear (x = 1 ..7) 25 1 CTEIF1 Channel x transfer error clear (x = 1 ..7) 3 1 CTEIF2 Channel x transfer error clear (x = 1 ..7) 7 1 CTEIF3 Channel x transfer error clear (x = 1 ..7) 11 1 CTEIF4 Channel x transfer error clear (x = 1 ..7) 15 1 CTEIF5 Channel x transfer error clear (x = 1 ..7) 19 1 CTEIF6 Channel x transfer error clear (x = 1 ..7) 23 1 CTEIF7 Channel x transfer error clear (x = 1 ..7) 27 1 ISR ISR interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 Channel x global interrupt flag (x = 1 ..7) 0 1 GIF2 Channel x global interrupt flag (x = 1 ..7) 4 1 GIF3 Channel x global interrupt flag (x = 1 ..7) 8 1 GIF4 Channel x global interrupt flag (x = 1 ..7) 12 1 GIF5 Channel x global interrupt flag (x = 1 ..7) 16 1 GIF6 Channel x global interrupt flag (x = 1 ..7) 20 1 GIF7 Channel x global interrupt flag (x = 1 ..7) 24 1 HTIF1 Channel x half transfer flag (x = 1 ..7) 2 1 HTIF2 Channel x half transfer flag (x = 1 ..7) 6 1 HTIF3 Channel x half transfer flag (x = 1 ..7) 10 1 HTIF4 Channel x half transfer flag (x = 1 ..7) 14 1 HTIF5 Channel x half transfer flag (x = 1 ..7) 18 1 HTIF6 Channel x half transfer flag (x = 1 ..7) 22 1 HTIF7 Channel x half transfer flag (x = 1 ..7) 26 1 TCIF1 Channel x transfer complete flag (x = 1 ..7) 1 1 TCIF2 Channel x transfer complete flag (x = 1 ..7) 5 1 TCIF3 Channel x transfer complete flag (x = 1 ..7) 9 1 TCIF4 Channel x transfer complete flag (x = 1 ..7) 13 1 TCIF5 Channel x transfer complete flag (x = 1 ..7) 17 1 TCIF6 Channel x transfer complete flag (x = 1 ..7) 21 1 TCIF7 Channel x transfer complete flag (x = 1 ..7) 25 1 TEIF1 Channel x transfer error flag (x = 1 ..7) 3 1 TEIF2 Channel x transfer error flag (x = 1 ..7) 7 1 TEIF3 Channel x transfer error flag (x = 1 ..7) 11 1 TEIF4 Channel x transfer error flag (x = 1 ..7) 15 1 TEIF5 Channel x transfer error flag (x = 1 ..7) 19 1 TEIF6 Channel x transfer error flag (x = 1 ..7) 23 1 TEIF7 Channel x transfer error flag (x = 1 ..7) 27 1 DMA2D DMA2D controller DMA2D 0x0 0x0 0xC00 registers n DMA2D DMA2D global interrupt 90 AMTCR AMTCR AHB master timer configuration register 0x4C 32 read-write n 0x0 0x0 DT Dead Time 8 8 EN Enable 0 1 BGCLUT BGCLUT BGCLUT 0x800 32 read-write n 0x0 0x0 APLHA APLHA 24 8 BLUE BLUE 0 8 GREEN GREEN 8 8 RED RED 16 8 BGCMAR BGCMAR background CLUT memory address register 0x30 32 read-write n 0x0 0x0 MA Memory address 0 32 BGCOLR BGCOLR background color register 0x28 32 read-write n 0x0 0x0 BLUE Blue Value 0 8 GREEN Green Value 8 8 RED Red Value 16 8 BGMAR BGMAR background memory address register 0x14 32 read-write n 0x0 0x0 MA Memory address 0 32 BGOR BGOR background offset register 0x18 32 read-write n 0x0 0x0 LO Line offset 0 14 BGPFCCR BGPFCCR background PFC control register 0x24 32 read-write n 0x0 0x0 AI Alpha Inverted 20 1 ALPHA Alpha value 24 8 AM Alpha mode 16 2 CCM CLUT Color mode 4 1 CM Color mode 0 4 CS CLUT size 8 8 RBS Red Blue Swap 21 1 START Start 5 1 CR CR control register 0x0 32 read-write n 0x0 0x0 ABORT Abort 2 1 CAEIE CLUT access error interrupt enable 11 1 CEIE Configuration Error Interrupt Enable 13 1 CTCIE CLUT transfer complete interrupt enable 12 1 MODE DMA2D mode 16 2 START Start 0 1 SUSP Suspend 1 1 TCIE Transfer complete interrupt enable 9 1 TEIE Transfer error interrupt enable 8 1 TWIE Transfer watermark interrupt enable 10 1 FGCLUT FGCLUT FGCLUT 0x400 32 read-write n 0x0 0x0 APLHA APLHA 24 8 BLUE BLUE 0 8 GREEN GREEN 8 8 RED RED 16 8 FGCMAR FGCMAR foreground CLUT memory address register 0x2C 32 read-write n 0x0 0x0 MA Memory Address 0 32 FGCOLR FGCOLR foreground color register 0x20 32 read-write n 0x0 0x0 BLUE Blue Value 0 8 GREEN Green Value 8 8 RED Red Value 16 8 FGMAR FGMAR foreground memory address register 0xC 32 read-write n 0x0 0x0 MA Memory address 0 32 FGOR FGOR foreground offset register 0x10 32 read-write n 0x0 0x0 LO Line offset 0 14 FGPFCCR FGPFCCR foreground PFC control register 0x1C 32 read-write n 0x0 0x0 AI Alpha Inverted 20 1 ALPHA Alpha value 24 8 AM Alpha mode 16 2 CCM CLUT color mode 4 1 CM Color mode 0 4 CS CLUT size 8 8 RBS Red Blue Swap 21 1 START Start 5 1 IFCR IFCR interrupt flag clear register 0x8 32 read-write n 0x0 0x0 CAECIF Clear CLUT access error interrupt flag 3 1 CCEIF Clear configuration error interrupt flag 5 1 CCTCIF Clear CLUT transfer complete interrupt flag 4 1 CTCIF Clear transfer complete interrupt flag 1 1 CTEIF Clear Transfer error interrupt flag 0 1 CTWIF Clear transfer watermark interrupt flag 2 1 ISR ISR Interrupt Status Register 0x4 32 read-only n 0x0 0x0 CAEIF CLUT access error interrupt flag 3 1 CEIF Configuration error interrupt flag 5 1 CTCIF CLUT transfer complete interrupt flag 4 1 TCIF Transfer complete interrupt flag 1 1 TEIF Transfer error interrupt flag 0 1 TWIF Transfer watermark interrupt flag 2 1 LWR LWR line watermark register 0x48 32 read-write n 0x0 0x0 LW Line watermark 0 16 NLR NLR number of line register 0x44 32 read-write n 0x0 0x0 NL Number of lines 0 16 PL Pixel per lines 16 14 OCOLR OCOLR output color register 0x38 32 read-write n 0x0 0x0 APLHA Alpha Channel Value 24 8 BLUE Blue Value 0 8 GREEN Green Value 8 8 RED Red Value 16 8 OMAR OMAR output memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory Address 0 32 OOR OOR output offset register 0x40 32 read-write n 0x0 0x0 LO Line Offset 0 14 OPFCCR OPFCCR output PFC control register 0x34 32 read-write n 0x0 0x0 AI Alpha Inverted 20 1 CM Color mode 0 3 RBS Red Blue Swap 21 1 DMAMUX1 DMA request multiplexer DMAMUX 0x0 0x0 0x400 registers n DMAMUX1_OVR DMAMUX Overrun interrupt 94 C0CR C0CR channel 0 configuration register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C10CR C10CR channel 10 configuration register 0x28 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C11CR C11CR channel 11 configuration register 0x2C 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C12CR C12CR channel 12 configuration register 0x30 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C13CR C13CR channel 13 configuration register 0x34 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C1CR C1CR channel 1 configuration register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C2CR C2CR channel 2 configuration register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C3CR C3CR channel 3 configuration register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C4CR C4CR channel 4 configuration register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C5CR C5CR channel 5 configuration register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C6CR C6CR channel 6 configuration register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C7CR C7CR channel 7 configuration register 0x1C 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C8CR C8CR channel 8 configuration register 0x20 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 C9CR C9CR channel 9 configuration register 0x24 32 read-write n 0x0 0x0 DMAREQ_ID DMA request identification 0 7 EGE Event generation enable 9 1 NBREQ Number of DMA requests minus 1 to forward 19 5 SE Synchronization enable 16 1 SOIE Synchronization overrun interrupt enable 8 1 SPOL Synchronization polarity 17 2 SYNC_ID Synchronization identification 24 5 CFR CFR clear flag register 0x84 32 write-only n 0x0 0x0 CSOF0 Clear synchronization overrun event flag 0 1 CSOF1 Clear synchronization overrun event flag 1 1 CSOF10 Clear synchronization overrun event flag 10 1 CSOF11 Clear synchronization overrun event flag 11 1 CSOF12 Clear synchronization overrun event flag 12 1 CSOF13 Clear synchronization overrun event flag 13 1 CSOF2 Clear synchronization overrun event flag 2 1 CSOF3 Clear synchronization overrun event flag 3 1 CSOF4 Clear synchronization overrun event flag 4 1 CSOF5 Clear synchronization overrun event flag 5 1 CSOF6 Clear synchronization overrun event flag 6 1 CSOF7 Clear synchronization overrun event flag 7 1 CSOF8 Clear synchronization overrun event flag 8 1 CSOF9 Clear synchronization overrun event flag 9 1 CSR CSR channel status register 0x80 32 read-only n 0x0 0x0 SOF0 Synchronization overrun event flag 0 1 SOF1 Synchronization overrun event flag 1 1 SOF10 Synchronization overrun event flag 10 1 SOF11 Synchronization overrun event flag 11 1 SOF12 Synchronization overrun event flag 12 1 SOF13 Synchronization overrun event flag 13 1 SOF2 Synchronization overrun event flag 2 1 SOF3 Synchronization overrun event flag 3 1 SOF4 Synchronization overrun event flag 4 1 SOF5 Synchronization overrun event flag 5 1 SOF6 Synchronization overrun event flag 6 1 SOF7 Synchronization overrun event flag 7 1 SOF8 Synchronization overrun event flag 8 1 SOF9 Synchronization overrun event flag 9 1 RG0CR RG0CR request generator channel 0 configuration register 0x100 32 read-write n 0x0 0x0 GE DMA request generator channel 0 enable 16 1 GNBREQ Number of DMA requests to be generated minus 1 19 5 GPOL DMA request generator trigger polarity 17 2 OIE Trigger overrun interrupt enable 8 1 SIG_ID Signal identification 0 5 RG1CR RG1CR request generator channel 1 configuration register 0x104 32 read-write n 0x0 0x0 GE DMA request generator channel 1 enable 16 1 GNBREQ Number of DMA requests to be generated minus 1 19 5 GPOL DMA request generator trigger polarity 17 2 OIE Trigger overrun interrupt enable 8 1 SIG_ID Signal identification 0 5 RG2CR RG2CR request generator channel 2 configuration register 0x108 32 read-write n 0x0 0x0 GE DMA request generator channel 2 enable 16 1 GNBREQ Number of DMA requests to be generated minus 1 19 5 GPOL DMA request generator trigger polarity 17 2 OIE Trigger overrun interrupt enable 8 1 SIG_ID Signal identification 0 5 RG3CR RG3CR request generator channel 3 configuration register 0x10C 32 read-write n 0x0 0x0 GE DMA request generator channel 3 enable 16 1 GNBREQ Number of DMA requests to be generated minus 1 19 5 GPOL DMA request generator trigger polarity 17 2 OIE Trigger overrun interrupt enable 8 1 SIG_ID Signal identification 0 5 RGCFR RGCFR request generator interrupt clear flag register 0x144 32 write-only n 0x0 0x0 COF0 Clear trigger overrun event flag 0 1 COF1 Clear trigger overrun event flag 1 1 COF2 Clear trigger overrun event flag 2 1 COF3 Clear trigger overrun event flag 3 1 RGSR RGSR request generator interrupt status register 0x140 32 read-only n 0x0 0x0 OF0 Trigger overrun event flag 0 1 OF1 Trigger overrun event flag 1 1 OF2 Trigger overrun event flag 2 1 OF3 Trigger overrun event flag 3 1 DSI DSI Host DSI 0x0 0x0 0x800 registers n DSIHSOT DSI global interrupt 78 CCR DSI_CCR DSI HOST Clock Control Register 0x8 32 read-write n 0x0 0x0 TOCKDIV Timeout Clock Division 8 8 TXECKDIV TX Escape Clock Division 0 8 CLCR DSI_CLCR DSI Host Clock Lane Configuration Register 0x80 32 read-write n 0x0 0x0 ACR Automatic Clock lane Control 1 1 DPCC D-PHY Clock Control 0 1 CLTCR DSI_CLTCR DSI Host Clock Lane Timer Configuration Register 0x84 32 read-write n 0x0 0x0 HS2LP_TIME High-Speed to Low-Power Time 16 10 LP2HS_TIME Low-Power to High-Speed Time 0 10 CMCR DSI_CMCR DSI Host Command mode Configuration Register 0x58 32 read-write n 0x0 0x0 ARE Acknowledge Request Enable 1 1 DLWTX DCS Long Write Transmission 19 1 DSR0TX DCS Short Read Zero parameter Transmission 18 1 DSW0TX DCS Short Write Zero parameter Transmission 16 1 DSW1TX DCS Short Read One parameter Transmission 17 1 GLWTX Generic Long Write Transmission 14 1 GSR0TX Generic Short Read Zero parameters Transmission 11 1 GSR1TX Generic Short Read One parameters Transmission 12 1 GSR2TX Generic Short Read Two parameters Transmission 13 1 GSW0TX Generic Short Write Zero parameters Transmission 8 1 GSW1TX Generic Short Write One parameters Transmission 9 1 GSW2TX Generic Short Write Two parameters Transmission 10 1 MRDPS Maximum Read Packet Size 24 1 TEARE Tearing Effect Acknowledge Request Enable 0 1 CR DSI_CR DSI Host Control Register 0x4 32 read-write n 0x0 0x0 EN Enable 0 1 DLTRC DSI_DLTRC DSI Host Data Lane Timer Configuration Register 0x88 32 read-write n 0x0 0x0 HS2LP_TIME High-Speed To Low-Power Time 24 8 LP2HS_TIME Low-Power To High-Speed Time 16 8 MRD_TIME Maximum Read Time 0 15 FIR0 DSI_FIR0 DSI Host Force Interrupt Register 0 0xB0 32 write-only n 0x0 0x0 FAE0 Force Acknowledge Error 0 0 1 FAE1 Force Acknowledge Error 1 1 1 FAE10 Force Acknowledge Error 10 10 1 FAE11 Force Acknowledge Error 11 11 1 FAE12 Force Acknowledge Error 12 12 1 FAE13 Force Acknowledge Error 13 13 1 FAE14 Force Acknowledge Error 14 14 1 FAE15 Force Acknowledge Error 15 15 1 FAE2 Force Acknowledge Error 2 2 1 FAE3 Force Acknowledge Error 3 3 1 FAE4 Force Acknowledge Error 4 4 1 FAE5 Force Acknowledge Error 5 5 1 FAE6 Force Acknowledge Error 6 6 1 FAE7 Force Acknowledge Error 7 7 1 FAE8 Force Acknowledge Error 8 8 1 FAE9 Force Acknowledge Error 9 9 1 FPE0 Force PHY Error 0 16 1 FPE1 Force PHY Error 1 17 1 FPE2 Force PHY Error 2 18 1 FPE3 Force PHY Error 3 19 1 FPE4 Force PHY Error 4 20 1 FIR1 DSI_FIR1 DSI Host Force Interrupt Register 1 0xB4 32 write-only n 0x0 0x0 FCRCE Force CRC Error 4 1 FECCME Force ECC Multi-bit Error 3 1 FECCSE Force ECC Single-bit Error 2 1 FEOTPE Force EoTp Error 6 1 FGCWRE Force Generic Command Write Error 8 1 FGPRDE Force Generic Payload Read Error 11 1 FGPRXE Force Generic Payload Receive Error 12 1 FGPTXE Force Generic Payload Transmit Error 10 1 FGPWRE Force Generic Payload Write Error 9 1 FLPWRE Force LTDC Payload Write Error 7 1 FPSE Force Packet Size Error 5 1 FTOHSTX Force Timeout High-Speed Transmission 0 1 FTOLPRX Force Timeout Low-Power Reception 1 1 GHCR DSI_GHCR DSI Host Generic Header Configuration Register 0x5C 32 read-write n 0x0 0x0 DT Type 0 6 VCID Channel 6 2 WCLSB WordCount LSB 8 8 WCMSB WordCount MSB 16 8 GPDR DSI_GPDR DSI Host Generic Payload Data Register 0x60 32 read-write n 0x0 0x0 DATA1 Payload Byte 1 0 8 DATA2 Payload Byte 2 8 8 DATA3 Payload Byte 3 16 8 DATA4 Payload Byte 4 24 8 GPSR DSI_GPSR DSI Host Generic Packet Status Register 0x64 32 read-only n 0x0 0x0 CMDFE Command FIFO Empty 0 1 CMDFF Command FIFO Full 1 1 PRDFE Payload Read FIFO Empty 4 1 PRDFF Payload Read FIFO Full 5 1 PWRFE Payload Write FIFO Empty 2 1 PWRFF Payload Write FIFO Full 3 1 RCB Read Command Busy 6 1 GVCIDR DSI_GVCIDR DSI Host Generic VCID Register 0x20 32 read-write n 0x0 0x0 VCID Virtual Channel ID 0 2 IER0 DSI_IER0 DSI Host Interrupt Enable Register 0 0xA8 32 read-write n 0x0 0x0 AE0IE Acknowledge Error 0 Interrupt Enable 0 1 AE10IE Acknowledge Error 10 Interrupt Enable 10 1 AE11IE Acknowledge Error 11 Interrupt Enable 11 1 AE12IE Acknowledge Error 12 Interrupt Enable 12 1 AE13IE Acknowledge Error 13 Interrupt Enable 13 1 AE14IE Acknowledge Error 14 Interrupt Enable 14 1 AE15IE Acknowledge Error 15 Interrupt Enable 15 1 AE1IE Acknowledge Error 1 Interrupt Enable 1 1 AE2IE Acknowledge Error 2 Interrupt Enable 2 1 AE3IE Acknowledge Error 3 Interrupt Enable 3 1 AE4IE Acknowledge Error 4 Interrupt Enable 4 1 AE5IE Acknowledge Error 5 Interrupt Enable 5 1 AE6IE Acknowledge Error 6 Interrupt Enable 6 1 AE7IE Acknowledge Error 7 Interrupt Enable 7 1 AE8IE Acknowledge Error 8 Interrupt Enable 8 1 AE9IE Acknowledge Error 9 Interrupt Enable 9 1 PE0IE PHY Error 0 Interrupt Enable 16 1 PE1IE PHY Error 1 Interrupt Enable 17 1 PE2IE PHY Error 2 Interrupt Enable 18 1 PE3IE PHY Error 3 Interrupt Enable 19 1 PE4IE PHY Error 4 Interrupt Enable 20 1 IER1 DSI_IER1 DSI Host Interrupt Enable Register 1 0xAC 32 read-write n 0x0 0x0 CRCEIE CRC Error Interrupt Enable 4 1 ECCMEIE ECC Multi-bit Error Interrupt Enable 3 1 ECCSEIE ECC Single-bit Error Interrupt Enable 2 1 EOTPEIE EoTp Error Interrupt Enable 6 1 GCWREIE Generic Command Write Error Interrupt Enable 8 1 GPRDEIE Generic Payload Read Error Interrupt Enable 11 1 GPRXEIE Generic Payload Receive Error Interrupt Enable 12 1 GPTXEIE Generic Payload Transmit Error Interrupt Enable 10 1 GPWREIE Generic Payload Write Error Interrupt Enable 9 1 LPWREIE LTDC Payload Write Error Interrupt Enable 7 1 PSEIE Packet Size Error Interrupt Enable 5 1 TOHSTXIE Timeout High-Speed Transmission Interrupt Enable 0 1 TOLPRXIE Timeout Low-Power Reception Interrupt Enable 1 1 ISR0 DSI_ISR0 DSI Host Interrupt and Status Register 0 0xA0 32 read-only n 0x0 0x0 AE0 Acknowledge Error 0 0 1 AE1 Acknowledge Error 1 1 1 AE10 Acknowledge Error 10 10 1 AE11 Acknowledge Error 11 11 1 AE12 Acknowledge Error 12 12 1 AE13 Acknowledge Error 13 13 1 AE14 Acknowledge Error 14 14 1 AE15 Acknowledge Error 15 15 1 AE2 Acknowledge Error 2 2 1 AE3 Acknowledge Error 3 3 1 AE4 Acknowledge Error 4 4 1 AE5 Acknowledge Error 5 5 1 AE6 Acknowledge Error 6 6 1 AE7 Acknowledge Error 7 7 1 AE8 Acknowledge Error 8 8 1 AE9 Acknowledge Error 9 9 1 PE0 PHY Error 0 16 1 PE1 PHY Error 1 17 1 PE2 PHY Error 2 18 1 PE3 PHY Error 3 19 1 PE4 PHY Error 4 20 1 ISR1 DSI_ISR1 DSI Host Interrupt and Status Register 1 0xA4 32 read-only n 0x0 0x0 CRCE CRC Error 4 1 ECCME ECC Multi-bit Error 3 1 ECCSE ECC Single-bit Error 2 1 EOTPE EoTp Error 6 1 GCWRE Generic Command Write Error 8 1 GPRDE Generic Payload Read Error 11 1 GPRXE Generic Payload Receive Error 12 1 GPTXE Generic Payload Transmit Error 10 1 GPWRE Generic Payload Write Error 9 1 LPWRE LTDC Payload Write Error 7 1 PSE Packet Size Error 5 1 TOHSTX Timeout High-Speed Transmission 0 1 TOLPRX Timeout Low-Power Reception 1 1 LCCCR DSI_LCCCR DSI Host LTDC Current Color Coding Register 0xC0 32 read-only n 0x0 0x0 COLC Color Coding 0 4 LPE Loosely Packed Enable 8 1 LCCR DSI_LCCR DSI Host LTDC Command Configuration Register 0x54 32 read-write n 0x0 0x0 CMDSIZE Command Size 0 16 LCOLCR DSI_LCOLCR DSI Host LTDC Color Coding Register 0x10 32 read-write n 0x0 0x0 COLC Color Coding 0 4 LPE Loosely Packet Enable 8 1 LCVCIDR DSI_LCVCIDR DSI Host LTDC Current VCID Register 0xBC 32 read-only n 0x0 0x0 VCID Virtual Channel ID 0 2 LPCR DSI_LPCR DSI Host LTDC Polarity Configuration Register 0x14 32 read-write n 0x0 0x0 DEP Data Enable Polarity 0 1 HSP HSYNC Polarity 2 1 VSP VSYNC Polarity 1 1 LPMCCR DSI_LPMCCR DSI Host Low-Power mode Current Configuration Register 0xC4 32 read-only n 0x0 0x0 LPSIZE Largest Packet Size 16 8 VLPSIZE VACT Largest Packet Size 0 8 LPMCR DSI_LPMCR DSI Host Low-Power mode Configuration Register 0x18 32 read-write n 0x0 0x0 LPSIZE Largest Packet Size 16 8 VLPSIZE VACT Largest Packet Size 0 8 LVCIDR DSI_LVCIDR DSI Host LTDC VCID Register 0xC 32 read-write n 0x0 0x0 VCID Virtual Channel ID 0 2 MCR DSI_MCR DSI Host mode Configuration Register 0x24 32 read-write n 0x0 0x0 CMDM Command mode 0 1 PCONFR DSI_PCONFR DSI Host PHY Configuration Register 0x90 32 read-write n 0x0 0x0 NL Number of Lanes 0 2 SW_TIME Stop Wait Time 8 8 PCR DSI_PCR DSI Host Protocol Configuration Register 0x1C 32 read-write n 0x0 0x0 BTAE Bus Turn Around Enable 2 1 CRCRXE CRC Reception Enable 4 1 ECCRXE ECC Reception Enable 3 1 ETRXE EoTp Reception Enable 1 1 ETTXE EoTp Transmission Enable 0 1 PCTLR DSI_PCTLR DSI Host PHY Control Register 0x8C 32 read-write n 0x0 0x0 CKE Clock Enable 2 1 DEN Digital Enable 1 1 PSR DSI_PSR DSI Host PHY Status Register 0x9C 32 read-only n 0x0 0x0 PD PHY Direction 1 1 PSS0 PHY Stop State lane 0 4 1 PSS1 PHY Stop State lane 1 7 1 PSSC PHY Stop State Clock lane 2 1 RUE0 RX ULPS Escape lane 0 6 1 UAN0 ULPS Active Not lane 1 5 1 UAN1 ULPS Active Not lane 1 8 1 UANC ULPS Active Not Clock lane 3 1 PTTCR DSI_PTTCR DSI Host PHY TX Triggers Configuration Register 0x98 32 read-write n 0x0 0x0 TX_TRIG Transmission Trigger 0 4 PUCR DSI_PUCR DSI Host PHY ULPS Control Register 0x94 32 read-write n 0x0 0x0 UECL ULPS Exit on Clock Lane 1 1 UEDL ULPS Exit on Data Lane 3 1 URCL ULPS Request on Clock Lane 0 1 URDL ULPS Request on Data Lane 2 1 TCCR0 DSI_TCCR0 DSI Host Timeout Counter Configuration Register 0 0x68 32 read-write n 0x0 0x0 HSTX_TOCNT High-Speed Transmission Timeout Counter 16 16 LPRX_TOCNT Low-power Reception Timeout Counter 0 16 TCCR1 DSI_TCCR1 DSI Host Timeout Counter Configuration Register 1 0x6C 32 read-write n 0x0 0x0 HSRD_TOCNT High-Speed Read Timeout Counter 0 16 TCCR2 DSI_TCCR2 DSI Host Timeout Counter Configuration Register 2 0x70 32 read-write n 0x0 0x0 LPRD_TOCNT Low-Power Read Timeout Counter 0 16 TCCR3 DSI_TCCR3 DSI Host Timeout Counter Configuration Register 3 0x74 32 read-write n 0x0 0x0 HSWR_TOCNT High-Speed Write Timeout Counter 0 16 PM Presp mode 24 1 TCCR4 DSI_TCCR4 DSI Host Timeout Counter Configuration Register 4 0x78 32 read-write n 0x0 0x0 LSWR_TOCNT Low-Power Write Timeout Counter 0 16 TCCR5 DSI_TCCR5 DSI Host Timeout Counter Configuration Register 5 0x7C 32 read-write n 0x0 0x0 BTA_TOCNT Bus-Turn-Around Timeout Counter 0 16 VCCCR DSI_VCCCR DSI Host Video Chunks Current Configuration Register 0xD0 32 read-only n 0x0 0x0 NUMC Number of Chunks 0 13 VCCR DSI_VCCR DSI Host Video Chunks Configuration Register 0x30 32 read-write n 0x0 0x0 NUMC Number of Chunks 0 13 VHBPCCR DSI_VHBPCCR DSI Host Video HBP Current Configuration Register 0xDC 32 read-only n 0x0 0x0 HBP Horizontal Back-Porch duration 0 12 VHBPCR DSI_VHBPCR DSI Host Video HBP Configuration Register 0x3C 32 read-write n 0x0 0x0 HBP Horizontal Back-Porch duration 0 12 VHSACCR DSI_VHSACCR DSI Host Video HSA Current Configuration Register 0xD8 32 read-only n 0x0 0x0 HSA Horizontal Synchronism Active duration 0 12 VHSACR DSI_VHSACR DSI Host Video HSA Configuration Register 0x38 32 read-write n 0x0 0x0 HSA Horizontal Synchronism Active duration 0 12 VLCCR DSI_VLCCR DSI Host Video Line Current Configuration Register 0xE0 32 read-only n 0x0 0x0 HLINE Horizontal Line duration 0 15 VLCR DSI_VLCR DSI Host Video Line Configuration Register 0x40 32 read-write n 0x0 0x0 HLINE Horizontal Line duration 0 15 VMCCR DSI_VMCCR DSI Host Video mode Current Configuration Register 0xC8 32 read-only n 0x0 0x0 FBTAAE Frame BTA Acknowledge Enable 8 1 LPCE Low-Power Command Enable 9 1 LPHBPE Low-power Horizontal Back-Porch Enable 6 1 LPHFE Low-Power Horizontal Front-Porch Enable 7 1 LPVAE Low-Power Vertical Active Enable 5 1 LPVBPE Low-power Vertical Back-Porch Enable 3 1 LPVFPE Low-power Vertical Front-Porch Enable 4 1 LPVSAE Low-Power Vertical Sync time Enable 2 1 VMT Video mode Type 0 2 VMCR DSI_VMCR DSI Host Video mode Configuration Register 0x28 32 read-write n 0x0 0x0 FBTAAE Frame Bus-Turn-Around Acknowledge Enable 14 1 LPCE Low-Power Command Enable 15 1 LPHBPE Low-Power Horizontal Back-Porch Enable 12 1 LPHFPE Low-Power Horizontal Front-Porch Enable 13 1 LPVAE Low-Power Vertical Active Enable 11 1 LPVBPE Low-power Vertical Back-Porch Enable 9 1 LPVFPE Low-power Vertical Front-porch Enable 10 1 LPVSAE Low-Power Vertical Sync Active Enable 8 1 PGE Pattern Generator Enable 16 1 PGM Pattern Generator mode 20 1 PGO Pattern Generator Orientation 24 1 VMT Video mode Type 0 2 VNPCCR DSI_VNPCCR DSI Host Video Null Packet Current Configuration Register 0xD4 32 read-only n 0x0 0x0 NPSIZE Null Packet Size 0 13 VNPCR DSI_VNPCR DSI Host Video Null Packet Configuration Register 0x34 32 read-write n 0x0 0x0 NPSIZE Null Packet Size 0 13 VPCCR DSI_VPCCR DSI Host Video Packet Current Configuration Register 0xCC 32 read-only n 0x0 0x0 VPSIZE Video Packet Size 0 14 VPCR DSI_VPCR DSI Host Video Packet Configuration Register 0x2C 32 read-write n 0x0 0x0 VPSIZE Video Packet Size 0 14 VR DSI_VR DSI Host Version Register 0x0 32 read-only n 0x0 0x0 VERSION Version of the DSI Host 0 32 VSCR DSI_VSCR DSI Host Video Shadow Control Register 0xB8 32 read-write n 0x0 0x0 EN Enable 0 1 UR Update Register 8 1 VVACCR DSI_VVACCR DSI Host Video VA Current Configuration Register 0xF0 32 read-only n 0x0 0x0 VA Vertical Active duration 0 14 VVACR DSI_VVACR DSI Host Video VA Configuration Register 0x50 32 read-write n 0x0 0x0 VA Vertical Active duration 0 14 VVBPCCR DSI_VVBPCCR DSI Host Video VBP Current Configuration Register 0xE8 32 read-only n 0x0 0x0 VBP Vertical Back-Porch duration 0 10 VVBPCR DSI_VVBPCR DSI Host Video VBP Configuration Register 0x48 32 read-write n 0x0 0x0 VBP Vertical Back-Porch duration 0 10 VVFPCCR DSI_VVFPCCR DSI Host Video VFP Current Configuration Register 0xEC 32 read-only n 0x0 0x0 VFP Vertical Front-Porch duration 0 10 VVFPCR DSI_VVFPCR DSI Host Video VFP Configuration Register 0x4C 32 read-write n 0x0 0x0 VFP Vertical Front-Porch duration 0 10 VVSACCR DSI_VVSACCR DSI Host Video VSA Current Configuration Register 0xE4 32 read-only n 0x0 0x0 VSA Vertical Synchronism Active duration 0 10 VVSACR DSI_VVSACR DSI Host Video VSA Configuration Register 0x44 32 read-write n 0x0 0x0 VSA Vertical Synchronism Active duration 0 10 WCFGR DSI_WCFGR DSI Wrapper Configuration Register 0x400 32 read-write n 0x0 0x0 AR Automatic Refresh 6 1 COLMUX Color Multiplexing 1 3 DSIM DSI Mode 0 1 TEPOL TE Polarity 5 1 TESRC TE Source 4 1 VSPOL VSync Polarity 7 1 WCR DSI_WCR DSI Wrapper Control Register 0x404 32 read-write n 0x0 0x0 COLM Color Mode 0 1 DSIEN DSI Enable 3 1 LTDCEN LTDC Enable 2 1 SHTDN Shutdown 1 1 WIER DSI_WIER DSI Wrapper Interrupt Enable Register 0x408 32 read-write n 0x0 0x0 ERIE End of Refresh Interrupt Enable 1 1 PLLLIE PLL Lock Interrupt Enable 9 1 PLLUIE PLL Unlock Interrupt Enable 10 1 RRIE Regulator Ready Interrupt Enable 13 1 TEIE Tearing Effect Interrupt Enable 0 1 WIFCR DSI_WIFCR DSI Wrapper Interrupt Flag Clear Register 0x410 32 read-write n 0x0 0x0 CERIF Clear End of Refresh Interrupt Flag 1 1 CPLLLIF Clear PLL Lock Interrupt Flag 9 1 CPLLUIF Clear PLL Unlock Interrupt Flag 10 1 CRRIF Clear Regulator Ready Interrupt Flag 13 1 CTEIF Clear Tearing Effect Interrupt Flag 0 1 WISR DSI_WISR DSI Wrapper Interrupt and Status Register 0x40C 32 read-only n 0x0 0x0 BUSY Busy Flag 2 1 ERIF End of Refresh Interrupt Flag 1 1 PLLLIF PLL Lock Interrupt Flag 9 1 PLLLS PLL Lock Status 8 1 PLLUIF PLL Unlock Interrupt Flag 10 1 RRIF Regulator Ready Interrupt Flag 13 1 RRS Regulator Ready Status 12 1 TEIF Tearing Effect Interrupt Flag 0 1 WPCR1 DSI_WPCR1 DSI Wrapper PHY Configuration Register 1 0x418 32 read-write n 0x0 0x0 CDOFFDL Contention Detection OFF on Data Lanes 14 1 FTXSMCL Force in TX Stop Mode the Clock Lane 12 1 FTXSMDL Force in TX Stop Mode the Data Lanes 13 1 HSICL Invert Hight-Speed data signal on Clock Lane 9 1 HSIDL0 Invert the Hight-Speed data signal on Data Lane 0 10 1 HSIDL1 Invert the High-Speed data signal on Data Lane 1 11 1 PDEN Pull-Down Enable 18 1 SWCL Swap Clock Lane pins 6 1 SWDL0 Swap Data Lane 0 pins 7 1 SWDL1 Swap Data Lane 1 pins 8 1 TCLKPOSTEN custom time for tCLK-POST Enable 27 1 TCLKPREPEN custom time for tCLK-PREPARE Enable 19 1 TCLKZEROEN custom time for tCLK-ZERO Enable 20 1 TDDL Turn Disable Data Lanes 16 1 THSEXITEN custom time for tHS-EXIT Enable 25 1 THSPREPEN custom time for tHS-PREPARE Enable 21 1 THSTRAILEN custom time for tHS-TRAIL Enable 22 1 THSZEROEN custom time for tHS-ZERO Enable 23 1 TLPXCEN custom time for tLPX for Clock lane Enable 26 1 TLPXDEN custom time for tLPX for Data lanes Enable 24 1 UIX4 Unit Interval multiplied by 4 0 6 WPCR2 DSI_WPCR2 DSI Wrapper PHY Configuration Register 2 0x41C 32 read-write n 0x0 0x0 FLPRXLPM Forces LP Receiver in Low-Power Mode 22 1 HSTXDCL High-Speed Transmission Delay on Clock Lane 0 2 HSTXDLL High-Speed Transmission Delay on Data Lanes 2 2 HSTXSRCCL High-Speed Transmission Slew Rate Control on Clock Lane 16 2 HSTXSRCDL High-Speed Transmission Slew Rate Control on Data Lanes 18 2 LPRXFT Low-Power RX low-pass Filtering Tuning 25 2 LPSRCL Low-Power transmission Slew Rate Compensation on Clock Lane 6 2 LPSRDL Low-Power transmission Slew Rate Compensation on Data Lanes 8 2 SDCC SDD Control 12 1 WPCR3 DSI_WPCR3 DSI Wrapper PHY Configuration Register 3 0x420 32 read-write n 0x0 0x0 TCLKPREP tCLK-PREPARE 0 8 TCLKZEO tCLK-ZERO 8 8 THSPREP tHS-PREPARE 16 8 THSTRAIL tHSTRAIL 24 8 WPCR4 DSI_WPCR4 DSI_WPCR4 0x424 32 read-write n 0x0 0x0 THSEXIT tHSEXIT 16 8 THSZERO tHS-ZERO 0 8 TLPXC tLPXC for Clock lane 24 8 TLPXD tLPX for Data lanes 8 8 WPCR5 DSI_WPCR5 DSI Wrapper PHY Configuration Register 5 0x428 32 read-write n 0x0 0x0 THSZERO tCLK-POST 0 8 WRPCR DSI_WRPCR DSI Wrapper Regulator and PLL Control Register 0x430 32 read-write n 0x0 0x0 IDF PLL Input Division Factor 11 4 NDIV PLL Loop Division Factor 2 7 ODF PLL Output Division Factor 16 2 PLLEN PLL Enable 0 1 REGEN Regulator Enable 24 1 EXTI External interrupt/event controller EXTI 0x0 0x0 0x400 registers n PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3 interrupt 9 EXTI4 EXTI Line 4 interrupt 10 EXTI9_5 EXTI Line5 to Line9 interrupts 23 EXTI15_10 EXTI Lines 10 to 15 interrupts 40 EMR1 EMR1 Event mask register 0x4 32 read-write n 0x0 0x0 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR2 Event Mask on line 2 2 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 MR23 Event Mask on line 23 23 1 MR24 Event Mask on line 24 24 1 MR25 Event Mask on line 25 25 1 MR26 Event Mask on line 26 26 1 MR27 Event Mask on line 27 27 1 MR28 Event Mask on line 28 28 1 MR29 Event Mask on line 29 29 1 MR3 Event Mask on line 3 3 1 MR30 Event Mask on line 30 30 1 MR31 Event Mask on line 31 31 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 EMR2 EMR2 Event mask register 0x24 32 read-write n 0x0 0x0 MR32 Event mask on external/internal line 32 0 1 MR33 Event mask on external/internal line 33 1 1 MR34 Event mask on external/internal line 34 2 1 MR35 Event mask on external/internal line 35 3 1 MR36 Event mask on external/internal line 36 4 1 MR37 Event mask on external/internal line 37 5 1 MR38 Event mask on external/internal line 38 6 1 MR39 Event mask on external/internal line 39 7 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 32 read-write n 0x0 0x0 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR2 Falling trigger event configuration of line 2 2 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 32 read-write n 0x0 0x0 FT35 Falling trigger event configuration bit of line 35 3 1 FT36 Falling trigger event configuration bit of line 36 4 1 FT37 Falling trigger event configuration bit of line 37 5 1 FT38 Falling trigger event configuration bit of line 38 6 1 IMR1 IMR1 Interrupt mask register 0x0 32 read-write n 0x0 0x0 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR2 Interrupt Mask on line 2 2 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 MR23 Interrupt Mask on line 23 23 1 MR24 Interrupt Mask on line 24 24 1 MR25 Interrupt Mask on line 25 25 1 MR26 Interrupt Mask on line 26 26 1 MR27 Interrupt Mask on line 27 27 1 MR28 Interrupt Mask on line 28 28 1 MR29 Interrupt Mask on line 29 29 1 MR3 Interrupt Mask on line 3 3 1 MR30 Interrupt Mask on line 30 30 1 MR31 Interrupt Mask on line 31 31 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 IMR2 IMR2 Interrupt mask register 0x20 32 read-write n 0x0 0x0 MR32 Interrupt Mask on external/internal line 32 0 1 MR33 Interrupt Mask on external/internal line 33 1 1 MR34 Interrupt Mask on external/internal line 34 2 1 MR35 Interrupt Mask on external/internal line 35 3 1 MR36 Interrupt Mask on external/internal line 36 4 1 MR37 Interrupt Mask on external/internal line 37 5 1 MR38 Interrupt Mask on external/internal line 38 6 1 MR39 Interrupt Mask on external/internal line 39 7 1 PR1 PR1 Pending register 0x14 32 read-write n 0x0 0x0 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR18 Pending bit 18 18 1 PR19 Pending bit 19 19 1 PR2 Pending bit 2 2 1 PR20 Pending bit 20 20 1 PR21 Pending bit 21 21 1 PR22 Pending bit 22 22 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR2 PR2 Pending register 0x34 32 read-write n 0x0 0x0 PIF35 Pending interrupt flag on line 35 3 1 PIF36 Pending interrupt flag on line 36 4 1 PIF37 Pending interrupt flag on line 37 5 1 PIF38 Pending interrupt flag on line 38 6 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 32 read-write n 0x0 0x0 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR2 Rising trigger event configuration of line 2 2 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 32 read-write n 0x0 0x0 RT35 Rising trigger event configuration bit of line 35 3 1 RT36 Rising trigger event configuration bit of line 36 4 1 RT37 Rising trigger event configuration bit of line 37 5 1 RT38 Rising trigger event configuration bit of line 38 6 1 SWIER1 SWIER1 Software interrupt event register 0x10 32 read-write n 0x0 0x0 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER2 Software Interrupt on line 2 2 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER2 SWIER2 Software interrupt event register 0x30 32 read-write n 0x0 0x0 SWI35 Software interrupt on line 35 3 1 SWI36 Software interrupt on line 36 4 1 SWI37 Software interrupt on line 37 5 1 SWI38 Software interrupt on line 38 6 1 FIREWALL Firewall Firewall 0x0 0x0 0x400 registers n CR CR Configuration register 0x20 32 read-write n 0x0 0x0 FPA Firewall pre alarm 0 1 VDE Volatile data execution 2 1 VDS Volatile data shared 1 1 CSL CSL Code segment length 0x4 32 read-write n 0x0 0x0 LENG code segment length 8 14 CSSA CSSA Code segment start address 0x0 32 read-write n 0x0 0x0 ADD code segment start address 8 16 NVDSL NVDSL Non-volatile data segment length 0xC 32 read-write n 0x0 0x0 LENG Non-volatile data segment length 8 14 NVDSSA NVDSSA Non-volatile data segment start address 0x8 32 read-write n 0x0 0x0 ADD Non-volatile data segment start address 8 16 VDSL VDSL Volatile data segment length 0x14 32 read-write n 0x0 0x0 LENG Non-volatile data segment length 6 10 VDSSA VDSSA Volatile data segment start address 0x10 32 read-write n 0x0 0x0 ADD Volatile data segment start address 6 10 FLASH Flash Flash 0x0 0x0 0x400 registers n FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 32 read-write n 0x0 0x0 DCEN Data cache enable 10 1 DCRST Data cache reset 12 1 ICEN Instruction cache enable 9 1 ICRST Instruction cache reset 11 1 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 CR CR Flash control register 0x14 32 read-write n 0x0 0x0 BKER Bank erase 11 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 FSTPG Fast programming 18 1 LOCK FLASH_CR Lock 31 1 MER1 Bank 1 Mass erase 2 1 MER2 Bank 2 Mass erase 15 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 OPTSTRT Options modification start 17 1 PER Page erase 1 1 PG Programming 0 1 PNB Page number 3 8 RDERRIE PCROP read error interrupt enable 26 1 START Start 16 1 ECCR ECCR Flash ECC register 0x18 32 read-write n 0x0 0x0 ADDR_ECC ECC fail address 0 19 read-only BK_ECC ECC fail bank 19 1 read-only ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write ECCIE ECC correction interrupt enable 24 1 read-write SYSF_ECC System Flash ECC fail 20 1 read-only KEYR KEYR Flash key register 0x8 32 write-only n 0x0 0x0 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 32 write-only n 0x0 0x0 OPTKEYR Option byte key 0 32 OPTR OPTR Flash option register 0x20 32 read-write n 0x0 0x0 BFB2 Dual-bank boot 20 1 BOR_LEV BOR reset Level 8 3 DUALBANK Dual-Bank on 512 KB or 256 KB Flash memory devices 21 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 nBOOT1 Boot configuration 23 1 nRST_STDBY nRST_STDBY 13 1 nRST_STOP nRST_STOP 12 1 RDP Read protection level 0 8 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 WWDG_SW Window watchdog selection 19 1 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 32 read-write n 0x0 0x0 PCROP1_END Bank 1 PCROP area end offset 0 16 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 32 read-write n 0x0 0x0 PCROP1_STRT Bank 1 PCROP area start offset 0 16 PCROP2ER PCROP2ER Flash Bank 2 PCROP End address register 0x48 32 read-write n 0x0 0x0 PCROP2_END Bank 2 PCROP area end offset 0 16 PCROP2SR PCROP2SR Flash Bank 2 PCROP Start address register 0x44 32 read-write n 0x0 0x0 PCROP2_STRT Bank 2 PCROP area start offset 0 16 PDKEYR PDKEYR Power down key register 0x4 32 write-only n 0x0 0x0 PDKEYR RUN_PD in FLASH_ACR key 0 32 SR SR Status register 0x10 32 read-write n 0x0 0x0 BSY Busy 16 1 read-only EOP End of operation 0 1 read-write FASTERR Fast programming error 9 1 read-write MISERR Fast programming data miss error 8 1 read-write OPERR Operation error 1 1 read-write OPTVERR Option validity error 15 1 read-write PGAERR Programming alignment error 5 1 read-write PGSERR Programming sequence error 7 1 read-write PROGERR Programming error 3 1 read-write RDERR PCROP read error 14 1 read-write SIZERR Size error 6 1 read-write WRPERR Write protected error 4 1 read-write WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 32 read-write n 0x0 0x0 WRP1A_END Bank 1 WRP first area A end offset 16 8 WRP1A_STRT Bank 1 WRP first area start offset 0 8 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 32 read-write n 0x0 0x0 WRP1B_END Bank 1 WRP second area B end offset 16 8 WRP1B_STRT Bank 1 WRP second area B start offset 0 8 WRP2AR WRP2AR Flash Bank 2 WRP area A address register 0x4C 32 read-write n 0x0 0x0 WRP2A_END Bank 2 WRP first area A end offset 16 8 WRP2A_STRT Bank 2 WRP first area A start offset 0 8 WRP2BR WRP2BR Flash Bank 2 WRP area B address register 0x50 32 read-write n 0x0 0x0 WRP2B_END Bank 2 WRP second area B end offset 16 8 WRP2B_STRT Bank 2 WRP second area B start offset 0 8 FMC Flexible memory controller FMC 0x0 0x0 0x400 registers n FMC FMC global Interrupt 48 FPU Floating point interrupt 81 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WFDIS Write FIFO Disable 21 1 WREN WREN 12 1 BCR2 BCR2 SRAM/NOR-Flash chip-select control register 2 0x8 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WRAPMOD WRAPMOD 10 1 WREN WREN 12 1 BCR3 BCR3 SRAM/NOR-Flash chip-select control register 3 0x10 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WRAPMOD WRAPMOD 10 1 WREN WREN 12 1 BCR4 BCR4 SRAM/NOR-Flash chip-select control register 4 0x18 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WRAPMOD WRAPMOD 10 1 WREN WREN 12 1 BTR1 BTR1 SRAM/NOR-Flash chip-select timing register 1 0x4 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR2 BTR2 SRAM/NOR-Flash chip-select timing register 2 0xC 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR3 BTR3 SRAM/NOR-Flash chip-select timing register 3 0x14 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR4 BTR4 SRAM/NOR-Flash chip-select timing register 4 0x1C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BWTR1 BWTR1 SRAM/NOR-Flash write timing registers 1 0x104 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BWTR2 BWTR2 SRAM/NOR-Flash write timing registers 2 0x10C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BWTR3 BWTR3 SRAM/NOR-Flash write timing registers 3 0x114 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BWTR4 BWTR4 SRAM/NOR-Flash write timing registers 4 0x11C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 DATLAT DATLAT 24 4 ECCR ECCR ECC result register 3 0x94 32 read-only n 0x0 0x0 ECCx ECCx 0 32 PATT PATT Attribute memory space timing register 3 0x8C 32 read-write n 0x0 0x0 ATTHIZx ATTHIZx 24 8 ATTHOLDx ATTHOLDx 16 8 ATTSETx ATTSETx 0 8 ATTWAITx ATTWAITx 8 8 PCR PCR PC Card/NAND Flash control register 3 0x80 32 read-write n 0x0 0x0 ECCEN ECCEN 6 1 ECCPS ECCPS 17 3 PBKEN PBKEN 2 1 PTYP PTYP 3 1 PWAITEN PWAITEN 1 1 PWID PWID 4 2 TAR TAR 13 4 TCLR TCLR 9 4 PMEM PMEM Common memory space timing register 3 0x88 32 read-write n 0x0 0x0 MEMHIZx MEMHIZx 24 8 MEMHOLDx MEMHOLDx 16 8 MEMSETx MEMSETx 0 8 MEMWAITx MEMWAITx 8 8 SR SR FIFO status and interrupt register 3 0x84 32 read-write n 0x0 0x0 FEMPT FEMPT 6 1 read-only IFEN IFEN 5 1 read-write IFS IFS 2 1 read-write ILEN ILEN 4 1 read-write ILS ILS 1 1 read-write IREN IREN 3 1 read-write IRS IRS 0 1 read-write FPU Floting point unit FPU 0x0 0x0 0xD registers n FPU Floating point interrupt 81 FPU Floating point interrupt 81 FPCAR FPCAR Floating-point context address register 0x4 32 read-write n 0x0 0x0 ADDRESS Location of unpopulated floating-point 3 29 FPCCR FPCCR Floating-point context control register 0x0 32 read-write n 0x0 0x0 ASPEN ASPEN 31 1 BFRDY BFRDY 6 1 HFRDY HFRDY 4 1 LSPACT LSPACT 0 1 LSPEN LSPEN 30 1 MMRDY MMRDY 5 1 MONRDY MONRDY 8 1 THREAD THREAD 3 1 USER USER 1 1 FPSCR FPSCR Floating-point status control register 0x8 32 read-write n 0x0 0x0 AHP Alternative half-precision control bit 26 1 C Carry condition code flag 29 1 DN Default NaN mode control bit 25 1 DZC Division by zero cumulative exception bit. 1 1 FZ Flush-to-zero mode control bit: 24 1 IDC Input denormal cumulative exception bit. 7 1 IOC Invalid operation cumulative exception bit 0 1 IXC Inexact cumulative exception bit 4 1 N Negative condition code flag 31 1 OFC Overflow cumulative exception bit 2 1 RMode Rounding Mode control field 22 2 UFC Underflow cumulative exception bit 3 1 V Overflow condition code flag 28 1 Z Zero condition code flag 30 1 FPU_CPACR Floating point unit CPACR FPU 0x0 0x0 0x5 registers n CPACR CPACR Coprocessor access control register 0x0 32 read-write n 0x0 0x0 CP CP 20 4 GFXMMU Graphic MMU GFXMMU 0x0 0x0 0x3000 registers n GFXMMU GFXMMU global error interrupt 93 B0CR B0CR Graphic MMU buffer 0 configuration register 0x20 32 read-write n 0x0 0x0 PBBA Physical buffer base address 23 9 PBO Physical buffer offset 4 19 B1CR B1CR Graphic MMU buffer 1 configuration register 0x24 32 read-write n 0x0 0x0 PBBA Physical buffer base address 23 9 PBO Physical buffer offset 4 19 B2CR B2CR Graphic MMU buffer 2 configuration register 0x28 32 read-write n 0x0 0x0 PBBA Physical buffer base address 23 9 PBO Physical buffer offset 4 19 B3CR B3CR Graphic MMU buffer 3 configuration register 0x2C 32 read-write n 0x0 0x0 PBBA Physical buffer base address 23 9 PBO Physical buffer offset 4 19 CR CR Graphic MMU configuration register 0x0 32 read-write n 0x0 0x0 AMEIE AHB master error interrupt enable 4 1 B0OIE Buffer 0 overflow interrupt enable 0 1 B1OIE Buffer 1 overflow interrupt enable 1 1 B2OIE Buffer 2 overflow interrupt enable 2 1 B3OIE Buffer 3 overflow interrupt enable 3 1 BM192 192 Block mode 6 1 DVR DVR Graphic MMU default value register 0x10 32 read-write n 0x0 0x0 DV Default value 0 32 FCR FCR Graphic MMU flag clear register 0x8 32 write-only n 0x0 0x0 CAMEF Clear AHB master error flag 4 1 CB0OF Clear buffer 0 overflow flag 0 1 CB1OF Clear buffer 1 overflow flag 1 1 CB2OF Clear buffer 2 overflow flag 2 1 CB3OF Clear buffer 3 overflow flag 3 1 IPIDR IPIDR Graphic MMU identification register 0xFF8 32 read-only n 0x0 0x0 ID Identification Code 0 32 LUT0H LUT0H Graphic MMU LUT entry 0 high 0x1004 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT0L LUT0L Graphic MMU LUT entry 0 low 0x1000 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1000H LUT1000H Graphic MMU LUT entry 1000 high 0x2F44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1000L LUT1000L Graphic MMU LUT entry 1000 low 0x2F40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1001H LUT1001H Graphic MMU LUT entry 1001 high 0x2F4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1001L LUT1001L Graphic MMU LUT entry 1001 low 0x2F48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1002H LUT1002H Graphic MMU LUT entry 1002 high 0x2F54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1002L LUT1002L Graphic MMU LUT entry 1002 low 0x2F50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1003H LUT1003H Graphic MMU LUT entry 1003 high 0x2F5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1003L LUT1003L Graphic MMU LUT entry 1003 low 0x2F58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1004H LUT1004H Graphic MMU LUT entry 1004 high 0x2F64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1004L LUT1004L Graphic MMU LUT entry 1004 low 0x2F60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1005H LUT1005H Graphic MMU LUT entry 1005 high 0x2F6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1005L LUT1005L Graphic MMU LUT entry 1005 low 0x2F68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1006H LUT1006H Graphic MMU LUT entry 1006 high 0x2F74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1006L LUT1006L Graphic MMU LUT entry 1006 low 0x2F70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1007H LUT1007H Graphic MMU LUT entry 1007 high 0x2F7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1007L LUT1007L Graphic MMU LUT entry 1007 low 0x2F78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1008H LUT1008H Graphic MMU LUT entry 1008 high 0x2F84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1008L LUT1008L Graphic MMU LUT entry 1008 low 0x2F80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1009H LUT1009H Graphic MMU LUT entry 1009 high 0x2F8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1009L LUT1009L Graphic MMU LUT entry 1009 low 0x2F88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT100H LUT100H Graphic MMU LUT entry 100 high 0x1324 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT100L LUT100L Graphic MMU LUT entry 100 low 0x1320 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1010H LUT1010H Graphic MMU LUT entry 1010 high 0x2F94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1010L LUT1010L Graphic MMU LUT entry 1010 low 0x2F90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1011H LUT1011H Graphic MMU LUT entry 1011 high 0x2F9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1011L LUT1011L Graphic MMU LUT entry 1011 low 0x2F98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1012H LUT1012H Graphic MMU LUT entry 1012 high 0x2FA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1012L LUT1012L Graphic MMU LUT entry 1012 low 0x2FA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1013H LUT1013H Graphic MMU LUT entry 1013 high 0x2FAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1013L LUT1013L Graphic MMU LUT entry 1013 low 0x2FA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1014H LUT1014H Graphic MMU LUT entry 1014 high 0x2FB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1014L LUT1014L Graphic MMU LUT entry 1014 low 0x2FB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1015H LUT1015H Graphic MMU LUT entry 1015 high 0x2FBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1015L LUT1015L Graphic MMU LUT entry 1015 low 0x2FB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1016H LUT1016H Graphic MMU LUT entry 1016 high 0x2FC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1016L LUT1016L Graphic MMU LUT entry 1016 low 0x2FC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1017H LUT1017H Graphic MMU LUT entry 1017 high 0x2FCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1017L LUT1017L Graphic MMU LUT entry 1017 low 0x2FC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1018H LUT1018H Graphic MMU LUT entry 1018 high 0x2FD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1018L LUT1018L Graphic MMU LUT entry 1018 low 0x2FD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1019H LUT1019H Graphic MMU LUT entry 1019 high 0x2FDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1019L LUT1019L Graphic MMU LUT entry 1019 low 0x2FD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT101H LUT101H Graphic MMU LUT entry 101 high 0x132C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT101L LUT101L Graphic MMU LUT entry 101 low 0x1328 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1020H LUT1020H Graphic MMU LUT entry 1020 high 0x2FE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1020L LUT1020L Graphic MMU LUT entry 1020 low 0x2FE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1021H LUT1021H Graphic MMU LUT entry 1021 high 0x2FEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1021L LUT1021L Graphic MMU LUT entry 1021 low 0x2FE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1022H LUT1022H Graphic MMU LUT entry 1022 high 0x2FF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1022L LUT1022L Graphic MMU LUT entry 1022 low 0x2FF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1023H LUT1023H Graphic MMU LUT entry 1023 high 0x2FFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1023L LUT1023L Graphic MMU LUT entry 1023 low 0x2FF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT102H LUT102H Graphic MMU LUT entry 102 high 0x1334 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT102L LUT102L Graphic MMU LUT entry 102 low 0x1330 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT103H LUT103H Graphic MMU LUT entry 103 high 0x133C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT103L LUT103L Graphic MMU LUT entry 103 low 0x1338 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT104H LUT104H Graphic MMU LUT entry 104 high 0x1344 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT104L LUT104L Graphic MMU LUT entry 104 low 0x1340 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT105H LUT105H Graphic MMU LUT entry 105 high 0x134C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT105L LUT105L Graphic MMU LUT entry 105 low 0x1348 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT106H LUT106H Graphic MMU LUT entry 106 high 0x1354 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT106L LUT106L Graphic MMU LUT entry 106 low 0x1350 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT107H LUT107H Graphic MMU LUT entry 107 high 0x135C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT107L LUT107L Graphic MMU LUT entry 107 low 0x1358 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT108H LUT108H Graphic MMU LUT entry 108 high 0x1364 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT108L LUT108L Graphic MMU LUT entry 108 low 0x1360 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT109H LUT109H Graphic MMU LUT entry 109 high 0x136C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT109L LUT109L Graphic MMU LUT entry 109 low 0x1368 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT10H LUT10H Graphic MMU LUT entry 10 high 0x1054 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT10L LUT10L Graphic MMU LUT entry 10 low 0x1050 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT110H LUT110H Graphic MMU LUT entry 110 high 0x1374 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT110L LUT110L Graphic MMU LUT entry 110 low 0x1370 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT111H LUT111H Graphic MMU LUT entry 111 high 0x137C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT111L LUT111L Graphic MMU LUT entry 111 low 0x1378 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT112H LUT112H Graphic MMU LUT entry 112 high 0x1384 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT112L LUT112L Graphic MMU LUT entry 112 low 0x1380 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT113H LUT113H Graphic MMU LUT entry 113 high 0x138C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT113L LUT113L Graphic MMU LUT entry 113 low 0x1388 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT114H LUT114H Graphic MMU LUT entry 114 high 0x1394 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT114L LUT114L Graphic MMU LUT entry 114 low 0x1390 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT115H LUT115H Graphic MMU LUT entry 115 high 0x139C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT115L LUT115L Graphic MMU LUT entry 115 low 0x1398 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT116H LUT116H Graphic MMU LUT entry 116 high 0x13A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT116L LUT116L Graphic MMU LUT entry 116 low 0x13A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT117H LUT117H Graphic MMU LUT entry 117 high 0x13AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT117L LUT117L Graphic MMU LUT entry 117 low 0x13A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT118H LUT118H Graphic MMU LUT entry 118 high 0x13B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT118L LUT118L Graphic MMU LUT entry 118 low 0x13B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT119H LUT119H Graphic MMU LUT entry 119 high 0x13BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT119L LUT119L Graphic MMU LUT entry 119 low 0x13B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT11H LUT11H Graphic MMU LUT entry 11 high 0x105C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT11L LUT11L Graphic MMU LUT entry 11 low 0x1058 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT120H LUT120H Graphic MMU LUT entry 120 high 0x13C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT120L LUT120L Graphic MMU LUT entry 120 low 0x13C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT121H LUT121H Graphic MMU LUT entry 121 high 0x13CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT121L LUT121L Graphic MMU LUT entry 121 low 0x13C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT122H LUT122H Graphic MMU LUT entry 122 high 0x13D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT122L LUT122L Graphic MMU LUT entry 122 low 0x13D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT123H LUT123H Graphic MMU LUT entry 123 high 0x13DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT123L LUT123L Graphic MMU LUT entry 123 low 0x13D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT124H LUT124H Graphic MMU LUT entry 124 high 0x13E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT124L LUT124L Graphic MMU LUT entry 124 low 0x13E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT125H LUT125H Graphic MMU LUT entry 125 high 0x13EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT125L LUT125L Graphic MMU LUT entry 125 low 0x13E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT126H LUT126H Graphic MMU LUT entry 126 high 0x13F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT126L LUT126L Graphic MMU LUT entry 126 low 0x13F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT127H LUT127H Graphic MMU LUT entry 127 high 0x13FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT127L LUT127L Graphic MMU LUT entry 127 low 0x13F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT128H LUT128H Graphic MMU LUT entry 128 high 0x1404 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT128L LUT128L Graphic MMU LUT entry 128 low 0x1400 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT129H LUT129H Graphic MMU LUT entry 129 high 0x140C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT129L LUT129L Graphic MMU LUT entry 129 low 0x1408 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT12H LUT12H Graphic MMU LUT entry 12 high 0x1064 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT12L LUT12L Graphic MMU LUT entry 12 low 0x1060 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT130H LUT130H Graphic MMU LUT entry 130 high 0x1414 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT130L LUT130L Graphic MMU LUT entry 130 low 0x1410 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT131H LUT131H Graphic MMU LUT entry 131 high 0x141C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT131L LUT131L Graphic MMU LUT entry 131 low 0x1418 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT132H LUT132H Graphic MMU LUT entry 132 high 0x1424 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT132L LUT132L Graphic MMU LUT entry 132 low 0x1420 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT133H LUT133H Graphic MMU LUT entry 133 high 0x142C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT133L LUT133L Graphic MMU LUT entry 133 low 0x1428 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT134H LUT134H Graphic MMU LUT entry 134 high 0x1434 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT134L LUT134L Graphic MMU LUT entry 134 low 0x1430 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT135H LUT135H Graphic MMU LUT entry 135 high 0x143C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT135L LUT135L Graphic MMU LUT entry 135 low 0x1438 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT136H LUT136H Graphic MMU LUT entry 136 high 0x1444 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT136L LUT136L Graphic MMU LUT entry 136 low 0x1440 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT137H LUT137H Graphic MMU LUT entry 137 high 0x144C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT137L LUT137L Graphic MMU LUT entry 137 low 0x1448 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT138H LUT138H Graphic MMU LUT entry 138 high 0x1454 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT138L LUT138L Graphic MMU LUT entry 138 low 0x1450 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT139H LUT139H Graphic MMU LUT entry 139 high 0x145C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT139L LUT139L Graphic MMU LUT entry 139 low 0x1458 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT13H LUT13H Graphic MMU LUT entry 13 high 0x106C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT13L LUT13L Graphic MMU LUT entry 13 low 0x1068 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT140H LUT140H Graphic MMU LUT entry 140 high 0x1464 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT140L LUT140L Graphic MMU LUT entry 140 low 0x1460 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT141H LUT141H Graphic MMU LUT entry 141 high 0x146C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT141L LUT141L Graphic MMU LUT entry 141 low 0x1468 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT142H LUT142H Graphic MMU LUT entry 142 high 0x1474 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT142L LUT142L Graphic MMU LUT entry 142 low 0x1470 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT143H LUT143H Graphic MMU LUT entry 143 high 0x147C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT143L LUT143L Graphic MMU LUT entry 143 low 0x1478 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT144H LUT144H Graphic MMU LUT entry 144 high 0x1484 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT144L LUT144L Graphic MMU LUT entry 144 low 0x1480 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT145H LUT145H Graphic MMU LUT entry 145 high 0x148C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT145L LUT145L Graphic MMU LUT entry 145 low 0x1488 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT146H LUT146H Graphic MMU LUT entry 146 high 0x1494 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT146L LUT146L Graphic MMU LUT entry 146 low 0x1490 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT147H LUT147H Graphic MMU LUT entry 147 high 0x149C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT147L LUT147L Graphic MMU LUT entry 147 low 0x1498 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT148H LUT148H Graphic MMU LUT entry 148 high 0x14A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT148L LUT148L Graphic MMU LUT entry 148 low 0x14A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT149H LUT149H Graphic MMU LUT entry 149 high 0x14AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT149L LUT149L Graphic MMU LUT entry 149 low 0x14A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT14H LUT14H Graphic MMU LUT entry 14 high 0x1074 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT14L LUT14L Graphic MMU LUT entry 14 low 0x1070 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT150H LUT150H Graphic MMU LUT entry 150 high 0x14B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT150L LUT150L Graphic MMU LUT entry 150 low 0x14B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT151H LUT151H Graphic MMU LUT entry 151 high 0x14BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT151L LUT151L Graphic MMU LUT entry 151 low 0x14B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT152H LUT152H Graphic MMU LUT entry 152 high 0x14C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT152L LUT152L Graphic MMU LUT entry 152 low 0x14C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT153H LUT153H Graphic MMU LUT entry 153 high 0x14CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT153L LUT153L Graphic MMU LUT entry 153 low 0x14C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT154H LUT154H Graphic MMU LUT entry 154 high 0x14D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT154L LUT154L Graphic MMU LUT entry 154 low 0x14D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT155H LUT155H Graphic MMU LUT entry 155 high 0x14DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT155L LUT155L Graphic MMU LUT entry 155 low 0x14D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT156H LUT156H Graphic MMU LUT entry 156 high 0x14E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT156L LUT156L Graphic MMU LUT entry 156 low 0x14E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT157H LUT157H Graphic MMU LUT entry 157 high 0x14EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT157L LUT157L Graphic MMU LUT entry 157 low 0x14E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT158H LUT158H Graphic MMU LUT entry 158 high 0x14F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT158L LUT158L Graphic MMU LUT entry 158 low 0x14F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT159H LUT159H Graphic MMU LUT entry 159 high 0x14FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT159L LUT159L Graphic MMU LUT entry 159 low 0x14F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT15H LUT15H Graphic MMU LUT entry 15 high 0x107C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT15L LUT15L Graphic MMU LUT entry 15 low 0x1078 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT160H LUT160H Graphic MMU LUT entry 160 high 0x1504 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT160L LUT160L Graphic MMU LUT entry 160 low 0x1500 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT161H LUT161H Graphic MMU LUT entry 161 high 0x150C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT161L LUT161L Graphic MMU LUT entry 161 low 0x1508 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT162H LUT162H Graphic MMU LUT entry 162 high 0x1514 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT162L LUT162L Graphic MMU LUT entry 162 low 0x1510 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT163H LUT163H Graphic MMU LUT entry 163 high 0x151C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT163L LUT163L Graphic MMU LUT entry 163 low 0x1518 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT164H LUT164H Graphic MMU LUT entry 164 high 0x1524 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT164L LUT164L Graphic MMU LUT entry 164 low 0x1520 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT165H LUT165H Graphic MMU LUT entry 165 high 0x152C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT165L LUT165L Graphic MMU LUT entry 165 low 0x1528 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT166H LUT166H Graphic MMU LUT entry 166 high 0x1534 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT166L LUT166L Graphic MMU LUT entry 166 low 0x1530 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT167H LUT167H Graphic MMU LUT entry 167 high 0x153C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT167L LUT167L Graphic MMU LUT entry 167 low 0x1538 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT168H LUT168H Graphic MMU LUT entry 168 high 0x1544 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT168L LUT168L Graphic MMU LUT entry 168 low 0x1540 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT169H LUT169H Graphic MMU LUT entry 169 high 0x154C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT169L LUT169L Graphic MMU LUT entry 169 low 0x1548 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT16H LUT16H Graphic MMU LUT entry 16 high 0x1084 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT16L LUT16L Graphic MMU LUT entry 16 low 0x1080 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT170H LUT170H Graphic MMU LUT entry 170 high 0x1554 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT170L LUT170L Graphic MMU LUT entry 170 low 0x1550 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT171H LUT171H Graphic MMU LUT entry 171 high 0x155C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT171L LUT171L Graphic MMU LUT entry 171 low 0x1558 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT172H LUT172H Graphic MMU LUT entry 172 high 0x1564 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT172L LUT172L Graphic MMU LUT entry 172 low 0x1560 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT173H LUT173H Graphic MMU LUT entry 173 high 0x156C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT173L LUT173L Graphic MMU LUT entry 173 low 0x1568 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT174H LUT174H Graphic MMU LUT entry 174 high 0x1574 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT174L LUT174L Graphic MMU LUT entry 174 low 0x1570 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT175H LUT175H Graphic MMU LUT entry 175 high 0x157C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT175L LUT175L Graphic MMU LUT entry 175 low 0x1578 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT176H LUT176H Graphic MMU LUT entry 176 high 0x1584 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT176L LUT176L Graphic MMU LUT entry 176 low 0x1580 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT177H LUT177H Graphic MMU LUT entry 177 high 0x158C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT177L LUT177L Graphic MMU LUT entry 177 low 0x1588 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT178H LUT178H Graphic MMU LUT entry 178 high 0x1594 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT178L LUT178L Graphic MMU LUT entry 178 low 0x1590 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT179H LUT179H Graphic MMU LUT entry 179 high 0x159C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT179L LUT179L Graphic MMU LUT entry 179 low 0x1598 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT17H LUT17H Graphic MMU LUT entry 17 high 0x108C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT17L LUT17L Graphic MMU LUT entry 17 low 0x1088 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT180H LUT180H Graphic MMU LUT entry 180 high 0x15A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT180L LUT180L Graphic MMU LUT entry 180 low 0x15A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT181H LUT181H Graphic MMU LUT entry 181 high 0x15AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT181L LUT181L Graphic MMU LUT entry 181 low 0x15A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT182H LUT182H Graphic MMU LUT entry 182 high 0x15B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT182L LUT182L Graphic MMU LUT entry 182 low 0x15B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT183H LUT183H Graphic MMU LUT entry 183 high 0x15BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT183L LUT183L Graphic MMU LUT entry 183 low 0x15B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT184H LUT184H Graphic MMU LUT entry 184 high 0x15C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT184L LUT184L Graphic MMU LUT entry 184 low 0x15C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT185H LUT185H Graphic MMU LUT entry 185 high 0x15CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT185L LUT185L Graphic MMU LUT entry 185 low 0x15C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT186H LUT186H Graphic MMU LUT entry 186 high 0x15D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT186L LUT186L Graphic MMU LUT entry 186 low 0x15D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT187H LUT187H Graphic MMU LUT entry 187 high 0x15DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT187L LUT187L Graphic MMU LUT entry 187 low 0x15D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT188H LUT188H Graphic MMU LUT entry 188 high 0x15E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT188L LUT188L Graphic MMU LUT entry 188 low 0x15E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT189H LUT189H Graphic MMU LUT entry 189 high 0x15EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT189L LUT189L Graphic MMU LUT entry 189 low 0x15E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT18H LUT18H Graphic MMU LUT entry 18 high 0x1094 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT18L LUT18L Graphic MMU LUT entry 18 low 0x1090 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT190H LUT190H Graphic MMU LUT entry 190 high 0x15F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT190L LUT190L Graphic MMU LUT entry 190 low 0x15F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT191H LUT191H Graphic MMU LUT entry 191 high 0x15FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT191L LUT191L Graphic MMU LUT entry 191 low 0x15F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT192H LUT192H Graphic MMU LUT entry 192 high 0x1604 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT192L LUT192L Graphic MMU LUT entry 192 low 0x1600 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT193H LUT193H Graphic MMU LUT entry 193 high 0x160C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT193L LUT193L Graphic MMU LUT entry 193 low 0x1608 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT194H LUT194H Graphic MMU LUT entry 194 high 0x1614 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT194L LUT194L Graphic MMU LUT entry 194 low 0x1610 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT195H LUT195H Graphic MMU LUT entry 195 high 0x161C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT195L LUT195L Graphic MMU LUT entry 195 low 0x1618 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT196H LUT196H Graphic MMU LUT entry 196 high 0x1624 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT196L LUT196L Graphic MMU LUT entry 196 low 0x1620 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT197H LUT197H Graphic MMU LUT entry 197 high 0x162C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT197L LUT197L Graphic MMU LUT entry 197 low 0x1628 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT198H LUT198H Graphic MMU LUT entry 198 high 0x1634 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT198L LUT198L Graphic MMU LUT entry 198 low 0x1630 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT199H LUT199H Graphic MMU LUT entry 199 high 0x163C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT199L LUT199L Graphic MMU LUT entry 199 low 0x1638 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT19H LUT19H Graphic MMU LUT entry 19 high 0x109C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT19L LUT19L Graphic MMU LUT entry 19 low 0x1098 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT1H LUT1H Graphic MMU LUT entry 1 high 0x100C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT1L LUT1L Graphic MMU LUT entry 1 low 0x1008 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT200H LUT200H Graphic MMU LUT entry 200 high 0x1644 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT200L LUT200L Graphic MMU LUT entry 200 low 0x1640 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT201H LUT201H Graphic MMU LUT entry 201 high 0x164C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT201L LUT201L Graphic MMU LUT entry 201 low 0x1648 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT202H LUT202H Graphic MMU LUT entry 202 high 0x1654 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT202L LUT202L Graphic MMU LUT entry 202 low 0x1650 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT203H LUT203H Graphic MMU LUT entry 203 high 0x165C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT203L LUT203L Graphic MMU LUT entry 203 low 0x1658 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT204H LUT204H Graphic MMU LUT entry 204 high 0x1664 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT204L LUT204L Graphic MMU LUT entry 204 low 0x1660 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT205H LUT205H Graphic MMU LUT entry 205 high 0x166C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT205L LUT205L Graphic MMU LUT entry 205 low 0x1668 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT206H LUT206H Graphic MMU LUT entry 206 high 0x1674 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT206L LUT206L Graphic MMU LUT entry 206 low 0x1670 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT207H LUT207H Graphic MMU LUT entry 207 high 0x167C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT207L LUT207L Graphic MMU LUT entry 207 low 0x1678 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT208H LUT208H Graphic MMU LUT entry 208 high 0x1684 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT208L LUT208L Graphic MMU LUT entry 208 low 0x1680 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT209H LUT209H Graphic MMU LUT entry 209 high 0x168C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT209L LUT209L Graphic MMU LUT entry 209 low 0x1688 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT20H LUT20H Graphic MMU LUT entry 20 high 0x10A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT20L LUT20L Graphic MMU LUT entry 20 low 0x10A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT210H LUT210H Graphic MMU LUT entry 210 high 0x1694 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT210L LUT210L Graphic MMU LUT entry 210 low 0x1690 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT211H LUT211H Graphic MMU LUT entry 211 high 0x169C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT211L LUT211L Graphic MMU LUT entry 211 low 0x1698 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT212H LUT212H Graphic MMU LUT entry 212 high 0x16A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT212L LUT212L Graphic MMU LUT entry 212 low 0x16A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT213H LUT213H Graphic MMU LUT entry 213 high 0x16AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT213L LUT213L Graphic MMU LUT entry 213 low 0x16A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT214H LUT214H Graphic MMU LUT entry 214 high 0x16B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT214L LUT214L Graphic MMU LUT entry 214 low 0x16B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT215H LUT215H Graphic MMU LUT entry 215 high 0x16BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT215L LUT215L Graphic MMU LUT entry 215 low 0x16B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT216H LUT216H Graphic MMU LUT entry 216 high 0x16C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT216L LUT216L Graphic MMU LUT entry 216 low 0x16C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT217H LUT217H Graphic MMU LUT entry 217 high 0x16CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT217L LUT217L Graphic MMU LUT entry 217 low 0x16C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT218H LUT218H Graphic MMU LUT entry 218 high 0x16D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT218L LUT218L Graphic MMU LUT entry 218 low 0x16D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT219H LUT219H Graphic MMU LUT entry 219 high 0x16DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT219L LUT219L Graphic MMU LUT entry 219 low 0x16D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT21H LUT21H Graphic MMU LUT entry 21 high 0x10AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT21L LUT21L Graphic MMU LUT entry 21 low 0x10A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT220H LUT220H Graphic MMU LUT entry 220 high 0x16E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT220L LUT220L Graphic MMU LUT entry 220 low 0x16E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT221H LUT221H Graphic MMU LUT entry 221 high 0x16EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT221L LUT221L Graphic MMU LUT entry 221 low 0x16E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT222H LUT222H Graphic MMU LUT entry 222 high 0x16F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT222L LUT222L Graphic MMU LUT entry 222 low 0x16F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT223H LUT223H Graphic MMU LUT entry 223 high 0x16FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT223L LUT223L Graphic MMU LUT entry 223 low 0x16F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT224H LUT224H Graphic MMU LUT entry 224 high 0x1704 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT224L LUT224L Graphic MMU LUT entry 224 low 0x1700 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT225H LUT225H Graphic MMU LUT entry 225 high 0x170C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT225L LUT225L Graphic MMU LUT entry 225 low 0x1708 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT226H LUT226H Graphic MMU LUT entry 226 high 0x1714 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT226L LUT226L Graphic MMU LUT entry 226 low 0x1710 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT227H LUT227H Graphic MMU LUT entry 227 high 0x171C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT227L LUT227L Graphic MMU LUT entry 227 low 0x1718 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT228H LUT228H Graphic MMU LUT entry 228 high 0x1724 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT228L LUT228L Graphic MMU LUT entry 228 low 0x1720 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT229H LUT229H Graphic MMU LUT entry 229 high 0x172C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT229L LUT229L Graphic MMU LUT entry 229 low 0x1728 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT22H LUT22H Graphic MMU LUT entry 22 high 0x10B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT22L LUT22L Graphic MMU LUT entry 22 low 0x10B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT230H LUT230H Graphic MMU LUT entry 230 high 0x1734 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT230L LUT230L Graphic MMU LUT entry 230 low 0x1730 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT231H LUT231H Graphic MMU LUT entry 231 high 0x173C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT231L LUT231L Graphic MMU LUT entry 231 low 0x1738 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT232H LUT232H Graphic MMU LUT entry 232 high 0x1744 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT232L LUT232L Graphic MMU LUT entry 232 low 0x1740 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT233H LUT233H Graphic MMU LUT entry 233 high 0x174C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT233L LUT233L Graphic MMU LUT entry 233 low 0x1748 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT234H LUT234H Graphic MMU LUT entry 234 high 0x1754 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT234L LUT234L Graphic MMU LUT entry 234 low 0x1750 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT235H LUT235H Graphic MMU LUT entry 235 high 0x175C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT235L LUT235L Graphic MMU LUT entry 235 low 0x1758 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT236H LUT236H Graphic MMU LUT entry 236 high 0x1764 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT236L LUT236L Graphic MMU LUT entry 236 low 0x1760 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT237H LUT237H Graphic MMU LUT entry 237 high 0x176C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT237L LUT237L Graphic MMU LUT entry 237 low 0x1768 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT238H LUT238H Graphic MMU LUT entry 238 high 0x1774 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT238L LUT238L Graphic MMU LUT entry 238 low 0x1770 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT239H LUT239H Graphic MMU LUT entry 239 high 0x177C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT239L LUT239L Graphic MMU LUT entry 239 low 0x1778 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT23H LUT23H Graphic MMU LUT entry 23 high 0x10BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT23L LUT23L Graphic MMU LUT entry 23 low 0x10B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT240H LUT240H Graphic MMU LUT entry 240 high 0x1784 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT240L LUT240L Graphic MMU LUT entry 240 low 0x1780 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT241H LUT241H Graphic MMU LUT entry 241 high 0x178C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT241L LUT241L Graphic MMU LUT entry 241 low 0x1788 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT242H LUT242H Graphic MMU LUT entry 242 high 0x1794 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT242L LUT242L Graphic MMU LUT entry 242 low 0x1790 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT243H LUT243H Graphic MMU LUT entry 243 high 0x179C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT243L LUT243L Graphic MMU LUT entry 243 low 0x1798 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT244H LUT244H Graphic MMU LUT entry 244 high 0x17A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT244L LUT244L Graphic MMU LUT entry 244 low 0x17A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT245H LUT245H Graphic MMU LUT entry 245 high 0x17AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT245L LUT245L Graphic MMU LUT entry 245 low 0x17A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT246H LUT246H Graphic MMU LUT entry 246 high 0x17B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT246L LUT246L Graphic MMU LUT entry 246 low 0x17B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT247H LUT247H Graphic MMU LUT entry 247 high 0x17BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT247L LUT247L Graphic MMU LUT entry 247 low 0x17B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT248H LUT248H Graphic MMU LUT entry 248 high 0x17C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT248L LUT248L Graphic MMU LUT entry 248 low 0x17C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT249H LUT249H Graphic MMU LUT entry 249 high 0x17CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT249L LUT249L Graphic MMU LUT entry 249 low 0x17C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT24H LUT24H Graphic MMU LUT entry 24 high 0x10C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT24L LUT24L Graphic MMU LUT entry 24 low 0x10C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT250H LUT250H Graphic MMU LUT entry 250 high 0x17D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT250L LUT250L Graphic MMU LUT entry 250 low 0x17D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT251H LUT251H Graphic MMU LUT entry 251 high 0x17DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT251L LUT251L Graphic MMU LUT entry 251 low 0x17D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT252H LUT252H Graphic MMU LUT entry 252 high 0x17E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT252L LUT252L Graphic MMU LUT entry 252 low 0x17E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT253H LUT253H Graphic MMU LUT entry 253 high 0x17EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT253L LUT253L Graphic MMU LUT entry 253 low 0x17E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT254H LUT254H Graphic MMU LUT entry 254 high 0x17F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT254L LUT254L Graphic MMU LUT entry 254 low 0x17F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT255H LUT255H Graphic MMU LUT entry 255 high 0x17FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT255L LUT255L Graphic MMU LUT entry 255 low 0x17F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT256H LUT256H Graphic MMU LUT entry 256 high 0x1804 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT256L LUT256L Graphic MMU LUT entry 256 low 0x1800 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT257H LUT257H Graphic MMU LUT entry 257 high 0x180C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT257L LUT257L Graphic MMU LUT entry 257 low 0x1808 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT258H LUT258H Graphic MMU LUT entry 258 high 0x1814 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT258L LUT258L Graphic MMU LUT entry 258 low 0x1810 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT259H LUT259H Graphic MMU LUT entry 259 high 0x181C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT259L LUT259L Graphic MMU LUT entry 259 low 0x1818 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT25H LUT25H Graphic MMU LUT entry 25 high 0x10CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT25L LUT25L Graphic MMU LUT entry 25 low 0x10C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT260H LUT260H Graphic MMU LUT entry 260 high 0x1824 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT260L LUT260L Graphic MMU LUT entry 260 low 0x1820 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT261H LUT261H Graphic MMU LUT entry 261 high 0x182C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT261L LUT261L Graphic MMU LUT entry 261 low 0x1828 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT262H LUT262H Graphic MMU LUT entry 262 high 0x1834 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT262L LUT262L Graphic MMU LUT entry 262 low 0x1830 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT263H LUT263H Graphic MMU LUT entry 263 high 0x183C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT263L LUT263L Graphic MMU LUT entry 263 low 0x1838 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT264H LUT264H Graphic MMU LUT entry 264 high 0x1844 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT264L LUT264L Graphic MMU LUT entry 264 low 0x1840 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT265H LUT265H Graphic MMU LUT entry 265 high 0x184C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT265L LUT265L Graphic MMU LUT entry 265 low 0x1848 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT266H LUT266H Graphic MMU LUT entry 266 high 0x1854 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT266L LUT266L Graphic MMU LUT entry 266 low 0x1850 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT267H LUT267H Graphic MMU LUT entry 267 high 0x185C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT267L LUT267L Graphic MMU LUT entry 267 low 0x1858 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT268H LUT268H Graphic MMU LUT entry 268 high 0x1864 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT268L LUT268L Graphic MMU LUT entry 268 low 0x1860 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT269H LUT269H Graphic MMU LUT entry 269 high 0x186C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT269L LUT269L Graphic MMU LUT entry 269 low 0x1868 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT26H LUT26H Graphic MMU LUT entry 26 high 0x10D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT26L LUT26L Graphic MMU LUT entry 26 low 0x10D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT270H LUT270H Graphic MMU LUT entry 270 high 0x1874 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT270L LUT270L Graphic MMU LUT entry 270 low 0x1870 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT271H LUT271H Graphic MMU LUT entry 271 high 0x187C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT271L LUT271L Graphic MMU LUT entry 271 low 0x1878 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT272H LUT272H Graphic MMU LUT entry 272 high 0x1884 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT272L LUT272L Graphic MMU LUT entry 272 low 0x1880 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT273H LUT273H Graphic MMU LUT entry 273 high 0x188C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT273L LUT273L Graphic MMU LUT entry 273 low 0x1888 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT274H LUT274H Graphic MMU LUT entry 274 high 0x1894 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT274L LUT274L Graphic MMU LUT entry 274 low 0x1890 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT275H LUT275H Graphic MMU LUT entry 275 high 0x189C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT275L LUT275L Graphic MMU LUT entry 275 low 0x1898 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT276H LUT276H Graphic MMU LUT entry 276 high 0x18A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT276L LUT276L Graphic MMU LUT entry 276 low 0x18A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT277H LUT277H Graphic MMU LUT entry 277 high 0x18AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT277L LUT277L Graphic MMU LUT entry 277 low 0x18A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT278H LUT278H Graphic MMU LUT entry 278 high 0x18B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT278L LUT278L Graphic MMU LUT entry 278 low 0x18B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT279H LUT279H Graphic MMU LUT entry 279 high 0x18BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT279L LUT279L Graphic MMU LUT entry 279 low 0x18B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT27H LUT27H Graphic MMU LUT entry 27 high 0x10DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT27L LUT27L Graphic MMU LUT entry 27 low 0x10D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT280H LUT280H Graphic MMU LUT entry 280 high 0x18C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT280L LUT280L Graphic MMU LUT entry 280 low 0x18C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT281H LUT281H Graphic MMU LUT entry 281 high 0x18CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT281L LUT281L Graphic MMU LUT entry 281 low 0x18C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT282H LUT282H Graphic MMU LUT entry 282 high 0x18D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT282L LUT282L Graphic MMU LUT entry 282 low 0x18D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT283H LUT283H Graphic MMU LUT entry 283 high 0x18DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT283L LUT283L Graphic MMU LUT entry 283 low 0x18D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT284H LUT284H Graphic MMU LUT entry 284 high 0x18E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT284L LUT284L Graphic MMU LUT entry 284 low 0x18E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT285H LUT285H Graphic MMU LUT entry 285 high 0x18EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT285L LUT285L Graphic MMU LUT entry 285 low 0x18E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT286H LUT286H Graphic MMU LUT entry 286 high 0x18F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT286L LUT286L Graphic MMU LUT entry 286 low 0x18F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT287H LUT287H Graphic MMU LUT entry 287 high 0x18FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT287L LUT287L Graphic MMU LUT entry 287 low 0x18F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT288H LUT288H Graphic MMU LUT entry 288 high 0x1904 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT288L LUT288L Graphic MMU LUT entry 288 low 0x1900 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT289H LUT289H Graphic MMU LUT entry 289 high 0x190C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT289L LUT289L Graphic MMU LUT entry 289 low 0x1908 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT28H LUT28H Graphic MMU LUT entry 28 high 0x10E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT28L LUT28L Graphic MMU LUT entry 28 low 0x10E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT290H LUT290H Graphic MMU LUT entry 290 high 0x1914 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT290L LUT290L Graphic MMU LUT entry 290 low 0x1910 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT291H LUT291H Graphic MMU LUT entry 291 high 0x191C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT291L LUT291L Graphic MMU LUT entry 291 low 0x1918 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT292H LUT292H Graphic MMU LUT entry 292 high 0x1924 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT292L LUT292L Graphic MMU LUT entry 292 low 0x1920 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT293H LUT293H Graphic MMU LUT entry 293 high 0x192C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT293L LUT293L Graphic MMU LUT entry 293 low 0x1928 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT294H LUT294H Graphic MMU LUT entry 294 high 0x1934 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT294L LUT294L Graphic MMU LUT entry 294 low 0x1930 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT295H LUT295H Graphic MMU LUT entry 295 high 0x193C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT295L LUT295L Graphic MMU LUT entry 295 low 0x1938 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT296H LUT296H Graphic MMU LUT entry 296 high 0x1944 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT296L LUT296L Graphic MMU LUT entry 296 low 0x1940 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT297H LUT297H Graphic MMU LUT entry 297 high 0x194C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT297L LUT297L Graphic MMU LUT entry 297 low 0x1948 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT298H LUT298H Graphic MMU LUT entry 298 high 0x1954 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT298L LUT298L Graphic MMU LUT entry 298 low 0x1950 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT299H LUT299H Graphic MMU LUT entry 299 high 0x195C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT299L LUT299L Graphic MMU LUT entry 299 low 0x1958 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT29H LUT29H Graphic MMU LUT entry 29 high 0x10EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT29L LUT29L Graphic MMU LUT entry 29 low 0x10E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT2H LUT2H Graphic MMU LUT entry 2 high 0x1014 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT2L LUT2L Graphic MMU LUT entry 2 low 0x1010 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT300H LUT300H Graphic MMU LUT entry 300 high 0x1964 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT300L LUT300L Graphic MMU LUT entry 300 low 0x1960 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT301H LUT301H Graphic MMU LUT entry 301 high 0x196C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT301L LUT301L Graphic MMU LUT entry 301 low 0x1968 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT302H LUT302H Graphic MMU LUT entry 302 high 0x1974 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT302L LUT302L Graphic MMU LUT entry 302 low 0x1970 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT303H LUT303H Graphic MMU LUT entry 303 high 0x197C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT303L LUT303L Graphic MMU LUT entry 303 low 0x1978 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT304H LUT304H Graphic MMU LUT entry 304 high 0x1984 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT304L LUT304L Graphic MMU LUT entry 304 low 0x1980 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT305H LUT305H Graphic MMU LUT entry 305 high 0x198C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT305L LUT305L Graphic MMU LUT entry 305 low 0x1988 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT306H LUT306H Graphic MMU LUT entry 306 high 0x1994 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT306L LUT306L Graphic MMU LUT entry 306 low 0x1990 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT307H LUT307H Graphic MMU LUT entry 307 high 0x199C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT307L LUT307L Graphic MMU LUT entry 307 low 0x1998 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT308H LUT308H Graphic MMU LUT entry 308 high 0x19A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT308L LUT308L Graphic MMU LUT entry 308 low 0x19A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT309H LUT309H Graphic MMU LUT entry 309 high 0x19AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT309L LUT309L Graphic MMU LUT entry 309 low 0x19A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT30H LUT30H Graphic MMU LUT entry 30 high 0x10F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT30L LUT30L Graphic MMU LUT entry 30 low 0x10F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT310H LUT310H Graphic MMU LUT entry 310 high 0x19B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT310L LUT310L Graphic MMU LUT entry 310 low 0x19B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT311H LUT311H Graphic MMU LUT entry 311 high 0x19BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT311L LUT311L Graphic MMU LUT entry 311 low 0x19B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT312H LUT312H Graphic MMU LUT entry 312 high 0x19C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT312L LUT312L Graphic MMU LUT entry 312 low 0x19C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT313H LUT313H Graphic MMU LUT entry 313 high 0x19CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT313L LUT313L Graphic MMU LUT entry 313 low 0x19C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT314H LUT314H Graphic MMU LUT entry 314 high 0x19D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT314L LUT314L Graphic MMU LUT entry 314 low 0x19D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT315H LUT315H Graphic MMU LUT entry 315 high 0x19DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT315L LUT315L Graphic MMU LUT entry 315 low 0x19D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT316H LUT316H Graphic MMU LUT entry 316 high 0x19E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT316L LUT316L Graphic MMU LUT entry 316 low 0x19E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT317H LUT317H Graphic MMU LUT entry 317 high 0x19EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT317L LUT317L Graphic MMU LUT entry 317 low 0x19E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT318H LUT318H Graphic MMU LUT entry 318 high 0x19F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT318L LUT318L Graphic MMU LUT entry 318 low 0x19F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT319H LUT319H Graphic MMU LUT entry 319 high 0x19FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT319L LUT319L Graphic MMU LUT entry 319 low 0x19F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT31H LUT31H Graphic MMU LUT entry 31 high 0x10FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT31L LUT31L Graphic MMU LUT entry 31 low 0x10F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT320H LUT320H Graphic MMU LUT entry 320 high 0x1A04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT320L LUT320L Graphic MMU LUT entry 320 low 0x1A00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT321H LUT321H Graphic MMU LUT entry 321 high 0x1A0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT321L LUT321L Graphic MMU LUT entry 321 low 0x1A08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT322H LUT322H Graphic MMU LUT entry 322 high 0x1A14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT322L LUT322L Graphic MMU LUT entry 322 low 0x1A10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT323H LUT323H Graphic MMU LUT entry 323 high 0x1A1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT323L LUT323L Graphic MMU LUT entry 323 low 0x1A18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT324H LUT324H Graphic MMU LUT entry 324 high 0x1A24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT324L LUT324L Graphic MMU LUT entry 324 low 0x1A20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT325H LUT325H Graphic MMU LUT entry 325 high 0x1A2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT325L LUT325L Graphic MMU LUT entry 325 low 0x1A28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT326H LUT326H Graphic MMU LUT entry 326 high 0x1A34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT326L LUT326L Graphic MMU LUT entry 326 low 0x1A30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT327H LUT327H Graphic MMU LUT entry 327 high 0x1A3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT327L LUT327L Graphic MMU LUT entry 327 low 0x1A38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT328H LUT328H Graphic MMU LUT entry 328 high 0x1A44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT328L LUT328L Graphic MMU LUT entry 328 low 0x1A40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT329H LUT329H Graphic MMU LUT entry 329 high 0x1A4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT329L LUT329L Graphic MMU LUT entry 329 low 0x1A48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT32H LUT32H Graphic MMU LUT entry 32 high 0x1104 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT32L LUT32L Graphic MMU LUT entry 32 low 0x1100 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT330H LUT330H Graphic MMU LUT entry 330 high 0x1A54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT330L LUT330L Graphic MMU LUT entry 330 low 0x1A50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT331H LUT331H Graphic MMU LUT entry 331 high 0x1A5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT331L LUT331L Graphic MMU LUT entry 331 low 0x1A58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT332H LUT332H Graphic MMU LUT entry 332 high 0x1A64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT332L LUT332L Graphic MMU LUT entry 332 low 0x1A60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT333H LUT333H Graphic MMU LUT entry 333 high 0x1A6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT333L LUT333L Graphic MMU LUT entry 333 low 0x1A68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT334H LUT334H Graphic MMU LUT entry 334 high 0x1A74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT334L LUT334L Graphic MMU LUT entry 334 low 0x1A70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT335H LUT335H Graphic MMU LUT entry 335 high 0x1A7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT335L LUT335L Graphic MMU LUT entry 335 low 0x1A78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT336H LUT336H Graphic MMU LUT entry 336 high 0x1A84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT336L LUT336L Graphic MMU LUT entry 336 low 0x1A80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT337H LUT337H Graphic MMU LUT entry 337 high 0x1A8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT337L LUT337L Graphic MMU LUT entry 337 low 0x1A88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT338H LUT338H Graphic MMU LUT entry 338 high 0x1A94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT338L LUT338L Graphic MMU LUT entry 338 low 0x1A90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT339H LUT339H Graphic MMU LUT entry 339 high 0x1A9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT339L LUT339L Graphic MMU LUT entry 339 low 0x1A98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT33H LUT33H Graphic MMU LUT entry 33 high 0x110C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT33L LUT33L Graphic MMU LUT entry 33 low 0x1108 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT340H LUT340H Graphic MMU LUT entry 340 high 0x1AA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT340L LUT340L Graphic MMU LUT entry 340 low 0x1AA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT341H LUT341H Graphic MMU LUT entry 341 high 0x1AAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT341L LUT341L Graphic MMU LUT entry 341 low 0x1AA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT342H LUT342H Graphic MMU LUT entry 342 high 0x1AB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT342L LUT342L Graphic MMU LUT entry 342 low 0x1AB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT343H LUT343H Graphic MMU LUT entry 343 high 0x1ABC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT343L LUT343L Graphic MMU LUT entry 343 low 0x1AB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT344H LUT344H Graphic MMU LUT entry 344 high 0x1AC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT344L LUT344L Graphic MMU LUT entry 344 low 0x1AC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT345H LUT345H Graphic MMU LUT entry 345 high 0x1ACC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT345L LUT345L Graphic MMU LUT entry 345 low 0x1AC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT346H LUT346H Graphic MMU LUT entry 346 high 0x1AD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT346L LUT346L Graphic MMU LUT entry 346 low 0x1AD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT347H LUT347H Graphic MMU LUT entry 347 high 0x1ADC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT347L LUT347L Graphic MMU LUT entry 347 low 0x1AD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT348H LUT348H Graphic MMU LUT entry 348 high 0x1AE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT348L LUT348L Graphic MMU LUT entry 348 low 0x1AE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT349H LUT349H Graphic MMU LUT entry 349 high 0x1AEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT349L LUT349L Graphic MMU LUT entry 349 low 0x1AE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT34H LUT34H Graphic MMU LUT entry 34 high 0x1114 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT34L LUT34L Graphic MMU LUT entry 34 low 0x1110 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT350H LUT350H Graphic MMU LUT entry 350 high 0x1AF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT350L LUT350L Graphic MMU LUT entry 350 low 0x1AF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT351H LUT351H Graphic MMU LUT entry 351 high 0x1AFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT351L LUT351L Graphic MMU LUT entry 351 low 0x1AF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT352H LUT352H Graphic MMU LUT entry 352 high 0x1B04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT352L LUT352L Graphic MMU LUT entry 352 low 0x1B00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT353H LUT353H Graphic MMU LUT entry 353 high 0x1B0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT353L LUT353L Graphic MMU LUT entry 353 low 0x1B08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT354H LUT354H Graphic MMU LUT entry 354 high 0x1B14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT354L LUT354L Graphic MMU LUT entry 354 low 0x1B10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT355H LUT355H Graphic MMU LUT entry 355 high 0x1B1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT355L LUT355L Graphic MMU LUT entry 355 low 0x1B18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT356H LUT356H Graphic MMU LUT entry 356 high 0x1B24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT356L LUT356L Graphic MMU LUT entry 356 low 0x1B20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT357H LUT357H Graphic MMU LUT entry 357 high 0x1B2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT357L LUT357L Graphic MMU LUT entry 357 low 0x1B28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT358H LUT358H Graphic MMU LUT entry 358 high 0x1B34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT358L LUT358L Graphic MMU LUT entry 358 low 0x1B30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT359H LUT359H Graphic MMU LUT entry 359 high 0x1B3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT359L LUT359L Graphic MMU LUT entry 359 low 0x1B38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT35H LUT35H Graphic MMU LUT entry 35 high 0x111C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT35L LUT35L Graphic MMU LUT entry 35 low 0x1118 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT360H LUT360H Graphic MMU LUT entry 360 high 0x1B44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT360L LUT360L Graphic MMU LUT entry 360 low 0x1B40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT361H LUT361H Graphic MMU LUT entry 361 high 0x1B4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT361L LUT361L Graphic MMU LUT entry 361 low 0x1B48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT362H LUT362H Graphic MMU LUT entry 362 high 0x1B54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT362L LUT362L Graphic MMU LUT entry 362 low 0x1B50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT363H LUT363H Graphic MMU LUT entry 363 high 0x1B5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT363L LUT363L Graphic MMU LUT entry 363 low 0x1B58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT364H LUT364H Graphic MMU LUT entry 364 high 0x1B64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT364L LUT364L Graphic MMU LUT entry 364 low 0x1B60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT365H LUT365H Graphic MMU LUT entry 365 high 0x1B6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT365L LUT365L Graphic MMU LUT entry 365 low 0x1B68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT366H LUT366H Graphic MMU LUT entry 366 high 0x1B74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT366L LUT366L Graphic MMU LUT entry 366 low 0x1B70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT367H LUT367H Graphic MMU LUT entry 367 high 0x1B7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT367L LUT367L Graphic MMU LUT entry 367 low 0x1B78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT368H LUT368H Graphic MMU LUT entry 368 high 0x1B84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT368L LUT368L Graphic MMU LUT entry 368 low 0x1B80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT369H LUT369H Graphic MMU LUT entry 369 high 0x1B8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT369L LUT369L Graphic MMU LUT entry 369 low 0x1B88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT36H LUT36H Graphic MMU LUT entry 36 high 0x1124 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT36L LUT36L Graphic MMU LUT entry 36 low 0x1120 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT370H LUT370H Graphic MMU LUT entry 370 high 0x1B94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT370L LUT370L Graphic MMU LUT entry 370 low 0x1B90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT371H LUT371H Graphic MMU LUT entry 371 high 0x1B9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT371L LUT371L Graphic MMU LUT entry 371 low 0x1B98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT372H LUT372H Graphic MMU LUT entry 372 high 0x1BA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT372L LUT372L Graphic MMU LUT entry 372 low 0x1BA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT373H LUT373H Graphic MMU LUT entry 373 high 0x1BAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT373L LUT373L Graphic MMU LUT entry 373 low 0x1BA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT374H LUT374H Graphic MMU LUT entry 374 high 0x1BB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT374L LUT374L Graphic MMU LUT entry 374 low 0x1BB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT375H LUT375H Graphic MMU LUT entry 375 high 0x1BBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT375L LUT375L Graphic MMU LUT entry 375 low 0x1BB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT376H LUT376H Graphic MMU LUT entry 376 high 0x1BC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT376L LUT376L Graphic MMU LUT entry 376 low 0x1BC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT377H LUT377H Graphic MMU LUT entry 377 high 0x1BCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT377L LUT377L Graphic MMU LUT entry 377 low 0x1BC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT378H LUT378H Graphic MMU LUT entry 378 high 0x1BD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT378L LUT378L Graphic MMU LUT entry 378 low 0x1BD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT379H LUT379H Graphic MMU LUT entry 379 high 0x1BDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT379L LUT379L Graphic MMU LUT entry 379 low 0x1BD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT37H LUT37H Graphic MMU LUT entry 37 high 0x112C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT37L LUT37L Graphic MMU LUT entry 37 low 0x1128 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT380H LUT380H Graphic MMU LUT entry 380 high 0x1BE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT380L LUT380L Graphic MMU LUT entry 380 low 0x1BE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT381H LUT381H Graphic MMU LUT entry 381 high 0x1BEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT381L LUT381L Graphic MMU LUT entry 381 low 0x1BE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT382H LUT382H Graphic MMU LUT entry 382 high 0x1BF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT382L LUT382L Graphic MMU LUT entry 382 low 0x1BF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT383H LUT383H Graphic MMU LUT entry 383 high 0x1BFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT383L LUT383L Graphic MMU LUT entry 383 low 0x1BF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT384H LUT384H Graphic MMU LUT entry 384 high 0x1C04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT384L LUT384L Graphic MMU LUT entry 384 low 0x1C00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT385H LUT385H Graphic MMU LUT entry 385 high 0x1C0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT385L LUT385L Graphic MMU LUT entry 385 low 0x1C08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT386H LUT386H Graphic MMU LUT entry 386 high 0x1C14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT386L LUT386L Graphic MMU LUT entry 386 low 0x1C10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT387H LUT387H Graphic MMU LUT entry 387 high 0x1C1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT387L LUT387L Graphic MMU LUT entry 387 low 0x1C18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT388H LUT388H Graphic MMU LUT entry 388 high 0x1C24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT388L LUT388L Graphic MMU LUT entry 388 low 0x1C20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT389H LUT389H Graphic MMU LUT entry 389 high 0x1C2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT389L LUT389L Graphic MMU LUT entry 389 low 0x1C28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT38H LUT38H Graphic MMU LUT entry 38 high 0x1134 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT38L LUT38L Graphic MMU LUT entry 38 low 0x1130 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT390H LUT390H Graphic MMU LUT entry 390 high 0x1C34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT390L LUT390L Graphic MMU LUT entry 390 low 0x1C30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT391H LUT391H Graphic MMU LUT entry 391 high 0x1C3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT391L LUT391L Graphic MMU LUT entry 391 low 0x1C38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT392H LUT392H Graphic MMU LUT entry 392 high 0x1C44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT392L LUT392L Graphic MMU LUT entry 392 low 0x1C40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT393H LUT393H Graphic MMU LUT entry 393 high 0x1C4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT393L LUT393L Graphic MMU LUT entry 393 low 0x1C48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT394H LUT394H Graphic MMU LUT entry 394 high 0x1C54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT394L LUT394L Graphic MMU LUT entry 394 low 0x1C50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT395H LUT395H Graphic MMU LUT entry 395 high 0x1C5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT395L LUT395L Graphic MMU LUT entry 395 low 0x1C58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT396H LUT396H Graphic MMU LUT entry 396 high 0x1C64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT396L LUT396L Graphic MMU LUT entry 396 low 0x1C60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT397H LUT397H Graphic MMU LUT entry 397 high 0x1C6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT397L LUT397L Graphic MMU LUT entry 397 low 0x1C68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT398H LUT398H Graphic MMU LUT entry 398 high 0x1C74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT398L LUT398L Graphic MMU LUT entry 398 low 0x1C70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT399H LUT399H Graphic MMU LUT entry 399 high 0x1C7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT399L LUT399L Graphic MMU LUT entry 399 low 0x1C78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT39H LUT39H Graphic MMU LUT entry 39 high 0x113C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT39L LUT39L Graphic MMU LUT entry 39 low 0x1138 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT3H LUT3H Graphic MMU LUT entry 3 high 0x101C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT3L LUT3L Graphic MMU LUT entry 3 low 0x1018 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT400H LUT400H Graphic MMU LUT entry 400 high 0x1C84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT400L LUT400L Graphic MMU LUT entry 400 low 0x1C80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT401H LUT401H Graphic MMU LUT entry 401 high 0x1C8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT401L LUT401L Graphic MMU LUT entry 401 low 0x1C88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT402H LUT402H Graphic MMU LUT entry 402 high 0x1C94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT402L LUT402L Graphic MMU LUT entry 402 low 0x1C90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT403H LUT403H Graphic MMU LUT entry 403 high 0x1C9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT403L LUT403L Graphic MMU LUT entry 403 low 0x1C98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT404H LUT404H Graphic MMU LUT entry 404 high 0x1CA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT404L LUT404L Graphic MMU LUT entry 404 low 0x1CA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT405H LUT405H Graphic MMU LUT entry 405 high 0x1CAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT405L LUT405L Graphic MMU LUT entry 405 low 0x1CA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT406H LUT406H Graphic MMU LUT entry 406 high 0x1CB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT406L LUT406L Graphic MMU LUT entry 406 low 0x1CB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT407H LUT407H Graphic MMU LUT entry 407 high 0x1CBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT407L LUT407L Graphic MMU LUT entry 407 low 0x1CB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT408H LUT408H Graphic MMU LUT entry 408 high 0x1CC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT408L LUT408L Graphic MMU LUT entry 408 low 0x1CC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT409H LUT409H Graphic MMU LUT entry 409 high 0x1CCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT409L LUT409L Graphic MMU LUT entry 409 low 0x1CC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT40H LUT40H Graphic MMU LUT entry 40 high 0x1144 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT40L LUT40L Graphic MMU LUT entry 40 low 0x1140 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT410H LUT410H Graphic MMU LUT entry 410 high 0x1CD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT410L LUT410L Graphic MMU LUT entry 410 low 0x1CD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT411H LUT411H Graphic MMU LUT entry 411 high 0x1CDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT411L LUT411L Graphic MMU LUT entry 411 low 0x1CD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT412H LUT412H Graphic MMU LUT entry 412 high 0x1CE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT412L LUT412L Graphic MMU LUT entry 412 low 0x1CE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT413H LUT413H Graphic MMU LUT entry 413 high 0x1CEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT413L LUT413L Graphic MMU LUT entry 413 low 0x1CE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT414H LUT414H Graphic MMU LUT entry 414 high 0x1CF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT414L LUT414L Graphic MMU LUT entry 414 low 0x1CF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT415H LUT415H Graphic MMU LUT entry 415 high 0x1CFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT415L LUT415L Graphic MMU LUT entry 415 low 0x1CF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT416H LUT416H Graphic MMU LUT entry 416 high 0x1D04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT416L LUT416L Graphic MMU LUT entry 416 low 0x1D00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT417H LUT417H Graphic MMU LUT entry 417 high 0x1D0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT417L LUT417L Graphic MMU LUT entry 417 low 0x1D08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT418H LUT418H Graphic MMU LUT entry 418 high 0x1D14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT418L LUT418L Graphic MMU LUT entry 418 low 0x1D10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT419H LUT419H Graphic MMU LUT entry 419 high 0x1D1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT419L LUT419L Graphic MMU LUT entry 419 low 0x1D18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT41H LUT41H Graphic MMU LUT entry 41 high 0x114C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT41L LUT41L Graphic MMU LUT entry 41 low 0x1148 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT420H LUT420H Graphic MMU LUT entry 420 high 0x1D24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT420L LUT420L Graphic MMU LUT entry 420 low 0x1D20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT421H LUT421H Graphic MMU LUT entry 421 high 0x1D2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT421L LUT421L Graphic MMU LUT entry 421 low 0x1D28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT422H LUT422H Graphic MMU LUT entry 422 high 0x1D34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT422L LUT422L Graphic MMU LUT entry 422 low 0x1D30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT423H LUT423H Graphic MMU LUT entry 423 high 0x1D3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT423L LUT423L Graphic MMU LUT entry 423 low 0x1D38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT424H LUT424H Graphic MMU LUT entry 424 high 0x1D44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT424L LUT424L Graphic MMU LUT entry 424 low 0x1D40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT425H LUT425H Graphic MMU LUT entry 425 high 0x1D4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT425L LUT425L Graphic MMU LUT entry 425 low 0x1D48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT426H LUT426H Graphic MMU LUT entry 426 high 0x1D54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT426L LUT426L Graphic MMU LUT entry 426 low 0x1D50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT427H LUT427H Graphic MMU LUT entry 427 high 0x1D5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT427L LUT427L Graphic MMU LUT entry 427 low 0x1D58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT428H LUT428H Graphic MMU LUT entry 428 high 0x1D64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT428L LUT428L Graphic MMU LUT entry 428 low 0x1D60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT429H LUT429H Graphic MMU LUT entry 429 high 0x1D6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT429L LUT429L Graphic MMU LUT entry 429 low 0x1D68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT42H LUT42H Graphic MMU LUT entry 42 high 0x1154 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT42L LUT42L Graphic MMU LUT entry 42 low 0x1150 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT430H LUT430H Graphic MMU LUT entry 430 high 0x1D74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT430L LUT430L Graphic MMU LUT entry 430 low 0x1D70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT431H LUT431H Graphic MMU LUT entry 431 high 0x1D7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT431L LUT431L Graphic MMU LUT entry 431 low 0x1D78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT432H LUT432H Graphic MMU LUT entry 432 high 0x1D84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT432L LUT432L Graphic MMU LUT entry 432 low 0x1D80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT433H LUT433H Graphic MMU LUT entry 433 high 0x1D8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT433L LUT433L Graphic MMU LUT entry 433 low 0x1D88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT434H LUT434H Graphic MMU LUT entry 434 high 0x1D94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT434L LUT434L Graphic MMU LUT entry 434 low 0x1D90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT435H LUT435H Graphic MMU LUT entry 435 high 0x1D9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT435L LUT435L Graphic MMU LUT entry 435 low 0x1D98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT436H LUT436H Graphic MMU LUT entry 436 high 0x1DA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT436L LUT436L Graphic MMU LUT entry 436 low 0x1DA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT437H LUT437H Graphic MMU LUT entry 437 high 0x1DAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT437L LUT437L Graphic MMU LUT entry 437 low 0x1DA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT438H LUT438H Graphic MMU LUT entry 438 high 0x1DB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT438L LUT438L Graphic MMU LUT entry 438 low 0x1DB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT439H LUT439H Graphic MMU LUT entry 439 high 0x1DBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT439L LUT439L Graphic MMU LUT entry 439 low 0x1DB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT43H LUT43H Graphic MMU LUT entry 43 high 0x115C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT43L LUT43L Graphic MMU LUT entry 43 low 0x1158 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT440H LUT440H Graphic MMU LUT entry 440 high 0x1DC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT440L LUT440L Graphic MMU LUT entry 440 low 0x1DC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT441H LUT441H Graphic MMU LUT entry 441 high 0x1DCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT441L LUT441L Graphic MMU LUT entry 441 low 0x1DC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT442H LUT442H Graphic MMU LUT entry 442 high 0x1DD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT442L LUT442L Graphic MMU LUT entry 442 low 0x1DD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT443H LUT443H Graphic MMU LUT entry 443 high 0x1DDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT443L LUT443L Graphic MMU LUT entry 443 low 0x1DD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT444H LUT444H Graphic MMU LUT entry 444 high 0x1DE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT444L LUT444L Graphic MMU LUT entry 444 low 0x1DE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT445H LUT445H Graphic MMU LUT entry 445 high 0x1DEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT445L LUT445L Graphic MMU LUT entry 445 low 0x1DE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT446H LUT446H Graphic MMU LUT entry 446 high 0x1DF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT446L LUT446L Graphic MMU LUT entry 446 low 0x1DF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT447H LUT447H Graphic MMU LUT entry 447 high 0x1DFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT447L LUT447L Graphic MMU LUT entry 447 low 0x1DF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT448H LUT448H Graphic MMU LUT entry 448 high 0x1E04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT448L LUT448L Graphic MMU LUT entry 448 low 0x1E00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT449H LUT449H Graphic MMU LUT entry 449 high 0x1E0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT449L LUT449L Graphic MMU LUT entry 449 low 0x1E08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT44H LUT44H Graphic MMU LUT entry 44 high 0x1164 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT44L LUT44L Graphic MMU LUT entry 44 low 0x1160 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT450H LUT450H Graphic MMU LUT entry 450 high 0x1E14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT450L LUT450L Graphic MMU LUT entry 450 low 0x1E10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT451H LUT451H Graphic MMU LUT entry 451 high 0x1E1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT451L LUT451L Graphic MMU LUT entry 451 low 0x1E18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT452H LUT452H Graphic MMU LUT entry 452 high 0x1E24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT452L LUT452L Graphic MMU LUT entry 452 low 0x1E20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT453H LUT453H Graphic MMU LUT entry 453 high 0x1E2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT453L LUT453L Graphic MMU LUT entry 453 low 0x1E28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT454H LUT454H Graphic MMU LUT entry 454 high 0x1E34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT454L LUT454L Graphic MMU LUT entry 454 low 0x1E30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT455H LUT455H Graphic MMU LUT entry 455 high 0x1E3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT455L LUT455L Graphic MMU LUT entry 455 low 0x1E38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT456H LUT456H Graphic MMU LUT entry 456 high 0x1E44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT456L LUT456L Graphic MMU LUT entry 456 low 0x1E40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT457H LUT457H Graphic MMU LUT entry 457 high 0x1E4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT457L LUT457L Graphic MMU LUT entry 457 low 0x1E48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT458H LUT458H Graphic MMU LUT entry 458 high 0x1E54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT458L LUT458L Graphic MMU LUT entry 458 low 0x1E50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT459H LUT459H Graphic MMU LUT entry 459 high 0x1E5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT459L LUT459L Graphic MMU LUT entry 459 low 0x1E58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT45H LUT45H Graphic MMU LUT entry 45 high 0x116C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT45L LUT45L Graphic MMU LUT entry 45 low 0x1168 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT460H LUT460H Graphic MMU LUT entry 460 high 0x1E64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT460L LUT460L Graphic MMU LUT entry 460 low 0x1E60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT461H LUT461H Graphic MMU LUT entry 461 high 0x1E6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT461L LUT461L Graphic MMU LUT entry 461 low 0x1E68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT462H LUT462H Graphic MMU LUT entry 462 high 0x1E74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT462L LUT462L Graphic MMU LUT entry 462 low 0x1E70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT463H LUT463H Graphic MMU LUT entry 463 high 0x1E7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT463L LUT463L Graphic MMU LUT entry 463 low 0x1E78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT464H LUT464H Graphic MMU LUT entry 464 high 0x1E84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT464L LUT464L Graphic MMU LUT entry 464 low 0x1E80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT465H LUT465H Graphic MMU LUT entry 465 high 0x1E8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT465L LUT465L Graphic MMU LUT entry 465 low 0x1E88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT466H LUT466H Graphic MMU LUT entry 466 high 0x1E94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT466L LUT466L Graphic MMU LUT entry 466 low 0x1E90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT467H LUT467H Graphic MMU LUT entry 467 high 0x1E9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT467L LUT467L Graphic MMU LUT entry 467 low 0x1E98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT468H LUT468H Graphic MMU LUT entry 468 high 0x1EA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT468L LUT468L Graphic MMU LUT entry 468 low 0x1EA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT469H LUT469H Graphic MMU LUT entry 469 high 0x1EAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT469L LUT469L Graphic MMU LUT entry 469 low 0x1EA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT46H LUT46H Graphic MMU LUT entry 46 high 0x1174 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT46L LUT46L Graphic MMU LUT entry 46 low 0x1170 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT470H LUT470H Graphic MMU LUT entry 470 high 0x1EB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT470L LUT470L Graphic MMU LUT entry 470 low 0x1EB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT471H LUT471H Graphic MMU LUT entry 471 high 0x1EBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT471L LUT471L Graphic MMU LUT entry 471 low 0x1EB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT472H LUT472H Graphic MMU LUT entry 472 high 0x1EC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT472L LUT472L Graphic MMU LUT entry 472 low 0x1EC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT473H LUT473H Graphic MMU LUT entry 473 high 0x1ECC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT473L LUT473L Graphic MMU LUT entry 473 low 0x1EC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT474H LUT474H Graphic MMU LUT entry 474 high 0x1ED4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT474L LUT474L Graphic MMU LUT entry 474 low 0x1ED0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT475H LUT475H Graphic MMU LUT entry 475 high 0x1EDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT475L LUT475L Graphic MMU LUT entry 475 low 0x1ED8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT476H LUT476H Graphic MMU LUT entry 476 high 0x1EE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT476L LUT476L Graphic MMU LUT entry 476 low 0x1EE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT477H LUT477H Graphic MMU LUT entry 477 high 0x1EEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT477L LUT477L Graphic MMU LUT entry 477 low 0x1EE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT478H LUT478H Graphic MMU LUT entry 478 high 0x1EF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT478L LUT478L Graphic MMU LUT entry 478 low 0x1EF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT479H LUT479H Graphic MMU LUT entry 479 high 0x1EFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT479L LUT479L Graphic MMU LUT entry 479 low 0x1EF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT47H LUT47H Graphic MMU LUT entry 47 high 0x117C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT47L LUT47L Graphic MMU LUT entry 47 low 0x1178 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT480H LUT480H Graphic MMU LUT entry 480 high 0x1F04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT480L LUT480L Graphic MMU LUT entry 480 low 0x1F00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT481H LUT481H Graphic MMU LUT entry 481 high 0x1F0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT481L LUT481L Graphic MMU LUT entry 481 low 0x1F08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT482H LUT482H Graphic MMU LUT entry 482 high 0x1F14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT482L LUT482L Graphic MMU LUT entry 482 low 0x1F10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT483H LUT483H Graphic MMU LUT entry 483 high 0x1F1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT483L LUT483L Graphic MMU LUT entry 483 low 0x1F18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT484H LUT484H Graphic MMU LUT entry 484 high 0x1F24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT484L LUT484L Graphic MMU LUT entry 484 low 0x1F20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT485H LUT485H Graphic MMU LUT entry 485 high 0x1F2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT485L LUT485L Graphic MMU LUT entry 485 low 0x1F28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT486H LUT486H Graphic MMU LUT entry 486 high 0x1F34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT486L LUT486L Graphic MMU LUT entry 486 low 0x1F30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT487H LUT487H Graphic MMU LUT entry 487 high 0x1F3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT487L LUT487L Graphic MMU LUT entry 487 low 0x1F38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT488H LUT488H Graphic MMU LUT entry 488 high 0x1F44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT488L LUT488L Graphic MMU LUT entry 488 low 0x1F40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT489H LUT489H Graphic MMU LUT entry 489 high 0x1F4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT489L LUT489L Graphic MMU LUT entry 489 low 0x1F48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT48H LUT48H Graphic MMU LUT entry 48 high 0x1184 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT48L LUT48L Graphic MMU LUT entry 48 low 0x1180 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT490H LUT490H Graphic MMU LUT entry 490 high 0x1F54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT490L LUT490L Graphic MMU LUT entry 490 low 0x1F50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT491H LUT491H Graphic MMU LUT entry 491 high 0x1F5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT491L LUT491L Graphic MMU LUT entry 491 low 0x1F58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT492H LUT492H Graphic MMU LUT entry 492 high 0x1F64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT492L LUT492L Graphic MMU LUT entry 492 low 0x1F60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT493H LUT493H Graphic MMU LUT entry 493 high 0x1F6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT493L LUT493L Graphic MMU LUT entry 493 low 0x1F68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT494H LUT494H Graphic MMU LUT entry 494 high 0x1F74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT494L LUT494L Graphic MMU LUT entry 494 low 0x1F70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT495H LUT495H Graphic MMU LUT entry 495 high 0x1F7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT495L LUT495L Graphic MMU LUT entry 495 low 0x1F78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT496H LUT496H Graphic MMU LUT entry 496 high 0x1F84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT496L LUT496L Graphic MMU LUT entry 496 low 0x1F80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT497H LUT497H Graphic MMU LUT entry 497 high 0x1F8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT497L LUT497L Graphic MMU LUT entry 497 low 0x1F88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT498H LUT498H Graphic MMU LUT entry 498 high 0x1F94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT498L LUT498L Graphic MMU LUT entry 498 low 0x1F90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT499H LUT499H Graphic MMU LUT entry 499 high 0x1F9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT499L LUT499L Graphic MMU LUT entry 499 low 0x1F98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT49H LUT49H Graphic MMU LUT entry 49 high 0x118C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT49L LUT49L Graphic MMU LUT entry 49 low 0x1188 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT4H LUT4H Graphic MMU LUT entry 4 high 0x1024 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT4L LUT4L Graphic MMU LUT entry 4 low 0x1020 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT500H LUT500H Graphic MMU LUT entry 500 high 0x1FA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT500L LUT500L Graphic MMU LUT entry 500 low 0x1FA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT501H LUT501H Graphic MMU LUT entry 501 high 0x1FAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT501L LUT501L Graphic MMU LUT entry 501 low 0x1FA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT502H LUT502H Graphic MMU LUT entry 502 high 0x1FB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT502L LUT502L Graphic MMU LUT entry 502 low 0x1FB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT503H LUT503H Graphic MMU LUT entry 503 high 0x1FBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT503L LUT503L Graphic MMU LUT entry 503 low 0x1FB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT504H LUT504H Graphic MMU LUT entry 504 high 0x1FC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT504L LUT504L Graphic MMU LUT entry 504 low 0x1FC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT505H LUT505H Graphic MMU LUT entry 505 high 0x1FCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT505L LUT505L Graphic MMU LUT entry 505 low 0x1FC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT506H LUT506H Graphic MMU LUT entry 506 high 0x1FD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT506L LUT506L Graphic MMU LUT entry 506 low 0x1FD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT507H LUT507H Graphic MMU LUT entry 507 high 0x1FDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT507L LUT507L Graphic MMU LUT entry 507 low 0x1FD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT508H LUT508H Graphic MMU LUT entry 508 high 0x1FE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT508L LUT508L Graphic MMU LUT entry 508 low 0x1FE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT509H LUT509H Graphic MMU LUT entry 509 high 0x1FEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT509L LUT509L Graphic MMU LUT entry 509 low 0x1FE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT50H LUT50H Graphic MMU LUT entry 50 high 0x1194 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT50L LUT50L Graphic MMU LUT entry 50 low 0x1190 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT510H LUT510H Graphic MMU LUT entry 510 high 0x1FF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT510L LUT510L Graphic MMU LUT entry 510 low 0x1FF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT511H LUT511H Graphic MMU LUT entry 511 high 0x1FFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT511L LUT511L Graphic MMU LUT entry 511 low 0x1FF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT512H LUT512H Graphic MMU LUT entry 512 high 0x2004 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT512L LUT512L Graphic MMU LUT entry 512 low 0x2000 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT513H LUT513H Graphic MMU LUT entry 513 high 0x200C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT513L LUT513L Graphic MMU LUT entry 513 low 0x2008 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT514H LUT514H Graphic MMU LUT entry 514 high 0x2014 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT514L LUT514L Graphic MMU LUT entry 514 low 0x2010 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT515H LUT515H Graphic MMU LUT entry 515 high 0x201C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT515L LUT515L Graphic MMU LUT entry 515 low 0x2018 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT516H LUT516H Graphic MMU LUT entry 516 high 0x2024 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT516L LUT516L Graphic MMU LUT entry 516 low 0x2020 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT517H LUT517H Graphic MMU LUT entry 517 high 0x202C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT517L LUT517L Graphic MMU LUT entry 517 low 0x2028 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT518H LUT518H Graphic MMU LUT entry 518 high 0x2034 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT518L LUT518L Graphic MMU LUT entry 518 low 0x2030 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT519H LUT519H Graphic MMU LUT entry 519 high 0x203C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT519L LUT519L Graphic MMU LUT entry 519 low 0x2038 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT51H LUT51H Graphic MMU LUT entry 51 high 0x119C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT51L LUT51L Graphic MMU LUT entry 51 low 0x1198 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT520H LUT520H Graphic MMU LUT entry 520 high 0x2044 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT520L LUT520L Graphic MMU LUT entry 520 low 0x2040 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT521H LUT521H Graphic MMU LUT entry 521 high 0x204C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT521L LUT521L Graphic MMU LUT entry 521 low 0x2048 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT522H LUT522H Graphic MMU LUT entry 522 high 0x2054 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT522L LUT522L Graphic MMU LUT entry 522 low 0x2050 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT523H LUT523H Graphic MMU LUT entry 523 high 0x205C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT523L LUT523L Graphic MMU LUT entry 523 low 0x2058 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT524H LUT524H Graphic MMU LUT entry 524 high 0x2064 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT524L LUT524L Graphic MMU LUT entry 524 low 0x2060 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT525H LUT525H Graphic MMU LUT entry 525 high 0x206C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT525L LUT525L Graphic MMU LUT entry 525 low 0x2068 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT526H LUT526H Graphic MMU LUT entry 526 high 0x2074 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT526L LUT526L Graphic MMU LUT entry 526 low 0x2070 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT527H LUT527H Graphic MMU LUT entry 527 high 0x207C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT527L LUT527L Graphic MMU LUT entry 527 low 0x2078 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT528H LUT528H Graphic MMU LUT entry 528 high 0x2084 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT528L LUT528L Graphic MMU LUT entry 528 low 0x2080 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT529H LUT529H Graphic MMU LUT entry 529 high 0x208C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT529L LUT529L Graphic MMU LUT entry 529 low 0x2088 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT52H LUT52H Graphic MMU LUT entry 52 high 0x11A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT52L LUT52L Graphic MMU LUT entry 52 low 0x11A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT530H LUT530H Graphic MMU LUT entry 530 high 0x2094 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT530L LUT530L Graphic MMU LUT entry 530 low 0x2090 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT531H LUT531H Graphic MMU LUT entry 531 high 0x209C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT531L LUT531L Graphic MMU LUT entry 531 low 0x2098 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT532H LUT532H Graphic MMU LUT entry 532 high 0x20A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT532L LUT532L Graphic MMU LUT entry 532 low 0x20A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT533H LUT533H Graphic MMU LUT entry 533 high 0x20AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT533L LUT533L Graphic MMU LUT entry 533 low 0x20A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT534H LUT534H Graphic MMU LUT entry 534 high 0x20B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT534L LUT534L Graphic MMU LUT entry 534 low 0x20B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT535H LUT535H Graphic MMU LUT entry 535 high 0x20BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT535L LUT535L Graphic MMU LUT entry 535 low 0x20B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT536H LUT536H Graphic MMU LUT entry 536 high 0x20C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT536L LUT536L Graphic MMU LUT entry 536 low 0x20C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT537H LUT537H Graphic MMU LUT entry 537 high 0x20CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT537L LUT537L Graphic MMU LUT entry 537 low 0x20C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT538H LUT538H Graphic MMU LUT entry 538 high 0x20D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT538L LUT538L Graphic MMU LUT entry 538 low 0x20D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT539H LUT539H Graphic MMU LUT entry 539 high 0x20DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT539L LUT539L Graphic MMU LUT entry 539 low 0x20D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT53H LUT53H Graphic MMU LUT entry 53 high 0x11AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT53L LUT53L Graphic MMU LUT entry 53 low 0x11A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT540H LUT540H Graphic MMU LUT entry 540 high 0x20E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT540L LUT540L Graphic MMU LUT entry 540 low 0x20E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT541H LUT541H Graphic MMU LUT entry 541 high 0x20EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT541L LUT541L Graphic MMU LUT entry 541 low 0x20E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT542H LUT542H Graphic MMU LUT entry 542 high 0x20F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT542L LUT542L Graphic MMU LUT entry 542 low 0x20F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT543H LUT543H Graphic MMU LUT entry 543 high 0x20FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT543L LUT543L Graphic MMU LUT entry 543 low 0x20F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT544H LUT544H Graphic MMU LUT entry 544 high 0x2104 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT544L LUT544L Graphic MMU LUT entry 544 low 0x2100 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT545H LUT545H Graphic MMU LUT entry 545 high 0x210C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT545L LUT545L Graphic MMU LUT entry 545 low 0x2108 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT546H LUT546H Graphic MMU LUT entry 546 high 0x2114 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT546L LUT546L Graphic MMU LUT entry 546 low 0x2110 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT547H LUT547H Graphic MMU LUT entry 547 high 0x211C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT547L LUT547L Graphic MMU LUT entry 547 low 0x2118 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT548H LUT548H Graphic MMU LUT entry 548 high 0x2124 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT548L LUT548L Graphic MMU LUT entry 548 low 0x2120 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT549H LUT549H Graphic MMU LUT entry 549 high 0x212C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT549L LUT549L Graphic MMU LUT entry 549 low 0x2128 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT54H LUT54H Graphic MMU LUT entry 54 high 0x11B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT54L LUT54L Graphic MMU LUT entry 54 low 0x11B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT550H LUT550H Graphic MMU LUT entry 550 high 0x2134 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT550L LUT550L Graphic MMU LUT entry 550 low 0x2130 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT551H LUT551H Graphic MMU LUT entry 551 high 0x213C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT551L LUT551L Graphic MMU LUT entry 551 low 0x2138 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT552H LUT552H Graphic MMU LUT entry 552 high 0x2144 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT552L LUT552L Graphic MMU LUT entry 552 low 0x2140 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT553H LUT553H Graphic MMU LUT entry 553 high 0x214C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT553L LUT553L Graphic MMU LUT entry 553 low 0x2148 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT554H LUT554H Graphic MMU LUT entry 554 high 0x2154 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT554L LUT554L Graphic MMU LUT entry 554 low 0x2150 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT555H LUT555H Graphic MMU LUT entry 555 high 0x215C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT555L LUT555L Graphic MMU LUT entry 555 low 0x2158 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT556H LUT556H Graphic MMU LUT entry 556 high 0x2164 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT556L LUT556L Graphic MMU LUT entry 556 low 0x2160 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT557H LUT557H Graphic MMU LUT entry 557 high 0x216C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT557L LUT557L Graphic MMU LUT entry 557 low 0x2168 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT558H LUT558H Graphic MMU LUT entry 558 high 0x2174 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT558L LUT558L Graphic MMU LUT entry 558 low 0x2170 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT559H LUT559H Graphic MMU LUT entry 559 high 0x217C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT559L LUT559L Graphic MMU LUT entry 559 low 0x2178 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT55H LUT55H Graphic MMU LUT entry 55 high 0x11BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT55L LUT55L Graphic MMU LUT entry 55 low 0x11B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT560H LUT560H Graphic MMU LUT entry 560 high 0x2184 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT560L LUT560L Graphic MMU LUT entry 560 low 0x2180 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT561H LUT561H Graphic MMU LUT entry 561 high 0x218C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT561L LUT561L Graphic MMU LUT entry 561 low 0x2188 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT562H LUT562H Graphic MMU LUT entry 562 high 0x2194 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT562L LUT562L Graphic MMU LUT entry 562 low 0x2190 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT563H LUT563H Graphic MMU LUT entry 563 high 0x219C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT563L LUT563L Graphic MMU LUT entry 563 low 0x2198 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT564H LUT564H Graphic MMU LUT entry 564 high 0x21A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT564L LUT564L Graphic MMU LUT entry 564 low 0x21A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT565H LUT565H Graphic MMU LUT entry 565 high 0x21AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT565L LUT565L Graphic MMU LUT entry 565 low 0x21A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT566H LUT566H Graphic MMU LUT entry 566 high 0x21B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT566L LUT566L Graphic MMU LUT entry 566 low 0x21B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT567H LUT567H Graphic MMU LUT entry 567 high 0x21BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT567L LUT567L Graphic MMU LUT entry 567 low 0x21B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT568H LUT568H Graphic MMU LUT entry 568 high 0x21C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT568L LUT568L Graphic MMU LUT entry 568 low 0x21C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT569H LUT569H Graphic MMU LUT entry 569 high 0x21CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT569L LUT569L Graphic MMU LUT entry 569 low 0x21C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT56H LUT56H Graphic MMU LUT entry 56 high 0x11C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT56L LUT56L Graphic MMU LUT entry 56 low 0x11C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT570H LUT570H Graphic MMU LUT entry 570 high 0x21D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT570L LUT570L Graphic MMU LUT entry 570 low 0x21D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT571H LUT571H Graphic MMU LUT entry 571 high 0x21DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT571L LUT571L Graphic MMU LUT entry 571 low 0x21D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT572H LUT572H Graphic MMU LUT entry 572 high 0x21E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT572L LUT572L Graphic MMU LUT entry 572 low 0x21E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT573H LUT573H Graphic MMU LUT entry 573 high 0x21EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT573L LUT573L Graphic MMU LUT entry 573 low 0x21E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT574H LUT574H Graphic MMU LUT entry 574 high 0x21F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT574L LUT574L Graphic MMU LUT entry 574 low 0x21F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT575H LUT575H Graphic MMU LUT entry 575 high 0x21FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT575L LUT575L Graphic MMU LUT entry 575 low 0x21F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT576H LUT576H Graphic MMU LUT entry 576 high 0x2204 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT576L LUT576L Graphic MMU LUT entry 576 low 0x2200 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT577H LUT577H Graphic MMU LUT entry 577 high 0x220C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT577L LUT577L Graphic MMU LUT entry 577 low 0x2208 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT578H LUT578H Graphic MMU LUT entry 578 high 0x2214 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT578L LUT578L Graphic MMU LUT entry 578 low 0x2210 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT579H LUT579H Graphic MMU LUT entry 579 high 0x221C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT579L LUT579L Graphic MMU LUT entry 579 low 0x2218 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT57H LUT57H Graphic MMU LUT entry 57 high 0x11CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT57L LUT57L Graphic MMU LUT entry 57 low 0x11C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT580H LUT580H Graphic MMU LUT entry 580 high 0x2224 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT580L LUT580L Graphic MMU LUT entry 580 low 0x2220 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT581H LUT581H Graphic MMU LUT entry 581 high 0x222C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT581L LUT581L Graphic MMU LUT entry 581 low 0x2228 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT582H LUT582H Graphic MMU LUT entry 582 high 0x2234 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT582L LUT582L Graphic MMU LUT entry 582 low 0x2230 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT583H LUT583H Graphic MMU LUT entry 583 high 0x223C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT583L LUT583L Graphic MMU LUT entry 583 low 0x2238 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT584H LUT584H Graphic MMU LUT entry 584 high 0x2244 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT584L LUT584L Graphic MMU LUT entry 584 low 0x2240 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT585H LUT585H Graphic MMU LUT entry 585 high 0x224C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT585L LUT585L Graphic MMU LUT entry 585 low 0x2248 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT586H LUT586H Graphic MMU LUT entry 586 high 0x2254 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT586L LUT586L Graphic MMU LUT entry 586 low 0x2250 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT587H LUT587H Graphic MMU LUT entry 587 high 0x225C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT587L LUT587L Graphic MMU LUT entry 587 low 0x2258 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT588H LUT588H Graphic MMU LUT entry 588 high 0x2264 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT588L LUT588L Graphic MMU LUT entry 588 low 0x2260 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT589H LUT589H Graphic MMU LUT entry 589 high 0x226C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT589L LUT589L Graphic MMU LUT entry 589 low 0x2268 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT58H LUT58H Graphic MMU LUT entry 58 high 0x11D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT58L LUT58L Graphic MMU LUT entry 58 low 0x11D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT590H LUT590H Graphic MMU LUT entry 590 high 0x2274 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT590L LUT590L Graphic MMU LUT entry 590 low 0x2270 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT591H LUT591H Graphic MMU LUT entry 591 high 0x227C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT591L LUT591L Graphic MMU LUT entry 591 low 0x2278 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT592H LUT592H Graphic MMU LUT entry 592 high 0x2284 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT592L LUT592L Graphic MMU LUT entry 592 low 0x2280 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT593H LUT593H Graphic MMU LUT entry 593 high 0x228C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT593L LUT593L Graphic MMU LUT entry 593 low 0x2288 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT594H LUT594H Graphic MMU LUT entry 594 high 0x2294 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT594L LUT594L Graphic MMU LUT entry 594 low 0x2290 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT595H LUT595H Graphic MMU LUT entry 595 high 0x229C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT595L LUT595L Graphic MMU LUT entry 595 low 0x2298 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT596H LUT596H Graphic MMU LUT entry 596 high 0x22A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT596L LUT596L Graphic MMU LUT entry 596 low 0x22A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT597H LUT597H Graphic MMU LUT entry 597 high 0x22AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT597L LUT597L Graphic MMU LUT entry 597 low 0x22A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT598H LUT598H Graphic MMU LUT entry 598 high 0x22B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT598L LUT598L Graphic MMU LUT entry 598 low 0x22B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT599H LUT599H Graphic MMU LUT entry 599 high 0x22BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT599L LUT599L Graphic MMU LUT entry 599 low 0x22B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT59H LUT59H Graphic MMU LUT entry 59 high 0x11DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT59L LUT59L Graphic MMU LUT entry 59 low 0x11D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT5H LUT5H Graphic MMU LUT entry 5 high 0x102C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT5L LUT5L Graphic MMU LUT entry 5 low 0x1028 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT600H LUT600H Graphic MMU LUT entry 600 high 0x22C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT600L LUT600L Graphic MMU LUT entry 600 low 0x22C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT601H LUT601H Graphic MMU LUT entry 601 high 0x22CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT601L LUT601L Graphic MMU LUT entry 601 low 0x22C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT602H LUT602H Graphic MMU LUT entry 602 high 0x22D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT602L LUT602L Graphic MMU LUT entry 602 low 0x22D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT603H LUT603H Graphic MMU LUT entry 603 high 0x22DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT603L LUT603L Graphic MMU LUT entry 603 low 0x22D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT604H LUT604H Graphic MMU LUT entry 604 high 0x22E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT604L LUT604L Graphic MMU LUT entry 604 low 0x22E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT605H LUT605H Graphic MMU LUT entry 605 high 0x22EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT605L LUT605L Graphic MMU LUT entry 605 low 0x22E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT606H LUT606H Graphic MMU LUT entry 606 high 0x22F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT606L LUT606L Graphic MMU LUT entry 606 low 0x22F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT607H LUT607H Graphic MMU LUT entry 607 high 0x22FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT607L LUT607L Graphic MMU LUT entry 607 low 0x22F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT608H LUT608H Graphic MMU LUT entry 608 high 0x2304 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT608L LUT608L Graphic MMU LUT entry 608 low 0x2300 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT609H LUT609H Graphic MMU LUT entry 609 high 0x230C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT609L LUT609L Graphic MMU LUT entry 609 low 0x2308 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT60H LUT60H Graphic MMU LUT entry 60 high 0x11E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT60L LUT60L Graphic MMU LUT entry 60 low 0x11E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT610H LUT610H Graphic MMU LUT entry 610 high 0x2314 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT610L LUT610L Graphic MMU LUT entry 610 low 0x2310 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT611H LUT611H Graphic MMU LUT entry 611 high 0x231C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT611L LUT611L Graphic MMU LUT entry 611 low 0x2318 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT612H LUT612H Graphic MMU LUT entry 612 high 0x2324 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT612L LUT612L Graphic MMU LUT entry 612 low 0x2320 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT613H LUT613H Graphic MMU LUT entry 613 high 0x232C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT613L LUT613L Graphic MMU LUT entry 613 low 0x2328 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT614H LUT614H Graphic MMU LUT entry 614 high 0x2334 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT614L LUT614L Graphic MMU LUT entry 614 low 0x2330 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT615H LUT615H Graphic MMU LUT entry 615 high 0x233C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT615L LUT615L Graphic MMU LUT entry 615 low 0x2338 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT616H LUT616H Graphic MMU LUT entry 616 high 0x2344 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT616L LUT616L Graphic MMU LUT entry 616 low 0x2340 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT617H LUT617H Graphic MMU LUT entry 617 high 0x234C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT617L LUT617L Graphic MMU LUT entry 617 low 0x2348 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT618H LUT618H Graphic MMU LUT entry 618 high 0x2354 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT618L LUT618L Graphic MMU LUT entry 618 low 0x2350 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT619H LUT619H Graphic MMU LUT entry 619 high 0x235C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT619L LUT619L Graphic MMU LUT entry 619 low 0x2358 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT61H LUT61H Graphic MMU LUT entry 61 high 0x11EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT61L LUT61L Graphic MMU LUT entry 61 low 0x11E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT620H LUT620H Graphic MMU LUT entry 620 high 0x2364 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT620L LUT620L Graphic MMU LUT entry 620 low 0x2360 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT621H LUT621H Graphic MMU LUT entry 621 high 0x236C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT621L LUT621L Graphic MMU LUT entry 621 low 0x2368 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT622H LUT622H Graphic MMU LUT entry 622 high 0x2374 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT622L LUT622L Graphic MMU LUT entry 622 low 0x2370 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT623H LUT623H Graphic MMU LUT entry 623 high 0x237C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT623L LUT623L Graphic MMU LUT entry 623 low 0x2378 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT624H LUT624H Graphic MMU LUT entry 624 high 0x2384 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT624L LUT624L Graphic MMU LUT entry 624 low 0x2380 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT625H LUT625H Graphic MMU LUT entry 625 high 0x238C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT625L LUT625L Graphic MMU LUT entry 625 low 0x2388 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT626H LUT626H Graphic MMU LUT entry 626 high 0x2394 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT626L LUT626L Graphic MMU LUT entry 626 low 0x2390 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT627H LUT627H Graphic MMU LUT entry 627 high 0x239C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT627L LUT627L Graphic MMU LUT entry 627 low 0x2398 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT628H LUT628H Graphic MMU LUT entry 628 high 0x23A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT628L LUT628L Graphic MMU LUT entry 628 low 0x23A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT629H LUT629H Graphic MMU LUT entry 629 high 0x23AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT629L LUT629L Graphic MMU LUT entry 629 low 0x23A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT62H LUT62H Graphic MMU LUT entry 62 high 0x11F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT62L LUT62L Graphic MMU LUT entry 62 low 0x11F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT630H LUT630H Graphic MMU LUT entry 630 high 0x23B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT630L LUT630L Graphic MMU LUT entry 630 low 0x23B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT631H LUT631H Graphic MMU LUT entry 631 high 0x23BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT631L LUT631L Graphic MMU LUT entry 631 low 0x23B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT632H LUT632H Graphic MMU LUT entry 632 high 0x23C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT632L LUT632L Graphic MMU LUT entry 632 low 0x23C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT633H LUT633H Graphic MMU LUT entry 633 high 0x23CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT633L LUT633L Graphic MMU LUT entry 633 low 0x23C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT634H LUT634H Graphic MMU LUT entry 634 high 0x23D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT634L LUT634L Graphic MMU LUT entry 634 low 0x23D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT635H LUT635H Graphic MMU LUT entry 635 high 0x23DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT635L LUT635L Graphic MMU LUT entry 635 low 0x23D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT636H LUT636H Graphic MMU LUT entry 636 high 0x23E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT636L LUT636L Graphic MMU LUT entry 636 low 0x23E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT637H LUT637H Graphic MMU LUT entry 637 high 0x23EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT637L LUT637L Graphic MMU LUT entry 637 low 0x23E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT638H LUT638H Graphic MMU LUT entry 638 high 0x23F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT638L LUT638L Graphic MMU LUT entry 638 low 0x23F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT639H LUT639H Graphic MMU LUT entry 639 high 0x23FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT639L LUT639L Graphic MMU LUT entry 639 low 0x23F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT63H LUT63H Graphic MMU LUT entry 63 high 0x11FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT63L LUT63L Graphic MMU LUT entry 63 low 0x11F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT640H LUT640H Graphic MMU LUT entry 640 high 0x2404 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT640L LUT640L Graphic MMU LUT entry 640 low 0x2400 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT641H LUT641H Graphic MMU LUT entry 641 high 0x240C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT641L LUT641L Graphic MMU LUT entry 641 low 0x2408 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT642H LUT642H Graphic MMU LUT entry 642 high 0x2414 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT642L LUT642L Graphic MMU LUT entry 642 low 0x2410 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT643H LUT643H Graphic MMU LUT entry 643 high 0x241C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT643L LUT643L Graphic MMU LUT entry 643 low 0x2418 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT644H LUT644H Graphic MMU LUT entry 644 high 0x2424 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT644L LUT644L Graphic MMU LUT entry 644 low 0x2420 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT645H LUT645H Graphic MMU LUT entry 645 high 0x242C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT645L LUT645L Graphic MMU LUT entry 645 low 0x2428 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT646H LUT646H Graphic MMU LUT entry 646 high 0x2434 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT646L LUT646L Graphic MMU LUT entry 646 low 0x2430 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT647H LUT647H Graphic MMU LUT entry 647 high 0x243C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT647L LUT647L Graphic MMU LUT entry 647 low 0x2438 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT648H LUT648H Graphic MMU LUT entry 648 high 0x2444 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT648L LUT648L Graphic MMU LUT entry 648 low 0x2440 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT649H LUT649H Graphic MMU LUT entry 649 high 0x244C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT649L LUT649L Graphic MMU LUT entry 649 low 0x2448 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT64H LUT64H Graphic MMU LUT entry 64 high 0x1204 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT64L LUT64L Graphic MMU LUT entry 64 low 0x1200 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT650H LUT650H Graphic MMU LUT entry 650 high 0x2454 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT650L LUT650L Graphic MMU LUT entry 650 low 0x2450 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT651H LUT651H Graphic MMU LUT entry 651 high 0x245C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT651L LUT651L Graphic MMU LUT entry 651 low 0x2458 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT652H LUT652H Graphic MMU LUT entry 652 high 0x2464 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT652L LUT652L Graphic MMU LUT entry 652 low 0x2460 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT653H LUT653H Graphic MMU LUT entry 653 high 0x246C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT653L LUT653L Graphic MMU LUT entry 653 low 0x2468 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT654H LUT654H Graphic MMU LUT entry 654 high 0x2474 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT654L LUT654L Graphic MMU LUT entry 654 low 0x2470 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT655H LUT655H Graphic MMU LUT entry 655 high 0x247C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT655L LUT655L Graphic MMU LUT entry 655 low 0x2478 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT656H LUT656H Graphic MMU LUT entry 656 high 0x2484 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT656L LUT656L Graphic MMU LUT entry 656 low 0x2480 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT657H LUT657H Graphic MMU LUT entry 657 high 0x248C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT657L LUT657L Graphic MMU LUT entry 657 low 0x2488 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT658H LUT658H Graphic MMU LUT entry 658 high 0x2494 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT658L LUT658L Graphic MMU LUT entry 658 low 0x2490 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT659H LUT659H Graphic MMU LUT entry 659 high 0x249C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT659L LUT659L Graphic MMU LUT entry 659 low 0x2498 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT65H LUT65H Graphic MMU LUT entry 65 high 0x120C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT65L LUT65L Graphic MMU LUT entry 65 low 0x1208 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT660H LUT660H Graphic MMU LUT entry 660 high 0x24A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT660L LUT660L Graphic MMU LUT entry 660 low 0x24A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT661H LUT661H Graphic MMU LUT entry 661 high 0x24AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT661L LUT661L Graphic MMU LUT entry 661 low 0x24A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT662H LUT662H Graphic MMU LUT entry 662 high 0x24B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT662L LUT662L Graphic MMU LUT entry 662 low 0x24B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT663H LUT663H Graphic MMU LUT entry 663 high 0x24BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT663L LUT663L Graphic MMU LUT entry 663 low 0x24B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT664H LUT664H Graphic MMU LUT entry 664 high 0x24C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT664L LUT664L Graphic MMU LUT entry 664 low 0x24C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT665H LUT665H Graphic MMU LUT entry 665 high 0x24CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT665L LUT665L Graphic MMU LUT entry 665 low 0x24C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT666H LUT666H Graphic MMU LUT entry 666 high 0x24D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT666L LUT666L Graphic MMU LUT entry 666 low 0x24D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT667H LUT667H Graphic MMU LUT entry 667 high 0x24DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT667L LUT667L Graphic MMU LUT entry 667 low 0x24D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT668H LUT668H Graphic MMU LUT entry 668 high 0x24E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT668L LUT668L Graphic MMU LUT entry 668 low 0x24E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT669H LUT669H Graphic MMU LUT entry 669 high 0x24EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT669L LUT669L Graphic MMU LUT entry 669 low 0x24E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT66H LUT66H Graphic MMU LUT entry 66 high 0x1214 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT66L LUT66L Graphic MMU LUT entry 66 low 0x1210 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT670H LUT670H Graphic MMU LUT entry 670 high 0x24F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT670L LUT670L Graphic MMU LUT entry 670 low 0x24F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT671H LUT671H Graphic MMU LUT entry 671 high 0x24FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT671L LUT671L Graphic MMU LUT entry 671 low 0x24F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT672H LUT672H Graphic MMU LUT entry 672 high 0x2504 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT672L LUT672L Graphic MMU LUT entry 672 low 0x2500 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT673H LUT673H Graphic MMU LUT entry 673 high 0x250C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT673L LUT673L Graphic MMU LUT entry 673 low 0x2508 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT674H LUT674H Graphic MMU LUT entry 674 high 0x2514 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT674L LUT674L Graphic MMU LUT entry 674 low 0x2510 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT675H LUT675H Graphic MMU LUT entry 675 high 0x251C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT675L LUT675L Graphic MMU LUT entry 675 low 0x2518 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT676H LUT676H Graphic MMU LUT entry 676 high 0x2524 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT676L LUT676L Graphic MMU LUT entry 676 low 0x2520 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT677H LUT677H Graphic MMU LUT entry 677 high 0x252C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT677L LUT677L Graphic MMU LUT entry 677 low 0x2528 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT678H LUT678H Graphic MMU LUT entry 678 high 0x2534 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT678L LUT678L Graphic MMU LUT entry 678 low 0x2530 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT679H LUT679H Graphic MMU LUT entry 679 high 0x253C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT679L LUT679L Graphic MMU LUT entry 679 low 0x2538 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT67H LUT67H Graphic MMU LUT entry 67 high 0x121C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT67L LUT67L Graphic MMU LUT entry 67 low 0x1218 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT680H LUT680H Graphic MMU LUT entry 680 high 0x2544 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT680L LUT680L Graphic MMU LUT entry 680 low 0x2540 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT681H LUT681H Graphic MMU LUT entry 681 high 0x254C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT681L LUT681L Graphic MMU LUT entry 681 low 0x2548 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT682H LUT682H Graphic MMU LUT entry 682 high 0x2554 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT682L LUT682L Graphic MMU LUT entry 682 low 0x2550 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT683H LUT683H Graphic MMU LUT entry 683 high 0x255C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT683L LUT683L Graphic MMU LUT entry 683 low 0x2558 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT684H LUT684H Graphic MMU LUT entry 684 high 0x2564 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT684L LUT684L Graphic MMU LUT entry 684 low 0x2560 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT685H LUT685H Graphic MMU LUT entry 685 high 0x256C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT685L LUT685L Graphic MMU LUT entry 685 low 0x2568 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT686H LUT686H Graphic MMU LUT entry 686 high 0x2574 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT686L LUT686L Graphic MMU LUT entry 686 low 0x2570 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT687H LUT687H Graphic MMU LUT entry 687 high 0x257C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT687L LUT687L Graphic MMU LUT entry 687 low 0x2578 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT688H LUT688H Graphic MMU LUT entry 688 high 0x2584 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT688L LUT688L Graphic MMU LUT entry 688 low 0x2580 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT689H LUT689H Graphic MMU LUT entry 689 high 0x258C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT689L LUT689L Graphic MMU LUT entry 689 low 0x2588 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT68H LUT68H Graphic MMU LUT entry 68 high 0x1224 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT68L LUT68L Graphic MMU LUT entry 68 low 0x1220 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT690H LUT690H Graphic MMU LUT entry 690 high 0x2594 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT690L LUT690L Graphic MMU LUT entry 690 low 0x2590 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT691H LUT691H Graphic MMU LUT entry 691 high 0x259C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT691L LUT691L Graphic MMU LUT entry 691 low 0x2598 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT692H LUT692H Graphic MMU LUT entry 692 high 0x25A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT692L LUT692L Graphic MMU LUT entry 692 low 0x25A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT693H LUT693H Graphic MMU LUT entry 693 high 0x25AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT693L LUT693L Graphic MMU LUT entry 693 low 0x25A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT694H LUT694H Graphic MMU LUT entry 694 high 0x25B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT694L LUT694L Graphic MMU LUT entry 694 low 0x25B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT695H LUT695H Graphic MMU LUT entry 695 high 0x25BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT695L LUT695L Graphic MMU LUT entry 695 low 0x25B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT696H LUT696H Graphic MMU LUT entry 696 high 0x25C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT696L LUT696L Graphic MMU LUT entry 696 low 0x25C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT697H LUT697H Graphic MMU LUT entry 697 high 0x25CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT697L LUT697L Graphic MMU LUT entry 697 low 0x25C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT698H LUT698H Graphic MMU LUT entry 698 high 0x25D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT698L LUT698L Graphic MMU LUT entry 698 low 0x25D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT699H LUT699H Graphic MMU LUT entry 699 high 0x25DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT699L LUT699L Graphic MMU LUT entry 699 low 0x25D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT69H LUT69H Graphic MMU LUT entry 69 high 0x122C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT69L LUT69L Graphic MMU LUT entry 69 low 0x1228 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT6H LUT6H Graphic MMU LUT entry 6 high 0x1034 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT6L LUT6L Graphic MMU LUT entry 6 low 0x1030 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT700H LUT700H Graphic MMU LUT entry 700 high 0x25E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT700L LUT700L Graphic MMU LUT entry 700 low 0x25E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT701H LUT701H Graphic MMU LUT entry 701 high 0x25EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT701L LUT701L Graphic MMU LUT entry 701 low 0x25E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT702H LUT702H Graphic MMU LUT entry 702 high 0x25F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT702L LUT702L Graphic MMU LUT entry 702 low 0x25F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT703H LUT703H Graphic MMU LUT entry 703 high 0x25FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT703L LUT703L Graphic MMU LUT entry 703 low 0x25F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT704H LUT704H Graphic MMU LUT entry 704 high 0x2604 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT704L LUT704L Graphic MMU LUT entry 704 low 0x2600 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT705H LUT705H Graphic MMU LUT entry 705 high 0x260C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT705L LUT705L Graphic MMU LUT entry 705 low 0x2608 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT706H LUT706H Graphic MMU LUT entry 706 high 0x2614 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT706L LUT706L Graphic MMU LUT entry 706 low 0x2610 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT707H LUT707H Graphic MMU LUT entry 707 high 0x261C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT707L LUT707L Graphic MMU LUT entry 707 low 0x2618 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT708H LUT708H Graphic MMU LUT entry 708 high 0x2624 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT708L LUT708L Graphic MMU LUT entry 708 low 0x2620 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT709H LUT709H Graphic MMU LUT entry 709 high 0x262C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT709L LUT709L Graphic MMU LUT entry 709 low 0x2628 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT70H LUT70H Graphic MMU LUT entry 70 high 0x1234 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT70L LUT70L Graphic MMU LUT entry 70 low 0x1230 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT710H LUT710H Graphic MMU LUT entry 710 high 0x2634 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT710L LUT710L Graphic MMU LUT entry 710 low 0x2630 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT711H LUT711H Graphic MMU LUT entry 711 high 0x263C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT711L LUT711L Graphic MMU LUT entry 711 low 0x2638 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT712H LUT712H Graphic MMU LUT entry 712 high 0x2644 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT712L LUT712L Graphic MMU LUT entry 712 low 0x2640 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT713H LUT713H Graphic MMU LUT entry 713 high 0x264C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT713L LUT713L Graphic MMU LUT entry 713 low 0x2648 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT714H LUT714H Graphic MMU LUT entry 714 high 0x2654 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT714L LUT714L Graphic MMU LUT entry 714 low 0x2650 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT715H LUT715H Graphic MMU LUT entry 715 high 0x265C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT715L LUT715L Graphic MMU LUT entry 715 low 0x2658 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT716H LUT716H Graphic MMU LUT entry 716 high 0x2664 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT716L LUT716L Graphic MMU LUT entry 716 low 0x2660 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT717H LUT717H Graphic MMU LUT entry 717 high 0x266C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT717L LUT717L Graphic MMU LUT entry 717 low 0x2668 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT718H LUT718H Graphic MMU LUT entry 718 high 0x2674 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT718L LUT718L Graphic MMU LUT entry 718 low 0x2670 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT719H LUT719H Graphic MMU LUT entry 719 high 0x267C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT719L LUT719L Graphic MMU LUT entry 719 low 0x2678 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT71H LUT71H Graphic MMU LUT entry 71 high 0x123C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT71L LUT71L Graphic MMU LUT entry 71 low 0x1238 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT720H LUT720H Graphic MMU LUT entry 720 high 0x2684 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT720L LUT720L Graphic MMU LUT entry 720 low 0x2680 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT721H LUT721H Graphic MMU LUT entry 721 high 0x268C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT721L LUT721L Graphic MMU LUT entry 721 low 0x2688 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT722H LUT722H Graphic MMU LUT entry 722 high 0x2694 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT722L LUT722L Graphic MMU LUT entry 722 low 0x2690 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT723H LUT723H Graphic MMU LUT entry 723 high 0x269C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT723L LUT723L Graphic MMU LUT entry 723 low 0x2698 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT724H LUT724H Graphic MMU LUT entry 724 high 0x26A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT724L LUT724L Graphic MMU LUT entry 724 low 0x26A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT725H LUT725H Graphic MMU LUT entry 725 high 0x26AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT725L LUT725L Graphic MMU LUT entry 725 low 0x26A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT726H LUT726H Graphic MMU LUT entry 726 high 0x26B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT726L LUT726L Graphic MMU LUT entry 726 low 0x26B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT727H LUT727H Graphic MMU LUT entry 727 high 0x26BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT727L LUT727L Graphic MMU LUT entry 727 low 0x26B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT728H LUT728H Graphic MMU LUT entry 728 high 0x26C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT728L LUT728L Graphic MMU LUT entry 728 low 0x26C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT729H LUT729H Graphic MMU LUT entry 729 high 0x26CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT729L LUT729L Graphic MMU LUT entry 729 low 0x26C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT72H LUT72H Graphic MMU LUT entry 72 high 0x1244 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT72L LUT72L Graphic MMU LUT entry 72 low 0x1240 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT730H LUT730H Graphic MMU LUT entry 730 high 0x26D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT730L LUT730L Graphic MMU LUT entry 730 low 0x26D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT731H LUT731H Graphic MMU LUT entry 731 high 0x26DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT731L LUT731L Graphic MMU LUT entry 731 low 0x26D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT732H LUT732H Graphic MMU LUT entry 732 high 0x26E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT732L LUT732L Graphic MMU LUT entry 732 low 0x26E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT733H LUT733H Graphic MMU LUT entry 733 high 0x26EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT733L LUT733L Graphic MMU LUT entry 733 low 0x26E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT734H LUT734H Graphic MMU LUT entry 734 high 0x26F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT734L LUT734L Graphic MMU LUT entry 734 low 0x26F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT735H LUT735H Graphic MMU LUT entry 735 high 0x26FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT735L LUT735L Graphic MMU LUT entry 735 low 0x26F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT736H LUT736H Graphic MMU LUT entry 736 high 0x2704 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT736L LUT736L Graphic MMU LUT entry 736 low 0x2700 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT737H LUT737H Graphic MMU LUT entry 737 high 0x270C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT737L LUT737L Graphic MMU LUT entry 737 low 0x2708 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT738H LUT738H Graphic MMU LUT entry 738 high 0x2714 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT738L LUT738L Graphic MMU LUT entry 738 low 0x2710 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT739H LUT739H Graphic MMU LUT entry 739 high 0x271C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT739L LUT739L Graphic MMU LUT entry 739 low 0x2718 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT73H LUT73H Graphic MMU LUT entry 73 high 0x124C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT73L LUT73L Graphic MMU LUT entry 73 low 0x1248 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT740H LUT740H Graphic MMU LUT entry 740 high 0x2724 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT740L LUT740L Graphic MMU LUT entry 740 low 0x2720 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT741H LUT741H Graphic MMU LUT entry 741 high 0x272C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT741L LUT741L Graphic MMU LUT entry 741 low 0x2728 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT742H LUT742H Graphic MMU LUT entry 742 high 0x2734 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT742L LUT742L Graphic MMU LUT entry 742 low 0x2730 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT743H LUT743H Graphic MMU LUT entry 743 high 0x273C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT743L LUT743L Graphic MMU LUT entry 743 low 0x2738 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT744H LUT744H Graphic MMU LUT entry 744 high 0x2744 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT744L LUT744L Graphic MMU LUT entry 744 low 0x2740 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT745H LUT745H Graphic MMU LUT entry 745 high 0x274C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT745L LUT745L Graphic MMU LUT entry 745 low 0x2748 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT746H LUT746H Graphic MMU LUT entry 746 high 0x2754 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT746L LUT746L Graphic MMU LUT entry 746 low 0x2750 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT747H LUT747H Graphic MMU LUT entry 747 high 0x275C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT747L LUT747L Graphic MMU LUT entry 747 low 0x2758 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT748H LUT748H Graphic MMU LUT entry 748 high 0x2764 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT748L LUT748L Graphic MMU LUT entry 748 low 0x2760 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT749H LUT749H Graphic MMU LUT entry 749 high 0x276C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT749L LUT749L Graphic MMU LUT entry 749 low 0x2768 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT74H LUT74H Graphic MMU LUT entry 74 high 0x1254 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT74L LUT74L Graphic MMU LUT entry 74 low 0x1250 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT750H LUT750H Graphic MMU LUT entry 750 high 0x2774 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT750L LUT750L Graphic MMU LUT entry 750 low 0x2770 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT751H LUT751H Graphic MMU LUT entry 751 high 0x277C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT751L LUT751L Graphic MMU LUT entry 751 low 0x2778 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT752H LUT752H Graphic MMU LUT entry 752 high 0x2784 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT752L LUT752L Graphic MMU LUT entry 752 low 0x2780 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT753H LUT753H Graphic MMU LUT entry 753 high 0x278C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT753L LUT753L Graphic MMU LUT entry 753 low 0x2788 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT754H LUT754H Graphic MMU LUT entry 754 high 0x2794 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT754L LUT754L Graphic MMU LUT entry 754 low 0x2790 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT755H LUT755H Graphic MMU LUT entry 755 high 0x279C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT755L LUT755L Graphic MMU LUT entry 755 low 0x2798 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT756H LUT756H Graphic MMU LUT entry 756 high 0x27A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT756L LUT756L Graphic MMU LUT entry 756 low 0x27A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT757H LUT757H Graphic MMU LUT entry 757 high 0x27AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT757L LUT757L Graphic MMU LUT entry 757 low 0x27A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT758H LUT758H Graphic MMU LUT entry 758 high 0x27B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT758L LUT758L Graphic MMU LUT entry 758 low 0x27B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT759H LUT759H Graphic MMU LUT entry 759 high 0x27BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT759L LUT759L Graphic MMU LUT entry 759 low 0x27B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT75H LUT75H Graphic MMU LUT entry 75 high 0x125C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT75L LUT75L Graphic MMU LUT entry 75 low 0x1258 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT760H LUT760H Graphic MMU LUT entry 760 high 0x27C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT760L LUT760L Graphic MMU LUT entry 760 low 0x27C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT761H LUT761H Graphic MMU LUT entry 761 high 0x27CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT761L LUT761L Graphic MMU LUT entry 761 low 0x27C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT762H LUT762H Graphic MMU LUT entry 762 high 0x27D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT762L LUT762L Graphic MMU LUT entry 762 low 0x27D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT763H LUT763H Graphic MMU LUT entry 763 high 0x27DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT763L LUT763L Graphic MMU LUT entry 763 low 0x27D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT764H LUT764H Graphic MMU LUT entry 764 high 0x27E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT764L LUT764L Graphic MMU LUT entry 764 low 0x27E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT765H LUT765H Graphic MMU LUT entry 765 high 0x27EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT765L LUT765L Graphic MMU LUT entry 765 low 0x27E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT766H LUT766H Graphic MMU LUT entry 766 high 0x27F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT766L LUT766L Graphic MMU LUT entry 766 low 0x27F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT767H LUT767H Graphic MMU LUT entry 767 high 0x27FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT767L LUT767L Graphic MMU LUT entry 767 low 0x27F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT768H LUT768H Graphic MMU LUT entry 768 high 0x2804 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT768L LUT768L Graphic MMU LUT entry 768 low 0x2800 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT769H LUT769H Graphic MMU LUT entry 769 high 0x280C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT769L LUT769L Graphic MMU LUT entry 769 low 0x2808 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT76H LUT76H Graphic MMU LUT entry 76 high 0x1264 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT76L LUT76L Graphic MMU LUT entry 76 low 0x1260 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT770H LUT770H Graphic MMU LUT entry 770 high 0x2814 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT770L LUT770L Graphic MMU LUT entry 770 low 0x2810 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT771H LUT771H Graphic MMU LUT entry 771 high 0x281C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT771L LUT771L Graphic MMU LUT entry 771 low 0x2818 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT772H LUT772H Graphic MMU LUT entry 772 high 0x2824 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT772L LUT772L Graphic MMU LUT entry 772 low 0x2820 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT773H LUT773H Graphic MMU LUT entry 773 high 0x282C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT773L LUT773L Graphic MMU LUT entry 773 low 0x2828 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT774H LUT774H Graphic MMU LUT entry 774 high 0x2834 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT774L LUT774L Graphic MMU LUT entry 774 low 0x2830 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT775H LUT775H Graphic MMU LUT entry 775 high 0x283C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT775L LUT775L Graphic MMU LUT entry 775 low 0x2838 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT776H LUT776H Graphic MMU LUT entry 776 high 0x2844 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT776L LUT776L Graphic MMU LUT entry 776 low 0x2840 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT777H LUT777H Graphic MMU LUT entry 777 high 0x284C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT777L LUT777L Graphic MMU LUT entry 777 low 0x2848 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT778H LUT778H Graphic MMU LUT entry 778 high 0x2854 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT778L LUT778L Graphic MMU LUT entry 778 low 0x2850 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT779H LUT779H Graphic MMU LUT entry 779 high 0x285C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT779L LUT779L Graphic MMU LUT entry 779 low 0x2858 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT77H LUT77H Graphic MMU LUT entry 77 high 0x126C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT77L LUT77L Graphic MMU LUT entry 77 low 0x1268 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT780H LUT780H Graphic MMU LUT entry 780 high 0x2864 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT780L LUT780L Graphic MMU LUT entry 780 low 0x2860 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT781H LUT781H Graphic MMU LUT entry 781 high 0x286C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT781L LUT781L Graphic MMU LUT entry 781 low 0x2868 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT782H LUT782H Graphic MMU LUT entry 782 high 0x2874 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT782L LUT782L Graphic MMU LUT entry 782 low 0x2870 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT783H LUT783H Graphic MMU LUT entry 783 high 0x287C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT783L LUT783L Graphic MMU LUT entry 783 low 0x2878 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT784H LUT784H Graphic MMU LUT entry 784 high 0x2884 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT784L LUT784L Graphic MMU LUT entry 784 low 0x2880 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT785H LUT785H Graphic MMU LUT entry 785 high 0x288C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT785L LUT785L Graphic MMU LUT entry 785 low 0x2888 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT786H LUT786H Graphic MMU LUT entry 786 high 0x2894 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT786L LUT786L Graphic MMU LUT entry 786 low 0x2890 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT787H LUT787H Graphic MMU LUT entry 787 high 0x289C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT787L LUT787L Graphic MMU LUT entry 787 low 0x2898 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT788H LUT788H Graphic MMU LUT entry 788 high 0x28A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT788L LUT788L Graphic MMU LUT entry 788 low 0x28A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT789H LUT789H Graphic MMU LUT entry 789 high 0x28AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT789L LUT789L Graphic MMU LUT entry 789 low 0x28A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT78H LUT78H Graphic MMU LUT entry 78 high 0x1274 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT78L LUT78L Graphic MMU LUT entry 78 low 0x1270 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT790H LUT790H Graphic MMU LUT entry 790 high 0x28B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT790L LUT790L Graphic MMU LUT entry 790 low 0x28B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT791H LUT791H Graphic MMU LUT entry 791 high 0x28BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT791L LUT791L Graphic MMU LUT entry 791 low 0x28B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT792H LUT792H Graphic MMU LUT entry 792 high 0x28C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT792L LUT792L Graphic MMU LUT entry 792 low 0x28C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT793H LUT793H Graphic MMU LUT entry 793 high 0x28CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT793L LUT793L Graphic MMU LUT entry 793 low 0x28C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT794H LUT794H Graphic MMU LUT entry 794 high 0x28D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT794L LUT794L Graphic MMU LUT entry 794 low 0x28D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT795H LUT795H Graphic MMU LUT entry 795 high 0x28DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT795L LUT795L Graphic MMU LUT entry 795 low 0x28D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT796H LUT796H Graphic MMU LUT entry 796 high 0x28E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT796L LUT796L Graphic MMU LUT entry 796 low 0x28E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT797H LUT797H Graphic MMU LUT entry 797 high 0x28EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT797L LUT797L Graphic MMU LUT entry 797 low 0x28E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT798H LUT798H Graphic MMU LUT entry 798 high 0x28F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT798L LUT798L Graphic MMU LUT entry 798 low 0x28F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT799H LUT799H Graphic MMU LUT entry 799 high 0x28FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT799L LUT799L Graphic MMU LUT entry 799 low 0x28F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT79H LUT79H Graphic MMU LUT entry 79 high 0x127C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT79L LUT79L Graphic MMU LUT entry 79 low 0x1278 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT7H LUT7H Graphic MMU LUT entry 7 high 0x103C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT7L LUT7L Graphic MMU LUT entry 7 low 0x1038 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT800H LUT800H Graphic MMU LUT entry 800 high 0x2904 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT800L LUT800L Graphic MMU LUT entry 800 low 0x2900 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT801H LUT801H Graphic MMU LUT entry 801 high 0x290C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT801L LUT801L Graphic MMU LUT entry 801 low 0x2908 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT802H LUT802H Graphic MMU LUT entry 802 high 0x2914 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT802L LUT802L Graphic MMU LUT entry 802 low 0x2910 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT803H LUT803H Graphic MMU LUT entry 803 high 0x291C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT803L LUT803L Graphic MMU LUT entry 803 low 0x2918 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT804H LUT804H Graphic MMU LUT entry 804 high 0x2924 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT804L LUT804L Graphic MMU LUT entry 804 low 0x2920 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT805H LUT805H Graphic MMU LUT entry 805 high 0x292C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT805L LUT805L Graphic MMU LUT entry 805 low 0x2928 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT806H LUT806H Graphic MMU LUT entry 806 high 0x2934 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT806L LUT806L Graphic MMU LUT entry 806 low 0x2930 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT807H LUT807H Graphic MMU LUT entry 807 high 0x293C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT807L LUT807L Graphic MMU LUT entry 807 low 0x2938 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT808H LUT808H Graphic MMU LUT entry 808 high 0x2944 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT808L LUT808L Graphic MMU LUT entry 808 low 0x2940 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT809H LUT809H Graphic MMU LUT entry 809 high 0x294C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT809L LUT809L Graphic MMU LUT entry 809 low 0x2948 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT80H LUT80H Graphic MMU LUT entry 80 high 0x1284 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT80L LUT80L Graphic MMU LUT entry 80 low 0x1280 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT810H LUT810H Graphic MMU LUT entry 810 high 0x2954 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT810L LUT810L Graphic MMU LUT entry 810 low 0x2950 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT811H LUT811H Graphic MMU LUT entry 811 high 0x295C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT811L LUT811L Graphic MMU LUT entry 811 low 0x2958 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT812H LUT812H Graphic MMU LUT entry 812 high 0x2964 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT812L LUT812L Graphic MMU LUT entry 812 low 0x2960 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT813H LUT813H Graphic MMU LUT entry 813 high 0x296C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT813L LUT813L Graphic MMU LUT entry 813 low 0x2968 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT814H LUT814H Graphic MMU LUT entry 814 high 0x2974 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT814L LUT814L Graphic MMU LUT entry 814 low 0x2970 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT815H LUT815H Graphic MMU LUT entry 815 high 0x297C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT815L LUT815L Graphic MMU LUT entry 815 low 0x2978 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT816H LUT816H Graphic MMU LUT entry 816 high 0x2984 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT816L LUT816L Graphic MMU LUT entry 816 low 0x2980 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT817H LUT817H Graphic MMU LUT entry 817 high 0x298C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT817L LUT817L Graphic MMU LUT entry 817 low 0x2988 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT818H LUT818H Graphic MMU LUT entry 818 high 0x2994 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT818L LUT818L Graphic MMU LUT entry 818 low 0x2990 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT819H LUT819H Graphic MMU LUT entry 819 high 0x299C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT819L LUT819L Graphic MMU LUT entry 819 low 0x2998 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT81H LUT81H Graphic MMU LUT entry 81 high 0x128C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT81L LUT81L Graphic MMU LUT entry 81 low 0x1288 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT820H LUT820H Graphic MMU LUT entry 820 high 0x29A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT820L LUT820L Graphic MMU LUT entry 820 low 0x29A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT821H LUT821H Graphic MMU LUT entry 821 high 0x29AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT821L LUT821L Graphic MMU LUT entry 821 low 0x29A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT822H LUT822H Graphic MMU LUT entry 822 high 0x29B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT822L LUT822L Graphic MMU LUT entry 822 low 0x29B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT823H LUT823H Graphic MMU LUT entry 823 high 0x29BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT823L LUT823L Graphic MMU LUT entry 823 low 0x29B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT824H LUT824H Graphic MMU LUT entry 824 high 0x29C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT824L LUT824L Graphic MMU LUT entry 824 low 0x29C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT825H LUT825H Graphic MMU LUT entry 825 high 0x29CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT825L LUT825L Graphic MMU LUT entry 825 low 0x29C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT826H LUT826H Graphic MMU LUT entry 826 high 0x29D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT826L LUT826L Graphic MMU LUT entry 826 low 0x29D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT827H LUT827H Graphic MMU LUT entry 827 high 0x29DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT827L LUT827L Graphic MMU LUT entry 827 low 0x29D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT828H LUT828H Graphic MMU LUT entry 828 high 0x29E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT828L LUT828L Graphic MMU LUT entry 828 low 0x29E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT829H LUT829H Graphic MMU LUT entry 829 high 0x29EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT829L LUT829L Graphic MMU LUT entry 829 low 0x29E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT82H LUT82H Graphic MMU LUT entry 82 high 0x1294 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT82L LUT82L Graphic MMU LUT entry 82 low 0x1290 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT830H LUT830H Graphic MMU LUT entry 830 high 0x29F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT830L LUT830L Graphic MMU LUT entry 830 low 0x29F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT831H LUT831H Graphic MMU LUT entry 831 high 0x29FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT831L LUT831L Graphic MMU LUT entry 831 low 0x29F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT832H LUT832H Graphic MMU LUT entry 832 high 0x2A04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT832L LUT832L Graphic MMU LUT entry 832 low 0x2A00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT833H LUT833H Graphic MMU LUT entry 833 high 0x2A0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT833L LUT833L Graphic MMU LUT entry 833 low 0x2A08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT834H LUT834H Graphic MMU LUT entry 834 high 0x2A14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT834L LUT834L Graphic MMU LUT entry 834 low 0x2A10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT835H LUT835H Graphic MMU LUT entry 835 high 0x2A1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT835L LUT835L Graphic MMU LUT entry 835 low 0x2A18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT836H LUT836H Graphic MMU LUT entry 836 high 0x2A24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT836L LUT836L Graphic MMU LUT entry 836 low 0x2A20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT837H LUT837H Graphic MMU LUT entry 837 high 0x2A2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT837L LUT837L Graphic MMU LUT entry 837 low 0x2A28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT838H LUT838H Graphic MMU LUT entry 838 high 0x2A34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT838L LUT838L Graphic MMU LUT entry 838 low 0x2A30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT839H LUT839H Graphic MMU LUT entry 839 high 0x2A3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT839L LUT839L Graphic MMU LUT entry 839 low 0x2A38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT83H LUT83H Graphic MMU LUT entry 83 high 0x129C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT83L LUT83L Graphic MMU LUT entry 83 low 0x1298 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT840H LUT840H Graphic MMU LUT entry 840 high 0x2A44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT840L LUT840L Graphic MMU LUT entry 840 low 0x2A40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT841H LUT841H Graphic MMU LUT entry 841 high 0x2A4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT841L LUT841L Graphic MMU LUT entry 841 low 0x2A48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT842H LUT842H Graphic MMU LUT entry 842 high 0x2A54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT842L LUT842L Graphic MMU LUT entry 842 low 0x2A50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT843H LUT843H Graphic MMU LUT entry 843 high 0x2A5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT843L LUT843L Graphic MMU LUT entry 843 low 0x2A58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT844H LUT844H Graphic MMU LUT entry 844 high 0x2A64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT844L LUT844L Graphic MMU LUT entry 844 low 0x2A60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT845H LUT845H Graphic MMU LUT entry 845 high 0x2A6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT845L LUT845L Graphic MMU LUT entry 845 low 0x2A68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT846H LUT846H Graphic MMU LUT entry 846 high 0x2A74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT846L LUT846L Graphic MMU LUT entry 846 low 0x2A70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT847H LUT847H Graphic MMU LUT entry 847 high 0x2A7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT847L LUT847L Graphic MMU LUT entry 847 low 0x2A78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT848H LUT848H Graphic MMU LUT entry 848 high 0x2A84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT848L LUT848L Graphic MMU LUT entry 848 low 0x2A80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT849H LUT849H Graphic MMU LUT entry 849 high 0x2A8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT849L LUT849L Graphic MMU LUT entry 849 low 0x2A88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT84H LUT84H Graphic MMU LUT entry 84 high 0x12A4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT84L LUT84L Graphic MMU LUT entry 84 low 0x12A0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT850H LUT850H Graphic MMU LUT entry 850 high 0x2A94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT850L LUT850L Graphic MMU LUT entry 850 low 0x2A90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT851H LUT851H Graphic MMU LUT entry 851 high 0x2A9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT851L LUT851L Graphic MMU LUT entry 851 low 0x2A98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT852H LUT852H Graphic MMU LUT entry 852 high 0x2AA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT852L LUT852L Graphic MMU LUT entry 852 low 0x2AA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT853H LUT853H Graphic MMU LUT entry 853 high 0x2AAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT853L LUT853L Graphic MMU LUT entry 853 low 0x2AA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT854H LUT854H Graphic MMU LUT entry 854 high 0x2AB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT854L LUT854L Graphic MMU LUT entry 854 low 0x2AB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT855H LUT855H Graphic MMU LUT entry 855 high 0x2ABC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT855L LUT855L Graphic MMU LUT entry 855 low 0x2AB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT856H LUT856H Graphic MMU LUT entry 856 high 0x2AC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT856L LUT856L Graphic MMU LUT entry 856 low 0x2AC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT857H LUT857H Graphic MMU LUT entry 857 high 0x2ACC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT857L LUT857L Graphic MMU LUT entry 857 low 0x2AC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT858H LUT858H Graphic MMU LUT entry 858 high 0x2AD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT858L LUT858L Graphic MMU LUT entry 858 low 0x2AD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT859H LUT859H Graphic MMU LUT entry 859 high 0x2ADC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT859L LUT859L Graphic MMU LUT entry 859 low 0x2AD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT85H LUT85H Graphic MMU LUT entry 85 high 0x12AC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT85L LUT85L Graphic MMU LUT entry 85 low 0x12A8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT860H LUT860H Graphic MMU LUT entry 860 high 0x2AE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT860L LUT860L Graphic MMU LUT entry 860 low 0x2AE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT861H LUT861H Graphic MMU LUT entry 861 high 0x2AEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT861L LUT861L Graphic MMU LUT entry 861 low 0x2AE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT862H LUT862H Graphic MMU LUT entry 862 high 0x2AF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT862L LUT862L Graphic MMU LUT entry 862 low 0x2AF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT863H LUT863H Graphic MMU LUT entry 863 high 0x2AFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT863L LUT863L Graphic MMU LUT entry 863 low 0x2AF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT864H LUT864H Graphic MMU LUT entry 864 high 0x2B04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT864L LUT864L Graphic MMU LUT entry 864 low 0x2B00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT865H LUT865H Graphic MMU LUT entry 865 high 0x2B0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT865L LUT865L Graphic MMU LUT entry 865 low 0x2B08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT866H LUT866H Graphic MMU LUT entry 866 high 0x2B14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT866L LUT866L Graphic MMU LUT entry 866 low 0x2B10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT867H LUT867H Graphic MMU LUT entry 867 high 0x2B1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT867L LUT867L Graphic MMU LUT entry 867 low 0x2B18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT868H LUT868H Graphic MMU LUT entry 868 high 0x2B24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT868L LUT868L Graphic MMU LUT entry 868 low 0x2B20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT869H LUT869H Graphic MMU LUT entry 869 high 0x2B2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT869L LUT869L Graphic MMU LUT entry 869 low 0x2B28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT86H LUT86H Graphic MMU LUT entry 86 high 0x12B4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT86L LUT86L Graphic MMU LUT entry 86 low 0x12B0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT870H LUT870H Graphic MMU LUT entry 870 high 0x2B34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT870L LUT870L Graphic MMU LUT entry 870 low 0x2B30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT871H LUT871H Graphic MMU LUT entry 871 high 0x2B3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT871L LUT871L Graphic MMU LUT entry 871 low 0x2B38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT872H LUT872H Graphic MMU LUT entry 872 high 0x2B44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT872L LUT872L Graphic MMU LUT entry 872 low 0x2B40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT873H LUT873H Graphic MMU LUT entry 873 high 0x2B4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT873L LUT873L Graphic MMU LUT entry 873 low 0x2B48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT874H LUT874H Graphic MMU LUT entry 874 high 0x2B54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT874L LUT874L Graphic MMU LUT entry 874 low 0x2B50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT875H LUT875H Graphic MMU LUT entry 875 high 0x2B5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT875L LUT875L Graphic MMU LUT entry 875 low 0x2B58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT876H LUT876H Graphic MMU LUT entry 876 high 0x2B64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT876L LUT876L Graphic MMU LUT entry 876 low 0x2B60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT877H LUT877H Graphic MMU LUT entry 877 high 0x2B6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT877L LUT877L Graphic MMU LUT entry 877 low 0x2B68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT878H LUT878H Graphic MMU LUT entry 878 high 0x2B74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT878L LUT878L Graphic MMU LUT entry 878 low 0x2B70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT879H LUT879H Graphic MMU LUT entry 879 high 0x2B7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT879L LUT879L Graphic MMU LUT entry 879 low 0x2B78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT87H LUT87H Graphic MMU LUT entry 87 high 0x12BC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT87L LUT87L Graphic MMU LUT entry 87 low 0x12B8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT880H LUT880H Graphic MMU LUT entry 880 high 0x2B84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT880L LUT880L Graphic MMU LUT entry 880 low 0x2B80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT881H LUT881H Graphic MMU LUT entry 881 high 0x2B8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT881L LUT881L Graphic MMU LUT entry 881 low 0x2B88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT882H LUT882H Graphic MMU LUT entry 882 high 0x2B94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT882L LUT882L Graphic MMU LUT entry 882 low 0x2B90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT883H LUT883H Graphic MMU LUT entry 883 high 0x2B9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT883L LUT883L Graphic MMU LUT entry 883 low 0x2B98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT884H LUT884H Graphic MMU LUT entry 884 high 0x2BA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT884L LUT884L Graphic MMU LUT entry 884 low 0x2BA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT885H LUT885H Graphic MMU LUT entry 885 high 0x2BAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT885L LUT885L Graphic MMU LUT entry 885 low 0x2BA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT886H LUT886H Graphic MMU LUT entry 886 high 0x2BB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT886L LUT886L Graphic MMU LUT entry 886 low 0x2BB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT887H LUT887H Graphic MMU LUT entry 887 high 0x2BBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT887L LUT887L Graphic MMU LUT entry 887 low 0x2BB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT888H LUT888H Graphic MMU LUT entry 888 high 0x2BC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT888L LUT888L Graphic MMU LUT entry 888 low 0x2BC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT889H LUT889H Graphic MMU LUT entry 889 high 0x2BCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT889L LUT889L Graphic MMU LUT entry 889 low 0x2BC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT88H LUT88H Graphic MMU LUT entry 88 high 0x12C4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT88L LUT88L Graphic MMU LUT entry 88 low 0x12C0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT890H LUT890H Graphic MMU LUT entry 890 high 0x2BD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT890L LUT890L Graphic MMU LUT entry 890 low 0x2BD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT891H LUT891H Graphic MMU LUT entry 891 high 0x2BDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT891L LUT891L Graphic MMU LUT entry 891 low 0x2BD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT892H LUT892H Graphic MMU LUT entry 892 high 0x2BE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT892L LUT892L Graphic MMU LUT entry 892 low 0x2BE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT893H LUT893H Graphic MMU LUT entry 893 high 0x2BEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT893L LUT893L Graphic MMU LUT entry 893 low 0x2BE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT894H LUT894H Graphic MMU LUT entry 894 high 0x2BF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT894L LUT894L Graphic MMU LUT entry 894 low 0x2BF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT895H LUT895H Graphic MMU LUT entry 895 high 0x2BFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT895L LUT895L Graphic MMU LUT entry 895 low 0x2BF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT896H LUT896H Graphic MMU LUT entry 896 high 0x2C04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT896L LUT896L Graphic MMU LUT entry 896 low 0x2C00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT897H LUT897H Graphic MMU LUT entry 897 high 0x2C0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT897L LUT897L Graphic MMU LUT entry 897 low 0x2C08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT898H LUT898H Graphic MMU LUT entry 898 high 0x2C14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT898L LUT898L Graphic MMU LUT entry 898 low 0x2C10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT899H LUT899H Graphic MMU LUT entry 899 high 0x2C1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT899L LUT899L Graphic MMU LUT entry 899 low 0x2C18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT89H LUT89H Graphic MMU LUT entry 89 high 0x12CC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT89L LUT89L Graphic MMU LUT entry 89 low 0x12C8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT8H LUT8H Graphic MMU LUT entry 8 high 0x1044 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT8L LUT8L Graphic MMU LUT entry 8 low 0x1040 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT900H LUT900H Graphic MMU LUT entry 900 high 0x2C24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT900L LUT900L Graphic MMU LUT entry 900 low 0x2C20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT901H LUT901H Graphic MMU LUT entry 901 high 0x2C2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT901L LUT901L Graphic MMU LUT entry 901 low 0x2C28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT902H LUT902H Graphic MMU LUT entry 902 high 0x2C34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT902L LUT902L Graphic MMU LUT entry 902 low 0x2C30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT903H LUT903H Graphic MMU LUT entry 903 high 0x2C3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT903L LUT903L Graphic MMU LUT entry 903 low 0x2C38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT904H LUT904H Graphic MMU LUT entry 904 high 0x2C44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT904L LUT904L Graphic MMU LUT entry 904 low 0x2C40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT905H LUT905H Graphic MMU LUT entry 905 high 0x2C4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT905L LUT905L Graphic MMU LUT entry 905 low 0x2C48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT906H LUT906H Graphic MMU LUT entry 906 high 0x2C54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT906L LUT906L Graphic MMU LUT entry 906 low 0x2C50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT907H LUT907H Graphic MMU LUT entry 907 high 0x2C5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT907L LUT907L Graphic MMU LUT entry 907 low 0x2C58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT908H LUT908H Graphic MMU LUT entry 908 high 0x2C64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT908L LUT908L Graphic MMU LUT entry 908 low 0x2C60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT909H LUT909H Graphic MMU LUT entry 909 high 0x2C6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT909L LUT909L Graphic MMU LUT entry 909 low 0x2C68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT90H LUT90H Graphic MMU LUT entry 90 high 0x12D4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT90L LUT90L Graphic MMU LUT entry 90 low 0x12D0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT910H LUT910H Graphic MMU LUT entry 910 high 0x2C74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT910L LUT910L Graphic MMU LUT entry 910 low 0x2C70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT911H LUT911H Graphic MMU LUT entry 911 high 0x2C7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT911L LUT911L Graphic MMU LUT entry 911 low 0x2C78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT912H LUT912H Graphic MMU LUT entry 912 high 0x2C84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT912L LUT912L Graphic MMU LUT entry 912 low 0x2C80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT913H LUT913H Graphic MMU LUT entry 913 high 0x2C8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT913L LUT913L Graphic MMU LUT entry 913 low 0x2C88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT914H LUT914H Graphic MMU LUT entry 914 high 0x2C94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT914L LUT914L Graphic MMU LUT entry 914 low 0x2C90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT915H LUT915H Graphic MMU LUT entry 915 high 0x2C9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT915L LUT915L Graphic MMU LUT entry 915 low 0x2C98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT916H LUT916H Graphic MMU LUT entry 916 high 0x2CA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT916L LUT916L Graphic MMU LUT entry 916 low 0x2CA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT917H LUT917H Graphic MMU LUT entry 917 high 0x2CAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT917L LUT917L Graphic MMU LUT entry 917 low 0x2CA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT918H LUT918H Graphic MMU LUT entry 918 high 0x2CB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT918L LUT918L Graphic MMU LUT entry 918 low 0x2CB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT919H LUT919H Graphic MMU LUT entry 919 high 0x2CBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT919L LUT919L Graphic MMU LUT entry 919 low 0x2CB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT91H LUT91H Graphic MMU LUT entry 91 high 0x12DC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT91L LUT91L Graphic MMU LUT entry 91 low 0x12D8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT920H LUT920H Graphic MMU LUT entry 920 high 0x2CC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT920L LUT920L Graphic MMU LUT entry 920 low 0x2CC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT921H LUT921H Graphic MMU LUT entry 921 high 0x2CCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT921L LUT921L Graphic MMU LUT entry 921 low 0x2CC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT922H LUT922H Graphic MMU LUT entry 922 high 0x2CD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT922L LUT922L Graphic MMU LUT entry 922 low 0x2CD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT923H LUT923H Graphic MMU LUT entry 923 high 0x2CDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT923L LUT923L Graphic MMU LUT entry 923 low 0x2CD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT924H LUT924H Graphic MMU LUT entry 924 high 0x2CE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT924L LUT924L Graphic MMU LUT entry 924 low 0x2CE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT925H LUT925H Graphic MMU LUT entry 925 high 0x2CEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT925L LUT925L Graphic MMU LUT entry 925 low 0x2CE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT926H LUT926H Graphic MMU LUT entry 926 high 0x2CF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT926L LUT926L Graphic MMU LUT entry 926 low 0x2CF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT927H LUT927H Graphic MMU LUT entry 927 high 0x2CFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT927L LUT927L Graphic MMU LUT entry 927 low 0x2CF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT928H LUT928H Graphic MMU LUT entry 928 high 0x2D04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT928L LUT928L Graphic MMU LUT entry 928 low 0x2D00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT929H LUT929H Graphic MMU LUT entry 929 high 0x2D0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT929L LUT929L Graphic MMU LUT entry 929 low 0x2D08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT92H LUT92H Graphic MMU LUT entry 92 high 0x12E4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT92L LUT92L Graphic MMU LUT entry 92 low 0x12E0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT930H LUT930H Graphic MMU LUT entry 930 high 0x2D14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT930L LUT930L Graphic MMU LUT entry 930 low 0x2D10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT931H LUT931H Graphic MMU LUT entry 931 high 0x2D1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT931L LUT931L Graphic MMU LUT entry 931 low 0x2D18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT932H LUT932H Graphic MMU LUT entry 932 high 0x2D24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT932L LUT932L Graphic MMU LUT entry 932 low 0x2D20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT933H LUT933H Graphic MMU LUT entry 933 high 0x2D2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT933L LUT933L Graphic MMU LUT entry 933 low 0x2D28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT934H LUT934H Graphic MMU LUT entry 934 high 0x2D34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT934L LUT934L Graphic MMU LUT entry 934 low 0x2D30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT935H LUT935H Graphic MMU LUT entry 935 high 0x2D3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT935L LUT935L Graphic MMU LUT entry 935 low 0x2D38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT936H LUT936H Graphic MMU LUT entry 936 high 0x2D44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT936L LUT936L Graphic MMU LUT entry 936 low 0x2D40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT937H LUT937H Graphic MMU LUT entry 937 high 0x2D4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT937L LUT937L Graphic MMU LUT entry 937 low 0x2D48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT938H LUT938H Graphic MMU LUT entry 938 high 0x2D54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT938L LUT938L Graphic MMU LUT entry 938 low 0x2D50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT939H LUT939H Graphic MMU LUT entry 939 high 0x2D5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT939L LUT939L Graphic MMU LUT entry 939 low 0x2D58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT93H LUT93H Graphic MMU LUT entry 93 high 0x12EC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT93L LUT93L Graphic MMU LUT entry 93 low 0x12E8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT940H LUT940H Graphic MMU LUT entry 940 high 0x2D64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT940L LUT940L Graphic MMU LUT entry 940 low 0x2D60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT941H LUT941H Graphic MMU LUT entry 941 high 0x2D6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT941L LUT941L Graphic MMU LUT entry 941 low 0x2D68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT942H LUT942H Graphic MMU LUT entry 942 high 0x2D74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT942L LUT942L Graphic MMU LUT entry 942 low 0x2D70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT943H LUT943H Graphic MMU LUT entry 943 high 0x2D7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT943L LUT943L Graphic MMU LUT entry 943 low 0x2D78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT944H LUT944H Graphic MMU LUT entry 944 high 0x2D84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT944L LUT944L Graphic MMU LUT entry 944 low 0x2D80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT945H LUT945H Graphic MMU LUT entry 945 high 0x2D8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT945L LUT945L Graphic MMU LUT entry 945 low 0x2D88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT946H LUT946H Graphic MMU LUT entry 946 high 0x2D94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT946L LUT946L Graphic MMU LUT entry 946 low 0x2D90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT947H LUT947H Graphic MMU LUT entry 947 high 0x2D9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT947L LUT947L Graphic MMU LUT entry 947 low 0x2D98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT948H LUT948H Graphic MMU LUT entry 948 high 0x2DA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT948L LUT948L Graphic MMU LUT entry 948 low 0x2DA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT949H LUT949H Graphic MMU LUT entry 949 high 0x2DAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT949L LUT949L Graphic MMU LUT entry 949 low 0x2DA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT94H LUT94H Graphic MMU LUT entry 94 high 0x12F4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT94L LUT94L Graphic MMU LUT entry 94 low 0x12F0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT950H LUT950H Graphic MMU LUT entry 950 high 0x2DB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT950L LUT950L Graphic MMU LUT entry 950 low 0x2DB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT951H LUT951H Graphic MMU LUT entry 951 high 0x2DBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT951L LUT951L Graphic MMU LUT entry 951 low 0x2DB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT952H LUT952H Graphic MMU LUT entry 952 high 0x2DC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT952L LUT952L Graphic MMU LUT entry 952 low 0x2DC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT953H LUT953H Graphic MMU LUT entry 953 high 0x2DCC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT953L LUT953L Graphic MMU LUT entry 953 low 0x2DC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT954H LUT954H Graphic MMU LUT entry 954 high 0x2DD4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT954L LUT954L Graphic MMU LUT entry 954 low 0x2DD0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT955H LUT955H Graphic MMU LUT entry 955 high 0x2DDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT955L LUT955L Graphic MMU LUT entry 955 low 0x2DD8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT956H LUT956H Graphic MMU LUT entry 956 high 0x2DE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT956L LUT956L Graphic MMU LUT entry 956 low 0x2DE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT957H LUT957H Graphic MMU LUT entry 957 high 0x2DEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT957L LUT957L Graphic MMU LUT entry 957 low 0x2DE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT958H LUT958H Graphic MMU LUT entry 958 high 0x2DF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT958L LUT958L Graphic MMU LUT entry 958 low 0x2DF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT959H LUT959H Graphic MMU LUT entry 959 high 0x2DFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT959L LUT959L Graphic MMU LUT entry 959 low 0x2DF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT95H LUT95H Graphic MMU LUT entry 95 high 0x12FC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT95L LUT95L Graphic MMU LUT entry 95 low 0x12F8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT960H LUT960H Graphic MMU LUT entry 960 high 0x2E04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT960L LUT960L Graphic MMU LUT entry 960 low 0x2E00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT961H LUT961H Graphic MMU LUT entry 961 high 0x2E0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT961L LUT961L Graphic MMU LUT entry 961 low 0x2E08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT962H LUT962H Graphic MMU LUT entry 962 high 0x2E14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT962L LUT962L Graphic MMU LUT entry 962 low 0x2E10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT963H LUT963H Graphic MMU LUT entry 963 high 0x2E1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT963L LUT963L Graphic MMU LUT entry 963 low 0x2E18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT964H LUT964H Graphic MMU LUT entry 964 high 0x2E24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT964L LUT964L Graphic MMU LUT entry 964 low 0x2E20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT965H LUT965H Graphic MMU LUT entry 965 high 0x2E2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT965L LUT965L Graphic MMU LUT entry 965 low 0x2E28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT966H LUT966H Graphic MMU LUT entry 966 high 0x2E34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT966L LUT966L Graphic MMU LUT entry 966 low 0x2E30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT967H LUT967H Graphic MMU LUT entry 967 high 0x2E3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT967L LUT967L Graphic MMU LUT entry 967 low 0x2E38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT968H LUT968H Graphic MMU LUT entry 968 high 0x2E44 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT968L LUT968L Graphic MMU LUT entry 968 low 0x2E40 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT969H LUT969H Graphic MMU LUT entry 969 high 0x2E4C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT969L LUT969L Graphic MMU LUT entry 969 low 0x2E48 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT96H LUT96H Graphic MMU LUT entry 96 high 0x1304 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT96L LUT96L Graphic MMU LUT entry 96 low 0x1300 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT970H LUT970H Graphic MMU LUT entry 970 high 0x2E54 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT970L LUT970L Graphic MMU LUT entry 970 low 0x2E50 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT971H LUT971H Graphic MMU LUT entry 971 high 0x2E5C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT971L LUT971L Graphic MMU LUT entry 971 low 0x2E58 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT972H LUT972H Graphic MMU LUT entry 972 high 0x2E64 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT972L LUT972L Graphic MMU LUT entry 972 low 0x2E60 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT973H LUT973H Graphic MMU LUT entry 973 high 0x2E6C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT973L LUT973L Graphic MMU LUT entry 973 low 0x2E68 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT974H LUT974H Graphic MMU LUT entry 974 high 0x2E74 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT974L LUT974L Graphic MMU LUT entry 974 low 0x2E70 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT975H LUT975H Graphic MMU LUT entry 975 high 0x2E7C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT975L LUT975L Graphic MMU LUT entry 975 low 0x2E78 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT976H LUT976H Graphic MMU LUT entry 976 high 0x2E84 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT976L LUT976L Graphic MMU LUT entry 976 low 0x2E80 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT977H LUT977H Graphic MMU LUT entry 977 high 0x2E8C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT977L LUT977L Graphic MMU LUT entry 977 low 0x2E88 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT978H LUT978H Graphic MMU LUT entry 978 high 0x2E94 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT978L LUT978L Graphic MMU LUT entry 978 low 0x2E90 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT979H LUT979H Graphic MMU LUT entry 979 high 0x2E9C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT979L LUT979L Graphic MMU LUT entry 979 low 0x2E98 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT97H LUT97H Graphic MMU LUT entry 97 high 0x130C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT97L LUT97L Graphic MMU LUT entry 97 low 0x1308 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT980H LUT980H Graphic MMU LUT entry 980 high 0x2EA4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT980L LUT980L Graphic MMU LUT entry 980 low 0x2EA0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT981H LUT981H Graphic MMU LUT entry 981 high 0x2EAC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT981L LUT981L Graphic MMU LUT entry 981 low 0x2EA8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT982H LUT982H Graphic MMU LUT entry 982 high 0x2EB4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT982L LUT982L Graphic MMU LUT entry 982 low 0x2EB0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT983H LUT983H Graphic MMU LUT entry 983 high 0x2EBC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT983L LUT983L Graphic MMU LUT entry 983 low 0x2EB8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT984H LUT984H Graphic MMU LUT entry 984 high 0x2EC4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT984L LUT984L Graphic MMU LUT entry 984 low 0x2EC0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT985H LUT985H Graphic MMU LUT entry 985 high 0x2ECC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT985L LUT985L Graphic MMU LUT entry 985 low 0x2EC8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT986H LUT986H Graphic MMU LUT entry 986 high 0x2ED4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT986L LUT986L Graphic MMU LUT entry 986 low 0x2ED0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT987H LUT987H Graphic MMU LUT entry 987 high 0x2EDC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT987L LUT987L Graphic MMU LUT entry 987 low 0x2ED8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT988H LUT988H Graphic MMU LUT entry 988 high 0x2EE4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT988L LUT988L Graphic MMU LUT entry 988 low 0x2EE0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT989H LUT989H Graphic MMU LUT entry 989 high 0x2EEC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT989L LUT989L Graphic MMU LUT entry 989 low 0x2EE8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT98H LUT98H Graphic MMU LUT entry 98 high 0x1314 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT98L LUT98L Graphic MMU LUT entry 98 low 0x1310 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT990H LUT990H Graphic MMU LUT entry 990 high 0x2EF4 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT990L LUT990L Graphic MMU LUT entry 990 low 0x2EF0 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT991H LUT991H Graphic MMU LUT entry 991 high 0x2EFC 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT991L LUT991L Graphic MMU LUT entry 991 low 0x2EF8 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT992H LUT992H Graphic MMU LUT entry 992 high 0x2F04 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT992L LUT992L Graphic MMU LUT entry 992 low 0x2F00 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT993H LUT993H Graphic MMU LUT entry 993 high 0x2F0C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT993L LUT993L Graphic MMU LUT entry 993 low 0x2F08 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT994H LUT994H Graphic MMU LUT entry 994 high 0x2F14 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT994L LUT994L Graphic MMU LUT entry 994 low 0x2F10 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT995H LUT995H Graphic MMU LUT entry 995 high 0x2F1C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT995L LUT995L Graphic MMU LUT entry 995 low 0x2F18 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT996H LUT996H Graphic MMU LUT entry 996 high 0x2F24 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT996L LUT996L Graphic MMU LUT entry 996 low 0x2F20 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT997H LUT997H Graphic MMU LUT entry 997 high 0x2F2C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT997L LUT997L Graphic MMU LUT entry 997 low 0x2F28 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT998H LUT998H Graphic MMU LUT entry 998 high 0x2F34 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT998L LUT998L Graphic MMU LUT entry 998 low 0x2F30 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT999H LUT999H Graphic MMU LUT entry 999 high 0x2F3C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT999L LUT999L Graphic MMU LUT entry 999 low 0x2F38 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT99H LUT99H Graphic MMU LUT entry 99 high 0x131C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT99L LUT99L Graphic MMU LUT entry 99 low 0x1318 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 LUT9H LUT9H Graphic MMU LUT entry 9 high 0x104C 32 read-write n 0x0 0x0 LO Line offset 4 18 LUT9L LUT9L Graphic MMU LUT entry 9 low 0x1048 32 read-write n 0x0 0x0 EN Enable 0 1 FVB First Valid Block 8 8 LVB Last Valid Block 16 8 SIDR SIDR Graphic MMU size identification register 0xFFC 32 read-only n 0x0 0x0 SID Size and ID 0 32 SR SR Graphic MMU status register 0x4 32 read-only n 0x0 0x0 AMEF AHB master error flag 4 1 B0OF Buffer 0 overflow flag 0 1 B1OF Buffer 1 overflow flag 1 1 B2OF Buffer 2 overflow flag 2 1 B3OF Buffer 3 overflow flag 3 1 VERR VERR Graphic MMU version register 0xFF4 32 read-only n 0x0 0x0 MAJREV Major revision 4 4 MINREV Minor revision 0 4 GPIOA General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOB General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOC General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOD General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOE General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOF General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOG General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOH General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 ASCR ASCR GPIO port analog switch control register 0x2C 32 read-write n 0x0 0x0 ASC0 Port analog switch control 0 1 ASC1 Port analog switch control 1 1 ASC10 Port analog switch control 10 1 ASC11 Port analog switch control 11 1 ASC12 Port analog switch control 12 1 ASC13 Port analog switch control 13 1 ASC14 Port analog switch control 14 1 ASC15 Port analog switch control 15 1 ASC2 Port analog switch control 2 1 ASC3 Port analog switch control 3 1 ASC4 Port analog switch control 4 1 ASC5 Port analog switch control 5 1 ASC6 Port analog switch control 6 1 ASC7 Port analog switch control 7 1 ASC8 Port analog switch control 8 1 ASC9 Port analog switch control 9 1 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOI General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 HASH Hash processor HASH 0x0 0x0 0x400 registers n CR CR control register 0x0 32 read-write n 0x0 0x0 ALGO0 Algorithm selection 7 1 read-write ALGO1 ALGO 18 1 read-write DATATYPE Data type selection 4 2 read-write DINNE DIN not empty 12 1 read-only DMAE DMA enable 3 1 read-write INIT Initialize message digest calculation 2 1 write-only LKEY Long key selection 16 1 read-write MDMAT Multiple DMA Transfers 13 1 read-write MODE Mode selection 6 1 read-write NBW Number of words already pushed 8 4 read-only CSR0 CSR0 context swap registers 0xF8 32 read-write n 0x0 0x0 CSR0 CSR0 0 32 CSR1 CSR1 context swap registers 0xFC 32 read-write n 0x0 0x0 CSR1 CSR1 0 32 CSR10 CSR10 context swap registers 0x120 32 read-write n 0x0 0x0 CSR10 CSR10 0 32 CSR11 CSR11 context swap registers 0x124 32 read-write n 0x0 0x0 CSR11 CSR11 0 32 CSR12 CSR12 context swap registers 0x128 32 read-write n 0x0 0x0 CSR12 CSR12 0 32 CSR13 CSR13 context swap registers 0x12C 32 read-write n 0x0 0x0 CSR13 CSR13 0 32 CSR14 CSR14 context swap registers 0x130 32 read-write n 0x0 0x0 CSR14 CSR14 0 32 CSR15 CSR15 context swap registers 0x134 32 read-write n 0x0 0x0 CSR15 CSR15 0 32 CSR16 CSR16 context swap registers 0x138 32 read-write n 0x0 0x0 CSR16 CSR16 0 32 CSR17 CSR17 context swap registers 0x13C 32 read-write n 0x0 0x0 CSR17 CSR17 0 32 CSR18 CSR18 context swap registers 0x140 32 read-write n 0x0 0x0 CSR18 CSR18 0 32 CSR19 CSR19 context swap registers 0x144 32 read-write n 0x0 0x0 CSR19 CSR19 0 32 CSR2 CSR2 context swap registers 0x100 32 read-write n 0x0 0x0 CSR2 CSR2 0 32 CSR20 CSR20 context swap registers 0x148 32 read-write n 0x0 0x0 CSR20 CSR20 0 32 CSR21 CSR21 context swap registers 0x14C 32 read-write n 0x0 0x0 CSR21 CSR21 0 32 CSR22 CSR22 context swap registers 0x150 32 read-write n 0x0 0x0 CSR22 CSR22 0 32 CSR23 CSR23 context swap registers 0x154 32 read-write n 0x0 0x0 CSR23 CSR23 0 32 CSR24 CSR24 context swap registers 0x158 32 read-write n 0x0 0x0 CSR24 CSR24 0 32 CSR25 CSR25 context swap registers 0x15C 32 read-write n 0x0 0x0 CSR25 CSR25 0 32 CSR26 CSR26 context swap registers 0x160 32 read-write n 0x0 0x0 CSR26 CSR26 0 32 CSR27 CSR27 context swap registers 0x164 32 read-write n 0x0 0x0 CSR27 CSR27 0 32 CSR28 CSR28 context swap registers 0x168 32 read-write n 0x0 0x0 CSR28 CSR28 0 32 CSR29 CSR29 context swap registers 0x16C 32 read-write n 0x0 0x0 CSR29 CSR29 0 32 CSR3 CSR3 context swap registers 0x104 32 read-write n 0x0 0x0 CSR3 CSR3 0 32 CSR30 CSR30 context swap registers 0x170 32 read-write n 0x0 0x0 CSR30 CSR30 0 32 CSR31 CSR31 context swap registers 0x174 32 read-write n 0x0 0x0 CSR31 CSR31 0 32 CSR32 CSR32 context swap registers 0x178 32 read-write n 0x0 0x0 CSR32 CSR32 0 32 CSR33 CSR33 context swap registers 0x17C 32 read-write n 0x0 0x0 CSR33 CSR33 0 32 CSR34 CSR34 context swap registers 0x180 32 read-write n 0x0 0x0 CSR34 CSR34 0 32 CSR35 CSR35 context swap registers 0x184 32 read-write n 0x0 0x0 CSR35 CSR35 0 32 CSR36 CSR36 context swap registers 0x188 32 read-write n 0x0 0x0 CSR36 CSR36 0 32 CSR37 CSR37 context swap registers 0x18C 32 read-write n 0x0 0x0 CSR37 CSR37 0 32 CSR38 CSR38 context swap registers 0x190 32 read-write n 0x0 0x0 CSR38 CSR38 0 32 CSR39 CSR39 context swap registers 0x194 32 read-write n 0x0 0x0 CSR39 CSR39 0 32 CSR4 CSR4 context swap registers 0x108 32 read-write n 0x0 0x0 CSR4 CSR4 0 32 CSR40 CSR40 context swap registers 0x198 32 read-write n 0x0 0x0 CSR40 CSR40 0 32 CSR41 CSR41 context swap registers 0x19C 32 read-write n 0x0 0x0 CSR41 CSR41 0 32 CSR42 CSR42 context swap registers 0x1A0 32 read-write n 0x0 0x0 CSR42 CSR42 0 32 CSR43 CSR43 context swap registers 0x1A4 32 read-write n 0x0 0x0 CSR43 CSR43 0 32 CSR44 CSR44 context swap registers 0x1A8 32 read-write n 0x0 0x0 CSR44 CSR44 0 32 CSR45 CSR45 context swap registers 0x1AC 32 read-write n 0x0 0x0 CSR45 CSR45 0 32 CSR46 CSR46 context swap registers 0x1B0 32 read-write n 0x0 0x0 CSR46 CSR46 0 32 CSR47 CSR47 context swap registers 0x1B4 32 read-write n 0x0 0x0 CSR47 CSR47 0 32 CSR48 CSR48 context swap registers 0x1B8 32 read-write n 0x0 0x0 CSR48 CSR48 0 32 CSR49 CSR49 context swap registers 0x1BC 32 read-write n 0x0 0x0 CSR49 CSR49 0 32 CSR5 CSR5 context swap registers 0x10C 32 read-write n 0x0 0x0 CSR5 CSR5 0 32 CSR50 CSR50 context swap registers 0x1C0 32 read-write n 0x0 0x0 CSR50 CSR50 0 32 CSR51 CSR51 context swap registers 0x1C4 32 read-write n 0x0 0x0 CSR51 CSR51 0 32 CSR52 CSR52 context swap registers 0x1C8 32 read-write n 0x0 0x0 CSR52 CSR52 0 32 CSR53 CSR53 context swap registers 0x1CC 32 read-write n 0x0 0x0 CSR53 CSR53 0 32 CSR6 CSR6 context swap registers 0x110 32 read-write n 0x0 0x0 CSR6 CSR6 0 32 CSR7 CSR7 context swap registers 0x114 32 read-write n 0x0 0x0 CSR7 CSR7 0 32 CSR8 CSR8 context swap registers 0x118 32 read-write n 0x0 0x0 CSR8 CSR8 0 32 CSR9 CSR9 context swap registers 0x11C 32 read-write n 0x0 0x0 CSR9 CSR9 0 32 DIN DIN data input register 0x4 32 read-write n 0x0 0x0 DATAIN Data input 0 32 HR0 HR0 digest registers 0xC 32 read-only n 0x0 0x0 H0 H0 0 32 HR1 HASH_HR1 read-only 0x314 32 read-only n 0x0 0x0 H1 H1 0 32 HR2 HASH_HR2 read-only 0x318 32 read-only n 0x0 0x0 H2 H2 0 32 HR3 HASH_HR3 read-only 0x31C 32 read-only n 0x0 0x0 H3 H3 0 32 HR4 HASH_HR4 read-only 0x320 32 read-only n 0x0 0x0 H4 H4 0 32 HR5 HASH_HR5 read-only 0x324 32 read-only n 0x0 0x0 H5 H5 0 32 HR6 HASH_HR6 read-only 0x328 32 read-only n 0x0 0x0 H6 H6 0 32 HR7 HASH_HR7 read-only 0x32C 32 read-only n 0x0 0x0 H7 H7 0 32 IMR IMR interrupt enable register 0x20 32 read-write n 0x0 0x0 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 32 read-write n 0x0 0x0 BUSY Busy bit 3 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write DMAS DMA Status 2 1 read-only STR STR start register 0x8 32 read-write n 0x0 0x0 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write I2C1 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C2 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C3 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C4 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C4_ER I2C4 error interrupt 83 I2C4_EV I2C4 event interrupt 84 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 IWDG Independent watchdog IWDG 0x0 0x0 0x400 registers n KR KR Key register 0x0 32 write-only n 0x0 0x0 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 32 read-write n 0x0 0x0 RL Watchdog counter reload value 0 12 SR SR Status register 0xC 32 read-only n 0x0 0x0 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 WINR WINR Window register 0x10 32 read-write n 0x0 0x0 WIN Watchdog counter window value 0 12 LPTIM1 Low power timer LPTIM 0x0 0x0 0x400 registers n LPTIM1 LP TIM1 interrupt 65 ARR ARR Autoreload Register 0x18 32 read-write n 0x0 0x0 ARR Auto reload value 0 16 CFGR CFGR Configuration Register 0xC 32 read-write n 0x0 0x0 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 COUNTMODE counter mode enabled 23 1 ENC Encoder mode enable 24 1 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 TIMOUT Timeout enable 19 1 TRGFLT Configurable digital filter for trigger 6 2 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 WAVE Waveform shape 20 1 WAVPOL Waveform shape polarity 21 1 CMP CMP Compare Register 0x14 32 read-write n 0x0 0x0 CMP Compare value 0 16 CNT CNT Counter Register 0x1C 32 read-only n 0x0 0x0 CNT Counter value 0 16 CR CR Control Register 0x10 32 read-write n 0x0 0x0 CNTSTRT Timer start in continuous mode 2 1 ENABLE LPTIM Enable 0 1 SNGSTRT LPTIM start in single mode 1 1 ICR ICR Interrupt Clear Register 0x4 32 write-only n 0x0 0x0 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPMCF compare match Clear Flag 0 1 CMPOKCF Compare register update OK Clear Flag 3 1 DOWNCF Direction change to down Clear Flag 6 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 UPCF Direction change to UP Clear Flag 5 1 IER IER Interrupt Enable Register 0x8 32 read-write n 0x0 0x0 ARRMIE Autoreload match Interrupt Enable 1 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPMIE Compare match Interrupt Enable 0 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 DOWNIE Direction change to down Interrupt Enable 6 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 UPIE Direction change to UP Interrupt Enable 5 1 ISR ISR Interrupt and Status Register 0x0 32 read-only n 0x0 0x0 ARRM Autoreload match 1 1 ARROK Autoreload register update OK 4 1 CMPM Compare match 0 1 CMPOK Compare register update OK 3 1 DOWN Counter direction change up to down 6 1 EXTTRIG External trigger edge event 2 1 UP Counter direction change down to up 5 1 LPTIM2 Low power timer LPTIM 0x0 0x0 0x400 registers n LPTIM2 LP TIM2 interrupt 66 ARR ARR Autoreload Register 0x18 32 read-write n 0x0 0x0 ARR Auto reload value 0 16 CFGR CFGR Configuration Register 0xC 32 read-write n 0x0 0x0 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 COUNTMODE counter mode enabled 23 1 ENC Encoder mode enable 24 1 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 TIMOUT Timeout enable 19 1 TRGFLT Configurable digital filter for trigger 6 2 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 WAVE Waveform shape 20 1 WAVPOL Waveform shape polarity 21 1 CMP CMP Compare Register 0x14 32 read-write n 0x0 0x0 CMP Compare value 0 16 CNT CNT Counter Register 0x1C 32 read-only n 0x0 0x0 CNT Counter value 0 16 CR CR Control Register 0x10 32 read-write n 0x0 0x0 CNTSTRT Timer start in continuous mode 2 1 ENABLE LPTIM Enable 0 1 SNGSTRT LPTIM start in single mode 1 1 ICR ICR Interrupt Clear Register 0x4 32 write-only n 0x0 0x0 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPMCF compare match Clear Flag 0 1 CMPOKCF Compare register update OK Clear Flag 3 1 DOWNCF Direction change to down Clear Flag 6 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 UPCF Direction change to UP Clear Flag 5 1 IER IER Interrupt Enable Register 0x8 32 read-write n 0x0 0x0 ARRMIE Autoreload match Interrupt Enable 1 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPMIE Compare match Interrupt Enable 0 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 DOWNIE Direction change to down Interrupt Enable 6 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 UPIE Direction change to UP Interrupt Enable 5 1 ISR ISR Interrupt and Status Register 0x0 32 read-only n 0x0 0x0 ARRM Autoreload match 1 1 ARROK Autoreload register update OK 4 1 CMPM Compare match 0 1 CMPOK Compare register update OK 3 1 DOWN Counter direction change up to down 6 1 EXTTRIG External trigger edge event 2 1 UP Counter direction change down to up 5 1 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n LPUART1 LPUART1 global interrupt 70 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR BRR 0 20 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 MSBFIRST Most significant bit first 19 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 FE FE 1 1 IDLE IDLE 4 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 LTCD Liquid crystal display controller LCD 0x0 0x0 0x400 registers n LCD_TFT LTDC global interrupt 91 LCD_TFT_ER LTDC global error interrupt 92 AWCR AWCR LTDC Active Width Configuration Register 0x10 32 read-write n 0x0 0x0 AAH Accumulated Active Height (in units of horizontal scan line) 0 11 AAW Accumulated Active Width (in units of pixel clock period) 16 12 BCCR BCCR LTDC Background Color Configuration Register 0x2C 32 read-write n 0x0 0x0 BCBLUE Background Color Blue value 0 8 BCGREEN Background Color Green value 8 8 BCRED Background Color Red value 16 8 BPCR BPCR LTDC Back Porch Configuration Register 0xC 32 read-write n 0x0 0x0 AHBP Accumulated Horizontal back porch (in units of pixel clock period) 16 12 AVBP Accumulated Vertical back porch (in units of horizontal scan line) 0 11 CDSR CDSR LTDC Current Display Status Register 0x48 32 read-only n 0x0 0x0 HDES Horizontal Data Enable display Status 1 1 HSYNCS Horizontal Synchronization display Status 3 1 VDES Vertical Data Enable display Status 0 1 VSYNCS Vertical Synchronization display Status 2 1 CPSR CPSR LTDC Current Position Status Register 0x44 32 read-only n 0x0 0x0 CXPOS Current X Position 16 16 CYPOS Current Y Position 0 16 GCR GCR LTDC Global Control Register 0x18 32 read-write n 0x0 0x0 DBW Dither Blue Width 4 3 read-only DEN Dither Enable 16 1 read-write DEPOL Not Data Enable Polarity 29 1 read-write DGW Dither Green Width 8 3 read-only DRW Dither Red Width 12 3 read-only HSPOL Horizontal Synchronization Polarity 31 1 read-write LTDCEN LCD-TFT controller enable bit 0 1 read-write PCPOL Pixel Clock Polarity 28 1 read-write VSPOL Vertical Synchronization Polarity 30 1 read-write ICR ICR LTDC Interrupt Clear Register 0x3C 32 write-only n 0x0 0x0 CFUIF Clears the FIFO Underrun Interrupt flag 1 1 CLIF Clears the Line Interrupt Flag 0 1 CRRIF Clears Register Reload Interrupt Flag 3 1 CTERRIF Clears the Transfer Error Interrupt Flag 2 1 IER IER LTDC Interrupt Enable Register 0x34 32 read-write n 0x0 0x0 FUIE FIFO Underrun Interrupt Enable 1 1 LIE Line Interrupt Enable 0 1 RRIE Register Reload interrupt enable 3 1 TERRIE Transfer Error Interrupt Enable 2 1 ISR ISR LTDC Interrupt Status Register 0x38 32 read-only n 0x0 0x0 FUIF FIFO Underrun Interrupt flag 1 1 LIF Line Interrupt flag 0 1 RRIF Register Reload Interrupt Flag 3 1 TERRIF Transfer Error interrupt flag 2 1 L1BFCR L1BFCR LTDC Layer Blending Factors Configuration Register 0xA0 32 read-write n 0x0 0x0 BF1 Blending Factor 1 8 3 BF2 Blending Factor 2 0 3 L1CACR L1CACR LTDC Layer Constant Alpha Configuration Register 0x98 32 read-write n 0x0 0x0 CONSTA Constant Alpha 0 8 L1CFBAR L1CFBAR LTDC Layer Color Frame Buffer Address Register 0xAC 32 read-write n 0x0 0x0 CFBADD Color Frame Buffer Start Address 0 32 L1CFBLNR L1CFBLNR LTDC Layer ColorFrame Buffer Line Number Register 0xB4 32 read-write n 0x0 0x0 CFBLNBR Frame Buffer Line Number 0 11 L1CFBLR L1CFBLR LTDC Layer Color Frame Buffer Length Register 0xB0 32 read-write n 0x0 0x0 CFBLL Color Frame Buffer Line Length 0 13 CFBP Color Frame Buffer Pitch in bytes 16 13 L1CKCR L1CKCR LTDC Layer Color Keying Configuration Register 0x90 32 read-write n 0x0 0x0 CKBLUE Color Key Blue value 0 8 CKGREEN Color Key Green value 8 8 CKRED Color Key Red value 16 8 L1CLUTWR L1CLUTWR LTDC Layerx CLUT Write Register 0xC4 32 write-only n 0x0 0x0 BLUE Blue value 0 8 CLUTADD CLUT Address 24 8 GREEN Green value 8 8 RED Red value 16 8 L1CR L1CR LTDC Layer Control Register 0x84 32 read-write n 0x0 0x0 CLUTEN Color Look-Up Table Enable 4 1 COLKEN Color Keying Enable 1 1 LEN Layer Enable 0 1 L1DCCR L1DCCR LTDC Layer Default Color Configuration Register 0x9C 32 read-write n 0x0 0x0 DCALPHA Default Color Alpha 24 8 DCBLUE Default Color Blue 0 8 DCGREEN Default Color Green 8 8 DCRED Default Color Red 16 8 L1PFCR L1PFCR LTDC Layer Pixel Format Configuration Register 0x94 32 read-write n 0x0 0x0 PF Pixel Format 0 3 L1WHPCR L1WHPCR LTDC Layer Window Horizontal Position Configuration Register 0x88 32 read-write n 0x0 0x0 WHSPPOS Window Horizontal Stop Position 16 12 WHSTPOS Window Horizontal Start Position 0 12 L1WVPCR L1WVPCR LTDC Layer Window Vertical Position Configuration Register 0x8C 32 read-write n 0x0 0x0 WVSPPOS Window Vertical Stop Position 16 11 WVSTPOS Window Vertical Start Position 0 11 L2BFCR L2BFCR LTDC Layer Blending Factors Configuration Register 0x124 32 read-write n 0x0 0x0 BF1 Blending Factor 1 8 3 BF2 Blending Factor 2 0 3 L2CACR L2CACR LTDC Layer Constant Alpha Configuration Register 0x118 32 read-write n 0x0 0x0 CONSTA Constant Alpha 0 8 L2CFBAR L2CFBAR LTDC Layer Color Frame Buffer Address Register 0x12C 32 read-write n 0x0 0x0 CFBADD Color Frame Buffer Start Address 0 32 L2CFBLNR L2CFBLNR LTDC Layer ColorFrame Buffer Line Number Register 0x134 32 read-write n 0x0 0x0 CFBLNBR Frame Buffer Line Number 0 11 L2CFBLR L2CFBLR LTDC Layer Color Frame Buffer Length Register 0x130 32 read-write n 0x0 0x0 CFBLL Color Frame Buffer Line Length 0 13 CFBP Color Frame Buffer Pitch in bytes 16 13 L2CKCR L2CKCR LTDC Layer Color Keying Configuration Register 0x110 32 read-write n 0x0 0x0 CKBLUE Color Key Blue value 0 8 CKGREEN Color Key Green value 8 8 CKRED Color Key Red value 16 8 L2CLUTWR L2CLUTWR LTDC Layerx CLUT Write Register 0x144 32 write-only n 0x0 0x0 BLUE Blue value 0 8 CLUTADD CLUT Address 24 8 GREEN Green value 8 8 RED Red value 16 8 L2CR L2CR LTDC Layer Control Register 0x104 32 read-write n 0x0 0x0 CLUTEN Color Look-Up Table Enable 4 1 COLKEN Color Keying Enable 1 1 LEN Layer Enable 0 1 L2DCCR L2DCCR LTDC Layer Default Color Configuration Register 0x11C 32 read-write n 0x0 0x0 DCALPHA Default Color Alpha 24 8 DCBLUE Default Color Blue 0 8 DCGREEN Default Color Green 8 8 DCRED Default Color Red 16 8 L2PFCR L2PFCR LTDC Layer Pixel Format Configuration Register 0x114 32 read-write n 0x0 0x0 PF Pixel Format 0 3 L2WHPCR L2WHPCR LTDC Layerx Window Horizontal Position Configuration Register 0x108 32 read-write n 0x0 0x0 WHSPPOS Window Horizontal Stop Position 16 12 WHSTPOS Window Horizontal Start Position 0 12 L2WVPCR L2WVPCR LTDC Layer Window Vertical Position Configuration Register 0x10C 32 read-write n 0x0 0x0 WVSPPOS Window Vertical Stop Position 16 11 WVSTPOS Window Vertical Start Position 0 11 LIPCR LIPCR LTDC Line Interrupt Position Configuration Register 0x40 32 read-write n 0x0 0x0 LIPOS Line Interrupt Position 0 11 SRCR SRCR LTDC Shadow Reload Configuration Register 0x24 32 read-write n 0x0 0x0 IMR Immediate Reload 0 1 VBR Vertical Blanking Reload 1 1 SSCR SSCR LTDC Synchronization Size Configuration Register 0x8 32 read-write n 0x0 0x0 HSW Horizontal Synchronization Width (in units of pixel clock period) 16 12 VSH Vertical Synchronization Height (in units of horizontal scan line) 0 11 TWCR TWCR LTDC Total Width Configuration Register 0x14 32 read-write n 0x0 0x0 TOTALH Total Height (in units of horizontal scan line) 0 11 TOTALW Total Width (in units of pixel clock period) 16 12 MPU Memory protection unit MPU 0x0 0x0 0x15 registers n CTRL MPU_CTRL MPU control register 0x4 32 read-write n 0x0 0x0 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RASR MPU_RASR MPU region attribute and size register 0x10 32 read-write n 0x0 0x0 AP Access permission 24 3 B memory attribute 16 1 C memory attribute 17 1 ENABLE Region enable bit. 0 1 S Shareable memory attribute 18 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 TEX memory attribute 19 3 XN Instruction access disable bit 28 1 RBAR MPU_RBAR MPU region base address register 0xC 32 read-write n 0x0 0x0 ADDR Region base address field 5 27 REGION MPU region field 0 4 VALID MPU region number valid 4 1 RNR MPU_RNR MPU region number register 0x8 32 read-write n 0x0 0x0 REGION MPU region 0 8 TYPER MPU_TYPER MPU type register 0x0 32 read-only n 0x0 0x0 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 SEPARATE Separate flag 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x356 registers n 0x0 0x356 registers n IABR0 IABR0 Interrupt Active Bit Register 0x200 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER0 ISER0 Interrupt Set-Enable Register 0x0 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 NVIC_STIR Nested vectored interrupt controller NVIC 0x0 0x0 0x5 registers n STIR STIR Software trigger interrupt register 0x0 32 read-write n 0x0 0x0 INTID Software generated interrupt ID 0 9 OCTOSPI1 OctoSPI OctoSPI 0x0 0x0 0x400 registers n OCTOSPI1 OCTOSPI1 global interrupt 71 ABR ABR alternate bytes register 0x120 32 read-write n 0x0 0x0 ALTERNATE Alternate bytes 0 32 AR AR address register 0x48 32 read-write n 0x0 0x0 ADDRESS ADDRESS 0 32 CCR CCR communication configuration register 0x100 32 read-write n 0x0 0x0 ABDTR Alternate bytes double transfer rate 19 1 ABMODE Alternate byte mode 16 3 ABSIZE Alternate bytes size 20 2 ADDTR Address double transfer rate 11 1 ADMODE Address mode 8 3 ADSIZE Address size 12 2 DDTR Alternate bytes double transfer rate 27 1 DMODE Data mode 24 3 DQSE DQS enable 29 1 IDTR Instruction double transfer rate 3 1 IMODE Instruction mode 0 3 ISIZE Instruction size 4 2 SIOO Send instruction only once mode 31 1 CR CR control register 0x0 32 read-write n 0x0 0x0 ABORT Abort request 1 1 APMS Automatic poll mode stop 22 1 DMAEN DMA enable 2 1 DQM Dual-quad mode 6 1 EN Enable 0 1 FMODE Functional mode 28 2 FSEL FLASH memory selection 7 1 FTHRES IFO threshold level 8 5 FTIE FIFO threshold interrupt enable 18 1 PMM Polling match mode 23 1 SMIE Status match interrupt enable 19 1 TCEN Timeout counter enable 3 1 TCIE Transfer complete interrupt enable 17 1 TEIE Transfer error interrupt enable 16 1 TOIE TimeOut interrupt enable 20 1 DCR1 DCR1 device configuration register 0x8 32 read-write n 0x0 0x0 CKMODE Mode 0 / mode 3 0 1 CSHT Chip-select high time 8 3 DEVSIZE Device size 16 5 FRCK Free running clock 1 1 MTYP Memory type 24 2 DCR2 DCR2 device configuration register 2 0xC 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 8 WRAPSIZE Wrap size 16 3 DCR3 DCR3 device configuration register 3 0x10 32 read-write n 0x0 0x0 CSBOUND CS boundary 16 5 DLR DLR data length register 0x40 32 read-write n 0x0 0x0 DL Data length 0 32 DR DR data register 0x50 32 read-write n 0x0 0x0 DATA Data 0 32 FCR FCR flag clear register 0x24 32 write-only n 0x0 0x0 CSMF Clear status match flag 3 1 CTCF Clear transfer complete flag 1 1 CTEF Clear transfer error flag 0 1 CTOF Clear timeout flag 4 1 HLCR HLCR HyperBusTM latency configuration register 0x200 32 read-write n 0x0 0x0 LM Latency mode 0 1 TACC Access time 8 8 TRWR Read write recovery time 16 8 WZL Write zero latency 1 1 HWCFGR HWCFGR HW configuration register 0x3F0 32 read-only n 0x0 0x0 AXI AXI interface 0 4 FIFO FIFO depth 4 8 IDL ID Length 20 4 MMW Memory map write 24 4 MST Master 28 4 PRES Prescaler 12 8 ID ID identification 0x3F8 32 read-only n 0x0 0x0 ID Identification 0 32 IR IR instruction register 0x110 32 read-write n 0x0 0x0 INSTRUCTION INSTRUCTION 0 32 LPTR LPTR low-power timeout register 0x130 32 read-write n 0x0 0x0 TIMEOUT Timeout period 0 16 MID MID magic ID 0x3FC 32 read-only n 0x0 0x0 MID Magic ID 0 32 PIR PIR polling interval register 0x90 32 read-write n 0x0 0x0 INTERVAL Polling interval 0 16 PSMAR PSMAR polling status match register 0x88 32 read-write n 0x0 0x0 MATCH Status match 0 32 PSMKR PSMKR polling status mask register 0x80 32 read-write n 0x0 0x0 MASK Status mask 0 32 SR SR status register 0x20 32 read-write n 0x0 0x0 BUSY BUSY 5 1 FLEVEL FIFO level 8 6 FTF FIFO threshold flag 2 1 SMF Status match flag 3 1 TCF Transfer complete flag 1 1 TEF Transfer error flag 0 1 TOF Timeout flag 4 1 TCR TCR timing configuration register 0x108 32 read-write n 0x0 0x0 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 VER VER version register 0x3F4 32 read-only n 0x0 0x0 VER Version 0 8 WABR WABR write alternate bytes register 0x1A0 32 read-write n 0x0 0x0 ALTERNATE Alternate bytes 0 32 WCCR WCCR write communication configuration register 0x180 32 read-write n 0x0 0x0 ABDTR Alternate bytes double transfer rate 19 1 ABMODE Alternate byte mode 16 3 ABSIZE Alternate bytes size 20 2 ADDTR Address double transfer rate 11 1 ADMODE Address mode 8 3 ADSIZE Address size 12 2 DDTR alternate bytes double transfer rate 27 1 DMODE Data mode 24 3 DQSE DQS enable 29 1 IDTR Instruction double transfer rate 3 1 IMODE Instruction mode 0 3 ISIZE Instruction size 4 2 SIOO Send instruction only once mode 31 1 WIR WIR write instruction register 0x190 32 read-write n 0x0 0x0 INSTRUCTION INSTRUCTION 0 32 WTCR WTCR write timing configuration register 0x188 32 read-write n 0x0 0x0 DCYC Number of dummy cycles 0 5 OCTOSPI2 OctoSPI OctoSPI 0x0 0x0 0x400 registers n OCTOSPI2 OCTOSPI2 global interrupt 76 ABR ABR alternate bytes register 0x120 32 read-write n 0x0 0x0 ALTERNATE Alternate bytes 0 32 AR AR address register 0x48 32 read-write n 0x0 0x0 ADDRESS ADDRESS 0 32 CCR CCR communication configuration register 0x100 32 read-write n 0x0 0x0 ABDTR Alternate bytes double transfer rate 19 1 ABMODE Alternate byte mode 16 3 ABSIZE Alternate bytes size 20 2 ADDTR Address double transfer rate 11 1 ADMODE Address mode 8 3 ADSIZE Address size 12 2 DDTR Alternate bytes double transfer rate 27 1 DMODE Data mode 24 3 DQSE DQS enable 29 1 IDTR Instruction double transfer rate 3 1 IMODE Instruction mode 0 3 ISIZE Instruction size 4 2 SIOO Send instruction only once mode 31 1 CR CR control register 0x0 32 read-write n 0x0 0x0 ABORT Abort request 1 1 APMS Automatic poll mode stop 22 1 DMAEN DMA enable 2 1 DQM Dual-quad mode 6 1 EN Enable 0 1 FMODE Functional mode 28 2 FSEL FLASH memory selection 7 1 FTHRES IFO threshold level 8 5 FTIE FIFO threshold interrupt enable 18 1 PMM Polling match mode 23 1 SMIE Status match interrupt enable 19 1 TCEN Timeout counter enable 3 1 TCIE Transfer complete interrupt enable 17 1 TEIE Transfer error interrupt enable 16 1 TOIE TimeOut interrupt enable 20 1 DCR1 DCR1 device configuration register 0x8 32 read-write n 0x0 0x0 CKMODE Mode 0 / mode 3 0 1 CSHT Chip-select high time 8 3 DEVSIZE Device size 16 5 FRCK Free running clock 1 1 MTYP Memory type 24 2 DCR2 DCR2 device configuration register 2 0xC 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 8 WRAPSIZE Wrap size 16 3 DCR3 DCR3 device configuration register 3 0x10 32 read-write n 0x0 0x0 CSBOUND CS boundary 16 5 DLR DLR data length register 0x40 32 read-write n 0x0 0x0 DL Data length 0 32 DR DR data register 0x50 32 read-write n 0x0 0x0 DATA Data 0 32 FCR FCR flag clear register 0x24 32 write-only n 0x0 0x0 CSMF Clear status match flag 3 1 CTCF Clear transfer complete flag 1 1 CTEF Clear transfer error flag 0 1 CTOF Clear timeout flag 4 1 HLCR HLCR HyperBusTM latency configuration register 0x200 32 read-write n 0x0 0x0 LM Latency mode 0 1 TACC Access time 8 8 TRWR Read write recovery time 16 8 WZL Write zero latency 1 1 HWCFGR HWCFGR HW configuration register 0x3F0 32 read-only n 0x0 0x0 AXI AXI interface 0 4 FIFO FIFO depth 4 8 IDL ID Length 20 4 MMW Memory map write 24 4 MST Master 28 4 PRES Prescaler 12 8 ID ID identification 0x3F8 32 read-only n 0x0 0x0 ID Identification 0 32 IR IR instruction register 0x110 32 read-write n 0x0 0x0 INSTRUCTION INSTRUCTION 0 32 LPTR LPTR low-power timeout register 0x130 32 read-write n 0x0 0x0 TIMEOUT Timeout period 0 16 MID MID magic ID 0x3FC 32 read-only n 0x0 0x0 MID Magic ID 0 32 PIR PIR polling interval register 0x90 32 read-write n 0x0 0x0 INTERVAL Polling interval 0 16 PSMAR PSMAR polling status match register 0x88 32 read-write n 0x0 0x0 MATCH Status match 0 32 PSMKR PSMKR polling status mask register 0x80 32 read-write n 0x0 0x0 MASK Status mask 0 32 SR SR status register 0x20 32 read-write n 0x0 0x0 BUSY BUSY 5 1 FLEVEL FIFO level 8 6 FTF FIFO threshold flag 2 1 SMF Status match flag 3 1 TCF Transfer complete flag 1 1 TEF Transfer error flag 0 1 TOF Timeout flag 4 1 TCR TCR timing configuration register 0x108 32 read-write n 0x0 0x0 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 VER VER version register 0x3F4 32 read-only n 0x0 0x0 VER Version 0 8 WABR WABR write alternate bytes register 0x1A0 32 read-write n 0x0 0x0 ALTERNATE Alternate bytes 0 32 WCCR WCCR write communication configuration register 0x180 32 read-write n 0x0 0x0 ABDTR Alternate bytes double transfer rate 19 1 ABMODE Alternate byte mode 16 3 ABSIZE Alternate bytes size 20 2 ADDTR Address double transfer rate 11 1 ADMODE Address mode 8 3 ADSIZE Address size 12 2 DDTR alternate bytes double transfer rate 27 1 DMODE Data mode 24 3 DQSE DQS enable 29 1 IDTR Instruction double transfer rate 3 1 IMODE Instruction mode 0 3 ISIZE Instruction size 4 2 SIOO Send instruction only once mode 31 1 WIR WIR write instruction register 0x190 32 read-write n 0x0 0x0 INSTRUCTION INSTRUCTION 0 32 WTCR WTCR write timing configuration register 0x188 32 read-write n 0x0 0x0 DCYC Number of dummy cycles 0 5 OCTOSPIM OctoSPI IO Manager OCTOSPIM 0x0 0x0 0x400 registers n P1CR P1CR OctoSPI IO Manager Port 1 Configuration Register 0x4 32 read-write n 0x0 0x0 CLKEN CLK/CLK Enable for Port 0 1 CLKSRC CLK/CLK Source for Port 1 1 DQSEN DQS Enable for Port 4 1 DQSSRC DQS Source for Port 5 1 IOHEN Enable for Port n 24 1 IOHSRC Source for Port 25 2 IOLEN Enable for Port 16 1 IOLSRC Source for Port 17 2 NCSEN CS Enable for Port 8 1 NCSSRC CS Source for Port 9 1 P2CR P2CR OctoSPI IO Manager Port 2 Configuration Register 0x8 32 read-write n 0x0 0x0 CLKEN CLK/CLK Enable for Port 0 1 CLKSRC CLK/CLK Source for Port 1 1 DQSEN DQS Enable for Port 4 1 DQSSRC DQS Source for Port 5 1 IOHEN Enable for Port n 24 1 IOHSRC Source for Port 25 2 IOLEN Enable for Port 16 1 IOLSRC Source for Port 17 2 NCSEN CS Enable for Port 8 1 NCSSRC CS Source for Port 9 1 OPAMP Operational amplifiers OPAMP 0x0 0x0 0x400 registers n OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 32 read-write n 0x0 0x0 CALON Calibration mode enabled 12 1 CALOUT Operational amplifier calibration output 15 1 CALSEL Calibration selection 13 1 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 OPA_RANGE Operational amplifier power supply range for stability 31 1 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 VM_SEL Inverting input selection 8 2 VP_SEL Non inverted input selection 10 1 OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-power mode 0x8 32 read-write n 0x0 0x0 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 32 read-write n 0x0 0x0 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x10 32 read-write n 0x0 0x0 CALON Calibration mode enabled 12 1 CALOUT Operational amplifier calibration output 15 1 CALSEL Calibration selection 13 1 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 VM_SEL Inverting input selection 8 2 VP_SEL Non inverted input selection 10 1 OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 32 read-write n 0x0 0x0 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 32 read-write n 0x0 0x0 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OTG_FS_DEVICE USB on the go full speed USB_OTG_FS 0x0 0x0 0x400 registers n DIEPCTL1 DIEPCTL1 OTG device endpoint-1 control register 0x120 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM_SD1PID SODDFRM/SD1PID 29 1 write-only Stall Stall 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write DIEPCTL2 DIEPCTL2 OTG device endpoint-2 control register 0x140 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only Stall Stall 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write DIEPCTL3 DIEPCTL3 OTG device endpoint-3 control register 0x160 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only Stall Stall 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write DIEPEMPMSK DIEPEMPMSK OTG_FS device IN endpoint FIFO empty interrupt mask register 0x34 32 read-write n 0x0 0x0 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DIEPINT0 DIEPINT0 device endpoint-x interrupt register 0x108 32 read-write n 0x0 0x0 EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only XFRC XFRC 0 1 read-write DIEPINT1 DIEPINT1 device endpoint-1 interrupt register 0x128 32 read-write n 0x0 0x0 EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only XFRC XFRC 0 1 read-write DIEPINT2 DIEPINT2 device endpoint-2 interrupt register 0x148 32 read-write n 0x0 0x0 EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only XFRC XFRC 0 1 read-write DIEPINT3 DIEPINT3 device endpoint-3 interrupt register 0x168 32 read-write n 0x0 0x0 EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only XFRC XFRC 0 1 read-write DIEPTSIZ0 DIEPTSIZ0 device endpoint-0 transfer size register 0x110 32 read-write n 0x0 0x0 PKTCNT Packet count 19 2 XFRSIZ Transfer size 0 7 DIEPTSIZ1 DIEPTSIZ1 device endpoint-1 transfer size register 0x130 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ2 DIEPTSIZ2 device endpoint-2 transfer size register 0x150 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ3 DIEPTSIZ3 device endpoint-3 transfer size register 0x170 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DOEPCTL0 DOEPCTL0 device endpoint-0 control register 0x300 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EPDIS EPDIS 30 1 read-only EPENA EPENA 31 1 write-only EPTYP EPTYP 18 2 read-only MPSIZ MPSIZ 0 2 read-only NAKSTS NAKSTS 17 1 read-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write Stall Stall 21 1 read-write USBAEP USBAEP 15 1 read-only DOEPCTL1 DOEPCTL1 device endpoint-1 control register 0x320 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write SODDFRM SODDFRM 29 1 write-only Stall Stall 21 1 read-write USBAEP USBAEP 15 1 read-write DOEPCTL2 DOEPCTL2 device endpoint-2 control register 0x340 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write SODDFRM SODDFRM 29 1 write-only Stall Stall 21 1 read-write USBAEP USBAEP 15 1 read-write DOEPCTL3 DOEPCTL3 device endpoint-3 control register 0x360 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPID EONUM/DPID 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write SODDFRM SODDFRM 29 1 write-only Stall Stall 21 1 read-write USBAEP USBAEP 15 1 read-write DOEPINT0 DOEPINT0 device endpoint-0 interrupt register 0x308 32 read-write n 0x0 0x0 B2BSTUP B2BSTUP 6 1 EPDISD EPDISD 1 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 XFRC XFRC 0 1 DOEPINT1 DOEPINT1 device endpoint-1 interrupt register 0x328 32 read-write n 0x0 0x0 B2BSTUP B2BSTUP 6 1 EPDISD EPDISD 1 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 XFRC XFRC 0 1 DOEPINT2 DOEPINT2 device endpoint-2 interrupt register 0x348 32 read-write n 0x0 0x0 B2BSTUP B2BSTUP 6 1 EPDISD EPDISD 1 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 XFRC XFRC 0 1 DOEPINT3 DOEPINT3 device endpoint-3 interrupt register 0x368 32 read-write n 0x0 0x0 B2BSTUP B2BSTUP 6 1 EPDISD EPDISD 1 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 XFRC XFRC 0 1 DOEPTSIZ0 DOEPTSIZ0 device OUT endpoint-0 transfer size register 0x310 32 read-write n 0x0 0x0 PKTCNT Packet count 19 1 STUPCNT SETUP packet count 29 2 XFRSIZ Transfer size 0 7 DOEPTSIZ1 DOEPTSIZ1 device OUT endpoint-1 transfer size register 0x330 32 read-write n 0x0 0x0 PKTCNT Packet count 19 10 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 XFRSIZ Transfer size 0 19 DOEPTSIZ2 DOEPTSIZ2 device OUT endpoint-2 transfer size register 0x350 32 read-write n 0x0 0x0 PKTCNT Packet count 19 10 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 XFRSIZ Transfer size 0 19 DOEPTSIZ3 DOEPTSIZ3 device OUT endpoint-3 transfer size register 0x370 32 read-write n 0x0 0x0 PKTCNT Packet count 19 10 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 XFRSIZ Transfer size 0 19 DTXFSTS0 DTXFSTS0 OTG_FS device IN endpoint transmit FIFO status register 0x118 32 read-only n 0x0 0x0 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS1 DTXFSTS1 OTG_FS device IN endpoint transmit FIFO status register 0x138 32 read-only n 0x0 0x0 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS2 DTXFSTS2 OTG_FS device IN endpoint transmit FIFO status register 0x158 32 read-only n 0x0 0x0 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS3 DTXFSTS3 OTG_FS device IN endpoint transmit FIFO status register 0x178 32 read-only n 0x0 0x0 INEPTFSAV IN endpoint TxFIFO space available 0 16 DVBUSDIS DVBUSDIS OTG_FS device VBUS discharge time register 0x28 32 read-write n 0x0 0x0 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_FS device VBUS pulsing time register 0x2C 32 read-write n 0x0 0x0 DVBUSP Device VBUS pulsing time 0 12 FS_DAINT FS_DAINT OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) 0x18 32 read-only n 0x0 0x0 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 FS_DAINTMSK FS_DAINTMSK OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) 0x1C 32 read-write n 0x0 0x0 IEPM IN EP interrupt mask bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 FS_DCFG FS_DCFG OTG_FS device configuration register (OTG_FS_DCFG) 0x0 32 read-write n 0x0 0x0 DAD Device address 4 7 DSPD Device speed 0 2 NZLSOHSK Non-zero-length status OUT handshake 2 1 PFIVL Periodic frame interval 11 2 FS_DCTL FS_DCTL OTG_FS device control register (OTG_FS_DCTL) 0x4 32 read-write n 0x0 0x0 CGINAK Clear global IN NAK 8 1 read-write CGONAK Clear global OUT NAK 10 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only POPRGDNE Power-on programming done 11 1 read-write RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write SGINAK Set global IN NAK 7 1 read-write SGONAK Set global OUT NAK 9 1 read-write TCTL Test control 4 3 read-write FS_DIEPCTL0 FS_DIEPCTL0 OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) 0x100 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-only EPTYP Endpoint type 18 2 read-only MPSIZ Maximum packet size 0 2 read-write NAKSTS NAK status 17 1 read-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write USBAEP USB active endpoint 15 1 read-only FS_DIEPMSK FS_DIEPMSK OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) 0x10 32 read-write n 0x0 0x0 EPDM Endpoint disabled interrupt mask 1 1 INEPNEM IN endpoint NAK effective mask 6 1 INEPNMM IN token received with EP mismatch mask 5 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 XFRCM Transfer completed interrupt mask 0 1 FS_DOEPMSK FS_DOEPMSK OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) 0x14 32 read-write n 0x0 0x0 EPDM Endpoint disabled interrupt mask 1 1 OTEPDM OUT token received when endpoint disabled mask 4 1 STUPM SETUP phase done mask 3 1 XFRCM Transfer completed interrupt mask 0 1 FS_DSTS FS_DSTS OTG_FS device status register (OTG_FS_DSTS) 0x8 32 read-only n 0x0 0x0 EERR Erratic error 3 1 ENUMSPD Enumerated speed 1 2 FNSOF Frame number of the received SOF 8 14 SUSPSTS Suspend status 0 1 OTG_FS_GLOBAL USB on the go full speed USB_OTG_FS 0x0 0x0 0x400 registers n OTG_FS USB OTG FS global Interrupt 67 FS_CID FS_CID core ID register 0x3C 32 read-write n 0x0 0x0 PRODUCT_ID Product ID field 0 32 FS_DIEPTXF1 FS_DIEPTXF1 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) 0x104 32 read-write n 0x0 0x0 INEPTXFD IN endpoint TxFIFO depth 16 16 INEPTXSA IN endpoint FIFO2 transmit RAM start address 0 16 FS_DIEPTXF2 FS_DIEPTXF2 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) 0x108 32 read-write n 0x0 0x0 INEPTXFD IN endpoint TxFIFO depth 16 16 INEPTXSA IN endpoint FIFO3 transmit RAM start address 0 16 FS_DIEPTXF3 FS_DIEPTXF3 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) 0x10C 32 read-write n 0x0 0x0 INEPTXFD IN endpoint TxFIFO depth 16 16 INEPTXSA IN endpoint FIFO4 transmit RAM start address 0 16 FS_GAHBCFG FS_GAHBCFG OTG_FS AHB configuration register (OTG_FS_GAHBCFG) 0x8 32 read-write n 0x0 0x0 GINT Global interrupt mask 0 1 PTXFELVL Periodic TxFIFO empty level 8 1 TXFELVL TxFIFO empty level 7 1 FS_GCCFG FS_GCCFG OTG_FS general core configuration register (OTG_FS_GCCFG) 0x38 32 read-write n 0x0 0x0 PWRDWN Power down 16 1 SOFOUTEN SOF output enable 20 1 VBUSASEN Enable the VBUS sensing device 18 1 VBUSBSEN Enable the VBUS sensing device 19 1 FS_GINTMSK FS_GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 32 read-write n 0x0 0x0 CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write ESUSPM Early suspend mask 10 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write HCIM Host channels interrupt mask 25 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IPXFRM_IISOOXFRM Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write MMISM Mode mismatch interrupt mask 1 1 read-write NPTXFEM Non-periodic TxFIFO empty mask 5 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write OTGINT OTG interrupt mask 2 1 read-write PRTIM Host port interrupt mask 24 1 read-only PTXFEM Periodic TxFIFO empty mask 26 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write SOFM Start of frame mask 3 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write USBRST USB reset mask 12 1 read-write USBSUSPM USB suspend mask 11 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write FS_GINTSTS FS_GINTSTS OTG_FS core interrupt register (OTG_FS_GINTSTS) 0x14 32 read-write n 0x0 0x0 CIDSCHG Connector ID status change 28 1 read-write CMOD Current mode of operation 0 1 read-only DISCINT Disconnect detected interrupt 29 1 read-write ENUMDNE Enumeration done 13 1 read-write EOPF End of periodic frame interrupt 15 1 read-write ESUSP Early suspend 10 1 read-write GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only HCINT Host channels interrupt 25 1 read-only HPRTINT Host port interrupt 24 1 read-only IEPINT IN endpoint interrupt 18 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write MMIS Mode mismatch interrupt 1 1 read-write NPTXFE Non-periodic TxFIFO empty 5 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only OTGINT OTG interrupt 2 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only RXFLVL RxFIFO non-empty 4 1 read-only SOF Start of frame 3 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write USBRST USB reset 12 1 read-write USBSUSP USB suspend 11 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write FS_GNPTXFSIZ_Device FS_GNPTXFSIZ_Device OTG_FS non-periodic transmit FIFO size register (Device mode) 0x28 32 read-write n 0x0 0x0 TX0FD Endpoint 0 TxFIFO depth 16 16 TX0FSA Endpoint 0 transmit RAM start address 0 16 FS_GNPTXFSIZ_Host FS_GNPTXFSIZ_Host OTG_FS non-periodic transmit FIFO size register (Host mode) FS_GNPTXFSIZ_Device 0x28 32 read-write n 0x0 0x0 NPTXFD Non-periodic TxFIFO depth 16 16 NPTXFSA Non-periodic transmit RAM start address 0 16 FS_GNPTXSTS FS_GNPTXSTS OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) 0x2C 32 read-only n 0x0 0x0 NPTQXSAV Non-periodic transmit request queue space available 16 8 NPTXFSAV Non-periodic TxFIFO space available 0 16 NPTXQTOP Top of the non-periodic transmit request queue 24 7 FS_GOTGCTL FS_GOTGCTL OTG_FS control and status register (OTG_FS_GOTGCTL) 0x0 32 read-write n 0x0 0x0 ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only DHNPEN Device HNP enabled 11 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write SRQ Session request 1 1 read-write SRQSCS Session request success 0 1 read-only FS_GOTGINT FS_GOTGINT OTG_FS interrupt register (OTG_FS_GOTGINT) 0x4 32 read-write n 0x0 0x0 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 HNGDET Host negotiation detected 17 1 HNSSCHG Host negotiation success status change 9 1 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 FS_GRSTCTL FS_GRSTCTL OTG_FS reset register (OTG_FS_GRSTCTL) 0x10 32 read-write n 0x0 0x0 AHBIDL AHB master idle 31 1 read-only CSRST Core soft reset 0 1 read-write FCRST Host frame counter reset 2 1 read-write HSRST HCLK soft reset 1 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write FS_GRXFSIZ FS_GRXFSIZ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) 0x24 32 read-write n 0x0 0x0 RXFD RxFIFO depth 0 16 FS_GRXSTSR_Device FS_GRXSTSR_Device OTG_FS Receive status debug read(Device mode) 0x1C 32 read-only n 0x0 0x0 BCNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 FRMNUM Frame number 21 4 PKTSTS Packet status 17 4 FS_GRXSTSR_Host FS_GRXSTSR_Host OTG_FS Receive status debug read(Host mode) FS_GRXSTSR_Device 0x1C 32 read-only n 0x0 0x0 BCNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 FRMNUM Frame number 21 4 PKTSTS Packet status 17 4 FS_GUSBCFG FS_GUSBCFG OTG_FS USB configuration register (OTG_FS_GUSBCFG) 0xC 32 read-write n 0x0 0x0 CTXPKT Corrupt Tx packet 31 1 read-write FDMOD Force device mode 30 1 read-write FHMOD Force host mode 29 1 read-write HNPCAP HNP-capable 9 1 read-write PHYSEL Full Speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write TOCAL FS timeout calibration 0 3 read-write TRDT USB turnaround time 10 4 read-write FS_HPTXFSIZ FS_HPTXFSIZ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) 0x100 32 read-write n 0x0 0x0 PTXFSIZ Host periodic TxFIFO depth 16 16 PTXSA Host periodic TxFIFO start address 0 16 OTG_FS_HOST USB on the go full speed USB_OTG_FS 0x0 0x0 0x400 registers n FS_HCCHAR0 FS_HCCHAR0 OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) 0x100 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR1 FS_HCCHAR1 OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) 0x120 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR2 FS_HCCHAR2 OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) 0x140 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR3 FS_HCCHAR3 OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) 0x160 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR4 FS_HCCHAR4 OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) 0x180 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR5 FS_HCCHAR5 OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) 0x1A0 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR6 FS_HCCHAR6 OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) 0x1C0 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCCHAR7 FS_HCCHAR7 OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) 0x1E0 32 read-write n 0x0 0x0 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 DAD Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYP Endpoint type 18 2 LSDEV Low-speed device 17 1 MCNT Multicount 20 2 MPSIZ Maximum packet size 0 11 ODDFRM Odd frame 29 1 FS_HCFG FS_HCFG OTG_FS host configuration register (OTG_FS_HCFG) 0x0 32 read-write n 0x0 0x0 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only FS_HCINT0 FS_HCINT0 OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) 0x108 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT1 FS_HCINT1 OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) 0x128 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT2 FS_HCINT2 OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) 0x148 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT3 FS_HCINT3 OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) 0x168 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT4 FS_HCINT4 OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) 0x188 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT5 FS_HCINT5 OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) 0x1A8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT6 FS_HCINT6 OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) 0x1C8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINT7 FS_HCINT7 OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) 0x1E8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBERR Babble error 8 1 CHH Channel halted 1 1 DTERR Data toggle error 10 1 FRMOR Frame overrun 9 1 NAK NAK response received interrupt 4 1 STALL STALL response received interrupt 3 1 TXERR Transaction error 7 1 XFRC Transfer completed 0 1 FS_HCINTMSK0 FS_HCINTMSK0 OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) 0x10C 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK1 FS_HCINTMSK1 OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) 0x12C 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK2 FS_HCINTMSK2 OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) 0x14C 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK3 FS_HCINTMSK3 OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) 0x16C 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK4 FS_HCINTMSK4 OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) 0x18C 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK5 FS_HCINTMSK5 OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) 0x1AC 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK6 FS_HCINTMSK6 OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) 0x1CC 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCINTMSK7 FS_HCINTMSK7 OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) 0x1EC 32 read-write n 0x0 0x0 ACKM ACK response received/transmitted interrupt mask 5 1 BBERRM Babble error mask 8 1 CHHM Channel halted mask 1 1 DTERRM Data toggle error mask 10 1 FRMORM Frame overrun mask 9 1 NAKM NAK response received interrupt mask 4 1 NYET response received interrupt mask 6 1 STALLM STALL response received interrupt mask 3 1 TXERRM Transaction error mask 7 1 XFRCM Transfer completed mask 0 1 FS_HCTSIZ0 FS_HCTSIZ0 OTG_FS host channel-0 transfer size register 0x110 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ1 FS_HCTSIZ1 OTG_FS host channel-1 transfer size register 0x130 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ2 FS_HCTSIZ2 OTG_FS host channel-2 transfer size register 0x150 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ3 FS_HCTSIZ3 OTG_FS host channel-3 transfer size register 0x170 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ4 FS_HCTSIZ4 OTG_FS host channel-x transfer size register 0x190 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ5 FS_HCTSIZ5 OTG_FS host channel-5 transfer size register 0x1B0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ6 FS_HCTSIZ6 OTG_FS host channel-6 transfer size register 0x1D0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HCTSIZ7 FS_HCTSIZ7 OTG_FS host channel-7 transfer size register 0x1F0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 FS_HFNUM FS_HFNUM OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) 0x8 32 read-only n 0x0 0x0 FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 FS_HPRT FS_HPRT OTG_FS host port control and status register (OTG_FS_HPRT) 0x40 32 read-write n 0x0 0x0 PCDET Port connect detected 1 1 read-write PCSTS Port connect status 0 1 read-only PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write PLSTS Port line status 10 2 read-only POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PPWR Port power 12 1 read-write PRES Port resume 6 1 read-write PRST Port reset 8 1 read-write PSPD Port speed 17 2 read-only PSUSP Port suspend 7 1 read-write PTCTL Port test control 13 4 read-write FS_HPTXSTS FS_HPTXSTS OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) 0x10 32 read-write n 0x0 0x0 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_FS Host all channels interrupt register 0x14 32 read-only n 0x0 0x0 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_FS host all channels interrupt mask register 0x18 32 read-write n 0x0 0x0 HAINTM Channel interrupt mask 0 16 HFIR HFIR OTG_FS Host frame interval register 0x4 32 read-write n 0x0 0x0 FRIVL Frame interval 0 16 OTG_FS_PWRCLK USB on the go full speed USB_OTG_FS 0x0 0x0 0x400 registers n FS_PCGCCTL FS_PCGCCTL OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) 0x0 32 read-write n 0x0 0x0 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY Suspended 4 1 STPPCLK Stop PHY clock 0 1 PWR Power control PWR 0x0 0x0 0x400 registers n CR1 CR1 Power control register 1 0x0 32 read-write n 0x0 0x0 DBP Disable backup domain write protection 8 1 LPMS Low-power mode selection 0 3 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 CR2 CR2 Power control register 2 0x4 32 read-write n 0x0 0x0 IOSV VDDIO2 Independent I/Os supply valid 9 1 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 PVME2 Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 5 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME4 Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 7 1 USV VDDUSB USB supply valid 10 1 CR3 CR3 Power control register 3 0x8 32 read-write n 0x0 0x0 APC Apply pull-up and pull-down configuration 10 1 EWF Enable internal wakeup line 15 1 EWUP1 Enable Wakeup pin WKUP1 0 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP5 Enable Wakeup pin WKUP5 4 1 RRS SRAM2 retention in Standby mode 8 1 CR4 CR4 Power control register 4 0xC 32 read-write n 0x0 0x0 VBE VBAT battery charging enable 8 1 VBRS VBAT battery charging resistor selection 9 1 WP1 Wakeup pin WKUP1 polarity 0 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP5 Wakeup pin WKUP5 polarity 4 1 PDCRA PDCRA Power Port A pull-down control register 0x24 32 read-write n 0x0 0x0 PD0 Port A pull-down bit y (y=0..15) 0 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD15 Port A pull-down bit y (y=0..15) 15 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 32 read-write n 0x0 0x0 PD0 Port B pull-down bit y (y=0..15) 0 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD15 Port B pull-down bit y (y=0..15) 15 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PDCRC PDCRC Power Port C pull-down control register 0x34 32 read-write n 0x0 0x0 PD0 Port C pull-down bit y (y=0..15) 0 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD15 Port C pull-down bit y (y=0..15) 15 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 32 read-write n 0x0 0x0 PD0 Port D pull-down bit y (y=0..15) 0 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD15 Port D pull-down bit y (y=0..15) 15 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PDCRE PDCRE Power Port E pull-down control register 0x44 32 read-write n 0x0 0x0 PD0 Port E pull-down bit y (y=0..15) 0 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD15 Port E pull-down bit y (y=0..15) 15 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 32 read-write n 0x0 0x0 PD0 Port F pull-down bit y (y=0..15) 0 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD13 Port F pull-down bit y (y=0..15) 13 1 PD14 Port F pull-down bit y (y=0..15) 14 1 PD15 Port F pull-down bit y (y=0..15) 15 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PDCRG PDCRG Power Port G pull-down control register 0x54 32 read-write n 0x0 0x0 PD0 Port G pull-down bit y (y=0..15) 0 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD15 Port G pull-down bit y (y=0..15) 15 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 32 read-write n 0x0 0x0 PD0 Port H pull-down bit y (y=0..1) 0 1 PD1 Port H pull-down bit y (y=0..1) 1 1 PUCRA PUCRA Power Port A pull-up control register 0x20 32 read-write n 0x0 0x0 PU0 Port A pull-up bit y (y=0..15) 0 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU15 Port A pull-up bit y (y=0..15) 15 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PUCRB PUCRB Power Port B pull-up control register 0x28 32 read-write n 0x0 0x0 PU0 Port B pull-up bit y (y=0..15) 0 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU15 Port B pull-up bit y (y=0..15) 15 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PUCRC PUCRC Power Port C pull-up control register 0x30 32 read-write n 0x0 0x0 PU0 Port C pull-up bit y (y=0..15) 0 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU15 Port C pull-up bit y (y=0..15) 15 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PUCRD PUCRD Power Port D pull-up control register 0x38 32 read-write n 0x0 0x0 PU0 Port D pull-up bit y (y=0..15) 0 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU15 Port D pull-up bit y (y=0..15) 15 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PUCRE PUCRE Power Port E pull-up control register 0x40 32 read-write n 0x0 0x0 PU0 Port E pull-up bit y (y=0..15) 0 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU15 Port E pull-up bit y (y=0..15) 15 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PUCRF PUCRF Power Port F pull-up control register 0x48 32 read-write n 0x0 0x0 PU0 Port F pull-up bit y (y=0..15) 0 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU13 Port F pull-up bit y (y=0..15) 13 1 PU14 Port F pull-up bit y (y=0..15) 14 1 PU15 Port F pull-up bit y (y=0..15) 15 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PUCRG PUCRG Power Port G pull-up control register 0x50 32 read-write n 0x0 0x0 PU0 Port G pull-up bit y (y=0..15) 0 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU15 Port G pull-up bit y (y=0..15) 15 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PUCRH PUCRH Power Port H pull-up control register 0x58 32 read-write n 0x0 0x0 PU0 Port H pull-up bit y (y=0..1) 0 1 PU1 Port H pull-up bit y (y=0..1) 1 1 SCR SCR Power status clear register 0x18 32 write-only n 0x0 0x0 SBF Clear standby flag 8 1 WUF1 Clear wakeup flag 1 0 1 WUF2 Clear wakeup flag 2 1 1 WUF3 Clear wakeup flag 3 2 1 WUF4 Clear wakeup flag 4 3 1 WUF5 Clear wakeup flag 5 4 1 SR1 SR1 Power status register 1 0x10 32 read-only n 0x0 0x0 CSBF Standby flag 8 1 CWUF1 Wakeup flag 1 0 1 CWUF2 Wakeup flag 2 1 1 CWUF3 Wakeup flag 3 2 1 CWUF4 Wakeup flag 4 3 1 CWUF5 Wakeup flag 5 4 1 WUFI Wakeup flag internal 15 1 SR2 SR2 Power status register 2 0x14 32 read-only n 0x0 0x0 PVDO Power voltage detector output 11 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 13 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V 15 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 VOSF Voltage scaling flag 10 1 RCC Reset and clock control RCC 0x0 0x0 0x400 registers n RCC RCC global interrupt 5 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 32 read-write n 0x0 0x0 CRCEN CRC clock enable 12 1 DMA1EN DMA1 clock enable 0 1 DMA2DEN DMA2D clock enable 17 1 DMA2EN DMA2 clock enable 1 1 DMAMUX1EN DMAMUX clock enable 2 1 FLASHEN Flash memory interface clock enable 8 1 GFXMMUEN Graphic MMU clock enable 18 1 TSCEN Touch Sensing Controller clock enable 16 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 32 read-write n 0x0 0x0 CRCRST CRC reset 12 1 DMA1RST DMA1 reset 0 1 DMA2DRST DMA2D reset 17 1 DMA2RST DMA2 reset 1 1 DMAMUX1RST DMAMUXRST 2 1 FLASHRST Flash memory interface reset 8 1 GFXMMURST GFXMMU reset 18 1 TSCRST Touch Sensing Controller reset 16 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 32 read-write n 0x0 0x0 CRCSMEN CRCSMEN 12 1 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 DMA2DSMEN DMA2D clock enable during Sleep and Stop modes 17 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMAMUX1SMEN DMAMUX clock enable during Sleep and Stop modes 2 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 GFXMMUSMEN GFXMMU clock enable during Sleep and Stop modes 18 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 TSCSMEN Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 32 read-write n 0x0 0x0 ADCEN ADC clock enable 13 1 AESEN AES accelerator clock enable 16 1 DCMIEN DCMI clock enable 14 1 GPIOAEN IO port A clock enable 0 1 GPIOBEN IO port B clock enable 1 1 GPIOCEN IO port C clock enable 2 1 GPIODEN IO port D clock enable 3 1 GPIOEEN IO port E clock enable 4 1 GPIOFEN IO port F clock enable 5 1 GPIOGEN IO port G clock enable 6 1 GPIOHEN IO port H clock enable 7 1 GPIOIEN IO port I clock enable 8 1 HASHEN HASH clock enable 17 1 OSPIMEN OctoSPI IO manager clock enable 20 1 OTGFSEN OTG full speed clock enable 12 1 RNGEN Random Number Generator clock enable 18 1 SDMMC1EN SDMMC1 clock enable 22 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 32 read-write n 0x0 0x0 ADCRST ADC reset 13 1 AESRST AES hardware accelerator reset 16 1 DCMIRST Digital Camera Interface reset 14 1 GPIOARST IO port A reset 0 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOERST IO port E reset 4 1 GPIOFRST IO port F reset 5 1 GPIOGRST IO port G reset 6 1 GPIOHRST IO port H reset 7 1 GPIOIRST IO port I reset 8 1 HASHRST Hash reset 17 1 OSPIMRST OCTOSPI IO manager reset 20 1 OTGFSRST USB OTG FS reset 12 1 RNGRST Random number generator reset 18 1 SDMMC1RST SDMMC1 reset 22 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 32 read-write n 0x0 0x0 ADCFSSMEN ADC clocks enable during Sleep and Stop modes 13 1 AESSMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 DCMISMEN DCMI clock enable during Sleep and Stop modes 14 1 GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes 5 1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes 6 1 GPIOHSMEN IO port H clocks enable during Sleep and Stop modes 7 1 GPIOISMEN IO port I clocks enable during Sleep and Stop modes 8 1 HASHSMEN HASH clock enable during Sleep and Stop modes 17 1 OSPIMSMEN OctoSPI IO manager clocks enable during Sleep and Stop modes 20 1 OTGFSSMEN OTG full speed clocks enable during Sleep and Stop modes 12 1 RNGSMEN Random Number Generator clocks enable during Sleep and Stop modes 18 1 SDMMC1SMEN SDMMC1 clocks enable during Sleep and Stop modes 22 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 SRAM3SMEN SRAM2 interface clocks enable during Sleep and Stop modes 10 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 32 read-write n 0x0 0x0 FMCEN Flexible memory controller clock enable 0 1 OSPI2EN OSPI2EN memory interface clock enable 9 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 32 read-write n 0x0 0x0 FMCRST Flexible memory controller reset 0 1 OSPI2RST OctOSPI2 memory interface reset 9 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 32 read-write n 0x0 0x0 FMCSMEN Flexible memory controller clocks enable during Sleep and Stop modes 0 1 OCTOSPI2 OctoSPI2 memory interface clocks enable during Sleep and Stop modes 9 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 32 read-write n 0x0 0x0 CAN1EN CAN1 clock enable 25 1 CRSEN Clock Recovery System clock enable 24 1 DAC1EN DAC1 interface clock enable 29 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 LPTIM1EN Low power timer 1 clock enable 31 1 OPAMPEN OPAMP interface clock enable 30 1 PWREN Power interface clock enable 28 1 RTCAPBEN RTC APB clock enable 10 1 SP3EN SPI3 clock enable 15 1 SPI2EN SPI2 clock enable 14 1 TIM2EN TIM2 timer clock enable 0 1 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM5EN TIM5 timer clock enable 3 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 UART4EN UART4 clock enable 19 1 UART5EN UART5 clock enable 20 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 WWDGEN Window watchdog clock enable 11 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 32 read-write n 0x0 0x0 I2C4EN I2C4 clock enable 1 1 LPTIM2EN LPTIM2EN 5 1 LPUART1EN Low power UART 1 clock enable 0 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 32 read-write n 0x0 0x0 CAN1RST CAN1 reset 25 1 CRSRST CRS reset 24 1 DAC1RST DAC1 interface reset 29 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 I2C3RST I2C3 reset 23 1 LPTIM1RST Low Power Timer 1 reset 31 1 OPAMPRST OPAMP interface reset 30 1 PWRRST Power interface reset 28 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 TIM2RST TIM2 timer reset 0 1 TIM3RST TIM3 timer reset 1 1 TIM4RST TIM3 timer reset 2 1 TIM5RST TIM5 timer reset 3 1 TIM6RST TIM6 timer reset 4 1 TIM7RST TIM7 timer reset 5 1 UART4RST UART4 reset 19 1 UART5RST UART5 reset 20 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 32 read-write n 0x0 0x0 I2C4RST I2C4 reset 1 1 LPTIM2RST Low-power timer 2 reset 5 1 LPUART1RST Low-power UART 1 reset 0 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 32 read-write n 0x0 0x0 CAN1SMEN CAN1 clocks enable during Sleep and Stop modes 25 1 CRSSMEN CRS clock enable during Sleep and Stop modes 24 1 DAC1SMEN DAC1 interface clocks enable during Sleep and Stop modes 29 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes 31 1 OPAMPSMEN OPAMP interface clocks enable during Sleep and Stop modes 30 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes 1 1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes 2 1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes 3 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 UART4SMEN UART4 clocks enable during Sleep and Stop modes 19 1 UART5SMEN UART5 clocks enable during Sleep and Stop modes 20 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 17 1 USART3SMEN USART3 clocks enable during Sleep and Stop modes 18 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 32 read-write n 0x0 0x0 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes 1 1 LPTIM2SMEN LPTIM2SMEN 5 1 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 APB2ENR APB2ENR APB2ENR 0x60 32 read-write n 0x0 0x0 DFSDM1EN DFSDM timer clock enable 24 1 DSIEN DSI clock enable 27 1 FWEN Firewall clock enable 7 1 LTDCEN LCD-TFT clock enable 26 1 SAI1EN SAI1 clock enable 21 1 SAI2EN SAI2 clock enable 22 1 SPI1EN SPI1 clock enable 12 1 SYSCFGEN SYSCFG clock enable 0 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 TIM1EN TIM1 timer clock enable 11 1 TIM8EN TIM8 timer clock enable 13 1 USART1EN USART1clock enable 14 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 32 read-write n 0x0 0x0 DFSDM1RST Digital filters for sigma-delata modulators (DFSDM) reset 24 1 DSIRST DSI reset 27 1 LTDCRST LCD-TFT reset 26 1 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 SAI2RST Serial audio interface 2 (SAI2) reset 22 1 SPI1RST SPI1 reset 12 1 SYSCFGRST System configuration (SYSCFG) reset 0 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 TIM1RST TIM1 timer reset 11 1 TIM8RST TIM8 timer reset 13 1 USART1RST USART1 reset 14 1 APB2SMENR APB2SMENR APB2SMENR 0x80 32 read-write n 0x0 0x0 DFSDM1SMEN DFSDM timer clocks enable during Sleep and Stop modes 24 1 DSISMEN DSI clocks enable during Sleep and Stop modes 27 1 LTDCSMEN LCD-TFT timer clocks enable during Sleep and Stop modes 26 1 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes 21 1 SAI2SMEN SAI2 clocks enable during Sleep and Stop modes 22 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes 18 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes 13 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 BDCR BDCR BDCR 0x90 32 read-write n 0x0 0x0 BDRST Backup domain software reset 16 1 read-write LSCOEN Low speed clock output enable 24 1 read-write LSCOSEL Low speed clock output selection 25 1 read-write LSEBYP LSE oscillator bypass 2 1 read-write LSECSSD LSECSSD 6 1 read-only LSECSSON LSECSSON 5 1 read-write LSEDRV SE oscillator drive capability 3 2 read-write LSEON LSE oscillator enable 0 1 read-write LSERDY LSE oscillator ready 1 1 read-only RTCEN RTC clock enable 15 1 read-write RTCSEL RTC clock source selection 8 2 read-write CCIPR CCIPR CCIPR 0x88 32 read-write n 0x0 0x0 ADCSEL ADCs clock source selection 28 2 CLK48SEL 48 MHz clock source selection 26 2 I2C1SEL I2C1 clock source selection 12 2 I2C2SEL I2C2 clock source selection 14 2 I2C3SEL I2C3 clock source selection 16 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 LPTIM2SEL Low power timer 2 clock source selection 20 2 LPUART1SEL LPUART1 clock source selection 10 2 SAI1SEL SAI1 clock source selection 22 2 SAI2SEL SAI2 clock source selection 24 2 UART4SEL UART4 clock source selection 6 2 UART5SEL UART5 clock source selection 8 2 USART1SEL USART1 clock source selection 0 2 USART2SEL USART2 clock source selection 2 2 USART3SEL USART3 clock source selection 4 2 CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 32 read-write n 0x0 0x0 ADFSDMSEL Digital filter for sigma delta modulator audio clock source selection 3 2 DFSDMSEL Digital filter for sigma delta modulator kernel clock source selection 2 1 DSISEL clock selection 12 1 I2C4SEL I2C4 clock source selection 0 2 OSPISEL Octospi clock source selection 20 2 PLLSAI2DIVR division factor for LTDC clock 16 2 SAI1SEL SAI1 clock source selection 5 3 SAI2SEL SAI2 clock source selection 8 3 SDMMCSEL SDMMC clock selection 14 1 CFGR CFGR Clock configuration register 0x8 32 read-write n 0x0 0x0 HPRE AHB prescaler 4 4 read-write MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOSEL Microcontroller clock output 24 3 read-write PPRE1 PB low-speed prescaler (APB1) 8 3 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write SW System clock switch 0 2 read-write SWS System clock switch status 2 2 read-only CICR CICR Clock interrupt clear register 0x20 32 write-only n 0x0 0x0 CSSC Clock security system interrupt clear 8 1 HSERDYC HSE ready interrupt clear 4 1 HSI48RDYC HSI48 oscillator ready interrupt clear 10 1 HSIRDYC HSI ready interrupt clear 3 1 LSECSSC LSE Clock security system interrupt clear 9 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 MSIRDYC MSI ready interrupt clear 2 1 PLLRDYC PLL ready interrupt clear 5 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLSAI2RDYC PLLSAI2 ready interrupt clear 7 1 CIER CIER Clock interrupt enable register 0x18 32 read-write n 0x0 0x0 HSERDYIE HSE ready interrupt enable 4 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 HSIRDYIE HSI ready interrupt enable 3 1 LSECSSIE LSE clock security system interrupt enable 9 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 MSIRDYIE MSI ready interrupt enable 2 1 PLLRDYIE PLL ready interrupt enable 5 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLSAI2RDYIE PLLSAI2 ready interrupt enable 7 1 CIFR CIFR Clock interrupt flag register 0x1C 32 read-only n 0x0 0x0 CSSF Clock security system interrupt flag 8 1 HSERDYF HSE ready interrupt flag 4 1 HSI48RDYF HSI48 ready interrupt flag 10 1 HSIRDYF HSI ready interrupt flag 3 1 LSECSSF LSE Clock security system interrupt flag 9 1 LSERDYF LSE ready interrupt flag 1 1 LSIRDYF LSI ready interrupt flag 0 1 MSIRDYF MSI ready interrupt flag 2 1 PLLRDYF PLL ready interrupt flag 5 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLSAI2RDYF PLLSAI2 ready interrupt flag 7 1 CR CR Clock control register 0x0 32 read-write n 0x0 0x0 CSSON Clock security system enable 19 1 write-only HSEBYP HSE crystal oscillator bypass 18 1 read-write HSEON HSE clock enable 16 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSIASFS HSI automatic start from Stop 11 1 read-write HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSION HSI clock enable 8 1 read-write HSIRDY HSI clock ready flag 10 1 read-only MSION MSI clock enable 0 1 read-write MSIPLLEN MSI clock PLL enable 2 1 read-write MSIRANGE MSI clock ranges 4 4 read-write MSIRDY MSI clock ready flag 1 1 read-only MSIRGSEL MSI clock range selection 3 1 write-only PLLON Main PLL enable 24 1 read-write PLLRDY Main PLL clock ready flag 25 1 read-only PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI2ON SAI2 PLL enable 28 1 read-write PLLSAI2RDY SAI2 PLL clock ready flag 29 1 read-only CRRCR CRRCR Clock recovery RC register 0x98 32 read-write n 0x0 0x0 HSI48CAL HSI48 clock calibration 7 9 read-only HSI48ON HSI48 clock enable 0 1 read-write HSI48RDY HSI48 clock ready flag 1 1 read-only CSR CSR CSR 0x94 32 read-write n 0x0 0x0 BORRSTF BOR flag 27 1 read-only FWRSTF Firewall reset flag 24 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only LPWRSTF Low-power reset flag 31 1 read-only LSION LSI oscillator enable 0 1 read-write LSIRDY LSI oscillator ready 1 1 read-only MSISRANGE SI range after Standby mode 8 4 read-write OBLRSTF Option byte loader reset flag 25 1 read-only PINRSTF Pin reset flag 26 1 read-only RMVF Remove reset flag 23 1 read-write SFTRSTF Software reset flag 28 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only ICSCR ICSCR Internal clock sources calibration register 0x4 32 read-write n 0x0 0x0 HSICAL HSI clock calibration 16 8 read-only HSITRIM HSI clock trimming 24 7 read-write MSICAL MSI clock calibration 0 8 read-only MSITRIM MSI clock trimming 8 8 read-write PLLCFGR PLLCFGR PLL configuration register 0xC 32 read-write n 0x0 0x0 PLLM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 4 PLLN Main PLL multiplication factor for VCO 8 7 PLLP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLQEN Main PLL PLLUSB1CLK output enable 20 1 PLLR Main PLL division factor for PLLCLK (system clock) 25 2 PLLREN Main PLL PLLCLK output enable 24 1 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 32 read-write n 0x0 0x0 PLLSAI1M Division factor for PLLSAI1 input clock 4 4 PLLSAI1N SAI1PLL multiplication factor for VCO 8 7 PLLSAI1P SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) 17 1 PLLSAI1PDIV PLLSAI1 division factor for PLLSAI1CLK 27 5 PLLSAI1PEN SAI1PLL PLLSAI1CLK output enable 16 1 PLLSAI1Q SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) 21 2 PLLSAI1QEN SAI1PLL PLLUSB2CLK output enable 20 1 PLLSAI1R PLLSAI1 division factor for PLLADC1CLK (ADC clock) 25 2 PLLSAI1REN PLLSAI1 PLLADC1CLK output enable 24 1 PLLSAI2CFGR PLLSAI2CFGR PLLSAI2 configuration register 0x14 32 read-write n 0x0 0x0 PLLSAI2M Division factor for PLLSAI2 input clock 4 4 PLLSAI2N SAI2PLL multiplication factor for VCO 8 7 PLLSAI2P SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock) 17 1 PLLSAI2PDIV PLLSAI2 division factor for PLLSAI2CLK 27 5 PLLSAI2PEN SAI2PLL PLLSAI2CLK output enable 16 1 PLLSAI2Q SAI2PLL PLLSAI2CLK output enable 21 2 PLLSAI2QEN PLLSAI2 division factor for PLLDISCLK 20 1 PLLSAI2R PLLSAI2 division factor for PLLADC2CLK (ADC clock) 25 2 PLLSAI2REN PLLSAI2 PLLADC2CLK output enable 24 1 RNG Random number generator RNG 0x0 0x0 0x400 registers n RNG_HASH RNG and HASH global interrupt 80 CR CR control register 0x0 32 read-write n 0x0 0x0 IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 DR DR data register 0x8 32 read-only n 0x0 0x0 RNDATA Random data 0 32 SR SR status register 0x4 32 read-write n 0x0 0x0 CECS Clock error current status 1 1 read-only CEIS Clock error interrupt status 5 1 read-write DRDY Data ready 0 1 read-only SECS Seed error current status 2 1 read-only SEIS Seed error interrupt status 6 1 read-write RTC Real-time clock RTC 0x0 0x0 0x400 registers n TAMP_STAMP Tamper and TimeStamp interrupts 2 RTC_WKUP RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts 3 RTC_ALARM RTC alarms through EXTI line 18 interrupts 41 ALRMAR ALRMAR alarm A register 0x1C 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 MSK2 Alarm A minutes mask 15 1 MSK3 Alarm A hours mask 23 1 MSK4 Alarm A date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x20 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 MSK2 Alarm B minutes mask 15 1 MSK3 Alarm B hours mask 23 1 MSK4 Alarm B date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMBSSR ALRMBSSR alarm B sub second register 0x48 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 BKP0R BKP0R backup register 0x50 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP10R BKP10R backup register 0x78 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP11R BKP11R backup register 0x7C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP12R BKP12R backup register 0x80 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP13R BKP13R backup register 0x84 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP14R BKP14R backup register 0x88 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP15R BKP15R backup register 0x8C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP16R BKP16R backup register 0x90 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP17R BKP17R backup register 0x94 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP18R BKP18R backup register 0x98 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP19R BKP19R backup register 0x9C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP1R BKP1R backup register 0x54 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP20R BKP20R backup register 0xA0 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP21R BKP21R backup register 0xA4 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP22R BKP22R backup register 0xA8 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP23R BKP23R backup register 0xAC 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP24R BKP24R backup register 0xB0 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP25R BKP25R backup register 0xB4 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP26R BKP26R backup register 0xB8 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP27R BKP27R backup register 0xBC 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP28R BKP28R backup register 0xC0 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP29R BKP29R backup register 0xC4 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP2R BKP2R backup register 0x58 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP30R BKP30R backup register 0xC8 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP31R BKP31R backup register 0xCC 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP3R BKP3R backup register 0x5C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP4R BKP4R backup register 0x60 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP5R BKP5R backup register 0x64 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP6R BKP6R backup register 0x68 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP7R BKP7R backup register 0x6C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP8R BKP8R backup register 0x70 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP9R BKP9R backup register 0x74 32 read-write n 0x0 0x0 BKP BKP 0 32 CALR CALR calibration register 0x3C 32 read-write n 0x0 0x0 CALM Calibration minus 0 9 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW8 Use an 8-second calibration cycle period 14 1 CR CR control register 0x8 32 read-write n 0x0 0x0 ADD1H Add 1 hour (summer time change) 16 1 ALRAE Alarm A enable 8 1 ALRAIE Alarm A interrupt enable 12 1 ALRBE Alarm B enable 9 1 ALRBIE Alarm B interrupt enable 13 1 BKP Backup 18 1 BYPSHAD Bypass the shadow registers 5 1 COE Calibration output enable 23 1 COSEL Calibration output selection 19 1 FMT Hour format 6 1 ITSE timestamp on internal event enable 24 1 OSEL Output selection 21 2 POL Output polarity 20 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 SUB1H Subtract 1 hour (winter time change) 17 1 TSE Time stamp enable 11 1 TSEDGE Time-stamp event active edge 3 1 TSIE Time-stamp interrupt enable 15 1 WCKSEL Wakeup clock selection 0 3 WUTE Wakeup timer enable 10 1 WUTIE Wakeup timer interrupt enable 14 1 DR DR date register 0x4 32 read-write n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 ISR ISR initialization and status register 0xC 32 read-write n 0x0 0x0 ALRAF Alarm A flag 8 1 read-write ALRAWF Alarm A write flag 0 1 read-only ALRBF Alarm B flag 9 1 read-write ALRBWF Alarm B write flag 1 1 read-only INIT Initialization mode 7 1 read-write INITF Initialization flag 6 1 read-only INITS Initialization status flag 4 1 read-only RECALPF Recalibration pending Flag 16 1 read-only RSF Registers synchronization flag 5 1 read-write SHPF Shift operation pending 3 1 read-write TAMP1F Tamper detection flag 13 1 read-write TAMP2F RTC_TAMP2 detection flag 14 1 read-write TAMP3F RTC_TAMP3 detection flag 15 1 read-write TSF Time-stamp flag 11 1 read-write TSOVF Time-stamp overflow flag 12 1 read-write WUTF Wakeup timer flag 10 1 read-write WUTWF Wakeup timer write flag 2 1 read-only OR OR option register 0x4C 32 read-write n 0x0 0x0 RTC_ALARM_TYPE RTC_ALARM on PC13 output type 0 1 RTC_OUT_RMP RTC_OUT remap 1 1 PRER PRER prescaler register 0x10 32 read-write n 0x0 0x0 PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 SHIFTR SHIFTR shift control register 0x2C 32 write-only n 0x0 0x0 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 SSR SSR sub second register 0x28 32 read-only n 0x0 0x0 SS Sub second value 0 16 TAMPCR TAMPCR tamper configuration register 0x40 32 read-write n 0x0 0x0 TAMP1E Tamper 1 detection enable 0 1 TAMP1IE Tamper 1 interrupt enable 16 1 TAMP1MF Tamper 1 mask flag 18 1 TAMP1NOERASE Tamper 1 no erase 17 1 TAMP1TRG Active level for tamper 1 1 1 TAMP2E Tamper 2 detection enable 3 1 TAMP2IE Tamper 2 interrupt enable 19 1 TAMP2MF Tamper 2 mask flag 21 1 TAMP2NOERASE Tamper 2 no erase 20 1 TAMP2TRG Active level for tamper 2 4 1 TAMP3E Tamper 3 detection enable 5 1 TAMP3IE Tamper 3 interrupt enable 22 1 TAMP3MF Tamper 3 mask flag 24 1 TAMP3NOERASE Tamper 3 no erase 23 1 TAMP3TRG Active level for tamper 3 6 1 TAMPFLT Tamper filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPIE Tamper interrupt enable 2 1 TAMPPRCH Tamper precharge duration 13 2 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPTS Activate timestamp on tamper detection event 7 1 TR TR time register 0x0 32 read-write n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 TSDR TSDR time stamp date register 0x34 32 read-only n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 TSSSR TSSSR timestamp sub second register 0x38 32 read-only n 0x0 0x0 SS Sub second value 0 16 TSTR TSTR time stamp time register 0x30 32 read-only n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WPR WPR write protection register 0x24 32 write-only n 0x0 0x0 KEY Write protection key 0 8 WUTR WUTR wakeup timer register 0x14 32 read-write n 0x0 0x0 WUT Wakeup auto-reload value bits 0 16 SAI1 Serial audio interface SAI 0x0 0x0 0x400 registers n SAI1 SAI1 global interrupt 74 ACLRFR ACLRFR AClear flag register 0x1C 32 read-write n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 ACR1 ACR1 AConfiguration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 4 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIAEN Audio block A enable 16 1 SYNCEN Synchronization enable 10 2 ACR2 ACR2 AConfiguration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 ADR ADR AData register 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 AFRCR AFRCR AFRCR 0xC 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 AIM AIM AInterrupt mask register2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDET Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 ASLOTR ASLOTR ASlot register 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 ASR ASR AStatus register 0x18 32 read-write n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 BCLRFR BCLRFR BClear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 BCR1 BCR1 BConfiguration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 4 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIBEN Audio block B enable 16 1 SYNCEN Synchronization enable 10 2 BCR2 BCR2 BConfiguration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 BDR BDR BData register 0x40 32 read-write n 0x0 0x0 DATA Data 0 32 BFRCR BFRCR BFRCR 0x2C 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 BIM BIM BInterrupt mask register2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDETIE Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 BSLOTR BSLOTR BSlot register 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 BSR BSR BStatus register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag 2 1 SAI2 Serial audio interface SAI 0x0 0x0 0x400 registers n SAI2 SAI2 global interrupt 75 ACLRFR ACLRFR AClear flag register 0x1C 32 read-write n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 ACR1 ACR1 AConfiguration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 4 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIAEN Audio block A enable 16 1 SYNCEN Synchronization enable 10 2 ACR2 ACR2 AConfiguration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 ADR ADR AData register 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 AFRCR AFRCR AFRCR 0xC 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 AIM AIM AInterrupt mask register2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDET Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 ASLOTR ASLOTR ASlot register 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 ASR ASR AStatus register 0x18 32 read-write n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 BCLRFR BCLRFR BClear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 BCR1 BCR1 BConfiguration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 4 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIBEN Audio block B enable 16 1 SYNCEN Synchronization enable 10 2 BCR2 BCR2 BConfiguration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 BDR BDR BData register 0x40 32 read-write n 0x0 0x0 DATA Data 0 32 BFRCR BFRCR BFRCR 0x2C 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 BIM BIM BInterrupt mask register2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDETIE Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 BSLOTR BSLOTR BSlot register 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 BSR BSR BStatus register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag 2 1 SCB System control block SCB 0x0 0x0 0x41 registers n AFSR AFSR Auxiliary fault status register 0x3C 32 read-write n 0x0 0x0 IMPDEF Implementation defined 0 32 AIRCR AIRCR Application interrupt and reset control register 0xC 32 read-write n 0x0 0x0 ENDIANESS ENDIANESS 15 1 PRIGROUP PRIGROUP 8 3 SYSRESETREQ SYSRESETREQ 2 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 VECTKEYSTAT Register key 16 16 VECTRESET VECTRESET 0 1 BFAR BFAR Bus fault address register 0x38 32 read-write n 0x0 0x0 BFAR Bus fault address 0 32 CCR CCR Configuration and control register 0x14 32 read-write n 0x0 0x0 BFHFNMIGN BFHFNMIGN 8 1 DIV_0_TRP DIV_0_TRP 4 1 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 STKALIGN STKALIGN 9 1 UNALIGN__TRP UNALIGN_ TRP 3 1 USERSETMPEND USERSETMPEND 1 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 32 read-write n 0x0 0x0 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 DIVBYZERO Divide by zero usage fault 25 1 IACCVIOL Instruction access violation flag 1 1 IBUSERR Instruction bus error 8 1 IMPRECISERR Imprecise data bus error 10 1 INVPC Invalid PC load usage fault 18 1 INVSTATE Invalid state usage fault 17 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 NOCP No coprocessor usage fault. 19 1 PRECISERR Precise data bus error 9 1 STKERR Bus fault on stacking for exception entry 12 1 UNALIGNED Unaligned access usage fault 24 1 UNDEFINSTR Undefined instruction usage fault 16 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 CPUID CPUID CPUID base register 0x0 32 read-only n 0x0 0x0 Constant Reads as 0xF 16 4 Implementer Implementer code 24 8 PartNo Part number of the processor 4 12 Revision Revision number 0 4 Variant Variant number 20 4 HFSR HFSR Hard fault status register 0x2C 32 read-write n 0x0 0x0 DEBUG_VT Reserved for Debug use 31 1 FORCED Forced hard fault 30 1 VECTTBL Vector table hard fault 1 1 ICSR ICSR Interrupt control and state register 0x4 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag 22 1 NMIPENDSET NMI set-pending bit. 31 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 RETTOBASE Return to base level 11 1 VECTACTIVE Active vector 0 9 VECTPENDING Pending vector 12 7 MMFAR MMFAR Memory management fault address register 0x34 32 read-write n 0x0 0x0 MMFAR Memory management fault address 0 32 SCR SCR System control register 0x10 32 read-write n 0x0 0x0 SEVEONPEND Send Event on Pending bit 4 1 SLEEPDEEP SLEEPDEEP 2 1 SLEEPONEXIT SLEEPONEXIT 1 1 SHCRS SHCRS System handler control and state register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT Bus fault exception active bit 1 1 BUSFAULTENA Bus fault enable bit 17 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 MEMFAULTACT Memory management fault exception active bit 0 1 MEMFAULTENA Memory management fault enable bit 16 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SVCALLACT SVC call active bit 7 1 SVCALLPENDED SVC call pending bit 15 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTACT Usage fault exception active bit 3 1 USGFAULTENA Usage fault enable bit 18 1 USGFAULTPENDED Usage fault exception pending bit 12 1 SHCSR SHCSR System handler control and state register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT Bus fault exception active bit 1 1 BUSFAULTENA Bus fault enable bit 17 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 MEMFAULTACT Memory management fault exception active bit 0 1 MEMFAULTENA Memory management fault enable bit 16 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SVCALLACT SVC call active bit 7 1 SVCALLPENDED SVC call pending bit 15 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTACT Usage fault exception active bit 3 1 USGFAULTENA Usage fault enable bit 18 1 USGFAULTPENDED Usage fault exception pending bit 12 1 SHPR1 SHPR1 System handler priority registers 0x18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 VTOR VTOR Vector table offset register 0x8 32 read-write n 0x0 0x0 TBLOFF Vector table base offset field 9 21 SCB_ACTRL System control block ACTLR SCB 0x0 0x0 0x5 registers n ACTRL ACTRL Auxiliary control register 0x0 32 read-write n 0x0 0x0 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISMCYCINT DISMCYCINT 0 1 DISOOFP DISOOFP 9 1 SDMMC1 Secure digital input/output interface SDIO 0x0 0x0 0x400 registers n SDMMC1 SDMMC global Interrupt 49 ARG ARG argument register 0x8 32 read-write n 0x0 0x0 CMDARG Command argument 0 32 CLKCR CLKCR SDI clock control register 0x4 32 read-write n 0x0 0x0 BYPASS Clock divider bypass enable bit 10 1 CLKDIV Clock divide factor 0 8 CLKEN Clock enable bit 8 1 HWFC_EN HW Flow Control enable 14 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 PWRSAV Power saving configuration bit 9 1 WIDBUS Wide bus mode enable bit 11 2 CMD CMD command register 0xC 32 read-write n 0x0 0x0 CE_ATACMD CE-ATA command 14 1 CMDINDEX Command index 0 6 CPSMEN Command path state machine (CPSM) Enable bit 10 1 ENCMDcompl Enable CMD completion 12 1 nIEN not Interrupt Enable 13 1 SDIOSuspend SD I/O suspend command 11 1 WAITINT CPSM waits for interrupt request 8 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) 9 1 WAITRESP Wait for response bits 6 2 DCOUNT DCOUNT data counter register 0x30 32 read-only n 0x0 0x0 DATACOUNT Data count value 0 25 DCTRL DCTRL data control register 0x2C 32 read-write n 0x0 0x0 DBLOCKSIZE Data block size 4 4 DMAEN DMA enable bit 3 1 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer 2 1 RWMOD Read wait mode 10 1 RWSTART Read wait start 8 1 RWSTOP Read wait stop 9 1 SDIOEN SD I/O enable functions 11 1 DLEN DLEN data length register 0x28 32 read-write n 0x0 0x0 DATALENGTH Data length value 0 25 DTIMER DTIMER data timer register 0x24 32 read-write n 0x0 0x0 DATATIME Data timeout period 0 32 FIFO FIFO data FIFO register 0x80 32 read-write n 0x0 0x0 FIFOData Receive and transmit FIFO data 0 32 FIFOCNT FIFOCNT FIFO counter register 0x48 32 read-only n 0x0 0x0 FIFOCOUNT Remaining number of words to be written to or read from the FIFO 0 24 ICR ICR interrupt clear register 0x38 32 read-write n 0x0 0x0 CCRCFAILC CCRCFAIL flag clear bit 0 1 CEATAENDC CEATAEND flag clear bit 23 1 CMDRENDC CMDREND flag clear bit 6 1 CMDSENTC CMDSENT flag clear bit 7 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DATAENDC DATAEND flag clear bit 8 1 DBCKENDC DBCKEND flag clear bit 10 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 RXOVERRC RXOVERR flag clear bit 5 1 SDIOITC SDIOIT flag clear bit 22 1 STBITERRC STBITERR flag clear bit 9 1 TXUNDERRC TXUNDERR flag clear bit 4 1 MASK MASK mask register 0x3C 32 read-write n 0x0 0x0 CCRCFAILIE Command CRC fail interrupt enable 0 1 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 CMDACTIE Command acting interrupt enable 11 1 CMDRENDIE Command response received interrupt enable 6 1 CMDSENTIE Command sent interrupt enable 7 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DATAENDIE Data end interrupt enable 8 1 DBCKENDIE Data block end interrupt enable 10 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 DTIMEOUTIE Data timeout interrupt enable 3 1 RXACTIE Data receive acting interrupt enable 13 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 STBITERRIE Start bit error interrupt enable 9 1 TXACTIE Data transmit acting interrupt enable 12 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 POWER POWER power control register 0x0 32 read-write n 0x0 0x0 PWRCTRL PWRCTRL 0 2 RESP1 RESP1 response 1..4 register 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 see Table 132 0 32 RESP2 RESP2 response 1..4 register 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 see Table 132 0 32 RESP3 RESP3 response 1..4 register 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 see Table 132 0 32 RESP4 RESP4 response 1..4 register 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 see Table 132 0 32 RESPCMD RESPCMD command response register 0x10 32 read-only n 0x0 0x0 RESPCMD Response command index 0 6 STA STA status register 0x34 32 read-only n 0x0 0x0 CCRCFAIL Command response received (CRC check failed) 0 1 CEATAEND CE-ATA command completion signal received for CMD61 23 1 CMDACT Command transfer in progress 11 1 CMDREND Command response received (CRC check passed) 6 1 CMDSENT Command sent (no response required) 7 1 CTIMEOUT Command response timeout 2 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 DBCKEND Data block sent/received (CRC check passed) 10 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 DTIMEOUT Data timeout 3 1 RXACT Data receive in progress 13 1 RXDAVL Data available in receive FIFO 21 1 RXFIFOE Receive FIFO empty 19 1 RXFIFOF Receive FIFO full 17 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 RXOVERR Received FIFO overrun error 5 1 SDIOIT SDIO interrupt received 22 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 TXACT Data transmit in progress 12 1 TXDAVL Data available in transmit FIFO 20 1 TXFIFOE Transmit FIFO empty 18 1 TXFIFOF Transmit FIFO full 16 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 TXUNDERR Transmit FIFO underrun error 4 1 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 SPI2 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI2 SPI2 global interrupt 36 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 SPI3 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI3 SPI3 global interrupt 51 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 STK SysTick timer STK 0x0 0x0 0x11 registers n CALIB CALIB SysTick calibration value register 0xC 32 read-write n 0x0 0x0 NOREF NOREF flag. Reads as zero 31 1 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 TENMS Calibration value 0 24 CTRL CTRL SysTick control and status register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 LOAD LOAD SysTick reload value register 0x4 32 read-write n 0x0 0x0 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 32 read-write n 0x0 0x0 CURRENT Current counter value 0 24 SWPMI1 Single Wire Protocol Master Interface SWPMI 0x0 0x0 0x400 registers n BRR BRR SWPMI Bitrate register 0x4 32 read-write n 0x0 0x0 BR Bitrate prescaler 0 6 CR CR SWPMI Configuration/Control register 0x0 32 read-write n 0x0 0x0 DEACT Single wire protocol master interface deactivate 10 1 LPBK Loopback mode enable 4 1 RXDMA Reception DMA enable 0 1 RXMODE Reception buffering mode 2 1 SWPME Single wire protocol master interface enable 5 1 TXDMA Transmission DMA enable 1 1 TXMODE Transmission buffering mode 3 1 ICR ICR SWPMI Interrupt Flag Clear register 0x10 32 write-only n 0x0 0x0 CRXBERF Clear receive CRC error flag 2 1 CRXBFF Clear receive buffer full flag 0 1 CRXOVRF Clear receive overrun error flag 3 1 CSRF Clear slave resume flag 8 1 CTCF Clear transfer complete flag 7 1 CTXBEF Clear transmit buffer empty flag 1 1 CTXUNRF Clear transmit underrun error flag 4 1 IER IER SWPMI Interrupt Enable register 0x14 32 read-write n 0x0 0x0 RIE Receive interrupt enable 5 1 RXBERIE Receive CRC error interrupt enable 2 1 RXBFIE Receive buffer full interrupt enable 0 1 RXOVRIE Receive overrun error interrupt enable 3 1 SRIE Slave resume interrupt enable 8 1 TCIE Transmit complete interrupt enable 7 1 TIE Transmit interrupt enable 6 1 TXBEIE Transmit buffer empty interrupt enable 1 1 TXUNRIE Transmit underrun error interrupt enable 4 1 ISR ISR SWPMI Interrupt and Status register 0xC 32 read-only n 0x0 0x0 DEACTF DEACTIVATED flag 10 1 RXBERF Receive CRC error flag 2 1 RXBFF Receive buffer full flag 0 1 RXNE Receive data register not empty 5 1 RXOVRF Receive overrun error flag 3 1 SRF Slave resume flag 8 1 SUSP SUSPEND flag 9 1 TCF Transfer complete flag 7 1 TXBEF Transmit buffer empty flag 1 1 TXE Transmit data register empty 6 1 TXUNRF Transmit underrun error flag 4 1 RDR RDR SWPMI Receive data register 0x20 32 read-only n 0x0 0x0 RD received data 0 32 RFL RFL SWPMI Receive Frame Length register 0x18 32 read-only n 0x0 0x0 RFL Receive frame length 0 5 TDR TDR SWPMI Transmit data register 0x1C 32 write-only n 0x0 0x0 TD Transmit data 0 32 SYSCFG System configuration controller SYSCFG 0x0 0x0 0x30 registers n CFGR1 CFGR1 configuration register 1 0x4 32 read-write n 0x0 0x0 BOOSTEN I/O analog switch voltage booster enable 8 1 FPU_IE Floating Point Unit interrupts enable bits 26 6 FWDIS Firewall disable 0 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 CFGR2 CFGR2 CFGR2 0x1C 32 read-write n 0x0 0x0 CLL Cortex-M4 LOCKUP (Hardfault) output enable bit 0 1 write-only ECCL ECC Lock 3 1 write-only PVDL PVD lock enable bit 2 1 write-only SPF SRAM2 parity error flag 8 1 read-write SPL SRAM2 parity lock bit 1 1 write-only EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 32 read-write n 0x0 0x0 EXTI0 EXTI 0 configuration bits 0 3 EXTI1 EXTI 1 configuration bits 4 3 EXTI2 EXTI 2 configuration bits 8 3 EXTI3 EXTI 3 configuration bits 12 3 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 32 read-write n 0x0 0x0 EXTI4 EXTI 4 configuration bits 0 3 EXTI5 EXTI 5 configuration bits 4 3 EXTI6 EXTI 6 configuration bits 8 3 EXTI7 EXTI 7 configuration bits 12 3 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 32 read-write n 0x0 0x0 EXTI10 EXTI 10 configuration bits 8 3 EXTI11 EXTI 11 configuration bits 12 3 EXTI8 EXTI 8 configuration bits 0 3 EXTI9 EXTI 9 configuration bits 4 3 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 32 read-write n 0x0 0x0 EXTI12 EXTI12 configuration bits 0 3 EXTI13 EXTI13 configuration bits 4 3 EXTI14 EXTI14 configuration bits 8 3 EXTI15 EXTI15 configuration bits 12 3 MEMRMP MEMRMP memory remap register 0x0 32 read-write n 0x0 0x0 FB_MODE Flash Bank mode selection 8 1 MEM_MODE Memory mapping selection 0 3 QFS QUADSPI memory mapping swap 3 1 SCSR SCSR SCSR 0x18 32 read-write n 0x0 0x0 SRAM2BSY SRAM2 busy by erase operation 1 1 read-only SRAM2ER SRAM2 Erase 0 1 read-write SKR SKR SKR 0x24 32 write-only n 0x0 0x0 KEY SRAM2 write protection key for software erase 0 8 SWPR SWPR SWPR 0x20 32 write-only n 0x0 0x0 P0WP P0WP 0 1 P10WP P10WP 10 1 P11WP P11WP 11 1 P12WP P12WP 12 1 P13WP P13WP 13 1 P14WP P14WP 14 1 P15WP P15WP 15 1 P16WP P16WP 16 1 P17WP P17WP 17 1 P18WP P18WP 18 1 P19WP P19WP 19 1 P1WP P1WP 1 1 P20WP P20WP 20 1 P21WP P21WP 21 1 P22WP P22WP 22 1 P23WP P23WP 23 1 P24WP P24WP 24 1 P25WP P25WP 25 1 P26WP P26WP 26 1 P27WP P27WP 27 1 P28WP P28WP 28 1 P29WP P29WP 29 1 P2WP P2WP 2 1 P30WP P30WP 30 1 P31WP SRAM2 page 31 write protection 31 1 P3WP P3WP 3 1 P4WP P4WP 4 1 P5WP P5WP 5 1 P6WP P6WP 6 1 P7WP P7WP 7 1 P8WP P8WP 8 1 P9WP P9WP 9 1 TIM1 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM1_BRK_TIM15 TIM1 Break/TIM15 global interrupts 24 TIM1_UP_TIM16 TIM1 Update/TIM16 global interrupts 25 TIM1_TRG_COM_TIM17 TIM1 Trigger and Commutation interrupts and TIM17 global interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x58 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 DMA address for full transfer 0x50 32 read-write n 0x0 0x0 ETR_ADC1_RMP External trigger remap on ADC1 analog watchdog 0 2 ETR_ADC3_RMP External trigger remap on ADC3 analog watchdog 2 2 TI1_RMP Input Capture 1 remap 4 1 OR2 OR2 DMA address for full transfer 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKDFBK0E BRK DFSDM_BREAK0 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INE BRK2 BKIN input enable 0 1 BK2INP BRK2 BKIN input polarity 9 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM15 General purpose timers TIM 0x0 0x0 0x400 registers n ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_2 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM16 General purpose timers TIM 0x0 0x0 0x400 registers n ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_2 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 TIM16 option register 1 0x50 32 read-write n 0x0 0x0 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarit 11 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM17 General purpose timers TIM 0x0 0x0 0x400 registers n ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_2 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 TIM16 option register 1 0x50 32 read-write n 0x0 0x0 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarit 11 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM2 General-purpose-timers TIM 0x0 0x0 0x400 registers n TIM2 TIM2 global interrupt 28 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR OR TIM2 option register 0x50 32 read-write n 0x0 0x0 ETR_RMP Timer2 ETR remap 0 3 TI4_RMP Internal trigger 3 2 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM3 General-purpose-timers TIM 0x0 0x0 0x400 registers n TIM3 TIM3 global interrupt 29 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR OR TIM2 option register 0x50 32 read-write n 0x0 0x0 ETR_RMP Timer2 ETR remap 0 3 TI4_RMP Internal trigger 3 2 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM4 General-purpose-timers TIM 0x0 0x0 0x400 registers n TIM4 TIM4 global interrupt 30 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR OR TIM2 option register 0x50 32 read-write n 0x0 0x0 ETR_RMP Timer2 ETR remap 0 3 TI4_RMP Internal trigger 3 2 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM5 General-purpose-timers TIM 0x0 0x0 0x400 registers n TIM5 TIM5 global interrupt 50 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 OR OR TIM2 option register 0x50 32 read-write n 0x0 0x0 ETR_RMP Timer2 ETR remap 0 3 TI4_RMP Internal trigger 3 2 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TIM6 Basic-timers TIM 0x0 0x0 0x400 registers n TIM6_DACUNDER TIM6 global and DAC1 and 2 underrun error interrupts 54 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 TIM7 Basic-timers TIM 0x0 0x0 0x400 registers n TIM7 TIM7 global interrupt 55 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 TIM8 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM8_BRK TIM8 Break Interrupt 43 TIM8_UP TIM8 Update Interrupt 44 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 45 TIM8_CC TIM8 Capture Compare Interrupt 46 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x58 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x48 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 OR1 OR1 DMA address for full transfer 0x50 32 read-write n 0x0 0x0 ETR_ADC2_RMP External trigger remap on ADC2 analog watchdog 0 2 ETR_ADC3_RMP External trigger remap on ADC3 analog watchdog 2 2 TI1_RMP Input Capture 1 remap 4 1 OR2 OR2 DMA address for full transfer 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKDFBK2E BRK DFSDM_BREAK2 enable 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2DFBK3E BRK2 DFSDM_BREAK3 enable 8 1 BK2INE BRK2 BKIN input enable 0 1 BK2INP BRK2 BKIN input polarity 9 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TSC Touch sensing controller TSC 0x0 0x0 0x400 registers n TSC TSC global interrupt 77 CR CR control register 0x0 32 read-write n 0x0 0x0 AM Acquisition mode 2 1 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 IODEF I/O Default mode 4 1 MCV Max count value 5 3 PGPSC pulse generator prescaler 12 3 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSPSC Spread spectrum prescaler 15 1 START Start a new acquisition 1 1 SYNCPOL Synchronization pin polarity 3 1 TSCE Touch sensing controller enable 0 1 ICR ICR interrupt clear register 0x8 32 read-write n 0x0 0x0 EOAIC End of acquisition interrupt clear 0 1 MCEIC Max count error interrupt clear 1 1 IER IER interrupt enable register 0x4 32 read-write n 0x0 0x0 EOAIE End of acquisition interrupt enable 0 1 MCEIE Max count error interrupt enable 1 1 IOASCR IOASCR I/O analog switch control register 0x18 32 read-write n 0x0 0x0 G1_IO1 G1_IO1 0 1 G1_IO2 G1_IO2 1 1 G1_IO3 G1_IO3 2 1 G1_IO4 G1_IO4 3 1 G2_IO1 G2_IO1 4 1 G2_IO2 G2_IO2 5 1 G2_IO3 G2_IO3 6 1 G2_IO4 G2_IO4 7 1 G3_IO1 G3_IO1 8 1 G3_IO2 G3_IO2 9 1 G3_IO3 G3_IO3 10 1 G3_IO4 G3_IO4 11 1 G4_IO1 G4_IO1 12 1 G4_IO2 G4_IO2 13 1 G4_IO3 G4_IO3 14 1 G4_IO4 G4_IO4 15 1 G5_IO1 G5_IO1 16 1 G5_IO2 G5_IO2 17 1 G5_IO3 G5_IO3 18 1 G5_IO4 G5_IO4 19 1 G6_IO1 G6_IO1 20 1 G6_IO2 G6_IO2 21 1 G6_IO3 G6_IO3 22 1 G6_IO4 G6_IO4 23 1 G7_IO1 G7_IO1 24 1 G7_IO2 G7_IO2 25 1 G7_IO3 G7_IO3 26 1 G7_IO4 G7_IO4 27 1 G8_IO1 G8_IO1 28 1 G8_IO2 G8_IO2 29 1 G8_IO3 G8_IO3 30 1 G8_IO4 G8_IO4 31 1 IOCCR IOCCR I/O channel control register 0x28 32 read-write n 0x0 0x0 G1_IO1 G1_IO1 0 1 G1_IO2 G1_IO2 1 1 G1_IO3 G1_IO3 2 1 G1_IO4 G1_IO4 3 1 G2_IO1 G2_IO1 4 1 G2_IO2 G2_IO2 5 1 G2_IO3 G2_IO3 6 1 G2_IO4 G2_IO4 7 1 G3_IO1 G3_IO1 8 1 G3_IO2 G3_IO2 9 1 G3_IO3 G3_IO3 10 1 G3_IO4 G3_IO4 11 1 G4_IO1 G4_IO1 12 1 G4_IO2 G4_IO2 13 1 G4_IO3 G4_IO3 14 1 G4_IO4 G4_IO4 15 1 G5_IO1 G5_IO1 16 1 G5_IO2 G5_IO2 17 1 G5_IO3 G5_IO3 18 1 G5_IO4 G5_IO4 19 1 G6_IO1 G6_IO1 20 1 G6_IO2 G6_IO2 21 1 G6_IO3 G6_IO3 22 1 G6_IO4 G6_IO4 23 1 G7_IO1 G7_IO1 24 1 G7_IO2 G7_IO2 25 1 G7_IO3 G7_IO3 26 1 G7_IO4 G7_IO4 27 1 G8_IO1 G8_IO1 28 1 G8_IO2 G8_IO2 29 1 G8_IO3 G8_IO3 30 1 G8_IO4 G8_IO4 31 1 IOG1CR IOG1CR I/O group x counter register 0x34 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG2CR IOG2CR I/O group x counter register 0x38 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG3CR IOG3CR I/O group x counter register 0x3C 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG4CR IOG4CR I/O group x counter register 0x40 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG5CR IOG5CR I/O group x counter register 0x44 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG6CR IOG6CR I/O group x counter register 0x48 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG7CR IOG7CR I/O group x counter register 0x4C 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOG8CR IOG8CR I/O group x counter register 0x50 32 read-only n 0x0 0x0 CNT Counter value 0 14 IOGCSR IOGCSR I/O group control status register 0x30 32 read-write n 0x0 0x0 G1E Analog I/O group x enable 0 1 read-write G1S Analog I/O group x status 16 1 read-only G2E Analog I/O group x enable 1 1 read-write G2S Analog I/O group x status 17 1 read-only G3E Analog I/O group x enable 2 1 read-write G3S Analog I/O group x status 18 1 read-only G4E Analog I/O group x enable 3 1 read-write G4S Analog I/O group x status 19 1 read-only G5E Analog I/O group x enable 4 1 read-write G5S Analog I/O group x status 20 1 read-only G6E Analog I/O group x enable 5 1 read-write G6S Analog I/O group x status 21 1 read-only G7E Analog I/O group x enable 6 1 read-write G7S Analog I/O group x status 22 1 read-only G8E Analog I/O group x enable 7 1 read-write G8S Analog I/O group x status 23 1 read-only IOHCR IOHCR I/O hysteresis control register 0x10 32 read-write n 0x0 0x0 G1_IO1 G1_IO1 0 1 G1_IO2 G1_IO2 1 1 G1_IO3 G1_IO3 2 1 G1_IO4 G1_IO4 3 1 G2_IO1 G2_IO1 4 1 G2_IO2 G2_IO2 5 1 G2_IO3 G2_IO3 6 1 G2_IO4 G2_IO4 7 1 G3_IO1 G3_IO1 8 1 G3_IO2 G3_IO2 9 1 G3_IO3 G3_IO3 10 1 G3_IO4 G3_IO4 11 1 G4_IO1 G4_IO1 12 1 G4_IO2 G4_IO2 13 1 G4_IO3 G4_IO3 14 1 G4_IO4 G4_IO4 15 1 G5_IO1 G5_IO1 16 1 G5_IO2 G5_IO2 17 1 G5_IO3 G5_IO3 18 1 G5_IO4 G5_IO4 19 1 G6_IO1 G6_IO1 20 1 G6_IO2 G6_IO2 21 1 G6_IO3 G6_IO3 22 1 G6_IO4 G6_IO4 23 1 G7_IO1 G7_IO1 24 1 G7_IO2 G7_IO2 25 1 G7_IO3 G7_IO3 26 1 G7_IO4 G7_IO4 27 1 G8_IO1 G8_IO1 28 1 G8_IO2 G8_IO2 29 1 G8_IO3 G8_IO3 30 1 G8_IO4 G8_IO4 31 1 IOSCR IOSCR I/O sampling control register 0x20 32 read-write n 0x0 0x0 G1_IO1 G1_IO1 0 1 G1_IO2 G1_IO2 1 1 G1_IO3 G1_IO3 2 1 G1_IO4 G1_IO4 3 1 G2_IO1 G2_IO1 4 1 G2_IO2 G2_IO2 5 1 G2_IO3 G2_IO3 6 1 G2_IO4 G2_IO4 7 1 G3_IO1 G3_IO1 8 1 G3_IO2 G3_IO2 9 1 G3_IO3 G3_IO3 10 1 G3_IO4 G3_IO4 11 1 G4_IO1 G4_IO1 12 1 G4_IO2 G4_IO2 13 1 G4_IO3 G4_IO3 14 1 G4_IO4 G4_IO4 15 1 G5_IO1 G5_IO1 16 1 G5_IO2 G5_IO2 17 1 G5_IO3 G5_IO3 18 1 G5_IO4 G5_IO4 19 1 G6_IO1 G6_IO1 20 1 G6_IO2 G6_IO2 21 1 G6_IO3 G6_IO3 22 1 G6_IO4 G6_IO4 23 1 G7_IO1 G7_IO1 24 1 G7_IO2 G7_IO2 25 1 G7_IO3 G7_IO3 26 1 G7_IO4 G7_IO4 27 1 G8_IO1 G8_IO1 28 1 G8_IO2 G8_IO2 29 1 G8_IO3 G8_IO3 30 1 G8_IO4 G8_IO4 31 1 ISR ISR interrupt status register 0xC 32 read-write n 0x0 0x0 EOAF End of acquisition flag 0 1 MCEF Max count error flag 1 1 UART4 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n UART4 Uart4 Interrupt 8 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 UART5 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n UART5 UART5 global interrupt 53 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART1 USART1 global interrupt 37 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART2 USART2 global interrupt 38 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART3 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART3 USART3 global interrupt 39 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 WUF WUF 20 1 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VREFBUF Voltage reference buffer VREF 0x0 0x0 0x1D0 registers n CCR CCR calibration control register 0x4 32 read-write n 0x0 0x0 TRIM Trimming code 0 6 CSR CSR VREF control and status register 0x0 32 read-write n 0x0 0x0 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 2 1 read-write WWDG System window watchdog WWDG 0x0 0x0 0x400 registers n WWDG Window Watchdog interrupt 0 CFR CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 WDGTB Timer base 7 2 CR CR Control register 0x0 32 read-write n 0x0 0x0 T 7-bit counter (MSB to LSB) 0 7 WDGA Activation bit 7 1 SR SR Status register 0x8 32 read-write n 0x0 0x0 EWIF Early wakeup interrupt flag 0 1