STMicroelectronics STM32MP153x 2024.04.28 STM32MP153x 8 32 ADC ADC ADC 0x0 0x0 0x100 registers n AWD2CR ADC_AWD2CR ADC analog watchdog 2 configuration register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 20 AWD3CR ADC_AWD3CR ADC analog watchdog 3 configuration register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 20 CALFACT ADC_CALFACT ADC calibration factors register 0xC4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 11 CALFACT_S CALFACT_S 0 11 CALFACT2 ADC_CALFACT2 ADC calibration factor register 2 0xC8 32 read-write n 0x0 0x0 LINCALFACT LINCALFACT 0 30 CFGR ADC_CFGR ADC configuration register 0xC 32 read-write n 0x0 0x0 AUTDLY AUTDLY 14 1 AWD1CH AWD1CH 26 5 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMNGT DMNGT 0 2 EXTEN EXTEN 10 2 EXTSEL EXTSEL 5 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS JQDIS 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 2 3 CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 32 read-write n 0x0 0x0 JOVSE JOVSE 1 1 LSHIFT LSHIFT 28 4 OSVR OSVR 16 10 OVSS OVSS 5 4 ROVSE ROVSE 0 1 ROVSM ROVSM 10 1 RSHIFT1 RSHIFT1 11 1 RSHIFT2 RSHIFT2 12 1 RSHIFT3 RSHIFT3 13 1 RSHIFT4 RSHIFT4 14 1 TROVS TROVS 9 1 CR ADC_CR ADC control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADCALLIN ADCALLIN 16 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 BOOST BOOST 8 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 LINCALRDYW1 LINCALRDYW1 22 1 LINCALRDYW2 LINCALRDYW2 23 1 LINCALRDYW3 LINCALRDYW3 24 1 LINCALRDYW4 LINCALRDYW4 25 1 LINCALRDYW5 LINCALRDYW5 26 1 LINCALRDYW6 LINCALRDYW6 27 1 DIFSEL ADC_DIFSEL ADC differential mode selection register 0xC0 32 read-write n 0x0 0x0 DIFSEL DIFSEL 0 20 DR ADC_DR ADC regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA RDATA 0 32 HTR1 ADC_HTR1 ADC watchdog threshold register 1 0x24 32 read-write n 0x0 0x0 HTR1 HTR1 0 26 HTR2 ADC_HTR2 ADC watchdog higher threshold register 2 0xB4 32 read-write n 0x0 0x0 HTR2 HTR2 0 26 HTR3 ADC_HTR3 ADC watchdog higher threshold register 3 0xBC 32 read-write n 0x0 0x0 HTR3 HTR3 0 26 IER ADC_IER ADC interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ISR ADC_ISR ADC interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 JDR1 ADC_JDR1 ADC injected data register 0x80 32 read-only n 0x0 0x0 JDATA JDATA 0 32 JDR2 ADC_JDR2 ADC injected data register 0x84 32 read-only n 0x0 0x0 JDATA JDATA 0 32 JDR3 ADC_JDR3 ADC injected data register 0x88 32 read-only n 0x0 0x0 JDATA JDATA 0 32 JDR4 ADC_JDR4 ADC injected data register 0x8C 32 read-only n 0x0 0x0 JDATA JDATA 0 32 JSQR ADC_JSQR ADC injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 LTR1 ADC_LTR1 ADC watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 LTR1 LTR1 0 26 LTR2 ADC_LTR2 ADC watchdog lower threshold register 2 0xB0 32 read-write n 0x0 0x0 LTR2 LTR2 0 26 LTR3 ADC_LTR3 ADC watchdog lower threshold register 3 0xB8 32 read-write n 0x0 0x0 LTR3 LTR3 0 26 OFR1 ADC_OFR1 ADC offset register 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 26 OFFSET1_CH OFFSET1_CH 26 5 SSATE SSATE 31 1 OFR2 ADC_OFR2 ADC offset register 0x64 32 read-write n 0x0 0x0 OFFSET2 OFFSET2 0 26 OFFSET2_CH OFFSET2_CH 26 5 SSATE SSATE 31 1 OFR3 ADC_OFR3 ADC offset register 0x68 32 read-write n 0x0 0x0 OFFSET3 OFFSET3 0 26 OFFSET3_CH OFFSET3_CH 26 5 SSATE SSATE 31 1 OFR4 ADC_OFR4 ADC offset register 0x6C 32 read-write n 0x0 0x0 OFFSET4 OFFSET4 0 26 OFFSET4_CH OFFSET4_CH 26 5 SSATE SSATE 31 1 PCSEL ADC_PCSEL ADC channel preselection register 0x1C 32 read-write n 0x0 0x0 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 SMPR1 ADC_SMPR1 ADC sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPR2 ADC_SMPR2 ADC sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SMP19 SMP19 27 3 SQR1 ADC_SQR1 ADC regular sequence register 1 0x30 32 read-write n 0x0 0x0 L L 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 ADC_SQR2 ADC regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 ADC_SQR3 ADC regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 ADC_SQR4 ADC regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 ADC2 ADC2 ADC2 0x0 0x0 0x100 registers n ADC_AWD2CR ADC_AWD2CR ADC analog watchdog 2 configuration register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 20 ADC_AWD3CR ADC_AWD3CR ADC analog watchdog 3 configuration register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 20 ADC_CALFACT ADC_CALFACT ADC calibration factors register 0xC4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 11 CALFACT_S CALFACT_S 0 11 ADC_CALFACT2 ADC_CALFACT2 ADC calibration factor register 2 0xC8 32 read-write n 0x0 0x0 LINCALFACT LINCALFACT 0 30 ADC_CFGR ADC_CFGR ADC configuration register 0xC 32 read-write n 0x0 0x0 AUTDLY AUTDLY 14 1 AWD1CH AWD1CH 26 5 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMNGT DMNGT 0 2 EXTEN EXTEN 10 2 EXTSEL EXTSEL 5 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS JQDIS 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 2 3 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 32 read-write n 0x0 0x0 JOVSE JOVSE 1 1 LSHIFT LSHIFT 28 4 OSVR OSVR 16 10 OVSS OVSS 5 4 ROVSE ROVSE 0 1 ROVSM ROVSM 10 1 RSHIFT1 RSHIFT1 11 1 RSHIFT2 RSHIFT2 12 1 RSHIFT3 RSHIFT3 13 1 RSHIFT4 RSHIFT4 14 1 TROVS TROVS 9 1 ADC_CR ADC_CR ADC control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADCALLIN ADCALLIN 16 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 BOOST BOOST 8 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 LINCALRDYW1 LINCALRDYW1 22 1 LINCALRDYW2 LINCALRDYW2 23 1 LINCALRDYW3 LINCALRDYW3 24 1 LINCALRDYW4 LINCALRDYW4 25 1 LINCALRDYW5 LINCALRDYW5 26 1 LINCALRDYW6 LINCALRDYW6 27 1 ADC_DIFSEL ADC_DIFSEL ADC differential mode selection register 0xC0 32 read-write n 0x0 0x0 DIFSEL DIFSEL 0 20 ADC_DR ADC_DR ADC regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA RDATA 0 32 ADC_HTR1 ADC_HTR1 ADC watchdog threshold register 1 0x24 32 read-write n 0x0 0x0 HTR1 HTR1 0 26 ADC_HTR2 ADC_HTR2 ADC watchdog higher threshold register 2 0xB4 32 read-write n 0x0 0x0 HTR2 HTR2 0 26 ADC_HTR3 ADC_HTR3 ADC watchdog higher threshold register 3 0xBC 32 read-write n 0x0 0x0 HTR3 HTR3 0 26 ADC_IER ADC_IER ADC interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ADC_ISR ADC_ISR ADC interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 ADC_JDR1 ADC_JDR1 ADC injected data register 0x80 32 read-only n 0x0 0x0 JDATA JDATA 0 32 ADC_JDR2 ADC_JDR2 ADC injected data register 0x84 32 read-only n 0x0 0x0 JDATA JDATA 0 32 ADC_JDR3 ADC_JDR3 ADC injected data register 0x88 32 read-only n 0x0 0x0 JDATA JDATA 0 32 ADC_JDR4 ADC_JDR4 ADC injected data register 0x8C 32 read-only n 0x0 0x0 JDATA JDATA 0 32 ADC_JSQR ADC_JSQR ADC injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 ADC_LTR1 ADC_LTR1 ADC watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 LTR1 LTR1 0 26 ADC_LTR2 ADC_LTR2 ADC watchdog lower threshold register 2 0xB0 32 read-write n 0x0 0x0 LTR2 LTR2 0 26 ADC_LTR3 ADC_LTR3 ADC watchdog lower threshold register 3 0xB8 32 read-write n 0x0 0x0 LTR3 LTR3 0 26 ADC_OFR1 ADC_OFR1 ADC offset register 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 26 OFFSET1_CH OFFSET1_CH 26 5 SSATE SSATE 31 1 ADC_OFR2 ADC_OFR2 ADC offset register 0x64 32 read-write n 0x0 0x0 OFFSET2 OFFSET2 0 26 OFFSET2_CH OFFSET2_CH 26 5 SSATE SSATE 31 1 ADC_OFR3 ADC_OFR3 ADC offset register 0x68 32 read-write n 0x0 0x0 OFFSET3 OFFSET3 0 26 OFFSET3_CH OFFSET3_CH 26 5 SSATE SSATE 31 1 ADC_OFR4 ADC_OFR4 ADC offset register 0x6C 32 read-write n 0x0 0x0 OFFSET4 OFFSET4 0 26 OFFSET4_CH OFFSET4_CH 26 5 SSATE SSATE 31 1 ADC_PCSEL ADC_PCSEL ADC channel preselection register 0x1C 32 read-write n 0x0 0x0 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 ADC_SMPR1 ADC_SMPR1 ADC sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 ADC_SMPR2 ADC_SMPR2 ADC sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SMP19 SMP19 27 3 ADC_SQR1 ADC_SQR1 ADC regular sequence register 1 0x30 32 read-write n 0x0 0x0 L L 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 ADC_SQR2 ADC_SQR2 ADC regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 ADC_SQR3 ADC_SQR3 ADC regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 ADC_SQR4 ADC_SQR4 ADC regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 OR ADC2_OR ADC2 option register 0xD0 32 read-write n 0x0 0x0 VDDCOREEN VDDCOREEN 0 1 ADC_common Analog-to-Digital Converter ADC 0x0 0x0 0x100 registers n CCR CCR ADC common control register 0x8 32 read-write n 0x0 0x0 CH17SEL CH17SEL 23 1 CH18SEL CH18SEL 24 1 CKMODE ADC clock mode 16 2 DELAY DELAY 8 3 DMACFG DMACFG 13 1 DUAL DUAL 0 5 MDMA MDMA 14 2 PRESC ADC prescaler 18 4 VREFEN VREFINT enable 22 1 CDR CDR Common regular data register for dual mode 0xC 32 read-only n 0x0 0x0 RDATA_MST RDATA_MST 0 16 RDATA_SLV RDATA_SLV 16 16 CDR2 CDR2 Common regular data register for dual mode 0x10 32 read-only n 0x0 0x0 RDATA_ALT RDATA_ALT 0 32 CSR CSR ADC Common status register 0x0 32 read-only n 0x0 0x0 ADDRDY_MST ADDRDY_MST 0 1 ADRDY_SLV ADRDY_SLV 16 1 AWD1_MST AWD1_MST 7 1 AWD1_SLV AWD1_SLV 23 1 AWD2_MST AWD2_MST 8 1 AWD2_SLV AWD2_SLV 24 1 AWD3_MST AWD3_MST 9 1 AWD3_SLV AWD3_SLV 25 1 EOC_MST EOC_MST 2 1 EOC_SLV EOC_SLV 18 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_SLV EOSMP_SLV 17 1 EOS_MST EOS_MST 3 1 EOS_SLV EOS_SLV 19 1 JEOC_MST JEOC_MST 5 1 JEOC_SLV JEOC_SLV 21 1 JEOS_MST JEOS_MST 6 1 JEOS_SLV JEOS_SLV 22 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_SLV JQOVF_SLV 26 1 OVR_MST OVR_MST 4 1 OVR_SLV OVR_SLV 20 1 AXIMC_Mx AXIMC_Mx AXIMC_Mx 0x0 0x0 0x100000 registers n AXIMC_COMP_ID_0 AXIMC_COMP_ID_0 AXIMC component ID0 register 0x1FF0 32 read-only n 0x0 0x0 PREAMBLE PREAMBLE 0 8 read-only AXIMC_COMP_ID_1 AXIMC_COMP_ID_1 AXIMC component ID1 register 0x1FF4 32 read-only n 0x0 0x0 CLASS CLASS 4 4 read-only PREAMBLE PREAMBLE 0 4 read-only AXIMC_COMP_ID_2 AXIMC_COMP_ID_2 AXIMC component ID2 register 0x1FF8 32 read-only n 0x0 0x0 PREAMBLE PREAMBLE 0 8 read-only AXIMC_COMP_ID_3 AXIMC_COMP_ID_3 AXIMC component ID3 register 0x1FFC 32 read-only n 0x0 0x0 PREAMBLE PREAMBLE 0 8 read-only AXIMC_FN_MOD_LB AXIMC_FN_MOD_LB AXIMC long burst capability inhibition register 0x4A02C 32 read-write n 0x0 0x0 FN_MOD_LB FN_MOD_LB 0 1 read-write AXIMC_M0_FN_MOD AXIMC_M0_FN_MOD AXIMC master 0 issuing capability override functionality register 0xE0 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M0_FN_MOD2 AXIMC_M0_FN_MOD2 AXIMC master 0 packing functionality register 0x0 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M0_FN_MOD_AHB AXIMC_M0_FN_MOD_AHB AXIMC master 0 AHB conversion override functionality register 0x42028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write AXIMC_M0_READ_QOS AXIMC_M0_READ_QOS AXIMC master 0 read priority register 0xDC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M0_WRITE_QOS AXIMC_M0_WRITE_QOS AXIMC master 0 write priority register 0xE4 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M10_FN_MOD AXIMC_M10_FN_MOD AXIMC master 10 issuing capability override functionality register 0xA0E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M10_READ_QOS AXIMC_M10_READ_QOS AXIMC master 10 read priority register 0xA0DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M10_WRITE_QOS AXIMC_M10_WRITE_QOS AXIMC master 10 write priority register 0xA0E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M1_FN_MOD AXIMC_M1_FN_MOD AXIMC master 1 issuing capability override functionality register 0x10E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M1_FN_MOD2 AXIMC_M1_FN_MOD2 AXIMC master 1 packing functionality register 0x1000 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M1_FN_MOD_AHB AXIMC_M1_FN_MOD_AHB AXIMC master 1 AHB conversion override functionality register 0x43028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write AXIMC_M1_READ_QOS AXIMC_M1_READ_QOS AXIMC master 1 read priority register 0x10DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M1_WRITE_QOS AXIMC_M1_WRITE_QOS AXIMC master 1 write priority register 0x10E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M2_FN_MOD AXIMC_M2_FN_MOD AXIMC master 2 issuing capability override functionality register 0x20E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M2_FN_MOD2 AXIMC_M2_FN_MOD2 AXIMC master 2 packing functionality register 0x2000 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M2_FN_MOD_AHB AXIMC_M2_FN_MOD_AHB AXIMC master 2 AHB conversion override functionality register 0x44028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write AXIMC_M2_READ_QOS AXIMC_M2_READ_QOS AXIMC master 2 read priority register 0x20DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M2_WRITE_QOS AXIMC_M2_WRITE_QOS AXIMC master 2 write priority register 0x20E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M3_FN_MOD AXIMC_M3_FN_MOD AXIMC master 3 packing functionality register 0x40E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M3_READ_QOS AXIMC_M3_READ_QOS AXIMC master 3 read priority register 0x40DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M3_WRITE_QOS AXIMC_M3_WRITE_QOS AXIMC master 3 write priority register 0x40E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M4_FN_MOD AXIMC_M4_FN_MOD AXIMC master 4 packing functionality register 0x80E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M4_FN_MOD2 AXIMC_M4_FN_MOD2 AXIMC master 4 packing functionality register 0x8000 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M4_READ_QOS AXIMC_M4_READ_QOS AXIMC master 4 read priority register 0x80DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M4_WRITE_QOS AXIMC_M4_WRITE_QOS AXIMC master 4 write priority register 0x80E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M5_FN_MOD AXIMC_M5_FN_MOD AXIMC master 5 issuing capability override functionality register 0x30E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M5_FN_MOD2 AXIMC_M5_FN_MOD2 AXIMC master 5 packing functionality register 0x3000 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M5_FN_MOD_AHB AXIMC_M5_FN_MOD_AHB AXIMC master 5 AHB conversion override functionality register 0x45028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write AXIMC_M5_READ_QOS AXIMC_M5_READ_QOS AXIMC master 5 read priority register 0x30DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M5_WRITE_QOS AXIMC_M5_WRITE_QOS AXIMC master 5 write priority register 0x30E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M6_FN_MOD AXIMC_M6_FN_MOD AXIMC master 6 issuing capability override functionality register 0xB0E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M6_FN_MOD2 AXIMC_M6_FN_MOD2 AXIMC master 6 packing functionality register 0xB000 32 read-write n 0x0 0x0 BYPASS_MERGE BYPASS_MERGE 0 1 read-write AXIMC_M6_FN_MOD_AHB AXIMC_M6_FN_MOD_AHB AXIMC master 6 AHB conversion override functionality register 0x4D028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE RD_INC_OVERRIDE 0 1 read-write WR_INC_OVERRIDE WR_INC_OVERRIDE 1 1 read-write AXIMC_M6_READ_QOS AXIMC_M6_READ_QOS AXIMC master 6 read priority register 0xB0DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M6_WRITE_QOS AXIMC_M6_WRITE_QOS AXIMC master 6 write priority register 0xB0E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M7_FN_MOD AXIMC_M7_FN_MOD AXIMC master 7 issuing capability override functionality register 0x50E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M7_READ_QOS AXIMC_M7_READ_QOS AXIMC master 7 read priority register 0x50DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M7_WRITE_QOS AXIMC_M7_WRITE_QOS AXIMC master 7 write priority register 0x50E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M8_FN_MOD AXIMC_M8_FN_MOD AXIMC master 8 issuing capability override functionality register 0x60E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M8_READ_QOS AXIMC_M8_READ_QOS AXIMC master 8 read priority register 0x60DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M8_WRITE_QOS AXIMC_M8_WRITE_QOS AXIMC master 8 write priority register 0x60E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_M9_FN_MOD AXIMC_M9_FN_MOD AXIMC master 9 issuing capability override functionality register 0x90E4 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE READ_ISS_OVERRIDE 0 1 read-write WRITE_ISS_OVERRIDE WRITE_ISS_OVERRIDE 1 1 read-write AXIMC_M9_READ_QOS AXIMC_M9_READ_QOS AXIMC master 9 read priority register 0x90DC 32 read-write n 0x0 0x0 AR_QOS AR_QOS 0 4 read-write AXIMC_M9_WRITE_QOS AXIMC_M9_WRITE_QOS AXIMC master 9 write priority register 0x90E0 32 read-write n 0x0 0x0 AW_QOS AW_QOS 0 4 read-write AXIMC_PERIPH_ID_0 AXIMC_PERIPH_ID_0 AXIMC peripheral ID0 register 0x1FE0 32 read-only n 0x0 0x0 PERIPH_ID_0 PERIPH_ID_0 0 8 read-only AXIMC_PERIPH_ID_1 AXIMC_PERIPH_ID_1 AXIMC peripheral ID1 register 0x1FE4 32 read-only n 0x0 0x0 PERIPH_ID_1 PERIPH_ID_1 0 8 read-only AXIMC_PERIPH_ID_2 AXIMC_PERIPH_ID_2 AXIMC peripheral ID2 register 0x1FE8 32 read-only n 0x0 0x0 PERIPH_ID_2 PERIPH_ID_2 0 8 read-only AXIMC_PERIPH_ID_3 AXIMC_PERIPH_ID_3 AXIMC peripheral ID3 register 0x1FEC 32 read-only n 0x0 0x0 CUST_MOD_NUM CUST_MOD_NUM 0 4 read-only REV_AND REV_AND 4 4 read-only AXIMC_PERIPH_ID_4 AXIMC_PERIPH_ID_4 AXIMC peripheral ID4 register 0x1FD0 32 read-only n 0x0 0x0 JEP106CON JEP106CON 0 4 read-only K4COUNT K4COUNT 4 4 read-only AXIMC_PERIPH_ID_5 AXIMC_PERIPH_ID_5 AXIMC peripheral ID5 register 0x1FD4 32 read-only n 0x0 0x0 PERIPH_ID_5 PERIPH_ID_5 0 8 read-only AXIMC_PERIPH_ID_6 AXIMC_PERIPH_ID_6 AXIMC peripheral ID6 register 0x1FD8 32 read-only n 0x0 0x0 PERIPH_ID_6 PERIPH_ID_6 0 8 read-only AXIMC_PERIPH_ID_7 AXIMC_PERIPH_ID_7 AXIMC peripheral ID7 register 0x1FDC 32 read-only n 0x0 0x0 PERIPH_ID_7 PERIPH_ID_7 0 8 read-only BSEC BSEC2 BSEC2 0x0 0x0 0x1000 registers n DENABLE BSEC_DENABLE reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181. 0x14 32 read-write n 0x0 0x0 CFGSDISABLE CFGSDISABLE 9 1 CP15SDISABLE CP15SDISABLE 7 2 DBGEN DBGEN 1 1 DBGSWENABLE DBGSWENABLE 10 1 DEVICEEN DEVICEEN 3 1 DFTEN DFTEN 0 1 HDPEN HDPEN 4 1 NIDEN NIDEN 2 1 SPIDEN SPIDEN 5 1 SPNIDEN SPNIDEN 6 1 HWCFGR BSEC_HWCFGR BSEC hardware configuration register 0xFF0 32 read-only n 0x0 0x0 ECC_USE ECC_USE 4 4 SIZE SIZE 0 4 IPIDR BSEC_IPIDR BSEC identification register 0xFF8 32 read-only n 0x0 0x0 ID ID 0 32 JTAGIN BSEC_JTAGIN BSEC JTAG input register 0xAC 32 read-only n 0x0 0x0 DATA DATA 0 16 JTAGOUT BSEC_JTAGOUT BSEC JTAG output register 0xB0 32 read-write n 0x0 0x0 DATA DATA 0 16 OTP_CONFIG BSEC_OTP_CONFIG BSEC OTP configuration register 0x0 32 read-write n 0x0 0x0 FRC FRC 1 2 PRGWIDTH PRGWIDTH 3 4 PWRUP PWRUP 0 1 TREAD TREAD 7 2 OTP_CONTROL BSEC_OTP_CONTROL BSEC OTP control register 0x4 32 read-write n 0x0 0x0 ADDR ADDR 0 7 LOCK LOCK 9 1 PROG PROG 8 1 OTP_DATA0 BSEC_OTP_DATA0 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x200 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA1 BSEC_OTP_DATA1 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x204 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA10 BSEC_OTP_DATA10 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x228 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA11 BSEC_OTP_DATA11 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x22C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA12 BSEC_OTP_DATA12 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x230 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA13 BSEC_OTP_DATA13 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x234 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA14 BSEC_OTP_DATA14 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x238 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA15 BSEC_OTP_DATA15 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x23C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA16 BSEC_OTP_DATA16 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x240 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA17 BSEC_OTP_DATA17 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x244 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA18 BSEC_OTP_DATA18 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x248 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA19 BSEC_OTP_DATA19 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x24C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA2 BSEC_OTP_DATA2 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x208 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA20 BSEC_OTP_DATA20 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x250 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA21 BSEC_OTP_DATA21 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x254 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA22 BSEC_OTP_DATA22 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x258 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA23 BSEC_OTP_DATA23 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x25C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA24 BSEC_OTP_DATA24 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x260 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA25 BSEC_OTP_DATA25 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x264 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA26 BSEC_OTP_DATA26 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x268 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA27 BSEC_OTP_DATA27 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x26C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA28 BSEC_OTP_DATA28 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x270 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA29 BSEC_OTP_DATA29 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x274 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA3 BSEC_OTP_DATA3 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x20C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA30 BSEC_OTP_DATA30 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x278 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA31 BSEC_OTP_DATA31 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x27C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA32 BSEC_OTP_DATA32 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x280 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA33 BSEC_OTP_DATA33 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x284 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA34 BSEC_OTP_DATA34 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x288 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA35 BSEC_OTP_DATA35 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x28C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA36 BSEC_OTP_DATA36 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x290 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA37 BSEC_OTP_DATA37 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x294 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA38 BSEC_OTP_DATA38 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x298 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA39 BSEC_OTP_DATA39 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x29C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA4 BSEC_OTP_DATA4 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x210 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA40 BSEC_OTP_DATA40 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA41 BSEC_OTP_DATA41 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA42 BSEC_OTP_DATA42 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA43 BSEC_OTP_DATA43 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2AC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA44 BSEC_OTP_DATA44 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA45 BSEC_OTP_DATA45 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA46 BSEC_OTP_DATA46 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA47 BSEC_OTP_DATA47 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2BC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA48 BSEC_OTP_DATA48 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA49 BSEC_OTP_DATA49 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA5 BSEC_OTP_DATA5 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x214 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA50 BSEC_OTP_DATA50 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA51 BSEC_OTP_DATA51 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2CC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA52 BSEC_OTP_DATA52 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA53 BSEC_OTP_DATA53 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA54 BSEC_OTP_DATA54 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA55 BSEC_OTP_DATA55 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2DC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA56 BSEC_OTP_DATA56 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA57 BSEC_OTP_DATA57 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA58 BSEC_OTP_DATA58 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA59 BSEC_OTP_DATA59 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2EC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA6 BSEC_OTP_DATA6 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x218 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA60 BSEC_OTP_DATA60 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F0 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA61 BSEC_OTP_DATA61 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F4 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA62 BSEC_OTP_DATA62 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F8 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA63 BSEC_OTP_DATA63 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2FC 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA64 BSEC_OTP_DATA64 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x300 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA65 BSEC_OTP_DATA65 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x304 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA66 BSEC_OTP_DATA66 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x308 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA67 BSEC_OTP_DATA67 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x30C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA68 BSEC_OTP_DATA68 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x310 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA69 BSEC_OTP_DATA69 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x314 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA7 BSEC_OTP_DATA7 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x21C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA70 BSEC_OTP_DATA70 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x318 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA71 BSEC_OTP_DATA71 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x31C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA72 BSEC_OTP_DATA72 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x320 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA73 BSEC_OTP_DATA73 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x324 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA74 BSEC_OTP_DATA74 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x328 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA75 BSEC_OTP_DATA75 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x32C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA76 BSEC_OTP_DATA76 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x330 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA77 BSEC_OTP_DATA77 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x334 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA78 BSEC_OTP_DATA78 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x338 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA79 BSEC_OTP_DATA79 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x33C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA8 BSEC_OTP_DATA8 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x220 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA80 BSEC_OTP_DATA80 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x340 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA81 BSEC_OTP_DATA81 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x344 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA82 BSEC_OTP_DATA82 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x348 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA83 BSEC_OTP_DATA83 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x34C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA84 BSEC_OTP_DATA84 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x350 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA85 BSEC_OTP_DATA85 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x354 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA86 BSEC_OTP_DATA86 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x358 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA87 BSEC_OTP_DATA87 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x35C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA88 BSEC_OTP_DATA88 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x360 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA89 BSEC_OTP_DATA89 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x364 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA9 BSEC_OTP_DATA9 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x224 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA90 BSEC_OTP_DATA90 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x368 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA91 BSEC_OTP_DATA91 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x36C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA92 BSEC_OTP_DATA92 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x370 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA93 BSEC_OTP_DATA93 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x374 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA94 BSEC_OTP_DATA94 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x378 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DATA95 BSEC_OTP_DATA95 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x37C 32 read-write n 0x0 0x0 DATA DATA 0 32 OTP_DISTURBED0 BSEC_OTP_DISTURBED0 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x1C 32 read-only n 0x0 0x0 DIS DIS 0 32 OTP_DISTURBED1 BSEC_OTP_DISTURBED1 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x20 32 read-only n 0x0 0x0 DIS DIS 0 32 OTP_DISTURBED2 BSEC_OTP_DISTURBED2 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x24 32 read-only n 0x0 0x0 DIS DIS 0 32 OTP_ERROR0 BSEC_OTP_ERROR0 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x34 32 read-only n 0x0 0x0 ERR ERR 0 32 OTP_ERROR1 BSEC_OTP_ERROR1 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x38 32 read-only n 0x0 0x0 ERR ERR 0 32 OTP_ERROR2 BSEC_OTP_ERROR2 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x3C 32 read-only n 0x0 0x0 ERR ERR 0 32 OTP_LOCK BSEC_OTP_LOCK BSEC OTP lock configuration register 0x10 32 read-write n 0x0 0x0 DENREG DENREG 2 1 GPLOCK GPLOCK 4 1 OTP OTP 0 1 ROMLOCK ROMLOCK 1 1 OTP_SPLOCK0 BSEC_OTP_SPLOCK0 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x64 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 OTP_SPLOCK1 BSEC_OTP_SPLOCK1 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x68 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 OTP_SPLOCK2 BSEC_OTP_SPLOCK2 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x6C 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 OTP_SRLOCK0 BSEC_OTP_SRLOCK0 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x94 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 OTP_SRLOCK1 BSEC_OTP_SRLOCK1 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x98 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 OTP_SRLOCK2 BSEC_OTP_SRLOCK2 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x9C 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 OTP_STATUS BSEC_OTP_STATUS BSEC OTP status register 0xC 32 read-only n 0x0 0x0 BIST1LOCK BIST1LOCK 6 1 BIST2LOCK BIST2LOCK 7 1 BUSY BUSY 3 1 FULLDBG FULLDBG 1 1 INVALID INVALID 2 1 PROGFAIL PROGFAIL 4 1 PWRON PWRON 5 1 SECURE SECURE 0 1 OTP_SWLOCK0 BSEC_OTP_SWLOCK0 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x7C 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 OTP_SWLOCK1 BSEC_OTP_SWLOCK1 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x80 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 OTP_SWLOCK2 BSEC_OTP_SWLOCK2 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x84 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 OTP_WRDATA BSEC_OTP_WRDATA BSEC OTP write data register 0x8 32 read-write n 0x0 0x0 WRDATA WRDATA 0 32 OTP_WRLOCK0 BSEC_OTP_WRLOCK0 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x4C 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 OTP_WRLOCK1 BSEC_OTP_WRLOCK1 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x50 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 OTP_WRLOCK2 BSEC_OTP_WRLOCK2 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178). 0x54 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 SCRATCH BSEC_SCRATCH BSEC scratch register 0xB4 32 read-write n 0x0 0x0 DATA DATA 0 32 SIDR BSEC_SIDR BSEC size identification register 0xFFC 32 read-only n 0x0 0x0 SID SID 0 32 VERR BSEC_VERR BSEC version register 0xFF4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 CCU CCU CCU 0x0 0x0 0x400 registers n FCCAN_CCU_CCFG FCCAN_CCU_CCFG Calibration configuration register 0x4 32 read-write n 0x0 0x0 BCC BCC 6 1 CDIV CDIV 16 4 CFL CFL 7 1 OCPM OCPM 8 8 SWR SWR 31 1 TQBT TQBT 0 5 FCCAN_CCU_CREL FCCAN_CCU_CREL Clock calibration unit core release register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 FCCAN_CCU_CSTAT FCCAN_CCU_CSTAT Calibration status register 0x8 32 read-only n 0x0 0x0 CALS CALS 30 2 OCPC OCPC 0 18 TQC TQC 18 11 FCCAN_CCU_CWD FCCAN_CCU_CWD The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset. 0xC 32 read-write n 0x0 0x0 WDC WDC 0 16 read-write WDV WDV 16 16 read-only FCCAN_CCU_IE FCCAN_CCU_IE The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line. 0x14 32 read-write n 0x0 0x0 CSCE CSCE 1 1 CWEE CWEE 0 1 FCCAN_CCU_IR FCCAN_CCU_IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not. 0x10 32 read-write n 0x0 0x0 CSC CSC 1 1 CWE CWE 0 1 CRC1 CRC1 CRC1 0x0 0x0 0x1000 registers n CRC_CR CRC_CR CRC control register 0x8 32 read-write n 0x0 0x0 POLYSIZE POLYSIZE 3 2 RESET RESET 0 1 REV_IN REV_IN 5 2 REV_OUT REV_OUT 7 1 CRC_DR CRC_DR CRC data register 0x0 32 read-write n 0x0 0x0 DR DR 0 32 CRC_IDR CRC_IDR CRC independent data register 0x4 32 read-write n 0x0 0x0 IDR IDR 0 32 CRC_INIT CRC_INIT CRC initial value 0x10 32 read-write n 0x0 0x0 CRC_INIT CRC_INIT 0 32 CRC_POL CRC_POL CRC polynomial 0x14 32 read-write n 0x0 0x0 POL POL 0 32 CRC2 CRC1 CRC1 0x0 0x0 0x1000 registers n CRC_CR CRC_CR CRC control register 0x8 32 read-write n 0x0 0x0 POLYSIZE POLYSIZE 3 2 RESET RESET 0 1 REV_IN REV_IN 5 2 REV_OUT REV_OUT 7 1 CRC_DR CRC_DR CRC data register 0x0 32 read-write n 0x0 0x0 DR DR 0 32 CRC_IDR CRC_IDR CRC independent data register 0x4 32 read-write n 0x0 0x0 IDR IDR 0 32 CRC_INIT CRC_INIT CRC initial value 0x10 32 read-write n 0x0 0x0 CRC_INIT CRC_INIT 0 32 CRC_POL CRC_POL CRC polynomial 0x14 32 read-write n 0x0 0x0 POL POL 0 32 CRYP1 CRYP1 CRYP1 0x0 0x0 0x400 registers n CRYP_CR CRYP_CR CRYP control register 0x0 32 read-write n 0x0 0x0 ALGODIR ALGODIR 2 1 read-write ALGOMODE ALGOMODE 3 3 read-write ALGOMODE3 ALGOMODE3 19 1 read-write CRYPEN CRYPEN 15 1 read-write DATATYPE DATATYPE 6 2 read-write FFLUSH FFLUSH 14 1 write-only GCM_CCMPH GCM_CCMPH 16 2 read-write KEYSIZE KEYSIZE 8 2 read-write NPBLB NPBLB 20 4 read-write CRYP_CSGCM0R CRYP_CSGCM0R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x70 32 read-write n 0x0 0x0 CSGCM0 CSGCM0 0 32 CRYP_CSGCM1R CRYP_CSGCM1R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x74 32 read-write n 0x0 0x0 CSGCM1 CSGCM1 0 32 CRYP_CSGCM2R CRYP_CSGCM2R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x78 32 read-write n 0x0 0x0 CSGCM2 CSGCM2 0 32 CRYP_CSGCM3R CRYP_CSGCM3R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x7C 32 read-write n 0x0 0x0 CSGCM3 CSGCM3 0 32 CRYP_CSGCM4R CRYP_CSGCM4R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x80 32 read-write n 0x0 0x0 CSGCM4 CSGCM4 0 32 CRYP_CSGCM5R CRYP_CSGCM5R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x84 32 read-write n 0x0 0x0 CSGCM5 CSGCM5 0 32 CRYP_CSGCM6R CRYP_CSGCM6R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x88 32 read-write n 0x0 0x0 CSGCM6 CSGCM6 0 32 CRYP_CSGCM7R CRYP_CSGCM7R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x8C 32 read-write n 0x0 0x0 CSGCM7 CSGCM7 0 32 CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x50 32 read-write n 0x0 0x0 CSGCMCCM0 CSGCMCCM0 0 32 CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x54 32 read-write n 0x0 0x0 CSGCMCCM1 CSGCMCCM1 0 32 CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x58 32 read-write n 0x0 0x0 CSGCMCCM2 CSGCMCCM2 0 32 CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x5C 32 read-write n 0x0 0x0 CSGCMCCM3 CSGCMCCM3 0 32 CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x60 32 read-write n 0x0 0x0 CSGCMCCM4 CSGCMCCM4 0 32 CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x64 32 read-write n 0x0 0x0 CSGCMCCM5 CSGCMCCM5 0 32 CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x68 32 read-write n 0x0 0x0 CSGCMCCM6 CSGCMCCM6 0 32 CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x6C 32 read-write n 0x0 0x0 CSGCMCCM7 CSGCMCCM7 0 32 CRYP_DIN CRYP_DIN The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 0x8 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 CRYP_DMACR CRYP_DMACR CRYP DMA control register 0x10 32 read-write n 0x0 0x0 DIEN DIEN 0 1 DOEN DOEN 1 1 CRYP_DOUT CRYP_DOUT The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 0xC 32 read-only n 0x0 0x0 DATAOUT DATAOUT 0 32 CRYP_HWCFGR CRYP_HWCFGR CRYP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CRYP_IMSCR CRYP_IMSCR The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 0x14 32 read-write n 0x0 0x0 INIM INIM 0 1 OUTIM OUTIM 1 1 CRYP_IPIDR CRYP_IPIDR CRYP Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 CRYP_IV0LR CRYP_IV0LR The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 0x40 32 read-write n 0x0 0x0 IV0 IV0 31 1 IV1 IV1 30 1 IV10 IV10 21 1 IV11 IV11 20 1 IV12 IV12 19 1 IV13 IV13 18 1 IV14 IV14 17 1 IV15 IV15 16 1 IV16 IV16 15 1 IV17 IV17 14 1 IV18 IV18 13 1 IV19 IV19 12 1 IV2 IV2 29 1 IV20 IV20 11 1 IV21 IV21 10 1 IV22 IV22 9 1 IV23 IV23 8 1 IV24 IV24 7 1 IV25 IV25 6 1 IV26 IV26 5 1 IV27 IV27 4 1 IV28 IV28 3 1 IV29 IV29 2 1 IV3 IV3 28 1 IV30 IV30 1 1 IV31 IV31 0 1 IV4 IV4 27 1 IV5 IV5 26 1 IV6 IV6 25 1 IV7 IV7 24 1 IV8 IV8 23 1 IV9 IV9 22 1 CRYP_IV0RR CRYP_IV0RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x44 32 read-write n 0x0 0x0 IV32 IV32 31 1 IV33 IV33 30 1 IV34 IV34 29 1 IV35 IV35 28 1 IV36 IV36 27 1 IV37 IV37 26 1 IV38 IV38 25 1 IV39 IV39 24 1 IV40 IV40 23 1 IV41 IV41 22 1 IV42 IV42 21 1 IV43 IV43 20 1 IV44 IV44 19 1 IV45 IV45 18 1 IV46 IV46 17 1 IV47 IV47 16 1 IV48 IV48 15 1 IV49 IV49 14 1 IV50 IV50 13 1 IV51 IV51 12 1 IV52 IV52 11 1 IV53 IV53 10 1 IV54 IV54 9 1 IV55 IV55 8 1 IV56 IV56 7 1 IV57 IV57 6 1 IV58 IV58 5 1 IV59 IV59 4 1 IV60 IV60 3 1 IV61 IV61 2 1 IV62 IV62 1 1 IV63 IV63 0 1 CRYP_IV1LR CRYP_IV1LR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x48 32 read-write n 0x0 0x0 IV64 IV64 31 1 IV65 IV65 30 1 IV66 IV66 29 1 IV67 IV67 28 1 IV68 IV68 27 1 IV69 IV69 26 1 IV70 IV70 25 1 IV71 IV71 24 1 IV72 IV72 23 1 IV73 IV73 22 1 IV74 IV74 21 1 IV75 IV75 20 1 IV76 IV76 19 1 IV77 IV77 18 1 IV78 IV78 17 1 IV79 IV79 16 1 IV80 IV80 15 1 IV81 IV81 14 1 IV82 IV82 13 1 IV83 IV83 12 1 IV84 IV84 11 1 IV85 IV85 10 1 IV86 IV86 9 1 IV87 IV87 8 1 IV88 IV88 7 1 IV89 IV89 6 1 IV90 IV90 5 1 IV91 IV91 4 1 IV92 IV92 3 1 IV93 IV93 2 1 IV94 IV94 1 1 IV95 IV95 0 1 CRYP_IV1RR CRYP_IV1RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x4C 32 read-write n 0x0 0x0 IV100 IV100 27 1 IV101 IV101 26 1 IV102 IV102 25 1 IV103 IV103 24 1 IV104 IV104 23 1 IV105 IV105 22 1 IV106 IV106 21 1 IV107 IV107 20 1 IV108 IV108 19 1 IV109 IV109 18 1 IV110 IV110 17 1 IV111 IV111 16 1 IV112 IV112 15 1 IV113 IV113 14 1 IV114 IV114 13 1 IV115 IV115 12 1 IV116 IV116 11 1 IV117 IV117 10 1 IV118 IV118 9 1 IV119 IV119 8 1 IV120 IV120 7 1 IV121 IV121 6 1 IV122 IV122 5 1 IV123 IV123 4 1 IV124 IV124 3 1 IV125 IV125 2 1 IV126 IV126 1 1 IV127 IV127 0 1 IV96 IV96 31 1 IV97 IV97 30 1 IV98 IV98 29 1 IV99 IV99 28 1 CRYP_K0LR CRYP_K0LR CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 0x20 32 write-only n 0x0 0x0 K K 0 32 CRYP_K0RR CRYP_K0RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x24 32 write-only n 0x0 0x0 K K 0 32 CRYP_K1LR CRYP_K1LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x28 32 write-only n 0x0 0x0 K K 0 32 CRYP_K1RR CRYP_K1RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x2C 32 write-only n 0x0 0x0 K K 0 32 CRYP_K2LR CRYP_K2LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x30 32 write-only n 0x0 0x0 K K 0 32 CRYP_K2RR CRYP_K2RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x34 32 write-only n 0x0 0x0 K K 0 32 CRYP_K3LR CRYP_K3LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x38 32 write-only n 0x0 0x0 K K 0 32 CRYP_K3RR CRYP_K3RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x3C 32 write-only n 0x0 0x0 K K 0 32 CRYP_MID CRYP_MID CRYP HW Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 CRYP_MISR CRYP_MISR The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 0x1C 32 read-only n 0x0 0x0 INMIS INMIS 0 1 OUTMIS OUTMIS 1 1 CRYP_RISR CRYP_RISR The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 0x18 32 read-only n 0x0 0x0 INRIS INRIS 0 1 OUTRIS OUTRIS 1 1 CRYP_SR CRYP_SR CRYP status register 0x4 32 read-only n 0x0 0x0 BUSY BUSY 4 1 IFEM IFEM 0 1 IFNF IFNF 1 1 OFFU OFFU 3 1 OFNE OFNE 2 1 CRYP_VERR CRYP_VERR CRYP HW Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 CRYP2 CRYP1 CRYP1 0x0 0x0 0x400 registers n CRYP_CR CRYP_CR CRYP control register 0x0 32 read-write n 0x0 0x0 ALGODIR ALGODIR 2 1 read-write ALGOMODE ALGOMODE 3 3 read-write ALGOMODE3 ALGOMODE3 19 1 read-write CRYPEN CRYPEN 15 1 read-write DATATYPE DATATYPE 6 2 read-write FFLUSH FFLUSH 14 1 write-only GCM_CCMPH GCM_CCMPH 16 2 read-write KEYSIZE KEYSIZE 8 2 read-write NPBLB NPBLB 20 4 read-write CRYP_CSGCM0R CRYP_CSGCM0R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x70 32 read-write n 0x0 0x0 CSGCM0 CSGCM0 0 32 CRYP_CSGCM1R CRYP_CSGCM1R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x74 32 read-write n 0x0 0x0 CSGCM1 CSGCM1 0 32 CRYP_CSGCM2R CRYP_CSGCM2R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x78 32 read-write n 0x0 0x0 CSGCM2 CSGCM2 0 32 CRYP_CSGCM3R CRYP_CSGCM3R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x7C 32 read-write n 0x0 0x0 CSGCM3 CSGCM3 0 32 CRYP_CSGCM4R CRYP_CSGCM4R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x80 32 read-write n 0x0 0x0 CSGCM4 CSGCM4 0 32 CRYP_CSGCM5R CRYP_CSGCM5R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x84 32 read-write n 0x0 0x0 CSGCM5 CSGCM5 0 32 CRYP_CSGCM6R CRYP_CSGCM6R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x88 32 read-write n 0x0 0x0 CSGCM6 CSGCM6 0 32 CRYP_CSGCM7R CRYP_CSGCM7R Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x8C 32 read-write n 0x0 0x0 CSGCM7 CSGCM7 0 32 CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x50 32 read-write n 0x0 0x0 CSGCMCCM0 CSGCMCCM0 0 32 CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x54 32 read-write n 0x0 0x0 CSGCMCCM1 CSGCMCCM1 0 32 CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x58 32 read-write n 0x0 0x0 CSGCMCCM2 CSGCMCCM2 0 32 CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x5C 32 read-write n 0x0 0x0 CSGCMCCM3 CSGCMCCM3 0 32 CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x60 32 read-write n 0x0 0x0 CSGCMCCM4 CSGCMCCM4 0 32 CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x64 32 read-write n 0x0 0x0 CSGCMCCM5 CSGCMCCM5 0 32 CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x68 32 read-write n 0x0 0x0 CSGCMCCM6 CSGCMCCM6 0 32 CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x6C 32 read-write n 0x0 0x0 CSGCMCCM7 CSGCMCCM7 0 32 CRYP_DIN CRYP_DIN The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 0x8 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 CRYP_DMACR CRYP_DMACR CRYP DMA control register 0x10 32 read-write n 0x0 0x0 DIEN DIEN 0 1 DOEN DOEN 1 1 CRYP_DOUT CRYP_DOUT The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 0xC 32 read-only n 0x0 0x0 DATAOUT DATAOUT 0 32 CRYP_HWCFGR CRYP_HWCFGR CRYP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CRYP_IMSCR CRYP_IMSCR The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 0x14 32 read-write n 0x0 0x0 INIM INIM 0 1 OUTIM OUTIM 1 1 CRYP_IPIDR CRYP_IPIDR CRYP Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 CRYP_IV0LR CRYP_IV0LR The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 0x40 32 read-write n 0x0 0x0 IV0 IV0 31 1 IV1 IV1 30 1 IV10 IV10 21 1 IV11 IV11 20 1 IV12 IV12 19 1 IV13 IV13 18 1 IV14 IV14 17 1 IV15 IV15 16 1 IV16 IV16 15 1 IV17 IV17 14 1 IV18 IV18 13 1 IV19 IV19 12 1 IV2 IV2 29 1 IV20 IV20 11 1 IV21 IV21 10 1 IV22 IV22 9 1 IV23 IV23 8 1 IV24 IV24 7 1 IV25 IV25 6 1 IV26 IV26 5 1 IV27 IV27 4 1 IV28 IV28 3 1 IV29 IV29 2 1 IV3 IV3 28 1 IV30 IV30 1 1 IV31 IV31 0 1 IV4 IV4 27 1 IV5 IV5 26 1 IV6 IV6 25 1 IV7 IV7 24 1 IV8 IV8 23 1 IV9 IV9 22 1 CRYP_IV0RR CRYP_IV0RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x44 32 read-write n 0x0 0x0 IV32 IV32 31 1 IV33 IV33 30 1 IV34 IV34 29 1 IV35 IV35 28 1 IV36 IV36 27 1 IV37 IV37 26 1 IV38 IV38 25 1 IV39 IV39 24 1 IV40 IV40 23 1 IV41 IV41 22 1 IV42 IV42 21 1 IV43 IV43 20 1 IV44 IV44 19 1 IV45 IV45 18 1 IV46 IV46 17 1 IV47 IV47 16 1 IV48 IV48 15 1 IV49 IV49 14 1 IV50 IV50 13 1 IV51 IV51 12 1 IV52 IV52 11 1 IV53 IV53 10 1 IV54 IV54 9 1 IV55 IV55 8 1 IV56 IV56 7 1 IV57 IV57 6 1 IV58 IV58 5 1 IV59 IV59 4 1 IV60 IV60 3 1 IV61 IV61 2 1 IV62 IV62 1 1 IV63 IV63 0 1 CRYP_IV1LR CRYP_IV1LR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x48 32 read-write n 0x0 0x0 IV64 IV64 31 1 IV65 IV65 30 1 IV66 IV66 29 1 IV67 IV67 28 1 IV68 IV68 27 1 IV69 IV69 26 1 IV70 IV70 25 1 IV71 IV71 24 1 IV72 IV72 23 1 IV73 IV73 22 1 IV74 IV74 21 1 IV75 IV75 20 1 IV76 IV76 19 1 IV77 IV77 18 1 IV78 IV78 17 1 IV79 IV79 16 1 IV80 IV80 15 1 IV81 IV81 14 1 IV82 IV82 13 1 IV83 IV83 12 1 IV84 IV84 11 1 IV85 IV85 10 1 IV86 IV86 9 1 IV87 IV87 8 1 IV88 IV88 7 1 IV89 IV89 6 1 IV90 IV90 5 1 IV91 IV91 4 1 IV92 IV92 3 1 IV93 IV93 2 1 IV94 IV94 1 1 IV95 IV95 0 1 CRYP_IV1RR CRYP_IV1RR Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x4C 32 read-write n 0x0 0x0 IV100 IV100 27 1 IV101 IV101 26 1 IV102 IV102 25 1 IV103 IV103 24 1 IV104 IV104 23 1 IV105 IV105 22 1 IV106 IV106 21 1 IV107 IV107 20 1 IV108 IV108 19 1 IV109 IV109 18 1 IV110 IV110 17 1 IV111 IV111 16 1 IV112 IV112 15 1 IV113 IV113 14 1 IV114 IV114 13 1 IV115 IV115 12 1 IV116 IV116 11 1 IV117 IV117 10 1 IV118 IV118 9 1 IV119 IV119 8 1 IV120 IV120 7 1 IV121 IV121 6 1 IV122 IV122 5 1 IV123 IV123 4 1 IV124 IV124 3 1 IV125 IV125 2 1 IV126 IV126 1 1 IV127 IV127 0 1 IV96 IV96 31 1 IV97 IV97 30 1 IV98 IV98 29 1 IV99 IV99 28 1 CRYP_K0LR CRYP_K0LR CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 0x20 32 write-only n 0x0 0x0 K K 0 32 CRYP_K0RR CRYP_K0RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x24 32 write-only n 0x0 0x0 K K 0 32 CRYP_K1LR CRYP_K1LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x28 32 write-only n 0x0 0x0 K K 0 32 CRYP_K1RR CRYP_K1RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x2C 32 write-only n 0x0 0x0 K K 0 32 CRYP_K2LR CRYP_K2LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x30 32 write-only n 0x0 0x0 K K 0 32 CRYP_K2RR CRYP_K2RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x34 32 write-only n 0x0 0x0 K K 0 32 CRYP_K3LR CRYP_K3LR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x38 32 write-only n 0x0 0x0 K K 0 32 CRYP_K3RR CRYP_K3RR Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x3C 32 write-only n 0x0 0x0 K K 0 32 CRYP_MID CRYP_MID CRYP HW Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 CRYP_MISR CRYP_MISR The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 0x1C 32 read-only n 0x0 0x0 INMIS INMIS 0 1 OUTMIS OUTMIS 1 1 CRYP_RISR CRYP_RISR The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 0x18 32 read-only n 0x0 0x0 INRIS INRIS 0 1 OUTRIS OUTRIS 1 1 CRYP_SR CRYP_SR CRYP status register 0x4 32 read-only n 0x0 0x0 BUSY BUSY 4 1 IFEM IFEM 0 1 IFNF IFNF 1 1 OFFU OFFU 3 1 OFNE OFNE 2 1 CRYP_VERR CRYP_VERR CRYP HW Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 DAC1 DAC1 DAC1 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 OTRIM1 0 5 OTRIM2 OTRIM2 16 5 DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 CEN1 14 1 CEN2 CEN2 30 1 DMAEN1 DMAEN1 12 1 DMAEN2 DMAEN2 28 1 DMAUDRIE1 DMAUDRIE1 13 1 DMAUDRIE2 DMAUDRIE2 29 1 EN1 EN1 0 1 EN2 EN2 16 1 HFSEL HFSEL 15 1 MAMP1 MAMP1 8 4 MAMP2 MAMP2 24 4 TEN1 TEN1 1 1 TEN2 TEN2 17 1 TSEL10 TSEL10 2 1 TSEL11 TSEL11 3 1 TSEL12 TSEL12 4 1 TSEL13 TSEL13 5 1 TSEL20 TSEL20 18 1 TSEL21 TSEL21 19 1 TSEL22 TSEL22 20 1 TSEL23 TSEL23 21 1 WAVE1 WAVE1 6 2 WAVE2 WAVE2 22 2 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 4 12 DAC_DHR12L2 DAC_DHR12L2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x18 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 4 12 DAC_DHR12LD DAC_DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 4 12 DACC2DHR DACC2DHR 20 12 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 12 DAC_DHR12R2 DAC_DHR12R2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x14 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 0 12 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 12 DACC2DHR DACC2DHR 16 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 8 DAC_DHR8R2 DAC_DHR8R2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x1C 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 0 8 DAC_DHR8RD DAC_DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 8 DACC2DHR DACC2DHR 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DACC1DOR 0 12 DAC_DOR2 DAC_DOR2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x30 32 read-only n 0x0 0x0 DACC2DOR DACC2DOR 0 12 DAC_HWCFGR0 DAC_HWCFGR0 DAC IP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 DUAL DUAL 0 4 LFSR LFSR 4 4 OR_CFG OR_CFG 16 8 SAMPLE SAMPLE 12 4 TRIANGLE TRIANGLE 8 4 DAC_IPIDR DAC_IPIDR No 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 MODE1 MODE1 0 3 MODE2 MODE2 16 3 DAC_SHHR DAC_SHHR DAC sample and hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 THOLD1 0 10 THOLD2 THOLD2 16 10 DAC_SHRR DAC_SHRR DAC sample and hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 TREFRESH1 0 8 TREFRESH2 TREFRESH2 16 8 DAC_SHSR1 DAC_SHSR1 DAC channel 1 sample and hold sample time register 0x40 32 read-write n 0x0 0x0 TSAMPLE1 TSAMPLE1 0 10 DAC_SHSR2 DAC_SHSR2 This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation. 0x44 32 read-write n 0x0 0x0 TSAMPLE2 TSAMPLE2 0 10 DAC_SIDR DAC_SIDR No 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 BWST1 15 1 read-only BWST2 BWST2 31 1 read-only CAL_FLAG1 CAL_FLAG1 14 1 read-only CAL_FLAG2 CAL_FLAG2 30 1 read-only DMAUDR1 DMAUDR1 13 1 read-write DMAUDR2 DMAUDR2 29 1 read-write DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 SWTRIG1 0 1 SWTRIG2 SWTRIG2 1 1 DAC_VERR DAC_VERR No 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DCMI DCMI DCMI 0x0 0x0 0x400 registers n CR DCMI_CR DCMI control register 0x0 32 read-write n 0x0 0x0 BSM BSM 16 2 CAPTURE CAPTURE 0 1 CM CM 1 1 CROP CROP 2 1 EDM EDM 10 2 ENABLE ENABLE 14 1 ESS ESS 4 1 FCRC FCRC 8 2 HSPOL HSPOL 6 1 JPEG JPEG 3 1 LSM LSM 19 1 OEBS OEBS 18 1 OELS OELS 20 1 PCKPOL PCKPOL 5 1 VSPOL VSPOL 7 1 CWSIZE DCMI_CWSIZE DCMI crop window size 0x24 32 read-write n 0x0 0x0 CAPCNT CAPCNT 0 14 VLINE VLINE 16 14 CWSTRT DCMI_CWSTRT DCMI crop window start 0x20 32 read-write n 0x0 0x0 HOFFCNT HOFFCNT 0 14 VST VST 16 13 DR DCMI_DR DCMI data register 0x28 32 read-only n 0x0 0x0 Byte0 Byte0 0 8 Byte1 Byte1 8 8 Byte2 Byte2 16 8 Byte3 Byte3 24 8 ESCR DCMI_ESCR DCMI embedded synchronization code register 0x18 32 read-write n 0x0 0x0 FEC FEC 24 8 FSC FSC 0 8 LEC LEC 16 8 LSC LSC 8 8 ESUR DCMI_ESUR DCMI embedded synchronization unmask register 0x1C 32 read-write n 0x0 0x0 FEU FEU 24 8 FSU FSU 0 8 LEU LEU 16 8 LSU LSU 8 8 ICR DCMI_ICR The DCMI_ICR register is write-only. 0x14 32 write-only n 0x0 0x0 ERR_ISC ERR_ISC 2 1 FRAME_ISC FRAME_ISC 0 1 LINE_ISC LINE_ISC 4 1 OVR_ISC OVR_ISC 1 1 VSYNC_ISC VSYNC_ISC 3 1 IER DCMI_IER The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. 0xC 32 read-write n 0x0 0x0 ERR_IE ERR_IE 2 1 FRAME_IE FRAME_IE 0 1 LINE_IE LINE_IE 4 1 OVR_IE OVR_IE 1 1 VSYNC_IE VSYNC_IE 3 1 MIS DCMI_MIS This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. 0x10 32 read-only n 0x0 0x0 ERR_MIS ERR_MIS 2 1 FRAME_MIS FRAME_MIS 0 1 LINE_MIS LINE_MIS 4 1 OVR_MIS OVR_MIS 1 1 VSYNC_MIS VSYNC_MIS 3 1 RIS DCMI_RIS DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. 0x8 32 read-only n 0x0 0x0 ERR_RIS ERR_RIS 2 1 FRAME_RIS FRAME_RIS 0 1 LINE_RIS LINE_RIS 4 1 OVR_RIS OVR_RIS 1 1 VSYNC_RIS VSYNC_RIS 3 1 SR DCMI_SR DCMI status register 0x4 32 read-only n 0x0 0x0 FNE FNE 2 1 HSYNC HSYNC 0 1 VSYNC VSYNC 1 1 DDRCTRL DDRCTRL DDRCTRL 0x0 0x0 0x1000 registers n ADDRMAP1 DDRCTRL_ADDRMAP1 DDRCTRL address map register 1 0x204 32 read-write n 0x0 0x0 ADDRMAP_BANK_B0 ADDRMAP_BANK_B0 0 6 ADDRMAP_BANK_B1 ADDRMAP_BANK_B1 8 6 ADDRMAP_BANK_B2 ADDRMAP_BANK_B2 16 6 ADDRMAP10 DDRCTRL_ADDRMAP10 DDRCTRL address map register 10 0x228 32 read-write n 0x0 0x0 ADDRMAP_ROW_B6 ADDRMAP_ROW_B6 0 4 ADDRMAP_ROW_B7 ADDRMAP_ROW_B7 8 4 ADDRMAP_ROW_B8 ADDRMAP_ROW_B8 16 4 ADDRMAP_ROW_B9 ADDRMAP_ROW_B9 24 4 ADDRMAP11 DDRCTRL_ADDRMAP11 DDRCTRL address map register 11 0x22C 32 read-write n 0x0 0x0 ADDRMAP_ROW_B10 ADDRMAP_ROW_B10 0 4 ADDRMAP2 DDRCTRL_ADDRMAP2 DDRCTRL address map register 2 0x208 32 read-write n 0x0 0x0 ADDRMAP_COL_B2 ADDRMAP_COL_B2 0 4 ADDRMAP_COL_B3 ADDRMAP_COL_B3 8 4 ADDRMAP_COL_B4 ADDRMAP_COL_B4 16 4 ADDRMAP_COL_B5 ADDRMAP_COL_B5 24 4 ADDRMAP3 DDRCTRL_ADDRMAP3 DDRCTRL address map register 3 0x20C 32 read-write n 0x0 0x0 ADDRMAP_COL_B6 ADDRMAP_COL_B6 0 4 ADDRMAP_COL_B7 ADDRMAP_COL_B7 8 5 ADDRMAP_COL_B8 ADDRMAP_COL_B8 16 5 ADDRMAP_COL_B9 ADDRMAP_COL_B9 24 5 ADDRMAP4 DDRCTRL_ADDRMAP4 DDRCTRL address map register 4 0x210 32 read-write n 0x0 0x0 ADDRMAP_COL_B10 ADDRMAP_COL_B10 0 5 ADDRMAP_COL_B11 ADDRMAP_COL_B11 8 5 ADDRMAP5 DDRCTRL_ADDRMAP5 DDRCTRL address map register 5 0x214 32 read-write n 0x0 0x0 ADDRMAP_ROW_B0 ADDRMAP_ROW_B0 0 4 ADDRMAP_ROW_B1 ADDRMAP_ROW_B1 8 4 ADDRMAP_ROW_B11 ADDRMAP_ROW_B11 24 4 ADDRMAP_ROW_B2_10 ADDRMAP_ROW_B2_10 16 4 ADDRMAP6 DDRCTRL_ADDRMAP6 DDRCTRL address register 6 0x218 32 read-write n 0x0 0x0 ADDRMAP_ROW_B12 ADDRMAP_ROW_B12 0 4 ADDRMAP_ROW_B13 ADDRMAP_ROW_B13 8 4 ADDRMAP_ROW_B14 ADDRMAP_ROW_B14 16 4 ADDRMAP_ROW_B15 ADDRMAP_ROW_B15 24 4 LPDDR3_6GB_12GB LPDDR3_6GB_12GB 31 1 ADDRMAP9 DDRCTRL_ADDRMAP9 DDRCTRL address map register 9 0x224 32 read-write n 0x0 0x0 ADDRMAP_ROW_B2 ADDRMAP_ROW_B2 0 4 ADDRMAP_ROW_B3 ADDRMAP_ROW_B3 8 4 ADDRMAP_ROW_B4 ADDRMAP_ROW_B4 16 4 ADDRMAP_ROW_B5 ADDRMAP_ROW_B5 24 4 CRCPARCTL0 DDRCTRL_CRCPARCTL0 DDRCTRL CRC parity control register 0 0xC0 32 read-write n 0x0 0x0 DFI_ALERT_ERR_CNT_CLR DFI_ALERT_ERR_CNT_CLR 2 1 DFI_ALERT_ERR_INT_CLR DFI_ALERT_ERR_INT_CLR 1 1 DFI_ALERT_ERR_INT_EN DFI_ALERT_ERR_INT_EN 0 1 CRCPARSTAT DDRCTRL_CRCPARSTAT DDRCTRL CRC parity status register 0xCC 32 read-only n 0x0 0x0 DFI_ALERT_ERR_CNT DFI_ALERT_ERR_CNT 0 16 DFI_ALERT_ERR_INT DFI_ALERT_ERR_INT 16 1 DBG0 DDRCTRL_DBG0 DDRCTRL debug register 0 0x300 32 read-write n 0x0 0x0 DIS_COLLISION_PAGE_OPT DIS_COLLISION_PAGE_OPT 4 1 DIS_WC DIS_WC 0 1 DBG1 DDRCTRL_DBG1 DDRCTRL debug register 1 0x304 32 read-write n 0x0 0x0 DIS_DQ DIS_DQ 0 1 DIS_HIF DIS_HIF 1 1 DBGCAM DDRCTRL_DBGCAM DDRCTRL CAM debug register 0x308 32 read-only n 0x0 0x0 DBG_HPR_Q_DEPTH DBG_HPR_Q_DEPTH 0 5 DBG_LPR_Q_DEPTH DBG_LPR_Q_DEPTH 8 5 DBG_RD_Q_EMPTY DBG_RD_Q_EMPTY 25 1 DBG_STALL DBG_STALL 24 1 DBG_WR_Q_EMPTY DBG_WR_Q_EMPTY 26 1 DBG_W_Q_DEPTH DBG_W_Q_DEPTH 16 5 RD_DATA_PIPELINE_EMPTY RD_DATA_PIPELINE_EMPTY 28 1 WR_DATA_PIPELINE_EMPTY WR_DATA_PIPELINE_EMPTY 29 1 DBGCMD DDRCTRL_DBGCMD DDRCTRL command debug register 0x30C 32 read-write n 0x0 0x0 CTRLUPD CTRLUPD 5 1 RANK0_REFRESH RANK0_REFRESH 0 1 ZQ_CALIB_SHORT ZQ_CALIB_SHORT 4 1 DBGSTAT DDRCTRL_DBGSTAT DDRCTRL status debug register 0x310 32 read-only n 0x0 0x0 CTRLUPD_BUSY CTRLUPD_BUSY 5 1 RANK0_REFRESH_BUSY RANK0_REFRESH_BUSY 0 1 ZQ_CALIB_SHORT_BUSY ZQ_CALIB_SHORT_BUSY 4 1 DERATEEN DDRCTRL_DERATEEN DDRCTRL temperature derate enable register 0x20 32 read-write n 0x0 0x0 DERATE_BYTE DERATE_BYTE 4 4 DERATE_ENABLE DERATE_ENABLE 0 1 DERATE_VALUE DERATE_VALUE 1 2 DERATEINT DDRCTRL_DERATEINT DDRCTRL temperature derate interval register 0x24 32 read-write n 0x0 0x0 MR4_READ_INTERVAL MR4_READ_INTERVAL 0 32 DFILPCFG0 DDRCTRL_DFILPCFG0 DDRCTRL low power configuration register 0 0x198 32 read-write n 0x0 0x0 DFI_LP_EN_DPD DFI_LP_EN_DPD 16 1 DFI_LP_EN_PD DFI_LP_EN_PD 0 1 DFI_LP_EN_SR DFI_LP_EN_SR 8 1 DFI_LP_WAKEUP_DPD DFI_LP_WAKEUP_DPD 20 4 DFI_LP_WAKEUP_PD DFI_LP_WAKEUP_PD 4 4 DFI_LP_WAKEUP_SR DFI_LP_WAKEUP_SR 12 4 DFI_TLP_RESP DFI_TLP_RESP 24 5 DFIMISC DDRCTRL_DFIMISC DDRCTRL DFI miscellaneous control register 0x1B0 32 read-write n 0x0 0x0 CTL_IDLE_EN CTL_IDLE_EN 4 1 DFI_FREQUENCY DFI_FREQUENCY 8 5 DFI_INIT_COMPLETE_EN DFI_INIT_COMPLETE_EN 0 1 DFI_INIT_START DFI_INIT_START 5 1 DFIPHYMSTR DDRCTRL_DFIPHYMSTR DDRCTRL DFI PHY master register 0x1C4 32 read-write n 0x0 0x0 DFI_PHYMSTR_EN DFI_PHYMSTR_EN 0 1 DFISTAT DDRCTRL_DFISTAT DDRCTRL DFI status register 0x1BC 32 read-only n 0x0 0x0 DFI_INIT_COMPLETE DFI_INIT_COMPLETE 0 1 DFI_LP_ACK DFI_LP_ACK 1 1 DFITMG0 DDRCTRL_DFITMG0 DDRCTRL DFI timing register 0 0x190 32 read-write n 0x0 0x0 DFI_TPHY_WRDATA DFI_TPHY_WRDATA 8 6 DFI_TPHY_WRLAT DFI_TPHY_WRLAT 0 6 DFI_T_CTRL_DELAY DFI_T_CTRL_DELAY 24 5 DFI_T_RDDATA_EN DFI_T_RDDATA_EN 16 7 DFITMG1 DDRCTRL_DFITMG1 DDRCTRL DFI timing register 1 0x194 32 read-write n 0x0 0x0 DFI_T_DRAM_CLK_DISABLE DFI_T_DRAM_CLK_DISABLE 8 5 DFI_T_DRAM_CLK_ENABLE DFI_T_DRAM_CLK_ENABLE 0 5 DFI_T_WRDATA_DELAY DFI_T_WRDATA_DELAY 16 5 DFIUPD0 DDRCTRL_DFIUPD0 DDRCTRL DFI update register 0 0x1A0 32 read-write n 0x0 0x0 CTRLUPD_PRE_SRX CTRLUPD_PRE_SRX 29 1 DFI_T_CTRLUP_MAX DFI_T_CTRLUP_MAX 16 10 DFI_T_CTRLUP_MIN DFI_T_CTRLUP_MIN 0 10 DIS_AUTO_CTRLUPD DIS_AUTO_CTRLUPD 31 1 DIS_AUTO_CTRLUPD_SRX DIS_AUTO_CTRLUPD_SRX 30 1 DFIUPD1 DDRCTRL_DFIUPD1 DDRCTRL DFI update register 1 0x1A4 32 read-write n 0x0 0x0 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0 8 DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DFI_T_CTRLUPD_INTERVAL_MIN_X1024 16 8 DFIUPD2 DDRCTRL_DFIUPD2 DDRCTRL DFI update register 2 0x1A8 32 read-write n 0x0 0x0 DFI_PHYUPD_EN DFI_PHYUPD_EN 31 1 DIMMCTL DDRCTRL_DIMMCTL DDRCTRL DIMM control register 0xF0 32 read-write n 0x0 0x0 DIMM_ADDR_MIRR_EN DIMM_ADDR_MIRR_EN 1 1 DIMM_STAGGER_CS_EN DIMM_STAGGER_CS_EN 0 1 DRAMTMG0 DDRCTRL_DRAMTMG0 DDRCTRL SDRAM timing register 0 0x100 32 read-write n 0x0 0x0 T_FAW T_FAW 16 6 T_RAS_MAX T_RAS_MAX 8 7 T_RAS_MIN T_RAS_MIN 0 6 WR2PRE WR2PRE 24 7 DRAMTMG1 DDRCTRL_DRAMTMG1 DDRCTRL SDRAM timing register 1 0x104 32 read-write n 0x0 0x0 RD2PRE RD2PRE 8 6 T_RC T_RC 0 7 T_XP T_XP 16 5 DRAMTMG14 DDRCTRL_DRAMTMG14 DDRCTRL SDRAM timing register 14 0x138 32 read-write n 0x0 0x0 T_XSR T_XSR 0 12 DRAMTMG15 DDRCTRL_DRAMTMG15 DDRCTRL SDRAM timing register 15 0x13C 32 read-write n 0x0 0x0 EN_DFI_LP_T_STAB EN_DFI_LP_T_STAB 31 1 T_STAB_X32 T_STAB_X32 0 8 DRAMTMG2 DDRCTRL_DRAMTMG2 DDRCTRL SDRAM timing register 2 0x108 32 read-write n 0x0 0x0 RD2WR RD2WR 8 6 READ_LATENCY READ_LATENCY 16 6 WR2RD WR2RD 0 6 WRITE_LATENCY WRITE_LATENCY 24 6 DRAMTMG3 DDRCTRL_DRAMTMG3 DDRCTRL SDRAM timing register 3 0x10C 32 read-write n 0x0 0x0 T_MOD T_MOD 0 10 T_MRD T_MRD 12 6 T_MRW T_MRW 20 10 DRAMTMG4 DDRCTRL_DRAMTMG4 DDRCTRL SDRAM timing register 4 0x110 32 read-write n 0x0 0x0 T_CCD T_CCD 16 4 T_RCD T_RCD 24 5 T_RP T_RP 0 5 T_RRD T_RRD 8 4 DRAMTMG5 DDRCTRL_DRAMTMG5 DDRCTRL SDRAM timing register 5 0x114 32 read-write n 0x0 0x0 T_CKE T_CKE 0 5 T_CKESR T_CKESR 8 6 T_CKSRE T_CKSRE 16 4 T_CKSRX T_CKSRX 24 4 DRAMTMG6 DDRCTRL_DRAMTMG6 DDRCTRL SDRAM timing register 6 0x118 32 read-write n 0x0 0x0 T_CKCSX T_CKCSX 0 4 T_CKDPDE T_CKDPDE 24 4 T_CKDPDX T_CKDPDX 16 4 DRAMTMG7 DDRCTRL_DRAMTMG7 DDRCTRL SDRAM timing register 7 0x11C 32 read-write n 0x0 0x0 T_CKPDE T_CKPDE 8 4 T_CKPDX T_CKPDX 0 4 DRAMTMG8 DDRCTRL_DRAMTMG8 DDRCTRL SDRAM timing register 8 0x120 32 read-write n 0x0 0x0 T_XS_DLL_X32 T_XS_DLL_X32 8 7 T_XS_X32 T_XS_X32 0 7 HWLPCTL DDRCTRL_HWLPCTL DDRCTRL hardware low power control register 0x38 32 read-write n 0x0 0x0 HW_LP_EN HW_LP_EN 0 1 HW_LP_EXIT_IDLE_EN HW_LP_EXIT_IDLE_EN 1 1 HW_LP_IDLE_X32 HW_LP_IDLE_X32 16 12 INIT0 DDRCTRL_INIT0 DDRCTRL SDRAM initialization register 0 0xD0 32 read-write n 0x0 0x0 POST_CKE_X1024 POST_CKE_X1024 16 10 PRE_CKE_X1024 PRE_CKE_X1024 0 12 SKIP_DRAM_INIT SKIP_DRAM_INIT 30 2 INIT1 DDRCTRL_INIT1 DDRCTRL SDRAM initialization register 1 0xD4 32 read-write n 0x0 0x0 DRAM_RSTN_X1024 DRAM_RSTN_X1024 16 9 PRE_OCD_X32 PRE_OCD_X32 0 4 INIT2 DDRCTRL_INIT2 DDRCTRL SDRAM initialization register 2 0xD8 32 read-write n 0x0 0x0 IDLE_AFTER_RESET_X32 IDLE_AFTER_RESET_X32 8 8 MIN_STABLE_CLOCK_X1 MIN_STABLE_CLOCK_X1 0 4 INIT3 DDRCTRL_INIT3 DDRCTRL SDRAM initialization register 3 0xDC 32 read-write n 0x0 0x0 EMR EMR 0 16 MR MR 16 16 INIT4 DDRCTRL_INIT4 DDRCTRL SDRAM initialization register 4 0xE0 32 read-write n 0x0 0x0 EMR2 EMR2 16 16 EMR3 EMR3 0 16 INIT5 DDRCTRL_INIT5 DDRCTRL SDRAM initialization register 5 0xE4 32 read-write n 0x0 0x0 DEV_ZQINIT_X32 DEV_ZQINIT_X32 16 8 MAX_AUTO_INIT_X1024 MAX_AUTO_INIT_X1024 0 10 MRCTRL0 DDRCTRL_MRCTRL0 Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en 0x10 32 read-write n 0x0 0x0 MR_ADDR MR_ADDR 12 4 MR_RANK MR_RANK 4 1 MR_TYPE MR_TYPE 0 1 MR_WR MR_WR 31 1 MRCTRL1 DDRCTRL_MRCTRL1 DDRCTRL mode register read/write control register 1 0x14 32 read-write n 0x0 0x0 MR_DATA MR_DATA 0 16 MRSTAT DDRCTRL_MRSTAT DDRCTRL mode register read/write status register 0x18 32 read-only n 0x0 0x0 MR_WR_BUSY MR_WR_BUSY 0 1 MSTR DDRCTRL_MSTR DDRCTRL master register 0 0x0 32 read-write n 0x0 0x0 BURSTCHOP BURSTCHOP 9 1 BURST_RDWR BURST_RDWR 16 4 DATA_BUS_WIDTH DATA_BUS_WIDTH 12 2 DDR3 DDR3 0 1 DLL_OFF_MODE DLL_OFF_MODE 15 1 EN_2T_TIMING_MODE EN_2T_TIMING_MODE 10 1 LPDDR2 LPDDR2 2 1 LPDDR3 LPDDR3 3 1 ODTCFG DDRCTRL_ODTCFG DDRCTRL ODT configuration register 0x240 32 read-write n 0x0 0x0 RD_ODT_DELAY RD_ODT_DELAY 2 5 RD_ODT_HOLD RD_ODT_HOLD 8 4 WR_ODT_DELAY WR_ODT_DELAY 16 5 WR_ODT_HOLD WR_ODT_HOLD 24 4 ODTMAP DDRCTRL_ODTMAP DDRCTRL ODT/Rank map register 0x244 32 read-write n 0x0 0x0 RANK0_RD_ODT RANK0_RD_ODT 4 1 RANK0_WR_ODT RANK0_WR_ODT 0 1 PCCFG DDRCTRL_PCCFG DDRCTRL port common configuration register 0x400 32 read-write n 0x0 0x0 BL_EXP_MODE BL_EXP_MODE 8 1 GO2CRITICAL_EN GO2CRITICAL_EN 0 1 PAGEMATCH_LIMIT PAGEMATCH_LIMIT 4 1 PCFGQOS0_0 DDRCTRL_PCFGQOS0_0 DDRCTRL port 0 read Q0S configuration register 0 0x494 32 read-write n 0x0 0x0 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 PCFGQOS0_1 DDRCTRL_PCFGQOS0_1 DDRCTRL port 1 read Q0S configuration register 0 0x544 32 read-write n 0x0 0x0 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 PCFGQOS1_0 DDRCTRL_PCFGQOS1_0 DDRCTRL port 0 read Q0S configuration register 1 0x498 32 read-write n 0x0 0x0 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 PCFGQOS1_1 DDRCTRL_PCFGQOS1_1 DDRCTRL port 1 read Q0S configuration register 1 0x548 32 read-write n 0x0 0x0 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 PCFGR_0 DDRCTRL_PCFGR_0 DDRCTRL port 0 configuration read register 0x404 32 read-write n 0x0 0x0 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 PCFGR_1 DDRCTRL_PCFGR_1 DDRCTRL port 1 configuration read register 0x4B4 32 read-write n 0x0 0x0 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 PCFGWQOS0_0 DDRCTRL_PCFGWQOS0_0 DDRCTRL port 0 write Q0S configuration register 0 0x49C 32 read-write n 0x0 0x0 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 PCFGWQOS0_1 DDRCTRL_PCFGWQOS0_1 DDRCTRL port 1 write Q0S configuration register 0 0x54C 32 read-write n 0x0 0x0 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 PCFGWQOS1_0 DDRCTRL_PCFGWQOS1_0 DDRCTRL port 0 write Q0S configuration register 1 0x4A0 32 read-write n 0x0 0x0 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 PCFGWQOS1_1 DDRCTRL_PCFGWQOS1_1 DDRCTRL port 1 write Q0S configuration register 1 0x550 32 read-write n 0x0 0x0 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 PCFGW_0 DDRCTRL_PCFGW_0 DDRCTRL port 0 configuration write register 0x408 32 read-write n 0x0 0x0 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 PCFGW_1 DDRCTRL_PCFGW_1 DDRCTRL port 1 configuration write register 0x4B8 32 read-write n 0x0 0x0 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 PCTRL_0 DDRCTRL_PCTRL_0 DDRCTRL port 0 control register 0x490 32 read-write n 0x0 0x0 PORT_EN PORT_EN 0 1 PCTRL_1 DDRCTRL_PCTRL_1 DDRCTRL port 1 control register 0x540 32 read-write n 0x0 0x0 PORT_EN PORT_EN 0 1 PERFHPR1 DDRCTRL_PERFHPR1 DDRCTRL high priority read CAM register 1 0x25C 32 read-write n 0x0 0x0 HPR_MAX_STARVE HPR_MAX_STARVE 0 16 HPR_XACT_RUN_LENGTH HPR_XACT_RUN_LENGTH 24 8 PERFLPR1 DDRCTRL_PERFLPR1 DDRCTRL low priority read CAM register 1 0x264 32 read-write n 0x0 0x0 LPR_MAX_STARVE LPR_MAX_STARVE 0 16 LPR_XACT_RUN_LENGTH LPR_XACT_RUN_LENGTH 24 8 PERFWR1 DDRCTRL_PERFWR1 DDRCTRL write CAM register 1 0x26C 32 read-write n 0x0 0x0 W_MAX_STARVE W_MAX_STARVE 0 16 W_XACT_RUN_LENGTH W_XACT_RUN_LENGTH 24 8 POISONCFG DDRCTRL_POISONCFG AXI Poison configuration register common for all AXI ports. 0x36C 32 read-write n 0x0 0x0 RD_POISON_INTR_CLR RD_POISON_INTR_CLR 24 1 RD_POISON_INTR_EN RD_POISON_INTR_EN 20 1 RD_POISON_SLVERR_EN RD_POISON_SLVERR_EN 16 1 WR_POISON_INTR_CLR WR_POISON_INTR_CLR 8 1 WR_POISON_INTR_EN WR_POISON_INTR_EN 4 1 WR_POISON_SLVERR_EN WR_POISON_SLVERR_EN 0 1 POISONSTAT DDRCTRL_POISONSTAT DDRCTRL AXI Poison status register 0x370 32 read-only n 0x0 0x0 RD_POISON_INTR_0 RD_POISON_INTR_0 16 1 RD_POISON_INTR_1 RD_POISON_INTR_1 17 1 WR_POISON_INTR_0 WR_POISON_INTR_0 0 1 WR_POISON_INTR_1 WR_POISON_INTR_1 1 1 PSTAT DDRCTRL_PSTAT DDRCTRL port status register 0x3FC 32 read-only n 0x0 0x0 RD_PORT_BUSY_0 RD_PORT_BUSY_0 0 1 RD_PORT_BUSY_1 RD_PORT_BUSY_1 1 1 WR_PORT_BUSY_0 WR_PORT_BUSY_0 16 1 WR_PORT_BUSY_1 WR_PORT_BUSY_1 17 1 PWRCTL DDRCTRL_PWRCTL DDRCTRL low power control register 0x30 32 read-write n 0x0 0x0 DEEPPOWERDOWN_EN DEEPPOWERDOWN_EN 2 1 DIS_CAM_DRAIN_SELFREF DIS_CAM_DRAIN_SELFREF 7 1 EN_DFI_DRAM_CLK_DISABLE EN_DFI_DRAM_CLK_DISABLE 3 1 POWERDOWN_EN POWERDOWN_EN 1 1 SELFREF_EN SELFREF_EN 0 1 SELFREF_SW SELFREF_SW 5 1 PWRTMG DDRCTRL_PWRTMG DDRCTRL low power timing register 0x34 32 read-write n 0x0 0x0 POWERDOWN_TO_X32 POWERDOWN_TO_X32 0 5 SELFREF_TO_X32 SELFREF_TO_X32 16 8 T_DPD_X4096 T_DPD_X4096 8 8 RFSHCTL0 DDRCTRL_RFSHCTL0 DDRCTRL refresh control register 0 0x50 32 read-write n 0x0 0x0 PER_BANK_REFRESH PER_BANK_REFRESH 2 1 REFRESH_BURST REFRESH_BURST 4 5 REFRESH_MARGIN REFRESH_MARGIN 20 4 REFRESH_TO_X32 REFRESH_TO_X32 12 5 RFSHCTL3 DDRCTRL_RFSHCTL3 DDRCTRL refresh control register 3 0x60 32 read-write n 0x0 0x0 DIS_AUTO_REFRESH DIS_AUTO_REFRESH 0 1 REFRESH_UPDATE_LEVEL REFRESH_UPDATE_LEVEL 1 1 RFSHTMG DDRCTRL_RFSHTMG DDRCTRL refresh timing register 0x64 32 read-write n 0x0 0x0 LPDDR3_TREFBW_EN LPDDR3_TREFBW_EN 15 1 T_RFC_MIN T_RFC_MIN 0 10 T_RFC_NOM_X1_SEL T_RFC_NOM_X1_SEL 31 1 T_RFC_NOM_X1_X32 T_RFC_NOM_X1_X32 16 12 SCHED DDRCTRL_SCHED DDRCTRL scheduler control register 0x250 32 read-write n 0x0 0x0 FORCE_LOW_PRI_N FORCE_LOW_PRI_N 0 1 GO2CRITICAL_HYSTERESIS GO2CRITICAL_HYSTERESIS 16 8 LPR_NUM_ENTRIES LPR_NUM_ENTRIES 8 4 PAGECLOSE PAGECLOSE 2 1 PREFER_WRITE PREFER_WRITE 1 1 RDWR_IDLE_GAP RDWR_IDLE_GAP 24 7 SCHED1 DDRCTRL_SCHED1 DDRCTRL scheduler control register 1 0x254 32 read-write n 0x0 0x0 PAGECLOSE_TIMER PAGECLOSE_TIMER 0 8 STAT DDRCTRL_STAT DDRCTRL operating mode status register 0x4 32 read-only n 0x0 0x0 OPERATING_MODE OPERATING_MODE 0 3 SELFREF_CAM_NOT_EMPTY SELFREF_CAM_NOT_EMPTY 12 1 SELFREF_TYPE SELFREF_TYPE 4 2 SWCTL DDRCTRL_SWCTL DDRCTRL software register programming control enable 0x320 32 read-write n 0x0 0x0 SW_DONE SW_DONE 0 1 SWSTAT DDRCTRL_SWSTAT DDRCTRL software register programming control status 0x324 32 read-only n 0x0 0x0 SW_DONE_ACK SW_DONE_ACK 0 1 ZQCTL0 DDRCTRL_ZQCTL0 DDRCTRL ZQ control register 0 0x180 32 read-write n 0x0 0x0 DIS_AUTO_ZQ DIS_AUTO_ZQ 31 1 DIS_SRX_ZQCL DIS_SRX_ZQCL 30 1 T_ZQ_LONG_NOP T_ZQ_LONG_NOP 16 11 T_ZQ_SHORT_NOP T_ZQ_SHORT_NOP 0 10 ZQ_RESISTOR_SHARED ZQ_RESISTOR_SHARED 29 1 ZQCTL1 DDRCTRL_ZQCTL1 DDRCTRL ZQ control register 1 0x184 32 read-write n 0x0 0x0 T_ZQ_RESET_NOP T_ZQ_RESET_NOP 20 10 T_ZQ_SHORT_INTERVAL_X1024 T_ZQ_SHORT_INTERVAL_X1024 0 20 ZQCTL2 DDRCTRL_ZQCTL2 DDRCTRL ZQ control register 2 0x188 32 read-write n 0x0 0x0 ZQ_RESET ZQ_RESET 0 1 ZQSTAT DDRCTRL_ZQSTAT DDRCTRL ZQ status register 0x18C 32 read-only n 0x0 0x0 ZQ_RESET_BUSY ZQ_RESET_BUSY 0 1 DDRPERFM DDRPERFM DDRPERFM 0x0 0x0 0x400 registers n CCR DDRPERFM_CCR Write-only register. A read request returns all zeros 0xC 32 write-only n 0x0 0x0 CCLR CCLR 0 4 TCLR TCLR 31 1 CFG DDRPERFM_CFG DDRPERFM configurationl register 0x4 32 read-write n 0x0 0x0 EN EN 0 4 SEL SEL 16 2 CNT0 DDRPERFM_CNT0 DDRPERFM event counter 0 register 0x60 32 read-only n 0x0 0x0 CNT CNT 0 32 CNT1 DDRPERFM_CNT1 DDRPERFM event counter 1 register 0x68 32 read-only n 0x0 0x0 CNT CNT 0 32 CNT2 DDRPERFM_CNT2 DDRPERFM event counter 2 register 0x70 32 read-only n 0x0 0x0 CNT CNT 0 32 CNT3 DDRPERFM_CNT3 DDRPERFM event counter 3 register 0x78 32 read-only n 0x0 0x0 CNT CNT 0 32 CTL DDRPERFM_CTL Write-only register. A read request returns all zeros. 0x0 32 write-only n 0x0 0x0 START START 0 1 STOP STOP 1 1 HWCFG DDRPERFM_HWCFG DDRPERFM hardware configuration register 0x3F0 32 read-only n 0x0 0x0 NCNT NCNT 0 4 ICR DDRPERFM_ICR Write-only register. A read request returns all zeros 0x18 32 write-only n 0x0 0x0 OVF OVF 0 1 ID DDRPERFM_ID DDRPERFM ID register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 IER DDRPERFM_IER DDRPERFM interrupt enable register 0x10 32 read-write n 0x0 0x0 OVFIE OVFIE 0 1 ISR DDRPERFM_ISR DDRPERFM interrupt status register 0x14 32 read-only n 0x0 0x0 OVFF OVFF 0 1 SID DDRPERFM_SID DDRPERFM magic ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 STATUS DDRPERFM_STATUS DDRPERFM status register 0x8 32 read-only n 0x0 0x0 BUSY BUSY 16 1 COVF COVF 0 4 TOVF TOVF 31 1 TCNT DDRPERFM_TCNT DDRPERFM time counter register 0x20 32 read-only n 0x0 0x0 CNT CNT 0 32 VER DDRPERFM_VER DDRPERFM version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DDRPHYC DDRPHYC DDRPHYC 0x0 0x0 0x1000 registers n ACDLLCR DDRPHYC_ACDLLCR DDRPHYC AC DLL control register 0x14 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 DLLDIS DLLDIS 31 1 DLLSRST DLLSRST 30 1 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 ACIOCR DDRPHYC_ACIOCR DDRPHYC ACIOC register 0x24 32 read-write n 0x0 0x0 ACIOM ACIOM 0 1 ACODT ACODT 2 1 ACOE ACOE 1 1 ACPDD ACPDD 3 1 ACPDR ACPDR 4 1 ACSR ACSR 30 2 CKODT CKODT 5 3 CKPDD CKPDD 8 3 CKPDR CKPDR 11 3 CSPDD CSPDD 18 1 RANKODT RANKODT 14 1 RANKPDR RANKPDR 22 1 RSTIOM RSTIOM 29 1 RSTODT RSTODT 26 1 RSTPDD RSTPDD 27 1 RSTPDR RSTPDR 28 1 DCR DDRPHYC_DCR DDRPHYC DC register 0x30 32 read-write n 0x0 0x0 DDR2T DDR2T 28 1 DDR8BNK DDR8BNK 3 1 DDRMD DDRMD 0 3 DDRTYPE DDRTYPE 8 2 MPRDQ MPRDQ 7 1 NOSRA NOSRA 27 1 PDQ PDQ 4 3 RDIMM RDIMM 30 1 TPD TPD 31 1 UDIMM UDIMM 29 1 DDR3_MR0 DDRPHYC_DDR3_MR0 DDRPHYC MR0 register for DDR3 0x40 16 read-write n 0x0 0x0 BL BL 0 2 BT BT 3 1 CL CL 4 3 CL0 CL0 2 1 DR DR 8 1 PD PD 12 1 RSVD RSVD 13 3 TM TM 7 1 WR WR 9 3 DDR3_MR1 DDRPHYC_DDR3_MR1 DDRPHYC MR1 register for DDR3 0x44 16 read-write n 0x0 0x0 AL AL 3 2 DE DE 0 1 DIC0 DIC0 1 1 DIC1 DIC1 5 1 LEVEL LEVEL 7 1 QOFF QOFF 12 1 RTT0 RTT0 2 1 RTT1 RTT1 6 1 RTT2 RTT2 9 1 TDQS TDQS 11 1 DDR3_MR2 DDRPHYC_DDR3_MR2 DDRPHYC MR2 register for DDR3 0x48 16 read-write n 0x0 0x0 ASR ASR 6 1 CWL CWL 3 3 PASR PASR 0 3 RTTWR RTTWR 9 2 SRT SRT 7 1 DDR3_MR3 DDRPHYC_DDR3_MR3 DDRPHYC MR3 register for DDR3 0x4C 8 read-write n 0x0 0x0 MPR MPR 2 1 MPRLOC MPRLOC 0 2 DLLGCR DDRPHYC_DLLGCR DDRPHYC DDR global control register 0x10 32 read-write n 0x0 0x0 ATC ATC 9 2 BPS200 BPS200 23 1 DLLRSVD2 DLLRSVD2 30 2 DRES DRES 0 2 DTC DTC 6 3 FDTRMSL FDTRMSL 27 2 IPUMP IPUMP 2 3 LOCKDET LOCKDET 29 1 MBIAS MBIAS 12 8 SBIAS2_0 SBIAS2_0 20 3 SBIAS5_3 SBIAS5_3 24 3 TESTEN TESTEN 5 1 TESTSW TESTSW 11 1 DSGCR DDRPHYC_DSGCR DDRPHYC DSGC register 0x2C 32 read-write n 0x0 0x0 BDISEN BDISEN 1 1 CKEOE CKEOE 31 1 CKEPDD CKEPDD 16 1 CKOE CKOE 28 1 DQSGE DQSGE 8 3 DQSGX DQSGX 5 3 FXDLAT FXDLAT 12 1 LPDLLPD LPDLLPD 4 1 LPIOPD LPIOPD 3 1 NL2OE NL2OE 25 1 NL2PD NL2PD 24 1 NOBUB NOBUB 11 1 ODTOE ODTOE 29 1 ODTPDD ODTPDD 20 1 PUREN PUREN 0 1 RSTOE RSTOE 30 1 TPDOE TPDOE 27 1 TPDPD TPDPD 26 1 ZUEN ZUEN 2 1 DTAR DDRPHYC_DTAR DDRPHYC DTA register 0x54 32 read-write n 0x0 0x0 DTBANK DTBANK 28 3 DTCOL DTCOL 0 12 DTMPR DTMPR 31 1 DTROW DTROW 12 16 DTDR0 DDRPHYC_DTDR0 DDRPHYC DTD register 0 0x58 32 read-write n 0x0 0x0 DTBYTE0 DTBYTE0 0 8 DTBYTE1 DTBYTE1 8 8 DTBYTE2 DTBYTE2 16 8 DTBYTE3 DTBYTE3 24 8 DTDR1 DDRPHYC_DTDR1 DDRPHYC DTD register 1 0x5C 32 read-write n 0x0 0x0 DTBYTE4 DTBYTE4 0 8 DTBYTE5 DTBYTE5 8 8 DTBYTE6 DTBYTE6 16 8 DTBYTE7 DTBYTE7 24 8 DTPR0 DDRPHYC_DTPR0 DDRPHYC DTP register 0 0x34 32 read-write n 0x0 0x0 TCCD TCCD 31 1 TMRD TMRD 0 2 TRAS TRAS 16 5 TRC TRC 25 6 TRCD TRCD 12 4 TRP TRP 8 4 TRRD TRRD 21 4 TRTP TRTP 2 3 TWTR TWTR 5 3 DTPR1 DDRPHYC_DTPR1 DDRPHYC DTP register 1 0x38 32 read-write n 0x0 0x0 TAOND TAOND 0 2 TDQSCKMAX TDQSCKMAX 27 3 TDQSCKMIN TDQSCKMIN 24 3 TFAW TFAW 3 6 TMOD TMOD 9 2 TRFC TRFC 16 8 TRTODT TRTODT 11 1 TRTW TRTW 2 1 DTPR2 DDRPHYC_DTPR2 DDRPHYC DTP register 2 0x3C 32 read-write n 0x0 0x0 TCKE TCKE 15 4 TDLLK TDLLK 19 10 TXP TXP 10 5 TXS TXS 0 10 DX0DLLCR DDRPHYC_DX0DLLCR DDRPHYC byte lane 0 DLLC register 0x1CC 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 DLLDIS DLLDIS 31 1 DLLSRST DLLSRST 30 1 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SDLBMODE SDLBMODE 19 1 SDPHASE SDPHASE 14 4 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 SSTART SSTART 12 2 DX0DQSTR DDRPHYC_DX0DQSTR DDRPHYC byte lane 0 DQST register 0x1D4 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 R0DGPS R0DGPS 12 2 R0DGSL R0DGSL 0 3 DX0DQTR DDRPHYC_DX0DQTR DDRPHYC byte lane 0 DQT register 0x1D0 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX0GCR DDRPHYC_DX0GCR DDRPHYC byte lane 0 GC register 0x1C0 32 read-write n 0x0 0x0 DQODT DQODT 2 1 DQRTT DQRTT 10 1 DQSODT DQSODT 1 1 DQSRPD DQSRPD 6 1 DQSRTT DQSRTT 9 1 DSEN DSEN 7 2 DXEN DXEN 0 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 R0RVSL R0RVSL 14 3 RTTOAL RTTOAL 13 1 RTTOH RTTOH 11 2 DX0GSR0 DDRPHYC_DX0GSR0 DDRPHYC byte lane 0 GS register 0 0x1C4 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX0GSR1 DDRPHYC_DX0GSR1 DDRPHYC byte lane 0 GS register 1 0x1C8 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX1DLLCR DDRPHYC_DX1DLLCR DDRPHYC byte lane 1 DLLC register 0x20C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 DLLDIS DLLDIS 31 1 DLLSRST DLLSRST 30 1 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SDLBMODE SDLBMODE 19 1 SDPHASE SDPHASE 14 4 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 SSTART SSTART 12 2 DX1DQSTR DDRPHYC_DX1DQSTR DDRPHYC byte lane 1 DQST register 0x214 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 R0DGPS R0DGPS 12 2 R0DGSL R0DGSL 0 3 DX1DQTR DDRPHYC_DX1DQTR DDRPHYC byte lane 1 DQT register 0x210 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX1GCR DDRPHYC_DX1GCR DDRPHYC byte lane 1 GC register 0x200 32 read-write n 0x0 0x0 DQODT DQODT 2 1 DQRTT DQRTT 10 1 DQSODT DQSODT 1 1 DQSRPD DQSRPD 6 1 DQSRTT DQSRTT 9 1 DSEN DSEN 7 2 DXEN DXEN 0 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 R0RVSL R0RVSL 14 3 RTTOAL RTTOAL 13 1 RTTOH RTTOH 11 2 DX1GSR0 DDRPHYC_DX1GSR0 DDRPHYC byte lane 1 GS register 0 0x204 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX1GSR1 DDRPHYC_DX1GSR1 DDRPHYC byte lane 1 GS register 1 0x208 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX2DLLCR DDRPHYC_DX2DLLCR DDRPHYC byte lane 2 DLLC register 0x24C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 DLLDIS DLLDIS 31 1 DLLSRST DLLSRST 30 1 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SDLBMODE SDLBMODE 19 1 SDPHASE SDPHASE 14 4 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 SSTART SSTART 12 2 DX2DQSTR DDRPHYC_DX2DQSTR DDRPHYC byte lane 2 DQST register 0x254 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 R0DGPS R0DGPS 12 2 R0DGSL R0DGSL 0 3 DX2DQTR DDRPHYC_DX2DQTR DDRPHYC byte lane 2 DQT register 0x250 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX2GCR DDRPHYC_DX2GCR DDRPHYC byte lane 2 GC register 0x240 32 read-write n 0x0 0x0 DQODT DQODT 2 1 DQRTT DQRTT 10 1 DQSODT DQSODT 1 1 DQSRPD DQSRPD 6 1 DQSRTT DQSRTT 9 1 DSEN DSEN 7 2 DXEN DXEN 0 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 R0RVSL R0RVSL 14 3 RTTOAL RTTOAL 13 1 RTTOH RTTOH 11 2 DX2GSR0 DDRPHYC_DX2GSR0 DDRPHYC byte lane 2 GS register 0 0x244 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX2GSR1 DDRPHYC_DX2GSR1 DDRPHYC byte lane 2 GS register 1 0x248 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DX3DLLCR DDRPHYC_DX3DLLCR DDRPHYC byte lane 3 DLLC register 0x28C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 DLLDIS DLLDIS 31 1 DLLSRST DLLSRST 30 1 MFBDLY MFBDLY 6 3 MFWDLY MFWDLY 9 3 SDLBMODE SDLBMODE 19 1 SDPHASE SDPHASE 14 4 SFBDLY SFBDLY 0 3 SFWDLY SFWDLY 3 3 SSTART SSTART 12 2 DX3DQSTR DDRPHYC_DX3DQSTR DDRPHYC byte lane 3 DQST register 0x294 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 DQSDLY DQSDLY 20 3 DQSNDLY DQSNDLY 23 3 R0DGPS R0DGPS 12 2 R0DGSL R0DGSL 0 3 DX3DQTR DDRPHYC_DX3DQTR DDRPHYC byte lane 3 DQT register 0x290 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 DQDLY1 DQDLY1 4 4 DQDLY2 DQDLY2 8 4 DQDLY3 DQDLY3 12 4 DQDLY4 DQDLY4 16 4 DQDLY5 DQDLY5 20 4 DQDLY6 DQDLY6 24 4 DQDLY7 DQDLY7 28 4 DX3GCR DDRPHYC_DX3GCR DDRPHYC byte lane 3 GC register 0x280 32 read-write n 0x0 0x0 DQODT DQODT 2 1 DQRTT DQRTT 10 1 DQSODT DQSODT 1 1 DQSRPD DQSRPD 6 1 DQSRTT DQSRTT 9 1 DSEN DSEN 7 2 DXEN DXEN 0 1 DXIOM DXIOM 3 1 DXPDD DXPDD 4 1 DXPDR DXPDR 5 1 R0RVSL R0RVSL 14 3 RTTOAL RTTOAL 13 1 RTTOH RTTOH 11 2 DX3GSR0 DDRPHYC_DX3GSR0 DDRPHYC byte lane 3 GS register 0 0x284 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 DTERR DTERR 4 1 DTIERR DTIERR 8 1 DTPASS DTPASS 13 3 DX3GSR1 DDRPHYC_DX3GSR1 DDRPHYC byte lane 3 GS register 1 0x288 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 DQSDFT DQSDFT 4 2 RVERR RVERR 12 1 RVIERR RVIERR 16 1 RVPASS RVPASS 20 3 DXCCR DDRPHYC_DXCCR DDRPHYC DXCC register 0x28 32 read-write n 0x0 0x0 AWDT AWDT 16 1 DQSNRES DQSNRES 8 4 DQSNRST DQSNRST 14 1 DQSRES DQSRES 4 4 DXIOM DXIOM 1 1 DXODT DXODT 0 1 DXPDD DXPDD 2 1 DXPDR DXPDR 3 1 RVSEL RVSEL 15 1 GPR0 DDRPHYC_GPR0 DDRPHYC general purpose register 0 0x178 32 read-write n 0x0 0x0 GPR0 GPR0 0 32 GPR1 DDRPHYC_GPR1 DDRPHYC general purpose register 1 0x17C 32 read-write n 0x0 0x0 GPR1 GPR1 0 32 ODTCR DDRPHYC_ODTCR DDRPHYC ODTC register 0x50 32 read-write n 0x0 0x0 RDODT RDODT 0 1 WRODT WRODT 16 1 PGCR DDRPHYC_PGCR DDRPHYC PHY global control register 0x8 32 read-write n 0x0 0x0 CKDV CKDV 12 2 CKEN CKEN 9 3 CKINV CKINV 14 1 DFTCMP DFTCMP 2 1 DFTLMT DFTLMT 3 2 DQSCFG DQSCFG 1 1 DTOSEL DTOSEL 5 4 IODDRM IODDRM 16 2 IOLB IOLB 15 1 ITMDMD ITMDMD 0 1 LBDQSS LBDQSS 29 1 LBGDQS LBGDQS 30 1 LBMODE LBMODE 31 1 PDDISDX PDDISDX 24 1 RANKEN RANKEN 18 4 RFSHDT RFSHDT 25 4 ZKSEL ZKSEL 22 2 PGSR DDRPHYC_PGSR DDRPHYC PHY global status register 0xC 32 read-only n 0x0 0x0 DFTERR DFTERR 7 1 DIDONE DIDONE 3 1 DLDONE DLDONE 1 1 DTDONE DTDONE 4 1 DTERR DTERR 5 1 DTIERR DTIERR 6 1 IDONE IDONE 0 1 RVEIRR RVEIRR 9 1 RVERR RVERR 8 1 TQ TQ 31 1 ZCDDONE ZCDDONE 2 1 PIR DDRPHYC_PIR DDRPHYC PHY initialization register 0x4 32 write-only n 0x0 0x0 CLRSR CLRSR 28 1 CTLDINIT CTLDINIT 18 1 DLLBYP DLLBYP 17 1 DLLLOCK DLLLOCK 2 1 DLLSRST DLLSRST 1 1 DRAMINIT DRAMINIT 6 1 DRAMRST DRAMRST 5 1 ICPC ICPC 16 1 INIT INIT 0 1 INITBYP INITBYP 31 1 ITMSRST ITMSRST 4 1 LOCKBYP LOCKBYP 29 1 QSTRN QSTRN 7 1 RVTRN RVTRN 8 1 ZCAL ZCAL 3 1 ZCALBYP ZCALBYP 30 1 PTR0 DDRPHYC_PTR0 DDRPHYC PT register 0 0x18 32 read-write n 0x0 0x0 TDLLLOCK TDLLLOCK 6 12 TDLLSRST TDLLSRST 0 6 TITMSRST TITMSRST 18 4 PTR1 DDRPHYC_PTR1 DDRPHYC PT register 1 0x1C 32 read-write n 0x0 0x0 TDINIT0 TDINIT0 0 19 TDINIT1 TDINIT1 19 8 PTR2 DDRPHYC_PTR2 DDRPHYC PT register 2 0x20 32 read-write n 0x0 0x0 TDINIT2 TDINIT2 0 17 TDINIT3 TDINIT3 17 10 RIDR DDRPHYC_RIDR DDRPHYC revision ID register 0x0 32 read-only n 0x0 0x0 PHYMDR PHYMDR 16 4 PHYMJR PHYMJR 20 4 PHYMNR PHYMNR 12 4 PUBMDR PUBMDR 4 4 PUBMJR PUBMJR 8 4 PUBMNR PUBMNR 0 4 UDRID UDRID 24 8 ZQ0CR0 DDRPHYC_ZQ0CR0 DDRPHYC ZQ0C register 0 0x180 32 read-write n 0x0 0x0 ZCAL ZCAL 30 1 ZCALBYP ZCALBYP 29 1 ZDATA ZDATA 0 20 ZDEN ZDEN 28 1 ZQPD ZQPD 31 1 ZQ0CR1 DDRPHYC_ZQ0CR1 DDRPHYC ZQ0CR1 register 0x184 8 read-write n 0x0 0x0 ZPROG ZPROG 0 8 ZQ0SR0 DDRPHYC_ZQ0SR0 DDRPHYC ZQ0S register 0 0x188 32 read-only n 0x0 0x0 ZCTRL ZCTRL 0 20 ZDONE ZDONE 31 1 ZERR ZERR 30 1 ZQ0SR1 DDRPHYC_ZQ0SR1 DDRPHYC ZQ0S register 1 0x18C 8 read-only n 0x0 0x0 OPD OPD 4 2 OPU OPU 6 2 ZPD ZPD 0 2 ZPU ZPU 2 2 DFSDM1 DFSDM1 DFSDM1 0x0 0x0 0x800 registers n DFSDM_CH0AWSCDR DFSDM_CH0AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH0CFGR1 DFSDM_CH0CFGR1 This register specifies the parameters used by channel y. 0x0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH0CFGR2 DFSDM_CH0CFGR2 This register specifies the parameters used by channel y. 0x4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH0DATINR DFSDM_CH0DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x10 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH0DLYR DFSDM_CH0DLYR DFSDM channel 0 delay register 0x14 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH0WDATR DFSDM_CH0WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH1AWSCDR DFSDM_CH1AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x28 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH1CFGR1 DFSDM_CH1CFGR1 This register specifies the parameters used by channel y. 0x20 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH1CFGR2 DFSDM_CH1CFGR2 This register specifies the parameters used by channel y. 0x24 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH1DATINR DFSDM_CH1DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x30 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH1DLYR DFSDM_CH1DLYR DFSDM channel 1 delay register 0x34 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH1WDATR DFSDM_CH1WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x2C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH2AWSCDR DFSDM_CH2AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x48 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH2CFGR1 DFSDM_CH2CFGR1 This register specifies the parameters used by channel y. 0x40 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH2CFGR2 DFSDM_CH2CFGR2 This register specifies the parameters used by channel y. 0x44 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH2DATINR DFSDM_CH2DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x50 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH2DLYR DFSDM_CH2DLYR DFSDM channel 2 delay register 0x54 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH2WDATR DFSDM_CH2WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x4C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH3AWSCDR DFSDM_CH3AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x68 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH3CFGR1 DFSDM_CH3CFGR1 This register specifies the parameters used by channel y. 0x60 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH3CFGR2 DFSDM_CH3CFGR2 This register specifies the parameters used by channel y. 0x64 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH3DATINR DFSDM_CH3DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x70 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH3DLYR DFSDM_CH3DLYR DFSDM channel 3 delay register 0x74 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH3WDATR DFSDM_CH3WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x6C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH4AWSCDR DFSDM_CH4AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0x88 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH4CFGR1 DFSDM_CH4CFGR1 This register specifies the parameters used by channel y. 0x80 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH4CFGR2 DFSDM_CH4CFGR2 This register specifies the parameters used by channel y. 0x84 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH4DATINR DFSDM_CH4DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x90 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH4DLYR DFSDM_CH4DLYR DFSDM channel 4 delay register 0x94 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH4WDATR DFSDM_CH4WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0x8C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH5AWSCDR DFSDM_CH5AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xA8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH5CFGR1 DFSDM_CH5CFGR1 This register specifies the parameters used by channel y. 0xA0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH5CFGR2 DFSDM_CH5CFGR2 This register specifies the parameters used by channel y. 0xA4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH5DATINR DFSDM_CH5DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xB0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH5DLYR DFSDM_CH5DLYR DFSDM channel 5 delay register 0xB4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH5WDATR DFSDM_CH5WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xAC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH6AWSCDR DFSDM_CH6AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xC8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH6CFGR1 DFSDM_CH6CFGR1 This register specifies the parameters used by channel y. 0xC0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH6CFGR2 DFSDM_CH6CFGR2 This register specifies the parameters used by channel y. 0xC4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH6DATINR DFSDM_CH6DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xD0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH6DLYR DFSDM_CH6DLYR DFSDM channel 6 delay register 0xD4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH6WDATR DFSDM_CH6WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xCC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_CH7AWSCDR DFSDM_CH7AWSCDR Short-circuit detector and analog watchdog settings for channel y. 0xE8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 DFSDM_CH7CFGR1 DFSDM_CH7CFGR1 This register specifies the parameters used by channel y. 0xE0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 CHINSEL CHINSEL 8 1 CKABEN CKABEN 6 1 CKOUTDIV CKOUTDIV 16 8 CKOUTSRC CKOUTSRC 30 1 DATMPX DATMPX 12 2 DATPACK DATPACK 14 2 DFSDMEN DFSDMEN 31 1 SCDEN SCDEN 5 1 SITP SITP 0 2 SPICKSEL SPICKSEL 2 2 DFSDM_CH7CFGR2 DFSDM_CH7CFGR2 This register specifies the parameters used by channel y. 0xE4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 OFFSET OFFSET 8 24 DFSDM_CH7DATINR DFSDM_CH7DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xF0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 INDAT1 INDAT1 16 16 DFSDM_CH7DLYR DFSDM_CH7DLYR DFSDM channel 7 delay register 0xF4 32 read-write n 0x0 0x0 PLSSKP PLSSKP 0 6 DFSDM_CH7WDATR DFSDM_CH7WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y. 0xEC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR DFSDM filter 0 analog watchdog clear flag register 0x12C 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR DFSDM filter 0 analog watchdog high threshold register 0x120 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR DFSDM filter 0 analog watchdog low threshold register 0x124 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT0AWSR DFSDM_FLT0AWSR DFSDM filter 0 analog watchdog status register 0x128 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR DFSDM filter 0 conversion timer register 0x138 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT0CR1 DFSDM_FLT0CR1 DFSDM filter 0 control register 1 0x100 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT0CR2 DFSDM_FLT0CR2 DFSDM filter 0 control register 2 0x104 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX DFSDM filter 0 extremes detector maximum register 0x130 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN DFSDM filter 0 extremes detector minimum register 0x134 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT0FCR DFSDM_FLT0FCR DFSDM filter 0 control register 0x114 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT0ICR DFSDM_FLT0ICR DFSDM filter 0 interrupt flag clear register 0x10C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT0ISR DFSDM_FLT0ISR DFSDM filter 0 interrupt and status register 0x108 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR DFSDM filter 0 injected channel group selection register 0x110 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR DFSDM filter 0 data register for injected group 0x118 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR DFSDM filter 0 data register for the regular channel 0x11C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR DFSDM filter 1 analog watchdog clear flag register 0x1AC 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR DFSDM filter 1 analog watchdog high threshold register 0x1A0 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR DFSDM filter 1 analog watchdog low threshold register 0x1A4 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT1AWSR DFSDM_FLT1AWSR DFSDM filter 1 analog watchdog status register 0x1A8 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR DFSDM filter 1 conversion timer register 0x1B8 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT1CR1 DFSDM_FLT1CR1 DFSDM filter 1 control register 1 0x180 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT1CR2 DFSDM_FLT1CR2 DFSDM filter 1 control register 2 0x184 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX DFSDM filter 1 extremes detector maximum register 0x1B0 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN DFSDM filter 1 extremes detector minimum register 0x1B4 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT1FCR DFSDM_FLT1FCR DFSDM filter 1 control register 0x194 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT1ICR DFSDM_FLT1ICR DFSDM filter 1 interrupt flag clear register 0x18C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT1ISR DFSDM_FLT1ISR DFSDM filter 1 interrupt and status register 0x188 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT1JCHGR DFSDM_FLT1JCHGR DFSDM filter 1 injected channel group selection register 0x190 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR DFSDM filter 1 data register for injected group 0x198 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR DFSDM filter 1 data register for the regular channel 0x19C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR DFSDM filter 2 analog watchdog clear flag register 0x22C 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR DFSDM filter 2 analog watchdog high threshold register 0x220 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR DFSDM filter 2 analog watchdog low threshold register 0x224 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT2AWSR DFSDM_FLT2AWSR DFSDM filter 2 analog watchdog status register 0x228 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR DFSDM filter 2 conversion timer register 0x238 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT2CR1 DFSDM_FLT2CR1 DFSDM filter 2 control register 1 0x200 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT2CR2 DFSDM_FLT2CR2 DFSDM filter 2 control register 2 0x204 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX DFSDM filter 2 extremes detector maximum register 0x230 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN DFSDM filter 2 extremes detector minimum register 0x234 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT2FCR DFSDM_FLT2FCR DFSDM filter 2 control register 0x214 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT2ICR DFSDM_FLT2ICR DFSDM filter 2 interrupt flag clear register 0x20C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT2ISR DFSDM_FLT2ISR DFSDM filter 2 interrupt and status register 0x208 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR DFSDM filter 2 injected channel group selection register 0x210 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR DFSDM filter 2 data register for injected group 0x218 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR DFSDM filter 2 data register for the regular channel 0x21C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR DFSDM filter 3 analog watchdog clear flag register 0x2AC 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR DFSDM filter 3 analog watchdog high threshold register 0x2A0 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR DFSDM filter 3 analog watchdog low threshold register 0x2A4 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT3AWSR DFSDM_FLT3AWSR DFSDM filter 3 analog watchdog status register 0x2A8 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR DFSDM filter 3 conversion timer register 0x2B8 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT3CR1 DFSDM_FLT3CR1 DFSDM filter 3 control register 1 0x280 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT3CR2 DFSDM_FLT3CR2 DFSDM filter 3 control register 2 0x284 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX DFSDM filter 3 extremes detector maximum register 0x2B0 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN DFSDM filter 3 extremes detector minimum register 0x2B4 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT3FCR DFSDM_FLT3FCR DFSDM filter 3 control register 0x294 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT3ICR DFSDM_FLT3ICR DFSDM filter 3 interrupt flag clear register 0x28C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT3ISR DFSDM_FLT3ISR DFSDM filter 3 interrupt and status register 0x288 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR DFSDM filter 3 injected channel group selection register 0x290 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR DFSDM filter 3 data register for injected group 0x298 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR DFSDM filter 3 data register for the regular channel 0x29C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_FLT4AWCFR DFSDM_FLT4AWCFR DFSDM filter 4 analog watchdog clear flag register 0x32C 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT4AWHTR DFSDM_FLT4AWHTR DFSDM filter 4 analog watchdog high threshold register 0x320 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT4AWLTR DFSDM_FLT4AWLTR DFSDM filter 4 analog watchdog low threshold register 0x324 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT4AWSR DFSDM_FLT4AWSR DFSDM filter 4 analog watchdog status register 0x328 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT4CNVTIMR DFSDM_FLT4CNVTIMR DFSDM filter 4 conversion timer register 0x338 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT4CR1 DFSDM_FLT4CR1 DFSDM filter 4 control register 1 0x300 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT4CR2 DFSDM_FLT4CR2 DFSDM filter 4 control register 2 0x304 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT4EXMAX DFSDM_FLT4EXMAX DFSDM filter 4 extremes detector maximum register 0x330 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT4EXMIN DFSDM_FLT4EXMIN DFSDM filter 4 extremes detector minimum register 0x334 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT4FCR DFSDM_FLT4FCR DFSDM filter 4 control register 0x314 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT4ICR DFSDM_FLT4ICR DFSDM filter 4 interrupt flag clear register 0x30C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT4ISR DFSDM_FLT4ISR DFSDM filter 4 interrupt and status register 0x308 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT4JCHGR DFSDM_FLT4JCHGR DFSDM filter 4 injected channel group selection register 0x310 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT4JDATAR DFSDM_FLT4JDATAR DFSDM filter 4 data register for injected group 0x318 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT4RDATAR DFSDM_FLT4RDATAR DFSDM filter 4 data register for the regular channel 0x31C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_FLT5AWCFR DFSDM_FLT5AWCFR DFSDM filter 5 analog watchdog clear flag register 0x3AC 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 CLRAWLTF CLRAWLTF 0 8 DFSDM_FLT5AWHTR DFSDM_FLT5AWHTR DFSDM filter 5 analog watchdog high threshold register 0x3A0 32 read-write n 0x0 0x0 AWHT AWHT 8 24 BKAWH BKAWH 0 4 DFSDM_FLT5AWLTR DFSDM_FLT5AWLTR DFSDM filter 5 analog watchdog low threshold register 0x3A4 32 read-write n 0x0 0x0 AWLT AWLT 8 24 BKAWL BKAWL 0 4 DFSDM_FLT5AWSR DFSDM_FLT5AWSR DFSDM filter 5 analog watchdog status register 0x3A8 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 AWLTF AWLTF 0 8 DFSDM_FLT5CNVTIMR DFSDM_FLT5CNVTIMR DFSDM filter 5 conversion timer register 0x3B8 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 DFSDM_FLT5CR1 DFSDM_FLT5CR1 DFSDM filter 5 control register 1 0x380 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 DFEN DFEN 0 1 FAST FAST 29 1 JDMAEN JDMAEN 5 1 JEXTEN JEXTEN 13 2 JEXTSEL JEXTSEL 8 5 JSCAN JSCAN 4 1 JSWSTART JSWSTART 1 1 JSYNC JSYNC 3 1 RCH RCH 24 3 RCONT RCONT 18 1 RDMAEN RDMAEN 21 1 RSWSTART RSWSTART 17 1 RSYNC RSYNC 19 1 DFSDM_FLT5CR2 DFSDM_FLT5CR2 DFSDM filter 5 control register 2 0x384 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 AWDIE AWDIE 4 1 CKABIE CKABIE 6 1 EXCH EXCH 8 8 JEOCIE JEOCIE 0 1 JOVRIE JOVRIE 2 1 REOCIE REOCIE 1 1 ROVRIE ROVRIE 3 1 SCDIE SCDIE 5 1 DFSDM_FLT5EXMAX DFSDM_FLT5EXMAX DFSDM filter 5 extremes detector maximum register 0x3B0 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 EXMAXCH EXMAXCH 0 3 DFSDM_FLT5EXMIN DFSDM_FLT5EXMIN DFSDM filter 5 extremes detector minimum register 0x3B4 32 read-write n 0x0 0x0 EXMIN EXMIN 8 24 read-write EXMINCH EXMINCH 0 3 read-only DFSDM_FLT5FCR DFSDM_FLT5FCR DFSDM filter 5 control register 0x394 32 read-write n 0x0 0x0 FORD FORD 29 3 FOSR FOSR 16 10 IOSR IOSR 0 8 DFSDM_FLT5ICR DFSDM_FLT5ICR DFSDM filter 5 interrupt flag clear register 0x38C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 CLRJOVRF CLRJOVRF 2 1 CLRROVRF CLRROVRF 3 1 CLRSCDF CLRSCDF 24 8 DFSDM_FLT5ISR DFSDM_FLT5ISR DFSDM filter 5 interrupt and status register 0x388 32 read-only n 0x0 0x0 AWDF AWDF 4 1 CKABF CKABF 16 8 JCIP JCIP 13 1 JEOCF JEOCF 0 1 JOVRF JOVRF 2 1 RCIP RCIP 14 1 REOCF REOCF 1 1 ROVRF ROVRF 3 1 SCDF SCDF 24 8 DFSDM_FLT5JCHGR DFSDM_FLT5JCHGR DFSDM filter 5 injected channel group selection register 0x390 32 read-write n 0x0 0x0 JCHG JCHG 0 8 DFSDM_FLT5JDATAR DFSDM_FLT5JDATAR DFSDM filter 5 data register for injected group 0x398 32 read-only n 0x0 0x0 JDATA JDATA 8 24 JDATACH JDATACH 0 3 DFSDM_FLT5RDATAR DFSDM_FLT5RDATAR DFSDM filter 5 data register for the regular channel 0x39C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 RDATACH RDATACH 0 3 RPEND RPEND 4 1 DFSDM_HWCFGR DFSDM_HWCFGR This register specifies the hardware configuration of DFSDM peripheral. 0x7F0 32 read-only n 0x0 0x0 NBF NBF 8 8 NBT NBT 0 8 DFSDM_IPIDR DFSDM_IPIDR This register specifies the identification of DFSDM peripheral. 0x7F8 32 read-only n 0x0 0x0 ID ID 0 32 DFSDM_SIDR DFSDM_SIDR This register specifies the size allocated to DFSDM registers. 0x7FC 32 read-only n 0x0 0x0 SID SID 0 32 DFSDM_VERR DFSDM_VERR This register specifies the version of DFSDM peripheral. 0x7F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DLYBQS DLYBQS DLYB 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 read-write SEN SEN 1 1 read-write DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DLYBSD1 DLYBSD1 DLYBSD1 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 SEN SEN 1 1 DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DLYBSD2 DLYBSD1 DLYBSD1 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 SEN SEN 1 1 DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DLYBSD3 DLYBSD1 DLYBSD1 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 SEN SEN 1 1 DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DMA1 DMA1 DMA1 0x0 0x0 0x400 registers n DMA_HIFCR DMA_HIFCR DMA high interrupt flag clear register 0xC 32 write-only n 0x0 0x0 CDMEIF4 CDMEIF4 2 1 CDMEIF5 CDMEIF5 8 1 CDMEIF6 CDMEIF6 18 1 CDMEIF7 CDMEIF7 24 1 CFEIF4 CFEIF4 0 1 CFEIF5 CFEIF5 6 1 CFEIF6 CFEIF6 16 1 CFEIF7 CFEIF7 22 1 CHTIF4 CHTIF4 4 1 CHTIF5 CHTIF5 10 1 CHTIF6 CHTIF6 20 1 CHTIF7 CHTIF7 26 1 CTCIF4 CTCIF4 5 1 CTCIF5 CTCIF5 11 1 CTCIF6 CTCIF6 21 1 CTCIF7 CTCIF7 27 1 CTEIF4 CTEIF4 3 1 CTEIF5 CTEIF5 9 1 CTEIF6 CTEIF6 19 1 CTEIF7 CTEIF7 25 1 DMA_HISR DMA_HISR DMA high interrupt status register 0x4 32 read-only n 0x0 0x0 DMEIF4 DMEIF4 2 1 DMEIF5 DMEIF5 8 1 DMEIF6 DMEIF6 18 1 DMEIF7 DMEIF7 24 1 FEIF4 FEIF4 0 1 FEIF5 FEIF5 6 1 FEIF6 FEIF6 16 1 FEIF7 FEIF7 22 1 HTIF4 HTIF4 4 1 HTIF5 HTIF5 10 1 HTIF6 HTIF6 20 1 HTIF7 HTIF7 26 1 TCIF4 TCIF4 5 1 TCIF5 TCIF5 11 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 27 1 TEIF4 TEIF4 3 1 TEIF5 TEIF5 9 1 TEIF6 TEIF6 19 1 TEIF7 TEIF7 25 1 DMA_HWCFGR1 DMA_HWCFGR1 DMA hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 DMA_DEF0 DMA_DEF0 0 2 DMA_DEF1 DMA_DEF1 4 2 DMA_DEF2 DMA_DEF2 8 2 DMA_DEF3 DMA_DEF3 12 2 DMA_DEF4 DMA_DEF4 16 2 DMA_DEF5 DMA_DEF5 20 2 DMA_DEF6 DMA_DEF6 24 2 DMA_DEF7 DMA_DEF7 28 2 DMA_HWCFGR2 DMA_HWCFGR2 DMA hardware configuration 2register 0x3EC 32 read-only n 0x0 0x0 CHSEL_WIDTH CHSEL_WIDTH 8 3 FIFO_SIZE FIFO_SIZE 0 2 WRITE_BUFFERABLE WRITE_BUFFERABLE 4 1 DMA_IPDR DMA_IPDR DMA IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DMA_LIFCR DMA_LIFCR DMA low interrupt flag clear register 0x8 32 write-only n 0x0 0x0 CDMEIF0 CDMEIF0 2 1 CDMEIF1 CDMEIF1 8 1 CDMEIF2 CDMEIF2 18 1 CDMEIF3 CDMEIF3 24 1 CFEIF0 CFEIF0 0 1 CFEIF1 CFEIF1 6 1 CFEIF2 CFEIF2 16 1 CFEIF3 CFEIF3 22 1 CHTIF0 CHTIF0 4 1 CHTIF1 CHTIF1 10 1 CHTIF2 CHTIF2 20 1 CHTIF3 CHTIF3 26 1 CTCIF0 CTCIF0 5 1 CTCIF1 CTCIF1 11 1 CTCIF2 CTCIF2 21 1 CTCIF3 CTCIF3 27 1 CTEIF0 CTEIF0 3 1 CTEIF1 CTEIF1 9 1 CTEIF2 CTEIF2 19 1 CTEIF3 CTEIF3 25 1 DMA_LISR DMA_LISR DMA low interrupt status register 0x0 32 read-only n 0x0 0x0 DMEIF0 DMEIF0 2 1 DMEIF1 DMEIF1 8 1 DMEIF2 DMEIF2 18 1 DMEIF3 DMEIF3 24 1 FEIF0 FEIF0 0 1 FEIF1 FEIF1 6 1 FEIF2 FEIF2 16 1 FEIF3 FEIF3 22 1 HTIF0 HTIF0 4 1 HTIF1 HTIF1 10 1 HTIF2 HTIF2 20 1 HTIF3 HTIF3 26 1 TCIF0 TCIF0 5 1 TCIF1 TCIF1 11 1 TCIF2 TCIF2 21 1 TCIF3 TCIF3 27 1 TEIF0 TEIF0 3 1 TEIF1 TEIF1 9 1 TEIF2 TEIF2 19 1 TEIF3 TEIF3 25 1 DMA_S0CR DMA_S0CR This register is used to configure the concerned stream. 0x10 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S0FCR DMA_S0FCR DMA stream 0 FIFO control register 0x24 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S0M0AR DMA_S0M0AR DMA stream 0 memory 0 address register 0x1C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S0M1AR DMA_S0M1AR DMA stream 0 memory 1 address register 0x20 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S0NDTR DMA_S0NDTR DMA stream 0 number of data register 0x14 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S0PAR DMA_S0PAR DMA stream 0 peripheral address register 0x18 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S1CR DMA_S1CR This register is used to configure the concerned stream. 0x28 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S1FCR DMA_S1FCR DMA stream 1 FIFO control register 0x3C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S1M0AR DMA_S1M0AR DMA stream 1 memory 0 address register 0x34 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S1M1AR DMA_S1M1AR DMA stream 1 memory 1 address register 0x38 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S1NDTR DMA_S1NDTR DMA stream 1 number of data register 0x2C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S1PAR DMA_S1PAR DMA stream 1 peripheral address register 0x30 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S2CR DMA_S2CR This register is used to configure the concerned stream. 0x40 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S2FCR DMA_S2FCR DMA stream 2 FIFO control register 0x54 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S2M0AR DMA_S2M0AR DMA stream 2 memory 0 address register 0x4C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S2M1AR DMA_S2M1AR DMA stream 2 memory 1 address register 0x50 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S2NDTR DMA_S2NDTR DMA stream 2 number of data register 0x44 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S2PAR DMA_S2PAR DMA stream 2 peripheral address register 0x48 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S3CR DMA_S3CR This register is used to configure the concerned stream. 0x58 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S3FCR DMA_S3FCR DMA stream 3 FIFO control register 0x6C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S3M0AR DMA_S3M0AR DMA stream 3 memory 0 address register 0x64 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S3M1AR DMA_S3M1AR DMA stream 3 memory 1 address register 0x68 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S3NDTR DMA_S3NDTR DMA stream 3 number of data register 0x5C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S3PAR DMA_S3PAR DMA stream 3 peripheral address register 0x60 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S4CR DMA_S4CR This register is used to configure the concerned stream. 0x70 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S4FCR DMA_S4FCR DMA stream 4 FIFO control register 0x84 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S4M0AR DMA_S4M0AR DMA stream 4 memory 0 address register 0x7C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S4M1AR DMA_S4M1AR DMA stream 4 memory 1 address register 0x80 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S4NDTR DMA_S4NDTR DMA stream 4 number of data register 0x74 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S4PAR DMA_S4PAR DMA stream 4 peripheral address register 0x78 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S5CR DMA_S5CR This register is used to configure the concerned stream. 0x88 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S5FCR DMA_S5FCR DMA stream 5 FIFO control register 0x9C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S5M0AR DMA_S5M0AR DMA stream 5 memory 0 address register 0x94 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S5M1AR DMA_S5M1AR DMA stream 5 memory 1 address register 0x98 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S5NDTR DMA_S5NDTR DMA stream 5 number of data register 0x8C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S5PAR DMA_S5PAR DMA stream 5 peripheral address register 0x90 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S6CR DMA_S6CR This register is used to configure the concerned stream. 0xA0 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S6FCR DMA_S6FCR DMA stream 6 FIFO control register 0xB4 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S6M0AR DMA_S6M0AR DMA stream 6 memory 0 address register 0xAC 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S6M1AR DMA_S6M1AR DMA stream 6 memory 1 address register 0xB0 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S6NDTR DMA_S6NDTR DMA stream 6 number of data register 0xA4 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S6PAR DMA_S6PAR DMA stream 6 peripheral address register 0xA8 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S7CR DMA_S7CR This register is used to configure the concerned stream. 0xB8 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S7FCR DMA_S7FCR DMA stream 7 FIFO control register 0xCC 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S7M0AR DMA_S7M0AR DMA stream 7 memory 0 address register 0xC4 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S7M1AR DMA_S7M1AR DMA stream 7 memory 1 address register 0xC8 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S7NDTR DMA_S7NDTR DMA stream 7 number of data register 0xBC 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S7PAR DMA_S7PAR DMA stream 7 peripheral address register 0xC0 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_SIDR DMA_SIDR DMA size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DMA_VERR DMA_VERR This register identifies the version of the IP. 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DMA2 DMA1 DMA1 0x0 0x0 0x400 registers n DMA_HIFCR DMA_HIFCR DMA high interrupt flag clear register 0xC 32 write-only n 0x0 0x0 CDMEIF4 CDMEIF4 2 1 CDMEIF5 CDMEIF5 8 1 CDMEIF6 CDMEIF6 18 1 CDMEIF7 CDMEIF7 24 1 CFEIF4 CFEIF4 0 1 CFEIF5 CFEIF5 6 1 CFEIF6 CFEIF6 16 1 CFEIF7 CFEIF7 22 1 CHTIF4 CHTIF4 4 1 CHTIF5 CHTIF5 10 1 CHTIF6 CHTIF6 20 1 CHTIF7 CHTIF7 26 1 CTCIF4 CTCIF4 5 1 CTCIF5 CTCIF5 11 1 CTCIF6 CTCIF6 21 1 CTCIF7 CTCIF7 27 1 CTEIF4 CTEIF4 3 1 CTEIF5 CTEIF5 9 1 CTEIF6 CTEIF6 19 1 CTEIF7 CTEIF7 25 1 DMA_HISR DMA_HISR DMA high interrupt status register 0x4 32 read-only n 0x0 0x0 DMEIF4 DMEIF4 2 1 DMEIF5 DMEIF5 8 1 DMEIF6 DMEIF6 18 1 DMEIF7 DMEIF7 24 1 FEIF4 FEIF4 0 1 FEIF5 FEIF5 6 1 FEIF6 FEIF6 16 1 FEIF7 FEIF7 22 1 HTIF4 HTIF4 4 1 HTIF5 HTIF5 10 1 HTIF6 HTIF6 20 1 HTIF7 HTIF7 26 1 TCIF4 TCIF4 5 1 TCIF5 TCIF5 11 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 27 1 TEIF4 TEIF4 3 1 TEIF5 TEIF5 9 1 TEIF6 TEIF6 19 1 TEIF7 TEIF7 25 1 DMA_HWCFGR1 DMA_HWCFGR1 DMA hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 DMA_DEF0 DMA_DEF0 0 2 DMA_DEF1 DMA_DEF1 4 2 DMA_DEF2 DMA_DEF2 8 2 DMA_DEF3 DMA_DEF3 12 2 DMA_DEF4 DMA_DEF4 16 2 DMA_DEF5 DMA_DEF5 20 2 DMA_DEF6 DMA_DEF6 24 2 DMA_DEF7 DMA_DEF7 28 2 DMA_HWCFGR2 DMA_HWCFGR2 DMA hardware configuration 2register 0x3EC 32 read-only n 0x0 0x0 CHSEL_WIDTH CHSEL_WIDTH 8 3 FIFO_SIZE FIFO_SIZE 0 2 WRITE_BUFFERABLE WRITE_BUFFERABLE 4 1 DMA_IPDR DMA_IPDR DMA IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DMA_LIFCR DMA_LIFCR DMA low interrupt flag clear register 0x8 32 write-only n 0x0 0x0 CDMEIF0 CDMEIF0 2 1 CDMEIF1 CDMEIF1 8 1 CDMEIF2 CDMEIF2 18 1 CDMEIF3 CDMEIF3 24 1 CFEIF0 CFEIF0 0 1 CFEIF1 CFEIF1 6 1 CFEIF2 CFEIF2 16 1 CFEIF3 CFEIF3 22 1 CHTIF0 CHTIF0 4 1 CHTIF1 CHTIF1 10 1 CHTIF2 CHTIF2 20 1 CHTIF3 CHTIF3 26 1 CTCIF0 CTCIF0 5 1 CTCIF1 CTCIF1 11 1 CTCIF2 CTCIF2 21 1 CTCIF3 CTCIF3 27 1 CTEIF0 CTEIF0 3 1 CTEIF1 CTEIF1 9 1 CTEIF2 CTEIF2 19 1 CTEIF3 CTEIF3 25 1 DMA_LISR DMA_LISR DMA low interrupt status register 0x0 32 read-only n 0x0 0x0 DMEIF0 DMEIF0 2 1 DMEIF1 DMEIF1 8 1 DMEIF2 DMEIF2 18 1 DMEIF3 DMEIF3 24 1 FEIF0 FEIF0 0 1 FEIF1 FEIF1 6 1 FEIF2 FEIF2 16 1 FEIF3 FEIF3 22 1 HTIF0 HTIF0 4 1 HTIF1 HTIF1 10 1 HTIF2 HTIF2 20 1 HTIF3 HTIF3 26 1 TCIF0 TCIF0 5 1 TCIF1 TCIF1 11 1 TCIF2 TCIF2 21 1 TCIF3 TCIF3 27 1 TEIF0 TEIF0 3 1 TEIF1 TEIF1 9 1 TEIF2 TEIF2 19 1 TEIF3 TEIF3 25 1 DMA_S0CR DMA_S0CR This register is used to configure the concerned stream. 0x10 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S0FCR DMA_S0FCR DMA stream 0 FIFO control register 0x24 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S0M0AR DMA_S0M0AR DMA stream 0 memory 0 address register 0x1C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S0M1AR DMA_S0M1AR DMA stream 0 memory 1 address register 0x20 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S0NDTR DMA_S0NDTR DMA stream 0 number of data register 0x14 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S0PAR DMA_S0PAR DMA stream 0 peripheral address register 0x18 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S1CR DMA_S1CR This register is used to configure the concerned stream. 0x28 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S1FCR DMA_S1FCR DMA stream 1 FIFO control register 0x3C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S1M0AR DMA_S1M0AR DMA stream 1 memory 0 address register 0x34 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S1M1AR DMA_S1M1AR DMA stream 1 memory 1 address register 0x38 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S1NDTR DMA_S1NDTR DMA stream 1 number of data register 0x2C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S1PAR DMA_S1PAR DMA stream 1 peripheral address register 0x30 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S2CR DMA_S2CR This register is used to configure the concerned stream. 0x40 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S2FCR DMA_S2FCR DMA stream 2 FIFO control register 0x54 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S2M0AR DMA_S2M0AR DMA stream 2 memory 0 address register 0x4C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S2M1AR DMA_S2M1AR DMA stream 2 memory 1 address register 0x50 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S2NDTR DMA_S2NDTR DMA stream 2 number of data register 0x44 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S2PAR DMA_S2PAR DMA stream 2 peripheral address register 0x48 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S3CR DMA_S3CR This register is used to configure the concerned stream. 0x58 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S3FCR DMA_S3FCR DMA stream 3 FIFO control register 0x6C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S3M0AR DMA_S3M0AR DMA stream 3 memory 0 address register 0x64 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S3M1AR DMA_S3M1AR DMA stream 3 memory 1 address register 0x68 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S3NDTR DMA_S3NDTR DMA stream 3 number of data register 0x5C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S3PAR DMA_S3PAR DMA stream 3 peripheral address register 0x60 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S4CR DMA_S4CR This register is used to configure the concerned stream. 0x70 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S4FCR DMA_S4FCR DMA stream 4 FIFO control register 0x84 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S4M0AR DMA_S4M0AR DMA stream 4 memory 0 address register 0x7C 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S4M1AR DMA_S4M1AR DMA stream 4 memory 1 address register 0x80 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S4NDTR DMA_S4NDTR DMA stream 4 number of data register 0x74 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S4PAR DMA_S4PAR DMA stream 4 peripheral address register 0x78 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S5CR DMA_S5CR This register is used to configure the concerned stream. 0x88 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S5FCR DMA_S5FCR DMA stream 5 FIFO control register 0x9C 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S5M0AR DMA_S5M0AR DMA stream 5 memory 0 address register 0x94 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S5M1AR DMA_S5M1AR DMA stream 5 memory 1 address register 0x98 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S5NDTR DMA_S5NDTR DMA stream 5 number of data register 0x8C 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S5PAR DMA_S5PAR DMA stream 5 peripheral address register 0x90 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S6CR DMA_S6CR This register is used to configure the concerned stream. 0xA0 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S6FCR DMA_S6FCR DMA stream 6 FIFO control register 0xB4 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S6M0AR DMA_S6M0AR DMA stream 6 memory 0 address register 0xAC 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S6M1AR DMA_S6M1AR DMA stream 6 memory 1 address register 0xB0 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S6NDTR DMA_S6NDTR DMA stream 6 number of data register 0xA4 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S6PAR DMA_S6PAR DMA stream 6 peripheral address register 0xA8 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_S7CR DMA_S7CR This register is used to configure the concerned stream. 0xB8 32 read-write n 0x0 0x0 CIRC CIRC 8 1 CT CT 19 1 DBM DBM 18 1 DIR DIR 6 2 DMEIE DMEIE 1 1 EN EN 0 1 HTIE HTIE 3 1 MBURST MBURST 23 2 MINC MINC 10 1 MSIZE MSIZE 13 2 PBURST PBURST 21 2 PFCTRL PFCTRL 5 1 PINC PINC 9 1 PINCOS PINCOS 15 1 PL PL 16 2 PSIZE PSIZE 11 2 TCIE TCIE 4 1 TEIE TEIE 2 1 DMA_S7FCR DMA_S7FCR DMA stream 7 FIFO control register 0xCC 32 read-write n 0x0 0x0 DMDIS DMDIS 2 1 read-write FEIE FEIE 7 1 read-write FS FS 3 3 read-only FTH FTH 0 2 read-write DMA_S7M0AR DMA_S7M0AR DMA stream 7 memory 0 address register 0xC4 32 read-write n 0x0 0x0 M0A M0A 0 32 DMA_S7M1AR DMA_S7M1AR DMA stream 7 memory 1 address register 0xC8 32 read-write n 0x0 0x0 M1A M1A 0 32 DMA_S7NDTR DMA_S7NDTR DMA stream 7 number of data register 0xBC 32 read-write n 0x0 0x0 NDT NDT 0 16 DMA_S7PAR DMA_S7PAR DMA stream 7 peripheral address register 0xC0 32 read-write n 0x0 0x0 PAR PAR 0 32 DMA_SIDR DMA_SIDR DMA size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DMA_VERR DMA_VERR This register identifies the version of the IP. 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DMAMUX1 DMAMUX1 DMAMUX1 0x0 0x0 0x400 registers n DMAMUX_C0CR DMAMUX_C0CR DMAMUX request line multiplexer channel 0 configuration register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C10CR DMAMUX_C10CR DMAMUX request line multiplexer channel 10 configuration register 0x28 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C11CR DMAMUX_C11CR DMAMUX request line multiplexer channel 11 configuration register 0x2C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C12CR DMAMUX_C12CR DMAMUX request line multiplexer channel 12 configuration register 0x30 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C13CR DMAMUX_C13CR DMAMUX request line multiplexer channel 13 configuration register 0x34 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C14CR DMAMUX_C14CR DMAMUX request line multiplexer channel 14 configuration register 0x38 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C15CR DMAMUX_C15CR DMAMUX request line multiplexer channel 15 configuration register 0x3C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C1CR DMAMUX_C1CR DMAMUX request line multiplexer channel 1 configuration register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C2CR DMAMUX_C2CR DMAMUX request line multiplexer channel 2 configuration register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C3CR DMAMUX_C3CR DMAMUX request line multiplexer channel 3 configuration register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C4CR DMAMUX_C4CR DMAMUX request line multiplexer channel 4 configuration register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C5CR DMAMUX_C5CR DMAMUX request line multiplexer channel 5 configuration register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C6CR DMAMUX_C6CR DMAMUX request line multiplexer channel 6 configuration register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C7CR DMAMUX_C7CR DMAMUX request line multiplexer channel 7 configuration register 0x1C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C8CR DMAMUX_C8CR DMAMUX request line multiplexer channel 8 configuration register 0x20 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_C9CR DMAMUX_C9CR DMAMUX request line multiplexer channel 9 configuration register 0x24 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 EGE EGE 9 1 NBREQ NBREQ 19 5 SE SE 16 1 SOIE SOIE 8 1 SPOL SPOL 17 2 SYNC_ID SYNC_ID 24 3 DMAMUX_CFR DMAMUX_CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 32 write-only n 0x0 0x0 CSOF0 CSOF0 0 1 CSOF1 CSOF1 1 1 CSOF10 CSOF10 10 1 CSOF11 CSOF11 11 1 CSOF12 CSOF12 12 1 CSOF13 CSOF13 13 1 CSOF14 CSOF14 14 1 CSOF15 CSOF15 15 1 CSOF2 CSOF2 2 1 CSOF3 CSOF3 3 1 CSOF4 CSOF4 4 1 CSOF5 CSOF5 5 1 CSOF6 CSOF6 6 1 CSOF7 CSOF7 7 1 CSOF8 CSOF8 8 1 CSOF9 CSOF9 9 1 DMAMUX_CSR DMAMUX_CSR DMAMUX request line multiplexer interrupt channel status register 0x80 32 read-only n 0x0 0x0 SOF0 SOF0 0 1 SOF1 SOF1 1 1 SOF10 SOF10 10 1 SOF11 SOF11 11 1 SOF12 SOF12 12 1 SOF13 SOF13 13 1 SOF14 SOF14 14 1 SOF15 SOF15 15 1 SOF2 SOF2 2 1 SOF3 SOF3 3 1 SOF4 SOF4 4 1 SOF5 SOF5 5 1 SOF6 SOF6 6 1 SOF7 SOF7 7 1 SOF8 SOF8 8 1 SOF9 SOF9 9 1 DMAMUX_HWCFGR1 DMAMUX_HWCFGR1 DMAMUX hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 NUM_DMA_PERIPH_REQ NUM_DMA_PERIPH_REQ 8 8 NUM_DMA_REQGEN NUM_DMA_REQGEN 24 8 NUM_DMA_STREAMS NUM_DMA_STREAMS 0 8 NUM_DMA_TRIG NUM_DMA_TRIG 16 8 DMAMUX_HWCFGR2 DMAMUX_HWCFGR2 DMAMUX hardware configuration 2 register 0x3EC 32 read-only n 0x0 0x0 NUM_DMA_EXT_REQ NUM_DMA_EXT_REQ 0 8 DMAMUX_IPIDR DMAMUX_IPIDR This register identifies the IP. 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 DMAMUX_RG0CR DMAMUX_RG0CR DMAMUX request generator channel 0 configuration register 0x100 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG1CR DMAMUX_RG1CR DMAMUX request generator channel 1 configuration register 0x104 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG2CR DMAMUX_RG2CR DMAMUX request generator channel 2 configuration register 0x108 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG3CR DMAMUX_RG3CR DMAMUX request generator channel 3 configuration register 0x10C 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG4CR DMAMUX_RG4CR DMAMUX request generator channel 4 configuration register 0x110 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG5CR DMAMUX_RG5CR DMAMUX request generator channel 5 configuration register 0x114 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG6CR DMAMUX_RG6CR DMAMUX request generator channel 6 configuration register 0x118 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RG7CR DMAMUX_RG7CR DMAMUX request generator channel 7 configuration register 0x11C 32 read-write n 0x0 0x0 GE GE 16 1 GNBREQ GNBREQ 19 5 GPOL GPOL 17 2 OIE OIE 8 1 SIG_ID SIG_ID 0 3 DMAMUX_RGCFR DMAMUX_RGCFR DMAMUX request generator interrupt clear flag register 0x144 32 write-only n 0x0 0x0 COF0 COF0 0 1 COF1 COF1 1 1 COF2 COF2 2 1 COF3 COF3 3 1 COF4 COF4 4 1 COF5 COF5 5 1 COF6 COF6 6 1 COF7 COF7 7 1 DMAMUX_RGSR DMAMUX_RGSR DMAMUX request generator interrupt status register 0x140 32 read-only n 0x0 0x0 OF0 OF0 0 1 OF1 OF1 1 1 OF2 OF2 2 1 OF3 OF3 3 1 OF4 OF4 4 1 OF5 OF5 5 1 OF6 OF6 6 1 OF7 OF7 7 1 DMAMUX_SIDR DMAMUX_SIDR DMAMUX size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 DMAMUX_VERR DMAMUX_VERR This register identifies the IP version. 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DTS DTS register block DTS 0x0 0x0 0x400 registers n CFGR1 DTS_CFGR1 DTS_CFGR1 is the configuration register for temperature sensor 1. 0x0 32 read-write n 0x0 0x0 HSREF_CLK_DIV HSREF_CLK_DIV 24 7 Q_MEAS_opt Q_MEAS_opt 21 1 REFCLK_SEL REFCLK_SEL 20 1 TS1_EN TS1_EN 0 1 TS1_INTRIG_SEL TS1_INTRIG_SEL 8 4 TS1_SMP_TIME TS1_SMP_TIME 16 4 TS1_START TS1_START 4 1 DR DTS_DR The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. 0x1C 32 read-write n 0x0 0x0 TS1_MFREQ TS1_MFREQ 0 16 ICIFR DTS_ICIFR DTS_ICIFR is the control register for the interrupt flags. 0x28 32 read-write n 0x0 0x0 TS1_CAITEF TS1_CAITEF 4 1 TS1_CAITHF TS1_CAITHF 6 1 TS1_CAITLF TS1_CAITLF 5 1 TS1_CITEF TS1_CITEF 0 1 TS1_CITHF TS1_CITHF 2 1 TS1_CITLF TS1_CITLF 1 1 ITENR DTS_ITENR Temperature sensor interrupt enable register 0x24 32 read-write n 0x0 0x0 TS1_AITEEN TS1_AITEEN 4 1 TS1_AITHEN TS1_AITHEN 6 1 TS1_AITLEN TS1_AITLEN 5 1 TS1_ITEEN TS1_ITEEN 0 1 TS1_ITHEN TS1_ITHEN 2 1 TS1_ITLEN TS1_ITLEN 1 1 ITR1 DTS_ITR1 DTS_ITR1 contains the threshold values for sensor 1. 0x14 32 read-write n 0x0 0x0 TS1_HITTHD TS1_HITTHD 16 16 TS1_LITTHD TS1_LITTHD 0 16 OR DTS_OR The DTS_OR contains general-purpose option bits. 0x2C 32 read-write n 0x0 0x0 TS_Op0 TS_Op0 0 1 TS_Op1 TS_Op1 1 1 TS_Op10 TS_Op10 10 1 TS_Op11 TS_Op11 11 1 TS_Op12 TS_Op12 12 1 TS_Op13 TS_Op13 13 1 TS_Op14 TS_Op14 14 1 TS_Op15 TS_Op15 15 1 TS_Op16 TS_Op16 16 1 TS_Op17 TS_Op17 17 1 TS_Op18 TS_Op18 18 1 TS_Op19 TS_Op19 19 1 TS_Op2 TS_Op2 2 1 TS_Op20 TS_Op20 20 1 TS_Op21 TS_Op21 21 1 TS_Op22 TS_Op22 22 1 TS_Op23 TS_Op23 23 1 TS_Op24 TS_Op24 24 1 TS_Op25 TS_Op25 25 1 TS_Op26 TS_Op26 26 1 TS_Op27 TS_Op27 27 1 TS_Op28 TS_Op28 28 1 TS_Op29 TS_Op29 29 1 TS_Op3 TS_Op3 3 1 TS_Op30 TS_Op30 30 1 TS_Op31 TS_Op31 31 1 TS_Op4 TS_Op4 4 1 TS_Op5 TS_Op5 5 1 TS_Op6 TS_Op6 6 1 TS_Op7 TS_Op7 7 1 TS_Op8 TS_Op8 8 1 TS_Op9 TS_Op9 9 1 RAMPVALR DTS_RAMPVALR The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. 0x10 32 read-only n 0x0 0x0 TS1_RAMP_COEFF TS1_RAMP_COEFF 0 16 SR DTS_SR Temperature sensor status register 0x20 32 read-only n 0x0 0x0 TS1_AITEF TS1_AITEF 4 1 TS1_AITHF TS1_AITHF 6 1 TS1_AITLF TS1_AITLF 5 1 TS1_ITEF TS1_ITEF 0 1 TS1_ITHF TS1_ITHF 2 1 TS1_ITLF TS1_ITLF 1 1 TS1_RDY TS1_RDY 15 1 T0VALR1 DTS_T0VALR1 DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. 0x8 32 read-only n 0x0 0x0 TS1_FMT0 TS1_FMT0 0 16 TS1_T0 TS1_T0 16 2 ETH_DMA ETH_DMA Ethernet 0x0 0x0 0x400 registers n ETH_DMAA4DACR ETH_DMAA4DACR AXI4 descriptor ACE control register 0x28 32 read-write n 0x0 0x0 RDP RDP 16 3 RDRC RDRC 8 4 TDWC TDWC 0 4 TDWD TDWD 4 2 WRP WRP 20 3 ETH_DMAA4RxACR ETH_DMAA4RxACR AXI4 receive channel ACE control register 0x24 32 read-write n 0x0 0x0 RDC RDC 24 2 RDWC RDWC 0 4 RHC RHC 16 4 RPC RPC 8 4 ETH_DMAA4TxACR ETH_DMAA4TxACR AXI4 transmit channel ACE control register 0x20 32 read-write n 0x0 0x0 TDRC TDRC 0 4 TEC TEC 8 4 THC THC 16 4 ETH_DMAC0CARxBR ETH_DMACCARxBR Channel current application receive buffer register 0x15C 32 read-only n 0x0 0x0 CURRBUFAPTR Application Receive Buffer Address Pointer 0 32 ETH_DMAC0CARxDR ETH_DMAC0CARxDR Channel 0 current application receive descriptor register DMAC1CATxDR 0x14C 32 read-only n 0x0 0x0 CURRDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC0CATxBR ETH_DMAC0CATxBR Channel 0 current application transmit buffer register 0x154 32 read-only n 0x0 0x0 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 ETH_DMAC0CATxDR ETH_DMAC0CATxDR Channel current application transmit descriptor register 0x144 32 read-only n 0x0 0x0 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC0CR ETH_DMAC0CR Channel 0 control register 0x100 32 read-write n 0x0 0x0 DSL DSL 18 3 MSS MSS 0 14 PBLX8 PBLX8 16 1 ETH_DMAC0IER ETH_DMACIER Channel interrupt enable register 0x134 32 read-write n 0x0 0x0 AIE Abnormal Interrupt Summary Enable 14 1 CDEE Context Descriptor Error Enable 13 1 ERIE Early Receive Interrupt Enable 11 1 ETIE Early Transmit Interrupt Enable 10 1 FBEE Fatal Bus Error Enable 12 1 NIE Normal Interrupt Summary Enable 15 1 RBUE Receive Buffer Unavailable Enable 7 1 RIE Receive Interrupt Enable 6 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 TBUE Transmit Buffer Unavailable Enable 2 1 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 ETH_DMAC0MFCR ETH_DMAC0MFCR Channel missed frame count register 0x16C 32 read-only n 0x0 0x0 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 ETH_DMAC0RxCR ETH_DMAC0RxCR Channel receive control register 0x108 32 read-write n 0x0 0x0 RBSZ Receive Buffer size 1 14 RPF DMA Rx Channel Packet Flush 31 1 RQOS RQOS 24 4 RXPBL RXPBL 16 6 SR Start or Stop Receive Command 0 1 ETH_DMAC0RxDLAR ETH_DMAC0RxDLAR Channel Rx descriptor list address register 0x11C 32 read-write n 0x0 0x0 RDESLA Start of Receive List 3 29 ETH_DMAC0RxDTPR ETH_DMAC0RxDTPR Channel Rx descriptor tail pointer register 0x128 32 read-write n 0x0 0x0 RDT Receive Descriptor Tail Pointer 3 29 ETH_DMAC0RxIWTR ETH_DMAC0RxIWTR Channel Rx interrupt watchdog timer register 0x138 32 read-write n 0x0 0x0 RWT Receive Interrupt Watchdog Timer Count 0 8 ETH_DMAC0RxRLR ETH_DMAC0RxRLR Channel Rx descriptor ring length register 0x130 32 read-write n 0x0 0x0 RDRL Receive Descriptor Ring Length 0 10 ETH_DMAC0SFCSR ETH_DMAC0SFCSR Channel i slot function control status register 0x13C 32 read-write n 0x0 0x0 ASC ASC 1 1 ESC ESC 0 1 RSN RSN 16 4 ETH_DMAC0SR ETH_DMAC0SR Channel status register 0x160 32 read-write n 0x0 0x0 AIS Abnormal Interrupt Summary 14 1 CDE Context Descriptor Error 13 1 ERI Early Receive Interrupt 11 1 ETI Early Transmit Interrupt 10 1 FBE Fatal Bus Error 12 1 NIS Normal Interrupt Summary 15 1 RBU Receive Buffer Unavailable 7 1 REB Rx DMA Error Bits 19 3 RI Receive Interrupt 6 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 TBU Transmit Buffer Unavailable 2 1 TEB Tx DMA Error Bits 16 3 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 ETH_DMAC0TxCR ETH_DMAC0TxCR Channel 0 transmit control register 0x104 32 read-write n 0x0 0x0 OSF OSF 4 1 ST ST 0 1 TCW TCW 1 3 TQOS TQOS 24 4 TSE TSE 12 1 TXPBL TXPBL 16 6 ETH_DMAC0TxDLAR ETH_DMAC0TxDLAR Channel i Tx descriptor list address register 0x114 32 read-write n 0x0 0x0 TDESLA Start of Transmit List 3 29 ETH_DMAC0TxDTPR ETH_DMAC0TxDTPR Channel Tx descriptor tail pointer register 0x120 32 read-write n 0x0 0x0 TDT Transmit Descriptor Tail Pointer 3 29 ETH_DMAC0TxRLR ETH_DMAC0TxRLR Channel Tx descriptor ring length register 0x12C 32 read-write n 0x0 0x0 TDRL Transmit Descriptor Ring Length 0 10 ETH_DMAC1CATxBR ETH_DMAC1CATxBR Channel 0 current application transmit buffer register 0x1D4 32 read-only n 0x0 0x0 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 ETH_DMAC1CATxDR ETH_DMAC1CATxDR Channel current application transmit descriptor register 0x1C4 32 read-only n 0x0 0x0 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC1CR ETH_DMAC1CR Channel 1 control register 0x180 32 read-write n 0x0 0x0 DSL DSL 18 3 MSS MSS 0 14 PBLX8 PBLX8 16 1 ETH_DMAC1IER ETH_DMAC1IER Channel interrupt enable register 0x1B4 32 read-write n 0x0 0x0 AIE Abnormal Interrupt Summary Enable 14 1 CDEE Context Descriptor Error Enable 13 1 ERIE Early Receive Interrupt Enable 11 1 ETIE Early Transmit Interrupt Enable 10 1 FBEE Fatal Bus Error Enable 12 1 NIE Normal Interrupt Summary Enable 15 1 RBUE Receive Buffer Unavailable Enable 7 1 RIE Receive Interrupt Enable 6 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 TBUE Transmit Buffer Unavailable Enable 2 1 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 ETH_DMAC1MFCR ETH_DMAC1MFCR Channel missed frame count register 0x1EC 32 read-only n 0x0 0x0 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 ETH_DMAC1SFCSR ETH_DMAC1SFCSR Channel i slot function control status register 0x1BC 32 read-write n 0x0 0x0 ASC ASC 1 1 ESC ESC 0 1 RSN RSN 16 4 ETH_DMAC1SR ETH_DMAC1SR Channel status register 0x1E0 32 read-write n 0x0 0x0 AIS Abnormal Interrupt Summary 14 1 CDE Context Descriptor Error 13 1 ERI Early Receive Interrupt 11 1 ETI Early Transmit Interrupt 10 1 FBE Fatal Bus Error 12 1 NIS Normal Interrupt Summary 15 1 RBU Receive Buffer Unavailable 7 1 REB Rx DMA Error Bits 19 3 RI Receive Interrupt 6 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 TBU Transmit Buffer Unavailable 2 1 TEB Tx DMA Error Bits 16 3 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 ETH_DMAC1TxCR ETH_DMAC1TxCR Channel 1 transmit control register 0x184 32 read-write n 0x0 0x0 OSF OSF 4 1 ST ST 0 1 TCW TCW 1 3 TQOS TQOS 24 4 TSE TSE 12 1 TXPBL TXPBL 16 6 ETH_DMAC1TxDLAR ETH_DMAC1TxDLAR Channel i Tx descriptor list address register 0x194 32 read-write n 0x0 0x0 TDESLA Start of Transmit List 3 29 ETH_DMAC1TxDTPR ETH_DMAC1TxDTPR Channel Tx descriptor tail pointer register 0x1A0 32 read-write n 0x0 0x0 TDT Transmit Descriptor Tail Pointer 3 29 ETH_DMAC1TxRLR ETH_DMAC1TxRLR Channel Tx descriptor ring length register 0x1AC 32 read-write n 0x0 0x0 TDRL Transmit Descriptor Ring Length 0 10 ETH_DMADSR ETH_DMADSR Debug status register 0xC 32 read-only n 0x0 0x0 AXRHSTS AXRHSTS 1 1 AXWHSTS AHB Master Write Channel 0 1 RPS0 RPS0 8 4 RPS1 RPS1 16 4 TPS0 TPS0 12 4 TPS1 TPS1 20 4 ETH_DMAISR ETH_DMAISR Interrupt status register 0x8 32 read-only n 0x0 0x0 DC0IS DMA Channel Interrupt Status 0 1 DC1IS DC1IS 1 1 MACIS MAC Interrupt Status 17 1 MTLIS MTL Interrupt Status 16 1 ETH_DMAMR ETH_DMAMR DMA mode register 0x0 32 read-write n 0x0 0x0 INTM Interrupt Mode 16 2 PR Priority ratio 12 3 SWR Software Reset 0 1 TAA TAA 2 3 TXPR Transmit priority 11 1 ETH_DMASBMR ETH_DMASBMR System bus mode register 0x4 32 read-write n 0x0 0x0 AAL Address-Aligned Beats 12 1 BLEN128 BLEN128 6 1 BLEN16 BLEN16 3 1 BLEN256 BLEN256 7 1 BLEN32 BLEN32 4 1 BLEN4 BLEN4 1 1 BLEN64 BLEN64 5 1 BLEN8 BLEN8 2 1 EN_LPI EN_LPI 31 1 FB Fixed Burst Length 0 1 LPI_XIT_PKT LPI_XIT_PKT 30 1 ONEKBBE ONEKBBE 13 1 RD_OSR_LMT RD_OSR_LMT 16 2 WR_OSR_LMT WR_OSR_LMT 24 2 ETH_MAC_MMC ETH_MAC_MMC Ethernet 0x0 0x0 0xBD4 registers n ETH_MAC1USTCR ETH_MAC1USTCR This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially. 0xDC 32 read-write n 0x0 0x0 TIC_1US_CNTR TIC_1US_CNTR 0 12 read-write ETH_MACA0HR ETH_MACA0HR The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. 0x300 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-only ETH_MACA0LR ETH_MACA0LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x304 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA1HR ETH_MACA1HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x308 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA1LR ETH_MACA1LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x30C 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA2HR ETH_MACA2HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x310 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA2LR ETH_MACA2LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x314 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA3HR ETH_MACA3HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x318 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA3LR ETH_MACA3LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x31C 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACACR ETH_MACACR The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot. 0xB40 32 read-write n 0x0 0x0 ATSEN0 ATSEN0 4 1 read-write ATSEN1 ATSEN1 5 1 read-write ATSEN2 ATSEN2 6 1 read-write ATSEN3 ATSEN3 7 1 read-write ATSFC ATSFC 0 1 read-write ETH_MACARPAR ETH_MACARPAR The ARP Address register contains the IPv4 Destination Address of the MAC. 0xAE0 32 read-write n 0x0 0x0 ARPPA ARPPA 0 32 read-write ETH_MACATSNR ETH_MACATSNR The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read. 0xB48 32 read-only n 0x0 0x0 AUXTSLO AUXTSLO 0 31 read-only ETH_MACATSSR ETH_MACATSSR The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register. 0xB4C 32 read-only n 0x0 0x0 AUXTSHI AUXTSHI 0 32 read-only ETH_MACCR ETH_MACCR The MAC Configuration Register establishes the operating mode of the MAC. 0x0 32 read-write n 0x0 0x0 ACS ACS 20 1 read-write ARPEN ARPEN 31 1 read-write BE BE 18 1 read-write BL BL 5 2 read-write CST CST 21 1 read-write DC DC 4 1 read-write DCRS DCRS 9 1 read-write DM DM 13 1 read-write DO DO 10 1 read-write DR DR 8 1 read-write ECRSFD ECRSFD 11 1 read-write FES FES 14 1 read-write GPSLCE GPSLCE 23 1 read-write IPC IPC 27 1 read-write IPG IPG 24 3 read-write JD JD 17 1 read-write JE JE 16 1 read-write LM LM 12 1 read-write PRELEN PRELEN 2 2 read-write PS PS 15 1 read-write RE RE 0 1 read-write S2KP S2KP 22 1 read-write SARC SARC 28 3 read-write TE TE 1 1 read-write WD WD 19 1 read-write ETH_MACDR ETH_MACDR The Debug register provides the debug status of various MAC blocks. 0x114 32 read-only n 0x0 0x0 RFCFCSTS RFCFCSTS 1 2 read-only RPESTS RPESTS 0 1 read-only TFCSTS TFCSTS 17 2 read-only TPESTS TPESTS 16 1 read-only ETH_MACECR ETH_MACECR The MAC Extended Configuration Register establishes the operating mode of the MAC. 0x4 32 read-write n 0x0 0x0 DCRCC DCRCC 16 1 read-write EIPG EIPG 25 5 read-write EIPGEN EIPGEN 24 1 read-write GPSL GPSL 0 14 read-write SPEN SPEN 17 1 read-write USP USP 18 1 read-write ETH_MACHT0R ETH_MACHT0R The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x10 32 read-write n 0x0 0x0 HT31T0 HT31T0 0 32 read-write ETH_MACHT1R ETH_MACHT1R The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x14 32 read-write n 0x0 0x0 HT63T32 HT63T32 0 32 read-write ETH_MACHWF1R ETH_MACHWF1R This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x120 32 read-only n 0x0 0x0 ADDR64 ADDR64 14 2 read-only ADVTHWORD ADVTHWORD 13 1 read-only AVSEL AVSEL 20 1 read-only DBGMEMA DBGMEMA 19 1 read-only DCBEN DCBEN 16 1 read-only HASHTBLSZ HASHTBLSZ 24 2 read-only L3L4FNUM L3L4FNUM 27 4 read-only OSTEN OSTEN 11 1 read-only PTOEN PTOEN 12 1 read-only RXFIFOSIZE RXFIFOSIZE 0 5 read-only SPHEN SPHEN 17 1 read-only TSOEN TSOEN 18 1 read-only TXFIFOSIZE TXFIFOSIZE 6 5 read-only ETH_MACHWF2R ETH_MACHWF2R This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x124 32 read-only n 0x0 0x0 AUXSNAPNUM AUXSNAPNUM 28 3 read-only PPSOUTNUM PPSOUTNUM 24 3 read-only RXCHCNT RXCHCNT 12 4 read-only RXQCNT RXQCNT 0 4 read-only TXCHCNT TXCHCNT 18 4 read-only TXQCNT TXQCNT 6 4 read-only ETH_MACIER ETH_MACIER The Interrupt Enable register contains the masks for generating the interrupts. 0xB4 32 read-write n 0x0 0x0 LPIIE LPIIE 5 1 read-write PHYIE PHYIE 3 1 read-write PMTIE PMTIE 4 1 read-write RGSMIIIE RGSMIIIE 0 1 read-write RXSTSIE RXSTSIE 14 1 read-write TSIE TSIE 12 1 read-write TXSTSIE TXSTSIE 13 1 read-write ETH_MACISR ETH_MACISR The Interrupt Status register contains the status of interrupts. 0xB0 32 read-only n 0x0 0x0 LPIIS LPIIS 5 1 read-only MMCIS MMCIS 8 1 read-only MMCRXIS MMCRXIS 9 1 read-only MMCTXIS MMCTXIS 10 1 read-only PHYIS PHYIS 3 1 read-only PMTIS PMTIS 4 1 read-only RGSMIIIS RGSMIIIS 0 1 read-only RXSTSIS RXSTSIS 14 1 read-only TSIS TSIS 12 1 read-only TXSTSIS TXSTSIS 13 1 read-only ETH_MACIVIR ETH_MACIVIR The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls. 0x64 32 read-write n 0x0 0x0 CSVL CSVL 19 1 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write VLT VLT 0 16 read-write VLTI VLTI 20 1 read-write ETH_MACL3A00R ETH_MACL3A00R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x910 32 read-write n 0x0 0x0 L3A00 L3A00 0 32 read-write ETH_MACL3A01R ETH_MACL3A01R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x940 32 read-write n 0x0 0x0 L3A01 L3A01 0 32 read-write ETH_MACL3A10R ETH_MACL3A10R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x914 32 read-write n 0x0 0x0 L3A10 L3A10 0 32 read-write ETH_MACL3A11R ETH_MACL3A11R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x944 32 read-write n 0x0 0x0 L3A11 L3A11 0 32 read-write ETH_MACL3A20 ETH_MACL3A20 The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x918 32 read-write n 0x0 0x0 L3A20 L3A20 0 32 read-write ETH_MACL3A21R ETH_MACL3A21R The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x948 32 read-write n 0x0 0x0 L3A21 L3A21 0 32 read-write ETH_MACL3A30 ETH_MACL3A30 The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x91C 32 read-write n 0x0 0x0 L3A30 L3A30 0 32 read-write ETH_MACL3A31R ETH_MACL3A31R The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x94C 32 read-write n 0x0 0x0 L3A31 L3A31 0 32 read-write ETH_MACL3L4C0R ETH_MACL3L4C0R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration. 0x900 32 read-write n 0x0 0x0 L3DAIM0 L3DAIM0 5 1 read-write L3DAM0 L3DAM0 4 1 read-write L3HDBM0 L3HDBM0 11 5 read-write L3HSBM0 L3HSBM0 6 5 read-write L3PEN0 L3PEN0 0 1 read-write L3SAIM0 L3SAIM0 3 1 read-write L3SAM0 L3SAM0 2 1 read-write L4DPIM0 L4DPIM0 21 1 read-write L4DPM0 L4DPM0 20 1 read-write L4PEN0 L4PEN0 16 1 read-write L4SPIM0 L4SPIM0 19 1 read-write L4SPM0 L4SPM0 18 1 read-write ETH_MACL3L4C1R ETH_MACL3L4C1R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. 0x930 32 read-write n 0x0 0x0 L3DAIM1 L3DAIM1 5 1 read-write L3DAM1 L3DAM1 4 1 read-write L3HDBM1 L3HDBM1 11 5 read-write L3HSBM1 L3HSBM1 6 5 read-write L3PEN1 L3PEN1 0 1 read-write L3SAIM1 L3SAIM1 3 1 read-write L3SAM1 L3SAM1 2 1 read-write L4DPIM1 L4DPIM1 21 1 read-write L4DPM1 L4DPM1 20 1 read-write L4PEN1 L4PEN1 16 1 read-write L4SPIM1 L4SPIM1 19 1 read-write L4SPM1 L4SPM1 18 1 read-write ETH_MACL4A0R ETH_MACL4A0R Layer4 address filter 0 register 0x904 32 read-write n 0x0 0x0 L4DP0 L4DP0 16 16 read-write L4SP0 L4SP0 0 16 read-write ETH_MACL4A1R ETH_MACL4A1R The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock. 0x934 32 read-write n 0x0 0x0 L4DP1 L4DP1 16 16 read-write L4SP1 L4SP1 0 16 read-write ETH_MACLCSR ETH_MACLCSR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xD0 32 read-write n 0x0 0x0 LPIEN LPIEN 16 1 read-write LPITE LPITE 20 1 read-write LPITXA LPITXA 19 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only RLPIST RLPIST 9 1 read-only TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only TLPIST TLPIST 8 1 read-only ETH_MACLETR ETH_MACLETR The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds. 0xD8 32 read-write n 0x0 0x0 LPIET LPIET 3 17 read-write ETH_MACLMIR ETH_MACLMIR This register contains the periodic intervals for automatic PTP packet generation. 0xBD0 32 read-write n 0x0 0x0 DRSYNCR DRSYNCR 8 3 read-write LMPDRI LMPDRI 24 8 read-write LSI LSI 0 8 read-write ETH_MACLTCR ETH_MACLTCR The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. 0xD4 32 read-write n 0x0 0x0 LST LST 16 10 read-write TWT TWT 0 16 read-write ETH_MACMDIOAR ETH_MACMDIOAR The MDIO Address register controls the management cycles to external PHY through a management interface. 0x200 32 read-write n 0x0 0x0 BTB BTB 26 1 read-write C45E C45E 1 1 read-write CR CR 8 4 read-write GB GB 0 1 read-write GOC GOC 2 2 read-write NTC NTC 12 3 read-write PA PA 21 5 read-write PSE PSE 27 1 read-write RDA RDA 16 5 read-write SKAP SKAP 4 1 read-write ETH_MACMDIODR ETH_MACMDIODR The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register. 0x204 32 read-write n 0x0 0x0 GD GD 0 16 read-write RA RA 16 16 read-write ETH_MACPCSR ETH_MACPCSR The PMT Control and Status Register is present only when you select the PMT module in coreConsultant. 0xC0 32 read-write n 0x0 0x0 GLBLUCAST GLBLUCAST 9 1 read-write MGKPKTEN MGKPKTEN 1 1 read-write MGKPRCVD MGKPRCVD 5 1 read-only PWRDWN PWRDWN 0 1 read-write RWKFILTRST RWKFILTRST 31 1 read-write RWKPFE RWKPFE 10 1 read-write RWKPKTEN RWKPKTEN 2 1 read-write RWKPRCVD RWKPRCVD 6 1 read-only RWKPTR RWKPTR 24 5 read-only ETH_MACPFR ETH_MACPFR The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets. 0x8 32 read-write n 0x0 0x0 DAIF DAIF 3 1 read-write DBF DBF 5 1 read-write DNTU DNTU 21 1 read-write HMC HMC 2 1 read-write HPF HPF 10 1 read-write HUC HUC 1 1 read-write IPFE IPFE 20 1 read-write PCF PCF 6 2 read-write PM PM 4 1 read-write PR PR 0 1 read-write RA RA 31 1 read-write SAF SAF 9 1 read-write SAIF SAIF 8 1 read-write VTFE VTFE 16 1 read-write ETH_MACPHYCSR ETH_MACPHYCSR The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY. 0xF8 32 read-write n 0x0 0x0 FALSCARDET FALSCARDET 21 1 read-only JABTO JABTO 20 1 read-only LNKMOD LNKMOD 16 1 read-only LNKSPEED LNKSPEED 17 2 read-only LNKSTS LNKSTS 19 1 read-only LUD LUD 1 1 read-write TC TC 0 1 read-write ETH_MACPOCR ETH_MACPOCR This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC0 32 read-write n 0x0 0x0 APDREQEN APDREQEN 2 1 read-write APDREQTRIG APDREQTRIG 5 1 read-write ASYNCEN ASYNCEN 1 1 read-write ASYNCTRIG ASYNCTRIG 4 1 read-write DN DN 8 8 read-write DRRDIS DRRDIS 6 1 read-write PTOEN PTOEN 0 1 read-write ETH_MACPPSCR ETH_MACPPSCR The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected. 0xB70 32 read-write n 0x0 0x0 PPSCTRL PPSCTRL 0 4 read-write PPSEN0 PPSEN0 4 1 read-write TRGTMODSEL0 TRGTMODSEL0 5 2 read-write ETH_MACPPSIR ETH_MACPPSIR The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]). 0xB88 32 read-write n 0x0 0x0 PPSINT0 PPSINT0 0 32 read-write ETH_MACPPSTTNR ETH_MACPPSTTNR The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected. 0xB84 32 read-write n 0x0 0x0 TRGTBUSY0 TRGTBUSY0 31 1 read-write TTSL0 TTSL0 0 31 read-write ETH_MACPPSTTSR ETH_MACPPSTTSR The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers. 0xB80 32 read-write n 0x0 0x0 TSTRH0 TSTRH0 0 32 read-write ETH_MACPPSWR ETH_MACPPSWR The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o). 0xB8C 32 read-write n 0x0 0x0 PPSWIDTH0 PPSWIDTH0 0 32 read-write ETH_MACQ0TxFCR ETH_MACQ0TxFCR The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register. 0x70 32 read-write n 0x0 0x0 DZPQ DZPQ 7 1 read-write FCB_BPA FCB_BPA 0 1 read-write PLT PLT 4 3 read-write PT PT 16 16 read-write TFE TFE 1 1 read-write ETH_MACRWKPFR ETH_MACRWKPFR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xC4 32 read-write n 0x0 0x0 LPIEN LPIEN 16 1 read-write LPITE LPITE 20 1 read-write LPITXA LPITXA 19 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only RLPIST RLPIST 9 1 read-only TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only TLPIST TLPIST 8 1 read-only ETH_MACRxFCR ETH_MACRxFCR The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet. 0x90 32 read-write n 0x0 0x0 RFE RFE 0 1 read-write UP UP 1 1 read-write ETH_MACRxQC0R ETH_MACRxQC0R The Receive Queue Control 0 register controls the queue management in the MAC Receiver. 0xA0 32 read-write n 0x0 0x0 RXQ0EN RXQ0EN 0 2 read-write RXQ1EN RXQ1EN 2 2 read-write ETH_MACRxQC1R ETH_MACRxQC1R The Receive Queue Control 1 register controls queue 1 management in the MAC receiver. 0xA4 32 read-write n 0x0 0x0 AVCPQ AVCPQ 0 3 read-write AVPTPQ AVPTPQ 4 3 read-write MCBCQ MCBCQ 16 3 read-write MCBCQEN MCBCQEN 20 1 read-write TACPQE TACPQE 21 1 read-write UPQ UPQ 12 3 read-write ETH_MACRxQC2R ETH_MACRxQC2R This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1. 0xA8 32 read-write n 0x0 0x0 PSRQ0 PSRQ0 0 8 read-write PSRQ1 PSRQ1 8 8 read-write ETH_MACRxTxSR ETH_MACRxTxSR The Receive Transmit Status register contains the Receive and Transmit Error status. 0xB8 32 read-only n 0x0 0x0 EXCOL EXCOL 5 1 read-only EXDEF EXDEF 3 1 read-only LCARR LCARR 2 1 read-only LCOL LCOL 4 1 read-only NCARR NCARR 1 1 read-only RWT RWT 8 1 read-only TJT TJT 0 1 read-only ETH_MACSPI0R ETH_MACSPI0R This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC4 32 read-write n 0x0 0x0 SPI0 SPI0 0 32 read-write ETH_MACSPI1R ETH_MACSPI1R This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC8 32 read-write n 0x0 0x0 SPI1 SPI1 0 32 read-write ETH_MACSPI2R ETH_MACSPI2R This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. 0xBCC 32 read-write n 0x0 0x0 SPI2 SPI2 0 16 read-write ETH_MACSSIR ETH_MACSSIR The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. 0xB04 32 read-write n 0x0 0x0 SNSINC SNSINC 8 8 read-write SSINC SSINC 16 8 read-write ETH_MACSTNR ETH_MACSTNR The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB0C 32 read-only n 0x0 0x0 TSSS TSSS 0 31 read-only ETH_MACSTNUR ETH_MACSTNUR This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input. 0xB14 32 read-write n 0x0 0x0 ADDSUB ADDSUB 31 1 read-write TSSS TSSS 0 31 read-write ETH_MACSTSR ETH_MACSTSR The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB08 32 read-only n 0x0 0x0 TSS TSS 0 32 read-only ETH_MACSTSUR ETH_MACSTSUR The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB10 32 read-write n 0x0 0x0 TSS TSS 0 32 read-write ETH_MACTSAR ETH_MACTSAR The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows. 0xB18 32 read-write n 0x0 0x0 TSAR TSAR 0 32 read-write ETH_MACTSCR ETH_MACTSCR This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver. 0xB00 32 read-write n 0x0 0x0 AV8021ASMEN AV8021ASMEN 28 1 read-write CSC CSC 19 1 read-only SNAPTYPSEL SNAPTYPSEL 16 2 read-write TSADDREG TSADDREG 5 1 read-write TSCFUPDT TSCFUPDT 1 1 read-write TSCTRLSSR TSCTRLSSR 9 1 read-write TSENA TSENA 0 1 read-write TSENALL TSENALL 8 1 read-write TSENMACADDR TSENMACADDR 18 1 read-write TSEVNTENA TSEVNTENA 14 1 read-write TSINIT TSINIT 2 1 read-write TSIPENA TSIPENA 11 1 read-write TSIPV4ENA TSIPV4ENA 13 1 read-write TSIPV6ENA TSIPV6ENA 12 1 read-write TSMSTRENA TSMSTRENA 15 1 read-write TSUPDT TSUPDT 3 1 read-write TSVER2ENA TSVER2ENA 10 1 read-write TXTSSTSM TXTSSTSM 24 1 read-write ETH_MACTSEACR ETH_MACTSEACR The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages. 0xB54 32 read-write n 0x0 0x0 OSTEAC OSTEAC 0 32 read-write ETH_MACTSECNR ETH_MACTSECNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path. 0xB5C 32 read-write n 0x0 0x0 TSEC TSEC 0 32 read-write ETH_MACTSIACR ETH_MACTSIACR The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages. 0xB50 32 read-write n 0x0 0x0 OSTIAC OSTIAC 0 32 read-write ETH_MACTSICNR ETH_MACTSICNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path. 0xB58 32 read-write n 0x0 0x0 TSIC TSIC 0 32 read-write ETH_MACTSSR ETH_MACTSSR The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register. 0xB20 32 read-only n 0x0 0x0 ATSNS ATSNS 25 5 read-only ATSSTM ATSSTM 24 1 read-only ATSSTN ATSSTN 16 4 read-only AUXTSTRIG AUXTSTRIG 2 1 read-only TSSOVF TSSOVF 0 1 read-only TSTARGT0 TSTARGT0 1 1 read-only TSTRGTERR0 TSTRGTERR0 3 1 read-only TXTSSIS TXTSSIS 15 1 read-only ETH_MACTxQPMR ETH_MACTxQPMR The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1. 0x98 32 read-only n 0x0 0x0 PSTQ0 PSTQ0 0 8 read-only PSTQ1 PSTQ1 8 8 read-only ETH_MACTxTSSNR ETH_MACTxTSSNR This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. 0xB30 32 read-only n 0x0 0x0 TXTSSLO TXTSSLO 0 31 read-only TXTSSMIS TXTSSMIS 31 1 read-only ETH_MACTxTSSSR ETH_MACTxTSSSR The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted. 0xB34 32 read-only n 0x0 0x0 TXTSSHI TXTSSHI 0 32 read-only ETH_MACVHTR ETH_MACVHTR When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. 0x58 32 read-write n 0x0 0x0 VLHT VLHT 0 16 read-write ETH_MACVIR ETH_MACVIR The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls. 0x60 32 read-write n 0x0 0x0 CSVL CSVL 19 1 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write VLT VLT 0 16 read-write VLTI VLTI 20 1 read-write ETH_MACVR ETH_MACVR The version register identifies the version of the Ethernet peripheral. 0x110 32 read-only n 0x0 0x0 SNPSVER SNPSVER 0 8 read-only USERVER USERVER 8 8 read-only ETH_MACVTR ETH_MACVTR The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets. 0x50 32 read-write n 0x0 0x0 DOVLTC DOVLTC 20 1 read-write EDVLP EDVLP 26 1 read-write EIVLRXS EIVLRXS 31 1 read-write EIVLS EIVLS 28 2 read-write ERIVLT ERIVLT 27 1 read-write ERSVLM ERSVLM 19 1 read-write ESVL ESVL 18 1 read-write ETV ETV 16 1 read-write EVLRXS EVLRXS 24 1 read-write EVLS EVLS 21 2 read-write VL VL 0 16 read-write VTHM VTHM 25 1 read-write VTIM VTIM 17 1 read-write ETH_MACWTR ETH_MACWTR The Watchdog Timeout register controls the watchdog timeout for received packets. 0xC 32 read-write n 0x0 0x0 PWE PWE 8 1 read-write WTO WTO 0 4 read-write MMC_CONTROL MMC_CONTROL This register configures the MMC operating mode. 0x700 32 read-write n 0x0 0x0 CNTFREEZ CNTFREEZ 3 1 read-write CNTPRST CNTPRST 4 1 read-write CNTPRSTLVL CNTPRSTLVL 5 1 read-write CNTRST CNTRST 0 1 read-write CNTSTOPRO CNTSTOPRO 1 1 read-write RSTONRD RSTONRD 2 1 read-write UCDBC UCDBC 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x704 32 read-only n 0x0 0x0 RXALGNERPIS RXALGNERPIS 6 1 read-only RXCRCERPIS RXCRCERPIS 5 1 read-only RXLPITRCIS RXLPITRCIS 27 1 read-only RXLPIUSCIS RXLPIUSCIS 26 1 read-only RXUCGPIS RXUCGPIS 17 1 read-only MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values. 0x70C 32 read-write n 0x0 0x0 RXALGNERPIM RXALGNERPIM 6 1 read-write RXCRCERPIM RXCRCERPIM 5 1 read-write RXLPITRCIM RXLPITRCIM 27 1 read-only RXLPIUSCIM RXLPIUSCIM 26 1 read-write RXUCGPIM RXUCGPIM 17 1 read-write MMC_TX_INTERRUPT MMC_TX_INTERRUPT This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x708 32 read-only n 0x0 0x0 TXGPKTIS TXGPKTIS 21 1 read-only TXLPITRCIS TXLPITRCIS 27 1 read-only TXLPIUSCIS TXLPIUSCIS 26 1 read-only TXMCOLGPIS TXMCOLGPIS 15 1 read-only TXSCOLGPIS TXSCOLGPIS 14 1 read-only MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration. 0x710 32 read-write n 0x0 0x0 TXGPKTIM TXGPKTIM 21 1 read-write TXLPITRCIM TXLPITRCIM 27 1 read-only TXLPIUSCIM TXLPIUSCIM 26 1 read-write TXMCOLGPIM TXMCOLGPIM 15 1 read-write TXSCOLGPIM TXSCOLGPIM 14 1 read-write RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode. 0x798 32 read-only n 0x0 0x0 RXALGNERR RXALGNERR 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with CRC error. 0x794 32 read-only n 0x0 0x0 RXCRCERR RXCRCERR 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Rx LPI. 0x7F8 32 read-only n 0x0 0x0 RXLPITRC RXLPITRC 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral. 0x7F4 32 read-only n 0x0 0x0 RXLPIUSC RXLPIUSC 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD This register provides the number of good unicast packets received by Ethernet peripheral. 0x7C4 32 read-only n 0x0 0x0 RXUCASTG RXUCASTG 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Tx LPI. 0x7F0 32 read-only n 0x0 0x0 TXLPITRC TXLPITRC 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral. 0x7EC 32 read-only n 0x0 0x0 TXLPIUSC TXLPIUSC 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode. 0x750 32 read-only n 0x0 0x0 TXMULTCOLG TXMULTCOLG 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD This register provides the number of good packets transmitted by Ethernet peripheral. 0x768 32 read-only n 0x0 0x0 TXPKTG TXPKTG 0 32 read-only TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode. 0x74C 32 read-only n 0x0 0x0 TXSNGLCOLG TXSNGLCOLG 0 32 read-only ETH_MTL ETH_MTL Ethernet 0x0 0x0 0x400 registers n ETH_MTLISR ETH_MTLISR The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC. 0x20 32 read-only n 0x0 0x0 Q0IS Q0IS 0 1 read-only Q1IS Q1IS 1 1 read-only ETH_MTLOMR ETH_MTLOMR The Operating Mode register establishes the Transmit and Receive operating modes and commands. 0x0 32 read-write n 0x0 0x0 CNTCLR CNTCLR 9 1 read-write CNTPRST CNTPRST 8 1 read-write DTXSTS DTXSTS 1 1 read-write RAA RAA 2 1 read-write SCHALG SCHALG 5 2 read-write ETH_MTLQ0ICSR ETH_MTLQ0ICSR Queue 0 interrupt control status Register 0x12C 32 read-write n 0x0 0x0 ABPSIE ABPSIE 9 1 read-write ABPSIS ABPSIS 1 1 read-write RXOIE RXOIE 24 1 read-write RXOVFIS RXOVFIS 16 1 read-write TXUIE TXUIE 8 1 read-write TXUNFIS TXUNFIS 0 1 read-only ETH_MTLQ1ICSR ETH_MTLQ1ICSR Queue 1 interrupt control status Register 0x16C 32 read-write n 0x0 0x0 ABPSIE ABPSIE 9 1 read-write ABPSIS ABPSIS 1 1 read-write RXOIE RXOIE 24 1 read-write RXOVFIS RXOVFIS 16 1 read-write TXUIE TXUIE 8 1 read-write TXUNFIS TXUNFIS 0 1 read-only ETH_MTLRxQ0CR ETH_MTLRxQ0CR Rx queue 0 control register 0x13C 32 read-write n 0x0 0x0 RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only RXQ_WEGT RXQ_WEGT 0 3 read-only ETH_MTLRxQ0DR ETH_MTLRxQ0DR Rx queue i debug register 0x138 32 read-only n 0x0 0x0 PRXQ PRXQ 16 14 read-only RRCSTS RRCSTS 1 2 read-only RWCSTS RWCSTS 0 1 read-only RXQSTS RXQSTS 4 2 read-only ETH_MTLRxQ0MPOCR ETH_MTLRxQ0MPOCR Rx queue 0 missed packet and overflow counter register 0x134 32 read-only n 0x0 0x0 MISCNTOVF MISCNTOVF 27 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only OVFPKTCNT OVFPKTCNT 0 11 read-only ETH_MTLRxQ0OMR ETH_MTLRxQ0OMR Rx queue 0 operating mode register 0x130 32 read-write n 0x0 0x0 DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write FEP FEP 4 1 read-write FUP FUP 3 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only RSF RSF 5 1 read-write RTC RTC 0 2 read-write ETH_MTLRxQ1CR ETH_MTLRxQ1CR Rx queue 1 control register 0x17C 32 read-write n 0x0 0x0 RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only RXQ_WEGT RXQ_WEGT 0 3 read-only ETH_MTLRxQ1DR ETH_MTLRxQ1DR Rx queue i debug register 0x178 32 read-only n 0x0 0x0 PRXQ PRXQ 16 14 read-only RRCSTS RRCSTS 1 2 read-only RWCSTS RWCSTS 0 1 read-only RXQSTS RXQSTS 4 2 read-only ETH_MTLRxQ1MPOCR ETH_MTLRxQ1MPOCR Rx queue 1 missed packet and overflow counter register 0x174 32 read-only n 0x0 0x0 MISCNTOVF MISCNTOVF 27 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only OVFPKTCNT OVFPKTCNT 0 11 read-only ETH_MTLRxQ1OMR ETH_MTLRxQ1OMR Rx queue 1 operating mode register 0x170 32 read-write n 0x0 0x0 DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write FEP FEP 4 1 read-write FUP FUP 3 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only RSF RSF 5 1 read-write RTC RTC 0 2 read-write ETH_MTLTxQ0DR ETH_MTLTxQ0DR Tx queue 0 underflow register 0x108 32 read-only n 0x0 0x0 PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQPAUSED TXQPAUSED 0 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only ETH_MTLTxQ0ESR ETH_MTLTxQ0ESR Tx queue x ETS status Register 0x114 32 read-only n 0x0 0x0 ABS ABS 0 24 read-only ETH_MTLTxQ0OMR ETH_MTLTxQ0OMR Tx queue 0 operating mode Register 0x100 32 read-write n 0x0 0x0 FTQ FTQ 0 1 read-write TQS TQS 16 9 read-write TSF TSF 1 1 read-write TTC TTC 4 2 read-write TXQEN TXQEN 2 2 read-write ETH_MTLTxQ0UR ETH_MTLTxQ0UR Tx queue 0 underflow register 0x104 32 read-only n 0x0 0x0 UFCNTOVF UFCNTOVF 11 1 read-only UFFRMCNT UFFRMCNT 0 11 read-only ETH_MTLTxQ1DR ETH_MTLTxQ1DR Tx queue 1 underflow register 0x148 32 read-only n 0x0 0x0 PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQPAUSED TXQPAUSED 0 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only ETH_MTLTxQ1ECR ETH_MTLTxQ1ECR The Queue ETS Control register controls the enhanced transmission selection operation. 0x150 32 read-write n 0x0 0x0 AVALG AVALG 2 1 read-write CC CC 3 1 read-write SLC SLC 4 3 read-write ETH_MTLTxQ1ESR ETH_MTLTxQ1ESR Tx queue x ETS status Register 0x154 32 read-only n 0x0 0x0 ABS ABS 0 24 read-only ETH_MTLTxQ1HCR ETH_MTLTxQ1HCR The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue. 0x160 32 read-write n 0x0 0x0 HC HC 0 29 read-write ETH_MTLTxQ1LCR ETH_MTLTxQ1LCR The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue. 0x164 32 read-write n 0x0 0x0 LC LC 0 29 read-write ETH_MTLTxQ1OMR ETH_MTLTxQ1OMR Tx queue 1 operating mode Register 0x140 32 read-write n 0x0 0x0 FTQ FTQ 0 1 read-write TQS TQS 16 9 read-write TSF TSF 1 1 read-write TTC TTC 4 2 read-write TXQEN TXQEN 2 2 read-write ETH_MTLTxQ1QWR ETH_MTLTxQ1QWR This register provides the average traffic transmitted on queue 1. 0x158 32 read-write n 0x0 0x0 ISCQW ISCQW 0 21 read-write ETH_MTLTxQ1SSCR ETH_MTLTxQ1SSCR The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue. 0x15C 32 read-write n 0x0 0x0 SSC SSC 0 14 read-write ETH_MTLTxQ1UR ETH_MTLTxQ1UR Tx queue 1 underflow register 0x144 32 read-only n 0x0 0x0 UFCNTOVF UFCNTOVF 11 1 read-only UFFRMCNT UFFRMCNT 0 11 read-only ETZPC ETZPC ETZPC 0x0 0x0 0x400 registers n DECPROT0 ETZPC_DECPROT0 Register reset values 0x10 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT1 ETZPC_DECPROT1 Register reset values 0x14 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT2 ETZPC_DECPROT2 Register reset values 0x18 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT3 ETZPC_DECPROT3 Register reset values 0x1C 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT4 ETZPC_DECPROT4 Register reset values 0x20 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT5 ETZPC_DECPROT5 Register reset values 0x24 32 read-write n 0x0 0x0 DECPROT0 DECPROT0 0 2 DECPROT1 DECPROT1 2 2 DECPROT10 DECPROT10 20 2 DECPROT11 DECPROT11 22 2 DECPROT12 DECPROT12 24 2 DECPROT13 DECPROT13 26 2 DECPROT14 DECPROT14 28 2 DECPROT15 DECPROT15 30 2 DECPROT2 DECPROT2 4 2 DECPROT3 DECPROT3 6 2 DECPROT4 DECPROT4 8 2 DECPROT5 DECPROT5 10 2 DECPROT6 DECPROT6 12 2 DECPROT7 DECPROT7 14 2 DECPROT8 DECPROT8 16 2 DECPROT9 DECPROT9 18 2 DECPROT_LOCK0 ETZPC_DECPROT_LOCK0 ETZPC decprot lock 0 register 0x30 32 read-write n 0x0 0x0 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK2 LOCK2 2 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK3 LOCK3 3 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 DECPROT_LOCK1 ETZPC_DECPROT_LOCK1 ETZPC decprot lock 1 register 0x34 32 read-write n 0x0 0x0 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK2 LOCK2 2 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK3 LOCK3 3 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 DECPROT_LOCK2 ETZPC_DECPROT_LOCK2 ETZPC decprot lock 2 register 0x38 32 read-write n 0x0 0x0 LOCK0 LOCK0 0 1 LOCK1 LOCK1 1 1 LOCK10 LOCK10 10 1 LOCK11 LOCK11 11 1 LOCK12 LOCK12 12 1 LOCK13 LOCK13 13 1 LOCK14 LOCK14 14 1 LOCK15 LOCK15 15 1 LOCK16 LOCK16 16 1 LOCK17 LOCK17 17 1 LOCK18 LOCK18 18 1 LOCK19 LOCK19 19 1 LOCK2 LOCK2 2 1 LOCK20 LOCK20 20 1 LOCK21 LOCK21 21 1 LOCK22 LOCK22 22 1 LOCK23 LOCK23 23 1 LOCK24 LOCK24 24 1 LOCK25 LOCK25 25 1 LOCK26 LOCK26 26 1 LOCK27 LOCK27 27 1 LOCK28 LOCK28 28 1 LOCK29 LOCK29 29 1 LOCK3 LOCK3 3 1 LOCK30 LOCK30 30 1 LOCK31 LOCK31 31 1 LOCK4 LOCK4 4 1 LOCK5 LOCK5 5 1 LOCK6 LOCK6 6 1 LOCK7 LOCK7 7 1 LOCK8 LOCK8 8 1 LOCK9 LOCK9 9 1 HWCFGR ETZPC_HWCFGR ETZPC IP HW configuration register 0x3F0 32 read-only n 0x0 0x0 CHUNKS1N4 CHUNKS1N4 24 8 NUM_AHB_SEC NUM_AHB_SEC 16 8 NUM_PER_SEC NUM_PER_SEC 8 8 NUM_TZMA NUM_TZMA 0 8 IDR ETZPC_IDR ETZPC IP version register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SIDR ETZPC_SIDR ETZPC IP version register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 TZMA0_SIZE ETZPC_TZMA0_SIZE ETZPC ROM secure size definition 0x0 32 read-write n 0x0 0x0 LOCK LOCK 31 1 R0SIZE R0SIZE 0 10 TZMA1_SIZE ETZPC_TZMA1_SIZE ETZPC RAM secure size definition 0x4 32 read-write n 0x0 0x0 LOCK LOCK 31 1 R0SIZE R0SIZE 0 10 VERR ETZPC_VERR ETZPC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 EXTI EXTI EXTI 0x0 0x0 0x400 registers n PVD_AVD PVD AND AVD detector through EXTI 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3 interrupt 9 EXTI4 EXTI Line 4 interrupt 10 EXTI5 EXTI line 5 interrupt 23 EXTI10 EXTI line 10 interrupt 40 EXTI11 EXTI line 11 interrupt 42 EXTI11 EXTI line 11 interrupt 42 EXTI6 EXTI line 6 interrupt 64 EXTI7 EXTI line 7 interrupt 65 EXTI8 EXTI line 8 interrupt 66 EXTI9 EXTI line 9 interrupt 67 EXTI12 EXTI line 12 interrupt 76 EXTI13 EXTI line 13 interrupt 77 EXTI14 EXTI line 14 interrupt 121 EXTI15 EXTI line 15 interrupt 127 C2EMR1 EXTI_C2EMR1 EXTI CPU2 wakeup with event mask register 0xC4 32 read-write n 0x0 0x0 EM0 EM0 0 1 EM1 EM1 1 1 EM10 EM10 10 1 EM11 EM11 11 1 EM12 EM12 12 1 EM13 EM13 13 1 EM14 EM14 14 1 EM15 EM15 15 1 EM17 EM17 17 1 EM18 EM18 18 1 EM19 EM19 19 1 EM2 EM2 2 1 EM3 EM3 3 1 EM4 EM4 4 1 EM5 EM5 5 1 EM6 EM6 6 1 EM7 EM7 7 1 EM8 EM8 8 1 EM9 EM9 9 1 C2EMR2 EXTI_C2EMR2 EXTI CPU2 wakeup with event mask register 0xD4 32 read-write n 0x0 0x0 C2EMR3 EXTI_C2EMR3 EXTI CPU2 wakeup with event mask register 0xE4 32 read-write n 0x0 0x0 EM66 EM66 2 1 C2IMR1 EXTI_C2IMR1 Contains register bits for configurable events and Direct events. 0xC0 32 read-write n 0x0 0x0 IM0 IM0 0 1 IM1 IM1 1 1 IM10 IM10 10 1 IM11 IM11 11 1 IM12 IM12 12 1 IM13 IM13 13 1 IM14 IM14 14 1 IM15 IM15 15 1 IM16 IM16 16 1 IM17 IM17 17 1 IM18 IM18 18 1 IM19 IM19 19 1 IM2 IM2 2 1 IM20 IM20 20 1 IM21 IM21 21 1 IM22 IM22 22 1 IM23 IM23 23 1 IM24 IM24 24 1 IM25 IM25 25 1 IM26 IM26 26 1 IM27 IM27 27 1 IM28 IM28 28 1 IM29 IM29 29 1 IM3 IM3 3 1 IM30 IM30 30 1 IM31 IM31 31 1 IM4 IM4 4 1 IM5 IM5 5 1 IM6 IM6 6 1 IM7 IM7 7 1 IM8 IM8 8 1 IM9 IM9 9 1 C2IMR2 EXTI_C2IMR2 Contains register bits for configurable events and direct events. 0xD0 32 read-write n 0x0 0x0 IM32 IM32 0 1 IM33 IM33 1 1 IM34 IM34 2 1 IM35 IM35 3 1 IM36 IM36 4 1 IM37 IM37 5 1 IM38 IM38 6 1 IM39 IM39 7 1 IM40 IM40 8 1 IM41 IM41 9 1 IM42 IM42 10 1 IM43 IM43 11 1 IM44 IM44 12 1 IM45 IM45 13 1 IM46 IM46 14 1 IM47 IM47 15 1 IM48 IM48 16 1 IM49 IM49 17 1 IM50 IM50 18 1 IM51 IM51 19 1 IM52 IM52 20 1 IM53 IM53 21 1 IM54 IM54 22 1 IM55 IM55 23 1 IM56 IM56 24 1 IM57 IM57 25 1 IM58 IM58 26 1 IM59 IM59 27 1 IM60 IM60 28 1 IM61 IM61 29 1 IM62 IM62 30 1 IM63 IM63 31 1 C2IMR3 EXTI_C2IMR3 Contains register bits for configurable events and direct events. 0xE0 32 read-write n 0x0 0x0 IM64 IM64 0 1 IM65 IM65 1 1 IM66 IM66 2 1 IM67 IM67 3 1 IM68 IM68 4 1 IM69 IM69 5 1 IM70 IM70 6 1 IM71 IM71 7 1 IM72 IM72 8 1 IM73 IM73 9 1 IM74 IM74 10 1 IM75 IM75 11 1 EMR1 EXTI_EMR1 EXTI CPU wakeup with event mask register 0x84 32 read-write n 0x0 0x0 EM0 EM0 0 1 EM1 EM1 1 1 EM10 EM10 10 1 EM11 EM11 11 1 EM12 EM12 12 1 EM13 EM13 13 1 EM14 EM14 14 1 EM15 EM15 15 1 EM17 EM17 17 1 EM18 EM18 18 1 EM19 EM19 19 1 EM2 EM2 2 1 EM3 EM3 3 1 EM4 EM4 4 1 EM5 EM5 5 1 EM6 EM6 6 1 EM7 EM7 7 1 EM8 EM8 8 1 EM9 EM9 9 1 EMR2 EXTI_EMR2 EXTI CPU wakeup with event mask register 0x94 32 read-write n 0x0 0x0 EMR3 EXTI_EMR3 EXTI CPU wakeup with event mask register 0xA4 32 read-write n 0x0 0x0 EM66 EM66 2 1 EXTICR1 EXTI_EXTICR1 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x60 32 read-write n 0x0 0x0 EXTI0 EXTI0 0 8 EXTI1 EXTI1 8 8 EXTI2 EXTI2 16 8 EXTI3 EXTI3 24 8 EXTICR2 EXTI_EXTICR2 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x64 32 read-write n 0x0 0x0 EXTI4 EXTI4 0 8 EXTI5 EXTI5 8 8 EXTI6 EXTI6 16 8 EXTI7 EXTI7 24 8 EXTICR3 EXTI_EXTICR3 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x68 32 read-write n 0x0 0x0 EXTI10 EXTI10 16 8 EXTI11 EXTI11 24 8 EXTI8 EXTI8 0 8 EXTI9 EXTI9 8 8 EXTICR4 EXTI_EXTICR4 EXTIm fields contain only the number of bits in line with the nb_ioport configuration. 0x6C 32 read-write n 0x0 0x0 EXTI12 EXTI12 0 8 EXTI13 EXTI13 8 8 EXTI14 EXTI14 16 8 EXTI15 EXTI15 24 8 FPR1 EXTI_FPR1 Contains only register bits for configurable events. 0x10 32 read-write n 0x0 0x0 FPIF0 FPIF0 0 1 FPIF1 FPIF1 1 1 FPIF10 FPIF10 10 1 FPIF11 FPIF11 11 1 FPIF12 FPIF12 12 1 FPIF13 FPIF13 13 1 FPIF14 FPIF14 14 1 FPIF15 FPIF15 15 1 FPIF16 FPIF16 16 1 FPIF2 FPIF2 2 1 FPIF3 FPIF3 3 1 FPIF4 FPIF4 4 1 FPIF5 FPIF5 5 1 FPIF6 FPIF6 6 1 FPIF7 FPIF7 7 1 FPIF8 FPIF8 8 1 FPIF9 FPIF9 9 1 FPR2 EXTI_FPR2 Contains only register bits for configurable events. 0x30 32 read-write n 0x0 0x0 FPR3 EXTI_FPR3 Contains only register bits for configurable events. 0x50 32 read-write n 0x0 0x0 FPIF65 FPIF65 1 1 FPIF66 FPIF66 2 1 FPIF68 FPIF68 4 1 FPIF73 FPIF73 9 1 FPIF74 FPIF74 10 1 FTSR1 EXTI_FTSR1 Contains only register bits for configurable events. 0x4 32 read-write n 0x0 0x0 FT0 FT0 0 1 FT1 FT1 1 1 FT10 FT10 10 1 FT11 FT11 11 1 FT12 FT12 12 1 FT13 FT13 13 1 FT14 FT14 14 1 FT15 FT15 15 1 FT16 FT16 16 1 FT2 FT2 2 1 FT3 FT3 3 1 FT4 FT4 4 1 FT5 FT5 5 1 FT6 FT6 6 1 FT7 FT7 7 1 FT8 FT8 8 1 FT9 FT9 9 1 FTSR2 EXTI_FTSR2 Contains only register bits for configurable events. 0x24 32 read-write n 0x0 0x0 FTSR3 EXTI_FTSR3 Contains only register bits for configurable events. 0x44 32 read-write n 0x0 0x0 FT65 FT65 1 1 FT66 FT66 2 1 FT68 FT68 4 1 FT73 FT73 9 1 FT74 FT74 10 1 HWCFGR1 EXTI_HWCFGR1 EXTI hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 CPUEVTEN CPUEVTEN 12 4 NBCPUS NBCPUS 8 4 NBEVENTS NBEVENTS 0 8 NBIOPORT NBIOPORT 16 8 HWCFGR10 EXTI_HWCFGR10 EXTI hardware configuration register 10 0x3CC 32 read-only n 0x0 0x0 HWCFGR11 EXTI_HWCFGR11 EXTI hardware configuration register 11 0x3C8 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR12 EXTI_HWCFGR12 EXTI hardware configuration register 12 0x3C4 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR13 EXTI_HWCFGR13 EXTI hardware configuration register 13 0x3C0 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR2 EXTI_HWCFGR2 EXTI hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 EVENT_TRG EVENT_TRG 0 32 HWCFGR3 EXTI_HWCFGR3 EXTI hardware configuration register 3 0x3E8 32 read-only n 0x0 0x0 EVENT_TRG EVENT_TRG 0 32 HWCFGR4 EXTI_HWCFGR4 EXTI hardware configuration register 4 0x3E4 32 read-only n 0x0 0x0 EVENT_TRG EVENT_TRG 0 32 HWCFGR5 EXTI_HWCFGR5 EXTI hardware configuration register 5 0x3E0 32 read-only n 0x0 0x0 CPUEVENT CPUEVENT 0 32 HWCFGR6 EXTI_HWCFGR6 EXTI hardware configuration register 6 0x3DC 32 read-only n 0x0 0x0 CPUEVENT CPUEVENT 0 32 HWCFGR7 EXTI_HWCFGR7 EXTI hardware configuration register 7 0x3D8 32 read-only n 0x0 0x0 CPUEVENT CPUEVENT 0 32 HWCFGR8 EXTI_HWCFGR8 EXTI hardware configuration register 8 0x3D4 32 read-only n 0x0 0x0 HWCFGR9 EXTI_HWCFGR9 EXTI hardware configuration register 9 0x3D0 32 read-only n 0x0 0x0 IMR1 EXTI_IMR1 Contains register bits for configurable events and Direct events. 0x80 32 read-write n 0x0 0x0 IM0 IM0 0 1 IM1 IM1 1 1 IM10 IM10 10 1 IM11 IM11 11 1 IM12 IM12 12 1 IM13 IM13 13 1 IM14 IM14 14 1 IM15 IM15 15 1 IM16 IM16 16 1 IM17 IM17 17 1 IM18 IM18 18 1 IM19 IM19 19 1 IM2 IM2 2 1 IM20 IM20 20 1 IM21 IM21 21 1 IM22 IM22 22 1 IM23 IM23 23 1 IM24 IM24 24 1 IM25 IM25 25 1 IM26 IM26 26 1 IM27 IM27 27 1 IM28 IM28 28 1 IM29 IM29 29 1 IM3 IM3 3 1 IM30 IM30 30 1 IM31 IM31 31 1 IM4 IM4 4 1 IM5 IM5 5 1 IM6 IM6 6 1 IM7 IM7 7 1 IM8 IM8 8 1 IM9 IM9 9 1 IMR2 EXTI_IMR2 Contains register bits for configurable events and direct events. 0x90 32 read-write n 0x0 0x0 IM32 IM32 0 1 IM33 IM33 1 1 IM34 IM34 2 1 IM35 IM35 3 1 IM36 IM36 4 1 IM37 IM37 5 1 IM38 IM38 6 1 IM39 IM39 7 1 IM40 IM40 8 1 IM41 IM41 9 1 IM42 IM42 10 1 IM43 IM43 11 1 IM44 IM44 12 1 IM45 IM45 13 1 IM46 IM46 14 1 IM47 IM47 15 1 IM48 IM48 16 1 IM49 IM49 17 1 IM50 IM50 18 1 IM51 IM51 19 1 IM52 IM52 20 1 IM53 IM53 21 1 IM54 IM54 22 1 IM55 IM55 23 1 IM56 IM56 24 1 IM57 IM57 25 1 IM58 IM58 26 1 IM59 IM59 27 1 IM60 IM60 28 1 IM61 IM61 29 1 IM62 IM62 30 1 IM63 IM63 31 1 IMR3 EXTI_IMR3 Contains register bits for configurable events and direct events. 0xA0 32 read-write n 0x0 0x0 IM64 IM64 0 1 IM65 IM65 1 1 IM66 IM66 2 1 IM67 IM67 3 1 IM68 IM68 4 1 IM69 IM69 5 1 IM70 IM70 6 1 IM71 IM71 7 1 IM72 IM72 8 1 IM73 IM73 9 1 IM74 IM74 10 1 IM75 IM75 11 1 IPIDR EXTI_IPIDR EXTI identification register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 RPR1 EXTI_RPR1 Contains only register bits for configurable events. 0xC 32 read-write n 0x0 0x0 RPIF0 RPIF0 0 1 RPIF1 RPIF1 1 1 RPIF10 RPIF10 10 1 RPIF11 RPIF11 11 1 RPIF12 RPIF12 12 1 RPIF13 RPIF13 13 1 RPIF14 RPIF14 14 1 RPIF15 RPIF15 15 1 RPIF16 RPIF16 16 1 RPIF2 RPIF2 2 1 RPIF3 RPIF3 3 1 RPIF4 RPIF4 4 1 RPIF5 RPIF5 5 1 RPIF6 RPIF6 6 1 RPIF7 RPIF7 7 1 RPIF8 RPIF8 8 1 RPIF9 RPIF9 9 1 RPR2 EXTI_RPR2 Contains only register bits for configurable events. 0x2C 32 read-write n 0x0 0x0 RPR3 EXTI_RPR3 Contains only register bits for configurable events. 0x4C 32 read-write n 0x0 0x0 RPIF65 RPIF65 1 1 RPIF66 RPIF66 2 1 RPIF68 RPIF68 4 1 RPIF73 RPIF73 9 1 RPIF74 RPIF74 10 1 RTSR1 EXTI_RTSR1 Contains only register bits for configurable events. 0x0 32 read-write n 0x0 0x0 RT0 RT0 0 1 RT1 RT1 1 1 RT10 RT10 10 1 RT11 RT11 11 1 RT12 RT12 12 1 RT13 RT13 13 1 RT14 RT14 14 1 RT15 RT15 15 1 RT16 RT16 16 1 RT2 RT2 2 1 RT3 RT3 3 1 RT4 RT4 4 1 RT5 RT5 5 1 RT6 RT6 6 1 RT7 RT7 7 1 RT8 RT8 8 1 RT9 RT9 9 1 RTSR2 EXTI_RTSR2 Contains only register bits for configurable events. 0x20 32 read-write n 0x0 0x0 RTSR3 EXTI_RTSR3 Contains only register bits for configurable events. 0x40 32 read-write n 0x0 0x0 RT65 RT65 1 1 RT66 RT66 2 1 RT68 RT68 4 1 RT73 RT73 9 1 RT74 RT74 10 1 SIDR EXTI_SIDR EXTI size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SWIER1 EXTI_SWIER1 Contains only register bits for configurable events. 0x8 32 read-write n 0x0 0x0 SWI0 SWI0 0 1 SWI1 SWI1 1 1 SWI10 SWI10 10 1 SWI11 SWI11 11 1 SWI12 SWI12 12 1 SWI13 SWI13 13 1 SWI14 SWI14 14 1 SWI15 SWI15 15 1 SWI16 SWI16 16 1 SWI2 SWI2 2 1 SWI3 SWI3 3 1 SWI4 SWI4 4 1 SWI5 SWI5 5 1 SWI6 SWI6 6 1 SWI7 SWI7 7 1 SWI8 SWI8 8 1 SWI9 SWI9 9 1 SWIER2 EXTI_SWIER2 Contains only register bits for configurable events. 0x28 32 read-write n 0x0 0x0 SWIER3 EXTI_SWIER3 Contains only register bits for configurable events. 0x48 32 read-write n 0x0 0x0 SWI65 SWI65 1 1 SWI66 SWI66 2 1 SWI68 SWI68 4 1 SWI73 SWI73 9 1 SWI74 SWI74 10 1 TZENR1 EXTI_TZENR1 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x14 32 read-write n 0x0 0x0 TZEN0 TZEN0 0 1 TZEN1 TZEN1 1 1 TZEN10 TZEN10 10 1 TZEN11 TZEN11 11 1 TZEN12 TZEN12 12 1 TZEN13 TZEN13 13 1 TZEN14 TZEN14 14 1 TZEN15 TZEN15 15 1 TZEN17 TZEN17 17 1 TZEN18 TZEN18 18 1 TZEN19 TZEN19 19 1 TZEN2 TZEN2 2 1 TZEN24 TZEN24 24 1 TZEN26 TZEN26 26 1 TZEN3 TZEN3 3 1 TZEN4 TZEN4 4 1 TZEN5 TZEN5 5 1 TZEN6 TZEN6 6 1 TZEN7 TZEN7 7 1 TZEN8 TZEN8 8 1 TZEN9 TZEN9 9 1 TZENR2 EXTI_TZENR2 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x34 32 read-write n 0x0 0x0 TZEN41 TZEN41 9 1 TZEN54 TZEN54 22 1 TZEN55 TZEN55 23 1 TZEN56 TZEN56 24 1 TZEN57 TZEN57 25 1 TZEN58 TZEN58 26 1 TZEN59 TZEN59 27 1 TZEN60 TZEN60 28 1 TZENR3 EXTI_TZENR3 This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events. 0x54 32 read-write n 0x0 0x0 VERR EXTI_VERR EXTI IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 FDCAN1 FDCAN1 FDCAN1 0x0 0x0 0x400 registers n FDCAN_CCCR FDCAN_CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 read-write BRSE BRSE 9 1 read-write CCE CCE 1 1 read-write CSA CSA 3 1 read-only CSR CSR 4 1 read-write DAR DAR 6 1 read-write EFBI EFBI 13 1 read-write FDOE FDOE 8 1 read-write INIT INIT 0 1 read-write MON MON 5 1 read-write NISO NISO 15 1 read-write PXHD PXHD 12 1 read-write TEST TEST 7 1 read-write TXP TXP 14 1 read-write FDCAN_CREL FDCAN_CREL FDCAN core release register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 FDCAN_DBTP FDCAN_DBTP This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 DSJW DSJW 0 4 DTSEG1 DTSEG1 8 5 DTSEG2 DTSEG2 4 4 TDC TDC 23 1 FDCAN_ECR FDCAN_ECR FDCAN error counter register 0x40 32 read-write n 0x0 0x0 CEL CEL 16 8 read-write RP RP 15 1 read-only TEC TEC 0 8 read-only TREC TREC 8 7 read-only FDCAN_ENDN FDCAN_ENDN FDCAN Endian register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 FDCAN_GFC FDCAN_GFC Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 ANFS ANFS 4 2 RRFE RRFE 0 1 RRFS RRFS 1 1 FDCAN_HPMS FDCAN_HPMS This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x94 32 read-only n 0x0 0x0 BIDX BIDX 0 6 FIDX FIDX 8 7 FLST FLST 15 1 MSI MSI 6 2 FDCAN_IE FDCAN_IE The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 BECE BECE 20 1 BEUE BEUE 21 1 BOE BOE 25 1 DRXE DRXE 19 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 HPME HPME 8 1 MRAFE MRAFE 17 1 PEAE PEAE 27 1 PEDE PEDE 28 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 TCE TCE 9 1 TCFE TCFE 10 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TFEE TFEE 11 1 TOOE TOOE 18 1 TSWE TSWE 16 1 WDIE WDIE 26 1 FDCAN_ILE FDCAN_ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 EINT1 EINT1 1 1 FDCAN_ILS FDCAN_ILS This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 BECL BECL 20 1 BEUL BEUL 21 1 BOL BOL 25 1 DRXL DRXL 19 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 HPML HPML 8 1 MRAFL MRAFL 17 1 PEAL PEAL 27 1 PEDL PEDL 28 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 TCFL TCFL 10 1 TCL TCL 9 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TFEL TFEL 11 1 TOOL TOOL 18 1 TSWL TSWL 16 1 WDIL WDIL 26 1 FDCAN_IR FDCAN_IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 BO BO 25 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 HPM HPM 8 1 MRAF MRAF 17 1 PEA PEA 27 1 PED PED 28 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF0N RF0N 0 1 RF0W RF0W 1 1 RF1F RF1F 6 1 RF1L RF1L 7 1 RF1N RF1N 4 1 RF1W RF1W 5 1 TC TC 9 1 TCF TCF 10 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TFE TFE 11 1 TOO TOO 18 1 TSW TSW 16 1 WDI WDI 26 1 FDCAN_NBTP FDCAN_NBTP This register is dedicated to the nominal bit timing used during the arbitration phase. 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 NSJW NSJW 25 7 NTSEG1 NTSEG1 8 8 NTSEG2 NTSEG2 0 7 FDCAN_NDAT1 FDCAN_NDAT1 FDCAN new data 1 register 0x98 32 read-write n 0x0 0x0 ND0 ND0 0 1 ND1 ND1 1 1 ND10 ND10 10 1 ND11 ND11 11 1 ND12 ND12 12 1 ND13 ND13 13 1 ND14 ND14 14 1 ND15 ND15 15 1 ND16 ND16 16 1 ND17 ND17 17 1 ND18 ND18 18 1 ND19 ND19 19 1 ND2 ND2 2 1 ND20 ND20 20 1 ND21 ND21 21 1 ND22 ND22 22 1 ND23 ND23 23 1 ND24 ND24 24 1 ND25 ND25 25 1 ND26 ND26 26 1 ND27 ND27 27 1 ND28 ND28 28 1 ND29 ND29 29 1 ND3 ND3 3 1 ND30 ND30 30 1 ND31 ND31 31 1 ND4 ND4 4 1 ND5 ND5 5 1 ND6 ND6 6 1 ND7 ND7 7 1 ND8 ND8 8 1 ND9 ND9 9 1 FDCAN_NDAT2 FDCAN_NDAT2 FDCAN new data 2 register 0x9C 32 read-write n 0x0 0x0 ND32 ND32 0 1 ND33 ND33 1 1 ND34 ND34 2 1 ND35 ND35 3 1 ND36 ND36 4 1 ND37 ND37 5 1 ND38 ND38 6 1 ND39 ND39 7 1 ND40 ND40 8 1 ND41 ND41 9 1 ND42 ND42 10 1 ND43 ND43 11 1 ND44 ND44 12 1 ND45 ND45 13 1 ND46 ND46 14 1 ND47 ND47 15 1 ND48 ND48 16 1 ND49 ND49 17 1 ND50 ND50 18 1 ND51 ND51 19 1 ND52 ND52 20 1 ND53 ND53 21 1 ND54 ND54 22 1 ND55 ND55 23 1 ND56 ND56 24 1 ND57 ND57 25 1 ND58 ND58 26 1 ND59 ND59 27 1 ND60 ND60 28 1 ND61 ND61 29 1 ND62 ND62 30 1 ND63 ND63 31 1 FDCAN_PSR FDCAN_PSR FDCAN protocol status register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 read-only BO BO 7 1 read-only DLEC DLEC 8 3 read-only EP EP 5 1 read-only EW EW 6 1 read-only LEC LEC 0 3 read-only PXE PXE 14 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write RESI RESI 11 1 read-write TDCV TDCV 16 7 read-only FDCAN_RWD FDCAN_RWD The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only FDCAN_RXBC FDCAN_RXBC FDCAN Rx buffer configuration register 0xAC 32 read-write n 0x0 0x0 RBSA RBSA 2 14 FDCAN_RXESC FDCAN_RXESC Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. 0xBC 32 read-only n 0x0 0x0 F0DS F0DS 0 3 F1DS F1DS 4 3 RBDS RBDS 8 3 FDCAN_RXF0A FDCAN_RXF0A FDCAN Rx FIFO 0 acknowledge register 0xA8 32 read-write n 0x0 0x0 F0AI F0AI 0 6 FDCAN_RXF0C FDCAN_RXF0C FDCAN Rx FIFO 0 configuration register 0xA0 32 read-write n 0x0 0x0 F0OM F0OM 31 1 F0S F0S 16 7 F0SA F0SA 2 14 F0WM F0WM 24 7 FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 status register 0xA4 32 read-write n 0x0 0x0 F0F F0F 24 1 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 RF0L RF0L 25 1 FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 acknowledge register 0xB8 32 read-write n 0x0 0x0 F1AI F1AI 0 6 FDCAN_RXF1C FDCAN_RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 32 read-write n 0x0 0x0 F1OM F1OM 31 1 F1S F1S 16 7 F1SA F1SA 2 14 F1WM F1WM 24 7 FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 status register 0xB4 32 read-only n 0x0 0x0 DMS DMS 30 2 F1F F1F 24 1 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 RF1L RF1L 25 1 FDCAN_SIDFC FDCAN_SIDFC Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. 0x84 32 read-write n 0x0 0x0 FLSSA FLSSA 2 14 LSS LSS 16 8 FDCAN_TDCR FDCAN_TDCR FDCAN transmitter delay compensation register 0x48 32 read-write n 0x0 0x0 TDCF TDCF 0 7 TDCO TDCO 8 7 FDCAN_TEST FDCAN_TEST Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 read-write RX RX 7 1 read-only TX TX 5 2 read-write FDCAN_TOCC FDCAN_TOCC FDCAN timeout counter configuration register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 TOP TOP 16 16 TOS TOS 1 2 FDCAN_TOCV FDCAN_TOCV FDCAN timeout counter value register 0x2C 32 read-write n 0x0 0x0 TOC TOC 0 16 FDCAN_TSCC FDCAN_TSCC FDCAN timestamp counter configuration register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 TSS TSS 0 2 FDCAN_TSCV FDCAN_TSCV FDCAN timestamp counter value register 0x24 32 read-write n 0x0 0x0 TSC TSC 0 16 FDCAN_TTCPT FDCAN_TTCPT FDCAN TT capture time register 0x13C 32 read-only n 0x0 0x0 CCV CCV 0 6 SWV SWV 16 16 FDCAN_TTCSM FDCAN_TTCSM FDCAN TT cycle sync mark register 0x140 32 read-only n 0x0 0x0 CSM CSM 0 16 FDCAN_TTCTC FDCAN_TTCTC FDCAN TT cycle time and count register 0x138 32 read-only n 0x0 0x0 CC CC 16 6 CT CT 0 16 FDCAN_TTGTP FDCAN_TTGTP If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. 0x118 32 read-write n 0x0 0x0 CTP CTP 16 16 TP TP 0 16 FDCAN_TTIE FDCAN_TTIE The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. 0x124 32 read-write n 0x0 0x0 AWE AWE 17 1 CERE CERE 18 1 CSME CSME 2 1 ELCE ELCE 14 1 GTDE GTDE 8 1 GTEE GTEE 9 1 GTWE GTWE 7 1 IWTE IWTE 15 1 RTMIE RTMIE 4 1 SBCE SBCE 0 1 SE1E SE1E 12 1 SE2E SE2E 13 1 SMCE SMCE 1 1 SOGE SOGE 3 1 SWEE SWEE 6 1 TTMIE TTMIE 5 1 TXOE TXOE 11 1 TXUE TXUE 10 1 WTE WTE 16 1 FDCAN_TTILS FDCAN_TTILS The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x128 32 read-write n 0x0 0x0 AWL AWL 17 1 CERL CERL 18 1 CSML CSML 2 1 ELCL ELCL 14 1 GTDL GTDL 8 1 GTEL GTEL 9 1 GTWL GTWL 7 1 IWTL IWTL 15 1 RTMIL RTMIL 4 1 SBCL SBCL 0 1 SE1L SE1L 12 1 SE2L SE2L 13 1 SMCL SMCL 1 1 SOGL SOGL 3 1 SWEL SWEL 6 1 TTMIL TTMIL 5 1 TXOL TXOL 11 1 TXUL TXUL 10 1 WTL WTL 16 1 FDCAN_TTIR FDCAN_TTIR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. 0x120 32 read-write n 0x0 0x0 AW AW 17 1 CER CER 18 1 CSM CSM 2 1 ELC ELC 14 1 GTD GTD 8 1 GTE GTE 9 1 GTW GTW 7 1 IWTG IWTG 15 1 RTMI RTMI 4 1 SBC SBC 0 1 SE1 SE1 12 1 SE2 SE2 13 1 SMC SMC 1 1 SOG SOG 3 1 SWE SWE 6 1 TTMI TTMI 5 1 TXO TXO 11 1 TXU TXU 10 1 WT WT 16 1 FDCAN_TTLGT FDCAN_TTLGT FDCAN TT local and global time register 0x134 32 read-only n 0x0 0x0 GT GT 16 16 LT LT 0 16 FDCAN_TTMLM FDCAN_TTMLM FDCAN TT matrix limits register 0x10C 32 read-write n 0x0 0x0 CCM CCM 0 6 CSS CSS 6 2 ENTT ENTT 16 12 TXEW TXEW 8 4 FDCAN_TTOCF FDCAN_TTOCF FDCAN TT operation configuration register 0x108 32 read-write n 0x0 0x0 AWL AWL 16 8 ECC ECC 25 1 EECS EECS 15 1 EGTF EGTF 24 1 EVTP EVTP 26 1 GEN GEN 3 1 IRTO IRTO 8 7 LDSDL LDSDL 5 3 OM OM 0 2 TM TM 4 1 FDCAN_TTOCN FDCAN_TTOCN FDCAN TT operation control register 0x114 32 read-write n 0x0 0x0 ECS ECS 1 1 read-write ESCN ESCN 13 1 read-write FGP FGP 10 1 read-write GCS GCS 9 1 read-write LCKC LCKC 15 1 read-only NIG NIG 12 1 read-write RTIE RTIE 5 1 read-write SGT SGT 0 1 read-write SWP SWP 2 1 read-write SWS SWS 3 2 read-write TMC TMC 6 2 read-write TMG TMG 11 1 read-write TTIE TTIE 8 1 read-write FDCAN_TTOST FDCAN_TTOST FDCAN TT operation status register 0x12C 32 read-only n 0x0 0x0 AWE AWE 29 1 EL EL 0 2 GFI GFI 23 1 GSI GSI 27 1 MS MS 2 2 QCS QCS 7 1 QGTP QGTP 6 1 RTO RTO 8 8 SPL SPL 31 1 SYS SYS 4 2 TMP TMP 24 3 WECS WECS 30 1 WFE WFE 28 1 WGTD WGTD 22 1 FDCAN_TTRMC FDCAN_TTRMC FDCAN TT reference message configuration register 0x104 32 read-write n 0x0 0x0 RID RID 0 29 RMPS RMPS 31 1 XTD XTD 30 1 FDCAN_TTTMC FDCAN_TTTMC FDCAN TT trigger memory configuration register 0x100 32 read-write n 0x0 0x0 TME TME 16 7 TMSA TMSA 2 14 FDCAN_TTTMK FDCAN_TTTMK A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. 0x11C 32 read-write n 0x0 0x0 LCKM LCKM 31 1 read-only TICC TICC 16 7 read-write TM TM 0 16 read-write FDCAN_TTTS FDCAN_TTTS The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. 0x300 32 read-write n 0x0 0x0 EVTSEL EVTSEL 4 2 SWTDEL SWTDEL 0 2 FDCAN_TURCF FDCAN_TURCF The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. 0x110 32 read-write n 0x0 0x0 DC DC 16 14 ELT ELT 31 1 NCL NCL 0 16 FDCAN_TURNA FDCAN_TURNA There is no drift compensation in TTCAN level 1. 0x130 32 read-only n 0x0 0x0 NAV NAV 0 18 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx buffer add request register 0xD0 32 read-write n 0x0 0x0 AR AR 0 32 FDCAN_TXBC FDCAN_TXBC FDCAN Tx buffer configuration register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx buffer cancellation finished register 0xDC 32 read-only n 0x0 0x0 CF CF 0 32 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE4 32 read-write n 0x0 0x0 CFIE CFIE 0 32 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx buffer cancellation request register 0xD4 32 read-write n 0x0 0x0 CR CR 0 32 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xE0 32 read-write n 0x0 0x0 TIE TIE 0 32 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx buffer transmission occurred register 0xD8 32 read-only n 0x0 0x0 TO TO 0 32 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx event FIFO acknowledge register 0xF8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 FDCAN_TXEFC FDCAN_TXEFC FDCAN Tx event FIFO configuration register 0xF0 32 read-write n 0x0 0x0 EFS EFS 16 6 EFSA EFSA 2 14 EFWM EFWM 24 6 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx event FIFO status register 0xF4 32 read-only n 0x0 0x0 EFF EFF 24 1 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 TEFL TEFL 25 1 FDCAN_TXESC FDCAN_TXESC Configures the number of data bytes belonging to a Tx buffer element. Data field sizes and gt 8 bytes are intended for CAN FD operation only. 0xC8 32 read-only n 0x0 0x0 TBDS TBDS 0 3 FDCAN_TXFQS FDCAN_TXFQS The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQF TFQF 21 1 TFQPI TFQPI 16 5 FDCAN_XIDAM FDCAN_XIDAM FDCAN extended ID and mask register 0x90 32 read-write n 0x0 0x0 EIDM EIDM 0 29 FDCAN_XIDFC FDCAN_XIDFC Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. 0x88 32 read-write n 0x0 0x0 FLESA FLESA 2 14 LSE LSE 16 8 FDCAN2 FDCAN1 FDCAN1 0x0 0x0 0x400 registers n FDCAN_CCCR FDCAN_CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 read-write BRSE BRSE 9 1 read-write CCE CCE 1 1 read-write CSA CSA 3 1 read-only CSR CSR 4 1 read-write DAR DAR 6 1 read-write EFBI EFBI 13 1 read-write FDOE FDOE 8 1 read-write INIT INIT 0 1 read-write MON MON 5 1 read-write NISO NISO 15 1 read-write PXHD PXHD 12 1 read-write TEST TEST 7 1 read-write TXP TXP 14 1 read-write FDCAN_CREL FDCAN_CREL FDCAN core release register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 FDCAN_DBTP FDCAN_DBTP This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 DSJW DSJW 0 4 DTSEG1 DTSEG1 8 5 DTSEG2 DTSEG2 4 4 TDC TDC 23 1 FDCAN_ECR FDCAN_ECR FDCAN error counter register 0x40 32 read-write n 0x0 0x0 CEL CEL 16 8 read-write RP RP 15 1 read-only TEC TEC 0 8 read-only TREC TREC 8 7 read-only FDCAN_ENDN FDCAN_ENDN FDCAN Endian register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 FDCAN_GFC FDCAN_GFC Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 ANFS ANFS 4 2 RRFE RRFE 0 1 RRFS RRFS 1 1 FDCAN_HPMS FDCAN_HPMS This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x94 32 read-only n 0x0 0x0 BIDX BIDX 0 6 FIDX FIDX 8 7 FLST FLST 15 1 MSI MSI 6 2 FDCAN_IE FDCAN_IE The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 BECE BECE 20 1 BEUE BEUE 21 1 BOE BOE 25 1 DRXE DRXE 19 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 HPME HPME 8 1 MRAFE MRAFE 17 1 PEAE PEAE 27 1 PEDE PEDE 28 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 TCE TCE 9 1 TCFE TCFE 10 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TFEE TFEE 11 1 TOOE TOOE 18 1 TSWE TSWE 16 1 WDIE WDIE 26 1 FDCAN_ILE FDCAN_ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 EINT1 EINT1 1 1 FDCAN_ILS FDCAN_ILS This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 BECL BECL 20 1 BEUL BEUL 21 1 BOL BOL 25 1 DRXL DRXL 19 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 HPML HPML 8 1 MRAFL MRAFL 17 1 PEAL PEAL 27 1 PEDL PEDL 28 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 TCFL TCFL 10 1 TCL TCL 9 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TFEL TFEL 11 1 TOOL TOOL 18 1 TSWL TSWL 16 1 WDIL WDIL 26 1 FDCAN_IR FDCAN_IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 BO BO 25 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 HPM HPM 8 1 MRAF MRAF 17 1 PEA PEA 27 1 PED PED 28 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF0N RF0N 0 1 RF0W RF0W 1 1 RF1F RF1F 6 1 RF1L RF1L 7 1 RF1N RF1N 4 1 RF1W RF1W 5 1 TC TC 9 1 TCF TCF 10 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TFE TFE 11 1 TOO TOO 18 1 TSW TSW 16 1 WDI WDI 26 1 FDCAN_NBTP FDCAN_NBTP This register is dedicated to the nominal bit timing used during the arbitration phase. 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 NSJW NSJW 25 7 NTSEG1 NTSEG1 8 8 NTSEG2 NTSEG2 0 7 FDCAN_NDAT1 FDCAN_NDAT1 FDCAN new data 1 register 0x98 32 read-write n 0x0 0x0 ND0 ND0 0 1 ND1 ND1 1 1 ND10 ND10 10 1 ND11 ND11 11 1 ND12 ND12 12 1 ND13 ND13 13 1 ND14 ND14 14 1 ND15 ND15 15 1 ND16 ND16 16 1 ND17 ND17 17 1 ND18 ND18 18 1 ND19 ND19 19 1 ND2 ND2 2 1 ND20 ND20 20 1 ND21 ND21 21 1 ND22 ND22 22 1 ND23 ND23 23 1 ND24 ND24 24 1 ND25 ND25 25 1 ND26 ND26 26 1 ND27 ND27 27 1 ND28 ND28 28 1 ND29 ND29 29 1 ND3 ND3 3 1 ND30 ND30 30 1 ND31 ND31 31 1 ND4 ND4 4 1 ND5 ND5 5 1 ND6 ND6 6 1 ND7 ND7 7 1 ND8 ND8 8 1 ND9 ND9 9 1 FDCAN_NDAT2 FDCAN_NDAT2 FDCAN new data 2 register 0x9C 32 read-write n 0x0 0x0 ND32 ND32 0 1 ND33 ND33 1 1 ND34 ND34 2 1 ND35 ND35 3 1 ND36 ND36 4 1 ND37 ND37 5 1 ND38 ND38 6 1 ND39 ND39 7 1 ND40 ND40 8 1 ND41 ND41 9 1 ND42 ND42 10 1 ND43 ND43 11 1 ND44 ND44 12 1 ND45 ND45 13 1 ND46 ND46 14 1 ND47 ND47 15 1 ND48 ND48 16 1 ND49 ND49 17 1 ND50 ND50 18 1 ND51 ND51 19 1 ND52 ND52 20 1 ND53 ND53 21 1 ND54 ND54 22 1 ND55 ND55 23 1 ND56 ND56 24 1 ND57 ND57 25 1 ND58 ND58 26 1 ND59 ND59 27 1 ND60 ND60 28 1 ND61 ND61 29 1 ND62 ND62 30 1 ND63 ND63 31 1 FDCAN_PSR FDCAN_PSR FDCAN protocol status register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 read-only BO BO 7 1 read-only DLEC DLEC 8 3 read-only EP EP 5 1 read-only EW EW 6 1 read-only LEC LEC 0 3 read-only PXE PXE 14 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write RESI RESI 11 1 read-write TDCV TDCV 16 7 read-only FDCAN_RWD FDCAN_RWD The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only FDCAN_RXBC FDCAN_RXBC FDCAN Rx buffer configuration register 0xAC 32 read-write n 0x0 0x0 RBSA RBSA 2 14 FDCAN_RXESC FDCAN_RXESC Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. 0xBC 32 read-only n 0x0 0x0 F0DS F0DS 0 3 F1DS F1DS 4 3 RBDS RBDS 8 3 FDCAN_RXF0A FDCAN_RXF0A FDCAN Rx FIFO 0 acknowledge register 0xA8 32 read-write n 0x0 0x0 F0AI F0AI 0 6 FDCAN_RXF0C FDCAN_RXF0C FDCAN Rx FIFO 0 configuration register 0xA0 32 read-write n 0x0 0x0 F0OM F0OM 31 1 F0S F0S 16 7 F0SA F0SA 2 14 F0WM F0WM 24 7 FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 status register 0xA4 32 read-write n 0x0 0x0 F0F F0F 24 1 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 RF0L RF0L 25 1 FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 acknowledge register 0xB8 32 read-write n 0x0 0x0 F1AI F1AI 0 6 FDCAN_RXF1C FDCAN_RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 32 read-write n 0x0 0x0 F1OM F1OM 31 1 F1S F1S 16 7 F1SA F1SA 2 14 F1WM F1WM 24 7 FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 status register 0xB4 32 read-only n 0x0 0x0 DMS DMS 30 2 F1F F1F 24 1 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 RF1L RF1L 25 1 FDCAN_SIDFC FDCAN_SIDFC Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708. 0x84 32 read-write n 0x0 0x0 FLSSA FLSSA 2 14 LSS LSS 16 8 FDCAN_TDCR FDCAN_TDCR FDCAN transmitter delay compensation register 0x48 32 read-write n 0x0 0x0 TDCF TDCF 0 7 TDCO TDCO 8 7 FDCAN_TEST FDCAN_TEST Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 read-write RX RX 7 1 read-only TX TX 5 2 read-write FDCAN_TOCC FDCAN_TOCC FDCAN timeout counter configuration register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 TOP TOP 16 16 TOS TOS 1 2 FDCAN_TOCV FDCAN_TOCV FDCAN timeout counter value register 0x2C 32 read-write n 0x0 0x0 TOC TOC 0 16 FDCAN_TSCC FDCAN_TSCC FDCAN timestamp counter configuration register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 TSS TSS 0 2 FDCAN_TSCV FDCAN_TSCV FDCAN timestamp counter value register 0x24 32 read-write n 0x0 0x0 TSC TSC 0 16 FDCAN_TTCPT FDCAN_TTCPT FDCAN TT capture time register 0x13C 32 read-only n 0x0 0x0 CCV CCV 0 6 SWV SWV 16 16 FDCAN_TTCSM FDCAN_TTCSM FDCAN TT cycle sync mark register 0x140 32 read-only n 0x0 0x0 CSM CSM 0 16 FDCAN_TTCTC FDCAN_TTCTC FDCAN TT cycle time and count register 0x138 32 read-only n 0x0 0x0 CC CC 16 6 CT CT 0 16 FDCAN_TTGTP FDCAN_TTGTP If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master. 0x118 32 read-write n 0x0 0x0 CTP CTP 16 16 TP TP 0 16 FDCAN_TTIE FDCAN_TTIE The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt. 0x124 32 read-write n 0x0 0x0 AWE AWE 17 1 CERE CERE 18 1 CSME CSME 2 1 ELCE ELCE 14 1 GTDE GTDE 8 1 GTEE GTEE 9 1 GTWE GTWE 7 1 IWTE IWTE 15 1 RTMIE RTMIE 4 1 SBCE SBCE 0 1 SE1E SE1E 12 1 SE2E SE2E 13 1 SMCE SMCE 1 1 SOGE SOGE 3 1 SWEE SWEE 6 1 TTMIE TTMIE 5 1 TXOE TXOE 11 1 TXUE TXUE 10 1 WTE WTE 16 1 FDCAN_TTILS FDCAN_TTILS The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1. 0x128 32 read-write n 0x0 0x0 AWL AWL 17 1 CERL CERL 18 1 CSML CSML 2 1 ELCL ELCL 14 1 GTDL GTDL 8 1 GTEL GTEL 9 1 GTWL GTWL 7 1 IWTL IWTL 15 1 RTMIL RTMIL 4 1 SBCL SBCL 0 1 SE1L SE1L 12 1 SE2L SE2L 13 1 SMCL SMCL 1 1 SOGL SOGL 3 1 SWEL SWEL 6 1 TTMIL TTMIL 5 1 TXOL TXOL 11 1 TXUL TXUL 10 1 WTL WTL 16 1 FDCAN_TTIR FDCAN_TTIR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. 0x120 32 read-write n 0x0 0x0 AW AW 17 1 CER CER 18 1 CSM CSM 2 1 ELC ELC 14 1 GTD GTD 8 1 GTE GTE 9 1 GTW GTW 7 1 IWTG IWTG 15 1 RTMI RTMI 4 1 SBC SBC 0 1 SE1 SE1 12 1 SE2 SE2 13 1 SMC SMC 1 1 SOG SOG 3 1 SWE SWE 6 1 TTMI TTMI 5 1 TXO TXO 11 1 TXU TXU 10 1 WT WT 16 1 FDCAN_TTLGT FDCAN_TTLGT FDCAN TT local and global time register 0x134 32 read-only n 0x0 0x0 GT GT 16 16 LT LT 0 16 FDCAN_TTMLM FDCAN_TTMLM FDCAN TT matrix limits register 0x10C 32 read-write n 0x0 0x0 CCM CCM 0 6 CSS CSS 6 2 ENTT ENTT 16 12 TXEW TXEW 8 4 FDCAN_TTOCF FDCAN_TTOCF FDCAN TT operation configuration register 0x108 32 read-write n 0x0 0x0 AWL AWL 16 8 ECC ECC 25 1 EECS EECS 15 1 EGTF EGTF 24 1 EVTP EVTP 26 1 GEN GEN 3 1 IRTO IRTO 8 7 LDSDL LDSDL 5 3 OM OM 0 2 TM TM 4 1 FDCAN_TTOCN FDCAN_TTOCN FDCAN TT operation control register 0x114 32 read-write n 0x0 0x0 ECS ECS 1 1 read-write ESCN ESCN 13 1 read-write FGP FGP 10 1 read-write GCS GCS 9 1 read-write LCKC LCKC 15 1 read-only NIG NIG 12 1 read-write RTIE RTIE 5 1 read-write SGT SGT 0 1 read-write SWP SWP 2 1 read-write SWS SWS 3 2 read-write TMC TMC 6 2 read-write TMG TMG 11 1 read-write TTIE TTIE 8 1 read-write FDCAN_TTOST FDCAN_TTOST FDCAN TT operation status register 0x12C 32 read-only n 0x0 0x0 AWE AWE 29 1 EL EL 0 2 GFI GFI 23 1 GSI GSI 27 1 MS MS 2 2 QCS QCS 7 1 QGTP QGTP 6 1 RTO RTO 8 8 SPL SPL 31 1 SYS SYS 4 2 TMP TMP 24 3 WECS WECS 30 1 WFE WFE 28 1 WGTD WGTD 22 1 FDCAN_TTRMC FDCAN_TTRMC FDCAN TT reference message configuration register 0x104 32 read-write n 0x0 0x0 RID RID 0 29 RMPS RMPS 31 1 XTD XTD 30 1 FDCAN_TTTMC FDCAN_TTTMC FDCAN TT trigger memory configuration register 0x100 32 read-write n 0x0 0x0 TME TME 16 7 TMSA TMSA 2 14 FDCAN_TTTMK FDCAN_TTTMK A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM. 0x11C 32 read-write n 0x0 0x0 LCKM LCKM 31 1 read-only TICC TICC 16 7 read-write TM TM 0 16 read-write FDCAN_TTTS FDCAN_TTTS The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger. 0x300 32 read-write n 0x0 0x0 EVTSEL EVTSEL 4 2 SWTDEL SWTDEL 0 2 FDCAN_TURCF FDCAN_TURCF The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process. 0x110 32 read-write n 0x0 0x0 DC DC 16 14 ELT ELT 31 1 NCL NCL 0 16 FDCAN_TURNA FDCAN_TURNA There is no drift compensation in TTCAN level 1. 0x130 32 read-only n 0x0 0x0 NAV NAV 0 18 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx buffer add request register 0xD0 32 read-write n 0x0 0x0 AR AR 0 32 FDCAN_TXBC FDCAN_TXBC FDCAN Tx buffer configuration register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx buffer cancellation finished register 0xDC 32 read-only n 0x0 0x0 CF CF 0 32 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx buffer cancellation finished interrupt enable register 0xE4 32 read-write n 0x0 0x0 CFIE CFIE 0 32 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx buffer cancellation request register 0xD4 32 read-write n 0x0 0x0 CR CR 0 32 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx buffer transmission interrupt enable register 0xE0 32 read-write n 0x0 0x0 TIE TIE 0 32 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx buffer transmission occurred register 0xD8 32 read-only n 0x0 0x0 TO TO 0 32 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx event FIFO acknowledge register 0xF8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 FDCAN_TXEFC FDCAN_TXEFC FDCAN Tx event FIFO configuration register 0xF0 32 read-write n 0x0 0x0 EFS EFS 16 6 EFSA EFSA 2 14 EFWM EFWM 24 6 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx event FIFO status register 0xF4 32 read-only n 0x0 0x0 EFF EFF 24 1 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 TEFL TEFL 25 1 FDCAN_TXESC FDCAN_TXESC Configures the number of data bytes belonging to a Tx buffer element. Data field sizes and gt 8 bytes are intended for CAN FD operation only. 0xC8 32 read-only n 0x0 0x0 TBDS TBDS 0 3 FDCAN_TXFQS FDCAN_TXFQS The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQF TFQF 21 1 TFQPI TFQPI 16 5 FDCAN_XIDAM FDCAN_XIDAM FDCAN extended ID and mask register 0x90 32 read-write n 0x0 0x0 EIDM EIDM 0 29 FDCAN_XIDFC FDCAN_XIDFC Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path. 0x88 32 read-write n 0x0 0x0 FLESA FLESA 2 14 LSE LSE 16 8 FMC FMC register block FMC 0x0 0x0 0x1000 registers n BCHDSR0 FMC_BCHDSR0 This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. . 0x27C 32 read-only n 0x0 0x0 DEF DEF 1 1 DEN DEN 4 4 DUE DUE 0 1 BCHDSR1 FMC_BCHDSR1 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors 0x280 32 read-only n 0x0 0x0 EBP1 EBP1 0 13 EBP2 EBP2 16 13 BCHDSR2 FMC_BCHDSR2 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively. 0x284 32 read-only n 0x0 0x0 EBP3 EBP3 0 13 EBP4 EBP4 16 13 BCHDSR3 FMC_BCHDSR3 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. 0x288 32 read-only n 0x0 0x0 EBP5 EBP5 0 13 EBP6 EBP6 16 13 BCHDSR4 FMC_BCHDSR4 The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. . 0x28C 32 read-only n 0x0 0x0 EBP7 EBP7 0 13 EBP8 EBP8 16 13 BCHICR FMC_BCHICR FMC BCH Interrupt Clear Register 0x258 32 write-only n 0x0 0x0 CDEFF CDEFF 2 1 CDERF CDERF 1 1 CDSRF CDSRF 3 1 CDUEF CDUEF 0 1 CEPBRF CEPBRF 4 1 BCHIER FMC_BCHIER FMC BCH Interrupt enable register 0x250 32 read-write n 0x0 0x0 DEFIE DEFIE 2 1 DERIE DERIE 1 1 DSRIE DSRIE 3 1 DUEIE DUEIE 0 1 EPBRIE EPBRIE 4 1 BCHISR FMC_BCHISR This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared. 0x254 32 read-only n 0x0 0x0 DEFF DEFF 2 1 DERF DERF 1 1 DSRF DSRF 3 1 DUEF DUEF 0 1 EPBRF EPBRF 4 1 BCHPBR1 FMC_BCHPBR1 These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant. 0x260 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR2 FMC_BCHPBR2 FMC BCH Parity Bits Register 2 0x264 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR3 FMC_BCHPBR3 FMC BCH Parity Bits Register 3 0x268 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR4 FMC_BCHPBR4 FMC BCH Parity Bits Register 4 0x26C 32 read-only n 0x0 0x0 BCHPB BCHPB 0 8 BCR1 FMC_BCR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x0 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 CPSIZE CPSIZE 16 3 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 FMCEN FMCEN 31 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 NBLSET NBLSET 22 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WREN WREN 12 1 BCR2 FMC_BCR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x8 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 CPSIZE CPSIZE 16 3 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 FMCEN FMCEN 31 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 NBLSET NBLSET 22 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WREN WREN 12 1 BCR3 FMC_BCR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x10 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 CPSIZE CPSIZE 16 3 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 FMCEN FMCEN 31 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 NBLSET NBLSET 22 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WREN WREN 12 1 BCR4 FMC_BCR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories. 0x18 32 read-write n 0x0 0x0 ASYNCWAIT ASYNCWAIT 15 1 BURSTEN BURSTEN 8 1 CBURSTRW CBURSTRW 19 1 CCLKEN CCLKEN 20 1 CPSIZE CPSIZE 16 3 EXTMOD EXTMOD 14 1 FACCEN FACCEN 6 1 FMCEN FMCEN 31 1 MBKEN MBKEN 0 1 MTYP MTYP 2 2 MUXEN MUXEN 1 1 MWID MWID 4 2 NBLSET NBLSET 22 2 WAITCFG WAITCFG 11 1 WAITEN WAITEN 13 1 WAITPOL WAITPOL 9 1 WREN WREN 12 1 BTR1 FMC_BTR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x4 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR2 FMC_BTR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0xC 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR3 FMC_BTR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x14 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BTR4 FMC_BTR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x1C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 CLKDIV CLKDIV 20 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 DATLAT DATLAT 24 4 BWTR1 FMC_BWTR1 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 BWTR2 FMC_BWTR2 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x10C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 BWTR3 FMC_BWTR3 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x114 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 BWTR4 FMC_BWTR4 This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x11C 32 read-write n 0x0 0x0 ACCMOD ACCMOD 28 2 ADDHLD ADDHLD 4 4 ADDSET ADDSET 0 4 BUSTURN BUSTURN 16 4 DATAHLD DATAHLD 30 2 DATAST DATAST 8 8 CSQAR1 FMC_CSQAR1 This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer. 0x210 32 read-write n 0x0 0x0 ADDC1 ADDC1 0 8 ADDC2 ADDC2 8 8 ADDC3 ADDC3 16 8 ADDC4 ADDC4 24 8 CSQAR2 FMC_CSQAR2 This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable. 0x214 32 read-write n 0x0 0x0 ADDC5 ADDC5 0 8 NANDCEN0 NANDCEN0 10 1 NANDCEN1 NANDCEN1 11 1 SAO SAO 16 16 CSQCFGR1 FMC_CSQCFGR1 FMC NAND Command Sequencer Configuration Register 1 0x204 32 read-write n 0x0 0x0 ACYNBR ACYNBR 4 3 CMD1 CMD1 8 8 CMD1T CMD1T 24 1 CMD2 CMD2 16 8 CMD2EN CMD2EN 1 1 CMD2T CMD2T 25 1 DMADEN DMADEN 2 1 CSQCFGR2 FMC_CSQCFGR2 This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. . 0x208 32 read-write n 0x0 0x0 DMASEN DMASEN 2 1 RCMD1 RCMD1 8 8 RCMD1T RCMD1T 24 1 RCMD2 RCMD2 16 8 RCMD2EN RCMD2EN 1 1 RCMD2T RCMD2T 25 1 SQSDTEN SQSDTEN 0 1 CSQCFGR3 FMC_CSQCFGR3 FMC NAND sequencer configuration register 3 0x20C 32 read-write n 0x0 0x0 AC1T AC1T 16 1 AC2T AC2T 17 1 AC3T AC3T 18 1 AC4T AC4T 19 1 AC5T AC5T 20 1 RAC1T RAC1T 22 1 RAC2T RAC2T 23 1 SDT SDT 21 1 SNBR SNBR 8 6 CSQCR FMC_CSQCR FMC NAND Command Sequencer Control Register 0x200 32 write-only n 0x0 0x0 CSQSTART CSQSTART 0 1 CSQEMSR FMC_CSQEMSR This register holds a sector error mapping status when the whole transfer is complete. 0x230 32 read-only n 0x0 0x0 SEM SEM 0 16 CSQICR FMC_CSQICR FMC NAND Command Sequencer Interrupt Clear Register 0x228 32 write-only n 0x0 0x0 CCMDTCF CCMDTCF 4 1 CSCF CSCF 1 1 CSEF CSEF 2 1 CSUEF CSUEF 3 1 CTCF CTCF 0 1 CSQIER FMC_CSQIER FMC NAND Command Sequencer Interrupt Enable Register 0x220 32 read-write n 0x0 0x0 CMDTCIE CMDTCIE 4 1 SCIE SCIE 1 1 SEIE SEIE 2 1 SUEIE SUEIE 3 1 TCIE TCIE 0 1 CSQISR FMC_CSQISR FMC NAND Command Sequencer Interrupt Status Register 0x224 32 read-write n 0x0 0x0 CMDTCF CMDTCF 4 1 SCF SCF 1 1 SEF SEF 2 1 SUEF SUEF 3 1 TCF TCF 0 1 HECCR FMC_HECCR This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 32 read-only n 0x0 0x0 HECC HECC 0 32 HPR FMC_HPR This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x90 32 read-only n 0x0 0x0 HPR HPR 0 32 HWCFGR1 FMC_HWCFGR1 FMC Hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 ID_SIZE ID_SIZE 12 4 NAND_ECC NAND_ECC 4 1 NAND_SEL NAND_SEL 0 1 RA_LN2DPTH RA_LN2DPTH 28 4 SDRAM_SEL SDRAM_SEL 8 1 WA_LN2DPTH WA_LN2DPTH 16 4 WD_LN2DPTH WD_LN2DPTH 20 4 WR_LN2DPTH WR_LN2DPTH 24 4 HWCFGR2 FMC_HWCFGR2 FMC Hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 NAND_BASE NAND_BASE 12 4 NOR_BASE NOR_BASE 4 4 RD_LN2DPTH RD_LN2DPTH 0 4 SDRAM1_BASE SDRAM1_BASE 16 4 SDRAM2_BASE SDRAM2_BASE 20 4 SDRAM_RBASE SDRAM_RBASE 8 4 IPIDR FMC_IPIDR FMC Identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 PATT FMC_PATT The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function). 0x8C 32 read-write n 0x0 0x0 ATTHIZ ATTHIZ 24 8 ATTHOLD ATTHOLD 16 8 ATTSET ATTSET 0 8 ATTWAIT ATTWAIT 8 8 PCR FMC_PCR NAND Flash Programmable control register 0x80 32 read-write n 0x0 0x0 BCHECC BCHECC 24 1 ECCALG ECCALG 8 1 ECCEN ECCEN 6 1 ECCSS ECCSS 17 3 PBKEN PBKEN 2 1 PWAITEN PWAITEN 1 1 PWID PWID 4 2 TAR TAR 13 4 TCEH TCEH 20 4 TCLR TCLR 9 4 WEN WEN 25 1 PCSCNTR FMC_PCSCNTR This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h 0x20 32 read-write n 0x0 0x0 CNTB1EN CNTB1EN 16 1 CNTB2EN CNTB2EN 17 1 CNTB3EN CNTB3EN 18 1 CNTB4EN CNTB4EN 19 1 CSCOUNT CSCOUNT 0 16 PMEM FMC_PMEM The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses. 0x88 32 read-write n 0x0 0x0 MEMHIZ MEMHIZ 24 8 MEMHOLD MEMHOLD 16 8 MEMSET MEMSET 0 8 MEMWAIT MEMWAIT 8 8 SIDR FMC_SIDR FMC Size Identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SR FMC_SR This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits. 0x84 32 read-only n 0x0 0x0 ISOST ISOST 0 2 NWRF NWRF 6 1 PEF PEF 4 1 VERR FMC_VERR FMC Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GICC GICC GICC 0x0 0x0 0x2000 registers n ABPR GICC_ABPR GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR. 0x1C 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 AEOIR GICC_AEOIR GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used. 0x24 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 AHPPIR GICC_AHPPIR ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR. 0x28 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 AIAR GICC_AIAR GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR. 0x20 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 APR0 GICC_APR0 GICC active priority register 0xD0 32 read-write n 0x0 0x0 APR0 APR0 0 32 BPR GICC_BPR GICC binary point register 0x8 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 CTLR GICC_CTLR GICC control register 0x0 32 read-write n 0x0 0x0 ACKCTL ACKCTL 2 1 CBPR CBPR 4 1 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 EOIMODENS EOIMODENS 10 1 EOIMODES EOIMODES 9 1 FIQBYPDISGRP0 FIQBYPDISGRP0 5 1 FIQBYPDISGRP1 FIQBYPDISGRP1 7 1 FIQEN FIQEN 3 1 IRQBYPDISGRP0 IRQBYPDISGRP0 6 1 IRQBYPDISGRP1 IRQBYPDISGRP1 8 1 DIR GICC_DIR GICC deactivate interrupt register 0x1000 32 write-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 EOIR GICC_EOIR GICC end of interrupt register 0x10 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 HPPIR GICC_HPPIR GICC highest priority pending interrupt register 0x18 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 IAR GICC_IAR GICC interrupt acknowledge register 0xC 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 IIDR GICC_IIDR GICC interface identification register 0xFC 32 read-only n 0x0 0x0 ARCH ARCH 16 4 IMPLEMENTER IMPLEMENTER 0 12 PRODUCTID PRODUCTID 20 12 REVISION REVISION 12 4 NSAPR0 GICC_NSAPR0 GICC non-secure active priority register 0xE0 32 read-write n 0x0 0x0 NSAPR0 NSAPR0 0 32 PMR GICC_PMR GICC input priority mask register 0x4 32 read-write n 0x0 0x0 PRIORITY PRIORITY 3 5 RPR GICC_RPR GICC running priority register 0x14 32 read-only n 0x0 0x0 PRIORITY PRIORITY 3 5 GICD GICD GICD 0x0 0x0 0x1000 registers n CIDR0 GICD_CIDR0 GICD component ID0 register 0xFF0 32 read-only n 0x0 0x0 CIDR0 CIDR0 0 32 CIDR1 GICD_CIDR1 GICD component ID1 register 0xFF4 32 read-only n 0x0 0x0 CIDR1 CIDR1 0 32 CIDR2 GICD_CIDR2 GICD component ID2 register 0xFF8 32 read-only n 0x0 0x0 CIDR2 CIDR2 0 32 CIDR3 GICD_CIDR3 GICD component ID3 register 0xFFC 32 read-only n 0x0 0x0 CIDR3 CIDR3 0 32 CPENDSGIR0 GICD_CPENDSGIR0 For SGI x*4 to SGI x*4+3 0xF10 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR1 GICD_CPENDSGIR1 For SGI x*4 to SGI x*4+3 0xF14 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR2 GICD_CPENDSGIR2 For SGI x*4 to SGI x*4+3 0xF18 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CPENDSGIR3 GICD_CPENDSGIR3 For SGI x*4 to SGI x*4+3 0xF1C 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 SGI_CLEAR_PENDING0 0 2 SGI_CLEAR_PENDING1 SGI_CLEAR_PENDING1 8 2 SGI_CLEAR_PENDING2 SGI_CLEAR_PENDING2 16 2 SGI_CLEAR_PENDING3 SGI_CLEAR_PENDING3 24 2 CTLR GICD_CTLR GICD control register 0x0 32 read-write n 0x0 0x0 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 ICACTIVER0 GICD_ICACTIVER0 For interrupts ID 0x380 32 read-write n 0x0 0x0 ICACTIVER0 ICACTIVER0 0 32 ICACTIVER1 GICD_ICACTIVER1 For interrupts ID 0x384 32 read-write n 0x0 0x0 ICACTIVER1 ICACTIVER1 0 32 ICACTIVER2 GICD_ICACTIVER2 For interrupts ID 0x388 32 read-write n 0x0 0x0 ICACTIVER2 ICACTIVER2 0 32 ICACTIVER3 GICD_ICACTIVER3 For interrupts ID 0x38C 32 read-write n 0x0 0x0 ICACTIVER3 ICACTIVER3 0 32 ICACTIVER4 GICD_ICACTIVER4 For interrupts ID 0x390 32 read-write n 0x0 0x0 ICACTIVER4 ICACTIVER4 0 32 ICACTIVER5 GICD_ICACTIVER5 For interrupts ID 0x394 32 read-write n 0x0 0x0 ICACTIVER5 ICACTIVER5 0 32 ICACTIVER6 GICD_ICACTIVER6 For interrupts ID 0x398 32 read-write n 0x0 0x0 ICACTIVER6 ICACTIVER6 0 32 ICACTIVER7 GICD_ICACTIVER7 For interrupts ID 0x39C 32 read-write n 0x0 0x0 ICACTIVER7 ICACTIVER7 0 32 ICACTIVER8 GICD_ICACTIVER8 For interrupts ID 0x3A0 32 read-write n 0x0 0x0 ICACTIVER8 ICACTIVER8 0 32 ICENABLER0 GICD_ICENABLER0 For interrupts ID = 0 to ID = 31 0x180 32 read-write n 0x0 0x0 ICENABLER0 ICENABLER0 0 32 ICENABLER1 GICD_ICENABLER1 For interrupts ID 0x184 32 read-write n 0x0 0x0 ICENABLER1 ICENABLER1 0 32 ICENABLER2 GICD_ICENABLER2 For interrupts ID 0x188 32 read-write n 0x0 0x0 ICENABLER2 ICENABLER2 0 32 ICENABLER3 GICD_ICENABLER3 For interrupts ID 0x18C 32 read-write n 0x0 0x0 ICENABLER3 ICENABLER3 0 32 ICENABLER4 GICD_ICENABLER4 For interrupts ID 0x190 32 read-write n 0x0 0x0 ICENABLER4 ICENABLER4 0 32 ICENABLER5 GICD_ICENABLER5 For interrupts ID 0x194 32 read-write n 0x0 0x0 ICENABLER5 ICENABLER5 0 32 ICENABLER6 GICD_ICENABLER6 For interrupts ID 0x198 32 read-write n 0x0 0x0 ICENABLER6 ICENABLER6 0 32 ICENABLER7 GICD_ICENABLER7 For interrupts ID 0x19C 32 read-write n 0x0 0x0 ICENABLER7 ICENABLER7 0 32 ICENABLER8 GICD_ICENABLER8 For interrupts ID 0x1A0 32 read-write n 0x0 0x0 ICENABLER8 ICENABLER8 0 32 ICFGR0 GICD_ICFGR0 GICD interrupt configuration register 0xC00 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR1 GICD_ICFGR1 GICD interrupt configuration register 0xC04 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR10 GICD_ICFGR10 GICD interrupt configuration register 10 0xC28 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR11 GICD_ICFGR11 GICD interrupt configuration register 11 0xC2C 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR12 GICD_ICFGR12 GICD interrupt configuration register 12 0xC30 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR13 GICD_ICFGR13 GICD interrupt configuration register 13 0xC34 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR14 GICD_ICFGR14 GICD interrupt configuration register 14 0xC38 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR15 GICD_ICFGR15 GICD interrupt configuration register 15 0xC3C 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR16 GICD_ICFGR16 GICD interrupt configuration register 16 0xC40 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR17 GICD_ICFGR17 GICD interrupt configuration register 17 0xC44 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR2 GICD_ICFGR2 GICD interrupt configuration register 2 0xC08 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR3 GICD_ICFGR3 GICD interrupt configuration register 3 0xC0C 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR4 GICD_ICFGR4 GICD interrupt configuration register 4 0xC10 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR5 GICD_ICFGR5 GICD interrupt configuration register 5 0xC14 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR6 GICD_ICFGR6 GICD interrupt configuration register 6 0xC18 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR7 GICD_ICFGR7 GICD interrupt configuration register 7 0xC1C 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR8 GICD_ICFGR8 GICD interrupt configuration register 8 0xC20 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICFGR9 GICD_ICFGR9 GICD interrupt configuration register 9 0xC24 32 read-write n 0x0 0x0 INT_CONFIG0 INT_CONFIG0 0 2 INT_CONFIG1 INT_CONFIG1 2 2 INT_CONFIG10 INT_CONFIG10 20 2 INT_CONFIG11 INT_CONFIG11 22 2 INT_CONFIG12 INT_CONFIG12 24 2 INT_CONFIG13 INT_CONFIG13 26 2 INT_CONFIG14 INT_CONFIG14 28 2 INT_CONFIG15 INT_CONFIG15 30 2 INT_CONFIG2 INT_CONFIG2 4 2 INT_CONFIG3 INT_CONFIG3 6 2 INT_CONFIG4 INT_CONFIG4 8 2 INT_CONFIG5 INT_CONFIG5 10 2 INT_CONFIG6 INT_CONFIG6 12 2 INT_CONFIG7 INT_CONFIG7 14 2 INT_CONFIG8 INT_CONFIG8 16 2 INT_CONFIG9 INT_CONFIG9 18 2 ICPENDR0 GICD_ICPENDR0 For interrupts ID 0x280 32 read-write n 0x0 0x0 ICPENDR0 ICPENDR0 0 32 ICPENDR1 GICD_ICPENDR1 For interrupts ID 0x284 32 read-write n 0x0 0x0 ICPENDR1 ICPENDR1 0 32 ICPENDR2 GICD_ICPENDR2 For interrupts ID 0x288 32 read-write n 0x0 0x0 ICPENDR2 ICPENDR2 0 32 ICPENDR3 GICD_ICPENDR3 For interrupts ID 0x28C 32 read-write n 0x0 0x0 ICPENDR3 ICPENDR3 0 32 ICPENDR4 GICD_ICPENDR4 For interrupts ID 0x290 32 read-write n 0x0 0x0 ICPENDR4 ICPENDR4 0 32 ICPENDR5 GICD_ICPENDR5 For interrupts ID 0x294 32 read-write n 0x0 0x0 ICPENDR5 ICPENDR5 0 32 ICPENDR6 GICD_ICPENDR6 For interrupts ID 0x298 32 read-write n 0x0 0x0 ICPENDR6 ICPENDR6 0 32 ICPENDR7 GICD_ICPENDR7 For interrupts ID 0x29C 32 read-write n 0x0 0x0 ICPENDR7 ICPENDR7 0 32 ICPENDR8 GICD_ICPENDR8 For interrupts ID 0x2A0 32 read-write n 0x0 0x0 ICPENDR8 ICPENDR8 0 32 IGROUPR0 GICD_IGROUPR0 For interrupts ID 0x80 32 read-write n 0x0 0x0 IGROUPR0 IGROUPR0 0 32 IGROUPR1 GICD_IGROUPR1 For interrupts ID 0x84 32 read-write n 0x0 0x0 IGROUPR1 IGROUPR1 0 32 IGROUPR2 GICD_IGROUPR2 For interrupts ID 0x88 32 read-write n 0x0 0x0 IGROUPR2 IGROUPR2 0 32 IGROUPR3 GICD_IGROUPR3 For interrupts ID = x*32 to ID = x*32+31 0x8C 32 read-write n 0x0 0x0 IGROUPR3 IGROUPR3 0 32 IGROUPR4 GICD_IGROUPR4 For interrupts ID = x*32 to ID = x*32+31 0x90 32 read-write n 0x0 0x0 IGROUPR4 IGROUPR4 0 32 IGROUPR5 GICD_IGROUPR5 For interrupts ID 0x94 32 read-write n 0x0 0x0 IGROUPR5 IGROUPR5 0 32 IGROUPR6 GICD_IGROUPR6 For interrupts ID 0x98 32 read-write n 0x0 0x0 IGROUPR6 IGROUPR6 0 32 IGROUPR7 GICD_IGROUPR7 For interrupts ID 0x9C 32 read-write n 0x0 0x0 IGROUPR7 IGROUPR7 0 32 IGROUPR8 GICD_IGROUPR8 For interrupts ID 0xA0 32 read-write n 0x0 0x0 IGROUPR8 IGROUPR8 0 32 IIDR GICD_IIDR GICD implementer identification register 0x8 32 read-only n 0x0 0x0 IMPLEMENTER IMPLEMENTER 0 12 PRODUCTID PRODUCTID 24 8 REVISION REVISION 16 4 VARIANT VARIANT 12 4 IPRIORITYR0 GICD_IPRIORITYR0 GICD interrupt priority register 0 0x400 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR1 GICD_IPRIORITYR1 GICD interrupt priority register 1 0x404 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR10 GICD_IPRIORITYR10 GICD interrupt priority register 10 0x428 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR11 GICD_IPRIORITYR11 GICD interrupt priority register 11 0x42C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR12 GICD_IPRIORITYR12 GICD interrupt priority register 12 0x430 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR13 GICD_IPRIORITYR13 GICD interrupt priority register 13 0x434 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR14 GICD_IPRIORITYR14 GICD interrupt priority register 14 0x438 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR15 GICD_IPRIORITYR15 GICD interrupt priority register 15 0x43C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR16 GICD_IPRIORITYR16 GICD interrupt priority register 16 0x440 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR17 GICD_IPRIORITYR17 GICD interrupt priority register 17 0x444 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR18 GICD_IPRIORITYR18 GICD interrupt priority register 18 0x448 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR19 GICD_IPRIORITYR19 GICD interrupt priority register 19 0x44C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR2 GICD_IPRIORITYR2 GICD interrupt priority register 2 0x408 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR20 GICD_IPRIORITYR20 GICD interrupt priority register 20 0x450 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR21 GICD_IPRIORITYR21 GICD interrupt priority register 21 0x454 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR22 GICD_IPRIORITYR22 GICD interrupt priority register 22 0x458 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR23 GICD_IPRIORITYR23 GICD interrupt priority register 23 0x45C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR24 GICD_IPRIORITYR24 GICD interrupt priority register 24 0x460 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR25 GICD_IPRIORITYR25 GICD interrupt priority register 25 0x464 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR26 GICD_IPRIORITYR26 GICD interrupt priority register 26 0x468 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR27 GICD_IPRIORITYR27 GICD interrupt priority register 27 0x46C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR28 GICD_IPRIORITYR28 GICD interrupt priority register 28 0x470 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR29 GICD_IPRIORITYR29 GICD interrupt priority register 29 0x474 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR3 GICD_IPRIORITYR3 GICD interrupt priority register 3 0x40C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR30 GICD_IPRIORITYR30 GICD interrupt priority register 30 0x478 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR31 GICD_IPRIORITYR31 GICD interrupt priority register 31 0x47C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR32 GICD_IPRIORITYR32 GICD interrupt priority register 32 0x480 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR33 GICD_IPRIORITYR33 GICD interrupt priority register 33 0x484 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR34 GICD_IPRIORITYR34 GICD interrupt priority register 34 0x488 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR35 GICD_IPRIORITYR35 GICD interrupt priority register 35 0x48C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR36 GICD_IPRIORITYR36 GICD interrupt priority register 36 0x490 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR37 GICD_IPRIORITYR37 GICD interrupt priority register 37 0x494 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR38 GICD_IPRIORITYR38 GICD interrupt priority register 38 0x498 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR39 GICD_IPRIORITYR39 GICD interrupt priority register 39 0x49C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR4 GICD_IPRIORITYR4 GICD interrupt priority register 4 0x410 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR40 GICD_IPRIORITYR40 GICD interrupt priority register 40 0x4A0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR41 GICD_IPRIORITYR41 GICD interrupt priority register 41 0x4A4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR42 GICD_IPRIORITYR42 GICD interrupt priority register 42 0x4A8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR43 GICD_IPRIORITYR43 GICD interrupt priority register 43 0x4AC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR44 GICD_IPRIORITYR44 GICD interrupt priority register 44 0x4B0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR45 GICD_IPRIORITYR45 GICD interrupt priority register 45 0x4B4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR46 GICD_IPRIORITYR46 GICD interrupt priority register 46 0x4B8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR47 GICD_IPRIORITYR47 GICD interrupt priority register 47 0x4BC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR48 GICD_IPRIORITYR48 GICD interrupt priority register 48 0x4C0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR49 GICD_IPRIORITYR49 GICD interrupt priority register 49 0x4C4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR5 GICD_IPRIORITYR5 GICD interrupt priority register 5 0x414 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR50 GICD_IPRIORITYR50 GICD interrupt priority register 50 0x4C8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR51 GICD_IPRIORITYR51 GICD interrupt priority register 51 0x4CC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR52 GICD_IPRIORITYR52 GICD interrupt priority register 52 0x4D0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR53 GICD_IPRIORITYR53 GICD interrupt priority register 53 0x4D4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR54 GICD_IPRIORITYR54 GICD interrupt priority register 54 0x4D8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR55 GICD_IPRIORITYR55 GICD interrupt priority register 55 0x4DC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR56 GICD_IPRIORITYR56 GICD interrupt priority register 56 0x4E0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR57 GICD_IPRIORITYR57 GICD interrupt priority register 57 0x4E4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR58 GICD_IPRIORITYR58 GICD interrupt priority register 58 0x4E8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR59 GICD_IPRIORITYR59 GICD interrupt priority register 59 0x4EC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR6 GICD_IPRIORITYR6 GICD interrupt priority register 6 0x418 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR60 GICD_IPRIORITYR60 GICD interrupt priority register 60 0x4F0 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR61 GICD_IPRIORITYR61 GICD interrupt priority register 61 0x4F4 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR62 GICD_IPRIORITYR62 GICD interrupt priority register 62 0x4F8 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR63 GICD_IPRIORITYR63 GICD interrupt priority register 63 0x4FC 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR64 GICD_IPRIORITYR64 GICD interrupt priority register 64 0x500 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR65 GICD_IPRIORITYR65 GICD interrupt priority register 65 0x504 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR66 GICD_IPRIORITYR66 GICD interrupt priority register 66 0x508 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR67 GICD_IPRIORITYR67 GICD interrupt priority register 67 0x50C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR68 GICD_IPRIORITYR68 GICD interrupt priority register 68 0x510 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR69 GICD_IPRIORITYR69 GICD interrupt priority register 69 0x514 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR7 GICD_IPRIORITYR7 GICD interrupt priority register 7 0x41C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR70 GICD_IPRIORITYR70 GICD interrupt priority register 70 0x518 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR71 GICD_IPRIORITYR71 GICD interrupt priority register 71 0x51C 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR8 GICD_IPRIORITYR8 GICD interrupt priority register 8 0x420 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 IPRIORITYR9 GICD_IPRIORITYR9 GICD interrupt priority register 9 0x424 32 read-write n 0x0 0x0 PRIORITY0 PRIORITY0 3 5 PRIORITY1 PRIORITY1 11 5 PRIORITY2 PRIORITY2 19 5 PRIORITY3 PRIORITY3 27 5 ISACTIVER0 GICD_ISACTIVER0 For interrupts ID 0x300 32 read-write n 0x0 0x0 ISACTIVER0 ISACTIVER0 0 32 ISACTIVER1 GICD_ISACTIVER1 For interrupts ID 0x304 32 read-write n 0x0 0x0 ISACTIVER1 ISACTIVER1 0 32 ISACTIVER2 GICD_ISACTIVER2 For interrupts ID 0x308 32 read-write n 0x0 0x0 ISACTIVER2 ISACTIVER2 0 32 ISACTIVER3 GICD_ISACTIVER3 For interrupts ID 0x30C 32 read-write n 0x0 0x0 ISACTIVER3 ISACTIVER3 0 32 ISACTIVER4 GICD_ISACTIVER4 For interrupts ID 0x310 32 read-write n 0x0 0x0 ISACTIVER4 ISACTIVER4 0 32 ISACTIVER5 GICD_ISACTIVER5 For interrupts ID 0x314 32 read-write n 0x0 0x0 ISACTIVER5 ISACTIVER5 0 32 ISACTIVER6 GICD_ISACTIVER6 For interrupts ID 0x318 32 read-write n 0x0 0x0 ISACTIVER6 ISACTIVER6 0 32 ISACTIVER7 GICD_ISACTIVER7 For interrupts ID 0x31C 32 read-write n 0x0 0x0 ISACTIVER7 ISACTIVER7 0 32 ISACTIVER8 GICD_ISACTIVER8 For interrupts ID 0x320 32 read-write n 0x0 0x0 ISACTIVER8 ISACTIVER8 0 32 ISENABLER0 GICD_ISENABLER0 For interrupts ID = 0 to ID = 31 0x100 32 read-write n 0x0 0x0 ISENABLER0 ISENABLER0 0 32 ISENABLER1 GICD_ISENABLER1 For interrupts ID 0x104 32 read-write n 0x0 0x0 ISENABLER1 ISENABLER1 0 32 ISENABLER2 GICD_ISENABLER2 For interrupts ID 0x108 32 read-write n 0x0 0x0 ISENABLER2 ISENABLER2 0 32 ISENABLER3 GICD_ISENABLER3 For interrupts ID 0x10C 32 read-write n 0x0 0x0 ISENABLER3 ISENABLER3 0 32 ISENABLER4 GICD_ISENABLER4 For interrupts ID 0x110 32 read-write n 0x0 0x0 ISENABLER4 ISENABLER4 0 32 ISENABLER5 GICD_ISENABLER5 For interrupts ID 0x114 32 read-write n 0x0 0x0 ISENABLER5 ISENABLER5 0 32 ISENABLER6 GICD_ISENABLER6 For interrupts ID 0x118 32 read-write n 0x0 0x0 ISENABLER6 ISENABLER6 0 32 ISENABLER7 GICD_ISENABLER7 For interrupts ID 0x11C 32 read-write n 0x0 0x0 ISENABLER7 ISENABLER7 0 32 ISENABLER8 GICD_ISENABLER8 For interrupts ID 0x120 32 read-write n 0x0 0x0 ISENABLER8 ISENABLER8 0 32 ISPENDR0 GICD_ISPENDR0 For interrupts ID 0x200 32 read-write n 0x0 0x0 ISPENDR0 ISPENDR0 0 32 ISPENDR1 GICD_ISPENDR1 For interrupts ID 0x204 32 read-write n 0x0 0x0 ISPENDR1 ISPENDR1 0 32 ISPENDR2 GICD_ISPENDR2 For interrupts ID 0x208 32 read-write n 0x0 0x0 ISPENDR2 ISPENDR2 0 32 ISPENDR3 GICD_ISPENDR3 For interrupts ID 0x20C 32 read-write n 0x0 0x0 ISPENDR3 ISPENDR3 0 32 ISPENDR4 GICD_ISPENDR4 For interrupts ID 0x210 32 read-write n 0x0 0x0 ISPENDR4 ISPENDR4 0 32 ISPENDR5 GICD_ISPENDR5 For interrupts ID 0x214 32 read-write n 0x0 0x0 ISPENDR5 ISPENDR5 0 32 ISPENDR6 GICD_ISPENDR6 For interrupts ID 0x218 32 read-write n 0x0 0x0 ISPENDR6 ISPENDR6 0 32 ISPENDR7 GICD_ISPENDR7 For interrupts ID 0x21C 32 read-write n 0x0 0x0 ISPENDR7 ISPENDR7 0 32 ISPENDR8 GICD_ISPENDR8 For interrupts ID 0x220 32 read-write n 0x0 0x0 ISPENDR8 ISPENDR8 0 32 ITARGETSR0 GICD_ITARGETSR0 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x800 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR1 GICD_ITARGETSR1 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x804 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR10 GICD_ITARGETSR10 GICD interrupt processor target register 10 0x828 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR11 GICD_ITARGETSR11 GICD interrupt processor target register 11 0x82C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR12 GICD_ITARGETSR12 GICD interrupt processor target register 12 0x830 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR13 GICD_ITARGETSR13 GICD interrupt processor target register 13 0x834 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR14 GICD_ITARGETSR14 GICD interrupt processor target register 14 0x838 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR15 GICD_ITARGETSR15 GICD interrupt processor target register 15 0x83C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR16 GICD_ITARGETSR16 GICD interrupt processor target register 16 0x840 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR17 GICD_ITARGETSR17 GICD interrupt processor target register 17 0x844 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR18 GICD_ITARGETSR18 GICD interrupt processor target register 18 0x848 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR19 GICD_ITARGETSR19 GICD interrupt processor target register 19 0x84C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR2 GICD_ITARGETSR2 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x808 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR20 GICD_ITARGETSR20 GICD interrupt processor target register 20 0x850 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR21 GICD_ITARGETSR21 GICD interrupt processor target register 21 0x854 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR22 GICD_ITARGETSR22 GICD interrupt processor target register 22 0x858 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR23 GICD_ITARGETSR23 GICD interrupt processor target register 23 0x85C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR24 GICD_ITARGETSR24 GICD interrupt processor target register 24 0x860 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR25 GICD_ITARGETSR25 GICD interrupt processor target register 25 0x864 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR26 GICD_ITARGETSR26 GICD interrupt processor target register 26 0x868 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR27 GICD_ITARGETSR27 GICD interrupt processor target register 27 0x86C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR28 GICD_ITARGETSR28 GICD interrupt processor target register 28 0x870 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR29 GICD_ITARGETSR29 GICD interrupt processor target register 29 0x874 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR3 GICD_ITARGETSR3 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x80C 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR30 GICD_ITARGETSR30 GICD interrupt processor target register 30 0x878 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR31 GICD_ITARGETSR31 GICD interrupt processor target register 31 0x87C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR32 GICD_ITARGETSR32 GICD interrupt processor target register 32 0x880 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR33 GICD_ITARGETSR33 GICD interrupt processor target register 33 0x884 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR34 GICD_ITARGETSR34 GICD interrupt processor target register 34 0x888 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR35 GICD_ITARGETSR35 GICD interrupt processor target register 35 0x88C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR36 GICD_ITARGETSR36 GICD interrupt processor target register 36 0x890 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR37 GICD_ITARGETSR37 GICD interrupt processor target register 37 0x894 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR38 GICD_ITARGETSR38 GICD interrupt processor target register 38 0x898 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR39 GICD_ITARGETSR39 GICD interrupt processor target register 39 0x89C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR4 GICD_ITARGETSR4 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x810 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR40 GICD_ITARGETSR40 GICD interrupt processor target register 40 0x8A0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR41 GICD_ITARGETSR41 GICD interrupt processor target register 41 0x8A4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR42 GICD_ITARGETSR42 GICD interrupt processor target register 42 0x8A8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR43 GICD_ITARGETSR43 GICD interrupt processor target register 43 0x8AC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR44 GICD_ITARGETSR44 GICD interrupt processor target register 44 0x8B0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR45 GICD_ITARGETSR45 GICD interrupt processor target register 45 0x8B4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR46 GICD_ITARGETSR46 GICD interrupt processor target register 46 0x8B8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR47 GICD_ITARGETSR47 GICD interrupt processor target register 47 0x8BC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR48 GICD_ITARGETSR48 GICD interrupt processor target register 48 0x8C0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR49 GICD_ITARGETSR49 GICD interrupt processor target register 49 0x8C4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR5 GICD_ITARGETSR5 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x814 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR50 GICD_ITARGETSR50 GICD interrupt processor target register 50 0x8C8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR51 GICD_ITARGETSR51 GICD interrupt processor target register 51 0x8CC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR52 GICD_ITARGETSR52 GICD interrupt processor target register 52 0x8D0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR53 GICD_ITARGETSR53 GICD interrupt processor target register 53 0x8D4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR54 GICD_ITARGETSR54 GICD interrupt processor target register 54 0x8D8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR55 GICD_ITARGETSR55 GICD interrupt processor target register 55 0x8DC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR56 GICD_ITARGETSR56 GICD interrupt processor target register 56 0x8E0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR57 GICD_ITARGETSR57 GICD interrupt processor target register 57 0x8E4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR58 GICD_ITARGETSR58 GICD interrupt processor target register 58 0x8E8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR59 GICD_ITARGETSR59 GICD interrupt processor target register 59 0x8EC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR6 GICD_ITARGETSR6 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x818 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR60 GICD_ITARGETSR60 GICD interrupt processor target register 60 0x8F0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR61 GICD_ITARGETSR61 GICD interrupt processor target register 61 0x8F4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR62 GICD_ITARGETSR62 GICD interrupt processor target register 62 0x8F8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR63 GICD_ITARGETSR63 GICD interrupt processor target register 63 0x8FC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR64 GICD_ITARGETSR64 GICD interrupt processor target register 64 0x900 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR65 GICD_ITARGETSR65 GICD interrupt processor target register 65 0x904 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR66 GICD_ITARGETSR66 GICD interrupt processor target register 66 0x908 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR67 GICD_ITARGETSR67 GICD interrupt processor target register 67 0x90C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR68 GICD_ITARGETSR68 GICD interrupt processor target register 68 0x910 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR69 GICD_ITARGETSR69 GICD interrupt processor target register 69 0x914 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR7 GICD_ITARGETSR7 For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read. 0x81C 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR70 GICD_ITARGETSR70 GICD interrupt processor target register 70 0x918 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR71 GICD_ITARGETSR71 GICD interrupt processor target register 71 0x91C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR8 GICD_ITARGETSR8 GICD interrupt processor target register 8 0x820 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 ITARGETSR9 GICD_ITARGETSR9 GICD interrupt processor target register 9 0x824 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU_TARGETS0 0 2 CPU_TARGETS1 CPU_TARGETS1 8 2 CPU_TARGETS2 CPU_TARGETS2 16 2 CPU_TARGETS3 CPU_TARGETS3 24 2 PIDR0 GICD_PIDR0 GICD peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PIDR0 PIDR0 0 32 PIDR1 GICD_PIDR1 GICD peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 PIDR1 PIDR1 0 32 PIDR2 GICD_PIDR2 GICD peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 PIDR2 PIDR2 0 32 PIDR3 GICD_PIDR3 GICD peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 PIDR3 PIDR3 0 32 PIDR4 GICD_PIDR4 GICD peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 PIDR4 PIDR4 0 32 PIDR5 GICD_PIDR5 GICD peripheral ID5 to ID7 register 5 0xFD4 32 read-only n 0x0 0x0 PIDR5 PIDR5 0 32 PIDR6 GICD_PIDR6 GICD peripheral ID5 to ID7 register 6 0xFD8 32 read-only n 0x0 0x0 PIDR6 PIDR6 0 32 PIDR7 GICD_PIDR7 GICD peripheral ID5 to ID7 register 7 0xFDC 32 read-only n 0x0 0x0 PIDR7 PIDR7 0 32 PPISR GICD_PPISR GICD private peripheral interrupt status register 0xD00 32 read-only n 0x0 0x0 PPI0 PPI0 12 1 PPI1 PPI1 13 1 PPI2 PPI2 14 1 PPI3 PPI3 15 1 PPI4 PPI4 11 1 PPI5 PPI5 10 1 PPI6 PPI6 9 1 SGIR GICD_SGIR GICD software generated interrupt register 0xF00 32 write-only n 0x0 0x0 CPUTARGETLIST CPUTARGETLIST 16 2 NSATT NSATT 15 1 SGIINTID SGIINTID 0 4 TARGETLISTFILTER TARGETLISTFILTER 24 2 SPENDSGIR0 GICD_SPENDSGIR0 For SGI x*4 to SGI x*4+3 0xF20 32 read-write n 0x0 0x0 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR1 GICD_SPENDSGIR1 For SGI x*4 to SGI x*4+3 0xF24 32 read-write n 0x0 0x0 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR2 GICD_SPENDSGIR2 For SGI x*4 to SGI x*4+3 0xF28 32 read-write n 0x0 0x0 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPENDSGIR3 GICD_SPENDSGIR3 For SGI x*4 to SGI x*4+3 0xF2C 32 read-write n 0x0 0x0 SGI_SET_PENDING0 SGI_SET_PENDING0 0 2 SGI_SET_PENDING1 SGI_SET_PENDING1 8 2 SGI_SET_PENDING2 SGI_SET_PENDING2 16 2 SGI_SET_PENDING3 SGI_SET_PENDING3 24 2 SPISR1 GICD_SPISR1 For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32] 0xD08 32 read-only n 0x0 0x0 SPISR1 SPISR1 0 32 SPISR2 GICD_SPISR2 For interrupts ID 0xD0C 32 read-only n 0x0 0x0 SPISR2 SPISR2 0 32 SPISR3 GICD_SPISR3 For interrupts ID 0xD10 32 read-only n 0x0 0x0 SPISR3 SPISR3 0 32 SPISR4 GICD_SPISR4 For interrupts ID 0xD14 32 read-only n 0x0 0x0 SPISR4 SPISR4 0 32 SPISR5 GICD_SPISR5 For interrupts ID 0xD18 32 read-only n 0x0 0x0 SPISR5 SPISR5 0 32 SPISR6 GICD_SPISR6 For interrupts ID 0xD1C 32 read-only n 0x0 0x0 SPISR6 SPISR6 0 32 SPISR7 GICD_SPISR7 For interrupts ID 0xD20 32 read-only n 0x0 0x0 SPISR7 SPISR7 0 32 TYPER GICD_TYPER GICD interrupt controller type register 0x4 32 read-only n 0x0 0x0 CPUNUMBER CPUNUMBER 5 3 ITLINESNUMBER ITLINESNUMBER 0 5 LSPI LSPI 11 5 SECURITYEXTN SECURITYEXTN 10 1 GICH GICH GICH 0x0 0x0 0x2000 registers n APR0 GICH_APR0 GICH active priority register 0xF0 32 read-write n 0x0 0x0 APR0 APR0 0 32 EISR0 GICH_EISR0 GICH end of interrupt status register 0x20 32 read-only n 0x0 0x0 EISR0 EISR0 0 32 ELSR0 GICH_ELSR0 GICH empty list status register 0x30 32 read-only n 0x0 0x0 ELSR0 ELSR0 0 32 HCR GICH_HCR GICH hypervisor control register 0x0 32 read-write n 0x0 0x0 EN EN 0 1 EOICOUNT EOICOUNT 27 5 LRENPIE LRENPIE 2 1 NPIE NPIE 3 1 UIE UIE 1 1 VGRP0DIE VGRP0DIE 5 1 VGRP0EIE VGRP0EIE 4 1 VGRP1DIE VGRP1DIE 7 1 VGRP1EIE VGRP1EIE 6 1 LR0 GICH_LR0 GICH list register 0 0x100 32 read-write n 0x0 0x0 GRP1 GRP1 30 1 HW HW 31 1 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 VIRTUALID VIRTUALID 0 10 LR1 GICH_LR1 GICH list register 1 0x104 32 read-write n 0x0 0x0 GRP1 GRP1 30 1 HW HW 31 1 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 VIRTUALID VIRTUALID 0 10 LR2 GICH_LR2 GICH list register 2 0x108 32 read-write n 0x0 0x0 GRP1 GRP1 30 1 HW HW 31 1 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 VIRTUALID VIRTUALID 0 10 LR3 GICH_LR3 GICH list register 3 0x10C 32 read-write n 0x0 0x0 GRP1 GRP1 30 1 HW HW 31 1 PHYSICALID PHYSICALID 10 10 PRIORITY PRIORITY 23 5 STATE STATE 28 2 VIRTUALID VIRTUALID 0 10 MISR GICH_MISR GICH maintenance interrupt status register 0x10 32 read-only n 0x0 0x0 EOI EOI 0 1 LRENP LRENP 2 1 NP NP 3 1 U U 1 1 VGRP0D VGRP0D 5 1 VGRP0E VGRP0E 4 1 VGRP1D VGRP1D 7 1 VGRP1E VGRP1E 6 1 VMCR GICH_VMCR GICH virtual machine control register 0x8 32 read-write n 0x0 0x0 VEM VEM 9 1 VMABP VMABP 18 3 VMACKCTL VMACKCTL 2 1 VMBP VMBP 21 3 VMCBPR VMCBPR 4 1 VMFIQEN VMFIQEN 3 1 VMGRP0EN VMGRP0EN 0 1 VMGRP1EN VMGRP1EN 1 1 VMPRIMASK VMPRIMASK 27 5 VTR GICH_VTR GICH VGIC type register 0x4 32 read-only n 0x0 0x0 LISTREGS LISTREGS 0 5 PREBITS PREBITS 26 3 PRIBITS PRIBITS 29 3 GICV GICV GICV 0x0 0x0 0x2000 registers n ABPR GICV_ABPR GICV VM aliased binary point register 0x1C 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 AEOIR GICV_AEOIR GICV VM aliased end of interrupt register 0x24 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 AHPPIR GICV_AHPPIR GICV VM aliased highest priority pending interrupt register 0x28 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 AIAR GICV_AIAR GICV VM aliased interrupt register 0x20 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 APR0 GICV_APR0 The GICV_APR0 is an alias of GICH_APR. 0xD0 32 read-write n 0x0 0x0 APR0 APR0 0 32 BPR GICV_BPR GICV VM binary point register 0x8 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 CTLR GICV_CTLR GICV virtual machine control register 0x0 32 read-write n 0x0 0x0 ACKCTL ACKCTL 2 1 CBPR CBPR 4 1 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 EOIMODE EOIMODE 9 1 FIQEN FIQEN 3 1 DIR GICV_DIR GICV VM deactivate interrupt register 0x1000 32 write-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 EOIR GICV_EOIR GICV VM end of interrupt register 0x10 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 HPPIR GICV_HPPIR GICV VM highest priority pending interrupt register 0x18 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 IAR GICV_IAR GICV VM interrupt acknowledge register 0xC 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 IIDR GICV_IIDR The GICV_IIDR is an alias of GICC_IIDR. 0xFC 32 read-only n 0x0 0x0 IIDR IIDR 0 32 PMR GICV_PMR GICV VM priority mask register 0x4 32 read-write n 0x0 0x0 PRIORITY PRIORITY 3 5 RPR GICV_RPR GICV VM running priority register 0x14 32 read-only n 0x0 0x0 PRIORITY PRIORITY 3 5 GPIOA GPIOA GPIOA 0x0 0x0 0x400 registers n AFRH GPIOA_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOA_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOA_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOA_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOA_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOA_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOA_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOA_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOA_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOA_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOA_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOA_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOA_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOA_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOA_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOA_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOA_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOA_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOA_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOA_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOA_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOA_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOA_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOA_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOA_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOB GPIOB GPIOB 0x0 0x0 0x400 registers n AFRH GPIOB_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOB_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOB_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOB_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOB_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOB_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOB_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOB_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOB_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOB_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOB_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOB_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOB_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOB_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOB_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOB_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOB_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOB_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOB_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOB_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOB_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOB_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOB_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOB_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOB_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOC GPIOC GPIOC 0x0 0x0 0x400 registers n AFRH GPIOC_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOC_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOC_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOC_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOC_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOC_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOC_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOC_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOC_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOC_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOC_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOC_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOC_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOC_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOC_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOC_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOC_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOC_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOC_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOC_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOC_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOC_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOC_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOC_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOC_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOD GPIOD GPIOD 0x0 0x0 0x400 registers n AFRH GPIOD_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOD_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOD_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOD_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOD_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOD_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOD_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOD_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOD_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOD_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOD_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOD_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOD_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOD_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOD_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOD_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOD_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOD_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOD_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOD_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOD_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOD_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOD_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOD_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOD_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOE GPIOE GPIOE 0x0 0x0 0x400 registers n AFRH GPIOE_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOE_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOE_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOE_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOE_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOE_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOE_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOE_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOE_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOE_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOE_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOE_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOE_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOE_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOE_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOE_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOE_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOE_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOE_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOE_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOE_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOE_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOE_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOE_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOE_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOF GPIOF GPIOF 0x0 0x0 0x400 registers n AFRH GPIOF_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOF_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOF_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOF_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOF_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOF_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOF_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOF_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOF_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOF_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOF_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOF_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOF_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOF_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOF_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOF_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOF_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOF_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOF_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOF_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOF_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOF_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOF_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOF_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOF_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOG GPIOG GPIOG 0x0 0x0 0x400 registers n AFRH GPIOG_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOG_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOG_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOG_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOG_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOG_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOG_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOG_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOG_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOG_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOG_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOG_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOG_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOG_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOG_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOG_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOG_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOG_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOG_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOG_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOG_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOG_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOG_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOG_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOG_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOH GPIOH GPIOH 0x0 0x0 0x400 registers n AFRH GPIOH_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOH_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOH_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOH_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOH_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOH_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOH_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOH_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOH_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOH_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOH_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOH_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOH_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOH_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOH_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOH_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOH_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOH_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOH_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOH_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOH_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOH_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOH_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOH_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOH_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOI GPIOI GPIOI 0x0 0x0 0x400 registers n AFRH GPIOI_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOI_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOI_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOI_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOI_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOI_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOI_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOI_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOI_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOI_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOI_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOI_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOI_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOI_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOI_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOI_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOI_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOI_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOI_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOI_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOI_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOI_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOI_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOI_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOI_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOJ GPIOJ GPIOJ 0x0 0x0 0x400 registers n AFRH GPIOJ_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOJ_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOJ_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOJ_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOJ_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOJ_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOJ_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOJ_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOJ_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOJ_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOJ_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOJ_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOJ_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOJ_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOJ_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOJ_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOJ_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOJ_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOJ_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOJ_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOJ_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOJ_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOJ_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOJ_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOJ_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOK GPIOK GPIOK 0x0 0x0 0x400 registers n AFRH GPIOK_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOK_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOK_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOK_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOK_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOK_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOK_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOK_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOK_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOK_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOK_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOK_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOK_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOK_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOK_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOK_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOK_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOK_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOK_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOK_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOK_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOK_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOK_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SIDR GPIOK_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOK_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GPIOZ GPIOZ GPIOZ 0x0 0x0 0x400 registers n AFRH GPIOZ_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 AFR11 AFR11 12 4 AFR12 AFR12 16 4 AFR13 AFR13 20 4 AFR14 AFR14 24 4 AFR15 AFR15 28 4 AFR8 AFR8 0 4 AFR9 AFR9 4 4 AFRL GPIOZ_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 AFR1 AFR1 4 4 AFR2 AFR2 8 4 AFR3 AFR3 12 4 AFR4 AFR4 16 4 AFR5 AFR5 20 4 AFR6 AFR6 24 4 AFR7 AFR7 28 4 BRR GPIOZ_BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR10 BR10 10 1 BR11 BR11 11 1 BR12 BR12 12 1 BR13 BR13 13 1 BR14 BR14 14 1 BR15 BR15 15 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BR8 BR8 8 1 BR9 BR9 9 1 BSRR GPIOZ_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 BR1 BR1 17 1 BR10 BR10 26 1 BR11 BR11 27 1 BR12 BR12 28 1 BR13 BR13 29 1 BR14 BR14 30 1 BR15 BR15 31 1 BR2 BR2 18 1 BR3 BR3 19 1 BR4 BR4 20 1 BR5 BR5 21 1 BR6 BR6 22 1 BR7 BR7 23 1 BR8 BR8 24 1 BR9 BR9 25 1 BS0 BS0 0 1 BS1 BS1 1 1 BS10 BS10 10 1 BS11 BS11 11 1 BS12 BS12 12 1 BS13 BS13 13 1 BS14 BS14 14 1 BS15 BS15 15 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 BS8 BS8 8 1 BS9 BS9 9 1 HWCFGR0 GPIOZ_HWCFGR0 GPIO hardware configuration register 0 0x3F0 32 read-only n 0x0 0x0 OR_RES OR_RES 0 16 HWCFGR1 GPIOZ_HWCFGR1 GPIO hardware configuration register 1 0x3EC 32 read-only n 0x0 0x0 AFRH_RES AFRH_RES 0 32 HWCFGR10 GPIOZ_HWCFGR10 For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ: 0x3C8 32 read-only n 0x0 0x0 AF_SIZE AF_SIZE 4 4 AHB_IOP AHB_IOP 0 4 LOCK_CFG LOCK_CFG 12 4 OR_CFG OR_CFG 20 4 SEC_CFG SEC_CFG 16 4 SPEED_CFG SPEED_CFG 8 4 HWCFGR2 GPIOZ_HWCFGR2 GPIO hardware configuration register 2 0x3E8 32 read-only n 0x0 0x0 AFRL_RES AFRL_RES 0 32 HWCFGR3 GPIOZ_HWCFGR3 GPIO hardware configuration register 3 0x3E4 32 read-only n 0x0 0x0 ODR_RES ODR_RES 0 16 OTYPER_RES OTYPER_RES 16 16 HWCFGR4 GPIOZ_HWCFGR4 GPIO hardware configuration register 4 0x3E0 32 read-only n 0x0 0x0 OSPEED_RES OSPEED_RES 0 32 HWCFGR5 GPIOZ_HWCFGR5 GPIO hardware configuration register 5 0x3DC 32 read-only n 0x0 0x0 PUPDR_RES PUPDR_RES 0 32 HWCFGR6 GPIOZ_HWCFGR6 GPIO hardware configuration register 6 0x3D8 32 read-only n 0x0 0x0 MODER_RES MODER_RES 0 32 HWCFGR7 GPIOZ_HWCFGR7 GPIO hardware configuration register 7 0x3D4 32 read-only n 0x0 0x0 AF_PRIO0 AF_PRIO0 0 4 AF_PRIO1 AF_PRIO1 4 4 AF_PRIO2 AF_PRIO2 8 4 AF_PRIO3 AF_PRIO3 12 4 AF_PRIO4 AF_PRIO4 16 4 AF_PRIO5 AF_PRIO5 20 4 AF_PRIO6 AF_PRIO6 24 4 AF_PRIO7 AF_PRIO7 28 4 HWCFGR8 GPIOZ_HWCFGR8 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3D0 32 read-only n 0x0 0x0 AF_PRIO10 AF_PRIO10 8 4 AF_PRIO11 AF_PRIO11 12 4 AF_PRIO12 AF_PRIO12 16 4 AF_PRIO13 AF_PRIO13 20 4 AF_PRIO14 AF_PRIO14 24 4 AF_PRIO15 AF_PRIO15 28 4 AF_PRIO8 AF_PRIO8 0 4 AF_PRIO9 AF_PRIO9 4 4 HWCFGR9 GPIOZ_HWCFGR9 For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ: 0x3CC 32 read-only n 0x0 0x0 EN_IO EN_IO 0 16 IDR GPIOZ_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR10 IDR10 10 1 IDR11 IDR11 11 1 IDR12 IDR12 12 1 IDR13 IDR13 13 1 IDR14 IDR14 14 1 IDR15 IDR15 15 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 IDR8 IDR8 8 1 IDR9 IDR9 9 1 IPIDR GPIOZ_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 IPIDR IPIDR 0 32 LCKR GPIOZ_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 LCK1 LCK1 1 1 LCK10 LCK10 10 1 LCK11 LCK11 11 1 LCK12 LCK12 12 1 LCK13 LCK13 13 1 LCK14 LCK14 14 1 LCK15 LCK15 15 1 LCK2 LCK2 2 1 LCK3 LCK3 3 1 LCK4 LCK4 4 1 LCK5 LCK5 5 1 LCK6 LCK6 6 1 LCK7 LCK7 7 1 LCK8 LCK8 8 1 LCK9 LCK9 9 1 LCKK LCKK 16 1 MODER GPIOZ_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 MODER1 MODER1 2 2 MODER10 MODER10 20 2 MODER11 MODER11 22 2 MODER12 MODER12 24 2 MODER13 MODER13 26 2 MODER14 MODER14 28 2 MODER15 MODER15 30 2 MODER2 MODER2 4 2 MODER3 MODER3 6 2 MODER4 MODER4 8 2 MODER5 MODER5 10 2 MODER6 MODER6 12 2 MODER7 MODER7 14 2 MODER8 MODER8 16 2 MODER9 MODER9 18 2 ODR GPIOZ_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR10 ODR10 10 1 ODR11 ODR11 11 1 ODR12 ODR12 12 1 ODR13 ODR13 13 1 ODR14 ODR14 14 1 ODR15 ODR15 15 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 ODR8 ODR8 8 1 ODR9 ODR9 9 1 OSPEEDR GPIOZ_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 OSPEEDR1 OSPEEDR1 2 2 OSPEEDR10 OSPEEDR10 20 2 OSPEEDR11 OSPEEDR11 22 2 OSPEEDR12 OSPEEDR12 24 2 OSPEEDR13 OSPEEDR13 26 2 OSPEEDR14 OSPEEDR14 28 2 OSPEEDR15 OSPEEDR15 30 2 OSPEEDR2 OSPEEDR2 4 2 OSPEEDR3 OSPEEDR3 6 2 OSPEEDR4 OSPEEDR4 8 2 OSPEEDR5 OSPEEDR5 10 2 OSPEEDR6 OSPEEDR6 12 2 OSPEEDR7 OSPEEDR7 14 2 OSPEEDR8 OSPEEDR8 16 2 OSPEEDR9 OSPEEDR9 18 2 OTYPER GPIOZ_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 OT1 OT1 1 1 OT10 OT10 10 1 OT11 OT11 11 1 OT12 OT12 12 1 OT13 OT13 13 1 OT14 OT14 14 1 OT15 OT15 15 1 OT2 OT2 2 1 OT3 OT3 3 1 OT4 OT4 4 1 OT5 OT5 5 1 OT6 OT6 6 1 OT7 OT7 7 1 OT8 OT8 8 1 OT9 OT9 9 1 PUPDR GPIOZ_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 PUPDR1 PUPDR1 2 2 PUPDR10 PUPDR10 20 2 PUPDR11 PUPDR11 22 2 PUPDR12 PUPDR12 24 2 PUPDR13 PUPDR13 26 2 PUPDR14 PUPDR14 28 2 PUPDR15 PUPDR15 30 2 PUPDR2 PUPDR2 4 2 PUPDR3 PUPDR3 6 2 PUPDR4 PUPDR4 8 2 PUPDR5 PUPDR5 10 2 PUPDR6 PUPDR6 12 2 PUPDR7 PUPDR7 14 2 PUPDR8 PUPDR8 16 2 PUPDR9 PUPDR9 18 2 SECCFGR GPIOZ_SECCFGR This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded. 0x30 32 write-only n 0x0 0x0 SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SIDR GPIOZ_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SIDR SIDR 0 32 VERR GPIOZ_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 HASH1 HASH register block HASH 0x0 0x0 0x400 registers n HASH_CR HASH_CR HASH control register 0x0 32 read-write n 0x0 0x0 ALGO0 ALGO0 7 1 read-write ALGO1 ALGO1 18 1 read-write DATATYPE DATATYPE 4 2 read-write DINNE DINNE 12 1 read-only DMAA DMAA 14 1 write-only DMAE DMAE 3 1 read-write INIT INIT 2 1 write-only LKEY LKEY 16 1 read-write MDMAT MDMAT 13 1 read-write MODE MODE 6 1 read-write NBW NBW 8 4 read-only HASH_CSR0 HASH_CSR0 These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. 0xF8 32 read-write n 0x0 0x0 CS0 CS0 0 32 HASH_CSR1 HASH_CSR1 HASH context swap registers 0xFC 32 read-write n 0x0 0x0 CS1 CS1 0 32 HASH_CSR10 HASH_CSR10 HASH context swap registers 0x120 32 read-write n 0x0 0x0 CS10 CS10 0 32 HASH_CSR11 HASH_CSR11 HASH context swap registers 0x124 32 read-write n 0x0 0x0 CS11 CS11 0 32 HASH_CSR12 HASH_CSR12 HASH context swap registers 0x128 32 read-write n 0x0 0x0 CS12 CS12 0 32 HASH_CSR13 HASH_CSR13 HASH context swap registers 0x12C 32 read-write n 0x0 0x0 CS13 CS13 0 32 HASH_CSR14 HASH_CSR14 HASH context swap registers 0x130 32 read-write n 0x0 0x0 CS14 CS14 0 32 HASH_CSR15 HASH_CSR15 HASH context swap registers 0x134 32 read-write n 0x0 0x0 CS15 CS15 0 32 HASH_CSR16 HASH_CSR16 HASH context swap registers 0x138 32 read-write n 0x0 0x0 CS16 CS16 0 32 HASH_CSR17 HASH_CSR17 HASH context swap registers 0x13C 32 read-write n 0x0 0x0 CS17 CS17 0 32 HASH_CSR18 HASH_CSR18 HASH context swap registers 0x140 32 read-write n 0x0 0x0 CS18 CS18 0 32 HASH_CSR19 HASH_CSR19 HASH context swap registers 0x144 32 read-write n 0x0 0x0 CS19 CS19 0 32 HASH_CSR2 HASH_CSR2 HASH context swap registers 0x100 32 read-write n 0x0 0x0 CS2 CS2 0 32 HASH_CSR20 HASH_CSR20 HASH context swap registers 0x148 32 read-write n 0x0 0x0 CS20 CS20 0 32 HASH_CSR21 HASH_CSR21 HASH context swap registers 0x14C 32 read-write n 0x0 0x0 CS21 CS21 0 32 HASH_CSR22 HASH_CSR22 HASH context swap registers 0x150 32 read-write n 0x0 0x0 CS22 CS22 0 32 HASH_CSR23 HASH_CSR23 HASH context swap registers 0x154 32 read-write n 0x0 0x0 CS23 CS23 0 32 HASH_CSR24 HASH_CSR24 HASH context swap registers 0x158 32 read-write n 0x0 0x0 CS24 CS24 0 32 HASH_CSR25 HASH_CSR25 HASH context swap registers 0x15C 32 read-write n 0x0 0x0 CS25 CS25 0 32 HASH_CSR26 HASH_CSR26 HASH context swap registers 0x160 32 read-write n 0x0 0x0 CS26 CS26 0 32 HASH_CSR27 HASH_CSR27 HASH context swap registers 0x164 32 read-write n 0x0 0x0 CS27 CS27 0 32 HASH_CSR28 HASH_CSR28 HASH context swap registers 0x168 32 read-write n 0x0 0x0 CS28 CS28 0 32 HASH_CSR29 HASH_CSR29 HASH context swap registers 0x16C 32 read-write n 0x0 0x0 CS29 CS29 0 32 HASH_CSR3 HASH_CSR3 HASH context swap registers 0x104 32 read-write n 0x0 0x0 CS3 CS3 0 32 HASH_CSR30 HASH_CSR30 HASH context swap registers 0x170 32 read-write n 0x0 0x0 CS30 CS30 0 32 HASH_CSR31 HASH_CSR31 HASH context swap registers 0x174 32 read-write n 0x0 0x0 CS31 CS31 0 32 HASH_CSR32 HASH_CSR32 HASH context swap registers 0x178 32 read-write n 0x0 0x0 CS32 CS32 0 32 HASH_CSR33 HASH_CSR33 HASH context swap registers 0x17C 32 read-write n 0x0 0x0 CS33 CS33 0 32 HASH_CSR34 HASH_CSR34 HASH context swap registers 0x180 32 read-write n 0x0 0x0 CS34 CS34 0 32 HASH_CSR35 HASH_CSR35 HASH context swap registers 0x184 32 read-write n 0x0 0x0 CS35 CS35 0 32 HASH_CSR36 HASH_CSR36 HASH context swap registers 0x188 32 read-write n 0x0 0x0 CS36 CS36 0 32 HASH_CSR37 HASH_CSR37 HASH context swap registers 0x18C 32 read-write n 0x0 0x0 CS37 CS37 0 32 HASH_CSR38 HASH_CSR38 HASH context swap registers 0x190 32 read-write n 0x0 0x0 CS38 CS38 0 32 HASH_CSR39 HASH_CSR39 HASH context swap registers 0x194 32 read-write n 0x0 0x0 CS39 CS39 0 32 HASH_CSR4 HASH_CSR4 HASH context swap registers 0x108 32 read-write n 0x0 0x0 CS4 CS4 0 32 HASH_CSR40 HASH_CSR40 HASH context swap registers 0x198 32 read-write n 0x0 0x0 CS40 CS40 0 32 HASH_CSR41 HASH_CSR41 HASH context swap registers 0x19C 32 read-write n 0x0 0x0 CS41 CS41 0 32 HASH_CSR42 HASH_CSR42 HASH context swap registers 0x1A0 32 read-write n 0x0 0x0 CS42 CS42 0 32 HASH_CSR43 HASH_CSR43 HASH context swap registers 0x1A4 32 read-write n 0x0 0x0 CS43 CS43 0 32 HASH_CSR44 HASH_CSR44 HASH context swap registers 0x1A8 32 read-write n 0x0 0x0 CS44 CS44 0 32 HASH_CSR45 HASH_CSR45 HASH context swap registers 0x1AC 32 read-write n 0x0 0x0 CS45 CS45 0 32 HASH_CSR46 HASH_CSR46 HASH context swap registers 0x1B0 32 read-write n 0x0 0x0 CS46 CS46 0 32 HASH_CSR47 HASH_CSR47 HASH context swap registers 0x1B4 32 read-write n 0x0 0x0 CS47 CS47 0 32 HASH_CSR48 HASH_CSR48 HASH context swap registers 0x1B8 32 read-write n 0x0 0x0 CS48 CS48 0 32 HASH_CSR49 HASH_CSR49 HASH context swap registers 0x1BC 32 read-write n 0x0 0x0 CS49 CS49 0 32 HASH_CSR5 HASH_CSR5 HASH context swap registers 0x10C 32 read-write n 0x0 0x0 CS5 CS5 0 32 HASH_CSR50 HASH_CSR50 HASH context swap registers 0x1C0 32 read-write n 0x0 0x0 CS50 CS50 0 32 HASH_CSR51 HASH_CSR51 HASH context swap registers 0x1C4 32 read-write n 0x0 0x0 CS51 CS51 0 32 HASH_CSR52 HASH_CSR52 HASH context swap registers 0x1C8 32 read-write n 0x0 0x0 CS52 CS52 0 32 HASH_CSR53 HASH_CSR53 HASH context swap registers 0x1CC 32 read-write n 0x0 0x0 CS53 CS53 0 32 HASH_CSR6 HASH_CSR6 HASH context swap registers 0x110 32 read-write n 0x0 0x0 CS6 CS6 0 32 HASH_CSR7 HASH_CSR7 HASH context swap registers 0x114 32 read-write n 0x0 0x0 CS7 CS7 0 32 HASH_CSR8 HASH_CSR8 HASH context swap registers 0x118 32 read-write n 0x0 0x0 CS8 CS8 0 32 HASH_CSR9 HASH_CSR9 HASH context swap registers 0x11C 32 read-write n 0x0 0x0 CS9 CS9 0 32 HASH_DIN HASH_DIN HASH_DIN is the data input register. 0x4 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 HASH_HR0 HASH_HR0 HASH digest register 0 0xC 32 read-only n 0x0 0x0 H0 H0 0 32 HASH_HR1 HASH_HR1 HASH digest register 1 0x10 32 read-only n 0x0 0x0 H1 H1 0 32 HASH_HR2 HASH_HR2 HASH digest register 2 0x14 32 read-only n 0x0 0x0 H2 H2 0 32 HASH_HR3 HASH_HR3 HASH digest register 3 0x18 32 read-only n 0x0 0x0 H3 H3 0 32 HASH_HR4 HASH_HR4 HASH digest register 4 0x1C 32 read-only n 0x0 0x0 H4 H4 0 32 HASH_HR5 HASH_HR5 HASH digest register 5 0x324 32 read-only n 0x0 0x0 H5 H5 0 32 HASH_HR6 HASH_HR6 HASH digest register 6 0x328 32 read-only n 0x0 0x0 H6 H6 0 32 HASH_HR7 HASH_HR7 HASH digest register 7 0x32C 32 read-only n 0x0 0x0 H7 H7 0 32 HASH_HWCFGR HASH_HWCFGR HASH Hardware Configuration Register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 HASH_IMR HASH_IMR HASH interrupt enable register 0x20 32 read-write n 0x0 0x0 DCIE DCIE 1 1 DINIE DINIE 0 1 HASH_IPIDR HASH_IPIDR HASH Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 HASH_MID HASH_MID HASH Hardware Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 HASH_SR HASH_SR HASH status register 0x24 32 read-write n 0x0 0x0 BUSY BUSY 3 1 read-only DCIS DCIS 1 1 read-write DINIS DINIS 0 1 read-write DMAS DMAS 2 1 read-only HASH_STR HASH_STR The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 0x8 32 read-write n 0x0 0x0 DCAL DCAL 8 1 write-only NBLW NBLW 0 5 read-write HASH_VERR HASH_VERR HASH Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 HASH2 HASH register block HASH 0x0 0x0 0x400 registers n HASH_CR HASH_CR HASH control register 0x0 32 read-write n 0x0 0x0 ALGO0 ALGO0 7 1 read-write ALGO1 ALGO1 18 1 read-write DATATYPE DATATYPE 4 2 read-write DINNE DINNE 12 1 read-only DMAA DMAA 14 1 write-only DMAE DMAE 3 1 read-write INIT INIT 2 1 write-only LKEY LKEY 16 1 read-write MDMAT MDMAT 13 1 read-write MODE MODE 6 1 read-write NBW NBW 8 4 read-only HASH_CSR0 HASH_CSR0 These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers. 0xF8 32 read-write n 0x0 0x0 CS0 CS0 0 32 HASH_CSR1 HASH_CSR1 HASH context swap registers 0xFC 32 read-write n 0x0 0x0 CS1 CS1 0 32 HASH_CSR10 HASH_CSR10 HASH context swap registers 0x120 32 read-write n 0x0 0x0 CS10 CS10 0 32 HASH_CSR11 HASH_CSR11 HASH context swap registers 0x124 32 read-write n 0x0 0x0 CS11 CS11 0 32 HASH_CSR12 HASH_CSR12 HASH context swap registers 0x128 32 read-write n 0x0 0x0 CS12 CS12 0 32 HASH_CSR13 HASH_CSR13 HASH context swap registers 0x12C 32 read-write n 0x0 0x0 CS13 CS13 0 32 HASH_CSR14 HASH_CSR14 HASH context swap registers 0x130 32 read-write n 0x0 0x0 CS14 CS14 0 32 HASH_CSR15 HASH_CSR15 HASH context swap registers 0x134 32 read-write n 0x0 0x0 CS15 CS15 0 32 HASH_CSR16 HASH_CSR16 HASH context swap registers 0x138 32 read-write n 0x0 0x0 CS16 CS16 0 32 HASH_CSR17 HASH_CSR17 HASH context swap registers 0x13C 32 read-write n 0x0 0x0 CS17 CS17 0 32 HASH_CSR18 HASH_CSR18 HASH context swap registers 0x140 32 read-write n 0x0 0x0 CS18 CS18 0 32 HASH_CSR19 HASH_CSR19 HASH context swap registers 0x144 32 read-write n 0x0 0x0 CS19 CS19 0 32 HASH_CSR2 HASH_CSR2 HASH context swap registers 0x100 32 read-write n 0x0 0x0 CS2 CS2 0 32 HASH_CSR20 HASH_CSR20 HASH context swap registers 0x148 32 read-write n 0x0 0x0 CS20 CS20 0 32 HASH_CSR21 HASH_CSR21 HASH context swap registers 0x14C 32 read-write n 0x0 0x0 CS21 CS21 0 32 HASH_CSR22 HASH_CSR22 HASH context swap registers 0x150 32 read-write n 0x0 0x0 CS22 CS22 0 32 HASH_CSR23 HASH_CSR23 HASH context swap registers 0x154 32 read-write n 0x0 0x0 CS23 CS23 0 32 HASH_CSR24 HASH_CSR24 HASH context swap registers 0x158 32 read-write n 0x0 0x0 CS24 CS24 0 32 HASH_CSR25 HASH_CSR25 HASH context swap registers 0x15C 32 read-write n 0x0 0x0 CS25 CS25 0 32 HASH_CSR26 HASH_CSR26 HASH context swap registers 0x160 32 read-write n 0x0 0x0 CS26 CS26 0 32 HASH_CSR27 HASH_CSR27 HASH context swap registers 0x164 32 read-write n 0x0 0x0 CS27 CS27 0 32 HASH_CSR28 HASH_CSR28 HASH context swap registers 0x168 32 read-write n 0x0 0x0 CS28 CS28 0 32 HASH_CSR29 HASH_CSR29 HASH context swap registers 0x16C 32 read-write n 0x0 0x0 CS29 CS29 0 32 HASH_CSR3 HASH_CSR3 HASH context swap registers 0x104 32 read-write n 0x0 0x0 CS3 CS3 0 32 HASH_CSR30 HASH_CSR30 HASH context swap registers 0x170 32 read-write n 0x0 0x0 CS30 CS30 0 32 HASH_CSR31 HASH_CSR31 HASH context swap registers 0x174 32 read-write n 0x0 0x0 CS31 CS31 0 32 HASH_CSR32 HASH_CSR32 HASH context swap registers 0x178 32 read-write n 0x0 0x0 CS32 CS32 0 32 HASH_CSR33 HASH_CSR33 HASH context swap registers 0x17C 32 read-write n 0x0 0x0 CS33 CS33 0 32 HASH_CSR34 HASH_CSR34 HASH context swap registers 0x180 32 read-write n 0x0 0x0 CS34 CS34 0 32 HASH_CSR35 HASH_CSR35 HASH context swap registers 0x184 32 read-write n 0x0 0x0 CS35 CS35 0 32 HASH_CSR36 HASH_CSR36 HASH context swap registers 0x188 32 read-write n 0x0 0x0 CS36 CS36 0 32 HASH_CSR37 HASH_CSR37 HASH context swap registers 0x18C 32 read-write n 0x0 0x0 CS37 CS37 0 32 HASH_CSR38 HASH_CSR38 HASH context swap registers 0x190 32 read-write n 0x0 0x0 CS38 CS38 0 32 HASH_CSR39 HASH_CSR39 HASH context swap registers 0x194 32 read-write n 0x0 0x0 CS39 CS39 0 32 HASH_CSR4 HASH_CSR4 HASH context swap registers 0x108 32 read-write n 0x0 0x0 CS4 CS4 0 32 HASH_CSR40 HASH_CSR40 HASH context swap registers 0x198 32 read-write n 0x0 0x0 CS40 CS40 0 32 HASH_CSR41 HASH_CSR41 HASH context swap registers 0x19C 32 read-write n 0x0 0x0 CS41 CS41 0 32 HASH_CSR42 HASH_CSR42 HASH context swap registers 0x1A0 32 read-write n 0x0 0x0 CS42 CS42 0 32 HASH_CSR43 HASH_CSR43 HASH context swap registers 0x1A4 32 read-write n 0x0 0x0 CS43 CS43 0 32 HASH_CSR44 HASH_CSR44 HASH context swap registers 0x1A8 32 read-write n 0x0 0x0 CS44 CS44 0 32 HASH_CSR45 HASH_CSR45 HASH context swap registers 0x1AC 32 read-write n 0x0 0x0 CS45 CS45 0 32 HASH_CSR46 HASH_CSR46 HASH context swap registers 0x1B0 32 read-write n 0x0 0x0 CS46 CS46 0 32 HASH_CSR47 HASH_CSR47 HASH context swap registers 0x1B4 32 read-write n 0x0 0x0 CS47 CS47 0 32 HASH_CSR48 HASH_CSR48 HASH context swap registers 0x1B8 32 read-write n 0x0 0x0 CS48 CS48 0 32 HASH_CSR49 HASH_CSR49 HASH context swap registers 0x1BC 32 read-write n 0x0 0x0 CS49 CS49 0 32 HASH_CSR5 HASH_CSR5 HASH context swap registers 0x10C 32 read-write n 0x0 0x0 CS5 CS5 0 32 HASH_CSR50 HASH_CSR50 HASH context swap registers 0x1C0 32 read-write n 0x0 0x0 CS50 CS50 0 32 HASH_CSR51 HASH_CSR51 HASH context swap registers 0x1C4 32 read-write n 0x0 0x0 CS51 CS51 0 32 HASH_CSR52 HASH_CSR52 HASH context swap registers 0x1C8 32 read-write n 0x0 0x0 CS52 CS52 0 32 HASH_CSR53 HASH_CSR53 HASH context swap registers 0x1CC 32 read-write n 0x0 0x0 CS53 CS53 0 32 HASH_CSR6 HASH_CSR6 HASH context swap registers 0x110 32 read-write n 0x0 0x0 CS6 CS6 0 32 HASH_CSR7 HASH_CSR7 HASH context swap registers 0x114 32 read-write n 0x0 0x0 CS7 CS7 0 32 HASH_CSR8 HASH_CSR8 HASH context swap registers 0x118 32 read-write n 0x0 0x0 CS8 CS8 0 32 HASH_CSR9 HASH_CSR9 HASH context swap registers 0x11C 32 read-write n 0x0 0x0 CS9 CS9 0 32 HASH_DIN HASH_DIN HASH_DIN is the data input register. 0x4 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 HASH_HR0 HASH_HR0 HASH digest register 0 0xC 32 read-only n 0x0 0x0 H0 H0 0 32 HASH_HR1 HASH_HR1 HASH digest register 1 0x10 32 read-only n 0x0 0x0 H1 H1 0 32 HASH_HR2 HASH_HR2 HASH digest register 2 0x14 32 read-only n 0x0 0x0 H2 H2 0 32 HASH_HR3 HASH_HR3 HASH digest register 3 0x18 32 read-only n 0x0 0x0 H3 H3 0 32 HASH_HR4 HASH_HR4 HASH digest register 4 0x1C 32 read-only n 0x0 0x0 H4 H4 0 32 HASH_HR5 HASH_HR5 HASH digest register 5 0x324 32 read-only n 0x0 0x0 H5 H5 0 32 HASH_HR6 HASH_HR6 HASH digest register 6 0x328 32 read-only n 0x0 0x0 H6 H6 0 32 HASH_HR7 HASH_HR7 HASH digest register 7 0x32C 32 read-only n 0x0 0x0 H7 H7 0 32 HASH_HWCFGR HASH_HWCFGR HASH Hardware Configuration Register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 HASH_IMR HASH_IMR HASH interrupt enable register 0x20 32 read-write n 0x0 0x0 DCIE DCIE 1 1 DINIE DINIE 0 1 HASH_IPIDR HASH_IPIDR HASH Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 HASH_MID HASH_MID HASH Hardware Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 HASH_SR HASH_SR HASH status register 0x24 32 read-write n 0x0 0x0 BUSY BUSY 3 1 read-only DCIS DCIS 1 1 read-write DINIS DINIS 0 1 read-write DMAS DMAS 2 1 read-only HASH_STR HASH_STR The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1 0x8 32 read-write n 0x0 0x0 DCAL DCAL 8 1 write-only NBLW NBLW 0 5 read-write HASH_VERR HASH_VERR HASH Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 HDMI_CEC HDMI_CEC HDMI_CEC 0x0 0x0 0x400 registers n CEC_CFGR CEC_CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 32 read-write n 0x0 0x0 BRDNOGEN BRDNOGEN 7 1 read-write BREGEN BREGEN 5 1 read-write BRESTP BRESTP 4 1 read-write LBPEGEN LBPEGEN 6 1 read-write LSTN LSTN 31 1 read-write OAR OAR 16 15 read-write RXTOL RXTOL 3 1 read-write SFT SFT 0 3 read-write SFTOP SFTOP 8 1 read-write CEC_CR CEC_CR CEC control register 0x0 32 read-write n 0x0 0x0 CECEN CECEN 0 1 read-write TXEOM TXEOM 2 1 read-write TXSOM TXSOM 1 1 read-write CEC_IER CEC_IER CEC interrupt enable register 0x14 32 read-write n 0x0 0x0 ARBLSTIE ARBLSTIE 7 1 read-write BREIE BREIE 3 1 read-write LBPEIE LBPEIE 5 1 read-write RXACKIE RXACKIE 6 1 read-write RXBRIE RXBRIE 0 1 read-write RXENDIE RXENDIE 1 1 read-write RXOVRIE RXOVRIE 2 1 read-write SBPEIE SBPEIE 4 1 read-write TXACKIE TXACKIE 12 1 read-write TXBRIE TXBRIE 8 1 read-write TXENDIE TXENDIE 9 1 read-write TXERRIE TXERRIE 11 1 read-write TXUDRIE TXUDRIE 10 1 read-write CEC_ISR CEC_ISR CEC Interrupt and Status Register 0x10 32 read-write n 0x0 0x0 ARBLST ARBLST 7 1 read-write BRE BRE 3 1 read-write LBPE LBPE 5 1 read-write RXACKE RXACKE 6 1 read-write RXBR RXBR 0 1 read-write RXEND RXEND 1 1 read-write RXOVR RXOVR 2 1 read-write SBPE SBPE 4 1 read-write TXACKE TXACKE 12 1 read-write TXBR TXBR 8 1 read-write TXEND TXEND 9 1 read-write TXERR TXERR 11 1 read-write TXUDR TXUDR 10 1 read-write CEC_RXDR CEC_RXDR CEC Rx data register 0xC 32 read-only n 0x0 0x0 RXD RXD 0 8 read-only CEC_TXDR CEC_TXDR CEC Tx data register 0x8 32 read-write n 0x0 0x0 TXD TXD 0 8 write-only HDP HDP HDP 0x0 0x0 0x400 registers n CTRL HDP_CTRL HDP Control 0x0 32 read-write n 0x0 0x0 EN EN 0 1 GPOCLR HDP_GPOCLR HDP GPO clear 0x18 32 write-only n 0x0 0x0 HDPGPOCLR HDPGPOCLR 0 8 GPOSET HDP_GPOSET HDP GPO set 0x14 32 write-only n 0x0 0x0 HDPGPOSET HDPGPOSET 0 8 GPOVAL HDP_GPOVAL HDP GPO value 0x1C 32 read-write n 0x0 0x0 HDPGPOVAL HDPGPOVAL 0 8 IPIDR HDP_IPIDR HDP IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 MUX HDP_MUX HDP multiplexing 0x4 32 read-write n 0x0 0x0 MUX0 MUX0 0 4 MUX1 MUX1 4 4 MUX2 MUX2 8 4 MUX3 MUX3 12 4 MUX4 MUX4 16 4 MUX5 MUX5 20 4 MUX6 MUX6 24 4 MUX7 MUX7 28 4 SIDR HDP_SIDR HDP size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VAL HDP_VAL HDP value 0x10 32 read-only n 0x0 0x0 HDPVAL HDPVAL 0 8 VERR HDP_VERR HDP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 HSEM HSEM HSEM_IPXACT 0x0 0x0 0x400 registers n C1ICR HSEM_C1ICR HSEM i1terrupt clear register 0x104 32 read-write n 0x0 0x0 ISC ISC 0 32 C1IER HSEM_C1IER HSEM i1terrupt enable register 0x100 32 read-write n 0x0 0x0 ISE ISE 0 32 C1ISR HSEM_C1ISR HSEM i1terrupt status register 0x108 32 read-only n 0x0 0x0 ISF ISF 0 32 C1MISR HSEM_C1MISR HSEM i1terrupt status register 0x10C 32 read-only n 0x0 0x0 MISF MISF 0 32 C2ICR HSEM_C2ICR HSEM i2terrupt clear register 0x114 32 read-write n 0x0 0x0 ISC ISC 0 32 C2IER HSEM_C2IER HSEM i2terrupt enable register 0x110 32 read-write n 0x0 0x0 ISE ISE 0 32 C2ISR HSEM_C2ISR HSEM i2terrupt status register 0x118 32 read-only n 0x0 0x0 ISF ISF 0 32 C2MISR HSEM_C2MISR HSEM i2terrupt status register 0x11C 32 read-only n 0x0 0x0 MISF MISF 0 32 CR HSEM_CR Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x140 32 write-only n 0x0 0x0 COREID COREID 8 4 KEY KEY 16 16 HWCFGR1 HSEM_HWCFGR1 HSEM hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 NBINT NBINT 8 4 NBSEM NBSEM 0 8 HWCFGR2 HSEM_HWCFGR2 HSEM hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 MASTERID1 MASTERID1 0 4 MASTERID2 MASTERID2 4 4 MASTERID3 MASTERID3 8 4 MASTERID4 MASTERID4 12 4 IPIDR HSEM_IPIDR HSEM IP identification register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 KEYR HSEM_KEYR HSEM interrupt clear register 0x144 32 read-write n 0x0 0x0 KEY KEY 16 16 R0 HSEM_R0 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x0 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R1 HSEM_R1 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x4 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R10 HSEM_R10 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x28 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R11 HSEM_R11 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x2C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R12 HSEM_R12 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x30 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R13 HSEM_R13 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x34 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R14 HSEM_R14 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x38 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R15 HSEM_R15 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x3C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R16 HSEM_R16 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x40 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R17 HSEM_R17 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x44 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R18 HSEM_R18 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x48 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R19 HSEM_R19 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x4C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R2 HSEM_R2 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x8 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R20 HSEM_R20 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x50 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R21 HSEM_R21 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x54 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R22 HSEM_R22 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x58 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R23 HSEM_R23 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x5C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R24 HSEM_R24 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x60 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R25 HSEM_R25 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x64 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R26 HSEM_R26 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x68 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R27 HSEM_R27 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x6C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R28 HSEM_R28 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x70 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R29 HSEM_R29 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x74 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R3 HSEM_R3 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0xC 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R30 HSEM_R30 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x78 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R31 HSEM_R31 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x7C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R4 HSEM_R4 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x10 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R5 HSEM_R5 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x14 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R6 HSEM_R6 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x18 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R7 HSEM_R7 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x1C 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R8 HSEM_R8 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x20 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 R9 HSEM_R9 The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded. 0x24 32 read-write n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR0 HSEM_RLR0 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x80 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR1 HSEM_RLR1 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x84 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR10 HSEM_RLR10 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR11 HSEM_RLR11 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xAC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR12 HSEM_RLR12 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR13 HSEM_RLR13 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR14 HSEM_RLR14 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xB8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR15 HSEM_RLR15 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xBC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR16 HSEM_RLR16 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR17 HSEM_RLR17 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR18 HSEM_RLR18 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xC8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR19 HSEM_RLR19 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xCC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR2 HSEM_RLR2 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x88 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR20 HSEM_RLR20 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR21 HSEM_RLR21 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR22 HSEM_RLR22 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xD8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR23 HSEM_RLR23 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xDC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR24 HSEM_RLR24 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR25 HSEM_RLR25 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR26 HSEM_RLR26 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xE8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR27 HSEM_RLR27 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xEC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR28 HSEM_RLR28 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR29 HSEM_RLR29 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR3 HSEM_RLR3 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x8C 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR30 HSEM_RLR30 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xF8 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR31 HSEM_RLR31 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xFC 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR4 HSEM_RLR4 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x90 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR5 HSEM_RLR5 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x94 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR6 HSEM_RLR6 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x98 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR7 HSEM_RLR7 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0x9C 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR8 HSEM_RLR8 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA0 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 RLR9 HSEM_RLR9 Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded. 0xA4 32 read-only n 0x0 0x0 COREID COREID 8 4 LOCK LOCK 31 1 PROCID PROCID 0 8 SIDR HSEM_SIDR HSEM size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR HSEM_VERR HSEM IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C1 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C2 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C3 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C4 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C5 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C6 I2C2 I2C2_IPXACT 0x0 0x0 0x400 registers n I2C_CR1 I2C_CR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck. 0x0 32 read-write n 0x0 0x0 ADDRIE ADDRIE 3 1 ALERTEN ALERTEN 22 1 ANFOFF ANFOFF 12 1 DNF DNF 8 4 ERRIE ERRIE 7 1 GCEN GCEN 19 1 NACKIE NACKIE 4 1 NOSTRETCH NOSTRETCH 17 1 PE PE 0 1 PECEN PECEN 23 1 RXDMAEN RXDMAEN 15 1 RXIE RXIE 2 1 SBC SBC 16 1 SMBDEN SMBDEN 21 1 SMBHEN SMBHEN 20 1 STOPIE STOPIE 5 1 TCIE TCIE 6 1 TXDMAEN TXDMAEN 14 1 TXIE TXIE 1 1 WUPEN WUPEN 18 1 I2C_CR2 I2C_CR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x4 32 read-write n 0x0 0x0 ADD10 ADD10 11 1 AUTOEND AUTOEND 25 1 HEAD10R HEAD10R 12 1 NACK NACK 15 1 NBYTES NBYTES 16 8 PECBYTE PECBYTE 26 1 RD_WRN RD_WRN 10 1 RELOAD RELOAD 24 1 SADD SADD 0 10 START START 13 1 STOP STOP 14 1 I2C_HWCFGR I2C_HWCFGR I2C hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ASYN ASYN 4 4 SMBUS SMBUS 0 4 WKP WKP 8 4 I2C_ICR I2C_ICR Access: No wait states 0x1C 32 write-only n 0x0 0x0 ADDRCF ADDRCF 3 1 ALERTCF ALERTCF 13 1 ARLOCF ARLOCF 9 1 BERRCF BERRCF 8 1 NACKCF NACKCF 4 1 OVRCF OVRCF 10 1 PECCF PECCF 11 1 STOPCF STOPCF 5 1 TIMOUTCF TIMOUTCF 12 1 I2C_IPIDR I2C_IPIDR I2C identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 I2C_ISR I2C_ISR Access: No wait states 0x18 32 read-write n 0x0 0x0 ADDCODE ADDCODE 17 7 read-only ADDR ADDR 3 1 read-only ALERT ALERT 13 1 read-only ARLO ARLO 9 1 read-only BERR BERR 8 1 read-only BUSY BUSY 15 1 read-only DIR DIR 16 1 read-only NACKF NACKF 4 1 read-only OVR OVR 10 1 read-only PECERR PECERR 11 1 read-only RXNE RXNE 2 1 read-only STOPF STOPF 5 1 read-only TC TC 6 1 read-only TCR TCR 7 1 read-only TIMEOUT TIMEOUT 12 1 read-only TXE TXE 0 1 read-write TXIS TXIS 1 1 read-write I2C_OAR1 I2C_OAR1 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x8 32 read-write n 0x0 0x0 OA1 OA1 0 10 OA1EN OA1EN 15 1 OA1MODE OA1MODE 10 1 I2C_OAR2 I2C_OAR2 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0xC 32 read-write n 0x0 0x0 OA2 OA2 1 7 OA2EN OA2EN 15 1 OA2MSK OA2MSK 8 3 I2C_PECR I2C_PECR Access: No wait states 0x20 32 read-only n 0x0 0x0 PEC PEC 0 8 I2C_RXDR I2C_RXDR Access: No wait states 0x24 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 I2C_SIDR I2C_SIDR I2C size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 I2C_TIMEOUTR I2C_TIMEOUTR Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck. 0x14 32 read-write n 0x0 0x0 TEXTEN TEXTEN 31 1 TIDLE TIDLE 12 1 TIMEOUTA TIMEOUTA 0 12 TIMEOUTB TIMEOUTB 16 12 TIMOUTEN TIMOUTEN 15 1 I2C_TIMINGR I2C_TIMINGR Access: No wait states 0x10 32 read-write n 0x0 0x0 PRESC PRESC 28 4 SCLDEL SCLDEL 20 4 SCLH SCLH 8 8 SCLL SCLL 0 8 SDADEL SDADEL 16 4 I2C_TXDR I2C_TXDR Access: No wait states 0x28 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 I2C_VERR I2C_VERR I2C version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 IPCC IPCC IPCC 0x0 0x0 0x400 registers n C1CR IPCC_C1CR IPCC Processor 1 control register 0x0 32 read-write n 0x0 0x0 RXOIE RXOIE 0 1 TXFIE TXFIE 16 1 C1MR IPCC_C1MR IPCC Processor 1 mask register 0x4 32 read-write n 0x0 0x0 CHxFM CHxFM 16 6 CHxOM CHxOM 0 6 C1SCR IPCC_C1SCR Reading this register will always return 0x0000 0000. 0x8 32 read-write n 0x0 0x0 CHxC CHxC 0 6 CHxS CHxS 16 6 C1TOC2SR IPCC_C1TOC2SR IPCC processor 1 to processor 2 status register 0xC 32 read-only n 0x0 0x0 CHxF CHxF 0 6 C2CR IPCC_C2CR IPCC Processor 2 control register 0x10 32 read-write n 0x0 0x0 RXOIE RXOIE 0 1 TXFIE TXFIE 16 1 C2MR IPCC_C2MR IPCC Processor 2 mask register 0x14 32 read-write n 0x0 0x0 CHxFM CHxFM 16 6 CHxOM CHxOM 0 6 C2SCR IPCC_C2SCR Reading this register will always return 0x0000 0000. 0x18 32 read-write n 0x0 0x0 CHxC CHxC 0 6 CHxS CHxS 16 6 C2TOC1SR IPCC_C2TOC1SR IPCC processor 2 to processor 1 status register 0x1C 32 read-only n 0x0 0x0 CHxF CHxF 0 6 HWCFGR IPCC_HWCFGR IPCC Hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CHANNELS CHANNELS 0 8 ID IPCC_ID IPCC IP Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 SID IPCC_SID IPCC Size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VER IPCC_VER IPCC IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 IWDG1 IWDG1 IWDG1 0x0 0x0 0x400 registers n IWDG_HWCFGR IWDG_HWCFGR IWDG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 PR_DEFAULT PR_DEFAULT 4 4 WINDOW WINDOW 0 4 IWDG_IDR IWDG_IDR IWDG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 IWDG_KR IWDG_KR Key register 0x0 32 write-only n 0x0 0x0 KEY KEY 0 16 IWDG_PR IWDG_PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR PR 0 3 IWDG_RLR IWDG_RLR Reload register 0x8 32 read-write n 0x0 0x0 RL RL 0 12 IWDG_SIDR IWDG_SIDR IWDG size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 IWDG_SR IWDG_SR Status register 0xC 32 read-only n 0x0 0x0 PVU PVU 0 1 RVU RVU 1 1 WVU WVU 2 1 IWDG_VERR IWDG_VERR IWDG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 IWDG_WINR IWDG_WINR Window register 0x10 32 read-write n 0x0 0x0 WIN WIN 0 12 IWDG2 IWDG1 IWDG1 0x0 0x0 0x400 registers n IWDG_HWCFGR IWDG_HWCFGR IWDG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 PR_DEFAULT PR_DEFAULT 4 4 WINDOW WINDOW 0 4 IWDG_IDR IWDG_IDR IWDG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 IWDG_KR IWDG_KR Key register 0x0 32 write-only n 0x0 0x0 KEY KEY 0 16 IWDG_PR IWDG_PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR PR 0 3 IWDG_RLR IWDG_RLR Reload register 0x8 32 read-write n 0x0 0x0 RL RL 0 12 IWDG_SIDR IWDG_SIDR IWDG size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 IWDG_SR IWDG_SR Status register 0xC 32 read-only n 0x0 0x0 PVU PVU 0 1 RVU RVU 1 1 WVU WVU 2 1 IWDG_VERR IWDG_VERR IWDG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 IWDG_WINR IWDG_WINR Window register 0x10 32 read-write n 0x0 0x0 WIN WIN 0 12 LPTIM1 LPTIM1 LPTIM1 0x0 0x0 0x400 registers n HWCFGR LPTIM1_HWCFGR LPTIM 1 peripheral hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 CKPOL CKPOL 1 2 CKSEL CKSEL 0 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 PRELOAD PRELOAD 22 1 PRESC PRESC 9 3 TIMOUT TIMOUT 19 1 TRGFLT TRGFLT 6 2 TRIGEN TRIGEN 17 2 TRIGSEL TRIGSEL 13 3 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 IN2SEL IN2SEL 4 2 LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 ENABLE ENABLE 0 1 RSTARE RSTARE 4 1 SNGSTRT SNGSTRT 1 1 LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 write-only n 0x0 0x0 ARRMCF ARRMCF 1 1 ARROKCF ARROKCF 4 1 CMPMCF CMPMCF 0 1 CMPOKCF CMPOKCF 3 1 DOWNCF DOWNCF 6 1 EXTTRIGCF EXTTRIGCF 2 1 UPCF UPCF 5 1 LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 ARROKIE ARROKIE 4 1 CMPMIE CMPMIE 0 1 CMPOKIE CMPOKIE 3 1 DOWNIE DOWNIE 6 1 EXTTRIGIE EXTTRIGIE 2 1 UPIE UPIE 5 1 LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 ARROK ARROK 4 1 CMPM CMPM 0 1 CMPOK CMPOK 3 1 DOWN DOWN 6 1 EXTTRIG EXTTRIG 2 1 UP UP 5 1 LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 LPTIM2 LPTIM2 LPTIM2 0x0 0x0 0x400 registers n HWCFGR LPTIM2_HWCFGR LPTIM 2 peripheral hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 CKPOL CKPOL 1 2 CKSEL CKSEL 0 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 PRELOAD PRELOAD 22 1 PRESC PRESC 9 3 TIMOUT TIMOUT 19 1 TRGFLT TRGFLT 6 2 TRIGEN TRIGEN 17 2 TRIGSEL TRIGSEL 13 3 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 IN2SEL IN2SEL 4 2 LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 ENABLE ENABLE 0 1 RSTARE RSTARE 4 1 SNGSTRT SNGSTRT 1 1 LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 write-only n 0x0 0x0 ARRMCF ARRMCF 1 1 ARROKCF ARROKCF 4 1 CMPMCF CMPMCF 0 1 CMPOKCF CMPOKCF 3 1 DOWNCF DOWNCF 6 1 EXTTRIGCF EXTTRIGCF 2 1 UPCF UPCF 5 1 LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 ARROKIE ARROKIE 4 1 CMPMIE CMPMIE 0 1 CMPOKIE CMPOKIE 3 1 DOWNIE DOWNIE 6 1 EXTTRIGIE EXTTRIGIE 2 1 UPIE UPIE 5 1 LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 ARROK ARROK 4 1 CMPM CMPM 0 1 CMPOK CMPOK 3 1 DOWN DOWN 6 1 EXTTRIG EXTTRIG 2 1 UP UP 5 1 LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 LPTIM3 LPTIM3 LPTIM3 0x0 0x0 0x400 registers n CFGR2 LPTIM3_CFGR2 LPTIM3 configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 HWCFGR LPTIM3_HWCFGR LPTIM 3 peripheral hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 CKPOL CKPOL 1 2 CKSEL CKSEL 0 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 PRELOAD PRELOAD 22 1 PRESC PRESC 9 3 TIMOUT TIMOUT 19 1 TRGFLT TRGFLT 6 2 TRIGEN TRIGEN 17 2 TRIGSEL TRIGSEL 13 3 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 ENABLE ENABLE 0 1 RSTARE RSTARE 4 1 SNGSTRT SNGSTRT 1 1 LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 write-only n 0x0 0x0 ARRMCF ARRMCF 1 1 ARROKCF ARROKCF 4 1 CMPMCF CMPMCF 0 1 CMPOKCF CMPOKCF 3 1 DOWNCF DOWNCF 6 1 EXTTRIGCF EXTTRIGCF 2 1 UPCF UPCF 5 1 LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 ARROKIE ARROKIE 4 1 CMPMIE CMPMIE 0 1 CMPOKIE CMPOKIE 3 1 DOWNIE DOWNIE 6 1 EXTTRIGIE EXTTRIGIE 2 1 UPIE UPIE 5 1 LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 ARROK ARROK 4 1 CMPM CMPM 0 1 CMPOK CMPOK 3 1 DOWN DOWN 6 1 EXTTRIG EXTTRIG 2 1 UP UP 5 1 LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 LPTIM4 LPTIM4 LPTIM4 0x0 0x0 0x400 registers n HWCFGR LPTIM4_HWCFGR LPTIM 4 peripheral hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 CKPOL CKPOL 1 2 CKSEL CKSEL 0 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 PRELOAD PRELOAD 22 1 PRESC PRESC 9 3 TIMOUT TIMOUT 19 1 TRGFLT TRGFLT 6 2 TRIGEN TRIGEN 17 2 TRIGSEL TRIGSEL 13 3 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 IN2SEL IN2SEL 4 2 LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 ENABLE ENABLE 0 1 RSTARE RSTARE 4 1 SNGSTRT SNGSTRT 1 1 LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 write-only n 0x0 0x0 ARRMCF ARRMCF 1 1 ARROKCF ARROKCF 4 1 CMPMCF CMPMCF 0 1 CMPOKCF CMPOKCF 3 1 DOWNCF DOWNCF 6 1 EXTTRIGCF EXTTRIGCF 2 1 UPCF UPCF 5 1 LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 ARROKIE ARROKIE 4 1 CMPMIE CMPMIE 0 1 CMPOKIE CMPOKIE 3 1 DOWNIE DOWNIE 6 1 EXTTRIGIE EXTTRIGIE 2 1 UPIE UPIE 5 1 LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 ARROK ARROK 4 1 CMPM CMPM 0 1 CMPOK CMPOK 3 1 DOWN DOWN 6 1 EXTTRIG EXTTRIG 2 1 UP UP 5 1 LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 LPTIM5 LPTIM5 LPTIM5 0x0 0x0 0x400 registers n HWCFGR LPTIM5_HWCFGR LPTIM 5 peripheral hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 8 CFG2 CFG2 8 8 CFG3 CFG3 16 4 CFG4 CFG4 24 8 LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 CKPOL CKPOL 1 2 CKSEL CKSEL 0 1 COUNTMODE COUNTMODE 23 1 ENC ENC 24 1 PRELOAD PRELOAD 22 1 PRESC PRESC 9 3 TIMOUT TIMOUT 19 1 TRGFLT TRGFLT 6 2 TRIGEN TRIGEN 17 2 TRIGSEL TRIGSEL 13 3 WAVE WAVE 20 1 WAVPOL WAVPOL 21 1 LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 IN2SEL IN2SEL 4 2 LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 COUNTRST COUNTRST 3 1 ENABLE ENABLE 0 1 RSTARE RSTARE 4 1 SNGSTRT SNGSTRT 1 1 LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 write-only n 0x0 0x0 ARRMCF ARRMCF 1 1 ARROKCF ARROKCF 4 1 CMPMCF CMPMCF 0 1 CMPOKCF CMPOKCF 3 1 DOWNCF DOWNCF 6 1 EXTTRIGCF EXTTRIGCF 2 1 UPCF UPCF 5 1 LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 ARROKIE ARROKIE 4 1 CMPMIE CMPMIE 0 1 CMPOKIE CMPOKIE 3 1 DOWNIE DOWNIE 6 1 EXTTRIGIE EXTTRIGIE 2 1 UPIE UPIE 5 1 LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 ARROK ARROK 4 1 CMPM CMPM 0 1 CMPOK CMPOK 3 1 DOWN DOWN 6 1 EXTTRIG EXTTRIG 2 1 UP UP 5 1 LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 LTDC LTDC LTDC 0x0 0x0 0x400 registers n AWCR LTDC_AWCR This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x10 32 read-write n 0x0 0x0 AAH AAH 0 12 AAW AAW 16 12 BCCR LTDC_BCCR This register defines the background color (RGB888). 0x2C 32 read-write n 0x0 0x0 BCBLUE BCBLUE 0 8 BCGREEN BCGREEN 8 8 BCRED BCRED 16 8 BPCR LTDC_BPCR This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0xC 32 read-write n 0x0 0x0 AHBP AHBP 16 12 AVBP AVBP 0 12 CDSR LTDC_CDSR This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. 0x48 32 read-only n 0x0 0x0 HDES HDES 1 1 HSYNCS HSYNCS 3 1 VDES VDES 0 1 VSYNCS VSYNCS 2 1 CPSR LTDC_CPSR LTDC current position status register 0x44 32 read-only n 0x0 0x0 CXPOS CXPOS 16 16 CYPOS CYPOS 0 16 GC1R LTDC_GC1R LTDC global configuration 1 register 0x1C 32 read-only n 0x0 0x0 BBEN BBEN 23 1 BCP BCP 22 1 BMEN BMEN 31 1 DT DT 14 2 DWP DWP 28 1 GCT GCT 17 3 IPP IPP 26 1 LNIP LNIP 24 1 PRBEN PRBEN 12 1 SHREN SHREN 21 1 SPP SPP 27 1 STREN STREN 29 1 TP TP 25 1 WBCH WBCH 0 4 WGCH WGCH 4 4 WRCH WRCH 8 4 GC2R LTDC_GC2R LTDC global configuration 2 register 0x20 32 read-only n 0x0 0x0 BW BW 4 3 DPAEN DPAEN 3 1 DVAEN DVAEN 2 1 EDCA EDCA 7 1 EDCEN EDCEN 0 1 STSAEN STSAEN 1 1 GCR LTDC_GCR This register defines the global configuration of the LCD-TFT controller. 0x18 32 read-write n 0x0 0x0 DBW DBW 4 3 read-only DEN DEN 16 1 read-write DEPOL DEPOL 29 1 read-write DGW DGW 8 3 read-only DRW DRW 12 3 read-only HSPOL HSPOL 31 1 read-write LTDCEN LTDCEN 0 1 read-write PCPOL PCPOL 28 1 read-write VSPOL VSPOL 30 1 read-write ICR LTDC_ICR LTDC Interrupt Clear Register 0x3C 32 write-only n 0x0 0x0 CFUIF CFUIF 1 1 CLIF CLIF 0 1 CRRIF CRRIF 3 1 CTERRIF CTERRIF 2 1 IDR LTDC_IDR LTDC identification register 0x0 32 read-only n 0x0 0x0 MAJVER MAJVER 16 8 MINVER MINVER 8 8 REV REV 0 8 IER LTDC_IER This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x34 32 read-write n 0x0 0x0 FUIE FUIE 1 1 LIE LIE 0 1 RRIE RRIE 3 1 TERRIE TERRIE 2 1 ISR LTDC_ISR This register returns the interrupt status flag. 0x38 32 read-only n 0x0 0x0 FUIF FUIF 1 1 LIF LIF 0 1 RRIF RRIF 3 1 TERRIF TERRIF 2 1 L1BFCR LTDC_L1BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0xA0 32 read-write n 0x0 0x0 BF1 BF1 8 3 BF2 BF2 0 3 L1CACR LTDC_L1CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x98 32 read-write n 0x0 0x0 CONSTA CONSTA 0 8 L1CFBAR LTDC_L1CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0xAC 32 read-write n 0x0 0x0 CFBADD CFBADD 0 32 L1CFBLNR LTDC_L1CFBLNR This register defines the number of lines in the color frame buffer. 0xB4 32 read-write n 0x0 0x0 CFBLNBR CFBLNBR 0 12 L1CFBLR LTDC_L1CFBLR This register defines the color frame buffer line length and pitch. 0xB0 32 read-write n 0x0 0x0 CFBLL CFBLL 0 14 CFBP CFBP 16 14 L1CKCR LTDC_L1CKCR This register defines the color key value (RGB), that is used by the color keying. 0x90 32 read-write n 0x0 0x0 CKBLUE CKBLUE 0 8 CKGREEN CKGREEN 8 8 CKRED CKRED 16 8 L1CLUTWR LTDC_L1CLUTWR This register defines the CLUT address and the RGB value. 0xC4 32 write-only n 0x0 0x0 BLUE BLUE 0 8 CLUTADD CLUTADD 24 8 GREEN GREEN 8 8 RED RED 16 8 L1CR LTDC_L1CR LTDC layer 1 control register 0x84 32 read-write n 0x0 0x0 CLUTEN CLUTEN 4 1 COLKEN COLKEN 1 1 LEN LEN 0 1 L1DCCR LTDC_L1DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x9C 32 read-write n 0x0 0x0 DCALPHA DCALPHA 24 8 DCBLUE DCBLUE 0 8 DCGREEN DCGREEN 8 8 DCRED DCRED 16 8 L1PFCR LTDC_L1PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x94 32 read-write n 0x0 0x0 PF PF 0 3 L1WHPCR LTDC_L1WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. 0x88 32 read-write n 0x0 0x0 WHSPPOS WHSPPOS 16 12 WHSTPOS WHSTPOS 0 12 L1WVPCR LTDC_L1WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x8C 32 read-write n 0x0 0x0 WVSPPOS WVSPPOS 16 12 WVSTPOS WVSTPOS 0 12 L2BFCR LTDC_L2BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0x120 32 read-write n 0x0 0x0 BF1 BF1 8 3 BF2 BF2 0 3 L2CACR LTDC_L2CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x118 32 read-write n 0x0 0x0 CONSTA CONSTA 0 8 L2CFBAR LTDC_L2CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0x12C 32 read-write n 0x0 0x0 CFBADD CFBADD 0 32 L2CFBLNR LTDC_L2CFBLNR This register defines the number of lines in the color frame buffer. 0x134 32 read-write n 0x0 0x0 CFBLNBR CFBLNBR 0 12 L2CFBLR LTDC_L2CFBLR This register defines the color frame buffer line length and pitch. 0x130 32 read-write n 0x0 0x0 CFBLL CFBLL 0 14 CFBP CFBP 16 14 L2CKCR LTDC_L2CKCR This register defines the color key value (RGB), that is used by the color keying. 0x110 32 read-write n 0x0 0x0 CKBLUE CKBLUE 0 8 CKGREEN CKGREEN 8 8 CKRED CKRED 16 8 L2CLUTWR LTDC_L2CLUTWR This register defines the CLUT address and the RGB value. 0x144 32 write-only n 0x0 0x0 BLUE BLUE 0 8 CLUTADD CLUTADD 24 8 GREEN GREEN 8 8 RED RED 16 8 L2CR LTDC_L2CR LTDC layer 2 control register 0x104 32 read-write n 0x0 0x0 CLUTEN CLUTEN 4 1 COLKEN COLKEN 1 1 LEN LEN 0 1 L2DCCR LTDC_L2DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x11C 32 read-write n 0x0 0x0 DCALPHA DCALPHA 24 8 DCBLUE DCBLUE 0 8 DCGREEN DCGREEN 8 8 DCRED DCRED 16 8 L2PFCR LTDC_L2PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x114 32 read-write n 0x0 0x0 PF PF 0 3 L2WHPCR LTDC_L2WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register. 0x108 32 read-write n 0x0 0x0 WHSPPOS WHSPPOS 16 12 WHSTPOS WHSTPOS 0 12 L2WVPCR LTDC_L2WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x10C 32 read-write n 0x0 0x0 WVSPPOS WVSPPOS 16 12 WVSTPOS WVSTPOS 0 12 LCR LTDC_LCR LDTC layer count register 0x4 32 read-only n 0x0 0x0 LNBR LNBR 0 8 LIPCR LTDC_LIPCR This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274. 0x40 32 read-write n 0x0 0x0 LIPOS LIPOS 0 12 SRCR LTDC_SRCR This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. 0x24 32 read-write n 0x0 0x0 IMR IMR 0 1 VBR VBR 1 1 SSCR LTDC_SSCR This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x8 32 read-write n 0x0 0x0 HSW HSW 16 12 VSH VSH 0 12 TWCR LTDC_TWCR This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration. 0x14 32 read-write n 0x0 0x0 TOTALH TOTALH 0 12 TOTALW TOTALW 16 12 MDIOS MDIOS MDIOS 0x0 0x0 0x400 registers n CLRFR MDIOS_CLRFR MDIOS clear flag register 0x18 32 read-write n 0x0 0x0 CPERF CPERF 0 1 read-write CSERF CSERF 1 1 read-write CTERF CTERF 2 1 read-write CR MDIOS_CR MDIOS configuration register 0x0 32 read-write n 0x0 0x0 DPC DPC 7 1 read-write EIE EIE 3 1 read-write EN EN 0 1 read-write PORT_ADDRESS PORT_ADDRESS 8 5 read-write RDIE RDIE 2 1 read-write WRIE WRIE 1 1 read-write CRDFR MDIOS_CRDFR MDIOS clear read flag register 0x10 32 read-write n 0x0 0x0 CRDF CRDF 0 32 read-write CWRFR MDIOS_CWRFR MDIOS clear write flag register 0x8 32 read-write n 0x0 0x0 CWRF CWRF 0 32 read-write DINR0 MDIOS_DINR0 MDIOS input data register 0x100 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR1 MDIOS_DINR1 MDIOS input data register 0x104 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR10 MDIOS_DINR10 MDIOS input data register 0x128 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR11 MDIOS_DINR11 MDIOS input data register 0x12C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR12 MDIOS_DINR12 MDIOS input data register 0x130 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR13 MDIOS_DINR13 MDIOS input data register 0x134 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR14 MDIOS_DINR14 MDIOS input data register 0x138 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR15 MDIOS_DINR15 MDIOS input data register 0x13C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR16 MDIOS_DINR16 MDIOS input data register 0x140 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR17 MDIOS_DINR17 MDIOS input data register 0x144 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR18 MDIOS_DINR18 MDIOS input data register 0x148 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR19 MDIOS_DINR19 MDIOS input data register 0x14C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR2 MDIOS_DINR2 MDIOS input data register 0x108 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR20 MDIOS_DINR20 MDIOS input data register 0x150 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR21 MDIOS_DINR21 MDIOS input data register 0x154 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR22 MDIOS_DINR22 MDIOS input data register 0x158 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR23 MDIOS_DINR23 MDIOS input data register 0x15C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR24 MDIOS_DINR24 MDIOS input data register 0x160 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR25 MDIOS_DINR25 MDIOS input data register 0x164 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR26 MDIOS_DINR26 MDIOS input data register 0x168 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR27 MDIOS_DINR27 MDIOS input data register 0x16C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR28 MDIOS_DINR28 MDIOS input data register 0x170 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR29 MDIOS_DINR29 MDIOS input data register 0x174 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR3 MDIOS_DINR3 MDIOS input data register 0x10C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR30 MDIOS_DINR30 MDIOS input data register 0x178 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR31 MDIOS_DINR31 MDIOS input data register 0x17C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR4 MDIOS_DINR4 MDIOS input data register 0x110 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR5 MDIOS_DINR5 MDIOS input data register 0x114 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR6 MDIOS_DINR6 MDIOS input data register 0x118 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR7 MDIOS_DINR7 MDIOS input data register 0x11C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR8 MDIOS_DINR8 MDIOS input data register 0x120 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR9 MDIOS_DINR9 MDIOS input data register 0x124 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DOUTR0 MDIOS_DOUTR0 MDIOS input data register 0x180 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR1 MDIOS_DOUTR1 MDIOS input data register 0x184 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR10 MDIOS_DOUTR10 MDIOS output data register 0x1A8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR11 MDIOS_DOUTR11 MDIOS output data register 0x1AC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR12 MDIOS_DOUTR12 MDIOS output data register 0x1B0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR13 MDIOS_DOUTR13 MDIOS output data register 0x1B4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR14 MDIOS_DOUTR14 MDIOS output data register 0x1B8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR15 MDIOS_DOUTR15 MDIOS output data register 0x1BC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR16 MDIOS_DOUTR16 MDIOS output data register 0x1C0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR17 MDIOS_DOUTR17 MDIOS output data register 0x1C4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR18 MDIOS_DOUTR18 MDIOS output data register 0x1C8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR19 MDIOS_DOUTR19 MDIOS output data register 0x1CC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR2 MDIOS_DOUTR2 MDIOS output data register 0x188 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR20 MDIOS_DOUTR20 MDIOS output data register 0x1D0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR21 MDIOS_DOUTR21 MDIOS output data register 0x1D4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR22 MDIOS_DOUTR22 MDIOS output data register 0x1D8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR23 MDIOS_DOUTR23 MDIOS output data register 0x1DC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR24 MDIOS_DOUTR24 MDIOS output data register 0x1E0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR25 MDIOS_DOUTR25 MDIOS output data register 0x1E4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR26 MDIOS_DOUTR26 MDIOS output data register 0x1E8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR27 MDIOS_DOUTR27 MDIOS output data register 0x1EC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR28 MDIOS_DOUTR28 MDIOS output data register 0x1F0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR29 MDIOS_DOUTR29 MDIOS output data register 0x1F4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR3 MDIOS_DOUTR3 MDIOS output data register 0x18C 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR30 MDIOS_DOUTR30 MDIOS output data register 0x1F8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR31 MDIOS_DOUTR31 MDIOS output data register 0x1FC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR4 MDIOS_DOUTR4 MDIOS output data register 0x190 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR5 MDIOS_DOUTR5 MDIOS output data register 0x194 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR6 MDIOS_DOUTR6 MDIOS output data register 0x198 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR7 MDIOS_DOUTR7 MDIOS output data register 0x19C 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR8 MDIOS_DOUTR8 MDIOS output data register 0x1A0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR9 MDIOS_DOUTR9 MDIOS output data register 0x1A4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only HWCFGR MDIOS_HWCFGR MDIOS HW configuration register 0x3F0 32 read-only n 0x0 0x0 NBREG NBREG 0 8 read-only IPIDR MDIOS_IPIDR MDIOS identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only RDFR MDIOS_RDFR MDIOS read flag register 0xC 32 read-only n 0x0 0x0 RDF RDF 0 32 read-only SIDR MDIOS_SIDR MDIOS size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SR MDIOS_SR MDIOS status register 0x14 32 read-only n 0x0 0x0 PERF PERF 0 1 read-only SERF SERF 1 1 read-only TERF TERF 2 1 read-only VERR MDIOS_VERR MDIOS version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only WRFR MDIOS_WRFR MDIOS write flag register 0x4 32 read-only n 0x0 0x0 WRF WRF 0 32 read-only MDMA MDMA1 MDMA1 0x0 0x0 0x1000 registers n C0BNDTR MDMA_C0BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x54 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C0BRUR MDMA_C0BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x60 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C0CR MDMA_C0CR This register is used to control the concerned channel. 0x4C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C0DAR MDMA_C0DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x5C 32 read-write n 0x0 0x0 DAR DAR 0 32 C0ESR MDMA_C0ESR MDMA channel 0 error status register 0x48 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C0IFCR MDMA_C0IFCR MDMA channel 0 interrupt flag clear register 0x44 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C0ISR MDMA_C0ISR MDMA channel 0 interrupt/status register 0x40 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C0LAR MDMA_C0LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x64 32 read-write n 0x0 0x0 LAR LAR 0 32 C0MAR MDMA_C0MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x70 32 read-write n 0x0 0x0 MAR MAR 0 32 C0MDR MDMA_C0MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x74 32 read-write n 0x0 0x0 MDR MDR 0 32 C0SAR MDMA_C0SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x58 32 read-write n 0x0 0x0 SAR SAR 0 32 C0TBR MDMA_C0TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x68 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C0TCR MDMA_C0TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x50 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C10BNDTR MDMA_C10BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x2D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C10BRUR MDMA_C10BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x2E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C10CR MDMA_C10CR This register is used to control the concerned channel. 0x2CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C10DAR MDMA_C10DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x2DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C10ESR MDMA_C10ESR MDMA channel 10 error status register 0x2C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C10IFCR MDMA_C10IFCR MDMA channel 10 interrupt flag clear register 0x2C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C10ISR MDMA_C10ISR MDMA channel 10 interrupt/status register 0x2C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C10LAR MDMA_C10LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x2E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C10MAR MDMA_C10MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x2F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C10MDR MDMA_C10MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x2F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C10SAR MDMA_C10SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x2D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C10TBR MDMA_C10TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x2E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C10TCR MDMA_C10TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x2D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C11BNDTR MDMA_C11BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x314 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C11BRUR MDMA_C11BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x320 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C11CR MDMA_C11CR This register is used to control the concerned channel. 0x30C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C11DAR MDMA_C11DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x31C 32 read-write n 0x0 0x0 DAR DAR 0 32 C11ESR MDMA_C11ESR MDMA channel 11 error status register 0x308 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C11IFCR MDMA_C11IFCR MDMA channel 11 interrupt flag clear register 0x304 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C11ISR MDMA_C11ISR MDMA channel 11 interrupt/status register 0x300 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C11LAR MDMA_C11LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x324 32 read-write n 0x0 0x0 LAR LAR 0 32 C11MAR MDMA_C11MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x330 32 read-write n 0x0 0x0 MAR MAR 0 32 C11MDR MDMA_C11MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x334 32 read-write n 0x0 0x0 MDR MDR 0 32 C11SAR MDMA_C11SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x318 32 read-write n 0x0 0x0 SAR SAR 0 32 C11TBR MDMA_C11TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x328 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C11TCR MDMA_C11TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x310 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C12BNDTR MDMA_C12BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x354 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C12BRUR MDMA_C12BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x360 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C12CR MDMA_C12CR This register is used to control the concerned channel. 0x34C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C12DAR MDMA_C12DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x35C 32 read-write n 0x0 0x0 DAR DAR 0 32 C12ESR MDMA_C12ESR MDMA channel 12 error status register 0x348 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C12IFCR MDMA_C12IFCR MDMA channel 12 interrupt flag clear register 0x344 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C12ISR MDMA_C12ISR MDMA channel 12 interrupt/status register 0x340 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C12LAR MDMA_C12LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x364 32 read-write n 0x0 0x0 LAR LAR 0 32 C12MAR MDMA_C12MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x370 32 read-write n 0x0 0x0 MAR MAR 0 32 C12MDR MDMA_C12MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x374 32 read-write n 0x0 0x0 MDR MDR 0 32 C12SAR MDMA_C12SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x358 32 read-write n 0x0 0x0 SAR SAR 0 32 C12TBR MDMA_C12TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x368 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C12TCR MDMA_C12TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x350 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C13BNDTR MDMA_C13BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x394 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C13BRUR MDMA_C13BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x3A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C13CR MDMA_C13CR This register is used to control the concerned channel. 0x38C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C13DAR MDMA_C13DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x39C 32 read-write n 0x0 0x0 DAR DAR 0 32 C13ESR MDMA_C13ESR MDMA channel 13 error status register 0x388 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C13IFCR MDMA_C13IFCR MDMA channel 13 interrupt flag clear register 0x384 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C13ISR MDMA_C13ISR MDMA channel 13 interrupt/status register 0x380 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C13LAR MDMA_C13LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x3A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C13MAR MDMA_C13MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x3B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C13MDR MDMA_C13MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x3B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C13SAR MDMA_C13SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x398 32 read-write n 0x0 0x0 SAR SAR 0 32 C13TBR MDMA_C13TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x3A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C13TCR MDMA_C13TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x390 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C14BNDTR MDMA_C14BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x3D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C14BRUR MDMA_C14BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x3E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C14CR MDMA_C14CR This register is used to control the concerned channel. 0x3CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C14DAR MDMA_C14DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x3DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C14ESR MDMA_C14ESR MDMA channel 14 error status register 0x3C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C14IFCR MDMA_C14IFCR MDMA channel 14 interrupt flag clear register 0x3C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C14ISR MDMA_C14ISR MDMA channel 14 interrupt/status register 0x3C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C14LAR MDMA_C14LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x3E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C14MAR MDMA_C14MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x3F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C14MDR MDMA_C14MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x3F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C14SAR MDMA_C14SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x3D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C14TBR MDMA_C14TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x3E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C14TCR MDMA_C14TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x3D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C15BNDTR MDMA_C15BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x414 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C15BRUR MDMA_C15BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x420 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C15CR MDMA_C15CR This register is used to control the concerned channel. 0x40C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C15DAR MDMA_C15DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x41C 32 read-write n 0x0 0x0 DAR DAR 0 32 C15ESR MDMA_C15ESR MDMA channel 15 error status register 0x408 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C15IFCR MDMA_C15IFCR MDMA channel 15 interrupt flag clear register 0x404 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C15ISR MDMA_C15ISR MDMA channel 15 interrupt/status register 0x400 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C15LAR MDMA_C15LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x424 32 read-write n 0x0 0x0 LAR LAR 0 32 C15MAR MDMA_C15MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x430 32 read-write n 0x0 0x0 MAR MAR 0 32 C15MDR MDMA_C15MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x434 32 read-write n 0x0 0x0 MDR MDR 0 32 C15SAR MDMA_C15SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x418 32 read-write n 0x0 0x0 SAR SAR 0 32 C15TBR MDMA_C15TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x428 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C15TCR MDMA_C15TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x410 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C16BNDTR MDMA_C16BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x454 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C16BRUR MDMA_C16BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x460 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C16CR MDMA_C16CR This register is used to control the concerned channel. 0x44C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C16DAR MDMA_C16DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x45C 32 read-write n 0x0 0x0 DAR DAR 0 32 C16ESR MDMA_C16ESR MDMA channel 16 error status register 0x448 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C16IFCR MDMA_C16IFCR MDMA channel 16 interrupt flag clear register 0x444 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C16ISR MDMA_C16ISR MDMA channel 16 interrupt/status register 0x440 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C16LAR MDMA_C16LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x464 32 read-write n 0x0 0x0 LAR LAR 0 32 C16MAR MDMA_C16MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x470 32 read-write n 0x0 0x0 MAR MAR 0 32 C16MDR MDMA_C16MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x474 32 read-write n 0x0 0x0 MDR MDR 0 32 C16SAR MDMA_C16SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x458 32 read-write n 0x0 0x0 SAR SAR 0 32 C16TBR MDMA_C16TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x468 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C16TCR MDMA_C16TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x450 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C17BNDTR MDMA_C17BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x494 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C17BRUR MDMA_C17BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x4A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C17CR MDMA_C17CR This register is used to control the concerned channel. 0x48C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C17DAR MDMA_C17DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x49C 32 read-write n 0x0 0x0 DAR DAR 0 32 C17ESR MDMA_C17ESR MDMA channel 17 error status register 0x488 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C17IFCR MDMA_C17IFCR MDMA channel 17 interrupt flag clear register 0x484 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C17ISR MDMA_C17ISR MDMA channel 17 interrupt/status register 0x480 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C17LAR MDMA_C17LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x4A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C17MAR MDMA_C17MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x4B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C17MDR MDMA_C17MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x4B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C17SAR MDMA_C17SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x498 32 read-write n 0x0 0x0 SAR SAR 0 32 C17TBR MDMA_C17TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x4A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C17TCR MDMA_C17TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x490 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C18BNDTR MDMA_C18BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x4D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C18BRUR MDMA_C18BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x4E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C18CR MDMA_C18CR This register is used to control the concerned channel. 0x4CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C18DAR MDMA_C18DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x4DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C18ESR MDMA_C18ESR MDMA channel 18 error status register 0x4C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C18IFCR MDMA_C18IFCR MDMA channel 18 interrupt flag clear register 0x4C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C18ISR MDMA_C18ISR MDMA channel 18 interrupt/status register 0x4C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C18LAR MDMA_C18LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x4E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C18MAR MDMA_C18MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x4F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C18MDR MDMA_C18MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x4F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C18SAR MDMA_C18SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x4D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C18TBR MDMA_C18TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x4E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C18TCR MDMA_C18TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x4D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C19BNDTR MDMA_C19BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x514 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C19BRUR MDMA_C19BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x520 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C19CR MDMA_C19CR This register is used to control the concerned channel. 0x50C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C19DAR MDMA_C19DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x51C 32 read-write n 0x0 0x0 DAR DAR 0 32 C19ESR MDMA_C19ESR MDMA channel 19 error status register 0x508 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C19IFCR MDMA_C19IFCR MDMA channel 19 interrupt flag clear register 0x504 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C19ISR MDMA_C19ISR MDMA channel 19 interrupt/status register 0x500 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C19LAR MDMA_C19LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x524 32 read-write n 0x0 0x0 LAR LAR 0 32 C19MAR MDMA_C19MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x530 32 read-write n 0x0 0x0 MAR MAR 0 32 C19MDR MDMA_C19MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x534 32 read-write n 0x0 0x0 MDR MDR 0 32 C19SAR MDMA_C19SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x518 32 read-write n 0x0 0x0 SAR SAR 0 32 C19TBR MDMA_C19TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x528 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C19TCR MDMA_C19TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x510 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C1BNDTR MDMA_C1BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x94 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C1BRUR MDMA_C1BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0xA0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C1CR MDMA_C1CR This register is used to control the concerned channel. 0x8C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C1DAR MDMA_C1DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x9C 32 read-write n 0x0 0x0 DAR DAR 0 32 C1ESR MDMA_C1ESR MDMA channel 1 error status register 0x88 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C1IFCR MDMA_C1IFCR MDMA channel 1 interrupt flag clear register 0x84 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C1ISR MDMA_C1ISR MDMA channel 1 interrupt/status register 0x80 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C1LAR MDMA_C1LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0xA4 32 read-write n 0x0 0x0 LAR LAR 0 32 C1MAR MDMA_C1MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0xB0 32 read-write n 0x0 0x0 MAR MAR 0 32 C1MDR MDMA_C1MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0xB4 32 read-write n 0x0 0x0 MDR MDR 0 32 C1SAR MDMA_C1SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x98 32 read-write n 0x0 0x0 SAR SAR 0 32 C1TBR MDMA_C1TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0xA8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C1TCR MDMA_C1TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x90 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C20BNDTR MDMA_C20BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x554 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C20BRUR MDMA_C20BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x560 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C20CR MDMA_C20CR This register is used to control the concerned channel. 0x54C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C20DAR MDMA_C20DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x55C 32 read-write n 0x0 0x0 DAR DAR 0 32 C20ESR MDMA_C20ESR MDMA channel 20 error status register 0x548 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C20IFCR MDMA_C20IFCR MDMA channel 20 interrupt flag clear register 0x544 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C20ISR MDMA_C20ISR MDMA channel 20 interrupt/status register 0x540 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C20LAR MDMA_C20LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x564 32 read-write n 0x0 0x0 LAR LAR 0 32 C20MAR MDMA_C20MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x570 32 read-write n 0x0 0x0 MAR MAR 0 32 C20MDR MDMA_C20MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x574 32 read-write n 0x0 0x0 MDR MDR 0 32 C20SAR MDMA_C20SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x558 32 read-write n 0x0 0x0 SAR SAR 0 32 C20TBR MDMA_C20TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x568 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C20TCR MDMA_C20TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x550 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C21BNDTR MDMA_C21BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x594 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C21BRUR MDMA_C21BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x5A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C21CR MDMA_C21CR This register is used to control the concerned channel. 0x58C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C21DAR MDMA_C21DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x59C 32 read-write n 0x0 0x0 DAR DAR 0 32 C21ESR MDMA_C21ESR MDMA channel 21 error status register 0x588 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C21IFCR MDMA_C21IFCR MDMA channel 21 interrupt flag clear register 0x584 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C21ISR MDMA_C21ISR MDMA channel 21 interrupt/status register 0x580 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C21LAR MDMA_C21LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x5A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C21MAR MDMA_C21MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x5B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C21MDR MDMA_C21MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x5B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C21SAR MDMA_C21SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x598 32 read-write n 0x0 0x0 SAR SAR 0 32 C21TBR MDMA_C21TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x5A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C21TCR MDMA_C21TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x590 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C22BNDTR MDMA_C22BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x5D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C22BRUR MDMA_C22BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x5E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C22CR MDMA_C22CR This register is used to control the concerned channel. 0x5CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C22DAR MDMA_C22DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x5DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C22ESR MDMA_C22ESR MDMA channel 22 error status register 0x5C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C22IFCR MDMA_C22IFCR MDMA channel 22 interrupt flag clear register 0x5C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C22ISR MDMA_C22ISR MDMA channel 22 interrupt/status register 0x5C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C22LAR MDMA_C22LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x5E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C22MAR MDMA_C22MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x5F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C22MDR MDMA_C22MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x5F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C22SAR MDMA_C22SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x5D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C22TBR MDMA_C22TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x5E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C22TCR MDMA_C22TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x5D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C23BNDTR MDMA_C23BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x614 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C23BRUR MDMA_C23BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x620 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C23CR MDMA_C23CR This register is used to control the concerned channel. 0x60C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C23DAR MDMA_C23DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x61C 32 read-write n 0x0 0x0 DAR DAR 0 32 C23ESR MDMA_C23ESR MDMA channel 23 error status register 0x608 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C23IFCR MDMA_C23IFCR MDMA channel 23 interrupt flag clear register 0x604 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C23ISR MDMA_C23ISR MDMA channel 23 interrupt/status register 0x600 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C23LAR MDMA_C23LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x624 32 read-write n 0x0 0x0 LAR LAR 0 32 C23MAR MDMA_C23MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x630 32 read-write n 0x0 0x0 MAR MAR 0 32 C23MDR MDMA_C23MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x634 32 read-write n 0x0 0x0 MDR MDR 0 32 C23SAR MDMA_C23SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x618 32 read-write n 0x0 0x0 SAR SAR 0 32 C23TBR MDMA_C23TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x628 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C23TCR MDMA_C23TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x610 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C24BNDTR MDMA_C24BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x654 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C24BRUR MDMA_C24BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x660 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C24CR MDMA_C24CR This register is used to control the concerned channel. 0x64C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C24DAR MDMA_C24DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x65C 32 read-write n 0x0 0x0 DAR DAR 0 32 C24ESR MDMA_C24ESR MDMA channel 24 error status register 0x648 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C24IFCR MDMA_C24IFCR MDMA channel 24 interrupt flag clear register 0x644 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C24ISR MDMA_C24ISR MDMA channel 24 interrupt/status register 0x640 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C24LAR MDMA_C24LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x664 32 read-write n 0x0 0x0 LAR LAR 0 32 C24MAR MDMA_C24MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x670 32 read-write n 0x0 0x0 MAR MAR 0 32 C24MDR MDMA_C24MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x674 32 read-write n 0x0 0x0 MDR MDR 0 32 C24SAR MDMA_C24SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x658 32 read-write n 0x0 0x0 SAR SAR 0 32 C24TBR MDMA_C24TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x668 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C24TCR MDMA_C24TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x650 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C25BNDTR MDMA_C25BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x694 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C25BRUR MDMA_C25BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x6A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C25CR MDMA_C25CR This register is used to control the concerned channel. 0x68C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C25DAR MDMA_C25DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x69C 32 read-write n 0x0 0x0 DAR DAR 0 32 C25ESR MDMA_C25ESR MDMA channel 25 error status register 0x688 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C25IFCR MDMA_C25IFCR MDMA channel 25 interrupt flag clear register 0x684 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C25ISR MDMA_C25ISR MDMA channel 25 interrupt/status register 0x680 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C25LAR MDMA_C25LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x6A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C25MAR MDMA_C25MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x6B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C25MDR MDMA_C25MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x6B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C25SAR MDMA_C25SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x698 32 read-write n 0x0 0x0 SAR SAR 0 32 C25TBR MDMA_C25TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x6A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C25TCR MDMA_C25TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x690 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C26BNDTR MDMA_C26BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x6D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C26BRUR MDMA_C26BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x6E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C26CR MDMA_C26CR This register is used to control the concerned channel. 0x6CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C26DAR MDMA_C26DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x6DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C26ESR MDMA_C26ESR MDMA channel 26 error status register 0x6C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C26IFCR MDMA_C26IFCR MDMA channel 26 interrupt flag clear register 0x6C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C26ISR MDMA_C26ISR MDMA channel 26 interrupt/status register 0x6C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C26LAR MDMA_C26LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x6E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C26MAR MDMA_C26MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x6F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C26MDR MDMA_C26MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x6F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C26SAR MDMA_C26SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x6D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C26TBR MDMA_C26TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x6E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C26TCR MDMA_C26TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x6D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C27BNDTR MDMA_C27BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x714 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C27BRUR MDMA_C27BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x720 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C27CR MDMA_C27CR This register is used to control the concerned channel. 0x70C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C27DAR MDMA_C27DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x71C 32 read-write n 0x0 0x0 DAR DAR 0 32 C27ESR MDMA_C27ESR MDMA channel 27 error status register 0x708 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C27IFCR MDMA_C27IFCR MDMA channel 27 interrupt flag clear register 0x704 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C27ISR MDMA_C27ISR MDMA channel 27 interrupt/status register 0x700 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C27LAR MDMA_C27LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x724 32 read-write n 0x0 0x0 LAR LAR 0 32 C27MAR MDMA_C27MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x730 32 read-write n 0x0 0x0 MAR MAR 0 32 C27MDR MDMA_C27MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x734 32 read-write n 0x0 0x0 MDR MDR 0 32 C27SAR MDMA_C27SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x718 32 read-write n 0x0 0x0 SAR SAR 0 32 C27TBR MDMA_C27TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x728 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C27TCR MDMA_C27TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x710 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C28BNDTR MDMA_C28BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x754 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C28BRUR MDMA_C28BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x760 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C28CR MDMA_C28CR This register is used to control the concerned channel. 0x74C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C28DAR MDMA_C28DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x75C 32 read-write n 0x0 0x0 DAR DAR 0 32 C28ESR MDMA_C28ESR MDMA channel 28 error status register 0x748 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C28IFCR MDMA_C28IFCR MDMA channel 28 interrupt flag clear register 0x744 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C28ISR MDMA_C28ISR MDMA channel 28 interrupt/status register 0x740 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C28LAR MDMA_C28LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x764 32 read-write n 0x0 0x0 LAR LAR 0 32 C28MAR MDMA_C28MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x770 32 read-write n 0x0 0x0 MAR MAR 0 32 C28MDR MDMA_C28MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x774 32 read-write n 0x0 0x0 MDR MDR 0 32 C28SAR MDMA_C28SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x758 32 read-write n 0x0 0x0 SAR SAR 0 32 C28TBR MDMA_C28TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x768 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C28TCR MDMA_C28TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x750 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C29BNDTR MDMA_C29BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x794 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C29BRUR MDMA_C29BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x7A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C29CR MDMA_C29CR This register is used to control the concerned channel. 0x78C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C29DAR MDMA_C29DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x79C 32 read-write n 0x0 0x0 DAR DAR 0 32 C29ESR MDMA_C29ESR MDMA channel 29 error status register 0x788 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C29IFCR MDMA_C29IFCR MDMA channel 29 interrupt flag clear register 0x784 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C29ISR MDMA_C29ISR MDMA channel 29 interrupt/status register 0x780 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C29LAR MDMA_C29LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x7A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C29MAR MDMA_C29MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x7B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C29MDR MDMA_C29MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x7B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C29SAR MDMA_C29SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x798 32 read-write n 0x0 0x0 SAR SAR 0 32 C29TBR MDMA_C29TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x7A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C29TCR MDMA_C29TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x790 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C2BNDTR MDMA_C2BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0xD4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C2BRUR MDMA_C2BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0xE0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C2CR MDMA_C2CR This register is used to control the concerned channel. 0xCC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C2DAR MDMA_C2DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0xDC 32 read-write n 0x0 0x0 DAR DAR 0 32 C2ESR MDMA_C2ESR MDMA channel 2 error status register 0xC8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C2IFCR MDMA_C2IFCR MDMA channel 2 interrupt flag clear register 0xC4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C2ISR MDMA_C2ISR MDMA channel 2 interrupt/status register 0xC0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C2LAR MDMA_C2LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0xE4 32 read-write n 0x0 0x0 LAR LAR 0 32 C2MAR MDMA_C2MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0xF0 32 read-write n 0x0 0x0 MAR MAR 0 32 C2MDR MDMA_C2MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0xF4 32 read-write n 0x0 0x0 MDR MDR 0 32 C2SAR MDMA_C2SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0xD8 32 read-write n 0x0 0x0 SAR SAR 0 32 C2TBR MDMA_C2TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0xE8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C2TCR MDMA_C2TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0xD0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C30BNDTR MDMA_C30BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x7D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C30BRUR MDMA_C30BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x7E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C30CR MDMA_C30CR This register is used to control the concerned channel. 0x7CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C30DAR MDMA_C30DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x7DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C30ESR MDMA_C30ESR MDMA channel 30 error status register 0x7C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C30IFCR MDMA_C30IFCR MDMA channel 30 interrupt flag clear register 0x7C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C30ISR MDMA_C30ISR MDMA channel 30 interrupt/status register 0x7C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C30LAR MDMA_C30LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x7E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C30MAR MDMA_C30MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x7F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C30MDR MDMA_C30MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x7F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C30SAR MDMA_C30SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x7D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C30TBR MDMA_C30TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x7E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C30TCR MDMA_C30TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x7D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C31BNDTR MDMA_C31BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x814 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C31BRUR MDMA_C31BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x820 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C31CR MDMA_C31CR This register is used to control the concerned channel. 0x80C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C31DAR MDMA_C31DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x81C 32 read-write n 0x0 0x0 DAR DAR 0 32 C31ESR MDMA_C31ESR MDMA channel 31 error status register 0x808 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C31IFCR MDMA_C31IFCR MDMA channel 31 interrupt flag clear register 0x804 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C31ISR MDMA_C31ISR MDMA channel 31 interrupt/status register 0x800 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C31LAR MDMA_C31LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x824 32 read-write n 0x0 0x0 LAR LAR 0 32 C31MAR MDMA_C31MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x830 32 read-write n 0x0 0x0 MAR MAR 0 32 C31MDR MDMA_C31MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x834 32 read-write n 0x0 0x0 MDR MDR 0 32 C31SAR MDMA_C31SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x818 32 read-write n 0x0 0x0 SAR SAR 0 32 C31TBR MDMA_C31TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x828 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C31TCR MDMA_C31TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x810 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C3BNDTR MDMA_C3BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x114 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C3BRUR MDMA_C3BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x120 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C3CR MDMA_C3CR This register is used to control the concerned channel. 0x10C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C3DAR MDMA_C3DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x11C 32 read-write n 0x0 0x0 DAR DAR 0 32 C3ESR MDMA_C3ESR MDMA channel 3 error status register 0x108 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C3IFCR MDMA_C3IFCR MDMA channel 3 interrupt flag clear register 0x104 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C3ISR MDMA_C3ISR MDMA channel 3 interrupt/status register 0x100 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C3LAR MDMA_C3LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x124 32 read-write n 0x0 0x0 LAR LAR 0 32 C3MAR MDMA_C3MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x130 32 read-write n 0x0 0x0 MAR MAR 0 32 C3MDR MDMA_C3MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x134 32 read-write n 0x0 0x0 MDR MDR 0 32 C3SAR MDMA_C3SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x118 32 read-write n 0x0 0x0 SAR SAR 0 32 C3TBR MDMA_C3TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x128 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C3TCR MDMA_C3TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x110 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C4BNDTR MDMA_C4BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x154 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C4BRUR MDMA_C4BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x160 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C4CR MDMA_C4CR This register is used to control the concerned channel. 0x14C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C4DAR MDMA_C4DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x15C 32 read-write n 0x0 0x0 DAR DAR 0 32 C4ESR MDMA_C4ESR MDMA channel 4 error status register 0x148 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C4IFCR MDMA_C4IFCR MDMA channel 4 interrupt flag clear register 0x144 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C4ISR MDMA_C4ISR MDMA channel 4 interrupt/status register 0x140 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C4LAR MDMA_C4LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x164 32 read-write n 0x0 0x0 LAR LAR 0 32 C4MAR MDMA_C4MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x170 32 read-write n 0x0 0x0 MAR MAR 0 32 C4MDR MDMA_C4MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x174 32 read-write n 0x0 0x0 MDR MDR 0 32 C4SAR MDMA_C4SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x158 32 read-write n 0x0 0x0 SAR SAR 0 32 C4TBR MDMA_C4TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x168 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C4TCR MDMA_C4TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x150 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C5BNDTR MDMA_C5BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x194 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C5BRUR MDMA_C5BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x1A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C5CR MDMA_C5CR This register is used to control the concerned channel. 0x18C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C5DAR MDMA_C5DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x19C 32 read-write n 0x0 0x0 DAR DAR 0 32 C5ESR MDMA_C5ESR MDMA channel 5 error status register 0x188 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C5IFCR MDMA_C5IFCR MDMA channel 5 interrupt flag clear register 0x184 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C5ISR MDMA_C5ISR MDMA channel 5 interrupt/status register 0x180 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C5LAR MDMA_C5LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x1A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C5MAR MDMA_C5MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x1B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C5MDR MDMA_C5MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x1B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C5SAR MDMA_C5SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x198 32 read-write n 0x0 0x0 SAR SAR 0 32 C5TBR MDMA_C5TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x1A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C5TCR MDMA_C5TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x190 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C6BNDTR MDMA_C6BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x1D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C6BRUR MDMA_C6BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x1E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C6CR MDMA_C6CR This register is used to control the concerned channel. 0x1CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C6DAR MDMA_C6DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x1DC 32 read-write n 0x0 0x0 DAR DAR 0 32 C6ESR MDMA_C6ESR MDMA channel 6 error status register 0x1C8 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C6IFCR MDMA_C6IFCR MDMA channel 6 interrupt flag clear register 0x1C4 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C6ISR MDMA_C6ISR MDMA channel 6 interrupt/status register 0x1C0 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C6LAR MDMA_C6LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x1E4 32 read-write n 0x0 0x0 LAR LAR 0 32 C6MAR MDMA_C6MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x1F0 32 read-write n 0x0 0x0 MAR MAR 0 32 C6MDR MDMA_C6MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x1F4 32 read-write n 0x0 0x0 MDR MDR 0 32 C6SAR MDMA_C6SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x1D8 32 read-write n 0x0 0x0 SAR SAR 0 32 C6TBR MDMA_C6TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x1E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C6TCR MDMA_C6TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x1D0 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C7BNDTR MDMA_C7BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x214 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C7BRUR MDMA_C7BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x220 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C7CR MDMA_C7CR This register is used to control the concerned channel. 0x20C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C7DAR MDMA_C7DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x21C 32 read-write n 0x0 0x0 DAR DAR 0 32 C7ESR MDMA_C7ESR MDMA channel 7 error status register 0x208 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C7IFCR MDMA_C7IFCR MDMA channel 7 interrupt flag clear register 0x204 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C7ISR MDMA_C7ISR MDMA channel 7 interrupt/status register 0x200 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C7LAR MDMA_C7LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x224 32 read-write n 0x0 0x0 LAR LAR 0 32 C7MAR MDMA_C7MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x230 32 read-write n 0x0 0x0 MAR MAR 0 32 C7MDR MDMA_C7MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x234 32 read-write n 0x0 0x0 MDR MDR 0 32 C7SAR MDMA_C7SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x218 32 read-write n 0x0 0x0 SAR SAR 0 32 C7TBR MDMA_C7TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x228 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C7TCR MDMA_C7TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x210 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C8BNDTR MDMA_C8BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x254 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C8BRUR MDMA_C8BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x260 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C8CR MDMA_C8CR This register is used to control the concerned channel. 0x24C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C8DAR MDMA_C8DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x25C 32 read-write n 0x0 0x0 DAR DAR 0 32 C8ESR MDMA_C8ESR MDMA channel 8 error status register 0x248 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C8IFCR MDMA_C8IFCR MDMA channel 8 interrupt flag clear register 0x244 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C8ISR MDMA_C8ISR MDMA channel 8 interrupt/status register 0x240 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C8LAR MDMA_C8LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x264 32 read-write n 0x0 0x0 LAR LAR 0 32 C8MAR MDMA_C8MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x270 32 read-write n 0x0 0x0 MAR MAR 0 32 C8MDR MDMA_C8MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x274 32 read-write n 0x0 0x0 MDR MDR 0 32 C8SAR MDMA_C8SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x258 32 read-write n 0x0 0x0 SAR SAR 0 32 C8TBR MDMA_C8TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x268 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C8TCR MDMA_C8TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x250 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 C9BNDTR MDMA_C9BNDTR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04). 0x294 32 read-write n 0x0 0x0 BNDT BNDT 0 17 BRC BRC 20 12 BRDUM BRDUM 19 1 BRSUM BRSUM 18 1 C9BRUR MDMA_C9BRUR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10). 0x2A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C9CR MDMA_C9CR This register is used to control the concerned channel. 0x28C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write BRTIE BRTIE 3 1 read-write BTIE BTIE 4 1 read-write CTCIE CTCIE 2 1 read-write EN EN 0 1 read-write HEX HEX 13 1 read-write PL PL 6 2 read-write SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write TEIE TEIE 1 1 read-write WEX WEX 14 1 read-write C9DAR MDMA_C9DAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M 0x29C 32 read-write n 0x0 0x0 DAR DAR 0 32 C9ESR MDMA_C9ESR MDMA channel 9 error status register 0x288 32 read-only n 0x0 0x0 ASE ASE 10 1 BSE BSE 11 1 TEA TEA 0 7 TED TED 7 1 TELD TELD 8 1 TEMD TEMD 9 1 C9IFCR MDMA_C9IFCR MDMA channel 9 interrupt flag clear register 0x284 32 write-only n 0x0 0x0 CBRTIF CBRTIF 2 1 CBTIF CBTIF 3 1 CCTCIF CCTCIF 1 1 CLTCIF CLTCIF 4 1 CTEIF CTEIF 0 1 C9ISR MDMA_C9ISR MDMA channel 9 interrupt/status register 0x280 32 read-only n 0x0 0x0 BRTIF BRTIF 2 1 BTIF BTIF 3 1 CRQA CRQA 16 1 CTCIF CTCIF 1 1 TCIF TCIF 4 1 TEIF TEIF 0 1 C9LAR MDMA_C9LAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block. 0x2A4 32 read-write n 0x0 0x0 LAR LAR 0 32 C9MAR MDMA_C9MAR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20). 0x2B0 32 read-write n 0x0 0x0 MAR MAR 0 32 C9MDR MDMA_C9MDR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24). 0x2B4 32 read-write n 0x0 0x0 MDR MDR 0 32 C9SAR MDMA_C9SAR In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08). 0x298 32 read-write n 0x0 0x0 SAR SAR 0 32 C9TBR MDMA_C9TBR In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18). 0x2A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 SBUS SBUS 16 1 TSEL TSEL 0 6 C9TCR MDMA_C9TCR This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00). 0x290 32 read-write n 0x0 0x0 BWM BWM 31 1 DBURST DBURST 15 3 DINC DINC 2 2 DINCOS DINCOS 10 2 DSIZE DSIZE 6 2 PAM PAM 26 2 PKE PKE 25 1 SBURST SBURST 12 3 SINC SINC 0 2 SINCOS SINCOS 8 2 SSIZE SSIZE 4 2 SWRM SWRM 30 1 TLEN TLEN 18 7 TRGM TRGM 28 2 GISR0 MDMA_GISR0 MDMA global interrupt/status register 0x0 32 read-only n 0x0 0x0 GIF0 GIF0 0 1 GIF1 GIF1 1 1 GIF10 GIF10 10 1 GIF11 GIF11 11 1 GIF12 GIF12 12 1 GIF13 GIF13 13 1 GIF14 GIF14 14 1 GIF15 GIF15 15 1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF2 GIF2 2 1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF3 GIF3 3 1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 GIF4 GIF4 4 1 GIF5 GIF5 5 1 GIF6 GIF6 6 1 GIF7 GIF7 7 1 GIF8 GIF8 8 1 GIF9 GIF9 9 1 SGISR0 MDMA_SGISR0 MDMA secure global interrupt/status register 0x8 32 read-only n 0x0 0x0 GIF0 GIF0 0 1 GIF1 GIF1 1 1 GIF10 GIF10 10 1 GIF11 GIF11 11 1 GIF12 GIF12 12 1 GIF13 GIF13 13 1 GIF14 GIF14 14 1 GIF15 GIF15 15 1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF2 GIF2 2 1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF3 GIF3 3 1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 GIF4 GIF4 4 1 GIF5 GIF5 5 1 GIF6 GIF6 6 1 GIF7 GIF7 7 1 GIF8 GIF8 8 1 GIF9 GIF9 9 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x401 registers n IABR0 IABR0 Interrupt Active Bit Register 0x200 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR3 IABR3 Interrupt Active Bit Register 0x20C 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR4 IABR4 Interrupt Active Bit Register 0x210 32 read-write n 0x0 0x0 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER3 ICER3 Interrupt Clear-Enable Register 0x8C 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER4 ICER4 Interrupt Clear-Enable Register 0x90 32 read-write n 0x0 0x0 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR3 ICPR3 Interrupt Clear-Pending Register 0x18C 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR4 ICPR4 Interrupt Clear-Pending Register 0x1C4 32 read-write n 0x0 0x0 IPR0 IPR0 Interrupt Priority Register 0x300 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR21 IPR21 Interrupt Priority Register 0x354 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR22 IPR22 Interrupt Priority Register 0x358 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR23 IPR23 Interrupt Priority Register 0x35C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR24 IPR24 Interrupt Priority Register 0x360 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR25 IPR25 Interrupt Priority Register 0x364 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR26 IPR26 Interrupt Priority Register 0x368 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR27 IPR27 Interrupt Priority Register 0x36C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR28 IPR28 Interrupt Priority Register 0x370 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR29 IPR29 Interrupt Priority Register 0x374 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR30 IPR30 Interrupt Priority Register 0x378 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR31 IPR31 Interrupt Priority Register 0x37C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR32 IPR32 Interrupt Priority Register 0x380 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR33 IPR33 Interrupt Priority Register 0x384 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR34 IPR34 Interrupt Priority Register 0x388 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR35 IPR35 Interrupt Priority Register 0x38C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR36 IPR36 Interrupt Priority Register 0x390 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR37 IPR37 Interrupt Priority Register 0x394 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR38 IPR38 Interrupt Priority Register 0x398 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER0 ISER0 Interrupt Set-Enable Register 0x0 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER3 ISER3 Interrupt Set-Enable Register 0xC 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER4 ISER4 Interrupt Set-Enable Register 0x10 32 read-write n 0x0 0x0 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR3 ISPR3 Interrupt Set-Pending Register 0x10C 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR4 ISPR4 Interrupt Set-Pending Register 0x110 32 read-write n 0x0 0x0 OTGHSFS1 OTGHSFS1 OTGHSFS1 0x0 0x0 0x1000 registers n OTG_CID OTG_CID This is a register containing the Product ID as reset value. 0x3C 32 read-write n 0x0 0x0 PRODUCT_ID PRODUCT_ID 0 32 OTG_DAINT OTG_DAINT When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx). 0x818 32 read-only n 0x0 0x0 IEPINT IEPINT 0 16 OEPINT OEPINT 16 16 OTG_DAINTMSK OTG_DAINTMSK The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set. 0x81C 32 read-write n 0x0 0x0 IEPM IEPM 0 16 OEPM OEPM 16 16 OTG_DCFG OTG_DCFG This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 0x800 32 read-write n 0x0 0x0 DAD DAD 4 7 DSPD DSPD 0 2 ERRATIM ERRATIM 15 1 NZLSOHSK NZLSOHSK 2 1 PERSCHIVL PERSCHIVL 24 2 PFIVL PFIVL 11 2 XCVRDLY XCVRDLY 14 1 OTG_DCTL OTG_DCTL OTG device control register 0x804 32 read-write n 0x0 0x0 CGINAK CGINAK 8 1 write-only CGONAK CGONAK 10 1 write-only DSBESLRJCT DSBESLRJCT 18 1 read-write GINSTS GINSTS 2 1 read-only GONSTS GONSTS 3 1 read-only POPRGDNE POPRGDNE 11 1 read-write RWUSIG RWUSIG 0 1 read-write SDIS SDIS 1 1 read-write SGINAK SGINAK 7 1 write-only SGONAK SGONAK 9 1 write-only TCTL TCTL 4 3 read-write OTG_DEACHINT OTG_DEACHINT OTG device each endpoint interrupt register 0x838 32 read-only n 0x0 0x0 IEP1INT IEP1INT 1 1 OEP1INT OEP1INT 17 1 OTG_DEACHINTMSK OTG_DEACHINTMSK There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT. 0x83C 32 read-write n 0x0 0x0 IEP1INTM IEP1INTM 1 1 OEP1INTM OEP1INTM 17 1 OTG_DIEPCTL0 OTG_DIEPCTL0 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x900 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL1 OTG_DIEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x920 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL2 OTG_DIEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x940 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL3 OTG_DIEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x960 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL4 OTG_DIEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x980 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL5 OTG_DIEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9A0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL6 OTG_DIEPCTL6 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9C0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL7 OTG_DIEPCTL7 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9E0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPCTL8 OTG_DIEPCTL8 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xA00 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only SODDFRM SODDFRM 29 1 write-only STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write USBAEP USBAEP 15 1 read-write OTG_DIEPDMA0 OTG_DIEPDMA0 OTG device IN endpoint 0 DMA address register 0x914 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA1 OTG_DIEPDMA1 OTG device IN endpoint 1 DMA address register 0x934 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA2 OTG_DIEPDMA2 OTG device IN endpoint 2 DMA address register 0x954 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA3 OTG_DIEPDMA3 OTG device IN endpoint 3 DMA address register 0x974 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA4 OTG_DIEPDMA4 OTG device IN endpoint 4 DMA address register 0x994 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA5 OTG_DIEPDMA5 OTG device IN endpoint 5 DMA address register 0x9B4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA6 OTG_DIEPDMA6 OTG device IN endpoint 6 DMA address register 0x9D4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA7 OTG_DIEPDMA7 OTG device IN endpoint 7 DMA address register 0x9F4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPDMA8 OTG_DIEPDMA8 OTG device IN endpoint 8 DMA address register 0xA14 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DIEPEMPMSK OTG_DIEPEMPMSK This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx). 0x834 32 read-write n 0x0 0x0 INEPTXFEM INEPTXFEM 0 16 OTG_DIEPINT0 OTG_DIEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x908 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT1 OTG_DIEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x928 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT2 OTG_DIEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x948 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT3 OTG_DIEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x968 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT4 OTG_DIEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x988 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT5 OTG_DIEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9A8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT6 OTG_DIEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9C8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT7 OTG_DIEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0x9E8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPINT8 OTG_DIEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xA08 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 read-write BNA BNA 9 1 read-write EPDISD EPDISD 1 1 read-write INEPNE INEPNE 6 1 read-only INEPNM INEPNM 5 1 read-write ITTXFE ITTXFE 4 1 read-write NAK NAK 13 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write TOC TOC 3 1 read-write TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write XFRC XFRC 0 1 read-write OTG_DIEPMSK OTG_DIEPMSK This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 0x810 32 read-write n 0x0 0x0 AHBERRM AHBERRM 2 1 BNAM BNAM 9 1 EPDM EPDM 1 1 INEPNEM INEPNEM 6 1 INEPNMM INEPNMM 5 1 ITTXFEMSK ITTXFEMSK 4 1 NAKM NAKM 13 1 TOM TOM 3 1 TXFURM TXFURM 8 1 XFRCM XFRCM 0 1 OTG_DIEPTSIZ0 OTG_DIEPTSIZ0 The application must modify this register before enabling endpoint 0. 0x910 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 2 XFRSIZ XFRSIZ 0 7 OTG_DIEPTSIZ1 OTG_DIEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x930 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ2 OTG_DIEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x950 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ3 OTG_DIEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x970 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ4 OTG_DIEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x990 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ5 OTG_DIEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9B0 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ6 OTG_DIEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9D0 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ7 OTG_DIEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9F0 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTSIZ8 OTG_DIEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xA10 32 read-write n 0x0 0x0 MCNT MCNT 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_DIEPTXF1 OTG_DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF2 OTG_DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF3 OTG_DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF4 OTG_DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF5 OTG_DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF6 OTG_DIEPTXF6 OTG device IN endpoint transmit FIFO 6 size register 0x118 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF7 OTG_DIEPTXF7 OTG device IN endpoint transmit FIFO 7 size register 0x11C 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DIEPTXF8 OTG_DIEPTXF8 OTG device IN endpoint transmit FIFO 8 size register 0x120 32 read-write n 0x0 0x0 INEPTXFD INEPTXFD 16 16 INEPTXSA INEPTXSA 0 16 OTG_DOEPCTL0 OTG_DOEPCTL0 This section describes the OTG_DOEPCTL0 register. 0xB00 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EPDIS EPDIS 30 1 read-only EPENA EPENA 31 1 write-only EPTYP EPTYP 18 2 read-only MPSIZ MPSIZ 0 2 read-only NAKSTS NAKSTS 17 1 read-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-only OTG_DOEPCTL1 OTG_DOEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB20 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL2 OTG_DOEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB40 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL3 OTG_DOEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB60 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL4 OTG_DOEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB80 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL5 OTG_DOEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBA0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL6 OTG_DOEPCTL6 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBC0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL7 OTG_DOEPCTL7 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBE0 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPCTL8 OTG_DOEPCTL8 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xC00 32 read-write n 0x0 0x0 CNAK CNAK 26 1 write-only EONUM_DPIP EONUM_DPIP 16 1 read-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write EPTYP EPTYP 18 2 read-write MPSIZ MPSIZ 0 11 read-write NAKSTS NAKSTS 17 1 read-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only SNAK SNAK 27 1 write-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write USBAEP USBAEP 15 1 read-write OTG_DOEPDMA0 OTG_DOEPDMA0 OTG device OUT endpoint 0 DMA address register 0xB14 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA1 OTG_DOEPDMA1 OTG device OUT endpoint 1 DMA address register 0xB34 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA2 OTG_DOEPDMA2 OTG device OUT endpoint 2 DMA address register 0xB54 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA3 OTG_DOEPDMA3 OTG device OUT endpoint 3 DMA address register 0xB74 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA4 OTG_DOEPDMA4 OTG device OUT endpoint 4 DMA address register 0xB94 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA5 OTG_DOEPDMA5 OTG device OUT endpoint 5 DMA address register 0xBB4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA6 OTG_DOEPDMA6 OTG device OUT endpoint 6 DMA address register 0xBD4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA7 OTG_DOEPDMA7 OTG device OUT endpoint 7 DMA address register 0xBF4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPDMA8 OTG_DOEPDMA8 OTG device OUT endpoint 8 DMA address register 0xC14 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_DOEPINT0 OTG_DOEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB08 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT1 OTG_DOEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB28 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT2 OTG_DOEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB48 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT3 OTG_DOEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB68 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT4 OTG_DOEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xB88 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT5 OTG_DOEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBA8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT6 OTG_DOEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBC8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT7 OTG_DOEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xBE8 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPINT8 OTG_DOEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers. 0xC08 32 read-write n 0x0 0x0 AHBERR AHBERR 2 1 B2BSTUP B2BSTUP 6 1 BERR BERR 12 1 BNA BNA 9 1 EPDISD EPDISD 1 1 NAK NAK 13 1 NYET NYET 14 1 OTEPDIS OTEPDIS 4 1 OUTPKTERR OUTPKTERR 8 1 STPKTRX STPKTRX 15 1 STSPHSRX STSPHSRX 5 1 STUP STUP 3 1 XFRC XFRC 0 1 OTG_DOEPMSK OTG_DOEPMSK This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x814 32 read-write n 0x0 0x0 AHBERRM AHBERRM 2 1 B2BSTUPM B2BSTUPM 6 1 BERRM BERRM 12 1 BNAM BNAM 9 1 EPDM EPDM 1 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 OTEPDM OTEPDM 4 1 OUTPKTERRM OUTPKTERRM 8 1 STSPHSRXM STSPHSRXM 5 1 STUPM STUPM 3 1 XFRCM XFRCM 0 1 OTG_DOEPTSIZ0 OTG_DOEPTSIZ0 The application must modify this register before enabling endpoint 0. 0xB10 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 1 STUPCNT STUPCNT 29 2 XFRSIZ XFRSIZ 0 7 OTG_DOEPTSIZ1 OTG_DOEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB30 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ2 OTG_DOEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB50 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ3 OTG_DOEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB70 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ4 OTG_DOEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB90 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ5 OTG_DOEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBB0 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ6 OTG_DOEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBD0 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ7 OTG_DOEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBF0 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DOEPTSIZ8 OTG_DOEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xC10 32 read-write n 0x0 0x0 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 XFRSIZ XFRSIZ 0 19 OTG_DSTS OTG_DSTS This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register. 0x808 32 read-only n 0x0 0x0 DEVLNSTS DEVLNSTS 22 2 EERR EERR 3 1 ENUMSPD ENUMSPD 1 2 FNSOF FNSOF 8 14 SUSPSTS SUSPSTS 0 1 OTG_DTHRCTL OTG_DTHRCTL OTG device threshold control register 0x830 32 read-write n 0x0 0x0 ARPEN ARPEN 27 1 ISOTHREN ISOTHREN 1 1 NONISOTHREN NONISOTHREN 0 1 RXTHREN RXTHREN 16 1 RXTHRLEN RXTHRLEN 17 9 TXTHRLEN TXTHRLEN 2 9 OTG_DTXFSTS0 OTG_DTXFSTS0 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x918 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS1 OTG_DTXFSTS1 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x938 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS2 OTG_DTXFSTS2 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x958 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS3 OTG_DTXFSTS3 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x978 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS4 OTG_DTXFSTS4 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x998 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS5 OTG_DTXFSTS5 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9B8 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS6 OTG_DTXFSTS6 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9D8 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS7 OTG_DTXFSTS7 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9F8 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DTXFSTS8 OTG_DTXFSTS8 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0xA18 32 read-only n 0x0 0x0 INEPTFSAV INEPTFSAV 0 16 OTG_DVBUSDIS OTG_DVBUSDIS This register specifies the VBUS discharge time after VBUS pulsing during SRP. 0x828 32 read-write n 0x0 0x0 VBUSDT VBUSDT 0 16 OTG_DVBUSPULSE OTG_DVBUSPULSE This register specifies the VBUS pulsing time during SRP. 0x82C 32 read-write n 0x0 0x0 DVBUSP DVBUSP 0 16 OTG_GAHBCFG OTG_GAHBCFG This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 0x8 32 read-write n 0x0 0x0 DMAEN DMAEN 5 1 GINTMSK GINTMSK 0 1 HBSTLEN HBSTLEN 1 4 PTXFELVL PTXFELVL 8 1 TXFELVL TXFELVL 7 1 OTG_GCCFG OTG_GCCFG OTG general core configuration register 0x38 32 read-write n 0x0 0x0 BCDEN BCDEN 17 1 read-write IDEN IDEN 22 1 read-write PDEN PDEN 19 1 read-write PDET PDET 1 1 read-only PS2DET PS2DET 3 1 read-only PWRDWN PWRDWN 16 1 read-write SDEN SDEN 20 1 read-write SDET SDET 2 1 read-only VBDEN VBDEN 21 1 read-write OTG_GINTMSK OTG_GINTMSK This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set. 0x18 32 read-write n 0x0 0x0 CIDSCHGM CIDSCHGM 28 1 read-write DISCINT DISCINT 29 1 read-write ENUMDNEM ENUMDNEM 13 1 read-write EOPFM EOPFM 15 1 read-write ESUSPM ESUSPM 10 1 read-write FSUSPM FSUSPM 22 1 read-write GINAKEFFM GINAKEFFM 6 1 read-write GONAKEFFM GONAKEFFM 7 1 read-write HCIM HCIM 25 1 read-write IEPINT IEPINT 18 1 read-write IISOIXFRM IISOIXFRM 20 1 read-write IPXFRM IPXFRM 21 1 read-write ISOODRPM ISOODRPM 14 1 read-write LPMINTM LPMINTM 27 1 read-write MMISM MMISM 1 1 read-write NPTXFEM NPTXFEM 5 1 read-write OEPINT OEPINT 19 1 read-write OTGINT OTGINT 2 1 read-write PRTIM PRTIM 24 1 read-only PTXFEM PTXFEM 26 1 read-write RSTDETM RSTDETM 23 1 read-write RXFLVLM RXFLVLM 4 1 read-write SOFM SOFM 3 1 read-write SRQIM SRQIM 30 1 read-write USBRST USBRST 12 1 read-write USBSUSPM USBSUSPM 11 1 read-write WUIM WUIM 31 1 read-write OTG_GINTSTS OTG_GINTSTS This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 0x14 32 read-write n 0x0 0x0 CIDSCHG CIDSCHG 28 1 read-write CMOD CMOD 0 1 read-only DATAFSUSP DATAFSUSP 22 1 read-write DISCINT DISCINT 29 1 read-write ENUMDNE ENUMDNE 13 1 read-write EOPF EOPF 15 1 read-write ESUSP ESUSP 10 1 read-write GINAKEFF GINAKEFF 6 1 read-only GONAKEFF GONAKEFF 7 1 read-only HCINT HCINT 25 1 read-only HPRTINT HPRTINT 24 1 read-only IEPINT IEPINT 18 1 read-only IISOIXFR IISOIXFR 20 1 read-write IPXFR IPXFR 21 1 read-write ISOODRP ISOODRP 14 1 read-write MMIS MMIS 1 1 read-write NPTXFE NPTXFE 5 1 read-only OEPINT OEPINT 19 1 read-only OTGINT OTGINT 2 1 read-only PTXFE PTXFE 26 1 read-only RXFLVL RXFLVL 4 1 read-only SOF SOF 3 1 read-write SRQINT SRQINT 30 1 read-write USBRST USBRST 12 1 read-write USBSUSP USBSUSP 11 1 read-write WKUPINT WKUPINT 31 1 read-write OTG_GLPMCFG OTG_GLPMCFG OTG core LPM configuration register 0x54 32 read-write n 0x0 0x0 BESL BESL 2 4 read-write BESLTHRS BESLTHRS 8 4 read-write ENBESL ENBESL 28 1 read-write L1DSEN L1DSEN 12 1 read-write L1RSMOK L1RSMOK 16 1 read-only L1SSEN L1SSEN 7 1 read-write LPMACK LPMACK 1 1 read-write LPMCHIDX LPMCHIDX 17 4 read-write LPMEN LPMEN 0 1 read-write LPMRCNT LPMRCNT 21 3 read-write LPMRCNTSTS LPMRCNTSTS 25 3 read-only LPMRSP LPMRSP 13 2 read-only REMWAKE REMWAKE 6 1 read-write SLPSTS SLPSTS 15 1 read-only SNDLPM SNDLPM 24 1 read-write OTG_GOTGCTL OTG_GOTGCTL The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. 0x0 32 read-write n 0x0 0x0 ASVLD ASVLD 18 1 read-only AVALOEN AVALOEN 4 1 read-write AVALOVAL AVALOVAL 5 1 read-write BSVLD BSVLD 19 1 read-only BVALOEN BVALOEN 6 1 read-write BVALOVAL BVALOVAL 7 1 read-write CIDSTS CIDSTS 16 1 read-only CURMOD CURMOD 21 1 read-only DBCT DBCT 17 1 read-only DHNPEN DHNPEN 11 1 read-write EHEN EHEN 12 1 read-write HNGSCS HNGSCS 8 1 read-only HNPRQ HNPRQ 9 1 read-write HSHNPEN HSHNPEN 10 1 read-write OTGVER OTGVER 20 1 read-write SRQ SRQ 1 1 read-write SRQSCS SRQSCS 0 1 read-only VBVALOEN VBVALOEN 2 1 read-write VBVALOVAL VBVALOVAL 3 1 read-write OTG_GOTGINT OTG_GOTGINT The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 0x4 32 read-write n 0x0 0x0 ADTOCHG ADTOCHG 18 1 DBCDNE DBCDNE 19 1 HNGDET HNGDET 17 1 HNSSCHG HNSSCHG 9 1 IDCHNG IDCHNG 20 1 SEDET SEDET 2 1 SRSSCHG SRSSCHG 8 1 OTG_GRSTCTL OTG_GRSTCTL The application uses this register to reset various hardware features inside the core. 0x10 32 read-write n 0x0 0x0 AHBIDL AHBIDL 31 1 read-only CSRST CSRST 0 1 read-write DMAREQ DMAREQ 30 1 read-only PSRST PSRST 1 1 read-write RXFFLSH RXFFLSH 4 1 read-write TXFFLSH TXFFLSH 5 1 read-write TXFNUM TXFNUM 6 5 read-write OTG_GRXFSIZ OTG_GRXFSIZ The application can program the RAM size that must be allocated to the Rx FIFO. 0x24 32 read-write n 0x0 0x0 RXFD RXFD 0 16 OTG_GRXSTSP OTG_GRXSTSP This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted. 0x20 32 read-only n 0x0 0x0 BCNT BCNT 4 11 DPID DPID 15 2 EPNUM EPNUM 0 4 FRMNUM FRMNUM 21 4 PKTSTS PKTSTS 17 4 STSPHST STSPHST 27 1 OTG_GRXSTSR OTG_GRXSTSR This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. 0x1C 32 read-only n 0x0 0x0 BCNT BCNT 4 11 DPID DPID 15 2 EPNUM EPNUM 0 4 FRMNUM FRMNUM 21 4 PKTSTS PKTSTS 17 4 STSPHST STSPHST 27 1 OTG_GUSBCFG OTG_GUSBCFG This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 0xC 32 read-write n 0x0 0x0 FDMOD FDMOD 30 1 FHMOD FHMOD 29 1 HNPCAP HNPCAP 9 1 PHYLPC PHYLPC 15 1 PHYSEL PHYSEL 6 1 SRPCAP SRPCAP 8 1 TOCAL TOCAL 0 3 TRDT TRDT 10 4 TSDPS TSDPS 22 1 OTG_HAINT OTG_HAINT When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 0x414 32 read-only n 0x0 0x0 HAINT HAINT 0 16 OTG_HAINTMSK OTG_HAINTMSK The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 0x418 32 read-write n 0x0 0x0 HAINTM HAINTM 0 16 OTG_HCCHAR0 OTG_HCCHAR0 OTG host channel 0 characteristics register 0x500 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR1 OTG_HCCHAR1 OTG host channel 1 characteristics register 0x520 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR10 OTG_HCCHAR10 OTG host channel 10 characteristics register 0x640 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR11 OTG_HCCHAR11 OTG host channel 11 characteristics register 0x660 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR12 OTG_HCCHAR12 OTG host channel 12 characteristics register 0x680 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR13 OTG_HCCHAR13 OTG host channel 13 characteristics register 0x6A0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR14 OTG_HCCHAR14 OTG host channel 14 characteristics register 0x6C0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR15 OTG_HCCHAR15 OTG host channel 15 characteristics register 0x6E0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR2 OTG_HCCHAR2 OTG host channel 2 characteristics register 0x540 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR3 OTG_HCCHAR3 OTG host channel 3 characteristics register 0x560 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR4 OTG_HCCHAR4 OTG host channel 4 characteristics register 0x580 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR5 OTG_HCCHAR5 OTG host channel 5 characteristics register 0x5A0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR6 OTG_HCCHAR6 OTG host channel 6 characteristics register 0x5C0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR7 OTG_HCCHAR7 OTG host channel 7 characteristics register 0x5E0 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR8 OTG_HCCHAR8 OTG host channel 8 characteristics register 0x600 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCCHAR9 OTG_HCCHAR9 OTG host channel 9 characteristics register 0x620 32 read-write n 0x0 0x0 CHDIS CHDIS 30 1 CHENA CHENA 31 1 DAD DAD 22 7 EPDIR EPDIR 15 1 EPNUM EPNUM 11 4 EPTYP EPTYP 18 2 LSDEV LSDEV 17 1 MCNT MCNT 20 2 MPSIZ MPSIZ 0 11 OTG_HCDMA0 OTG_HCDMA0 OTG host channel 0 DMA address register in buffer DMA [alternate] 0x514 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA1 OTG_HCDMA1 OTG host channel 1 DMA address register in buffer DMA [alternate] 0x534 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA10 OTG_HCDMA10 OTG host channel 10 DMA address register in buffer DMA [alternate] 0x654 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA11 OTG_HCDMA11 OTG host channel 11 DMA address register in buffer DMA [alternate] 0x674 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA12 OTG_HCDMA12 OTG host channel 12 DMA address register in buffer DMA [alternate] 0x694 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA13 OTG_HCDMA13 OTG host channel 13 DMA address register in buffer DMA [alternate] 0x6B4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA14 OTG_HCDMA14 OTG host channel 14 DMA address register in buffer DMA [alternate] 0x6D4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA15 OTG_HCDMA15 OTG host channel 15 DMA address register in buffer DMA [alternate] 0x6F4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA2 OTG_HCDMA2 OTG host channel 2 DMA address register in buffer DMA [alternate] 0x554 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA3 OTG_HCDMA3 OTG host channel 3 DMA address register in buffer DMA [alternate] 0x574 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA4 OTG_HCDMA4 OTG host channel 4 DMA address register in buffer DMA [alternate] 0x594 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA5 OTG_HCDMA5 OTG host channel 5 DMA address register in buffer DMA [alternate] 0x5B4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA6 OTG_HCDMA6 OTG host channel 6 DMA address register in buffer DMA [alternate] 0x5D4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA7 OTG_HCDMA7 OTG host channel 7 DMA address register in buffer DMA [alternate] 0x5F4 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA8 OTG_HCDMA8 OTG host channel 8 DMA address register in buffer DMA [alternate] 0x614 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMA9 OTG_HCDMA9 OTG host channel 9 DMA address register in buffer DMA [alternate] 0x634 32 read-write n 0x0 0x0 DMAADDR DMAADDR 0 32 OTG_HCDMAB0 OTG_HCDMAB0 OTG host channel-n DMA address buffer register 0x51C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB1 OTG_HCDMAB1 OTG host channel-n DMA address buffer register 0x53C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB10 OTG_HCDMAB10 OTG host channel-n DMA address buffer register 0x65C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB11 OTG_HCDMAB11 OTG host channel-n DMA address buffer register 0x67C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB12 OTG_HCDMAB12 OTG host channel-n DMA address buffer register 0x69C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB13 OTG_HCDMAB13 OTG host channel-n DMA address buffer register 0x6BC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB14 OTG_HCDMAB14 OTG host channel-n DMA address buffer register 0x6DC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB15 OTG_HCDMAB15 OTG host channel-n DMA address buffer register 0x6FC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB2 OTG_HCDMAB2 OTG host channel-n DMA address buffer register 0x55C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB3 OTG_HCDMAB3 OTG host channel-n DMA address buffer register 0x57C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB4 OTG_HCDMAB4 OTG host channel-n DMA address buffer register 0x59C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB5 OTG_HCDMAB5 OTG host channel-n DMA address buffer register 0x5BC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB6 OTG_HCDMAB6 OTG host channel-n DMA address buffer register 0x5DC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB7 OTG_HCDMAB7 OTG host channel-n DMA address buffer register 0x5FC 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB8 OTG_HCDMAB8 OTG host channel-n DMA address buffer register 0x61C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCDMAB9 OTG_HCDMAB9 OTG host channel-n DMA address buffer register 0x63C 32 read-only n 0x0 0x0 HCDMAB HCDMAB 0 32 OTG_HCFG OTG_HCFG This register configures the core after power-on. Do not make changes to this register after initializing the host. 0x400 32 read-write n 0x0 0x0 DESCDMA DESCDMA 23 1 read-write FRLSTEN FRLSTEN 24 2 read-write FSLSPCS FSLSPCS 0 2 read-write FSLSS FSLSS 2 1 read-only PERSSCHEDENA PERSSCHEDENA 26 1 read-write OTG_HCINT0 OTG_HCINT0 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x508 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT1 OTG_HCINT1 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x528 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT10 OTG_HCINT10 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x648 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT11 OTG_HCINT11 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x668 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT12 OTG_HCINT12 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x688 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT13 OTG_HCINT13 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6A8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT14 OTG_HCINT14 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6C8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT15 OTG_HCINT15 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x6E8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT2 OTG_HCINT2 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x548 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT3 OTG_HCINT3 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x568 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT4 OTG_HCINT4 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x588 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT5 OTG_HCINT5 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5A8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT6 OTG_HCINT6 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5C8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT7 OTG_HCINT7 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x5E8 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT8 OTG_HCINT8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x608 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINT9 OTG_HCINT9 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers. 0x628 32 read-write n 0x0 0x0 ACK ACK 5 1 AHBERR AHBERR 2 1 BBERR BBERR 8 1 BNA BNA 11 1 CHH CHH 1 1 DESCLSTROLL DESCLSTROLL 13 1 DTERR DTERR 10 1 FRMOR FRMOR 9 1 NAK NAK 4 1 NYET NYET 6 1 STALL STALL 3 1 TXERR TXERR 7 1 XCSXACTERR XCSXACTERR 12 1 XFRC XFRC 0 1 OTG_HCINTMSK0 OTG_HCINTMSK0 This register reflects the mask for each channel status described in the previous section. 0x50C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK1 OTG_HCINTMSK1 This register reflects the mask for each channel status described in the previous section. 0x52C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK10 OTG_HCINTMSK10 This register reflects the mask for each channel status described in the previous section. 0x64C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK11 OTG_HCINTMSK11 This register reflects the mask for each channel status described in the previous section. 0x66C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK12 OTG_HCINTMSK12 This register reflects the mask for each channel status described in the previous section. 0x68C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK13 OTG_HCINTMSK13 This register reflects the mask for each channel status described in the previous section. 0x6AC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK14 OTG_HCINTMSK14 This register reflects the mask for each channel status described in the previous section. 0x6CC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK15 OTG_HCINTMSK15 This register reflects the mask for each channel status described in the previous section. 0x6EC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK2 OTG_HCINTMSK2 This register reflects the mask for each channel status described in the previous section. 0x54C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK3 OTG_HCINTMSK3 This register reflects the mask for each channel status described in the previous section. 0x56C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK4 OTG_HCINTMSK4 This register reflects the mask for each channel status described in the previous section. 0x58C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK5 OTG_HCINTMSK5 This register reflects the mask for each channel status described in the previous section. 0x5AC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK6 OTG_HCINTMSK6 This register reflects the mask for each channel status described in the previous section. 0x5CC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK7 OTG_HCINTMSK7 This register reflects the mask for each channel status described in the previous section. 0x5EC 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK8 OTG_HCINTMSK8 This register reflects the mask for each channel status described in the previous section. 0x60C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCINTMSK9 OTG_HCINTMSK9 This register reflects the mask for each channel status described in the previous section. 0x62C 32 read-write n 0x0 0x0 ACKM ACKM 5 1 AHBERRM AHBERRM 2 1 BBERRM BBERRM 8 1 BNAMSK BNAMSK 11 1 CHHM CHHM 1 1 DESCLSTROLLMSK DESCLSTROLLMSK 13 1 DTERRM DTERRM 10 1 FRMORM FRMORM 9 1 NAKM NAKM 4 1 NYET NYET 6 1 STALLM STALLM 3 1 TXERRM TXERRM 7 1 XFRCM XFRCM 0 1 OTG_HCSPLT0 OTG_HCSPLT0 OTG host channel 0 split control register 0x504 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT1 OTG_HCSPLT1 OTG host channel 1 split control register 0x524 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT10 OTG_HCSPLT10 OTG host channel 10 split control register 0x644 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT11 OTG_HCSPLT11 OTG host channel 11 split control register 0x664 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT12 OTG_HCSPLT12 OTG host channel 12 split control register 0x684 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT13 OTG_HCSPLT13 OTG host channel 13 split control register 0x6A4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT14 OTG_HCSPLT14 OTG host channel 14 split control register 0x6C4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT15 OTG_HCSPLT15 OTG host channel 15 split control register 0x6E4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT2 OTG_HCSPLT2 OTG host channel 2 split control register 0x544 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT3 OTG_HCSPLT3 OTG host channel 3 split control register 0x564 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT4 OTG_HCSPLT4 OTG host channel 4 split control register 0x584 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT5 OTG_HCSPLT5 OTG host channel 5 split control register 0x5A4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT6 OTG_HCSPLT6 OTG host channel 6 split control register 0x5C4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT7 OTG_HCSPLT7 OTG host channel 7 split control register 0x5E4 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT8 OTG_HCSPLT8 OTG host channel 8 split control register 0x604 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCSPLT9 OTG_HCSPLT9 OTG host channel 9 split control register 0x624 32 read-write n 0x0 0x0 COMPLSPLT COMPLSPLT 16 1 HUBADDR HUBADDR 7 7 PRTADDR PRTADDR 0 7 SPLITEN SPLITEN 31 1 XACTPOS XACTPOS 14 2 OTG_HCTSIZ0 OTG_HCTSIZ0 OTG host channel 0 transfer size register 0x510 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ1 OTG_HCTSIZ1 OTG host channel 1 transfer size register 0x530 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ10 OTG_HCTSIZ10 OTG host channel 10 transfer size register 0x650 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ11 OTG_HCTSIZ11 OTG host channel 11 transfer size register 0x670 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ12 OTG_HCTSIZ12 OTG host channel 12 transfer size register 0x690 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ13 OTG_HCTSIZ13 OTG host channel 13 transfer size register 0x6B0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ14 OTG_HCTSIZ14 OTG host channel 14 transfer size register 0x6D0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ15 OTG_HCTSIZ15 OTG host channel 15 transfer size register 0x6F0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ2 OTG_HCTSIZ2 OTG host channel 2 transfer size register 0x550 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ3 OTG_HCTSIZ3 OTG host channel 3 transfer size register 0x570 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ4 OTG_HCTSIZ4 OTG host channel 4 transfer size register 0x590 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ5 OTG_HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ6 OTG_HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ7 OTG_HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ8 OTG_HCTSIZ8 OTG host channel 8 transfer size register 0x610 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HCTSIZ9 OTG_HCTSIZ9 OTG host channel 9 transfer size register 0x630 32 read-write n 0x0 0x0 DPID DPID 29 2 PKTCNT PKTCNT 19 10 XFRSIZ XFRSIZ 0 19 OTG_HFIR OTG_HFIR This register stores the frame interval information for the current speed to which the OTG controller has enumerated. 0x404 32 read-write n 0x0 0x0 FRIVL FRIVL 0 16 RLDCTRL RLDCTRL 16 1 OTG_HFLBADDR OTG_HFLBADDR This register holds the starting address of the frame list information (scatter/gather mode). 0x41C 32 read-write n 0x0 0x0 HFLBADDR HFLBADDR 0 32 OTG_HFNUM OTG_HFNUM This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 0x408 32 read-only n 0x0 0x0 FRNUM FRNUM 0 16 FTREM FTREM 16 16 OTG_HNPTXFSIZ OTG_HNPTXFSIZ Host mode 0x28 32 read-write n 0x0 0x0 NPTXFD NPTXFD 16 16 NPTXFSA NPTXFSA 0 16 OTG_HNPTXSTS OTG_HNPTXSTS In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 0x2C 32 read-only n 0x0 0x0 NPTQXSAV NPTQXSAV 16 8 NPTXFSAV NPTXFSAV 0 16 NPTXQTOP NPTXQTOP 24 7 OTG_HPRT OTG_HPRT This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 0x440 32 read-write n 0x0 0x0 PCDET PCDET 1 1 read-write PCSTS PCSTS 0 1 read-only PENA PENA 2 1 read-write PENCHNG PENCHNG 3 1 read-write PLSTS PLSTS 10 2 read-only POCA POCA 4 1 read-only POCCHNG POCCHNG 5 1 read-write PPWR PPWR 12 1 read-write PRES PRES 6 1 read-write PRST PRST 8 1 read-write PSPD PSPD 17 2 read-only PSUSP PSUSP 7 1 read-write PTCTL PTCTL 13 4 read-write OTG_HPTXFSIZ OTG_HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 32 read-write n 0x0 0x0 PTXFSIZ PTXFSIZ 16 16 PTXSA PTXSA 0 16 OTG_HPTXSTS OTG_HPTXSTS This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 0x410 32 read-only n 0x0 0x0 PTXFSAVL PTXFSAVL 0 16 PTXQSAV PTXQSAV 16 8 PTXQTOP PTXQTOP 24 8 OTG_HS_DIEPEACHMSK1 OTG_HS_DIEPEACHMSK1 This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x844 32 read-write n 0x0 0x0 AHBERRM AHBERRM 2 1 BNAM BNAM 9 1 EPDM EPDM 1 1 INEPNEM INEPNEM 6 1 ITTXFEMSK ITTXFEMSK 4 1 NAKM NAKM 13 1 TOM TOM 3 1 TXFURM TXFURM 8 1 XFRCM XFRCM 0 1 OTG_HS_DOEPEACHMSK1 OTG_HS_DOEPEACHMSK1 This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x884 32 read-write n 0x0 0x0 AHBERRM AHBERRM 2 1 B2BSTUPM B2BSTUPM 6 1 BERRM BERRM 12 1 BNAM BNAM 9 1 EPDM EPDM 1 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 OTEPDM OTEPDM 4 1 OUTPKTERRM OUTPKTERRM 8 1 STUPM STUPM 3 1 XFRCM XFRCM 0 1 OTG_PCGCCTL OTG_PCGCCTL This register is available in host and device modes. 0xE00 32 read-write n 0x0 0x0 ENL1GTG ENL1GTG 5 1 read-write GATEHCLK GATEHCLK 1 1 read-write PHYSLEEP PHYSLEEP 6 1 read-only PHYSUSP PHYSUSP 4 1 read-only STPPCLK STPPCLK 0 1 read-write SUSP SUSP 7 1 read-only PWR PWR PWR 0x0 0x0 0x400 registers n CR1 PWR_CR1 Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. 0x0 32 read-write n 0x0 0x0 ALS ALS 17 2 AVDEN AVDEN 16 1 DBP DBP 8 1 LPCFG LPCFG 1 1 LPDS LPDS 0 1 LVDS LVDS 2 1 PLS PLS 5 3 PVDEN PVDEN 4 1 CR2 PWR_CR2 Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x8 32 read-write n 0x0 0x0 BREN BREN 0 1 read-write BRRDY BRRDY 16 1 read-only MONEN MONEN 4 1 read-write RREN RREN 1 1 read-write RRRDY RRRDY 17 1 read-only TEMPH TEMPH 23 1 read-only TEMPL TEMPL 22 1 read-only VBATH VBATH 21 1 read-only VBATL VBATL 20 1 read-only CR3 PWR_CR3 Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0xC 32 read-write n 0x0 0x0 DDRRETEN DDRRETEN 12 1 read-write DDRSRDIS DDRSRDIS 11 1 read-write DDRSREN DDRSREN 10 1 read-write POPL POPL 17 5 read-write REG11EN REG11EN 30 1 read-write REG11RDY REG11RDY 31 1 read-only REG18EN REG18EN 28 1 read-write REG18RDY REG18RDY 29 1 read-only USB33DEN USB33DEN 24 1 read-write USB33RDY USB33RDY 26 1 read-only VBE VBE 8 1 read-write VBRS VBRS 9 1 read-write CSR1 PWR_CSR1 Reset on any system reset. 0x4 32 read-only n 0x0 0x0 AVDO AVDO 16 1 PVDO PVDO 4 1 ID PWR_ID PWR IP identification register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 MCUCR PWR_MCUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x14 32 read-write n 0x0 0x0 CSSF CSSF 9 1 read-write DEEPSLEEP DEEPSLEEP 15 1 read-only PDDS PDDS 0 1 read-write SBF SBF 6 1 read-only STOPF STOPF 5 1 read-only MCUWKUPENR PWR_MCUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x2C 32 read-write n 0x0 0x0 WKUPEN1 WKUPEN1 0 1 WKUPEN2 WKUPEN2 1 1 WKUPEN3 WKUPEN3 2 1 WKUPEN4 WKUPEN4 3 1 WKUPEN5 WKUPEN5 4 1 WKUPEN6 WKUPEN6 5 1 MPUCR PWR_MPUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x10 32 read-write n 0x0 0x0 CSSF CSSF 9 1 read-write CSTBYDIS CSTBYDIS 3 1 read-write PDDS PDDS 0 1 read-write SBF SBF 6 1 read-only SBFMPU SBFMPU 7 1 read-only STANDBYWFIL2 STANDBYWFIL2 15 1 read-only STOPF STOPF 5 1 read-only MPUWKUPENR PWR_MPUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x28 32 read-write n 0x0 0x0 WKUPEN1 WKUPEN1 0 1 WKUPEN2 WKUPEN2 1 1 WKUPEN3 WKUPEN3 2 1 WKUPEN4 WKUPEN4 3 1 WKUPEN5 WKUPEN5 4 1 WKUPEN6 WKUPEN6 5 1 SID PWR_SID PWR size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VER PWR_VER PWR IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 WKUPCR PWR_WKUPCR Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x20 32 read-write n 0x0 0x0 WKUPC1 WKUPC1 0 1 WKUPC2 WKUPC2 1 1 WKUPC3 WKUPC3 2 1 WKUPC4 WKUPC4 3 1 WKUPC5 WKUPC5 4 1 WKUPC6 WKUPC6 5 1 WKUPP1 WKUPP1 8 1 WKUPP2 WKUPP2 9 1 WKUPP3 WKUPP3 10 1 WKUPP4 WKUPP4 11 1 WKUPP5 WKUPP5 12 1 WKUPP6 WKUPP6 13 1 WKUPPUPD1 WKUPPUPD1 16 2 WKUPPUPD2 WKUPPUPD2 18 2 WKUPPUPD3 WKUPPUPD3 20 2 WKUPPUPD4 WKUPPUPD4 22 2 WKUPPUPD5 WKUPPUPD5 24 2 WKUPPUPD6 WKUPPUPD6 26 2 WKUPFR PWR_WKUPFR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) 0x24 32 read-only n 0x0 0x0 WKUPF1 WKUPF1 0 1 WKUPF2 WKUPF2 1 1 WKUPF3 WKUPF3 2 1 WKUPF4 WKUPF4 3 1 WKUPF5 WKUPF5 4 1 WKUPF6 WKUPF6 5 1 QUADSPI QUADSPI1 QUADSPI1 0x0 0x0 0x1000 registers n ABR QUADSPI_ABR QUADSPI alternate bytes registers 0x1C 32 read-write n 0x0 0x0 ALTERNATE ALTERNATE 0 32 AR QUADSPI_AR QUADSPI address register 0x18 32 read-write n 0x0 0x0 ADDRESS ADDRESS 0 32 CCR QUADSPI_CCR QUADSPI communication configuration register 0x14 32 read-write n 0x0 0x0 ABMODE ABMODE 14 2 ABSIZE ABSIZE 16 2 ADMODE ADMODE 10 2 ADSIZE ADSIZE 12 2 DCYC DCYC 18 5 DDRM DDRM 31 1 DHHC DHHC 30 1 DMODE DMODE 24 2 FMODE FMODE 26 2 FRCM FRCM 29 1 IMODE IMODE 8 2 INSTRUCTION INSTRUCTION 0 8 SIOO SIOO 28 1 CR QUADSPI_CR QUADSPI control register 0x0 32 read-write n 0x0 0x0 ABORT ABORT 1 1 APMS APMS 22 1 DFM DFM 6 1 DMAEN DMAEN 2 1 EN EN 0 1 FSEL FSEL 7 1 FTHRES FTHRES 8 4 FTIE FTIE 18 1 PMM PMM 23 1 PRESCALER PRESCALER 24 8 SMIE SMIE 19 1 SSHIFT SSHIFT 4 1 TCEN TCEN 3 1 TCIE TCIE 17 1 TEIE TEIE 16 1 TOIE TOIE 20 1 DCR QUADSPI_DCR QUADSPI device configuration register 0x4 32 read-write n 0x0 0x0 CKMODE CKMODE 0 1 CSHT CSHT 8 3 FSIZE FSIZE 16 5 DLR QUADSPI_DLR QUADSPI data length register 0x10 32 read-write n 0x0 0x0 DL DL 0 32 DR QUADSPI_DR QUADSPI data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 FCR QUADSPI_FCR QUADSPI flag clear register 0xC 32 write-only n 0x0 0x0 CSMF CSMF 3 1 CTCF CTCF 1 1 CTEF CTEF 0 1 CTOF CTOF 4 1 HWCFGR QUADSPI_HWCFGR QUADSPI HW configuration register 0x3F0 32 read-only n 0x0 0x0 FIFOPTR FIFOPTR 4 4 FIFOSIZE FIFOSIZE 0 4 IDLENGTH IDLENGTH 12 4 PRESCVAL PRESCVAL 8 4 IPIDR QUADSPI_IPIDR QUADSPI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 LPTR QUADSPI_LPTR QUADSPI low-power timeout register 0x30 32 read-write n 0x0 0x0 TIMEOUT TIMEOUT 0 16 PIR QUADSPI_PIR QUADSPI polling interval register 0x2C 32 read-write n 0x0 0x0 INTERVAL INTERVAL 0 16 PSMAR QUADSPI_PSMAR QUADSPI polling status match register 0x28 32 read-write n 0x0 0x0 MATCH MATCH 0 32 PSMKR QUADSPI_PSMKR QUADSPI polling status mask register 0x24 32 read-write n 0x0 0x0 MASK MASK 0 32 SIDR QUADSPI_SIDR QUADSPI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SR QUADSPI_SR QUADSPI status register 0x8 32 read-only n 0x0 0x0 BUSY BUSY 5 1 FLEVEL FLEVEL 8 5 FTF FTF 2 1 SMF SMF 3 1 TCF TCF 1 1 TEF TEF 0 1 TOF TOF 4 1 VERR QUADSPI_VERR QUADSPI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 RCC RCC RCC 0x0 0x0 0x1000 registers n RCC RCC global interrupt 5 RCC_WAKEUP RCC MPU wakeup interrupt 145 ADCCKSELR RCC_ADCCKSELR This register is used to control the selection of the kernel clock for the ADC block. 0x928 32 read-write n 0x0 0x0 ADCSRC ADCSRC 0 2 AHB2RSTCLRR RCC_AHB2RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x99C 32 read-write n 0x0 0x0 ADC12RST ADC12RST 5 1 DMA1RST DMA1RST 0 1 DMA2RST DMA2RST 1 1 DMAMUXRST DMAMUXRST 2 1 SDMMC3RST SDMMC3RST 16 1 USBORST USBORST 8 1 AHB2RSTSETR RCC_AHB2RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x998 32 read-write n 0x0 0x0 ADC12RST ADC12RST 5 1 DMA1RST DMA1RST 0 1 DMA2RST DMA2RST 1 1 DMAMUXRST DMAMUXRST 2 1 SDMMC3RST SDMMC3RST 16 1 USBORST USBORST 8 1 AHB3RSTCLRR RCC_AHB3RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x9A4 32 read-write n 0x0 0x0 CRC2RST CRC2RST 7 1 CRYP2RST CRYP2RST 4 1 DCMIRST DCMIRST 0 1 HASH2RST HASH2RST 5 1 HSEMRST HSEMRST 11 1 IPCCRST IPCCRST 12 1 RNG2RST RNG2RST 6 1 AHB3RSTSETR RCC_AHB3RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x9A0 32 read-write n 0x0 0x0 CRC2RST CRC2RST 7 1 CRYP2RST CRYP2RST 4 1 DCMIRST DCMIRST 0 1 HASH2RST HASH2RST 5 1 HSEMRST HSEMRST 11 1 IPCCRST IPCCRST 12 1 RNG2RST RNG2RST 6 1 AHB4RSTCLRR RCC_AHB4RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x9AC 32 read-write n 0x0 0x0 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 GPIOGRST GPIOGRST 6 1 GPIOHRST GPIOHRST 7 1 GPIOIRST GPIOIRST 8 1 GPIOJRST GPIOJRST 9 1 GPIOKRST GPIOKRST 10 1 AHB4RSTSETR RCC_AHB4RSTSETR This register is used to activate the reset of the corresponding peripheral 0x9A8 32 read-write n 0x0 0x0 GPIOARST GPIOARST 0 1 GPIOBRST GPIOBRST 1 1 GPIOCRST GPIOCRST 2 1 GPIODRST GPIODRST 3 1 GPIOERST GPIOERST 4 1 GPIOFRST GPIOFRST 5 1 GPIOGRST GPIOGRST 6 1 GPIOHRST GPIOHRST 7 1 GPIOIRST GPIOIRST 8 1 GPIOJRST GPIOJRST 9 1 GPIOKRST GPIOKRST 10 1 AHB5RSTCLRR RCC_AHB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x194 32 read-write n 0x0 0x0 AXIMCRST AXIMCRST 16 1 CRYP1RST CRYP1RST 4 1 GPIOZRST GPIOZRST 0 1 HASH1RST HASH1RST 5 1 RNG1RST RNG1RST 6 1 AHB5RSTSETR RCC_AHB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x190 32 read-write n 0x0 0x0 AXIMCRST AXIMCRST 16 1 CRYP1RST CRYP1RST 4 1 GPIOZRST GPIOZRST 0 1 HASH1RST HASH1RST 5 1 RNG1RST RNG1RST 6 1 AHB6RSTCLRR RCC_AHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x19C 32 read-write n 0x0 0x0 CRC1RST CRC1RST 20 1 ETHMACRST ETHMACRST 10 1 FMCRST FMCRST 12 1 QSPIRST QSPIRST 14 1 SDMMC1RST SDMMC1RST 16 1 SDMMC2RST SDMMC2RST 17 1 USBHRST USBHRST 24 1 AHB6RSTSETR RCC_AHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x198 32 read-write n 0x0 0x0 CRC1RST CRC1RST 20 1 ETHMACRST ETHMACRST 10 1 FMCRST FMCRST 12 1 GPURST GPURST 5 1 QSPIRST QSPIRST 14 1 SDMMC1RST SDMMC1RST 16 1 SDMMC2RST SDMMC2RST 17 1 USBHRST USBHRST 24 1 APB1DIVR RCC_APB1DIVR This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information. 0x834 32 read-write n 0x0 0x0 APB1DIV APB1DIV 0 3 read-write APB1DIVRDY APB1DIVRDY 31 1 read-only APB1RSTCLRR RCC_APB1RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x984 32 read-write n 0x0 0x0 CECRST CECRST 27 1 DAC12RST DAC12RST 29 1 I2C1RST I2C1RST 21 1 I2C2RST I2C2RST 22 1 I2C3RST I2C3RST 23 1 I2C5RST I2C5RST 24 1 LPTIM1RST LPTIM1RST 9 1 MDIOSRST MDIOSRST 31 1 SPDIFRST SPDIFRST 26 1 SPI2RST SPI2RST 11 1 SPI3RST SPI3RST 12 1 TIM12RST TIM12RST 6 1 TIM13RST TIM13RST 7 1 TIM14RST TIM14RST 8 1 TIM2RST TIM2RST 0 1 TIM3RST TIM3RST 1 1 TIM4RST TIM4RST 2 1 TIM5RST TIM5RST 3 1 TIM6RST TIM6RST 4 1 TIM7RST TIM7RST 5 1 UART4RST UART4RST 16 1 UART5RST UART5RST 17 1 UART7RST UART7RST 18 1 UART8RST UART8RST 19 1 USART2RST USART2RST 14 1 USART3RST USART3RST 15 1 APB1RSTSETR RCC_APB1RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x980 32 read-write n 0x0 0x0 CECRST CECRST 27 1 DAC12RST DAC12RST 29 1 I2C1RST I2C1RST 21 1 I2C2RST I2C2RST 22 1 I2C3RST I2C3RST 23 1 I2C5RST I2C5RST 24 1 LPTIM1RST LPTIM1RST 9 1 MDIOSRST MDIOSRST 31 1 SPDIFRST SPDIFRST 26 1 SPI2RST SPI2RST 11 1 SPI3RST SPI3RST 12 1 TIM12RST TIM12RST 6 1 TIM13RST TIM13RST 7 1 TIM14RST TIM14RST 8 1 TIM2RST TIM2RST 0 1 TIM3RST TIM3RST 1 1 TIM4RST TIM4RST 2 1 TIM5RST TIM5RST 3 1 TIM6RST TIM6RST 4 1 TIM7RST TIM7RST 5 1 UART4RST UART4RST 16 1 UART5RST UART5RST 17 1 UART7RST UART7RST 18 1 UART8RST UART8RST 19 1 USART2RST USART2RST 14 1 USART3RST USART3RST 15 1 APB2DIVR RCC_APB2DIVR This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information. 0x838 32 read-write n 0x0 0x0 APB2DIV APB2DIV 0 3 read-write APB2DIVRDY APB2DIVRDY 31 1 read-only APB2RSTCLRR RCC_APB2RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x98C 32 read-write n 0x0 0x0 DFSDMRST DFSDMRST 20 1 FDCANRST FDCANRST 24 1 SAI1RST SAI1RST 16 1 SAI2RST SAI2RST 17 1 SAI3RST SAI3RST 18 1 SPI1RST SPI1RST 8 1 SPI4RST SPI4RST 9 1 SPI5RST SPI5RST 10 1 TIM15RST TIM15RST 2 1 TIM16RST TIM16RST 3 1 TIM17RST TIM17RST 4 1 TIM1RST TIM1RST 0 1 TIM8RST TIM8RST 1 1 USART6RST USART6RST 13 1 APB2RSTSETR RCC_APB2RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x988 32 read-write n 0x0 0x0 DFSDMRST DFSDMRST 20 1 FDCANRST FDCANRST 24 1 SAI1RST SAI1RST 16 1 SAI2RST SAI2RST 17 1 SAI3RST SAI3RST 18 1 SPI1RST SPI1RST 8 1 SPI4RST SPI4RST 9 1 SPI5RST SPI5RST 10 1 TIM15RST TIM15RST 2 1 TIM16RST TIM16RST 3 1 TIM17RST TIM17RST 4 1 TIM1RST TIM1RST 0 1 TIM8RST TIM8RST 1 1 USART6RST USART6RST 13 1 APB3DIVR RCC_APB3DIVR This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information. 0x83C 32 read-write n 0x0 0x0 APB3DIV APB3DIV 0 3 read-write APB3DIVRDY APB3DIVRDY 31 1 read-only APB3RSTCLRR RCC_APB3RSTCLRR This register is used to release the reset of the corresponding peripheral. 0x994 32 read-write n 0x0 0x0 DTSRST DTSRST 16 1 LPTIM2RST LPTIM2RST 0 1 LPTIM3RST LPTIM3RST 1 1 LPTIM4RST LPTIM4RST 2 1 LPTIM5RST LPTIM5RST 3 1 SAI4RST SAI4RST 8 1 SYSCFGRST SYSCFGRST 11 1 VREFRST VREFRST 13 1 APB3RSTSETR RCC_APB3RSTSETR This register is used to activate the reset of the corresponding peripheral. 0x990 32 read-write n 0x0 0x0 DTSRST DTSRST 16 1 LPTIM2RST LPTIM2RST 0 1 LPTIM3RST LPTIM3RST 1 1 LPTIM4RST LPTIM4RST 2 1 LPTIM5RST LPTIM5RST 3 1 SAI4RST SAI4RST 8 1 SYSCFGRST SYSCFGRST 11 1 VREFRST VREFRST 13 1 APB4DIVR RCC_APB4DIVR This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x3C 32 read-write n 0x0 0x0 APB4DIV APB4DIV 0 3 read-write APB4DIVRDY APB4DIVRDY 31 1 read-only APB4RSTCLRR RCC_APB4RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x184 32 read-write n 0x0 0x0 DDRPERFMRST DDRPERFMRST 8 1 DSIRST DSIRST 4 1 LTDCRST LTDCRST 0 1 USBPHYRST USBPHYRST 16 1 APB4RSTSETR RCC_APB4RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x180 32 read-write n 0x0 0x0 DDRPERFMRST DDRPERFMRST 8 1 DSIRST DSIRST 4 1 LTDCRST LTDCRST 0 1 USBPHYRST USBPHYRST 16 1 APB5DIVR RCC_APB5DIVR This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x40 32 read-write n 0x0 0x0 APB5DIV APB5DIV 0 3 read-write APB5DIVRDY APB5DIVRDY 31 1 read-only APB5RSTCLRR RCC_APB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x18C 32 read-write n 0x0 0x0 I2C4RST I2C4RST 2 1 I2C6RST I2C6RST 3 1 SPI6RST SPI6RST 0 1 STGENRST STGENRST 20 1 USART1RST USART1RST 4 1 APB5RSTSETR RCC_APB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x188 32 read-write n 0x0 0x0 I2C4RST I2C4RST 2 1 I2C6RST I2C6RST 3 1 SPI6RST SPI6RST 0 1 STGENRST STGENRST 20 1 USART1RST USART1RST 4 1 ASSCKSELR RCC_ASSCKSELR This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x24 32 read-write n 0x0 0x0 AXISSRC AXISSRC 0 3 read-write AXISSRCRDY AXISSRCRDY 31 1 read-only AXIDIVR RCC_AXIDIVR This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x30 32 read-write n 0x0 0x0 AXIDIV AXIDIV 0 3 read-write AXIDIVRDY AXIDIVRDY 31 1 read-only BDCR RCC_BDCR This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode. 0x140 32 read-write n 0x0 0x0 DIGBYP DIGBYP 3 1 read-only LSEBYP LSEBYP 1 1 read-write LSECSSD LSECSSD 9 1 read-only LSECSSON LSECSSON 8 1 read-write LSEDRV LSEDRV 4 2 read-write LSEON LSEON 0 1 read-write LSERDY LSERDY 2 1 read-only RTCCKEN RTCCKEN 20 1 read-write RTCSRC RTCSRC 16 2 read-only VSWRST VSWRST 31 1 read-write BR_RSTSCLRR RCC_BR_RSTSCLRR This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode. 0x400 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 HCSSRSTF HCSSRSTF 3 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 MCSYSRSTF MCSYSRSTF 7 1 MPSYSRSTF MPSYSRSTF 6 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 PADRSTF PADRSTF 2 1 PORRSTF PORRSTF 0 1 VCORERSTF VCORERSTF 4 1 CECCKSELR RCC_CECCKSELR This register is used to control the selection of the kernel clock for the CEC-HDMI. 0x918 32 read-write n 0x0 0x0 CECSRC CECSRC 0 2 CPERCKSELR RCC_CPERCKSELR This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays. 0xD0 32 read-write n 0x0 0x0 CKPERSRC CKPERSRC 0 2 CSICFGR RCC_CSICFGR This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details. 0x1C 32 read-write n 0x0 0x0 CSICAL CSICAL 16 8 read-only CSITRIM CSITRIM 8 5 read-write DBGCFGR RCC_DBGCFGR This is register contains the enable control of the debug and trace function, and the clock divider for the trace function. 0x80C 32 read-write n 0x0 0x0 DBGCKEN DBGCKEN 8 1 DBGRST DBGRST 12 1 TRACECKEN TRACECKEN 9 1 TRACEDIV TRACEDIV 0 3 DDRITFCR RCC_DDRITFCR This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode. 0xD8 32 read-write n 0x0 0x0 AXIDCGEN AXIDCGEN 8 1 DDRC1EN DDRC1EN 0 1 DDRC1LPEN DDRC1LPEN 1 1 DDRC2EN DDRC2EN 2 1 DDRC2LPEN DDRC2LPEN 3 1 DDRCAPBEN DDRCAPBEN 6 1 DDRCAPBLPEN DDRCAPBLPEN 7 1 DDRCAPBRST DDRCAPBRST 14 1 DDRCAXIRST DDRCAXIRST 15 1 DDRCKMOD DDRCKMOD 20 3 DDRCORERST DDRCORERST 16 1 DDRPHYCAPBEN DDRPHYCAPBEN 9 1 DDRPHYCAPBLPEN DDRPHYCAPBLPEN 10 1 DDRPHYCEN DDRPHYCEN 4 1 DDRPHYCLPEN DDRPHYCLPEN 5 1 DFILP_WIDTH DFILP_WIDTH 25 3 DPHYAPBRST DPHYAPBRST 17 1 DPHYCTLRST DPHYCTLRST 19 1 DPHYRST DPHYRST 18 1 GSKPCTRL GSKPCTRL 24 1 GSKPMOD GSKPMOD 23 1 GSKP_DUR GSKP_DUR 28 4 KERDCG_DLY KERDCG_DLY 11 3 DSICKSELR RCC_DSICKSELR This register is used to control the selection of the kernel clock for the DSI block. 0x924 32 read-write n 0x0 0x0 DSISRC DSISRC 0 1 ETHCKSELR RCC_ETHCKSELR This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8FC 32 read-write n 0x0 0x0 ETHPTPDIV ETHPTPDIV 4 4 ETHSRC ETHSRC 0 2 FDCANCKSELR RCC_FDCANCKSELR This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x90C 32 read-write n 0x0 0x0 FDCANSRC FDCANSRC 0 2 FMCCKSELR RCC_FMCCKSELR This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x904 32 read-write n 0x0 0x0 FMCSRC FMCSRC 0 2 HSICFGR RCC_HSICFGR This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x18 32 read-write n 0x0 0x0 HSICAL HSICAL 16 12 read-only HSIDIV HSIDIV 0 2 read-write HSITRIM HSITRIM 8 7 read-write I2C12CKSELR RCC_I2C12CKSELR This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C0 32 read-write n 0x0 0x0 I2C12SRC I2C12SRC 0 3 I2C35CKSELR RCC_I2C35CKSELR This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C4 32 read-write n 0x0 0x0 I2C35SRC I2C35SRC 0 3 I2C46CKSELR RCC_I2C46CKSELR This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC0 32 read-write n 0x0 0x0 I2C46SRC I2C46SRC 0 3 IDR RCC_IDR This register gives the unique identifier of the RCC 0xFF8 32 read-only n 0x0 0x0 ID ID 0 32 LPTIM1CKSELR RCC_LPTIM1CKSELR This register is used to control the selection of the kernel clock for the LPTIM1 block. 0x934 32 read-write n 0x0 0x0 LPTIM1SRC LPTIM1SRC 0 3 LPTIM23CKSELR RCC_LPTIM23CKSELR This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. 0x930 32 read-write n 0x0 0x0 LPTIM23SRC LPTIM23SRC 0 3 LPTIM45CKSELR RCC_LPTIM45CKSELR This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. 0x92C 32 read-write n 0x0 0x0 LPTIM45SRC LPTIM45SRC 0 3 MCO1CFGR RCC_MCO1CFGR This register is used to select the clock generated on MCO1 output. 0x800 32 read-write n 0x0 0x0 MCO1DIV MCO1DIV 4 4 MCO1ON MCO1ON 12 1 MCO1SEL MCO1SEL 0 3 MCO2CFGR RCC_MCO2CFGR This register is used to select the clock generated on MCO2 output. 0x804 32 read-write n 0x0 0x0 MCO2DIV MCO2DIV 4 4 MCO2ON MCO2ON 12 1 MCO2SEL MCO2SEL 0 3 MCUDIVR RCC_MCUDIVR This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x830 32 read-write n 0x0 0x0 MCUDIV MCUDIV 0 4 read-write MCUDIVRDY MCUDIVRDY 31 1 read-only MC_AHB2ENCLRR RCC_MC_AHB2ENCLRR This register is used to clear the peripheral clock enable bit 0xA9C 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 SDMMC3EN SDMMC3EN 16 1 USBOEN USBOEN 8 1 MC_AHB2ENSETR RCC_MC_AHB2ENSETR This register is used to set the peripheral clock enable bit 0xA98 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 SDMMC3EN SDMMC3EN 16 1 USBOEN USBOEN 8 1 MC_AHB2LPENCLRR RCC_MC_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB9C 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 SDMMC3LPEN SDMMC3LPEN 16 1 USBOLPEN USBOLPEN 8 1 MC_AHB2LPENSETR RCC_MC_AHB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB98 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 SDMMC3LPEN SDMMC3LPEN 16 1 USBOLPEN USBOLPEN 8 1 MC_AHB3ENCLRR RCC_MC_AHB3ENCLRR This register is used to clear the peripheral clock enable bit 0xAA4 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 CRYP2EN CRYP2EN 4 1 DCMIEN DCMIEN 0 1 HASH2EN HASH2EN 5 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 RNG2EN RNG2EN 6 1 MC_AHB3ENSETR RCC_MC_AHB3ENSETR This register is used to set the peripheral clock enable bit 0xAA0 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 CRYP2EN CRYP2EN 4 1 DCMIEN DCMIEN 0 1 HASH2EN HASH2EN 5 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 RNG2EN RNG2EN 6 1 MC_AHB3LPENCLRR RCC_MC_AHB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xBA4 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 CRYP2LPEN CRYP2LPEN 4 1 DCMILPEN DCMILPEN 0 1 HASH2LPEN HASH2LPEN 5 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 RNG2LPEN RNG2LPEN 6 1 MC_AHB3LPENSETR RCC_MC_AHB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xBA0 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 CRYP2LPEN CRYP2LPEN 4 1 DCMILPEN DCMILPEN 0 1 HASH2LPEN HASH2LPEN 5 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 RNG2LPEN RNG2LPEN 6 1 MC_AHB4ENCLRR RCC_MC_AHB4ENCLRR This register is used to clear the peripheral clock enable bit 0xAAC 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MC_AHB4ENSETR RCC_MC_AHB4ENSETR This register is used to set the peripheral clock enable bit 0xAA8 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MC_AHB4LPENCLRR RCC_MC_AHB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBAC 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MC_AHB4LPENSETR RCC_MC_AHB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xBA8 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MC_AHB5ENCLRR RCC_MC_AHB5ENCLRR This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. 0x294 32 read-write n 0x0 0x0 BKPSRAMEN BKPSRAMEN 8 1 CRYP1EN CRYP1EN 4 1 GPIOZEN GPIOZEN 0 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 MC_AHB5ENSETR RCC_MC_AHB5ENSETR This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode. 0x290 32 read-write n 0x0 0x0 BKPSRAMEN BKPSRAMEN 8 1 CRYP1EN CRYP1EN 4 1 GPIOZEN GPIOZEN 0 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 MC_AHB5LPENCLRR RCC_MC_AHB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode. 0x394 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 CRYP1LPEN CRYP1LPEN 4 1 GPIOZLPEN GPIOZLPEN 0 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 MC_AHB5LPENSETR RCC_MC_AHB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode. 0x390 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 CRYP1LPEN CRYP1LPEN 4 1 GPIOZLPEN GPIOZLPEN 0 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 MC_AHB6ENCLRR RCC_MC_AHB6ENCLRR This register is used to clear the peripheral clock enable bit 0x29C 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 ETHCKEN ETHCKEN 7 1 ETHMACEN ETHMACEN 10 1 ETHRXEN ETHRXEN 9 1 ETHTXEN ETHTXEN 8 1 FMCEN FMCEN 12 1 GPUEN GPUEN 5 1 MDMAEN MDMAEN 0 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 USBHEN USBHEN 24 1 MC_AHB6ENSETR RCC_MC_AHB6ENSETR This register is used to set the peripheral clock enable bit 0x298 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 ETHCKEN ETHCKEN 7 1 ETHMACEN ETHMACEN 10 1 ETHRXEN ETHRXEN 9 1 ETHTXEN ETHTXEN 8 1 FMCEN FMCEN 12 1 GPUEN GPUEN 5 1 MDMAEN MDMAEN 0 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 USBHEN USBHEN 24 1 MC_AHB6LPENCLRR RCC_MC_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x39C 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 ETHCKLPEN ETHCKLPEN 7 1 ETHMACLPEN ETHMACLPEN 10 1 ETHRXLPEN ETHRXLPEN 9 1 ETHSTPEN ETHSTPEN 11 1 ETHTXLPEN ETHTXLPEN 8 1 FMCLPEN FMCLPEN 12 1 GPULPEN GPULPEN 5 1 MDMALPEN MDMALPEN 0 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 USBHLPEN USBHLPEN 24 1 MC_AHB6LPENSETR RCC_MC_AHB6LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x398 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 ETHCKLPEN ETHCKLPEN 7 1 ETHMACLPEN ETHMACLPEN 10 1 ETHRXLPEN ETHRXLPEN 9 1 ETHSTPEN ETHSTPEN 11 1 ETHTXLPEN ETHTXLPEN 8 1 FMCLPEN FMCLPEN 12 1 GPULPEN GPULPEN 5 1 MDMALPEN MDMALPEN 0 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 USBHLPEN USBHLPEN 24 1 MC_APB1ENCLRR RCC_MC_APB1ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA84 32 read-write n 0x0 0x0 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 LPTIM1EN LPTIM1EN 9 1 MDIOSEN MDIOSEN 31 1 SPDIFEN SPDIFEN 26 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 MC_APB1ENSETR RCC_MC_APB1ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . 0xA80 32 read-write n 0x0 0x0 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 LPTIM1EN LPTIM1EN 9 1 MDIOSEN MDIOSEN 31 1 SPDIFEN SPDIFEN 26 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 WWDG1EN WWDG1EN 28 1 MC_APB1LPENCLRR RCC_MC_APB1LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB84 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 LPTIM1LPEN LPTIM1LPEN 9 1 MDIOSLPEN MDIOSLPEN 31 1 SPDIFLPEN SPDIFLPEN 26 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 WWDG1LPEN WWDG1LPEN 28 1 MC_APB1LPENSETR RCC_MC_APB1LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB80 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 LPTIM1LPEN LPTIM1LPEN 9 1 MDIOSLPEN MDIOSLPEN 31 1 SPDIFLPEN SPDIFLPEN 26 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 WWDG1LPEN WWDG1LPEN 28 1 MC_APB2ENCLRR RCC_MC_APB2ENCLRR This register is used to clear the peripheral clock enable bit 0xA8C 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 DFSDMEN DFSDMEN 20 1 FDCANEN FDCANEN 24 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 USART6EN USART6EN 13 1 MC_APB2ENSETR RCC_MC_APB2ENSETR This register is used to set the peripheral clock enable bit 0xA88 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 DFSDMEN DFSDMEN 20 1 FDCANEN FDCANEN 24 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 USART6EN USART6EN 13 1 MC_APB2LPENCLRR RCC_MC_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB8C 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 DFSDMLPEN DFSDMLPEN 20 1 FDCANLPEN FDCANLPEN 24 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 USART6LPEN USART6LPEN 13 1 MC_APB2LPENSETR RCC_MC_APB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB88 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 DFSDMLPEN DFSDMLPEN 20 1 FDCANLPEN FDCANLPEN 24 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 USART6LPEN USART6LPEN 13 1 MC_APB3ENCLRR RCC_MC_APB3ENCLRR This register is used to clear the peripheral clock enable bit 0xA94 32 read-write n 0x0 0x0 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 MC_APB3ENSETR RCC_MC_APB3ENSETR This register is used to set the peripheral clock enable bit 0xA90 32 read-write n 0x0 0x0 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 MC_APB3LPENCLRR RCC_MC_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0xB94 32 read-write n 0x0 0x0 DTSLPEN DTSLPEN 16 1 LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 MC_APB3LPENSETR RCC_MC_APB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0xB90 32 read-write n 0x0 0x0 DTSLPEN DTSLPEN 16 1 LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 MC_APB4ENCLRR RCC_MC_APB4ENCLRR This register is used to clear the peripheral clock enable bit 0x284 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 DSIEN DSIEN 4 1 LTDCEN LTDCEN 0 1 STGENROEN STGENROEN 20 1 USBPHYEN USBPHYEN 16 1 MC_APB4ENSETR RCC_MC_APB4ENSETR This register is used to set the peripheral clock enable bit 0x280 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 DSIEN DSIEN 4 1 LTDCEN LTDCEN 0 1 STGENROEN STGENROEN 20 1 USBPHYEN USBPHYEN 16 1 MC_APB4LPENCLRR RCC_MC_APB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x384 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 DSILPEN DSILPEN 4 1 LTDCLPEN LTDCLPEN 0 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 USBPHYLPEN USBPHYLPEN 16 1 MC_APB4LPENSETR RCC_MC_APB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x380 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 DSILPEN DSILPEN 4 1 LTDCLPEN LTDCLPEN 0 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 USBPHYLPEN USBPHYLPEN 16 1 MC_APB5ENCLRR RCC_MC_APB5ENCLRR This register is used to clear the peripheral clock enable bit 0x28C 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 RTCAPBEN RTCAPBEN 8 1 SPI6EN SPI6EN 0 1 STGENEN STGENEN 20 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 USART1EN USART1EN 4 1 MC_APB5ENSETR RCC_MC_APB5ENSETR This register is used to set the peripheral clock enable bit 0x288 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 RTCAPBEN RTCAPBEN 8 1 SPI6EN SPI6EN 0 1 STGENEN STGENEN 20 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 USART1EN USART1EN 4 1 MC_APB5LPENCLRR RCC_MC_APB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit 0x38C 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 RTCAPBLPEN RTCAPBLPEN 8 1 SPI6LPEN SPI6LPEN 0 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 USART1LPEN USART1LPEN 4 1 MC_APB5LPENSETR RCC_MC_APB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit. 0x388 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 RTCAPBLPEN RTCAPBLPEN 8 1 SPI6LPEN SPI6LPEN 0 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 USART1LPEN USART1LPEN 4 1 MC_AXIMENCLRR RCC_MC_AXIMENCLRR This register is used to clear the peripheral clock enable bit 0xAB4 32 read-write n 0x0 0x0 SYSRAMEN SYSRAMEN 0 1 MC_AXIMENSETR RCC_MC_AXIMENSETR This register is used to set the peripheral clock enable bit 0xAB0 32 read-write n 0x0 0x0 SYSRAMEN SYSRAMEN 0 1 MC_AXIMLPENCLRR RCC_MC_AXIMLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBB4 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 MC_AXIMLPENSETR RCC_MC_AXIMLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. 0xBB0 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 MC_CIER RCC_MC_CIER This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. 0xC14 32 read-write n 0x0 0x0 CSIRDYIE CSIRDYIE 4 1 HSERDYIE HSERDYIE 3 1 HSIRDYIE HSIRDYIE 2 1 LSECSSIE LSECSSIE 16 1 LSERDYIE LSERDYIE 1 1 LSIRDYIE LSIRDYIE 0 1 PLL1DYIE PLL1DYIE 8 1 PLL2DYIE PLL2DYIE 9 1 PLL3DYIE PLL3DYIE 10 1 PLL4DYIE PLL4DYIE 11 1 WKUPIE WKUPIE 20 1 MC_CIFR RCC_MC_CIFR This register shall be used by the MCU in order to read and clear the interrupt flags. 0xC18 32 read-write n 0x0 0x0 CSIRDYF CSIRDYF 4 1 HSERDYF HSERDYF 3 1 HSIRDYF HSIRDYF 2 1 LSECSSF LSECSSF 16 1 LSERDYF LSERDYF 1 1 LSIRDYF LSIRDYF 0 1 PLL1DYF PLL1DYF 8 1 PLL2DYF PLL2DYF 9 1 PLL3DYF PLL3DYF 10 1 PLL4DYF PLL4DYF 11 1 WKUPF WKUPF 20 1 MC_MLAHBENCLRR RCC_MC_MLAHBENCLRR This register is used to clear the peripheral clock enable bit 0xABC 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 MC_MLAHBENSETR RCC_MC_MLAHBENSETR This register is used to set the peripheral clock enable bit 0xAB8 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 MC_MLAHBLPENCLRR RCC_MC_MLAHBLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. 0xBBC 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 MC_MLAHBLPENSETR RCC_MC_MLAHBLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral. 0xBB8 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 MC_RSTSCLRR RCC_MC_RSTSCLRR This register is used by the MCU to check the reset source. 0xC00 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 HCSSRSTF HCSSRSTF 3 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 MCSYSRSTF MCSYSRSTF 7 1 MCURSTF MCURSTF 5 1 MPSYSRSTF MPSYSRSTF 6 1 PADRSTF PADRSTF 2 1 PORRSTF PORRSTF 0 1 VCORERSTF VCORERSTF 4 1 WWDG1RSTF WWDG1RSTF 10 1 MPCKDIVR RCC_MPCKDIVR This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x2C 32 read-write n 0x0 0x0 MPUDIV MPUDIV 0 3 read-write MPUDIVRDY MPUDIVRDY 31 1 read-only MPCKSELR RCC_MPCKSELR This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x20 32 read-write n 0x0 0x0 MPUSRC MPUSRC 0 2 read-write MPUSRCRDY MPUSRCRDY 31 1 read-only MP_AHB2ENCLRR RCC_MP_AHB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA1C 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 SDMMC3EN SDMMC3EN 16 1 USBOEN USBOEN 8 1 MP_AHB2ENSETR RCC_MP_AHB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral 0xA18 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 DMA1EN DMA1EN 0 1 DMA2EN DMA2EN 1 1 DMAMUXEN DMAMUXEN 2 1 SDMMC3EN SDMMC3EN 16 1 USBOEN USBOEN 8 1 MP_AHB2LPENCLRR RCC_MP_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB1C 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 SDMMC3LPEN SDMMC3LPEN 16 1 USBOLPEN USBOLPEN 8 1 MP_AHB2LPENSETR RCC_MP_AHB2LPENSETR This register is used by the MPU in order to set the PERxLPEN bit. 0xB18 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 DMA1LPEN DMA1LPEN 0 1 DMA2LPEN DMA2LPEN 1 1 DMAMUXLPEN DMAMUXLPEN 2 1 SDMMC3LPEN SDMMC3LPEN 16 1 USBOLPEN USBOLPEN 8 1 MP_AHB3ENCLRR RCC_MP_AHB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA24 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 CRYP2EN CRYP2EN 4 1 DCMIEN DCMIEN 0 1 HASH2EN HASH2EN 5 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 RNG2EN RNG2EN 6 1 MP_AHB3ENSETR RCC_MP_AHB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral 0xA20 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 CRYP2EN CRYP2EN 4 1 DCMIEN DCMIEN 0 1 HASH2EN HASH2EN 5 1 HSEMEN HSEMEN 11 1 IPCCEN IPCCEN 12 1 RNG2EN RNG2EN 6 1 MP_AHB3LPENCLRR RCC_MP_AHB3LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit 0xB24 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 CRYP2LPEN CRYP2LPEN 4 1 DCMILPEN DCMILPEN 0 1 HASH2LPEN HASH2LPEN 5 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 RNG2LPEN RNG2LPEN 6 1 MP_AHB3LPENSETR RCC_MP_AHB3LPENSETR This register is used by the MPU 0xB20 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 CRYP2LPEN CRYP2LPEN 4 1 DCMILPEN DCMILPEN 0 1 HASH2LPEN HASH2LPEN 5 1 HSEMLPEN HSEMLPEN 11 1 IPCCLPEN IPCCLPEN 12 1 RNG2LPEN RNG2LPEN 6 1 MP_AHB4ENCLRR RCC_MP_AHB4ENCLRR This register is used to clear the peripheral clock enable bit 0xA2C 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MP_AHB4ENSETR RCC_MP_AHB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. 0xA28 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 GPIOBEN GPIOBEN 1 1 GPIOCEN GPIOCEN 2 1 GPIODEN GPIODEN 3 1 GPIOEEN GPIOEEN 4 1 GPIOFEN GPIOFEN 5 1 GPIOGEN GPIOGEN 6 1 GPIOHEN GPIOHEN 7 1 GPIOIEN GPIOIEN 8 1 GPIOJEN GPIOJEN 9 1 GPIOKEN GPIOKEN 10 1 MP_AHB4LPENCLRR RCC_MP_AHB4LPENCLRR This register is used by the MPU 0xB2C 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MP_AHB4LPENSETR RCC_MP_AHB4LPENSETR This register is used by the MPU 0xB28 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 GPIOBLPEN GPIOBLPEN 1 1 GPIOCLPEN GPIOCLPEN 2 1 GPIODLPEN GPIODLPEN 3 1 GPIOELPEN GPIOELPEN 4 1 GPIOFLPEN GPIOFLPEN 5 1 GPIOGLPEN GPIOGLPEN 6 1 GPIOHLPEN GPIOHLPEN 7 1 GPIOILPEN GPIOILPEN 8 1 GPIOJLPEN GPIOJLPEN 9 1 GPIOKLPEN GPIOKLPEN 10 1 MP_AHB5ENCLRR RCC_MP_AHB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x214 32 read-write n 0x0 0x0 AXIMCEN AXIMCEN 16 1 BKPSRAMEN BKPSRAMEN 8 1 CRYP1EN CRYP1EN 4 1 GPIOZEN GPIOZEN 0 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 MP_AHB5ENSETR RCC_MP_AHB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x210 32 read-write n 0x0 0x0 AXIMCEN AXIMCEN 16 1 BKPSRAMEN BKPSRAMEN 8 1 CRYP1EN CRYP1EN 4 1 GPIOZEN GPIOZEN 0 1 HASH1EN HASH1EN 5 1 RNG1EN RNG1EN 6 1 MP_AHB5LPENCLRR RCC_MP_AHB5LPENCLRR This register is used by the MCU 0x314 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 CRYP1LPEN CRYP1LPEN 4 1 GPIOZLPEN GPIOZLPEN 0 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 MP_AHB5LPENSETR RCC_MP_AHB5LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x310 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 CRYP1LPEN CRYP1LPEN 4 1 GPIOZLPEN GPIOZLPEN 0 1 HASH1LPEN HASH1LPEN 5 1 RNG1LPEN RNG1LPEN 6 1 MP_AHB6ENCLRR RCC_MP_AHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x21C 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 ETHCKEN ETHCKEN 7 1 ETHMACEN ETHMACEN 10 1 ETHRXEN ETHRXEN 9 1 ETHTXEN ETHTXEN 8 1 FMCEN FMCEN 12 1 GPUEN GPUEN 5 1 MDMAEN MDMAEN 0 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 USBHEN USBHEN 24 1 MP_AHB6ENSETR RCC_MP_AHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x218 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 ETHCKEN ETHCKEN 7 1 ETHMACEN ETHMACEN 10 1 ETHRXEN ETHRXEN 9 1 ETHTXEN ETHTXEN 8 1 FMCEN FMCEN 12 1 GPUEN GPUEN 5 1 MDMAEN MDMAEN 0 1 QSPIEN QSPIEN 14 1 SDMMC1EN SDMMC1EN 16 1 SDMMC2EN SDMMC2EN 17 1 USBHEN USBHEN 24 1 MP_AHB6LPENCLRR RCC_MP_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0x31C 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 ETHCKLPEN ETHCKLPEN 7 1 ETHMACLPEN ETHMACLPEN 10 1 ETHRXLPEN ETHRXLPEN 9 1 ETHSTPEN ETHSTPEN 11 1 ETHTXLPEN ETHTXLPEN 8 1 FMCLPEN FMCLPEN 12 1 GPULPEN GPULPEN 5 1 MDMALPEN MDMALPEN 0 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 USBHLPEN USBHLPEN 24 1 MP_AHB6LPENSETR RCC_MP_AHB6LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0x318 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 ETHCKLPEN ETHCKLPEN 7 1 ETHMACLPEN ETHMACLPEN 10 1 ETHRXLPEN ETHRXLPEN 9 1 ETHSTPEN ETHSTPEN 11 1 ETHTXLPEN ETHTXLPEN 8 1 FMCLPEN FMCLPEN 12 1 GPULPEN GPULPEN 5 1 MDMALPEN MDMALPEN 0 1 QSPILPEN QSPILPEN 14 1 SDMMC1LPEN SDMMC1LPEN 16 1 SDMMC2LPEN SDMMC2LPEN 17 1 USBHLPEN USBHLPEN 24 1 MP_APB1ENCLRR RCC_MP_APB1ENCLRR This register is used to clear the peripheral clock enable bit 0xA04 32 read-write n 0x0 0x0 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 LPTIM1EN LPTIM1EN 9 1 MDIOSEN MDIOSEN 31 1 SPDIFEN SPDIFEN 26 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 MP_APB1ENSETR RCC_MP_APB1ENSETR This register is used to set the peripheral clock enable bit 0xA00 32 read-write n 0x0 0x0 CECEN CECEN 27 1 DAC12EN DAC12EN 29 1 I2C1EN I2C1EN 21 1 I2C2EN I2C2EN 22 1 I2C3EN I2C3EN 23 1 I2C5EN I2C5EN 24 1 LPTIM1EN LPTIM1EN 9 1 MDIOSEN MDIOSEN 31 1 SPDIFEN SPDIFEN 26 1 SPI2EN SPI2EN 11 1 SPI3EN SPI3EN 12 1 TIM12EN TIM12EN 6 1 TIM13EN TIM13EN 7 1 TIM14EN TIM14EN 8 1 TIM2EN TIM2EN 0 1 TIM3EN TIM3EN 1 1 TIM4EN TIM4EN 2 1 TIM5EN TIM5EN 3 1 TIM6EN TIM6EN 4 1 TIM7EN TIM7EN 5 1 UART4EN UART4EN 16 1 UART5EN UART5EN 17 1 UART7EN UART7EN 18 1 UART8EN UART8EN 19 1 USART2EN USART2EN 14 1 USART3EN USART3EN 15 1 MP_APB1LPENCLRR RCC_MP_APB1LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bits . 0xB04 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 LPTIM1LPEN LPTIM1LPEN 9 1 MDIOSLPEN MDIOSLPEN 31 1 SPDIFLPEN SPDIFLPEN 26 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 MP_APB1LPENSETR RCC_MP_APB1LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB00 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 DAC12LPEN DAC12LPEN 29 1 I2C1LPEN I2C1LPEN 21 1 I2C2LPEN I2C2LPEN 22 1 I2C3LPEN I2C3LPEN 23 1 I2C5LPEN I2C5LPEN 24 1 LPTIM1LPEN LPTIM1LPEN 9 1 MDIOSLPEN MDIOSLPEN 31 1 SPDIFLPEN SPDIFLPEN 26 1 SPI2LPEN SPI2LPEN 11 1 SPI3LPEN SPI3LPEN 12 1 TIM12LPEN TIM12LPEN 6 1 TIM13LPEN TIM13LPEN 7 1 TIM14LPEN TIM14LPEN 8 1 TIM2LPEN TIM2LPEN 0 1 TIM3LPEN TIM3LPEN 1 1 TIM4LPEN TIM4LPEN 2 1 TIM5LPEN TIM5LPEN 3 1 TIM6LPEN TIM6LPEN 4 1 TIM7LPEN TIM7LPEN 5 1 UART4LPEN UART4LPEN 16 1 UART5LPEN UART5LPEN 17 1 UART7LPEN UART7LPEN 18 1 UART8LPEN UART8LPEN 19 1 USART2LPEN USART2LPEN 14 1 USART3LPEN USART3LPEN 15 1 MP_APB2ENCLRR RCC_MP_APB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA0C 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 DFSDMEN DFSDMEN 20 1 FDCANEN FDCANEN 24 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 USART6EN USART6EN 13 1 MP_APB2ENSETR RCC_MP_APB2ENSETR This register is used to set the peripheral clock enable bit 0xA08 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 DFSDMEN DFSDMEN 20 1 FDCANEN FDCANEN 24 1 SAI1EN SAI1EN 16 1 SAI2EN SAI2EN 17 1 SAI3EN SAI3EN 18 1 SPI1EN SPI1EN 8 1 SPI4EN SPI4EN 9 1 SPI5EN SPI5EN 10 1 TIM15EN TIM15EN 2 1 TIM16EN TIM16EN 3 1 TIM17EN TIM17EN 4 1 TIM1EN TIM1EN 0 1 TIM8EN TIM8EN 1 1 USART6EN USART6EN 13 1 MP_APB2LPENCLRR RCC_MP_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB0C 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 DFSDMLPEN DFSDMLPEN 20 1 FDCANLPEN FDCANLPEN 24 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 USART6LPEN USART6LPEN 13 1 MP_APB2LPENSETR RCC_MP_APB2LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB08 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 DFSDMLPEN DFSDMLPEN 20 1 FDCANLPEN FDCANLPEN 24 1 SAI1LPEN SAI1LPEN 16 1 SAI2LPEN SAI2LPEN 17 1 SAI3LPEN SAI3LPEN 18 1 SPI1LPEN SPI1LPEN 8 1 SPI4LPEN SPI4LPEN 9 1 SPI5LPEN SPI5LPEN 10 1 TIM15LPEN TIM15LPEN 2 1 TIM16LPEN TIM16LPEN 3 1 TIM17LPEN TIM17LPEN 4 1 TIM1LPEN TIM1LPEN 0 1 TIM8LPEN TIM8LPEN 1 1 USART6LPEN USART6LPEN 13 1 MP_APB3ENCLRR RCC_MP_APB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. 0xA14 32 read-write n 0x0 0x0 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 MP_APB3ENSETR RCC_MP_APB3ENSETR This register is used to set the peripheral clock enable bit 0xA10 32 read-write n 0x0 0x0 DTSEN DTSEN 16 1 HDPEN HDPEN 20 1 LPTIM2EN LPTIM2EN 0 1 LPTIM3EN LPTIM3EN 1 1 LPTIM4EN LPTIM4EN 2 1 LPTIM5EN LPTIM5EN 3 1 SAI4EN SAI4EN 8 1 SYSCFGEN SYSCFGEN 11 1 VREFEN VREFEN 13 1 MP_APB3LPENCLRR RCC_MP_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits 0xB14 32 read-write n 0x0 0x0 DTSLPEN DTSLPEN 16 1 LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 MP_APB3LPENSETR RCC_MP_APB3LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0xB10 32 read-write n 0x0 0x0 DTSLPEN DTSLPEN 16 1 LPTIM2LPEN LPTIM2LPEN 0 1 LPTIM3LPEN LPTIM3LPEN 1 1 LPTIM4LPEN LPTIM4LPEN 2 1 LPTIM5LPEN LPTIM5LPEN 3 1 SAI4LPEN SAI4LPEN 8 1 SYSCFGLPEN SYSCFGLPEN 11 1 VREFLPEN VREFLPEN 13 1 MP_APB4ENCLRR RCC_MP_APB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x204 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 DSIEN DSIEN 4 1 IWDG2APBEN IWDG2APBEN 15 1 LTDCEN LTDCEN 0 1 STGENROEN STGENROEN 20 1 USBPHYEN USBPHYEN 16 1 MP_APB4ENSETR RCC_MP_APB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x200 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 DSIEN DSIEN 4 1 IWDG2APBEN IWDG2APBEN 15 1 LTDCEN LTDCEN 0 1 STGENROEN STGENROEN 20 1 USBPHYEN USBPHYEN 16 1 MP_APB4LPENCLRR RCC_MP_APB4LPENCLRR This register is used by the MCU 0x304 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 DSILPEN DSILPEN 4 1 IWDG2APBLPEN IWDG2APBLPEN 15 1 LTDCLPEN LTDCLPEN 0 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 USBPHYLPEN USBPHYLPEN 16 1 MP_APB4LPENSETR RCC_MP_APB4LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits 0x300 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 DSILPEN DSILPEN 4 1 IWDG2APBLPEN IWDG2APBLPEN 15 1 LTDCLPEN LTDCLPEN 0 1 STGENROLPEN STGENROLPEN 20 1 STGENROSTPEN STGENROSTPEN 21 1 USBPHYLPEN USBPHYLPEN 16 1 MP_APB5ENCLRR RCC_MP_APB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x20C 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 IWDG1APBEN IWDG1APBEN 15 1 RTCAPBEN RTCAPBEN 8 1 SPI6EN SPI6EN 0 1 STGENEN STGENEN 20 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 USART1EN USART1EN 4 1 MP_APB5ENSETR RCC_MP_APB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x208 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 I2C4EN I2C4EN 2 1 I2C6EN I2C6EN 3 1 IWDG1APBEN IWDG1APBEN 15 1 RTCAPBEN RTCAPBEN 8 1 SPI6EN SPI6EN 0 1 STGENEN STGENEN 20 1 TZC1EN TZC1EN 11 1 TZC2EN TZC2EN 12 1 TZPCEN TZPCEN 13 1 USART1EN USART1EN 4 1 MP_APB5LPENCLRR RCC_MP_APB5LPENCLRR This register is used by the Mpu. 0x30C 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 IWDG1APBLPEN IWDG1APBLPEN 15 1 RTCAPBLPEN RTCAPBLPEN 8 1 SPI6LPEN SPI6LPEN 0 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 USART1LPEN USART1LPEN 4 1 MP_APB5LPENSETR RCC_MP_APB5LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x308 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 I2C4LPEN I2C4LPEN 2 1 I2C6LPEN I2C6LPEN 3 1 IWDG1APBLPEN IWDG1APBLPEN 15 1 RTCAPBLPEN RTCAPBLPEN 8 1 SPI6LPEN SPI6LPEN 0 1 STGENLPEN STGENLPEN 20 1 STGENSTPEN STGENSTPEN 21 1 TZC1LPEN TZC1LPEN 11 1 TZC2LPEN TZC2LPEN 12 1 TZPCLPEN TZPCLPEN 13 1 USART1LPEN USART1LPEN 4 1 MP_APRSTCR RCC_MP_APRSTCR This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode. 0x110 32 read-write n 0x0 0x0 RDCTLEN RDCTLEN 0 1 RSTTO RSTTO 8 7 MP_APRSTSR RCC_MP_APRSTSR This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode. 0x114 32 read-only n 0x0 0x0 RSTTOV RSTTOV 8 7 MP_AXIMLPENCLRR RCC_MP_AXIMLPENCLRR This register is used by the MPU 0xB34 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 MP_AXIMLPENSETR RCC_MP_AXIMLPENSETR This register is used by the MPU 0xB30 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 MP_BOOTCR RCC_MP_BOOTCR This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU. 0x100 32 read-write n 0x0 0x0 MCU_BEN MCU_BEN 0 1 MPU_BEN MPU_BEN 1 1 MP_CIER RCC_MP_CIER This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x414 32 read-write n 0x0 0x0 CSIRDYIE CSIRDYIE 4 1 HSERDYIE HSERDYIE 3 1 HSIRDYIE HSIRDYIE 2 1 LSECSSIE LSECSSIE 16 1 LSERDYIE LSERDYIE 1 1 LSIRDYIE LSIRDYIE 0 1 PLL1DYIE PLL1DYIE 8 1 PLL2DYIE PLL2DYIE 9 1 PLL3DYIE PLL3DYIE 10 1 PLL4DYIE PLL4DYIE 11 1 WKUPIE WKUPIE 20 1 MP_CIFR RCC_MP_CIFR This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x418 32 read-write n 0x0 0x0 CSIRDYF CSIRDYF 4 1 HSERDYF HSERDYF 3 1 HSIRDYF HSIRDYF 2 1 LSECSSF LSECSSF 16 1 LSERDYF LSERDYF 1 1 LSIRDYF LSIRDYF 0 1 PLL1DYF PLL1DYF 8 1 PLL2DYF PLL2DYF 9 1 PLL3DYF PLL3DYF 10 1 PLL4DYF PLL4DYF 11 1 WKUPF WKUPF 20 1 MP_GCR RCC_MP_GCR The register contains global control bits. If TZEN = , this register can only be modified in secure mode. 0x10C 32 read-write n 0x0 0x0 BOOT_MCU BOOT_MCU 0 1 MP_GRSTCSETR RCC_MP_GRSTCSETR This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset. 0x404 32 read-write n 0x0 0x0 MCURST MCURST 1 1 MPSYSRST MPSYSRST 0 1 MPUP0RST MPUP0RST 4 1 MPUP1RST MPUP1RST 5 1 MP_IWDGFZCLRR RCC_MP_IWDGFZCLRR This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x410 32 read-write n 0x0 0x0 FZ_IWDG1 FZ_IWDG1 0 1 FZ_IWDG2 FZ_IWDG2 1 1 MP_IWDGFZSETR RCC_MP_IWDGFZSETR This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x40C 32 read-write n 0x0 0x0 FZ_IWDG1 FZ_IWDG1 0 1 FZ_IWDG2 FZ_IWDG2 1 1 MP_MLAHBENCLRR RCC_MP_MLAHBENCLRR This register is used to clear the peripheral clock enable bit. 0xA3C 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 MP_MLAHBENSETR RCC_MP_MLAHBENSETR This register is used to set the peripheral clock enable bit 0xA38 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 MP_MLAHBLPENCLRR RCC_MP_MLAHBLPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit 0xB3C 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 MP_MLAHBLPENSETR RCC_MP_MLAHBLPENSETR This register is used by the MPU in order to set the PERxLPEN bit 0xB38 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 SRAM1LPEN SRAM1LPEN 0 1 SRAM2LPEN SRAM2LPEN 1 1 SRAM34LPEN SRAM34LPEN 2 1 MP_RSTSCLRR RCC_MP_RSTSCLRR This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. 0x408 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 CSTDBYRSTF CSTDBYRSTF 12 1 HCSSRSTF HCSSRSTF 3 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 MCSYSRSTF MCSYSRSTF 7 1 MPSYSRSTF MPSYSRSTF 6 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 PADRSTF PADRSTF 2 1 PORRSTF PORRSTF 0 1 SPARE SPARE 15 1 STDBYRSTF STDBYRSTF 11 1 VCORERSTF VCORERSTF 4 1 MP_RSTSSETR RCC_MP_RSTSSETR This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode. 0x420 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 CSTDBYRSTF CSTDBYRSTF 12 1 HCSSRSTF HCSSRSTF 3 1 IWDG1RSTF IWDG1RSTF 8 1 IWDG2RSTF IWDG2RSTF 9 1 MCSYSRSTF MCSYSRSTF 7 1 MPSYSRSTF MPSYSRSTF 6 1 MPUP0RSTF MPUP0RSTF 13 1 MPUP1RSTF MPUP1RSTF 14 1 PADRSTF PADRSTF 2 1 PORRSTF PORRSTF 0 1 SPARE SPARE 15 1 STDBYRSTF STDBYRSTF 11 1 VCORERSTF VCORERSTF 4 1 MP_SREQCLRR RCC_MP_SREQCLRR Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x108 32 read-write n 0x0 0x0 STPREQ_P0 STPREQ_P0 0 1 STPREQ_P1 STPREQ_P1 1 1 MP_SREQSETR RCC_MP_SREQSETR Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x104 32 read-write n 0x0 0x0 STPREQ_P0 STPREQ_P0 0 1 STPREQ_P1 STPREQ_P1 1 1 MP_TZAHB6ENCLRR RCC_MP_TZAHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x224 32 read-write n 0x0 0x0 MDMAEN MDMAEN 0 1 MP_TZAHB6ENSETR RCC_MP_TZAHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x220 32 read-write n 0x0 0x0 MDMAEN MDMAEN 0 1 MP_TZAHB6LPENCLRR RCC_MP_TZAHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x324 32 read-write n 0x0 0x0 MDMALPEN MDMALPEN 0 1 MP_TZAHB6LPENSETR RCC_MP_TZAHB6LPENSETR This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode. 0x320 32 read-write n 0x0 0x0 MDMALPEN MDMALPEN 0 1 MSSCKSELR RCC_MSSCKSELR This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x48 32 read-write n 0x0 0x0 MCUSSRC MCUSSRC 0 2 read-write MCUSSRCRDY MCUSSRCRDY 31 1 read-only OCENCLRR RCC_OCENCLRR This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x10 32 read-write n 0x0 0x0 CSIKERON CSIKERON 5 1 CSION CSION 4 1 DIGBYP DIGBYP 7 1 HSEBYP HSEBYP 10 1 HSEKERON HSEKERON 9 1 HSEON HSEON 8 1 HSIKERON HSIKERON 1 1 HSION HSION 0 1 OCENSETR RCC_OCENSETR This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xC 32 read-write n 0x0 0x0 CSIKERON CSIKERON 5 1 CSION CSION 4 1 DIGBYP DIGBYP 7 1 HSEBYP HSEBYP 10 1 HSECSSON HSECSSON 11 1 HSEKERON HSEKERON 9 1 HSEON HSEON 8 1 HSIKERON HSIKERON 1 1 HSION HSION 0 1 OCRDYR RCC_OCRDYR This is a read-only access register, It contains the status flags of oscillators. Writing has no effect. 0x808 32 read-only n 0x0 0x0 AXICKRDY AXICKRDY 24 1 CKREST CKREST 25 1 CSIRDY CSIRDY 4 1 HSERDY HSERDY 8 1 HSIDIVRDY HSIDIVRDY 2 1 HSIRDY HSIRDY 0 1 MPUCKRDY MPUCKRDY 23 1 PLL1CFGR1 RCC_PLL1CFGR1 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x84 32 read-write n 0x0 0x0 DIVM1 DIVM1 16 6 DIVN DIVN 0 9 PLL1CFGR2 RCC_PLL1CFGR2 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x88 32 read-write n 0x0 0x0 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL1CR RCC_PLL1CR This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x80 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL1RDY PLL1RDY 1 1 read-only PLLON PLLON 0 1 read-write SSCG_CTRL SSCG_CTRL 2 1 read-write PLL1CSGR RCC_PLL1CSGR This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x90 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 MOD_PER MOD_PER 0 13 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 TPDFN_DIS TPDFN_DIS 13 1 PLL1FRACR RCC_PLL1FRACR This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x8C 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 FRACV FRACV 3 13 PLL2CFGR1 RCC_PLL2CFGR1 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x98 32 read-write n 0x0 0x0 DIVM2 DIVM2 16 6 DIVN DIVN 0 9 PLL2CFGR2 RCC_PLL2CFGR2 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x9C 32 read-write n 0x0 0x0 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL2CR RCC_PLL2CR This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x94 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL2RDY PLL2RDY 1 1 read-only PLLON PLLON 0 1 read-write SSCG_CTRL SSCG_CTRL 2 1 read-write PLL2CSGR RCC_PLL2CSGR This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA4 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 MOD_PER MOD_PER 0 13 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 TPDFN_DIS TPDFN_DIS 13 1 PLL2FRACR RCC_PLL2FRACR This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA0 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 FRACV FRACV 3 13 PLL3CFGR1 RCC_PLL3CFGR1 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x884 32 read-write n 0x0 0x0 DIVM3 DIVM3 16 6 DIVN DIVN 0 9 IFRGE IFRGE 24 2 PLL3CFGR2 RCC_PLL3CFGR2 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x888 32 read-write n 0x0 0x0 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL3CR RCC_PLL3CR This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x880 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL3RDY PLL3RDY 1 1 read-only PLLON PLLON 0 1 read-write SSCG_CTRL SSCG_CTRL 2 1 read-write PLL3CSGR RCC_PLL3CSGR This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x890 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 MOD_PER MOD_PER 0 13 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 TPDFN_DIS TPDFN_DIS 13 1 PLL3FRACR RCC_PLL3FRACR This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x88C 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 FRACV FRACV 3 13 PLL4CFGR1 RCC_PLL4CFGR1 This register is used to configure the PLL4. 0x898 32 read-write n 0x0 0x0 DIVM4 DIVM4 16 6 DIVN DIVN 0 9 IFRGE IFRGE 24 2 PLL4CFGR2 RCC_PLL4CFGR2 This register is used to configure the PLL4. 0x89C 32 read-write n 0x0 0x0 DIVP DIVP 0 7 DIVQ DIVQ 8 7 DIVR DIVR 16 7 PLL4CR RCC_PLL4CR This register is used to control the PLL4. 0x894 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write DIVQEN DIVQEN 5 1 read-write DIVREN DIVREN 6 1 read-write PLL4RDY PLL4RDY 1 1 read-only PLLON PLLON 0 1 read-write SSCG_CTRL SSCG_CTRL 2 1 read-write PLL4CSGR RCC_PLL4CSGR This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x8A4 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 MOD_PER MOD_PER 0 13 RPDFN_DIS RPDFN_DIS 14 1 SSCG_MODE SSCG_MODE 15 1 TPDFN_DIS TPDFN_DIS 13 1 PLL4FRACR RCC_PLL4FRACR This register is used to fine-tune the frequency of the PLL4 VCO. 0x8A0 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 FRACV FRACV 3 13 PWRLPDLYCR RCC_PWRLPDLYCR This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode. 0x41C 32 read-write n 0x0 0x0 MCTMPSKP MCTMPSKP 24 1 PWRLP_DLY PWRLP_DLY 0 22 QSPICKSELR RCC_QSPICKSELR This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x900 32 read-write n 0x0 0x0 QSPISRC QSPISRC 0 2 RCK12SELR RCC_RCK12SELR This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x28 32 read-write n 0x0 0x0 PLL12SRC PLL12SRC 0 2 read-write PLL12SRCRDY PLL12SRCRDY 31 1 read-only RCK3SELR RCC_RCK3SELR This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x820 32 read-write n 0x0 0x0 PLL3SRC PLL3SRC 0 2 read-write PLL3SRCRDY PLL3SRCRDY 31 1 read-only RCK4SELR RCC_RCK4SELR This register is used to select the reference clock for PLL4. 0x824 32 read-write n 0x0 0x0 PLL4SRC PLL4SRC 0 2 read-write PLL4SRCRDY PLL4SRCRDY 31 1 read-only RDLSICR RCC_RDLSICR This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode. 0x144 32 read-write n 0x0 0x0 EADLY EADLY 24 3 read-write LSION LSION 0 1 read-write LSIRDY LSIRDY 1 1 read-only MRD MRD 16 5 read-write SPARE SPARE 27 5 read-write RNG1CKSELR RCC_RNG1CKSELR This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xCC 32 read-write n 0x0 0x0 RNG1SRC RNG1SRC 0 2 RNG2CKSELR RCC_RNG2CKSELR This register is used to control the selection of the kernel clock for the RNG2. 0x920 32 read-write n 0x0 0x0 RNG2SRC RNG2SRC 0 2 RTCDIVR RCC_RTCDIVR This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode. 0x44 32 read-write n 0x0 0x0 RTCDIV RTCDIV 0 6 SAI1CKSELR RCC_SAI1CKSELR This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8C8 32 read-write n 0x0 0x0 SAI1SRC SAI1SRC 0 3 SAI2CKSELR RCC_SAI2CKSELR This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8CC 32 read-write n 0x0 0x0 SAI2SRC SAI2SRC 0 3 SAI3CKSELR RCC_SAI3CKSELR This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D0 32 read-write n 0x0 0x0 SAI3SRC SAI3SRC 0 3 SAI4CKSELR RCC_SAI4CKSELR This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D4 32 read-write n 0x0 0x0 SAI4SRC SAI4SRC 0 3 SDMMC12CKSELR RCC_SDMMC12CKSELR This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F4 32 read-write n 0x0 0x0 SDMMC12SRC SDMMC12SRC 0 3 SDMMC3CKSELR RCC_SDMMC3CKSELR This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F8 32 read-write n 0x0 0x0 SDMMC3SRC SDMMC3SRC 0 3 SIDR RCC_SIDR This register gives the decoding space, which is for the RCC of 4 kB. 0xFFC 32 read-only n 0x0 0x0 SID SID 0 32 SPDIFCKSELR RCC_SPDIFCKSELR This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x914 32 read-write n 0x0 0x0 SPDIFSRC SPDIFSRC 0 2 SPI2S1CKSELR RCC_SPI2S1CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8D8 32 read-write n 0x0 0x0 SPI1SRC SPI1SRC 0 3 SPI2S23CKSELR RCC_SPI2S23CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8DC 32 read-write n 0x0 0x0 SPI23SRC SPI23SRC 0 3 SPI45CKSELR RCC_SPI45CKSELR This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E0 32 read-write n 0x0 0x0 SPI45SRC SPI45SRC 0 3 SPI6CKSELR RCC_SPI6CKSELR This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC4 32 read-write n 0x0 0x0 SPI6SRC SPI6SRC 0 3 STGENCKSELR RCC_STGENCKSELR This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xD4 32 read-write n 0x0 0x0 STGENSRC STGENSRC 0 2 TIMG1PRER RCC_TIMG1PRER This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information. 0x828 32 read-write n 0x0 0x0 TIMG1PRE TIMG1PRE 0 1 read-write TIMG1PRERDY TIMG1PRERDY 31 1 read-only TIMG2PRER RCC_TIMG2PRER This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information. 0x82C 32 read-write n 0x0 0x0 TIMG2PRE TIMG2PRE 0 1 read-write TIMG2PRERDY TIMG2PRERDY 31 1 read-only TZAHB6RSTCLRR RCC_TZAHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A4 32 read-write n 0x0 0x0 MDMARST MDMARST 0 1 TZAHB6RSTSETR RCC_TZAHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A0 32 read-write n 0x0 0x0 MDMARST MDMARST 0 1 TZCR RCC_TZCR This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode. 0x0 32 read-write n 0x0 0x0 MCKPROT MCKPROT 1 1 TZEN TZEN 0 1 UART1CKSELR RCC_UART1CKSELR This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode. 0xC8 32 read-write n 0x0 0x0 UART1SRC UART1SRC 0 3 UART24CKSELR RCC_UART24CKSELR This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E8 32 read-write n 0x0 0x0 UART24SRC UART24SRC 0 3 UART35CKSELR RCC_UART35CKSELR This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8EC 32 read-write n 0x0 0x0 UART35SRC UART35SRC 0 3 UART6CKSELR RCC_UART6CKSELR This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8E4 32 read-write n 0x0 0x0 UART6SRC UART6SRC 0 3 UART78CKSELR RCC_UART78CKSELR This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. 0x8F0 32 read-write n 0x0 0x0 UART78SRC UART78SRC 0 3 USBCKSELR RCC_USBCKSELR This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG 0x91C 32 read-write n 0x0 0x0 USBOSRC USBOSRC 4 1 USBPHYSRC USBPHYSRC 0 2 VERR RCC_VERR This register gives the IP version 0xFF4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 RNG1 RNG1 RNG1 0x0 0x0 0x400 registers n RNG_CR RNG_CR RNG control register 0x0 32 read-write n 0x0 0x0 CED CED 5 1 IE IE 3 1 RNGEN RNGEN 2 1 RNG_DR RNG_DR The RNG_DR register is a read-only register. 0x8 32 read-only n 0x0 0x0 RNDATA RNDATA 0 32 RNG_HWCFGR RNG_HWCFGR RNG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 RNG_IPIDR RNG_IPIDR RNG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 RNG_SIDR RNG_SIDR RNG size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 RNG_SR RNG_SR RNG status register 0x4 32 read-write n 0x0 0x0 CECS CECS 1 1 read-only CEIS CEIS 5 1 read-write DRDY DRDY 0 1 read-only SECS SECS 2 1 read-only SEIS SEIS 6 1 read-write RNG_VERR RNG_VERR RNG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 RNG2 RNG2 RNG2 0x0 0x0 0x400 registers n RNG_CR RNG_CR RNG control register 0x0 32 read-write n 0x0 0x0 CED CED 5 1 IE IE 3 1 RNGEN RNGEN 2 1 RNG_DR RNG_DR The RNG_DR register is a read-only register. 0x8 32 read-only n 0x0 0x0 RNDATA RNDATA 0 32 RNG_HWCFGR RNG_HWCFGR RNG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 RNG_IPIDR RNG_IPIDR RNG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 RNG_SIDR RNG_SIDR RNG size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 RNG_SR RNG_SR RNG status register 0x4 32 read-write n 0x0 0x0 CECS CECS 1 1 read-only CEIS CEIS 5 1 read-write DRDY DRDY 0 1 read-only SECS SECS 2 1 read-only SEIS SEIS 6 1 read-write RNG_VERR RNG_VERR RNG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 RTC RTC RTC 0x0 0x0 0x400 registers n RTC_WKUP_ALARM RTC Tamper or TimeStamp 3 RTC_TS RTC timestamp interrupt 41 RTC_WKUP_ALARM_S RTC wakeup timer and alarms (A and B) secure interrupt 198 RTC_TS_S RTC timestamp secure interrupt 199 ALRMAR RTC_ALRMAR This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x40 32 read-write n 0x0 0x0 DT DT 28 2 DU DU 24 4 HT HT 20 2 HU HU 16 4 MNT MNT 12 3 MNU MNU 8 4 MSK1 MSK1 7 1 MSK2 MSK2 15 1 MSK3 MSK3 23 1 MSK4 MSK4 31 1 PM PM 22 1 ST ST 4 3 SU SU 0 4 WDSEL WDSEL 30 1 ALRMASSR RTC_ALRMASSR This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x44 32 read-write n 0x0 0x0 MASKSS MASKSS 24 4 SS SS 0 15 ALRMBR RTC_ALRMBR This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x48 32 read-write n 0x0 0x0 DT DT 28 2 DU DU 24 4 HT HT 20 2 HU HU 16 4 MNT MNT 12 3 MNU MNU 8 4 MSK1 MSK1 7 1 MSK2 MSK2 15 1 MSK3 MSK3 23 1 MSK4 MSK4 31 1 PM PM 22 1 ST ST 4 3 SU SU 0 4 WDSEL WDSEL 30 1 ALRMBSSR RTC_ALRMBSSR This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x4C 32 read-write n 0x0 0x0 MASKSS MASKSS 24 4 SS SS 0 15 CALR RTC_CALR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x28 32 read-write n 0x0 0x0 CALM CALM 0 9 CALP CALP 15 1 CALW16 CALW16 13 1 CALW8 CALW8 14 1 CFGR RTC_CFGR RTC configuration register 0x60 32 read-write n 0x0 0x0 LSCOEN LSCOEN 1 2 OUT2_RMP OUT2_RMP 0 1 CR RTC_CR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x18 32 read-write n 0x0 0x0 ADD1H ADD1H 16 1 write-only ALRAE ALRAE 8 1 read-write ALRAIE ALRAIE 12 1 read-write ALRBE ALRBE 9 1 read-write ALRBIE ALRBIE 13 1 read-write BKP BKP 18 1 read-write BYPSHAD BYPSHAD 5 1 read-write COE COE 23 1 read-write COSEL COSEL 19 1 read-write FMT FMT 6 1 read-write ITSE ITSE 24 1 read-write OSEL OSEL 21 2 read-write OUT2EN OUT2EN 31 1 read-write POL POL 20 1 read-write REFCKON REFCKON 4 1 read-write SUB1H SUB1H 17 1 write-only TAMPALRM_PU TAMPALRM_PU 29 1 read-write TAMPALRM_TYPE TAMPALRM_TYPE 30 1 read-write TAMPOE TAMPOE 26 1 read-write TAMPTS TAMPTS 25 1 read-write TSE TSE 11 1 read-write TSEDGE TSEDGE 3 1 read-write TSIE TSIE 15 1 read-write WUCKSEL WUCKSEL 0 3 read-write WUTE WUTE 10 1 read-write WUTIE WUTIE 14 1 read-write DR RTC_DR The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x4 32 read-write n 0x0 0x0 DT DT 4 2 DU DU 0 4 MT MT 12 1 MU MU 8 4 WDU WDU 13 3 YT YT 20 4 YU YU 16 4 HWCFGR RTC_HWCFGR RTC hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ALARMB ALARMB 0 4 OPTIONREG_OUT OPTIONREG_OUT 16 8 SMOOTH_CALIB SMOOTH_CALIB 8 4 TIMESTAMP TIMESTAMP 12 4 TRUST_ZONE TRUST_ZONE 24 4 WAKEUP WAKEUP 4 4 ICSR RTC_ICSR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0xC 32 read-write n 0x0 0x0 ALRAWF ALRAWF 0 1 read-only ALRBWF ALRBWF 1 1 read-only INIT INIT 7 1 read-write INITF INITF 6 1 read-only INITS INITS 4 1 read-only RECALPF RECALPF 16 1 read-only RSF RSF 5 1 read-write SHPF SHPF 3 1 read-only WUTWF WUTWF 2 1 read-only IPIDR RTC_IPIDR RTC identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 MISR RTC_MISR RTC non-secure masked interrupt status register 0x54 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 ITSMF ITSMF 5 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 WUTMF WUTMF 2 1 PRER RTC_PRER This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x10 32 read-write n 0x0 0x0 PREDIV_A PREDIV_A 16 7 PREDIV_S PREDIV_S 0 15 SCR RTC_SCR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x5C 32 write-only n 0x0 0x0 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CITSF CITSF 5 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CWUTF CWUTF 2 1 SHIFTR RTC_SHIFTR This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x2C 32 write-only n 0x0 0x0 ADD1S ADD1S 31 1 SUBFS SUBFS 0 15 SIDR RTC_SIDR RTC size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SMCR RTC_SMCR This register can be written only when the APB access is secure. 0x20 32 read-write n 0x0 0x0 ALRADPROT ALRADPROT 0 1 ALRBDPROT ALRBDPROT 1 1 CALDPROT CALDPROT 13 1 DECPROT DECPROT 15 1 INITDPROT INITDPROT 14 1 TSDPROT TSDPROT 3 1 WUTDPROT WUTDPROT 2 1 SMISR RTC_SMISR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x58 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 ITSMF ITSMF 5 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 WUTMF WUTMF 2 1 SR RTC_SR This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x50 32 read-only n 0x0 0x0 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 ITSF ITSF 5 1 TSF TSF 3 1 TSOVF TSOVF 4 1 WUTF WUTF 2 1 SSR RTC_SSR RTC sub second register 0x8 32 read-only n 0x0 0x0 SS SS 0 16 TR RTC_TR The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x0 32 read-write n 0x0 0x0 HT HT 20 2 HU HU 16 4 MNT MNT 12 3 MNU MNU 8 4 PM PM 22 1 ST ST 4 3 SU SU 0 4 TSDR RTC_TSDR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x34 32 read-only n 0x0 0x0 DT DT 4 2 DU DU 0 4 MT MT 12 1 MU MU 8 4 WDU WDU 13 3 TSSSR RTC_TSSSR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x38 32 read-only n 0x0 0x0 SS SS 0 16 TSTR RTC_TSTR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x30 32 read-only n 0x0 0x0 HT HT 20 2 HU HU 16 4 MNT MNT 12 3 MNU MNU 8 4 PM PM 22 1 ST ST 4 3 SU SU 0 4 VERR RTC_VERR RTC version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 WPR RTC_WPR RTC write protection register 0x24 32 write-only n 0x0 0x0 KEY KEY 0 8 WUTR RTC_WUTR This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes. 0x14 32 read-write n 0x0 0x0 WUT WUT 0 16 SAI1 SAI1 register block SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 0x14 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 0x34 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN SYNCIN 0 2 SYNCOUT SYNCOUT 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IPIDR SAI_IPIDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 MICNBR MICNBR 4 2 PDMEN PDMEN 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI2 SAI1 register block SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 0x14 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 0x34 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN SYNCIN 0 2 SYNCOUT SYNCOUT 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IPIDR SAI_IPIDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 MICNBR MICNBR 4 2 PDMEN PDMEN 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI3 SAI1 register block SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 0x14 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 0x34 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN SYNCIN 0 2 SYNCOUT SYNCOUT 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IPIDR SAI_IPIDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 MICNBR MICNBR 4 2 PDMEN PDMEN 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI4 SAI1 register block SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 0x14 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET CAFSDET 5 1 CCNRDY CCNRDY 4 1 CLFSDET CLFSDET 6 1 CMUTEDET CMUTEDET 1 1 COVRUDR COVRUDR 0 1 CWCKCFG CWCKCFG 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR CKSTR 9 1 DMAEN DMAEN 17 1 DS DS 5 3 LSBFIRST LSBFIRST 8 1 MCKDIV MCKDIV 20 6 MCKEN MCKEN 27 1 MODE MODE 0 2 MONO MONO 12 1 NODIV NODIV 19 1 OSR OSR 26 1 OUTDRIV OUTDRIV 13 1 PRTCFG PRTCFG 2 2 SAIEN SAIEN 16 1 SYNCEN SYNCEN 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP COMP 14 2 read-write CPL CPL 13 1 read-write FFLUSH FFLUSH 3 1 write-only FTH FTH 0 3 read-write MUTE MUTE 5 1 read-write MUTECNT MUTECNT 7 6 read-write MUTEVAL MUTEVAL 6 1 read-write TRIS TRIS 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA DATA 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL FRL 0 8 read-write FSALL FSALL 8 7 read-write FSDEF FSDEF 16 1 read-only FSOFF FSOFF 18 1 read-write FSPOL FSPOL 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 0x34 32 read-write n 0x0 0x0 AFSDETIE AFSDETIE 5 1 CNRDYIE CNRDYIE 4 1 FREQIE FREQIE 3 1 LFSDETIE LFSDETIE 6 1 MUTEDETIE MUTEDETIE 1 1 OVRUDRIE OVRUDRIE 0 1 WCKCFGIE WCKCFGIE 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF FBOFF 0 5 NBSLOT NBSLOT 8 4 SLOTEN SLOTEN 16 16 SLOTSZ SLOTSZ 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET AFSDET 5 1 CNRDY CNRDY 4 1 FLVL FLVL 16 3 FREQ FREQ 3 1 LFSDET LFSDET 6 1 MUTEDET MUTEDET 1 1 OVRUDR OVRUDR 0 1 WCKCFG WCKCFG 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN SYNCIN 0 2 SYNCOUT SYNCOUT 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IPIDR SAI_IPIDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 MICNBR MICNBR 4 2 PDMEN PDMEN 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SDMMC1 SDMMC1 SDMMC2 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME ACKTIME 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG CMDARG 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED BUSSPEED 19 1 CLKDIV CLKDIV 0 10 DDR DDR 18 1 HWFC_EN HWFC_EN 17 1 NEGEDGE NEGEDGE 16 1 PWRSAV PWRSAV 12 1 SELCLKRX SELCLKRX 20 2 WIDBUS WIDBUS 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN BOOTEN 15 1 BOOTMODE BOOTMODE 14 1 CMDINDEX CMDINDEX 0 6 CMDSTOP CMDSTOP 7 1 CMDSUSPEND CMDSUSPEND 16 1 CMDTRANS CMDTRANS 6 1 CPSMEN CPSMEN 12 1 DTHOLD DTHOLD 13 1 WAITINT WAITINT 10 1 WAITPEND WAITPEND 11 1 WAITRESP WAITRESP 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT DATACOUNT 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN BOOTACKEN 12 1 DBLOCKSIZE DBLOCKSIZE 4 4 DTDIR DTDIR 1 1 DTEN DTEN 0 1 DTMODE DTMODE 2 2 FIFORST FIFORST 13 1 RWMOD RWMOD 10 1 RWSTART RWSTART 8 1 RWSTOP RWSTOP 9 1 SDIOEN SDIOEN 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH DATALENGTH 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME DATATIME 0 32 SDMMC_FIFOR0 SDMMC_FIFOR0 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR1 SDMMC_FIFOR1 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x84 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR10 SDMMC_FIFOR10 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR11 SDMMC_FIFOR11 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xAC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR12 SDMMC_FIFOR12 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR13 SDMMC_FIFOR13 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR14 SDMMC_FIFOR14 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR15 SDMMC_FIFOR15 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xBC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR2 SDMMC_FIFOR2 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x88 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR3 SDMMC_FIFOR3 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x8C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR4 SDMMC_FIFOR4 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x90 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR5 SDMMC_FIFOR5 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x94 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR6 SDMMC_FIFOR6 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x98 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR7 SDMMC_FIFOR7 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x9C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR8 SDMMC_FIFOR8 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR9 SDMMC_FIFOR9 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAILC 23 1 ACKTIMEOUTC ACKTIMEOUTC 24 1 BUSYD0ENDC BUSYD0ENDC 21 1 CCRCFAILC CCRCFAILC 0 1 CKSTOPC CKSTOPC 26 1 CMDRENDC CMDRENDC 6 1 CMDSENTC CMDSENTC 7 1 CTIMEOUTC CTIMEOUTC 2 1 DABORTC DABORTC 11 1 DATAENDC DATAENDC 8 1 DBCKENDC DBCKENDC 10 1 DCRCFAILC DCRCFAILC 1 1 DHOLDC DHOLDC 9 1 DTIMEOUTC DTIMEOUTC 3 1 IDMABTCC IDMABTCC 28 1 IDMATEC IDMATEC 27 1 RXOVERRC RXOVERRC 5 1 SDIOITC SDIOITC 22 1 TXUNDERRC TXUNDERRC 4 1 VSWENDC VSWENDC 25 1 SDMMC_IDMABAR SDMMC_IDMABAR SDMMC IDMA linked list memory base register 0x68 32 read-write n 0x0 0x0 IDMABA IDMABA 2 30 SDMMC_IDMABASER SDMMC_IDMABASER The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE IDMABASE 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT IDMABNDT 5 12 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABMODE IDMABMODE 1 1 IDMAEN IDMAEN 0 1 SDMMC_IDMALAR SDMMC_IDMALAR SDMMC IDMA linked list address register 0x64 32 read-write n 0x0 0x0 ABR ABR 29 1 IDMALA IDMALA 2 14 ULA ULA 31 1 ULS ULS 30 1 SDMMC_IPIDR SDMMC_IPIDR SDMMC identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID IP_ID 0 32 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE ACKFAILIE 23 1 ACKTIMEOUTIE ACKTIMEOUTIE 24 1 BUSYD0ENDIE BUSYD0ENDIE 21 1 CCRCFAILIE CCRCFAILIE 0 1 CKSTOPIE CKSTOPIE 26 1 CMDRENDIE CMDRENDIE 6 1 CMDSENTIE CMDSENTIE 7 1 CTIMEOUTIE CTIMEOUTIE 2 1 DABORTIE DABORTIE 11 1 DATAENDIE DATAENDIE 8 1 DBCKENDIE DBCKENDIE 10 1 DCRCFAILIE DCRCFAILIE 1 1 DHOLDIE DHOLDIE 9 1 DTIMEOUTIE DTIMEOUTIE 3 1 IDMABTCIE IDMABTCIE 28 1 RXFIFOFIE RXFIFOFIE 17 1 RXFIFOHFIE RXFIFOHFIE 15 1 RXOVERRIE RXOVERRIE 5 1 SDIOITIE SDIOITIE 22 1 TXFIFOEIE TXFIFOEIE 18 1 TXFIFOHEIE TXFIFOHEIE 14 1 TXUNDERRIE TXUNDERRIE 4 1 VSWENDIE VSWENDIE 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL DIRPOL 4 1 PWRCTRL PWRCTRL 0 2 VSWITCH VSWITCH 2 1 VSWITCHEN VSWITCHEN 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 CARDSTATUS1 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 CARDSTATUS2 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 CARDSTATUS3 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 CARDSTATUS4 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 0x10 32 read-only n 0x0 0x0 RESPCMD RESPCMD 0 6 SDMMC_SIDR SDMMC_SIDR SDMMC size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL ACKFAIL 23 1 ACKTIMEOUT ACKTIMEOUT 24 1 BUSYD0 BUSYD0 20 1 BUSYD0END BUSYD0END 21 1 CCRCFAIL CCRCFAIL 0 1 CKSTOP CKSTOP 26 1 CMDREND CMDREND 6 1 CMDSENT CMDSENT 7 1 CPSMACT CPSMACT 13 1 CTIMEOUT CTIMEOUT 2 1 DABORT DABORT 11 1 DATAEND DATAEND 8 1 DBCKEND DBCKEND 10 1 DCRCFAIL DCRCFAIL 1 1 DHOLD DHOLD 9 1 DPSMACT DPSMACT 12 1 DTIMEOUT DTIMEOUT 3 1 IDMABTC IDMABTC 28 1 IDMATE IDMATE 27 1 RXFIFOE RXFIFOE 19 1 RXFIFOF RXFIFOF 17 1 RXFIFOHF RXFIFOHF 15 1 RXOVERR RXOVERR 5 1 SDIOIT SDIOIT 22 1 TXFIFOE TXFIFOE 18 1 TXFIFOF TXFIFOF 16 1 TXFIFOHE TXFIFOHE 14 1 TXUNDERR TXUNDERR 4 1 VSWEND VSWEND 25 1 SDMMC_VERR SDMMC_VERR SDMMC version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SDMMC2 SDMMC1 SDMMC2 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME ACKTIME 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG CMDARG 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED BUSSPEED 19 1 CLKDIV CLKDIV 0 10 DDR DDR 18 1 HWFC_EN HWFC_EN 17 1 NEGEDGE NEGEDGE 16 1 PWRSAV PWRSAV 12 1 SELCLKRX SELCLKRX 20 2 WIDBUS WIDBUS 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN BOOTEN 15 1 BOOTMODE BOOTMODE 14 1 CMDINDEX CMDINDEX 0 6 CMDSTOP CMDSTOP 7 1 CMDSUSPEND CMDSUSPEND 16 1 CMDTRANS CMDTRANS 6 1 CPSMEN CPSMEN 12 1 DTHOLD DTHOLD 13 1 WAITINT WAITINT 10 1 WAITPEND WAITPEND 11 1 WAITRESP WAITRESP 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT DATACOUNT 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN BOOTACKEN 12 1 DBLOCKSIZE DBLOCKSIZE 4 4 DTDIR DTDIR 1 1 DTEN DTEN 0 1 DTMODE DTMODE 2 2 FIFORST FIFORST 13 1 RWMOD RWMOD 10 1 RWSTART RWSTART 8 1 RWSTOP RWSTOP 9 1 SDIOEN SDIOEN 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH DATALENGTH 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME DATATIME 0 32 SDMMC_FIFOR0 SDMMC_FIFOR0 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR1 SDMMC_FIFOR1 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x84 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR10 SDMMC_FIFOR10 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR11 SDMMC_FIFOR11 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xAC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR12 SDMMC_FIFOR12 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR13 SDMMC_FIFOR13 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR14 SDMMC_FIFOR14 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR15 SDMMC_FIFOR15 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xBC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR2 SDMMC_FIFOR2 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x88 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR3 SDMMC_FIFOR3 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x8C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR4 SDMMC_FIFOR4 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x90 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR5 SDMMC_FIFOR5 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x94 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR6 SDMMC_FIFOR6 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x98 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR7 SDMMC_FIFOR7 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x9C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR8 SDMMC_FIFOR8 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR9 SDMMC_FIFOR9 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAILC 23 1 ACKTIMEOUTC ACKTIMEOUTC 24 1 BUSYD0ENDC BUSYD0ENDC 21 1 CCRCFAILC CCRCFAILC 0 1 CKSTOPC CKSTOPC 26 1 CMDRENDC CMDRENDC 6 1 CMDSENTC CMDSENTC 7 1 CTIMEOUTC CTIMEOUTC 2 1 DABORTC DABORTC 11 1 DATAENDC DATAENDC 8 1 DBCKENDC DBCKENDC 10 1 DCRCFAILC DCRCFAILC 1 1 DHOLDC DHOLDC 9 1 DTIMEOUTC DTIMEOUTC 3 1 IDMABTCC IDMABTCC 28 1 IDMATEC IDMATEC 27 1 RXOVERRC RXOVERRC 5 1 SDIOITC SDIOITC 22 1 TXUNDERRC TXUNDERRC 4 1 VSWENDC VSWENDC 25 1 SDMMC_IDMABAR SDMMC_IDMABAR SDMMC IDMA linked list memory base register 0x68 32 read-write n 0x0 0x0 IDMABA IDMABA 2 30 SDMMC_IDMABASER SDMMC_IDMABASER The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE IDMABASE 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT IDMABNDT 5 12 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABMODE IDMABMODE 1 1 IDMAEN IDMAEN 0 1 SDMMC_IDMALAR SDMMC_IDMALAR SDMMC IDMA linked list address register 0x64 32 read-write n 0x0 0x0 ABR ABR 29 1 IDMALA IDMALA 2 14 ULA ULA 31 1 ULS ULS 30 1 SDMMC_IPIDR SDMMC_IPIDR SDMMC identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID IP_ID 0 32 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE ACKFAILIE 23 1 ACKTIMEOUTIE ACKTIMEOUTIE 24 1 BUSYD0ENDIE BUSYD0ENDIE 21 1 CCRCFAILIE CCRCFAILIE 0 1 CKSTOPIE CKSTOPIE 26 1 CMDRENDIE CMDRENDIE 6 1 CMDSENTIE CMDSENTIE 7 1 CTIMEOUTIE CTIMEOUTIE 2 1 DABORTIE DABORTIE 11 1 DATAENDIE DATAENDIE 8 1 DBCKENDIE DBCKENDIE 10 1 DCRCFAILIE DCRCFAILIE 1 1 DHOLDIE DHOLDIE 9 1 DTIMEOUTIE DTIMEOUTIE 3 1 IDMABTCIE IDMABTCIE 28 1 RXFIFOFIE RXFIFOFIE 17 1 RXFIFOHFIE RXFIFOHFIE 15 1 RXOVERRIE RXOVERRIE 5 1 SDIOITIE SDIOITIE 22 1 TXFIFOEIE TXFIFOEIE 18 1 TXFIFOHEIE TXFIFOHEIE 14 1 TXUNDERRIE TXUNDERRIE 4 1 VSWENDIE VSWENDIE 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL DIRPOL 4 1 PWRCTRL PWRCTRL 0 2 VSWITCH VSWITCH 2 1 VSWITCHEN VSWITCHEN 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 CARDSTATUS1 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 CARDSTATUS2 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 CARDSTATUS3 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 CARDSTATUS4 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 0x10 32 read-only n 0x0 0x0 RESPCMD RESPCMD 0 6 SDMMC_SIDR SDMMC_SIDR SDMMC size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL ACKFAIL 23 1 ACKTIMEOUT ACKTIMEOUT 24 1 BUSYD0 BUSYD0 20 1 BUSYD0END BUSYD0END 21 1 CCRCFAIL CCRCFAIL 0 1 CKSTOP CKSTOP 26 1 CMDREND CMDREND 6 1 CMDSENT CMDSENT 7 1 CPSMACT CPSMACT 13 1 CTIMEOUT CTIMEOUT 2 1 DABORT DABORT 11 1 DATAEND DATAEND 8 1 DBCKEND DBCKEND 10 1 DCRCFAIL DCRCFAIL 1 1 DHOLD DHOLD 9 1 DPSMACT DPSMACT 12 1 DTIMEOUT DTIMEOUT 3 1 IDMABTC IDMABTC 28 1 IDMATE IDMATE 27 1 RXFIFOE RXFIFOE 19 1 RXFIFOF RXFIFOF 17 1 RXFIFOHF RXFIFOHF 15 1 RXOVERR RXOVERR 5 1 SDIOIT SDIOIT 22 1 TXFIFOE TXFIFOE 18 1 TXFIFOF TXFIFOF 16 1 TXFIFOHE TXFIFOHE 14 1 TXUNDERR TXUNDERR 4 1 VSWEND VSWEND 25 1 SDMMC_VERR SDMMC_VERR SDMMC version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SDMMC3 SDMMC1 SDMMC2 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME ACKTIME 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG CMDARG 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED BUSSPEED 19 1 CLKDIV CLKDIV 0 10 DDR DDR 18 1 HWFC_EN HWFC_EN 17 1 NEGEDGE NEGEDGE 16 1 PWRSAV PWRSAV 12 1 SELCLKRX SELCLKRX 20 2 WIDBUS WIDBUS 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN BOOTEN 15 1 BOOTMODE BOOTMODE 14 1 CMDINDEX CMDINDEX 0 6 CMDSTOP CMDSTOP 7 1 CMDSUSPEND CMDSUSPEND 16 1 CMDTRANS CMDTRANS 6 1 CPSMEN CPSMEN 12 1 DTHOLD DTHOLD 13 1 WAITINT WAITINT 10 1 WAITPEND WAITPEND 11 1 WAITRESP WAITRESP 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT DATACOUNT 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN BOOTACKEN 12 1 DBLOCKSIZE DBLOCKSIZE 4 4 DTDIR DTDIR 1 1 DTEN DTEN 0 1 DTMODE DTMODE 2 2 FIFORST FIFORST 13 1 RWMOD RWMOD 10 1 RWSTART RWSTART 8 1 RWSTOP RWSTOP 9 1 SDIOEN SDIOEN 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH DATALENGTH 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME DATATIME 0 32 SDMMC_FIFOR0 SDMMC_FIFOR0 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR1 SDMMC_FIFOR1 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x84 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR10 SDMMC_FIFOR10 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR11 SDMMC_FIFOR11 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xAC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR12 SDMMC_FIFOR12 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR13 SDMMC_FIFOR13 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR14 SDMMC_FIFOR14 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xB8 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR15 SDMMC_FIFOR15 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xBC 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR2 SDMMC_FIFOR2 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x88 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR3 SDMMC_FIFOR3 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x8C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR4 SDMMC_FIFOR4 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x90 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR5 SDMMC_FIFOR5 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x94 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR6 SDMMC_FIFOR6 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x98 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR7 SDMMC_FIFOR7 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x9C 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR8 SDMMC_FIFOR8 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA0 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_FIFOR9 SDMMC_FIFOR9 The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0xA4 32 read-write n 0x0 0x0 FIFODATA FIFODATA 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAILC 23 1 ACKTIMEOUTC ACKTIMEOUTC 24 1 BUSYD0ENDC BUSYD0ENDC 21 1 CCRCFAILC CCRCFAILC 0 1 CKSTOPC CKSTOPC 26 1 CMDRENDC CMDRENDC 6 1 CMDSENTC CMDSENTC 7 1 CTIMEOUTC CTIMEOUTC 2 1 DABORTC DABORTC 11 1 DATAENDC DATAENDC 8 1 DBCKENDC DBCKENDC 10 1 DCRCFAILC DCRCFAILC 1 1 DHOLDC DHOLDC 9 1 DTIMEOUTC DTIMEOUTC 3 1 IDMABTCC IDMABTCC 28 1 IDMATEC IDMATEC 27 1 RXOVERRC RXOVERRC 5 1 SDIOITC SDIOITC 22 1 TXUNDERRC TXUNDERRC 4 1 VSWENDC VSWENDC 25 1 SDMMC_IDMABAR SDMMC_IDMABAR SDMMC IDMA linked list memory base register 0x68 32 read-write n 0x0 0x0 IDMABA IDMABA 2 30 SDMMC_IDMABASER SDMMC_IDMABASER The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE IDMABASE 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT IDMABNDT 5 12 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABMODE IDMABMODE 1 1 IDMAEN IDMAEN 0 1 SDMMC_IDMALAR SDMMC_IDMALAR SDMMC IDMA linked list address register 0x64 32 read-write n 0x0 0x0 ABR ABR 29 1 IDMALA IDMALA 2 14 ULA ULA 31 1 ULS ULS 30 1 SDMMC_IPIDR SDMMC_IPIDR SDMMC identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID IP_ID 0 32 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE ACKFAILIE 23 1 ACKTIMEOUTIE ACKTIMEOUTIE 24 1 BUSYD0ENDIE BUSYD0ENDIE 21 1 CCRCFAILIE CCRCFAILIE 0 1 CKSTOPIE CKSTOPIE 26 1 CMDRENDIE CMDRENDIE 6 1 CMDSENTIE CMDSENTIE 7 1 CTIMEOUTIE CTIMEOUTIE 2 1 DABORTIE DABORTIE 11 1 DATAENDIE DATAENDIE 8 1 DBCKENDIE DBCKENDIE 10 1 DCRCFAILIE DCRCFAILIE 1 1 DHOLDIE DHOLDIE 9 1 DTIMEOUTIE DTIMEOUTIE 3 1 IDMABTCIE IDMABTCIE 28 1 RXFIFOFIE RXFIFOFIE 17 1 RXFIFOHFIE RXFIFOHFIE 15 1 RXOVERRIE RXOVERRIE 5 1 SDIOITIE SDIOITIE 22 1 TXFIFOEIE TXFIFOEIE 18 1 TXFIFOHEIE TXFIFOHEIE 14 1 TXUNDERRIE TXUNDERRIE 4 1 VSWENDIE VSWENDIE 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL DIRPOL 4 1 PWRCTRL PWRCTRL 0 2 VSWITCH VSWITCH 2 1 VSWITCHEN VSWITCHEN 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 CARDSTATUS1 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 CARDSTATUS2 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 CARDSTATUS3 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 CARDSTATUS4 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response). 0x10 32 read-only n 0x0 0x0 RESPCMD RESPCMD 0 6 SDMMC_SIDR SDMMC_SIDR SDMMC size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL ACKFAIL 23 1 ACKTIMEOUT ACKTIMEOUT 24 1 BUSYD0 BUSYD0 20 1 BUSYD0END BUSYD0END 21 1 CCRCFAIL CCRCFAIL 0 1 CKSTOP CKSTOP 26 1 CMDREND CMDREND 6 1 CMDSENT CMDSENT 7 1 CPSMACT CPSMACT 13 1 CTIMEOUT CTIMEOUT 2 1 DABORT DABORT 11 1 DATAEND DATAEND 8 1 DBCKEND DBCKEND 10 1 DCRCFAIL DCRCFAIL 1 1 DHOLD DHOLD 9 1 DPSMACT DPSMACT 12 1 DTIMEOUT DTIMEOUT 3 1 IDMABTC IDMABTC 28 1 IDMATE IDMATE 27 1 RXFIFOE RXFIFOE 19 1 RXFIFOF RXFIFOF 17 1 RXFIFOHF RXFIFOHF 15 1 RXOVERR RXOVERR 5 1 SDIOIT SDIOIT 22 1 TXFIFOE TXFIFOE 18 1 TXFIFOF TXFIFOF 16 1 TXFIFOHE TXFIFOHE 14 1 TXUNDERR TXUNDERR 4 1 VSWEND VSWEND 25 1 SDMMC_VERR SDMMC_VERR SDMMC version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPDIFRX SPDIFRX SPDIFRX 0x0 0x0 0x400 registers n CR SPDIFRX_CR Control register 0x0 32 read-write n 0x0 0x0 CBDMAEN CBDMAEN 10 1 read-write CHSEL CHSEL 11 1 read-write CKSBKPEN CKSBKPEN 21 1 read-write CKSEN CKSEN 20 1 read-write CUMSK CUMSK 8 1 read-write DRFMT DRFMT 4 2 read-write INSEL INSEL 16 3 read-write NBTR NBTR 12 2 read-write PMSK PMSK 6 1 read-write PTMSK PTMSK 9 1 read-write RXDMAEN RXDMAEN 2 1 read-write RXSTEO RXSTEO 3 1 read-write SPDIFRXEN SPDIFRXEN 0 2 read-write VMSK VMSK 7 1 read-write WFA WFA 14 1 read-write CSR SPDIFRX_CSR Channel status register 0x14 32 read-only n 0x0 0x0 CS CS 16 8 read-only SOB SOB 24 1 read-only USR USR 0 16 read-only DIR SPDIFRX_DIR Debug information register 0x18 32 read-only n 0x0 0x0 THI THI 0 13 read-only TLO TLO 16 13 read-only FMT0_DR SPDIFRX_FMT0_DR This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00: 0x10 32 read-only n 0x0 0x0 C C 27 1 read-only DR DR 0 24 read-only PE PE 24 1 read-only PT PT 28 2 read-only U U 26 1 read-only V V 25 1 read-only IFCR SPDIFRX_IFCR Interrupt flag clear register 0xC 32 read-write n 0x0 0x0 OVRCF OVRCF 3 1 write-only PERRCF PERRCF 2 1 write-only SBDCF SBDCF 4 1 write-only SYNCDCF SYNCDCF 5 1 write-only IMR SPDIFRX_IMR Interrupt mask register 0x4 32 read-write n 0x0 0x0 CSRNEIE CSRNEIE 1 1 read-write IFEIE IFEIE 6 1 read-write OVRIE OVRIE 3 1 read-write PERRIE PERRIE 2 1 read-write RXNEIE RXNEIE 0 1 read-write SBLKIE SBLKIE 4 1 read-write SYNCDIE SYNCDIE 5 1 read-write IPIDR SPDIFRX_IPIDR SPDIFRX identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only SIDR SPDIFRX_SIDR SPDIFRX size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SR SPDIFRX_SR Status register 0x8 32 read-only n 0x0 0x0 CSRNE CSRNE 1 1 read-only FERR FERR 6 1 read-only OVR OVR 3 1 read-only PERR PERR 2 1 read-only RXNE RXNE 0 1 read-only SBD SBD 4 1 read-only SERR SERR 7 1 read-only SYNCD SYNCD 5 1 read-only TERR TERR 8 1 read-only WIDTH5 WIDTH5 16 15 read-only VERR SPDIFRX_VERR SPDIFRX version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only SPI1 SPI1 SPI1 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPI2 SPI2 SPI2 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPI3 SPI2 SPI2 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPI4 SPI2 SPI2 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPI5 SPI2 SPI2 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SPI6 SPI2 SPI2 0x0 0x0 0x400 registers n SPI2S_CR1 SPI2S_CR1 SPI/I2S control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 read-write CSTART CSTART 9 1 read-write CSUSP CSUSP 10 1 write-only HDDIR HDDIR 11 1 read-write IOLOCK IOLOCK 16 1 read-write MASRX MASRX 8 1 read-write RCRCINI RCRCINI 14 1 read-write SPE SPE 0 1 read-write SSI SSI 12 1 read-write TCRCINI TCRCINI 15 1 read-write SPI2S_IER SPI2S_IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 SPI2S_IFCR SPI2S_IFCR SPI/I2S interrupt/status flags clear register 0x18 32 write-only n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 SPI2S_RXDR SPI2S_RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SPI2S_SR SPI2S_SR SPI/I2S status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 SPI2S_TXDR SPI2S_TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 SPI_CFG1 SPI_CFG1 Content of this register is write protected when SPI is enabled 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 SPI_CFG2 SPI_CFG2 The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register. 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 SPI_CR2 SPI_CR2 SPI control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 SPI_CRCPOLY SPI_CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 SPI_I2SCFGR SPI_I2SCFGR All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode. 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 SPI_I2S_HWCFGR SPI_I2S_HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 SPI_IPIDR SPI_IPIDR SPI/I2S identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SPI_RXCRC SPI_RXCRC SPI receiver CRC register 0x48 32 read-only n 0x0 0x0 RXCRC RXCRC 0 32 SPI_SIDR SPI_SIDR SPI/I2S size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SPI_TXCRC SPI_TXCRC SPI transmitter CRC register 0x44 32 read-only n 0x0 0x0 TXCRC TXCRC 0 32 SPI_UDRDR SPI_UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 SPI_VERR SPI_VERR SPI/I2S version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 STGENC STGENC STGENC 0x0 0x0 0x1000 registers n CIDR0 STGENC_CIDR0 STGENC component ID0 register 0xFF0 32 read-only n 0x0 0x0 PRMBL_0 PRMBL_0 0 8 CIDR1 STGENC_CIDR1 STGENC component ID1 register 0xFF4 32 read-only n 0x0 0x0 CLASS CLASS 4 4 PRMBL_1 PRMBL_1 0 4 CIDR2 STGENC_CIDR2 STGENC component ID2 register 0xFF8 32 read-only n 0x0 0x0 PRMBL_2 PRMBL_2 0 8 CIDR3 STGENC_CIDR3 STGENC component ID3 register 0xFFC 32 read-only n 0x0 0x0 PRMBL_3 PRMBL_3 0 8 CNTCR STGENC_CNTCR STGENC control register 0x0 32 read-write n 0x0 0x0 EN EN 0 1 HLTDBG HLTDBG 1 1 CNTCVL STGENC_CNTCVL the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0x8 32 read-write n 0x0 0x0 CNTCVL_L_32 CNTCVL_L_32 0 32 CNTCVU STGENC_CNTCVU the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0xC 32 read-write n 0x0 0x0 CNTCVU_U_32 CNTCVU_U_32 0 32 CNTFID0 STGENC_CNTFID0 the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x20 32 read-write n 0x0 0x0 FREQ FREQ 0 32 CNTSR STGENC_CNTSR STGENC status register 0x4 32 read-only n 0x0 0x0 EN EN 0 1 HLTDBG HLTDBG 1 1 PIDR0 STGENC_PIDR0 STGENC peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PART_0 PART_0 0 8 PIDR1 STGENC_PIDR1 STGENC peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 DES_0 DES_0 4 4 PART_1 PART_1 0 4 PIDR2 STGENC_PIDR2 STGENC peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 DES_1 DES_1 0 3 JEDEC JEDEC 3 1 REVISION REVISION 4 4 PIDR3 STGENC_PIDR3 STGENC peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 CMOD CMOD 0 4 REVAND REVAND 4 4 PIDR4 STGENC_PIDR4 STGENC peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 DES_2 DES_2 0 4 SIZE SIZE 4 4 PIDR5 STGENC_PIDR5 STGENC peripheral ID5 register 0xFD4 32 read-only n 0x0 0x0 PIDR5 PIDR5 0 32 PIDR6 STGENC_PIDR6 STGENC peripheral ID6 register 0xFD8 32 read-only n 0x0 0x0 PIDR6 PIDR6 0 32 PIDR7 STGENC_PIDR7 STGENC peripheral ID7 register 0xFDC 32 read-only n 0x0 0x0 PIDR7 PIDR7 0 32 STGENR STGENR STGENR 0x0 0x0 0x1000 registers n CIDR0 STGENR_CIDR0 STGENR component ID0 register 0xFF0 32 read-only n 0x0 0x0 PRMBL_0 PRMBL_0 0 8 CIDR1 STGENR_CIDR1 STGENR component ID1 register 0xFF4 32 read-only n 0x0 0x0 CLASS CLASS 4 4 PRMBL_1 PRMBL_1 0 4 CIDR2 STGENR_CIDR2 STGENR component ID2 register 0xFF8 32 read-only n 0x0 0x0 PRMBL_2 PRMBL_2 0 8 CIDR3 STGENR_CIDR3 STGENR component ID3 register 0xFFC 32 read-only n 0x0 0x0 PRMBL_3 PRMBL_3 0 8 CNTCVL STGENR_CNTCVL the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x0 32 read-only n 0x0 0x0 CNTCVL_L_32 CNTCVL_L_32 0 32 CNTCVU STGENR_CNTCVU the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x4 32 read-only n 0x0 0x0 CNTCVU_U_32 CNTCVU_U_32 0 32 PIDR0 STGENR_PIDR0 STGENR peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PART_0 PART_0 0 8 PIDR1 STGENR_PIDR1 STGENR peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 DES_0 DES_0 4 4 PART_1 PART_1 0 4 PIDR2 STGENR_PIDR2 STGENR peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 DES_1 DES_1 0 3 JEDEC JEDEC 3 1 REVISION REVISION 4 4 PIDR3 STGENR_PIDR3 STGENR peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 CMOD CMOD 0 4 REVAND REVAND 4 4 PIDR4 STGENR_PIDR4 STGENR peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 DES_2 DES_2 0 4 SIZE SIZE 4 4 PIDR5 STGENR_PIDR5 STGENR peripheral ID5 register 0xFD4 32 read-only n 0x0 0x0 PIDR5 PIDR5 0 32 PIDR6 STGENR_PIDR6 STGENR peripheral ID6 register 0xFD8 32 read-only n 0x0 0x0 PIDR6 PIDR6 0 32 PIDR7 STGENR_PIDR7 STGENR peripheral ID7 register 0xFDC 32 read-only n 0x0 0x0 PIDR7 PIDR7 0 32 SYSCFG SYSCFG SYSCFG 0x0 0x0 0x400 registers n BOOTR SYSCFG_BOOTR This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. ) 0x0 32 read-write n 0x0 0x0 BOOT0 BOOT0 0 1 read-only BOOT0_PD BOOT0_PD 4 1 read-write BOOT1 BOOT1 1 1 read-only BOOT1_PD BOOT1_PD 5 1 read-write BOOT2 BOOT2 2 1 read-only BOOT2_PD BOOT2_PD 6 1 read-write CBR SYSCFG_CBR SYSCFG control timer break register 0x2C 32 read-write n 0x0 0x0 CLL CLL 0 1 PVDL PVDL 2 1 CMPCR SYSCFG_CMPCR SYSCFG compensation cell control register 0x20 32 read-write n 0x0 0x0 ANSRC ANSRC 24 4 read-only APSRC APSRC 28 4 read-only RANSRC RANSRC 16 4 read-write RAPSRC RAPSRC 20 4 read-write READY READY 8 1 read-only SW_CTRL SW_CTRL 1 1 read-write CMPENCLRR SYSCFG_CMPENCLRR SYSCFG compensation cell enable set register 0x28 32 read-write n 0x0 0x0 MCU_EN MCU_EN 1 1 MPU_EN MPU_EN 0 1 CMPENSETR SYSCFG_CMPENSETR SYSCFG compensation cell enable set register 0x24 32 read-write n 0x0 0x0 MCU_EN MCU_EN 1 1 MPU_EN MPU_EN 0 1 ICNR SYSCFG_ICNR SYSCFG interconnect control register 0x1C 32 read-write n 0x0 0x0 AXI_M0 AXI_M0 0 1 AXI_M1 AXI_M1 1 1 AXI_M10 AXI_M10 10 1 AXI_M2 AXI_M2 2 1 AXI_M3 AXI_M3 3 1 AXI_M5 AXI_M5 5 1 AXI_M6 AXI_M6 6 1 AXI_M7 AXI_M7 7 1 AXI_M8 AXI_M8 8 1 AXI_M9 AXI_M9 9 1 IOCTRLCLRR SYSCFG_IOCTRLCLRR SYSCFG IO control register 0x58 32 read-write n 0x0 0x0 HSLVEN_ETH HSLVEN_ETH 2 1 HSLVEN_QUADSPI HSLVEN_QUADSPI 1 1 HSLVEN_SDMMC HSLVEN_SDMMC 3 1 HSLVEN_SPI HSLVEN_SPI 4 1 HSLVEN_TRACE HSLVEN_TRACE 0 1 IOCTRLSETR SYSCFG_IOCTRLSETR SYSCFG IO control register 0x18 32 read-write n 0x0 0x0 HSLVEN_ETH HSLVEN_ETH 2 1 HSLVEN_QUADSPI HSLVEN_QUADSPI 1 1 HSLVEN_SDMMC HSLVEN_SDMMC 3 1 HSLVEN_SPI HSLVEN_SPI 4 1 HSLVEN_TRACE HSLVEN_TRACE 0 1 IPIDR SYSCFG_IPIDR SYSCFG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 PMCCLRR SYSCFG_PMCCLRR SYSCFG peripheral mode configuration clear register 0x44 32 read-write n 0x0 0x0 ANA0_SEL ANA0_SEL 24 1 ANA1_SEL ANA1_SEL 25 1 ANASWVDD ANASWVDD 9 1 EN_BOOSTER EN_BOOSTER 8 1 ETH_CLK_SEL ETH_CLK_SEL 16 1 ETH_REF_CLK_SEL ETH_REF_CLK_SEL 17 1 ETH_SEL ETH_SEL 21 3 ETH_SELMII ETH_SELMII 20 1 I2C1_FMP I2C1_FMP 0 1 I2C2_FMP I2C2_FMP 1 1 I2C3_FMP I2C3_FMP 2 1 I2C4_FMP I2C4_FMP 3 1 I2C5_FMP I2C5_FMP 4 1 I2C6_FMP I2C6_FMP 5 1 PMCSETR SYSCFG_PMCSETR SYSCFG peripheral mode configuration set register 0x4 32 read-write n 0x0 0x0 ANA0_SEL ANA0_SEL 24 1 ANA1_SEL ANA1_SEL 25 1 ANASWVDD ANASWVDD 9 1 EN_BOOSTER EN_BOOSTER 8 1 ETH_CLK_SEL ETH_CLK_SEL 16 1 ETH_REF_CLK_SEL ETH_REF_CLK_SEL 17 1 ETH_SEL ETH_SEL 21 3 ETH_SELMII ETH_SELMII 20 1 I2C1_FMP I2C1_FMP 0 1 I2C2_FMP I2C2_FMP 1 1 I2C3_FMP I2C3_FMP 2 1 I2C4_FMP I2C4_FMP 3 1 I2C5_FMP I2C5_FMP 4 1 I2C6_FMP I2C6_FMP 5 1 SIDR SYSCFG_SIDR SYSCFG size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR SYSCFG_VERR SYSCFG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 TAMP TAMP TAMP 0x0 0x0 0x400 registers n TAMP Tamper interrupt (include LSECSS interrupts) 2 TAMP_S TAMP tamper secure interrupt 197 ATCR1 TAMP_ATCR1 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x10 32 read-write n 0x0 0x0 ATCKSEL ATCKSEL 16 3 ATOSEL1 ATOSEL1 8 2 ATOSEL2 ATOSEL2 10 2 ATOSEL3 ATOSEL3 12 2 ATOSHARE ATOSHARE 30 1 ATPER ATPER 24 3 FLTEN FLTEN 31 1 TAMP1AM TAMP1AM 0 1 TAMP2AM TAMP2AM 1 1 TAMP3AM TAMP3AM 2 1 ATOR TAMP_ATOR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x18 32 read-only n 0x0 0x0 INITS INITS 15 1 PRNG PRNG 0 8 SEEDF SEEDF 14 1 ATSEEDR TAMP_ATSEEDR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x14 32 write-only n 0x0 0x0 SEED SEED 0 32 BKP0R TAMP_BKP0R TAMP backup 0 register 0x100 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP10R TAMP_BKP10R TAMP backup 10 register 0x128 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP11R TAMP_BKP11R TAMP backup 11 register 0x12C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP12R TAMP_BKP12R TAMP backup 12 register 0x130 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP13R TAMP_BKP13R TAMP backup 13 register 0x134 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP14R TAMP_BKP14R TAMP backup 14 register 0x138 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP15R TAMP_BKP15R TAMP backup 15 register 0x13C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP16R TAMP_BKP16R TAMP backup 16 register 0x140 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP17R TAMP_BKP17R TAMP backup 17 register 0x144 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP18R TAMP_BKP18R TAMP backup 18 register 0x148 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP19R TAMP_BKP19R TAMP backup 19 register 0x14C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP1R TAMP_BKP1R TAMP backup 1 register 0x104 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP20R TAMP_BKP20R TAMP backup 20 register 0x150 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP21R TAMP_BKP21R TAMP backup 21 register 0x154 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP22R TAMP_BKP22R TAMP backup 22 register 0x158 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP23R TAMP_BKP23R TAMP backup 23 register 0x15C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP24R TAMP_BKP24R TAMP backup 24 register 0x160 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP25R TAMP_BKP25R TAMP backup 25 register 0x164 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP26R TAMP_BKP26R TAMP backup 26 register 0x168 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP27R TAMP_BKP27R TAMP backup 27 register 0x16C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP28R TAMP_BKP28R TAMP backup 28 register 0x170 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP29R TAMP_BKP29R TAMP backup 29 register 0x174 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP2R TAMP_BKP2R TAMP backup 2 register 0x108 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP30R TAMP_BKP30R TAMP backup 30 register 0x178 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP31R TAMP_BKP31R TAMP backup 31 register 0x17C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP3R TAMP_BKP3R TAMP backup 3 register 0x10C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP4R TAMP_BKP4R TAMP backup 4 register 0x110 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP5R TAMP_BKP5R TAMP backup 5 register 0x114 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP6R TAMP_BKP6R TAMP backup 6 register 0x118 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP7R TAMP_BKP7R TAMP backup 7 register 0x11C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP8R TAMP_BKP8R TAMP backup 8 register 0x120 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP9R TAMP_BKP9R TAMP backup 9 register 0x124 32 read-write n 0x0 0x0 BKP BKP 0 32 CFGR TAMP_CFGR TAMP configuration register 0x50 32 read-write n 0x0 0x0 OUT3_RMP OUT3_RMP 0 1 COUNTR TAMP_COUNTR TAMP monotonic counter register 0x40 32 read-only n 0x0 0x0 COUNT COUNT 0 32 CR1 TAMP_CR1 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x0 32 read-write n 0x0 0x0 ITAMP1E ITAMP1E 16 1 ITAMP2E ITAMP2E 17 1 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP8E ITAMP8E 23 1 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP3E 2 1 CR2 TAMP_CR2 This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x4 32 read-write n 0x0 0x0 TAMP1MSK TAMP1MSK 16 1 TAMP1NOER TAMP1NOER 0 1 TAMP1TRG TAMP1TRG 24 1 TAMP2MSK TAMP2MSK 17 1 TAMP2NOER TAMP2NOER 1 1 TAMP2TRG TAMP2TRG 25 1 TAMP3MSK TAMP3MSK 18 1 TAMP3NOER TAMP3NOER 2 1 TAMP3TRG TAMP3TRG 26 1 FLTCR TAMP_FLTCR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0xC 32 read-write n 0x0 0x0 TAMPFLT TAMPFLT 3 2 TAMPFREQ TAMPFREQ 0 3 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 HWCFGR1 TAMP_HWCFGR1 TAMP hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 ACTIVE_TAMPER ACTIVE_TAMPER 12 4 BACKUP_REGS BACKUP_REGS 0 8 INT_TAMPER INT_TAMPER 16 16 TAMPER TAMPER 8 4 HWCFGR2 TAMP_HWCFGR2 TAMP hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 OPTIONREG_OUT OPTIONREG_OUT 0 8 TRUST_ZONE TRUST_ZONE 8 4 IER TAMP_IER This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x2C 32 read-write n 0x0 0x0 ITAMP1IE ITAMP1IE 16 1 ITAMP2IE ITAMP2IE 17 1 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP8IE ITAMP8IE 23 1 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 IPIDR TAMP_IPIDR TAMP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 MISR TAMP_MISR TAMP non-secure masked interrupt status register 0x34 32 read-only n 0x0 0x0 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 SCR TAMP_SCR TAMP status clear register 0x3C 32 write-only n 0x0 0x0 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP8F CITAMP8F 23 1 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 SIDR TAMP_SIDR TAMP size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SMCR TAMP_SMCR This register can be written only when the APB access is secure. 0x20 32 read-write n 0x0 0x0 BKPRWDPROT BKPRWDPROT 0 8 BKPWDPROT BKPWDPROT 16 8 TAMPDPROT TAMPDPROT 31 1 SMISR TAMP_SMISR TAMP secure masked interrupt status register 0x38 32 read-only n 0x0 0x0 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP8MF ITAMP8MF 23 1 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 SR TAMP_SR This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes. 0x30 32 read-only n 0x0 0x0 ITAMP1F ITAMP1F 16 1 ITAMP2F ITAMP2F 17 1 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP8F ITAMP8F 23 1 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 VERR TAMP_VERR TAMP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 TIM1 TIM1 TIM1 0x0 0x0 0x400 registers n AF1 TIM1_AF1 TIM1 alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK0E BKDF1BK0E 8 1 BKINE BKINE 0 1 BKINP BKINP 9 1 ETRSEL ETRSEL 14 4 AF2 TIM1_AF2 TIM1 Alternate function register 2 0x64 32 read-write n 0x0 0x0 BK2DF1BK1E BK2DF1BK1E 8 1 BK2INE BK2INE 0 1 BK2INP BK2INP 9 1 ARR TIM1_ARR TIM1 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM1_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM1_CCER TIM1 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE1 TIM1_CCMR1ALTERNATE1 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE17 TIM1_CCMR2ALTERNATE17 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM1_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM1_CCR1 TIM1 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM1_CCR2 TIM1 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM1_CCR3 TIM1 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM1_CCR4 TIM1 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM1_CCR5 TIM1 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM1_CCR6 TIM1 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM1_CNT TIM1 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM1_CR1 TIM1 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM1_CR2 TIM1 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM1_DCR TIM1 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM1_DIER TIM1 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM1_DMAR TIM1 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM1_EGR TIM1 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM1_PSC TIM1 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM1_RCR TIM1 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM1_SMCR TIM1 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM1_SR TIM1 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TISEL TIM1_TISEL TIM1 timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TIM13 TIM13 TIM13 0x0 0x0 0x400 registers n ARR TIM13_ARR TIM13 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 CCER TIM13_CCER TIM13 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CCMR1 TIM13_CCMR1 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1M OC1M 4 3 OC1M3 OC1M3 16 1 OC1PE OC1PE 3 1 CCR1 TIM13_CCR1 TIM13 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CNT TIM13_CNT TIM13 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 UIFCPY UIFCPY 31 1 CR1 TIM13_CR1 TIM13 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 DIER TIM13_DIER TIM13 Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1IE CC1IE 1 1 UIE UIE 0 1 EGR TIM13_EGR TIM13 event generation register 0x14 16 write-only n 0x0 0x0 CC1G CC1G 1 1 UG UG 0 1 PSC TIM13_PSC TIM13 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 SR TIM13_SR TIM13 status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 UIF UIF 0 1 TISEL TIM13_TISEL TIM13 timer input selection register 0x68 16 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TIM14 TIM14 TIM14 0x0 0x0 0x400 registers n ARR TIM14_ARR TIM14 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 CCER TIM14_CCER TIM14 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CCMR1 TIM14_CCMR1 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 OC1FE OC1FE 2 1 OC1M OC1M 4 3 OC1M3 OC1M3 16 1 OC1PE OC1PE 3 1 CCR1 TIM14_CCR1 TIM14 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CNT TIM14_CNT TIM14 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 UIFCPY UIFCPY 31 1 CR1 TIM14_CR1 TIM14 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 DIER TIM14_DIER TIM14 Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1IE CC1IE 1 1 UIE UIE 0 1 EGR TIM14_EGR TIM14 event generation register 0x14 16 write-only n 0x0 0x0 CC1G CC1G 1 1 UG UG 0 1 PSC TIM14_PSC TIM14 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 SR TIM14_SR TIM14 status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 UIF UIF 0 1 TISEL TIM14_TISEL TIM14 timer input selection register 0x68 16 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TIM15 TIM15 TIMER 0x0 0x0 0x400 registers n AF1 TIM15_AF1 TIM15 alternate register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK0E BKDF1BK0E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write ARR TIM15_ARR TIM15 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write CCER TIM15_CCER TIM15 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CCR1 TIM15_CCR1 TIM15 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write CCR2 TIM15_CCR2 TIM15 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 read-write CNT TIM15_CNT TIM15 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM15_CR1 TIM15 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write CR2 TIM15_CR2 TIM15 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write MMS MMS 4 3 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write OIS2 OIS2 10 1 read-write TI1S TI1S 7 1 read-write DCR TIM15_DCR TIM15 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write DIER TIM15_DIER TIM15 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write DMAR TIM15_DMAR TIM15 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write PSC TIM15_PSC TIM15 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write RCR TIM15_RCR TIM15 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write SR TIM15_SR TIM15 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write COMIF COMIF 5 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_BDTR TIMx_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 BG BG 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 COMG COMG 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TISEL TIM15_TISEL TIM15 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TIM16 TIM16 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIM17_AF1 TIM17 alternate function register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK2E BKDF1BK2E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write TIMx_ARR TIMx_ARR TIM16/TIM17 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER TIM16/TIM17 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCR1 TIMx_CCR1 TIM16/TIM17 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIM16/TIM17 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM16/TIM17 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM16/TIM17 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write TIMx_DCR TIMx_DCR TIM16/TIM17 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM16/TIM17 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIM16/TIM17 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIM16/TIM17 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM16/TIM17 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write TIMx_SR TIMx_SR TIM16/TIM17 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write COMIF COMIF 5 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIM17_TISEL TIM17 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM17 TIM16 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIM17_AF1 TIM17 alternate function register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK2E BKDF1BK2E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write TIMx_ARR TIMx_ARR TIM16/TIM17 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER TIM16/TIM17 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCR1 TIMx_CCR1 TIM16/TIM17 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIM16/TIM17 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM16/TIM17 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM16/TIM17 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write TIMx_DCR TIMx_DCR TIM16/TIM17 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM16/TIM17 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIM16/TIM17 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIM16/TIM17 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM16/TIM17 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write TIMx_SR TIMx_SR TIM16/TIM17 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write COMIF COMIF 5 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIM17_TISEL TIM17 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM2 TIM2 TIM2 0x0 0x0 0x400 registers n ARR TIM2_ARR TIM2 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM2_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM2_CCER TIM2 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE2 TIM2_CCMR1ALTERNATE2 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE18 TIM2_CCMR2ALTERNATE18 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM2_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM2_CCR1 TIM2 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM2_CCR2 TIM2 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM2_CCR3 TIM2 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM2_CCR4 TIM2 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM2_CCR5 TIM2 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM2_CCR6 TIM2 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM2_CNT TIM2 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM2_CR1 TIM2 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM2_CR2 TIM2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM2_DCR TIM2 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM2_DIER TIM2 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM2_DMAR TIM2 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM2_EGR TIM2 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM2_PSC TIM2 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM2_RCR TIM2 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM2_SMCR TIM2 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM2_SR TIM2 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM3 TIM3 TIM3 0x0 0x0 0x400 registers n ARR TIM3_ARR TIM3 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM3_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM3_CCER TIM3 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE3 TIM3_CCMR1ALTERNATE3 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE19 TIM3_CCMR2ALTERNATE19 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM3_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM3_CCR1 TIM3 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM3_CCR2 TIM3 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM3_CCR3 TIM3 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM3_CCR4 TIM3 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM3_CCR5 TIM3 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM3_CCR6 TIM3 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM3_CNT TIM3 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM3_CR1 TIM3 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM3_CR2 TIM3 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM3_DCR TIM3 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM3_DIER TIM3 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM3_DMAR TIM3 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM3_EGR TIM3 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM3_PSC TIM3 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM3_RCR TIM3 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM3_SMCR TIM3 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM3_SR TIM3 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM4 TIM4 TIM4 0x0 0x0 0x400 registers n ARR TIM4_ARR TIM4 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM4_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM4_CCER TIM4 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE4 TIM4_CCMR1ALTERNATE4 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE20 TIM4_CCMR2ALTERNATE20 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM4_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM4_CCR1 TIM4 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM4_CCR2 TIM4 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM4_CCR3 TIM4 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM4_CCR4 TIM4 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM4_CCR5 TIM4 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM4_CCR6 TIM4 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM4_CNT TIM4 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM4_CR1 TIM4 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM4_CR2 TIM4 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM4_DCR TIM4 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM4_DIER TIM4 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM4_DMAR TIM4 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM4_EGR TIM4 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM4_PSC TIM4 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM4_RCR TIM4 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM4_SMCR TIM4 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM4_SR TIM4 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM5 TIM5 TIM5 0x0 0x0 0x400 registers n ARR TIM5_ARR TIM5 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM5_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM5_CCER TIM5 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE5 TIM5_CCMR1ALTERNATE5 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE21 TIM5_CCMR2ALTERNATE21 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM5_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM5_CCR1 TIM5 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM5_CCR2 TIM5 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM5_CCR3 TIM5 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM5_CCR4 TIM5 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM5_CCR5 TIM5 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM5_CCR6 TIM5 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM5_CNT TIM5 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM5_CR1 TIM5 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM5_CR2 TIM5 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM5_DCR TIM5 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM5_DIER TIM5 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM5_DMAR TIM5 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM5_EGR TIM5 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM5_PSC TIM5 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM5_RCR TIM5 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM5_SMCR TIM5 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM5_SR TIM5 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM6 TIM6 TIM6 0x0 0x0 0x400 registers n ARR TIM6_ARR TIM6 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM6_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM6_CCER TIM6 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE6 TIM6_CCMR1ALTERNATE6 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE22 TIM6_CCMR2ALTERNATE22 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM6_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM6_CCR1 TIM6 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM6_CCR2 TIM6 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM6_CCR3 TIM6 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM6_CCR4 TIM6 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM6_CCR5 TIM6 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM6_CCR6 TIM6 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM6_CNT TIM6 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM6_CR1 TIM6 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM6_CR2 TIM6 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM6_DCR TIM6 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM6_DIER TIM6 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM6_DMAR TIM6 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM6_EGR TIM6 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM6_PSC TIM6 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM6_RCR TIM6 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM6_SMCR TIM6 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM6_SR TIM6 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM7 TIM7 TIM7 0x0 0x0 0x400 registers n ARR TIM7_ARR TIM7 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM7_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM7_CCER TIM7 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE7 TIM7_CCMR1ALTERNATE7 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE23 TIM7_CCMR2ALTERNATE23 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM7_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM7_CCR1 TIM7 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM7_CCR2 TIM7 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM7_CCR3 TIM7 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM7_CCR4 TIM7 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM7_CCR5 TIM7 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM7_CCR6 TIM7 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM7_CNT TIM7 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM7_CR1 TIM7 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM7_CR2 TIM7 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM7_DCR TIM7 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM7_DIER TIM7 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM7_DMAR TIM7 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM7_EGR TIM7 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM7_PSC TIM7 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM7_RCR TIM7 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM7_SMCR TIM7 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM7_SR TIM7 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TIM8 TIM8 TIM8 0x0 0x0 0x400 registers n AF1 TIM8_AF1 TIM8 Alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK2E BKDF1BK2E 8 1 BKINE BKINE 0 1 BKINP BKINP 9 1 ETRSEL ETRSEL 14 4 AF2 TIM8_AF2 TIM8 Alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2DF1BK3E BK2DF1BK3E 8 1 BK2INE BK2INE 0 1 BK2INP BK2INP 9 1 ARR TIM8_ARR TIM8 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 BDTR TIM8_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 BK2BID BK2BID 29 1 BK2DSRM BK2DSRM 27 1 BK2E BK2E 24 1 BK2F BK2F 20 4 BK2P BK2P 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE BKE 12 1 BKF BKF 16 4 BKP BKP 13 1 DTG DTG 0 8 LOCK LOCK 8 2 MOE MOE 15 1 OSSI OSSI 10 1 OSSR OSSR 11 1 CCER TIM8_CCER TIM8 capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1NE CC1NE 2 1 CC1NP CC1NP 3 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2NE CC2NE 6 1 CC2NP CC2NP 7 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3NE CC3NE 10 1 CC3NP CC3NP 11 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4NP CC4NP 15 1 CC4P CC4P 13 1 CC5E CC5E 16 1 CC5P CC5P 17 1 CC6E CC6E 20 1 CC6P CC6P 21 1 CCMR1ALTERNATE8 TIM8_CCMR1ALTERNATE8 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x18 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR2ALTERNATE24 TIM8_CCMR2ALTERNATE24 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode: 0x1C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR3 TIM8_CCMR3 The channels 5 and 6 can only be configured in output. Output compare mode: 0x54 32 read-write n 0x0 0x0 OC5CE OC5CE 7 1 OC5FE OC5FE 2 1 OC5M OC5M 4 3 OC5M3 OC5M3 16 1 OC5PE OC5PE 3 1 OC6CE OC6CE 15 1 OC6FE OC6FE 10 1 OC6M OC6M 12 3 OC6M3 OC6M3 24 1 OC6PE OC6PE 11 1 CCR1 TIM8_CCR1 TIM8 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 CCR2 TIM8_CCR2 TIM8 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 CCR3 TIM8_CCR3 TIM8 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 CCR4 TIM8_CCR4 TIM8 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 CCR5 TIM8_CCR5 TIM8 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 TIM8_CCR6 TIM8 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 CNT TIM8_CNT TIM8 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM8_CR1 TIM8 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 CEN CEN 0 1 CKD CKD 8 2 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 UIFREMAP UIFREMAP 11 1 URS URS 2 1 CR2 TIM8_CR2 TIM8 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 CCPC CCPC 0 1 CCUS CCUS 2 1 MMS MMS 4 3 MMS2 MMS2 20 4 OIS1 OIS1 8 1 OIS1N OIS1N 9 1 OIS2 OIS2 10 1 OIS2N OIS2N 11 1 OIS3 OIS3 12 1 OIS3N OIS3N 13 1 OIS4 OIS4 14 1 OIS5 OIS5 16 1 OIS6 OIS6 18 1 TI1S TI1S 7 1 DCR TIM8_DCR TIM8 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 DBL DBL 8 5 DIER TIM8_DIER TIM8 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 CC1DE CC1DE 9 1 CC1IE CC1IE 1 1 CC2DE CC2DE 10 1 CC2IE CC2IE 2 1 CC3DE CC3DE 11 1 CC3IE CC3IE 3 1 CC4DE CC4DE 12 1 CC4IE CC4IE 4 1 COMDE COMDE 13 1 COMIE COMIE 5 1 TDE TDE 14 1 TIE TIE 6 1 UDE UDE 8 1 UIE UIE 0 1 DMAR TIM8_DMAR TIM8 DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMAB 0 32 EGR TIM8_EGR TIM8 event generation register 0x14 16 write-only n 0x0 0x0 B2G B2G 8 1 BG BG 7 1 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 COMG COMG 5 1 TG TG 6 1 UG UG 0 1 PSC TIM8_PSC TIM8 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 RCR TIM8_RCR TIM8 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 SMCR TIM8_SMCR TIM8 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 SMS3 SMS3 16 1 TS TS 4 3 TS3 TS3 20 1 TS4 TS4 21 1 SR TIM8_SR TIM8 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 BIF BIF 7 1 CC1IF CC1IF 1 1 CC1OF CC1OF 9 1 CC2IF CC2IF 2 1 CC2OF CC2OF 10 1 CC3IF CC3IF 3 1 CC3OF CC3OF 11 1 CC4IF CC4IF 4 1 CC4OF CC4OF 12 1 CC5IF CC5IF 16 1 CC6IF CC6IF 17 1 COMIF COMIF 5 1 SBIF SBIF 13 1 TIF TIF 6 1 UIF UIF 0 1 TISEL TIM8_TISEL TIM8 timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TZC TZC TZC 0x0 0x0 0x1000 registers n TZC_IT TrustZone DDR address space controller 4 ACTION TZC_ACTION Controls interrupt and bus error response behavior when regions permission failures occur. 0x4 32 read-write n 0x0 0x0 REACTION_VALUE REACTION_VALUE 0 2 read-write BUILD_CONFIG TZC_BUILD_CONFIG Provides information about TZC configuration. 0x0 32 read-only n 0x0 0x0 ADDRESS_WIDTH ADDRESS_WIDTH 8 6 read-only NO_OF_FILTERS NO_OF_FILTERS 24 2 read-only NO_OF_REGIONS NO_OF_REGIONS 0 5 read-only CID0 TZC_CID0 Component ID 0. 0xFF0 32 read-only n 0x0 0x0 COMP_ID_0 COMP_ID_0 0 8 read-only CID1 TZC_CID1 Component ID 1. 0xFF4 32 read-only n 0x0 0x0 COMP_ID_1 COMP_ID_1 0 8 read-only CID2 TZC_CID2 Component ID 2. 0xFF8 32 read-only n 0x0 0x0 COMP_ID_2 COMP_ID_2 0 8 read-only CID3 TZC_CID3 Component ID 3. 0xFFC 32 read-only n 0x0 0x0 COMP_ID_3 COMP_ID_3 0 8 read-only FAIL_ADDRESS_HIGH0 TZC_FAIL_ADDRESS_HIGH0 Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address. 0x24 32 read-only n 0x0 0x0 FAIL_ADDRESS_HIGH1 TZC_FAIL_ADDRESS_HIGH1 Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address. 0x34 32 read-only n 0x0 0x0 FAIL_ADDRESS_LOW0 TZC_FAIL_ADDRESS_LOW0 Address low bits of the first failed access in the associated filter (0 to 1). 0x20 32 read-only n 0x0 0x0 ADDR_STATUS_LOW ADDR_STATUS_LOW 0 32 read-only FAIL_ADDRESS_LOW1 TZC_FAIL_ADDRESS_LOW1 Address low bits of the first failed access in the associated filter (0 to 1). 0x30 32 read-only n 0x0 0x0 ADDR_STATUS_LOW ADDR_STATUS_LOW 0 32 read-only FAIL_CONTROL0 TZC_FAIL_CONTROL0 Status information about the first access that failed a region permission check in the associated filter (0 to 1). 0x28 32 read-only n 0x0 0x0 DIRECTION DIRECTION 24 1 read-only NON_SECURE NON_SECURE 21 1 read-only PRIVILEGE PRIVILEGE 20 1 read-only FAIL_CONTROL1 TZC_FAIL_CONTROL1 Status information about the first access that failed a region permission check in the associated filter (0 to 1). 0x38 32 read-only n 0x0 0x0 DIRECTION DIRECTION 24 1 read-only NON_SECURE NON_SECURE 21 1 read-only PRIVILEGE PRIVILEGE 20 1 read-only FAIL_ID0 TZC_FAIL_ID0 Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD). 0x2C 32 read-only n 0x0 0x0 ID ID 0 11 read-only FAIL_ID1 TZC_FAIL_ID1 Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD). 0x3C 32 read-only n 0x0 0x0 ID ID 0 11 read-only GATE_KEEPER TZC_GATE_KEEPER Provides control and status for the gate keeper in each filter unit implemented. 0x8 32 read-write n 0x0 0x0 OPENREQ OPENREQ 0 2 read-write OPENSTAT OPENSTAT 16 2 read-only INT_CLEAR TZC_INT_CLEAR Interrupt clear for each filter. 0x14 32 read-write n 0x0 0x0 CLEAR CLEAR 0 2 write-only INT_STATUS TZC_INT_STATUS Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. 0x10 32 read-only n 0x0 0x0 OVERLAP OVERLAP 16 2 read-only OVERRUN OVERRUN 8 2 read-only STATUS STATUS 0 2 read-only PID0 TZC_PID0 Peripheral ID 0. 0xFE0 32 read-only n 0x0 0x0 PER_ID_0 PER_ID_0 0 8 read-only PID1 TZC_PID1 Peripheral ID 1. 0xFE4 32 read-only n 0x0 0x0 PER_ID_1 PER_ID_1 0 8 read-only PID2 TZC_PID2 Peripheral ID 2. 0xFE8 32 read-only n 0x0 0x0 PER_ID_2 PER_ID_2 0 8 read-only PID3 TZC_PID3 Peripheral ID 3. 0xFEC 32 read-only n 0x0 0x0 PER_ID_3 PER_ID_3 0 8 read-only PID4 TZC_PID4 Peripheral ID 4. 0xFD0 32 read-only n 0x0 0x0 PER_ID_4 PER_ID_4 0 8 read-only PID5 TZC_PID5 Peripheral ID 5. 0xFD4 32 read-only n 0x0 0x0 PER_ID_5 PER_ID_5 0 8 read-only PID6 TZC_PID6 Peripheral ID 6. 0xFD8 32 read-only n 0x0 0x0 PER_ID_6 PER_ID_6 0 8 read-only PID7 TZC_PID7 Peripheral ID 7. 0xFDC 32 read-only n 0x0 0x0 PER_ID_7 PER_ID_7 0 8 read-only REGION_ATTRIBUTE0 TZC_REGION_ATTRIBUTE0 Region 0 attributes. 0x110 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-only S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE1 TZC_REGION_ATTRIBUTE1 Region x attributes. 0x130 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE2 TZC_REGION_ATTRIBUTE2 Region x attributes. 0x150 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE3 TZC_REGION_ATTRIBUTE3 Region x attributes. 0x170 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE4 TZC_REGION_ATTRIBUTE4 Region x attributes. 0x190 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE5 TZC_REGION_ATTRIBUTE5 Region x attributes. 0x1B0 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE6 TZC_REGION_ATTRIBUTE6 Region x attributes. 0x1D0 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE7 TZC_REGION_ATTRIBUTE7 Region x attributes. 0x1F0 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_ATTRIBUTE8 TZC_REGION_ATTRIBUTE8 Region x attributes. 0x210 32 read-write n 0x0 0x0 FILTER_EN FILTER_EN 0 2 read-write S_RD_EN S_RD_EN 30 1 read-write S_WR_EN S_WR_EN 31 1 read-write REGION_BASE_HIGH0 TZC_REGION_BASE_HIGH0 Base address high are not used with 32-bit address. 0x104 32 read-only n 0x0 0x0 REGION_BASE_HIGH1 TZC_REGION_BASE_HIGH1 Base address high are not used with 32-bit address. 0x124 32 read-only n 0x0 0x0 REGION_BASE_HIGH2 TZC_REGION_BASE_HIGH2 Base address high are not used with 32-bit address. 0x144 32 read-only n 0x0 0x0 REGION_BASE_HIGH3 TZC_REGION_BASE_HIGH3 Base address high are not used with 32-bit address. 0x164 32 read-only n 0x0 0x0 REGION_BASE_HIGH4 TZC_REGION_BASE_HIGH4 Base address high are not used with 32-bit address. 0x184 32 read-only n 0x0 0x0 REGION_BASE_HIGH5 TZC_REGION_BASE_HIGH5 Base address high are not used with 32-bit address. 0x1A4 32 read-only n 0x0 0x0 REGION_BASE_HIGH6 TZC_REGION_BASE_HIGH6 Base address high are not used with 32-bit address. 0x1C4 32 read-only n 0x0 0x0 REGION_BASE_HIGH7 TZC_REGION_BASE_HIGH7 Base address high are not used with 32-bit address. 0x2E4 32 read-only n 0x0 0x0 REGION_BASE_HIGH8 TZC_REGION_BASE_HIGH8 Base address high are not used with 32-bit address. 0x204 32 read-only n 0x0 0x0 REGION_BASE_LOW1 TZC_REGION_BASE_LOW1 Base address low for regions 1 to 8. 0x120 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW2 TZC_REGION_BASE_LOW2 Base address low for regions 1 to 8. 0x140 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW3 TZC_REGION_BASE_LOW3 Base address low for regions 1 to 8. 0x160 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW4 TZC_REGION_BASE_LOW4 Base address low for regions 1 to 8. 0x180 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW5 TZC_REGION_BASE_LOW5 Base address low for regions 1 to 8. 0x1A0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW6 TZC_REGION_BASE_LOW6 Base address low for regions 1 to 8. 0x1C0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW7 TZC_REGION_BASE_LOW7 Base address low for regions 1 to 8. 0x2E0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_BASE_LOW8 TZC_REGION_BASE_LOW8 Base address low for regions 1 to 8. 0x200 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW BASE_ADDRESS_LOW 12 20 read-write REGION_ID_ACCESS0 TZC_REGION_ID_ACCESS0 Region non-secure access based on NSAID. 0x114 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS1 TZC_REGION_ID_ACCESS1 Region non-secure access based on NSAID. 0x134 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS2 TZC_REGION_ID_ACCESS2 Region non-secure access based on NSAID. 0x154 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS3 TZC_REGION_ID_ACCESS3 Region non-secure access based on NSAID. 0x174 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS4 TZC_REGION_ID_ACCESS4 Region non-secure access based on NSAID. 0x194 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS5 TZC_REGION_ID_ACCESS5 Region non-secure access based on NSAID. 0x1B4 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS6 TZC_REGION_ID_ACCESS6 Region non-secure access based on NSAID. 0x1D4 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS7 TZC_REGION_ID_ACCESS7 Region non-secure access based on NSAID. 0x2F4 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_ID_ACCESS8 TZC_REGION_ID_ACCESS8 Region non-secure access based on NSAID. 0x314 32 read-write n 0x0 0x0 NSAID_RD_EN NSAID_RD_EN 0 16 read-write NSAID_WR_EN NSAID_WR_EN 16 16 read-write REGION_TOP_HIGH0 TZC_REGION_TOP_HIGH0 Top address high of region are not used with 32-bit address. 0x10C 32 read-only n 0x0 0x0 REGION_TOP_HIGH1 TZC_REGION_TOP_HIGH1 Top address high of region are not used with 32-bit address. 0x12C 32 read-only n 0x0 0x0 REGION_TOP_HIGH2 TZC_REGION_TOP_HIGH2 Top address high of region are not used with 32-bit address. 0x14C 32 read-only n 0x0 0x0 REGION_TOP_HIGH3 TZC_REGION_TOP_HIGH3 Top address high of region are not used with 32-bit address. 0x16C 32 read-only n 0x0 0x0 REGION_TOP_HIGH4 TZC_REGION_TOP_HIGH4 Top address high of region are not used with 32-bit address. 0x18C 32 read-only n 0x0 0x0 REGION_TOP_HIGH5 TZC_REGION_TOP_HIGH5 Top address high of region are not used with 32-bit address. 0x1AC 32 read-only n 0x0 0x0 REGION_TOP_HIGH6 TZC_REGION_TOP_HIGH6 Top address high of region are not used with 32-bit address. 0x1CC 32 read-only n 0x0 0x0 REGION_TOP_HIGH7 TZC_REGION_TOP_HIGH7 Top address high of region are not used with 32-bit address. 0x2EC 32 read-only n 0x0 0x0 REGION_TOP_HIGH8 TZC_REGION_TOP_HIGH8 Top address high of region are not used with 32-bit address. 0x30C 32 read-only n 0x0 0x0 REGION_TOP_LOW0 TZC_REGION_TOP_LOW0 Top address bits [31:12] for region 0. 0x108 32 read-only n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-only REGION_TOP_LOW1 TZC_REGION_TOP_LOW1 Top address bits [31:12] for region x. 0x128 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW2 TZC_REGION_TOP_LOW2 Top address bits [31:12] for region x. 0x148 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW3 TZC_REGION_TOP_LOW3 Top address bits [31:12] for region x. 0x168 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW4 TZC_REGION_TOP_LOW4 Top address bits [31:12] for region x. 0x188 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW5 TZC_REGION_TOP_LOW5 Top address bits [31:12] for region x. 0x1A8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW6 TZC_REGION_TOP_LOW6 Top address bits [31:12] for region x. 0x1C8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW7 TZC_REGION_TOP_LOW7 Top address bits [31:12] for region x. 0x1E8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write REGION_TOP_LOW8 TZC_REGION_TOP_LOW8 Top address bits [31:12] for region x. 0x308 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW TOP_ADDRESS_LOW 12 20 read-write SPECULATION_CTRL TZC_SPECULATION_CTRL Controls read and write access speculation. 0xC 32 read-write n 0x0 0x0 READSPEC_DISABLE READSPEC_DISABLE 0 1 read-write WRITESPEC_DISABLE WRITESPEC_DISABLE 1 1 read-write UART4 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART5 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART7 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART8 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART3 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART6 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USBPHYC USBPHYC USBPHYC 0x0 0x0 0x1000 registers n MISC USBPHYC_MISC This register is used to control the switch between controllers for the HS PHY. 0x8 32 read-write n 0x0 0x0 PPCKDIS PPCKDIS 1 2 SWITHOST SWITHOST 0 1 PLL USBPHYC_PLL This register is used to control the PLL of the HS PHY. 0x0 32 read-write n 0x0 0x0 PLLDITHEN0 PLLDITHEN0 30 1 PLLDITHEN1 PLLDITHEN1 31 1 PLLEN PLLEN 26 1 PLLFRACCTL PLLFRACCTL 29 1 PLLFRACIN PLLFRACIN 10 16 PLLNDIV PLLNDIV 0 7 PLLODF PLLODF 7 3 PLLSTRB PLLSTRB 27 1 PLLSTRBYP PLLSTRBYP 28 1 TUNE1 USBPHYC_TUNE1 This register is used to control the tune interface of the HS PHY, port #x. 0x10C 32 read-write n 0x0 0x0 FSDRVRFADJ FSDRVRFADJ 7 1 HDRXGNEQEN HDRXGNEQEN 22 1 HSDRVCHKITRM HSDRVCHKITRM 9 4 HSDRVCHKZTRM HSDRVCHKZTRM 13 2 HSDRVCURINCR HSDRVCURINCR 6 1 HSDRVDCCUR HSDRVDCCUR 4 1 HSDRVDCLEV HSDRVDCLEV 5 1 HSDRVRFRED HSDRVRFRED 8 1 HSDRVSLEW HSDRVSLEW 3 1 HSFALLPREEM HSFALLPREEM 25 1 HSRXOFF HSRXOFF 23 2 INCURREN INCURREN 0 1 INCURRINT INCURRINT 1 1 LFSCAPEN LFSCAPEN 2 1 OTPCOMP OTPCOMP 15 5 SHTCCTCTLPROT SHTCCTCTLPROT 26 1 SQLCHCTL SQLCHCTL 20 2 STAGSEL STAGSEL 27 1 TUNE2 USBPHYC_TUNE2 This register is used to control the tune interface of the HS PHY, port #x. 0x20C 32 read-write n 0x0 0x0 FSDRVRFADJ FSDRVRFADJ 7 1 HDRXGNEQEN HDRXGNEQEN 22 1 HSDRVCHKITRM HSDRVCHKITRM 9 4 HSDRVCHKZTRM HSDRVCHKZTRM 13 2 HSDRVCURINCR HSDRVCURINCR 6 1 HSDRVDCCUR HSDRVDCCUR 4 1 HSDRVDCLEV HSDRVDCLEV 5 1 HSDRVRFRED HSDRVRFRED 8 1 HSDRVSLEW HSDRVSLEW 3 1 HSFALLPREEM HSFALLPREEM 25 1 HSRXOFF HSRXOFF 23 2 INCURREN INCURREN 0 1 INCURRINT INCURRINT 1 1 LFSCAPEN LFSCAPEN 2 1 OTPCOMP OTPCOMP 15 5 SHTCCTCTLPROT SHTCCTCTLPROT 26 1 SQLCHCTL SQLCHCTL 20 2 STAGSEL STAGSEL 27 1 VERR USBPHYC_VERR This register defines the version of this IP. 0xFFC 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 VREFBUF VREFBUF VREFBUF 0x0 0x0 0x400 registers n CCR VREFBUF_CCR VREFBUF calibration control register 0x4 32 read-write n 0x0 0x0 TRIM TRIM 0 6 CSR VREFBUF_CSR VREFBUF control and status register 0x0 32 read-write n 0x0 0x0 ENVR ENVR 0 1 read-write HIZ HIZ 1 1 read-write VRR VRR 3 1 read-only VRS VRS 4 3 read-write WWDG1 WWDG1 WWDG1 0x0 0x0 0x400 registers n WWDG1_IT Window Watchdog interrupt 0 WWDG_CFR WWDG_CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI EWI 9 1 read-write W W 0 7 read-write WDGTB WDGTB 11 3 read-write WWDG_CR WWDG_CR Control register 0x0 32 read-write n 0x0 0x0 T T 0 7 read-write WDGA WDGA 7 1 read-write WWDG_HWCFGR WWDG_HWCFGR WWDG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 PREDIV PREDIV 0 16 read-only WWDG_IPIDR WWDG_IPIDR WWDG ID register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only WWDG_SIDR WWDG_SIDR WWDG size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only WWDG_SR WWDG_SR Status register 0x8 32 read-write n 0x0 0x0 EWIF EWIF 0 1 read-write WWDG_VERR WWDG_VERR WWDG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only