STMicroelectronics STM32MP1_v0r3 2024.04.30 STM32MP1_v0r3 8 32 ADC1 Analog to Digital Converter ADC 0x0 0x0 0xD1 registers n ADC_AWD2CR ADC_AWD2CR ADC analog watchdog 2 configuration register 0xA0 32 read-write n 0x0 0x0 AWD2CH ADC analog watchdog 2 monitored channel selection 0 20 ADC_AWD3CR ADC_AWD3CR ADC analog watchdog 3 configuration register 0xA4 32 read-write n 0x0 0x0 AWD3CH ADC analog watchdog 3 monitored channel selection 1 20 ADC_CALFACT ADC_CALFACT ADC calibration factors register 0xC4 32 read-write n 0x0 0x0 CALFACT_D ADC calibration factor in differential mode 16 11 CALFACT_S ADC calibration factor in single-ended mode 0 11 ADC_CALFACT2 ADC_CALFACT2 ADC Calibration Factor register 2 0xC8 32 read-write n 0x0 0x0 LINCALFACT Linearity Calibration Factor 0 30 ADC_CFGR ADC_CFGR ADC configuration register 1 0xC 32 read-write n 0x0 0x0 AUTDLY ADC low power auto wait 14 1 AWD1EN ADC analog watchdog 1 enable on scope ADC group regular 23 1 AWD1SGL ADC analog watchdog 1 monitoring a single channel or all channels 22 1 AWDCH1CH ADC analog watchdog 1 monitored channel selection 26 5 CONT ADC group regular continuous conversion mode 13 1 DISCEN ADC group regular sequencer discontinuous mode 16 1 DISCNUM ADC group regular sequencer discontinuous number of ranks 17 3 DMNGT ADC DMA transfer enable 0 2 EXTEN ADC group regular external trigger polarity 10 2 EXTSEL ADC group regular external trigger source 5 5 JAUTO ADC group injected automatic trigger mode 25 1 JAWD1EN ADC analog watchdog 1 enable on scope ADC group injected 24 1 JDISCEN ADC group injected sequencer discontinuous mode 20 1 JQDIS ADC group injected contexts queue disable 31 1 JQM ADC group injected contexts queue mode 21 1 OVRMOD ADC group regular overrun configuration 12 1 RES ADC data resolution 2 3 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 32 read-write n 0x0 0x0 JOVSE ADC oversampler enable on scope ADC group injected 1 1 LSHIFT Left shift factor 28 4 OSR Oversampling ratio 16 10 OVSS ADC oversampling shift 5 4 ROVSE ADC oversampler enable on scope ADC group regular 0 1 ROVSM Regular Oversampling mode 10 1 RSHIFT1 Right-shift data after Offset 1 correction 11 1 RSHIFT2 Right-shift data after Offset 2 correction 12 1 RSHIFT3 Right-shift data after Offset 3 correction 13 1 RSHIFT4 Right-shift data after Offset 4 correction 14 1 TROVS ADC oversampling discontinuous mode (triggered mode) for ADC group regular 9 1 ADC_CR ADC_CR ADC control register 0x8 32 read-write n 0x0 0x0 ADCAL ADC calibration 31 1 ADCALDIF ADC differential mode for calibration 30 1 ADCALLIN Linearity calibration 16 1 ADDIS ADC disable 1 1 ADEN ADC enable 0 1 ADSTART ADC group regular conversion start 2 1 ADSTP ADC group regular conversion stop 4 1 ADVREGEN ADC voltage regulator enable 28 1 BOOST Boost mode control 8 1 DEEPPWD ADC deep power down enable 29 1 JADSTART ADC group injected conversion start 3 1 JADSTP ADC group injected conversion stop 5 1 LINCALRDYW1 Linearity calibration ready Word 1 22 1 LINCALRDYW2 Linearity calibration ready Word 2 23 1 LINCALRDYW3 Linearity calibration ready Word 3 24 1 LINCALRDYW4 Linearity calibration ready Word 4 25 1 LINCALRDYW5 Linearity calibration ready Word 5 26 1 LINCALRDYW6 Linearity calibration ready Word 6 27 1 ADC_DIFSEL ADC_DIFSEL ADC channel differential or single-ended mode selection register 0xC0 32 read-write n 0x0 0x0 DIFSEL ADC channel differential or single-ended mode for channel 0 20 ADC_DR ADC_DR ADC group regular conversion data register 0x40 32 read-only n 0x0 0x0 RDATA ADC group regular conversion data 0 32 ADC_HTR2 ADC_HTR2 ADC watchdog higher threshold register 2 0xB4 32 read-write n 0x0 0x0 HTR2 Analog watchdog 2 higher threshold 0 26 ADC_HTR3 ADC_HTR3 ADC watchdog higher threshold register 3 0xBC 32 read-write n 0x0 0x0 HTR3 Analog watchdog 3 higher threshold 0 26 ADC_IER ADC_IER ADC interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADC ready interrupt 0 1 AWD1IE ADC analog watchdog 1 interrupt 7 1 AWD2IE ADC analog watchdog 2 interrupt 8 1 AWD3IE ADC analog watchdog 3 interrupt 9 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOSIE ADC group regular end of sequence conversions interrupt 3 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 JEOCIE ADC group injected end of unitary conversion interrupt 5 1 JEOSIE ADC group injected end of sequence conversions interrupt 6 1 JQOVFIE ADC group injected contexts queue overflow interrupt 10 1 OVRIE ADC group regular overrun interrupt 4 1 ADC_ISR ADC_ISR ADC interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADC ready flag 0 1 AWD1 ADC analog watchdog 1 flag 7 1 AWD2 ADC analog watchdog 2 flag 8 1 AWD3 ADC analog watchdog 3 flag 9 1 EOC ADC group regular end of unitary conversion flag 2 1 EOS ADC group regular end of sequence conversions flag 3 1 EOSMP ADC group regular end of sampling flag 1 1 JEOC ADC group injected end of unitary conversion flag 5 1 JEOS ADC group injected end of sequence conversions flag 6 1 JQOVF ADC group injected contexts queue overflow flag 10 1 OVR ADC group regular overrun flag 4 1 ADC_JDR1 ADC_JDR1 ADC group injected sequencer rank 1 register 0x80 32 read-only n 0x0 0x0 JDATA1 ADC group injected sequencer rank 1 conversion data 0 32 ADC_JDR2 ADC_JDR2 ADC group injected sequencer rank 2 register 0x84 32 read-only n 0x0 0x0 JDATA2 ADC group injected sequencer rank 2 conversion data 0 32 ADC_JDR3 ADC_JDR3 ADC group injected sequencer rank 3 register 0x88 32 read-only n 0x0 0x0 JDATA3 ADC group injected sequencer rank 3 conversion data 0 32 ADC_JDR4 ADC_JDR4 ADC group injected sequencer rank 4 register 0x8C 32 read-only n 0x0 0x0 JDATA4 ADC group injected sequencer rank 4 conversion data 0 32 ADC_JSQR ADC_JSQR ADC group injected sequencer register 0x4C 32 read-write n 0x0 0x0 JEXTEN ADC group injected external trigger polarity 7 2 JEXTSEL ADC group injected external trigger source 2 5 JL ADC group injected sequencer scan length 0 2 JSQ1 ADC group injected sequencer rank 1 9 5 JSQ2 ADC group injected sequencer rank 2 15 5 JSQ3 ADC group injected sequencer rank 3 21 5 JSQ4 ADC group injected sequencer rank 4 27 5 ADC_LHTR1 ADC_LHTR1 ADC analog watchdog 2 threshold register 0x24 32 read-write n 0x0 0x0 LHTR1 ADC analog watchdog 2 threshold low 0 26 ADC_LTR1 ADC_LTR1 ADC analog watchdog 1 threshold register 0x20 32 read-write n 0x0 0x0 LTR1 ADC analog watchdog 1 threshold low 0 26 ADC_LTR2 ADC_LTR2 ADC watchdog lower threshold register 2 0xB0 32 read-write n 0x0 0x0 LTR2 Analog watchdog 2 lower threshold 0 26 ADC_LTR3 ADC_LTR3 ADC watchdog lower threshold register 3 0xB8 32 read-write n 0x0 0x0 LTR3 Analog watchdog 3 lower threshold 0 26 ADC_OFR1 ADC_OFR1 ADC offset number 1 register 0x60 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR2 ADC_OFR2 ADC offset number 2 register 0x64 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR3 ADC_OFR3 ADC offset number 3 register 0x68 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR4 ADC_OFR4 ADC offset number 4 register 0x6C 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_PCSEL ADC_PCSEL ADC channel preselection register 0x1C 32 read-write n 0x0 0x0 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 ADC_SMPR1 ADC_SMPR1 ADC sampling time register 1 0x14 32 read-write n 0x0 0x0 SMP0 ADC channel 0 sampling time selection 0 3 SMP1 ADC channel 1 sampling time selection 3 3 SMP2 ADC channel 2 sampling time selection 6 3 SMP3 ADC channel 3 sampling time selection 9 3 SMP4 ADC channel 4 sampling time selection 12 3 SMP5 ADC channel 5 sampling time selection 15 3 SMP6 ADC channel 6 sampling time selection 18 3 SMP7 ADC channel 7 sampling time selection 21 3 SMP8 ADC channel 8 sampling time selection 24 3 SMP9 ADC channel 9 sampling time selection 27 3 ADC_SMPR2 ADC_SMPR2 ADC sampling time register 2 0x18 32 read-write n 0x0 0x0 SMP10 ADC channel 10 sampling time selection 0 3 SMP11 ADC channel 11 sampling time selection 3 3 SMP12 ADC channel 12 sampling time selection 6 3 SMP13 ADC channel 13 sampling time selection 9 3 SMP14 ADC channel 14 sampling time selection 12 3 SMP15 ADC channel 15 sampling time selection 15 3 SMP16 ADC channel 16 sampling time selection 18 3 SMP17 ADC channel 17 sampling time selection 21 3 SMP18 ADC channel 18 sampling time selection 24 3 SMP19 ADC channel 18 sampling time selection 27 3 ADC_SQR1 ADC_SQR1 ADC group regular sequencer ranks register 1 0x30 32 read-write n 0x0 0x0 L3 L3 0 4 SQ1 ADC group regular sequencer rank 1 6 5 SQ2 ADC group regular sequencer rank 2 12 5 SQ3 ADC group regular sequencer rank 3 18 5 SQ4 ADC group regular sequencer rank 4 24 5 ADC_SQR2 ADC_SQR2 ADC group regular sequencer ranks register 2 0x34 32 read-write n 0x0 0x0 SQ5 ADC group regular sequencer rank 5 0 5 SQ6 ADC group regular sequencer rank 6 6 5 SQ7 ADC group regular sequencer rank 7 12 5 SQ8 ADC group regular sequencer rank 8 18 5 SQ9 ADC group regular sequencer rank 9 24 5 ADC_SQR3 ADC_SQR3 ADC group regular sequencer ranks register 3 0x38 32 read-write n 0x0 0x0 SQ10 ADC group regular sequencer rank 10 0 5 SQ11 ADC group regular sequencer rank 11 6 5 SQ12 ADC group regular sequencer rank 12 12 5 SQ13 ADC group regular sequencer rank 13 18 5 SQ14 ADC group regular sequencer rank 14 24 5 ADC_SQR4 ADC_SQR4 ADC group regular sequencer ranks register 4 0x3C 32 read-write n 0x0 0x0 SQ15 ADC group regular sequencer rank 15 0 5 SQ16 ADC group regular sequencer rank 16 6 5 ADC12_Common Analog-to-Digital Converter ADC 0x0 0x0 0x14 registers n CCR CCR ADC common control register 0x8 32 read-write n 0x0 0x0 CKMODE ADC clock mode 16 2 DAMDF Dual ADC Mode Data Format 14 2 DELAY Delay between 2 sampling phases 8 4 DUAL Dual ADC mode selection 0 5 PRESC ADC prescaler 18 4 TSEN Temperature sensor enable 23 1 VBATEN VBAT enable 24 1 VREFEN VREFINT enable 22 1 CDR CDR ADC common regular data register for dual and triple modes 0xC 32 read-only n 0x0 0x0 RDATA_MST Regular data of the master ADC 0 16 RDATA_SLV Regular data of the slave ADC 16 16 CDR2 CDR2 ADC common regular data register for dual and triple modes 0x10 32 read-only n 0x0 0x0 RDATA_ALT RDATA_ALT 0 32 CSR CSR ADC Common status register 0x0 32 read-only n 0x0 0x0 ADRDY_MST Master ADC ready 0 1 ADRDY_SLV Slave ADC ready 16 1 AWD1_MST Analog watchdog 1 flag of the master ADC 7 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_MST Analog watchdog 2 flag of the master ADC 8 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_MST Analog watchdog 3 flag of the master ADC 9 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 EOC_MST End of regular conversion of the master ADC 2 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOSMP_MST End of Sampling phase flag of the master ADC 1 1 EOSMP_SLV End of Sampling phase flag of the slave ADC 17 1 EOS_MST End of regular sequence flag of the master ADC 3 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 JEOC_MST End of injected conversion flag of the master ADC 5 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_MST End of injected sequence flag of the master ADC 6 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 JQOVF_MST Injected Context Queue Overflow flag of the master ADC 10 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 OVR_MST Overrun flag of the master ADC 4 1 OVR_SLV Overrun flag of the slave ADC 20 1 ADC2 Analog to Digital Converter ADC 0x0 0x0 0xD4 registers n ADC_AWD2CR ADC_AWD2CR ADC analog watchdog 2 configuration register 0xA0 32 read-write n 0x0 0x0 AWD2CH ADC analog watchdog 2 monitored channel selection 0 20 ADC_AWD3CR ADC_AWD3CR ADC analog watchdog 3 configuration register 0xA4 32 read-write n 0x0 0x0 AWD3CH ADC analog watchdog 3 monitored channel selection 1 20 ADC_CALFACT ADC_CALFACT ADC calibration factors register 0xC4 32 read-write n 0x0 0x0 CALFACT_D ADC calibration factor in differential mode 16 11 CALFACT_S ADC calibration factor in single-ended mode 0 11 ADC_CALFACT2 ADC_CALFACT2 ADC Calibration Factor register 2 0xC8 32 read-write n 0x0 0x0 LINCALFACT Linearity Calibration Factor 0 30 ADC_CFGR ADC_CFGR ADC configuration register 1 0xC 32 read-write n 0x0 0x0 AUTDLY ADC low power auto wait 14 1 AWD1EN ADC analog watchdog 1 enable on scope ADC group regular 23 1 AWD1SGL ADC analog watchdog 1 monitoring a single channel or all channels 22 1 AWDCH1CH ADC analog watchdog 1 monitored channel selection 26 5 CONT ADC group regular continuous conversion mode 13 1 DISCEN ADC group regular sequencer discontinuous mode 16 1 DISCNUM ADC group regular sequencer discontinuous number of ranks 17 3 DMNGT ADC DMA transfer enable 0 2 EXTEN ADC group regular external trigger polarity 10 2 EXTSEL ADC group regular external trigger source 5 5 JAUTO ADC group injected automatic trigger mode 25 1 JAWD1EN ADC analog watchdog 1 enable on scope ADC group injected 24 1 JDISCEN ADC group injected sequencer discontinuous mode 20 1 JQDIS ADC group injected contexts queue disable 31 1 JQM ADC group injected contexts queue mode 21 1 OVRMOD ADC group regular overrun configuration 12 1 RES ADC data resolution 2 3 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 32 read-write n 0x0 0x0 JOVSE ADC oversampler enable on scope ADC group injected 1 1 LSHIFT Left shift factor 28 4 OSR Oversampling ratio 16 10 OVSS ADC oversampling shift 5 4 ROVSE ADC oversampler enable on scope ADC group regular 0 1 ROVSM Regular Oversampling mode 10 1 RSHIFT1 Right-shift data after Offset 1 correction 11 1 RSHIFT2 Right-shift data after Offset 2 correction 12 1 RSHIFT3 Right-shift data after Offset 3 correction 13 1 RSHIFT4 Right-shift data after Offset 4 correction 14 1 TROVS ADC oversampling discontinuous mode (triggered mode) for ADC group regular 9 1 ADC_CR ADC_CR ADC control register 0x8 32 read-write n 0x0 0x0 ADCAL ADC calibration 31 1 ADCALDIF ADC differential mode for calibration 30 1 ADCALLIN Linearity calibration 16 1 ADDIS ADC disable 1 1 ADEN ADC enable 0 1 ADSTART ADC group regular conversion start 2 1 ADSTP ADC group regular conversion stop 4 1 ADVREGEN ADC voltage regulator enable 28 1 BOOST Boost mode control 8 1 DEEPPWD ADC deep power down enable 29 1 JADSTART ADC group injected conversion start 3 1 JADSTP ADC group injected conversion stop 5 1 LINCALRDYW1 Linearity calibration ready Word 1 22 1 LINCALRDYW2 Linearity calibration ready Word 2 23 1 LINCALRDYW3 Linearity calibration ready Word 3 24 1 LINCALRDYW4 Linearity calibration ready Word 4 25 1 LINCALRDYW5 Linearity calibration ready Word 5 26 1 LINCALRDYW6 Linearity calibration ready Word 6 27 1 ADC_DIFSEL ADC_DIFSEL ADC channel differential or single-ended mode selection register 0xC0 32 read-write n 0x0 0x0 DIFSEL ADC channel differential or single-ended mode for channel 0 20 ADC_DR ADC_DR ADC group regular conversion data register 0x40 32 read-only n 0x0 0x0 RDATA ADC group regular conversion data 0 32 ADC_HTR2 ADC_HTR2 ADC watchdog higher threshold register 2 0xB4 32 read-write n 0x0 0x0 HTR2 Analog watchdog 2 higher threshold 0 26 ADC_HTR3 ADC_HTR3 ADC watchdog higher threshold register 3 0xBC 32 read-write n 0x0 0x0 HTR3 Analog watchdog 3 higher threshold 0 26 ADC_IER ADC_IER ADC interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADC ready interrupt 0 1 AWD1IE ADC analog watchdog 1 interrupt 7 1 AWD2IE ADC analog watchdog 2 interrupt 8 1 AWD3IE ADC analog watchdog 3 interrupt 9 1 EOCIE ADC group regular end of unitary conversion interrupt 2 1 EOSIE ADC group regular end of sequence conversions interrupt 3 1 EOSMPIE ADC group regular end of sampling interrupt 1 1 JEOCIE ADC group injected end of unitary conversion interrupt 5 1 JEOSIE ADC group injected end of sequence conversions interrupt 6 1 JQOVFIE ADC group injected contexts queue overflow interrupt 10 1 OVRIE ADC group regular overrun interrupt 4 1 ADC_ISR ADC_ISR ADC interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADC ready flag 0 1 AWD1 ADC analog watchdog 1 flag 7 1 AWD2 ADC analog watchdog 2 flag 8 1 AWD3 ADC analog watchdog 3 flag 9 1 EOC ADC group regular end of unitary conversion flag 2 1 EOS ADC group regular end of sequence conversions flag 3 1 EOSMP ADC group regular end of sampling flag 1 1 JEOC ADC group injected end of unitary conversion flag 5 1 JEOS ADC group injected end of sequence conversions flag 6 1 JQOVF ADC group injected contexts queue overflow flag 10 1 OVR ADC group regular overrun flag 4 1 ADC_JDR1 ADC_JDR1 ADC group injected sequencer rank 1 register 0x80 32 read-only n 0x0 0x0 JDATA1 ADC group injected sequencer rank 1 conversion data 0 32 ADC_JDR2 ADC_JDR2 ADC group injected sequencer rank 2 register 0x84 32 read-only n 0x0 0x0 JDATA2 ADC group injected sequencer rank 2 conversion data 0 32 ADC_JDR3 ADC_JDR3 ADC group injected sequencer rank 3 register 0x88 32 read-only n 0x0 0x0 JDATA3 ADC group injected sequencer rank 3 conversion data 0 32 ADC_JDR4 ADC_JDR4 ADC group injected sequencer rank 4 register 0x8C 32 read-only n 0x0 0x0 JDATA4 ADC group injected sequencer rank 4 conversion data 0 32 ADC_JSQR ADC_JSQR ADC group injected sequencer register 0x4C 32 read-write n 0x0 0x0 JEXTEN ADC group injected external trigger polarity 7 2 JEXTSEL ADC group injected external trigger source 2 5 JL ADC group injected sequencer scan length 0 2 JSQ1 ADC group injected sequencer rank 1 9 5 JSQ2 ADC group injected sequencer rank 2 15 5 JSQ3 ADC group injected sequencer rank 3 21 5 JSQ4 ADC group injected sequencer rank 4 27 5 ADC_LHTR1 ADC_LHTR1 ADC analog watchdog 2 threshold register 0x24 32 read-write n 0x0 0x0 LHTR1 ADC analog watchdog 2 threshold low 0 26 ADC_LTR1 ADC_LTR1 ADC analog watchdog 1 threshold register 0x20 32 read-write n 0x0 0x0 LTR1 ADC analog watchdog 1 threshold low 0 26 ADC_LTR2 ADC_LTR2 ADC watchdog lower threshold register 2 0xB0 32 read-write n 0x0 0x0 LTR2 Analog watchdog 2 lower threshold 0 26 ADC_LTR3 ADC_LTR3 ADC watchdog lower threshold register 3 0xB8 32 read-write n 0x0 0x0 LTR3 Analog watchdog 3 lower threshold 0 26 ADC_OFR1 ADC_OFR1 ADC offset number 1 register 0x60 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR2 ADC_OFR2 ADC offset number 2 register 0x64 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR3 ADC_OFR3 ADC offset number 3 register 0x68 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_OFR4 ADC_OFR4 ADC offset number 4 register 0x6C 32 read-write n 0x0 0x0 OFFSET1 ADC offset number 1 offset level 0 26 OFFSET1_CH ADC offset number 1 channel selection 26 5 SSATE ADC offset number 1 enable 31 1 ADC_PCSEL ADC_PCSEL ADC channel preselection register 0x1C 32 read-write n 0x0 0x0 PCSEL0 PCSEL0 0 1 PCSEL1 PCSEL1 1 1 PCSEL10 PCSEL10 10 1 PCSEL11 PCSEL11 11 1 PCSEL12 PCSEL12 12 1 PCSEL13 PCSEL13 13 1 PCSEL14 PCSEL14 14 1 PCSEL15 PCSEL15 15 1 PCSEL16 PCSEL16 16 1 PCSEL17 PCSEL17 17 1 PCSEL18 PCSEL18 18 1 PCSEL19 PCSEL19 19 1 PCSEL2 PCSEL2 2 1 PCSEL3 PCSEL3 3 1 PCSEL4 PCSEL4 4 1 PCSEL5 PCSEL5 5 1 PCSEL6 PCSEL6 6 1 PCSEL7 PCSEL7 7 1 PCSEL8 PCSEL8 8 1 PCSEL9 PCSEL9 9 1 ADC_SMPR1 ADC_SMPR1 ADC sampling time register 1 0x14 32 read-write n 0x0 0x0 SMP0 ADC channel 0 sampling time selection 0 3 SMP1 ADC channel 1 sampling time selection 3 3 SMP2 ADC channel 2 sampling time selection 6 3 SMP3 ADC channel 3 sampling time selection 9 3 SMP4 ADC channel 4 sampling time selection 12 3 SMP5 ADC channel 5 sampling time selection 15 3 SMP6 ADC channel 6 sampling time selection 18 3 SMP7 ADC channel 7 sampling time selection 21 3 SMP8 ADC channel 8 sampling time selection 24 3 SMP9 ADC channel 9 sampling time selection 27 3 ADC_SMPR2 ADC_SMPR2 ADC sampling time register 2 0x18 32 read-write n 0x0 0x0 SMP10 ADC channel 10 sampling time selection 0 3 SMP11 ADC channel 11 sampling time selection 3 3 SMP12 ADC channel 12 sampling time selection 6 3 SMP13 ADC channel 13 sampling time selection 9 3 SMP14 ADC channel 14 sampling time selection 12 3 SMP15 ADC channel 15 sampling time selection 15 3 SMP16 ADC channel 16 sampling time selection 18 3 SMP17 ADC channel 17 sampling time selection 21 3 SMP18 ADC channel 18 sampling time selection 24 3 SMP19 ADC channel 18 sampling time selection 27 3 ADC_SQR1 ADC_SQR1 ADC group regular sequencer ranks register 1 0x30 32 read-write n 0x0 0x0 L3 L3 0 4 SQ1 ADC group regular sequencer rank 1 6 5 SQ2 ADC group regular sequencer rank 2 12 5 SQ3 ADC group regular sequencer rank 3 18 5 SQ4 ADC group regular sequencer rank 4 24 5 ADC_SQR2 ADC_SQR2 ADC group regular sequencer ranks register 2 0x34 32 read-write n 0x0 0x0 SQ5 ADC group regular sequencer rank 5 0 5 SQ6 ADC group regular sequencer rank 6 6 5 SQ7 ADC group regular sequencer rank 7 12 5 SQ8 ADC group regular sequencer rank 8 18 5 SQ9 ADC group regular sequencer rank 9 24 5 ADC_SQR3 ADC_SQR3 ADC group regular sequencer ranks register 3 0x38 32 read-write n 0x0 0x0 SQ10 ADC group regular sequencer rank 10 0 5 SQ11 ADC group regular sequencer rank 11 6 5 SQ12 ADC group regular sequencer rank 12 12 5 SQ13 ADC group regular sequencer rank 13 18 5 SQ14 ADC group regular sequencer rank 14 24 5 ADC_SQR4 ADC_SQR4 ADC group regular sequencer ranks register 4 0x3C 32 read-write n 0x0 0x0 SQ15 ADC group regular sequencer rank 15 0 5 SQ16 ADC group regular sequencer rank 16 6 5 OR ADC2_OR ADC2 option register CR 0xD0 32 read-write n 0x0 0x0 VDDCOREEN VDDCOREEN 0 1 AXIMC AXIMC AXIMC 0x0 0x0 0x100000 registers n COMP_ID_0 COMP_ID_0 AXIMC component ID0 register 0x1FF0 32 read-only n 0x0 0x0 PREAMBLE preamble bits 0 8 COMP_ID_1 COMP_ID_1 AXIMC component ID1 register 0x1FF4 32 read-only n 0x0 0x0 CLASS Component class 4 4 PREAMBLE preamble bits 0 4 COMP_ID_2 COMP_ID_2 AXIMC component ID2 register 0x1FF8 32 read-only n 0x0 0x0 PREAMBLE preamble bits 0 8 COMP_ID_3 COMP_ID_3 AXIMC component ID3 register 0x1FFC 32 read-only n 0x0 0x0 PREAMBLE preamble bits 0 8 FN_MOD_LB FN_MOD_LB AXIMC long burst capability inhibition register 0x4A02C 32 read-write n 0x0 0x0 FN_MOD_LB controls burst breaking of long bursts 0 1 M0_FN_MOD M0_FN_MOD AXIMC master 0 issuing capability override functionality register 0x42108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M0_FN_MOD2 M0_FN_MOD2 AXIMC master 0 packing functionality register 0x42024 32 read-write n 0x0 0x0 BYPASS_MERGE Disable packing of beats to match the output data 0 1 M0_FN_MOD_AHB M0_FN_MOD_AHB AXIMC master 0 AHB conversion override functionality register 0x42028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE Converts all AHB-Lite write transactions 0 1 WR_INC_OVERRIDE Converts all AHB-Lite read transactions 1 1 M0_READ_QOS M0_READ_QOS AXIMC master 0 read priority register 0x42100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M0_WRITE_QOS M0_WRITE_QOS AXIMC master 0 write priority register 0x42104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M10_FN_MOD M10_FN_MOD AXIMC master 10 issuing capability override functionality register 0x4C108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M10_READ_QOS M10_READ_QOS AXIMC master 10 read priority register 0x4C100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M10_WRITE_QOS M10_WRITE_QOS AXIMC master 10 write priority register 0x4C104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M1_FN_MOD M1_FN_MOD AXIMC master 1 issuing capability override functionality register 0x43108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M1_FN_MOD2 M1_FN_MOD2 AXIMC master 1 packing functionality register 0x43024 32 read-write n 0x0 0x0 BYPASS_MERGE Disable packing of beats to match the output data 0 1 M1_FN_MOD_AHB M1_FN_MOD_AHB AXIMC master 1 AHB conversion override functionality register 0x43028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE Converts all AHB-Lite write transactions 0 1 WR_INC_OVERRIDE Converts all AHB-Lite read transactions 1 1 M1_READ_QOS M1_READ_QOS AXIMC master 1 read priority register 0x43100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M1_WRITE_QOS M1_WRITE_QOS AXIMC master 1 write priority register 0x43104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M2_FN_MOD M2_FN_MOD AXIMC master 2 issuing capability override functionality register 0x44108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M2_FN_MOD2 M2_FN_MOD2 AXIMC master 2 packing functionality register 0x44024 32 read-write n 0x0 0x0 BYPASS_MERGE Disable packing of beats to match the output data 0 1 M2_FN_MOD_AHB M2_FN_MOD_AHB AXIMC master 2 AHB conversion override functionality register 0x44028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE Converts all AHB-Lite write transactions 0 1 WR_INC_OVERRIDE Converts all AHB-Lite read transactions 1 1 M2_READ_QOS M2_READ_QOS AXIMC master 2 read priority register 0x44100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M2_WRITE_QOS M2_WRITE_QOS AXIMC master 2 write priority register 0x44104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M3_FN_MOD M3_FN_MOD AXIMC master 3 packing functionality register 0x46108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M3_READ_QOS M3_READ_QOS AXIMC master 3 read priority register 0x46100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M3_WRITE_QOS M3_WRITE_QOS AXIMC master 3 write priority register 0x46104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M4_FN_MOD M4_FN_MOD AXIMC master 4 packing functionality register 0x4A108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M4_READ_QOS M4_READ_QOS AXIMC master 4 read priority register 0x4A100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M4_WRITE_QOS M4_WRITE_QOS AXIMC master 4 write priority register 0x4A104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M5_FN_MOD M5_FN_MOD AXIMC master 5 issuing capability override functionality register 0x45108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M5_FN_MOD2 M5_FN_MOD2 AXIMC master 5 packing functionality register 0x45024 32 read-write n 0x0 0x0 BYPASS_MERGE Disable packing of beats to match the output data 0 1 M5_FN_MOD_AHB M5_FN_MOD_AHB AXIMC master 5 AHB conversion override functionality register 0x45028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE converts all AHB-Lite write transactions to a series of single beat 0 1 WR_INC_OVERRIDE converts all AHB-Lite read transactions to a series of single beat 1 1 M5_READ_QOS M5_READ_QOS AXIMC master 5 read priority register 0x45100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M5_WRITE_QOS M5_WRITE_QOS AXIMC master 5 write priority register 0x45104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M6_FN_MOD M6_FN_MOD AXIMC master 6 issuing capability override functionality register 0x4D108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M6_FN_MOD_AHB M6_FN_MOD_AHB AXIMC master 6 AHB conversion override functionality register 0x4D028 32 read-write n 0x0 0x0 RD_INC_OVERRIDE converts all AHB-Lite write transactions to a series of single beat 0 1 WR_INC_OVERRIDE converts all AHB-Lite read transactions to a series of single beat 1 1 M6_READ_QOS M6_READ_QOS AXIMC master 6 read priority register 0x4D100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M6_WRITE_QOS M6_WRITE_QOS AXIMC master 6 write priority register 0x4D104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M7_FN_MOD M7_FN_MOD AXIMC master 7 issuing capability override functionality register 0x47108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M7_READ_QOS M7_READ_QOS AXIMC master 7 read priority register 0x47100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M7_WRITE_QOS M7_WRITE_QOS AXIMC master 7 write priority register 0x47104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M8_FN_MOD M8_FN_MOD AXIMC master 8 issuing capability override functionality register 0x48108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M8_READ_QOS M8_READ_QOS AXIMC master 8 read priority register 0x48100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M8_WRITE_QOS M8_WRITE_QOS AXIMC master 8 write priority register 0x48104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 M9_FN_MOD M9_FN_MOD AXIMC master 9 issuing capability override functionality register 0x4B108 32 read-write n 0x0 0x0 READ_ISS_OVERRIDE override AMIB read issuing capability 0 1 WRITE_ISS_OVERRIDE override AMIB write issuing capability 1 1 M9_READ_QOS M9_READ_QOS AXIMC master 9 read priority register 0x4B100 32 read-write n 0x0 0x0 AR_QOS read channel QoS setting 0 4 M9_WRITE_QOS M9_WRITE_QOS AXIMC master 9 write priority register 0x4B104 32 read-write n 0x0 0x0 AW_QOS write channel QoS setting 0 4 PERIPH_ID_0 PERIPH_ID_0 AXIMC peripheral ID0 register 0x1FE0 32 read-only n 0x0 0x0 PERIPH_ID_0 part number 0 8 PERIPH_ID_1 PERIPH_ID_1 AXIMC peripheral ID1 register 0x1FE4 32 read-only n 0x0 0x0 PERIPH_ID_1 part number 0 8 PERIPH_ID_2 PERIPH_ID_2 AXIMC peripheral ID2 register 0x1FE8 32 read-only n 0x0 0x0 PERIPH_ID_2 part number 0 8 PERIPH_ID_3 PERIPH_ID_3 AXIMC peripheral ID3 register 0x1FEC 32 read-only n 0x0 0x0 CUST_MOD_NUM customer modification 0 4 REV_AND customer version 4 4 PERIPH_ID_4 PERIPH_ID_4 AXIMC peripheral ID4 register 0x1FD0 32 read-only n 0x0 0x0 JEP106CON JEP106 continuation code 0 4 KCOUNT4 register file size 4 4 PERIPH_ID_5 PERIPH_ID_5 AXIMC peripheral ID5 register 0x1FD4 32 read-only n 0x0 0x0 PERIPH_ID_5 not used 0 8 PERIPH_ID_6 PERIPH_ID_6 AXIMC peripheral ID6 register 0x1FD8 32 read-only n 0x0 0x0 PERIPH_ID_6 not used 0 8 PERIPH_ID_7 PERIPH_ID_7 AXIMC peripheral ID7 register 0x1FDC8 32 read-only n 0x0 0x0 PERIPH_ID_7 not used 0 8 BSEC BSEC BSEC 0x0 0x0 0x1000 registers n DENABLE BSEC_DENABLE reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page187. 0x14 32 read-write n 0x0 0x0 CFGSDISABLE CFGSDISABLE 9 1 read-write CP15SDISABLE CP15SDISABLE 7 2 read-write DBGEN DBGEN 1 1 read-write DBGSWENABLE DBGSWENABLE 10 1 read-write DEVICEEN DEVICEEN 3 1 read-write DFTEN DFTEN 0 1 read-write HDPEN HDPEN 4 1 read-write NIDEN NIDEN 2 1 read-write SPIDEN SPIDEN 5 1 read-write SPNIDEN SPNIDEN 6 1 read-write HWCFGR BSEC_HWCFGR BSEC hardware configuration register 0xFF0 32 read-only n 0x0 0x0 ECC_USE ECC_USE 4 4 read-only SIZE SIZE 0 4 read-only IPIDR BSEC_IPIDR BSEC identification register 0xFF8 32 read-only n 0x0 0x0 ID ID 0 32 read-only JTAGIN BSEC_JTAGIN BSEC JTAG input register 0xAC 32 read-only n 0x0 0x0 DATA DATA 0 16 read-only JTAGOUT BSEC_JTAGOUT BSEC JTAG output register 0xB0 32 read-write n 0x0 0x0 DATA DATA 0 16 read-write OTP_CONFIG BSEC_OTP_CONFIG BSEC OTP configuration register 0x0 32 read-write n 0x0 0x0 FRC FRC 1 2 read-write PRGWIDTH PRGWIDTH 3 4 read-write PWRUP PWRUP 0 1 read-write TREAD TREAD 7 2 read-write OTP_CONTROL BSEC_OTP_CONTROL BSEC OTP control register 0x4 32 read-write n 0x0 0x0 ADDR ADDR 0 7 read-write LOCK LOCK 9 1 read-write PROG PROG 8 1 read-write OTP_DATA0 BSEC_OTP_DATA0 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x200 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA1 BSEC_OTP_DATA1 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x204 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA10 BSEC_OTP_DATA10 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x228 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA11 BSEC_OTP_DATA11 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x22C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA12 BSEC_OTP_DATA12 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x230 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA13 BSEC_OTP_DATA13 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x234 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA14 BSEC_OTP_DATA14 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x238 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA15 BSEC_OTP_DATA15 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x23C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA16 BSEC_OTP_DATA16 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x240 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA17 BSEC_OTP_DATA17 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x244 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA18 BSEC_OTP_DATA18 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x248 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA19 BSEC_OTP_DATA19 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x24C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA2 BSEC_OTP_DATA2 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x208 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA20 BSEC_OTP_DATA20 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x250 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA21 BSEC_OTP_DATA21 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x254 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA22 BSEC_OTP_DATA22 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x258 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA23 BSEC_OTP_DATA23 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x25C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA24 BSEC_OTP_DATA24 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x260 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA25 BSEC_OTP_DATA25 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x264 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA26 BSEC_OTP_DATA26 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x268 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA27 BSEC_OTP_DATA27 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x26C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA28 BSEC_OTP_DATA28 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x270 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA29 BSEC_OTP_DATA29 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x274 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA3 BSEC_OTP_DATA3 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x20C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA30 BSEC_OTP_DATA30 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x278 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA31 BSEC_OTP_DATA31 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x27C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA32 BSEC_OTP_DATA32 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x280 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA33 BSEC_OTP_DATA33 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x284 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA34 BSEC_OTP_DATA34 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x288 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA35 BSEC_OTP_DATA35 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x28C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA36 BSEC_OTP_DATA36 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x290 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA37 BSEC_OTP_DATA37 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x294 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA38 BSEC_OTP_DATA38 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x298 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA39 BSEC_OTP_DATA39 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x29C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA4 BSEC_OTP_DATA4 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x210 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA40 BSEC_OTP_DATA40 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA41 BSEC_OTP_DATA41 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA42 BSEC_OTP_DATA42 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2A8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA43 BSEC_OTP_DATA43 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2AC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA44 BSEC_OTP_DATA44 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA45 BSEC_OTP_DATA45 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA46 BSEC_OTP_DATA46 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2B8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA47 BSEC_OTP_DATA47 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2BC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA48 BSEC_OTP_DATA48 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA49 BSEC_OTP_DATA49 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA5 BSEC_OTP_DATA5 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x214 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA50 BSEC_OTP_DATA50 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2C8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA51 BSEC_OTP_DATA51 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2CC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA52 BSEC_OTP_DATA52 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA53 BSEC_OTP_DATA53 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA54 BSEC_OTP_DATA54 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2D8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA55 BSEC_OTP_DATA55 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2DC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA56 BSEC_OTP_DATA56 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA57 BSEC_OTP_DATA57 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA58 BSEC_OTP_DATA58 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2E8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA59 BSEC_OTP_DATA59 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2EC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA6 BSEC_OTP_DATA6 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x218 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA60 BSEC_OTP_DATA60 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F0 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA61 BSEC_OTP_DATA61 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA62 BSEC_OTP_DATA62 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2F8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA63 BSEC_OTP_DATA63 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x2FC 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA64 BSEC_OTP_DATA64 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x300 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA65 BSEC_OTP_DATA65 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x304 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA66 BSEC_OTP_DATA66 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x308 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA67 BSEC_OTP_DATA67 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x30C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA68 BSEC_OTP_DATA68 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x310 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA69 BSEC_OTP_DATA69 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x314 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA7 BSEC_OTP_DATA7 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x21C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA70 BSEC_OTP_DATA70 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x318 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA71 BSEC_OTP_DATA71 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x31C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA72 BSEC_OTP_DATA72 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x320 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA73 BSEC_OTP_DATA73 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x324 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA74 BSEC_OTP_DATA74 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x328 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA75 BSEC_OTP_DATA75 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x32C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA76 BSEC_OTP_DATA76 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x330 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA77 BSEC_OTP_DATA77 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x334 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA78 BSEC_OTP_DATA78 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x338 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA79 BSEC_OTP_DATA79 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x33C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA8 BSEC_OTP_DATA8 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x220 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA80 BSEC_OTP_DATA80 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x340 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA81 BSEC_OTP_DATA81 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x344 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA82 BSEC_OTP_DATA82 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x348 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA83 BSEC_OTP_DATA83 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x34C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA84 BSEC_OTP_DATA84 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x350 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA85 BSEC_OTP_DATA85 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x354 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA86 BSEC_OTP_DATA86 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x358 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA87 BSEC_OTP_DATA87 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x35C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA88 BSEC_OTP_DATA88 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x360 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA89 BSEC_OTP_DATA89 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x364 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA9 BSEC_OTP_DATA9 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x224 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA90 BSEC_OTP_DATA90 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x368 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA91 BSEC_OTP_DATA91 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x36C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA92 BSEC_OTP_DATA92 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x370 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA93 BSEC_OTP_DATA93 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x374 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA94 BSEC_OTP_DATA94 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x378 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DATA95 BSEC_OTP_DATA95 Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page181) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode. 0x37C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write OTP_DISTURBED0 BSEC_OTP_DISTURBED0 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x1C 32 read-only n 0x0 0x0 DIS DIS 0 32 read-only OTP_DISTURBED1 BSEC_OTP_DISTURBED1 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x20 32 read-only n 0x0 0x0 DIS DIS 0 32 read-only OTP_DISTURBED2 BSEC_OTP_DISTURBED2 BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. 0x24 32 read-only n 0x0 0x0 DIS DIS 0 32 read-only OTP_ERROR0 BSEC_OTP_ERROR0 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x34 32 read-only n 0x0 0x0 ERR ERR 0 32 read-only OTP_ERROR1 BSEC_OTP_ERROR1 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x38 32 read-only n 0x0 0x0 ERR ERR 0 32 read-only OTP_ERROR2 BSEC_OTP_ERROR2 BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC. 0x3C 32 read-only n 0x0 0x0 ERR ERR 0 32 read-only OTP_LOCK BSEC_OTP_LOCK BSEC OTP lock configuration register 0x10 32 read-write n 0x0 0x0 DENREG DENREG 2 1 read-write GPLOCK GPLOCK 4 1 read-write OTP OTP 0 1 read-write ROMLOCK ROMLOCK 1 1 read-write OTP_SPLOCK0 BSEC_OTP_SPLOCK0 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x64 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 read-write OTP_SPLOCK1 BSEC_OTP_SPLOCK1 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x68 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 read-write OTP_SPLOCK2 BSEC_OTP_SPLOCK2 BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored. 0x6C 32 read-write n 0x0 0x0 SPLOCK SPLOCK 0 32 read-write OTP_SRLOCK0 BSEC_OTP_SRLOCK0 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x94 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 read-write OTP_SRLOCK1 BSEC_OTP_SRLOCK1 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x98 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 read-write OTP_SRLOCK2 BSEC_OTP_SRLOCK2 BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect. 0x9C 32 read-write n 0x0 0x0 SRLOCK SRLOCK 0 32 read-write OTP_STATUS BSEC_OTP_STATUS BSEC OTP status register 0xC 32 read-only n 0x0 0x0 BIST1LOCK BIST1LOCK 6 1 read-only BIST2LOCK BIST2LOCK 7 1 read-only BUSY BUSY 3 1 read-only FULLDBG FULLDBG 1 1 read-only INVALID INVALID 2 1 read-only PROGFAIL PROGFAIL 4 1 read-only PWRON PWRON 5 1 read-only SECURE SECURE 0 1 read-only OTP_SWLOCK0 BSEC_OTP_SWLOCK0 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x7C 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 read-write OTP_SWLOCK1 BSEC_OTP_SWLOCK1 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x80 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 read-write OTP_SWLOCK2 BSEC_OTP_SWLOCK2 BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented. 0x84 32 read-write n 0x0 0x0 SWLOCK SWLOCK 0 32 read-write OTP_WRDATA BSEC_OTP_WRDATA BSEC OTP write data register 0x8 32 read-write n 0x0 0x0 WRDATA WRDATA 0 32 read-write OTP_WRLOCK0 BSEC_OTP_WRLOCK0 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page184). 0x4C 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 read-only OTP_WRLOCK1 BSEC_OTP_WRLOCK1 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page184). 0x50 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 read-only OTP_WRLOCK2 BSEC_OTP_WRLOCK2 BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page184). 0x54 32 read-only n 0x0 0x0 WRLOCK WRLOCK 0 32 read-only SCRATCH BSEC_SCRATCH BSEC scratch register 0xB4 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write SIDR BSEC_SIDR BSEC size identification register 0xFFC 32 read-only n 0x0 0x0 SID SID 0 32 read-only VERR BSEC_VERR BSEC version register 0xFF4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only CCU CCU registers CCU 0x0 0x0 0x400 registers n CCFG CCFG Calibration Configuration Register 0x4 32 read-write n 0x0 0x0 BCC Bypass Clock Calibration 6 1 CDIV Clock Divider 16 4 CFL Calibration Field Length 7 1 OCPM Oscillator Clock Periods Minimum 8 8 SWR Software Reset 31 1 TQBT Time Quanta per Bit Time 0 5 CREL CREL Clock Calibration Unit Core Release Register 0x0 32 read-write n 0x0 0x0 DAY Time Stamp Day 0 8 MON Time Stamp Month 8 8 REL Core Release 28 4 STEP Step of Core Release 24 4 SUBSTEP Sub-step of Core Release 20 4 YEAR Time Stamp Year 16 4 CSTAT CSTAT Calibration Status Register 0x8 32 read-write n 0x0 0x0 CALS Calibration State 30 2 OCPC Oscillator Clock Period Counter 0 18 TQC Time Quanta Counter 18 11 CWD CWD Calibration Watchdog Register 0xC 32 read-write n 0x0 0x0 WDC WDC 0 16 WDV WDV 16 16 IE IE Clock Calibration Unit Interrupt Enable Register 0x14 32 read-write n 0x0 0x0 CSCE Calibration State Changed Enable 1 1 CWEE Calibration Watchdog Event Enable 0 1 IR IR Clock Calibration Unit Interrupt Register 0x10 32 read-write n 0x0 0x0 CSC Calibration State Changed 1 1 CWE Calibration Watchdog Event 0 1 CEC CEC HDMI_CEC 0x0 0x0 0x400 registers n CFGR CEC_CFGR This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0. 0x4 32 read-write n 0x0 0x0 BRDNOGEN BRDNOGEN 7 1 read-write BREGEN BREGEN 5 1 read-write BRESTP BRESTP 4 1 read-write LBPEGEN LBPEGEN 6 1 read-write LSTN LSTN 31 1 read-write OAR OAR 16 15 read-write RXTOL RXTOL 3 1 read-write SFT SFT 0 3 read-write SFTOP SFTOP 8 1 read-write CR CEC_CR CEC control register 0x0 32 read-write n 0x0 0x0 CECEN CECEN 0 1 read-write TXEOM TXEOM 2 1 read-write TXSOM TXSOM 1 1 read-write IER CEC_IER CEC interrupt enable register 0x14 32 read-write n 0x0 0x0 ARBLSTIE ARBLSTIE 7 1 read-write BREIE BREIE 3 1 read-write LBPEIE LBPEIE 5 1 read-write RXACKIE RXACKIE 6 1 read-write RXBRIE RXBRIE 0 1 read-write RXENDIE RXENDIE 1 1 read-write RXOVRIE RXOVRIE 2 1 read-write SBPEIE SBPEIE 4 1 read-write TXACKIE TXACKIE 12 1 read-write TXBRIE TXBRIE 8 1 read-write TXENDIE TXENDIE 9 1 read-write TXERRIE TXERRIE 11 1 read-write TXUDRIE TXUDRIE 10 1 read-write ISR CEC_ISR CEC Interrupt and Status Register 0x10 32 read-write n 0x0 0x0 ARBLST ARBLST 7 1 read-write BRE BRE 3 1 read-write LBPE LBPE 5 1 read-write RXACKE RXACKE 6 1 read-write RXBR RXBR 0 1 read-write RXEND RXEND 1 1 read-write RXOVR RXOVR 2 1 read-write SBPE SBPE 4 1 read-write TXACKE TXACKE 12 1 read-write TXBR TXBR 8 1 read-write TXEND TXEND 9 1 read-write TXERR TXERR 11 1 read-write TXUDR TXUDR 10 1 read-write RXDR CEC_RXDR CEC Rx data register 0xC 32 read-only n 0x0 0x0 RXD RXD 0 8 read-only TXDR CEC_TXDR CEC Tx data register 0x8 32 read-write n 0x0 0x0 TXD TXD 0 8 write-only CRC1 Cyclic redundancy check calculation unit CRC 0x0 0x0 0x1000 registers n CRC_CR CRC_CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE POLYSIZE 3 2 read-write RESET RESET 0 1 read-write REV_IN REV_IN 5 2 read-write REV_OUT REV_OUT 7 1 read-write CRC_DR CRC_DR Data register 0x0 32 read-write n 0x0 0x0 DR DR 0 32 read-write CRC_IDR CRC_IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR IDR 0 32 read-write CRC_INIT CRC_INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 CRC_INIT CRC_INIT 0 32 read-write CRC_POL CRC_POL CRC polynomial 0x14 32 read-write n 0x0 0x0 POL POL 0 32 read-write CRC2 Cyclic redundancy check calculation unit CRC 0x0 0x0 0x1000 registers n CRC_CR CRC_CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE POLYSIZE 3 2 read-write RESET RESET 0 1 read-write REV_IN REV_IN 5 2 read-write REV_OUT REV_OUT 7 1 read-write CRC_DR CRC_DR Data register 0x0 32 read-write n 0x0 0x0 DR DR 0 32 read-write CRC_IDR CRC_IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR IDR 0 32 read-write CRC_INIT CRC_INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 CRC_INIT CRC_INIT 0 32 read-write CRC_POL CRC_POL CRC polynomial 0x14 32 read-write n 0x0 0x0 POL POL 0 32 read-write CRYP1 Cryptographic processor CRYP 0x0 0x0 0x400 registers n CRYP CRYP global interrupt 79 CRYP_CR CRYP_CR control register 0x0 32 read-write n 0x0 0x0 ALGODIR Algorithm direction 2 1 read-write ALGOMODE0 Algorithm mode 3 3 read-write ALGOMODE3 ALGOMODE 19 1 read-write CRYPEN Cryptographic processor enable 15 1 read-write DATATYPE Data type selection 6 2 read-write FFLUSH FIFO flush 14 1 write-only GCM_CCMPH GCM_CCMPH 16 2 read-write KEYSIZE Key size selection (AES mode only) 8 2 read-write NPBLB NPBLB 20 4 read-write CRYP_CSGCM0R CRYP_CSGCM0R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x70 32 read-write n 0x0 0x0 CRYP_CSGCM0R CRYP_CSGCM0R 0 32 read-write CRYP_CSGCM1R CRYP_CSGCM1R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x74 32 read-write n 0x0 0x0 CRYP_CSGCM1R CRYP_CSGCM1R 0 32 read-write CRYP_CSGCM2R CRYP_CSGCM2R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x78 32 read-write n 0x0 0x0 CRYP_CSGCM2R CRYP_CSGCM2R 0 32 read-write CRYP_CSGCM3R CRYP_CSGCM3R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x7C 32 read-write n 0x0 0x0 CRYP_CSGCM3R CRYP_CSGCM3R 0 32 read-write CRYP_CSGCM4R CRYP_CSGCM4R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x80 32 read-write n 0x0 0x0 CRYP_CSGCM4R CRYP_CSGCM4R 0 32 read-write CRYP_CSGCM5R CRYP_CSGCM5R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x84 32 read-write n 0x0 0x0 CRYP_CSGCM5R CRYP_CSGCM5R 0 32 read-write CRYP_CSGCM6R CRYP_CSGCM6R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x88 32 read-write n 0x0 0x0 CRYP_CSGCM6R CRYP_CSGCM6R 0 32 read-write CRYP_CSGCM7R CRYP_CSGCM7R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x8C 32 read-write n 0x0 0x0 CRYP_CSGCM7R CRYP_CSGCM7R 0 32 read-write CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x50 32 read-write n 0x0 0x0 CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R 0 32 read-write CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x54 32 read-write n 0x0 0x0 CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R 0 32 read-write CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x58 32 read-write n 0x0 0x0 CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R 0 32 read-write CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x5C 32 read-write n 0x0 0x0 CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R 0 32 read-write CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x60 32 read-write n 0x0 0x0 CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R 0 32 read-write CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x64 32 read-write n 0x0 0x0 CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R 0 32 read-write CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x68 32 read-write n 0x0 0x0 CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R 0 32 read-write CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x6C 32 read-write n 0x0 0x0 CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R 0 32 read-write CRYP_DIN CRYP_DIN The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 0x8 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 read-write CRYP_DMACR CRYP_DMACR CRYP DMA control register 0x10 32 read-write n 0x0 0x0 DIEN DIEN 0 1 read-write DOEN DOEN 1 1 read-write CRYP_DOUT CRYP_DOUT The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 0xC 32 read-only n 0x0 0x0 DATAOUT DATAOUT 0 32 read-only CRYP_HWCFGR CRYP_HWCFGR CRYP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 read-only CFG2 CFG2 4 4 read-only CFG3 CFG3 8 4 read-only CFG4 CFG4 12 4 read-only CRYP_IMSCR CRYP_IMSCR The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 0x14 32 read-write n 0x0 0x0 INIM INIM 0 1 read-write OUTIM OUTIM 1 1 read-write CRYP_IPIDR CRYP_IPIDR CRYP Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only CRYP_IV0LR CRYP_IV0LR The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section23.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 0x40 32 read-write n 0x0 0x0 IV0 IV0 31 1 read-write IV1 IV1 30 1 read-write IV10 IV10 21 1 read-write IV11 IV11 20 1 read-write IV12 IV12 19 1 read-write IV13 IV13 18 1 read-write IV14 IV14 17 1 read-write IV15 IV15 16 1 read-write IV16 IV16 15 1 read-write IV17 IV17 14 1 read-write IV18 IV18 13 1 read-write IV19 IV19 12 1 read-write IV2 IV2 29 1 read-write IV20 IV20 11 1 read-write IV21 IV21 10 1 read-write IV22 IV22 9 1 read-write IV23 IV23 8 1 read-write IV24 IV24 7 1 read-write IV25 IV25 6 1 read-write IV26 IV26 5 1 read-write IV27 IV27 4 1 read-write IV28 IV28 3 1 read-write IV29 IV29 2 1 read-write IV3 IV3 28 1 read-write IV30 IV30 1 1 read-write IV31 IV31 0 1 read-write IV4 IV4 27 1 read-write IV5 IV5 26 1 read-write IV6 IV6 25 1 read-write IV7 IV7 24 1 read-write IV8 IV8 23 1 read-write IV9 IV9 22 1 read-write CRYP_IV0RR CRYP_IV0RR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x44 32 read-write n 0x0 0x0 IV32 IV32 31 1 read-write IV33 IV33 30 1 read-write IV34 IV34 29 1 read-write IV35 IV35 28 1 read-write IV36 IV36 27 1 read-write IV37 IV37 26 1 read-write IV38 IV38 25 1 read-write IV39 IV39 24 1 read-write IV40 IV40 23 1 read-write IV41 IV41 22 1 read-write IV42 IV42 21 1 read-write IV43 IV43 20 1 read-write IV44 IV44 19 1 read-write IV45 IV45 18 1 read-write IV46 IV46 17 1 read-write IV47 IV47 16 1 read-write IV48 IV48 15 1 read-write IV49 IV49 14 1 read-write IV50 IV50 13 1 read-write IV51 IV51 12 1 read-write IV52 IV52 11 1 read-write IV53 IV53 10 1 read-write IV54 IV54 9 1 read-write IV55 IV55 8 1 read-write IV56 IV56 7 1 read-write IV57 IV57 6 1 read-write IV58 IV58 5 1 read-write IV59 IV59 4 1 read-write IV60 IV60 3 1 read-write IV61 IV61 2 1 read-write IV62 IV62 1 1 read-write IV63 IV63 0 1 read-write CRYP_IV1LR CRYP_IV1LR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x48 32 read-write n 0x0 0x0 IV64 IV64 31 1 read-write IV65 IV65 30 1 read-write IV66 IV66 29 1 read-write IV67 IV67 28 1 read-write IV68 IV68 27 1 read-write IV69 IV69 26 1 read-write IV70 IV70 25 1 read-write IV71 IV71 24 1 read-write IV72 IV72 23 1 read-write IV73 IV73 22 1 read-write IV74 IV74 21 1 read-write IV75 IV75 20 1 read-write IV76 IV76 19 1 read-write IV77 IV77 18 1 read-write IV78 IV78 17 1 read-write IV79 IV79 16 1 read-write IV80 IV80 15 1 read-write IV81 IV81 14 1 read-write IV82 IV82 13 1 read-write IV83 IV83 12 1 read-write IV84 IV84 11 1 read-write IV85 IV85 10 1 read-write IV86 IV86 9 1 read-write IV87 IV87 8 1 read-write IV88 IV88 7 1 read-write IV89 IV89 6 1 read-write IV90 IV90 5 1 read-write IV91 IV91 4 1 read-write IV92 IV92 3 1 read-write IV93 IV93 2 1 read-write IV94 IV94 1 1 read-write IV95 IV95 0 1 read-write CRYP_IV1RR CRYP_IV1RR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x4C 32 read-write n 0x0 0x0 IV100 IV100 27 1 read-write IV101 IV101 26 1 read-write IV102 IV102 25 1 read-write IV103 IV103 24 1 read-write IV104 IV104 23 1 read-write IV105 IV105 22 1 read-write IV106 IV106 21 1 read-write IV107 IV107 20 1 read-write IV108 IV108 19 1 read-write IV109 IV109 18 1 read-write IV110 IV110 17 1 read-write IV111 IV111 16 1 read-write IV112 IV112 15 1 read-write IV113 IV113 14 1 read-write IV114 IV114 13 1 read-write IV115 IV115 12 1 read-write IV116 IV116 11 1 read-write IV117 IV117 10 1 read-write IV118 IV118 9 1 read-write IV119 IV119 8 1 read-write IV120 IV120 7 1 read-write IV121 IV121 6 1 read-write IV122 IV122 5 1 read-write IV123 IV123 4 1 read-write IV124 IV124 3 1 read-write IV125 IV125 2 1 read-write IV126 IV126 1 1 read-write IV127 IV127 0 1 read-write IV96 IV96 31 1 read-write IV97 IV97 30 1 read-write IV98 IV98 29 1 read-write IV99 IV99 28 1 read-write CRYP_K0LR CRYP_K0LR CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section23.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 0x20 32 write-only n 0x0 0x0 K224 K224 0 1 write-only K225 K225 1 1 write-only K226 K226 2 1 write-only K227 K227 3 1 write-only K228 K228 4 1 write-only K229 K229 5 1 write-only K230 K230 6 1 write-only K231 K231 7 1 write-only K232 K232 8 1 write-only K233 K233 9 1 write-only K234 K234 10 1 write-only K235 K235 11 1 write-only K236 K236 12 1 write-only K237 K237 13 1 write-only K238 K238 14 1 write-only K239 K239 15 1 write-only K240 K240 16 1 write-only K241 K241 17 1 write-only K242 K242 18 1 write-only K243 K243 19 1 write-only K244 K244 20 1 write-only K245 K245 21 1 write-only K246 K246 22 1 write-only K247 K247 23 1 write-only K248 K248 24 1 write-only K249 K249 25 1 write-only K250 K250 26 1 write-only K251 K251 27 1 write-only K252 K252 28 1 write-only K253 K253 29 1 write-only K254 K254 30 1 write-only K255 K255 31 1 write-only CRYP_K0RR CRYP_K0RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x24 32 write-only n 0x0 0x0 K192 K192 0 1 write-only K193 K193 1 1 write-only K194 K194 2 1 write-only K195 K195 3 1 write-only K196 K196 4 1 write-only K197 K197 5 1 write-only K198 K198 6 1 write-only K199 K199 7 1 write-only K200 K200 8 1 write-only K201 K201 9 1 write-only K202 K202 10 1 write-only K203 K203 11 1 write-only K204 K204 12 1 write-only K205 K205 13 1 write-only K206 K206 14 1 write-only K207 K207 15 1 write-only K208 K208 16 1 write-only K209 K209 17 1 write-only K210 K210 18 1 write-only K211 K211 19 1 write-only K212 K212 20 1 write-only K213 K213 21 1 write-only K214 K214 22 1 write-only K215 K215 23 1 write-only K216 K216 24 1 write-only K217 K217 25 1 write-only K218 K218 26 1 write-only K219 K219 27 1 write-only K220 K220 28 1 write-only K221 K221 29 1 write-only K222 K222 30 1 write-only K223 K223 31 1 write-only CRYP_K1LR CRYP_K1LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x28 32 write-only n 0x0 0x0 K160 K160 0 1 write-only K161 K161 1 1 write-only K162 K162 2 1 write-only K163 K163 3 1 write-only K164 K164 4 1 write-only K165 K165 5 1 write-only K166 K166 6 1 write-only K167 K167 7 1 write-only K168 K168 8 1 write-only K169 K169 9 1 write-only K170 K170 10 1 write-only K171 K171 11 1 write-only K172 K172 12 1 write-only K173 K173 13 1 write-only K174 K174 14 1 write-only K175 K175 15 1 write-only K176 K176 16 1 write-only K177 K177 17 1 write-only K178 K178 18 1 write-only K179 K179 19 1 write-only K180 K180 20 1 write-only K181 K181 21 1 write-only K182 K182 22 1 write-only K183 K183 23 1 write-only K184 K184 24 1 write-only K185 K185 25 1 write-only K186 K186 26 1 write-only K187 K187 27 1 write-only K188 K188 28 1 write-only K189 K189 29 1 write-only K190 K190 30 1 write-only K191 K191 31 1 write-only CRYP_K1RR CRYP_K1RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x2C 32 write-only n 0x0 0x0 K128 K128 0 1 write-only K129 K129 1 1 write-only K130 K130 2 1 write-only K131 K131 3 1 write-only K132 K132 4 1 write-only K133 K133 5 1 write-only K134 K134 6 1 write-only K135 K135 7 1 write-only K136 K136 8 1 write-only K137 K137 9 1 write-only K138 K138 10 1 write-only K139 K139 11 1 write-only K140 K140 12 1 write-only K141 K141 13 1 write-only K142 K142 14 1 write-only K143 K143 15 1 write-only K144 K144 16 1 write-only K145 K145 17 1 write-only K146 K146 18 1 write-only K147 K147 19 1 write-only K148 K148 20 1 write-only K149 K149 21 1 write-only K150 K150 22 1 write-only K151 K151 23 1 write-only K152 K152 24 1 write-only K153 K153 25 1 write-only K154 K154 26 1 write-only K155 K155 27 1 write-only K156 K156 28 1 write-only K157 K157 29 1 write-only K158 K158 30 1 write-only K159 K159 31 1 write-only CRYP_K2LR CRYP_K2LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x30 32 write-only n 0x0 0x0 K100 K100 4 1 write-only K101 K101 5 1 write-only K102 K102 6 1 write-only K103 K103 7 1 write-only K104 K104 8 1 write-only K105 K105 9 1 write-only K106 K106 10 1 write-only K107 K107 11 1 write-only K108 K108 12 1 write-only K109 K109 13 1 write-only K110 K110 14 1 write-only K111 K111 15 1 write-only K112 K112 16 1 write-only K113 K113 17 1 write-only K114 K114 18 1 write-only K115 K115 19 1 write-only K116 K116 20 1 write-only K117 K117 21 1 write-only K118 K118 22 1 write-only K119 K119 23 1 write-only K120 K120 24 1 write-only K121 K121 25 1 write-only K122 K122 26 1 write-only K123 K123 27 1 write-only K124 K124 28 1 write-only K125 K125 29 1 write-only K126 K126 30 1 write-only K127 K127 31 1 write-only K96 K96 0 1 write-only K97 K97 1 1 write-only K98 K98 2 1 write-only K99 K99 3 1 write-only CRYP_K2RR CRYP_K2RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x34 32 write-only n 0x0 0x0 K64 K64 0 1 write-only K65 K65 1 1 write-only K66 K66 2 1 write-only K67 K67 3 1 write-only K68 K68 4 1 write-only K69 K69 5 1 write-only K70 K70 6 1 write-only K71 K71 7 1 write-only K72 K72 8 1 write-only K73 K73 9 1 write-only K74 K74 10 1 write-only K75 K75 11 1 write-only K76 K76 12 1 write-only K77 K77 13 1 write-only K78 K78 14 1 write-only K79 K79 15 1 write-only K80 K80 16 1 write-only K81 K81 17 1 write-only K82 K82 18 1 write-only K83 K83 19 1 write-only K84 K84 20 1 write-only K85 K85 21 1 write-only K86 K86 22 1 write-only K87 K87 23 1 write-only K88 K88 24 1 write-only K89 K89 25 1 write-only K90 K90 26 1 write-only K91 K91 27 1 write-only K92 K92 28 1 write-only K93 K93 29 1 write-only K94 K94 30 1 write-only K95 K95 31 1 write-only CRYP_K3LR CRYP_K3LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x38 32 write-only n 0x0 0x0 K32 K32 0 1 write-only K33 K33 1 1 write-only K34 K34 2 1 write-only K35 K35 3 1 write-only K36 K36 4 1 write-only K37 K37 5 1 write-only K38 K38 6 1 write-only K39 K39 7 1 write-only K40 K40 8 1 write-only K41 K41 9 1 write-only K42 K42 10 1 write-only K43 K43 11 1 write-only K44 K44 12 1 write-only K45 K45 13 1 write-only K46 K46 14 1 write-only K47 K47 15 1 write-only K48 K48 16 1 write-only K49 K49 17 1 write-only K50 K50 18 1 write-only K51 K51 19 1 write-only K52 K52 20 1 write-only K53 K53 21 1 write-only K54 K54 22 1 write-only K55 K55 23 1 write-only K56 K56 24 1 write-only K57 K57 25 1 write-only K58 K58 26 1 write-only K59 K59 27 1 write-only K60 K60 28 1 write-only K61 K61 29 1 write-only K62 K62 30 1 write-only K63 K63 31 1 write-only CRYP_K3RR CRYP_K3RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x3C 32 write-only n 0x0 0x0 K0 K0 0 1 write-only K1 K1 1 1 write-only K10 K10 10 1 write-only K11 K11 11 1 write-only K12 K12 12 1 write-only K13 K13 13 1 write-only K14 K14 14 1 write-only K15 K15 15 1 write-only K16 K16 16 1 write-only K17 K17 17 1 write-only K18 K18 18 1 write-only K19 K19 19 1 write-only K2 K2 2 1 write-only K20 K20 20 1 write-only K21 K21 21 1 write-only K22 K22 22 1 write-only K23 K23 23 1 write-only K24 K24 24 1 write-only K25 K25 25 1 write-only K26 K26 26 1 write-only K27 K27 27 1 write-only K28 K28 28 1 write-only K29 K29 29 1 write-only K3 K3 3 1 write-only K30 K30 30 1 write-only K31 K31 31 1 write-only K4 K4 4 1 write-only K5 K5 5 1 write-only K6 K6 6 1 write-only K7 K7 7 1 write-only K8 K8 8 1 write-only K9 K9 9 1 write-only CRYP_MID CRYP_MID CRYP HW Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 read-only CRYP_MISR CRYP_MISR The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 0x1C 32 read-only n 0x0 0x0 INMIS INMIS 0 1 read-only OUTMIS OUTMIS 1 1 read-only CRYP_RISR CRYP_RISR The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 0x18 32 read-only n 0x0 0x0 INRIS INRIS 0 1 read-only OUTRIS OUTRIS 1 1 read-only CRYP_SR CRYP_SR CRYP status register 0x4 32 read-only n 0x0 0x0 BUSY BUSY 4 1 read-only IFEM IFEM 0 1 read-only IFNF IFNF 1 1 read-only OFFU OFFU 3 1 read-only OFNE OFNE 2 1 read-only CRYP_VERR CRYP_VERR CRYP HW Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 read-only CRYP2 Cryptographic processor CRYP 0x0 0x0 0x400 registers n CRYP_CR CRYP_CR control register 0x0 32 read-write n 0x0 0x0 ALGODIR Algorithm direction 2 1 read-write ALGOMODE0 Algorithm mode 3 3 read-write ALGOMODE3 ALGOMODE 19 1 read-write CRYPEN Cryptographic processor enable 15 1 read-write DATATYPE Data type selection 6 2 read-write FFLUSH FIFO flush 14 1 write-only GCM_CCMPH GCM_CCMPH 16 2 read-write KEYSIZE Key size selection (AES mode only) 8 2 read-write NPBLB NPBLB 20 4 read-write CRYP_CSGCM0R CRYP_CSGCM0R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x70 32 read-write n 0x0 0x0 CRYP_CSGCM0R CRYP_CSGCM0R 0 32 read-write CRYP_CSGCM1R CRYP_CSGCM1R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x74 32 read-write n 0x0 0x0 CRYP_CSGCM1R CRYP_CSGCM1R 0 32 read-write CRYP_CSGCM2R CRYP_CSGCM2R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x78 32 read-write n 0x0 0x0 CRYP_CSGCM2R CRYP_CSGCM2R 0 32 read-write CRYP_CSGCM3R CRYP_CSGCM3R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x7C 32 read-write n 0x0 0x0 CRYP_CSGCM3R CRYP_CSGCM3R 0 32 read-write CRYP_CSGCM4R CRYP_CSGCM4R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x80 32 read-write n 0x0 0x0 CRYP_CSGCM4R CRYP_CSGCM4R 0 32 read-write CRYP_CSGCM5R CRYP_CSGCM5R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x84 32 read-write n 0x0 0x0 CRYP_CSGCM5R CRYP_CSGCM5R 0 32 read-write CRYP_CSGCM6R CRYP_CSGCM6R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x88 32 read-write n 0x0 0x0 CRYP_CSGCM6R CRYP_CSGCM6R 0 32 read-write CRYP_CSGCM7R CRYP_CSGCM7R Please refer to Section23.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details. 0x8C 32 read-write n 0x0 0x0 CRYP_CSGCM7R CRYP_CSGCM7R 0 32 read-write CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x50 32 read-write n 0x0 0x0 CRYP_CSGCMCCM0R CRYP_CSGCMCCM0R 0 32 read-write CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x54 32 read-write n 0x0 0x0 CRYP_CSGCMCCM1R CRYP_CSGCMCCM1R 0 32 read-write CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x58 32 read-write n 0x0 0x0 CRYP_CSGCMCCM2R CRYP_CSGCMCCM2R 0 32 read-write CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x5C 32 read-write n 0x0 0x0 CRYP_CSGCMCCM3R CRYP_CSGCMCCM3R 0 32 read-write CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x60 32 read-write n 0x0 0x0 CRYP_CSGCMCCM4R CRYP_CSGCMCCM4R 0 32 read-write CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x64 32 read-write n 0x0 0x0 CRYP_CSGCMCCM5R CRYP_CSGCMCCM5R 0 32 read-write CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x68 32 read-write n 0x0 0x0 CRYP_CSGCMCCM6R CRYP_CSGCMCCM6R 0 32 read-write CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers. 0x6C 32 read-write n 0x0 0x0 CRYP_CSGCMCCM7R CRYP_CSGCMCCM7R 0 32 read-write CRYP_DIN CRYP_DIN The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data. 0x8 32 read-write n 0x0 0x0 DATAIN DATAIN 0 32 read-write CRYP_DMACR CRYP_DMACR CRYP DMA control register 0x10 32 read-write n 0x0 0x0 DIEN DIEN 0 1 read-write DOEN DOEN 1 1 read-write CRYP_DOUT CRYP_DOUT The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section23.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned. 0xC 32 read-only n 0x0 0x0 DATAOUT DATAOUT 0 32 read-only CRYP_HWCFGR CRYP_HWCFGR CRYP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 read-only CFG2 CFG2 4 4 read-only CFG3 CFG3 8 4 read-only CFG4 CFG4 12 4 read-only CRYP_IMSCR CRYP_IMSCR The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset. 0x14 32 read-write n 0x0 0x0 INIM INIM 0 1 read-write OUTIM OUTIM 1 1 read-write CRYP_IPIDR CRYP_IPIDR CRYP Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only CRYP_IV0LR CRYP_IV0LR The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section23.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 0x40 32 read-write n 0x0 0x0 IV0 IV0 31 1 read-write IV1 IV1 30 1 read-write IV10 IV10 21 1 read-write IV11 IV11 20 1 read-write IV12 IV12 19 1 read-write IV13 IV13 18 1 read-write IV14 IV14 17 1 read-write IV15 IV15 16 1 read-write IV16 IV16 15 1 read-write IV17 IV17 14 1 read-write IV18 IV18 13 1 read-write IV19 IV19 12 1 read-write IV2 IV2 29 1 read-write IV20 IV20 11 1 read-write IV21 IV21 10 1 read-write IV22 IV22 9 1 read-write IV23 IV23 8 1 read-write IV24 IV24 7 1 read-write IV25 IV25 6 1 read-write IV26 IV26 5 1 read-write IV27 IV27 4 1 read-write IV28 IV28 3 1 read-write IV29 IV29 2 1 read-write IV3 IV3 28 1 read-write IV30 IV30 1 1 read-write IV31 IV31 0 1 read-write IV4 IV4 27 1 read-write IV5 IV5 26 1 read-write IV6 IV6 25 1 read-write IV7 IV7 24 1 read-write IV8 IV8 23 1 read-write IV9 IV9 22 1 read-write CRYP_IV0RR CRYP_IV0RR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x44 32 read-write n 0x0 0x0 IV32 IV32 31 1 read-write IV33 IV33 30 1 read-write IV34 IV34 29 1 read-write IV35 IV35 28 1 read-write IV36 IV36 27 1 read-write IV37 IV37 26 1 read-write IV38 IV38 25 1 read-write IV39 IV39 24 1 read-write IV40 IV40 23 1 read-write IV41 IV41 22 1 read-write IV42 IV42 21 1 read-write IV43 IV43 20 1 read-write IV44 IV44 19 1 read-write IV45 IV45 18 1 read-write IV46 IV46 17 1 read-write IV47 IV47 16 1 read-write IV48 IV48 15 1 read-write IV49 IV49 14 1 read-write IV50 IV50 13 1 read-write IV51 IV51 12 1 read-write IV52 IV52 11 1 read-write IV53 IV53 10 1 read-write IV54 IV54 9 1 read-write IV55 IV55 8 1 read-write IV56 IV56 7 1 read-write IV57 IV57 6 1 read-write IV58 IV58 5 1 read-write IV59 IV59 4 1 read-write IV60 IV60 3 1 read-write IV61 IV61 2 1 read-write IV62 IV62 1 1 read-write IV63 IV63 0 1 read-write CRYP_IV1LR CRYP_IV1LR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x48 32 read-write n 0x0 0x0 IV64 IV64 31 1 read-write IV65 IV65 30 1 read-write IV66 IV66 29 1 read-write IV67 IV67 28 1 read-write IV68 IV68 27 1 read-write IV69 IV69 26 1 read-write IV70 IV70 25 1 read-write IV71 IV71 24 1 read-write IV72 IV72 23 1 read-write IV73 IV73 22 1 read-write IV74 IV74 21 1 read-write IV75 IV75 20 1 read-write IV76 IV76 19 1 read-write IV77 IV77 18 1 read-write IV78 IV78 17 1 read-write IV79 IV79 16 1 read-write IV80 IV80 15 1 read-write IV81 IV81 14 1 read-write IV82 IV82 13 1 read-write IV83 IV83 12 1 read-write IV84 IV84 11 1 read-write IV85 IV85 10 1 read-write IV86 IV86 9 1 read-write IV87 IV87 8 1 read-write IV88 IV88 7 1 read-write IV89 IV89 6 1 read-write IV90 IV90 5 1 read-write IV91 IV91 4 1 read-write IV92 IV92 3 1 read-write IV93 IV93 2 1 read-write IV94 IV94 1 1 read-write IV95 IV95 0 1 read-write CRYP_IV1RR CRYP_IV1RR Refer to Section23.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details. 0x4C 32 read-write n 0x0 0x0 IV100 IV100 27 1 read-write IV101 IV101 26 1 read-write IV102 IV102 25 1 read-write IV103 IV103 24 1 read-write IV104 IV104 23 1 read-write IV105 IV105 22 1 read-write IV106 IV106 21 1 read-write IV107 IV107 20 1 read-write IV108 IV108 19 1 read-write IV109 IV109 18 1 read-write IV110 IV110 17 1 read-write IV111 IV111 16 1 read-write IV112 IV112 15 1 read-write IV113 IV113 14 1 read-write IV114 IV114 13 1 read-write IV115 IV115 12 1 read-write IV116 IV116 11 1 read-write IV117 IV117 10 1 read-write IV118 IV118 9 1 read-write IV119 IV119 8 1 read-write IV120 IV120 7 1 read-write IV121 IV121 6 1 read-write IV122 IV122 5 1 read-write IV123 IV123 4 1 read-write IV124 IV124 3 1 read-write IV125 IV125 2 1 read-write IV126 IV126 1 1 read-write IV127 IV127 0 1 read-write IV96 IV96 31 1 read-write IV97 IV97 30 1 read-write IV98 IV98 29 1 read-write IV99 IV99 28 1 read-write CRYP_K0LR CRYP_K0LR CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section23.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register) 0x20 32 write-only n 0x0 0x0 K224 K224 0 1 write-only K225 K225 1 1 write-only K226 K226 2 1 write-only K227 K227 3 1 write-only K228 K228 4 1 write-only K229 K229 5 1 write-only K230 K230 6 1 write-only K231 K231 7 1 write-only K232 K232 8 1 write-only K233 K233 9 1 write-only K234 K234 10 1 write-only K235 K235 11 1 write-only K236 K236 12 1 write-only K237 K237 13 1 write-only K238 K238 14 1 write-only K239 K239 15 1 write-only K240 K240 16 1 write-only K241 K241 17 1 write-only K242 K242 18 1 write-only K243 K243 19 1 write-only K244 K244 20 1 write-only K245 K245 21 1 write-only K246 K246 22 1 write-only K247 K247 23 1 write-only K248 K248 24 1 write-only K249 K249 25 1 write-only K250 K250 26 1 write-only K251 K251 27 1 write-only K252 K252 28 1 write-only K253 K253 29 1 write-only K254 K254 30 1 write-only K255 K255 31 1 write-only CRYP_K0RR CRYP_K0RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x24 32 write-only n 0x0 0x0 K192 K192 0 1 write-only K193 K193 1 1 write-only K194 K194 2 1 write-only K195 K195 3 1 write-only K196 K196 4 1 write-only K197 K197 5 1 write-only K198 K198 6 1 write-only K199 K199 7 1 write-only K200 K200 8 1 write-only K201 K201 9 1 write-only K202 K202 10 1 write-only K203 K203 11 1 write-only K204 K204 12 1 write-only K205 K205 13 1 write-only K206 K206 14 1 write-only K207 K207 15 1 write-only K208 K208 16 1 write-only K209 K209 17 1 write-only K210 K210 18 1 write-only K211 K211 19 1 write-only K212 K212 20 1 write-only K213 K213 21 1 write-only K214 K214 22 1 write-only K215 K215 23 1 write-only K216 K216 24 1 write-only K217 K217 25 1 write-only K218 K218 26 1 write-only K219 K219 27 1 write-only K220 K220 28 1 write-only K221 K221 29 1 write-only K222 K222 30 1 write-only K223 K223 31 1 write-only CRYP_K1LR CRYP_K1LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x28 32 write-only n 0x0 0x0 K160 K160 0 1 write-only K161 K161 1 1 write-only K162 K162 2 1 write-only K163 K163 3 1 write-only K164 K164 4 1 write-only K165 K165 5 1 write-only K166 K166 6 1 write-only K167 K167 7 1 write-only K168 K168 8 1 write-only K169 K169 9 1 write-only K170 K170 10 1 write-only K171 K171 11 1 write-only K172 K172 12 1 write-only K173 K173 13 1 write-only K174 K174 14 1 write-only K175 K175 15 1 write-only K176 K176 16 1 write-only K177 K177 17 1 write-only K178 K178 18 1 write-only K179 K179 19 1 write-only K180 K180 20 1 write-only K181 K181 21 1 write-only K182 K182 22 1 write-only K183 K183 23 1 write-only K184 K184 24 1 write-only K185 K185 25 1 write-only K186 K186 26 1 write-only K187 K187 27 1 write-only K188 K188 28 1 write-only K189 K189 29 1 write-only K190 K190 30 1 write-only K191 K191 31 1 write-only CRYP_K1RR CRYP_K1RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x2C 32 write-only n 0x0 0x0 K128 K128 0 1 write-only K129 K129 1 1 write-only K130 K130 2 1 write-only K131 K131 3 1 write-only K132 K132 4 1 write-only K133 K133 5 1 write-only K134 K134 6 1 write-only K135 K135 7 1 write-only K136 K136 8 1 write-only K137 K137 9 1 write-only K138 K138 10 1 write-only K139 K139 11 1 write-only K140 K140 12 1 write-only K141 K141 13 1 write-only K142 K142 14 1 write-only K143 K143 15 1 write-only K144 K144 16 1 write-only K145 K145 17 1 write-only K146 K146 18 1 write-only K147 K147 19 1 write-only K148 K148 20 1 write-only K149 K149 21 1 write-only K150 K150 22 1 write-only K151 K151 23 1 write-only K152 K152 24 1 write-only K153 K153 25 1 write-only K154 K154 26 1 write-only K155 K155 27 1 write-only K156 K156 28 1 write-only K157 K157 29 1 write-only K158 K158 30 1 write-only K159 K159 31 1 write-only CRYP_K2LR CRYP_K2LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x30 32 write-only n 0x0 0x0 K100 K100 4 1 write-only K101 K101 5 1 write-only K102 K102 6 1 write-only K103 K103 7 1 write-only K104 K104 8 1 write-only K105 K105 9 1 write-only K106 K106 10 1 write-only K107 K107 11 1 write-only K108 K108 12 1 write-only K109 K109 13 1 write-only K110 K110 14 1 write-only K111 K111 15 1 write-only K112 K112 16 1 write-only K113 K113 17 1 write-only K114 K114 18 1 write-only K115 K115 19 1 write-only K116 K116 20 1 write-only K117 K117 21 1 write-only K118 K118 22 1 write-only K119 K119 23 1 write-only K120 K120 24 1 write-only K121 K121 25 1 write-only K122 K122 26 1 write-only K123 K123 27 1 write-only K124 K124 28 1 write-only K125 K125 29 1 write-only K126 K126 30 1 write-only K127 K127 31 1 write-only K96 K96 0 1 write-only K97 K97 1 1 write-only K98 K98 2 1 write-only K99 K99 3 1 write-only CRYP_K2RR CRYP_K2RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x34 32 write-only n 0x0 0x0 K64 K64 0 1 write-only K65 K65 1 1 write-only K66 K66 2 1 write-only K67 K67 3 1 write-only K68 K68 4 1 write-only K69 K69 5 1 write-only K70 K70 6 1 write-only K71 K71 7 1 write-only K72 K72 8 1 write-only K73 K73 9 1 write-only K74 K74 10 1 write-only K75 K75 11 1 write-only K76 K76 12 1 write-only K77 K77 13 1 write-only K78 K78 14 1 write-only K79 K79 15 1 write-only K80 K80 16 1 write-only K81 K81 17 1 write-only K82 K82 18 1 write-only K83 K83 19 1 write-only K84 K84 20 1 write-only K85 K85 21 1 write-only K86 K86 22 1 write-only K87 K87 23 1 write-only K88 K88 24 1 write-only K89 K89 25 1 write-only K90 K90 26 1 write-only K91 K91 27 1 write-only K92 K92 28 1 write-only K93 K93 29 1 write-only K94 K94 30 1 write-only K95 K95 31 1 write-only CRYP_K3LR CRYP_K3LR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x38 32 write-only n 0x0 0x0 K32 K32 0 1 write-only K33 K33 1 1 write-only K34 K34 2 1 write-only K35 K35 3 1 write-only K36 K36 4 1 write-only K37 K37 5 1 write-only K38 K38 6 1 write-only K39 K39 7 1 write-only K40 K40 8 1 write-only K41 K41 9 1 write-only K42 K42 10 1 write-only K43 K43 11 1 write-only K44 K44 12 1 write-only K45 K45 13 1 write-only K46 K46 14 1 write-only K47 K47 15 1 write-only K48 K48 16 1 write-only K49 K49 17 1 write-only K50 K50 18 1 write-only K51 K51 19 1 write-only K52 K52 20 1 write-only K53 K53 21 1 write-only K54 K54 22 1 write-only K55 K55 23 1 write-only K56 K56 24 1 write-only K57 K57 25 1 write-only K58 K58 26 1 write-only K59 K59 27 1 write-only K60 K60 28 1 write-only K61 K61 29 1 write-only K62 K62 30 1 write-only K63 K63 31 1 write-only CRYP_K3RR CRYP_K3RR Refer to Section23.6.9: CRYP key register 0L (CRYP_K0LR) for details. 0x3C 32 write-only n 0x0 0x0 K0 K0 0 1 write-only K1 K1 1 1 write-only K10 K10 10 1 write-only K11 K11 11 1 write-only K12 K12 12 1 write-only K13 K13 13 1 write-only K14 K14 14 1 write-only K15 K15 15 1 write-only K16 K16 16 1 write-only K17 K17 17 1 write-only K18 K18 18 1 write-only K19 K19 19 1 write-only K2 K2 2 1 write-only K20 K20 20 1 write-only K21 K21 21 1 write-only K22 K22 22 1 write-only K23 K23 23 1 write-only K24 K24 24 1 write-only K25 K25 25 1 write-only K26 K26 26 1 write-only K27 K27 27 1 write-only K28 K28 28 1 write-only K29 K29 29 1 write-only K3 K3 3 1 write-only K30 K30 30 1 write-only K31 K31 31 1 write-only K4 K4 4 1 write-only K5 K5 5 1 write-only K6 K6 6 1 write-only K7 K7 7 1 write-only K8 K8 8 1 write-only K9 K9 9 1 write-only CRYP_MID CRYP_MID CRYP HW Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 read-only CRYP_MISR CRYP_MISR The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect. 0x1C 32 read-only n 0x0 0x0 INMIS INMIS 0 1 read-only OUTMIS OUTMIS 1 1 read-only CRYP_RISR CRYP_RISR The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect. 0x18 32 read-only n 0x0 0x0 INRIS INRIS 0 1 read-only OUTRIS OUTRIS 1 1 read-only CRYP_SR CRYP_SR CRYP status register 0x4 32 read-only n 0x0 0x0 BUSY BUSY 4 1 read-only IFEM IFEM 0 1 read-only IFNF IFNF 1 1 read-only OFFU OFFU 3 1 read-only OFNE OFNE 2 1 read-only CRYP_VERR CRYP_VERR CRYP HW Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 read-only DAC1 DAC1 DAC 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 OTRIM1 0 5 read-write OTRIM2 OTRIM2 16 5 read-write DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 CEN1 14 1 read-write CEN2 CEN2 30 1 read-write DMAEN1 DMAEN1 12 1 read-write DMAEN2 DMAEN2 28 1 read-write DMAUDRIE1 DMAUDRIE1 13 1 read-write DMAUDRIE2 DMAUDRIE2 29 1 read-write EN1 EN1 0 1 read-write EN2 EN2 16 1 read-write HFSEL HFSEL 15 1 read-write MAMP1 MAMP1 8 4 read-write MAMP2 MAMP2 24 4 read-write TEN1 TEN1 1 1 read-write TEN2 TEN2 17 1 read-write TSEL10 TSEL10 2 1 read-write TSEL11 TSEL11 3 1 read-write TSEL12 TSEL12 4 1 read-write TSEL13 TSEL13 5 1 read-write TSEL20 TSEL20 18 1 read-write TSEL21 TSEL21 19 1 read-write TSEL22 TSEL22 20 1 read-write TSEL23 TSEL23 21 1 read-write WAVE1 WAVE1 6 2 read-write WAVE2 WAVE2 22 2 read-write DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 4 12 read-write DAC_DHR12L2 DAC_DHR12L2 This register is available only on dual-channel DACs. Refer to Section1.3: DAC implementation. 0x18 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 4 12 read-write DAC_DHR12LD DAC_DHR12LD Dual DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 4 12 read-write DACC2DHR DACC2DHR 20 12 read-write DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 12 read-write DAC_DHR12R2 DAC_DHR12R2 This register is available only on dual-channel DACs. Refer to Section1.3: DAC implementation. 0x14 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 0 12 read-write DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 12 read-write DACC2DHR DACC2DHR 16 12 read-write DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 8 read-write DAC_DHR8R2 DAC_DHR8R2 This register is available only on dual-channel DACs. Refer to Section1.3: DAC implementation. 0x1C 32 read-write n 0x0 0x0 DACC2DHR DACC2DHR 0 8 read-write DAC_DHR8RD DAC_DHR8RD Dual DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DACC1DHR 0 8 read-write DACC2DHR DACC2DHR 8 8 read-write DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DACC1DOR 0 12 read-only DAC_DOR2 DAC_DOR2 This register is available only on dual-channel DACs. Refer to Section1.3: DAC implementation. 0x30 32 read-only n 0x0 0x0 DACC2DOR DACC2DOR 0 12 read-only DAC_IPIDR DAC_IPIDR DAC IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DAC_IP_HWCFGR0 DAC_IP_HWCFGR0 DAC IP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 DUAL DUAL 0 4 read-only LFSR LFSR 4 4 read-only OR_CFG OR_CFG 16 8 read-only SAMPLE SAMPLE 12 4 read-only TRIANGLE TRIANGLE 8 4 read-only DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 MODE1 MODE1 0 3 read-write MODE2 MODE2 16 3 read-write DAC_SHHR DAC_SHHR DAC sample and hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 THOLD1 0 10 read-write THOLD2 THOLD2 16 10 read-write DAC_SHRR DAC_SHRR DAC sample and hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 TREFRESH1 0 8 read-write TREFRESH2 TREFRESH2 16 8 read-write DAC_SHSR1 DAC_SHSR1 DAC channel 1 sample and hold sample time register 0x40 32 read-write n 0x0 0x0 TSAMPLE1 TSAMPLE1 0 10 read-write DAC_SHSR2 DAC_SHSR2 This register is available only on dual-channel DACs. Refer to Section1.3: DAC implementation. 0x44 32 read-write n 0x0 0x0 TSAMPLE2 TSAMPLE2 0 10 read-write DAC_SIDR DAC_SIDR DAC size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 BWST1 15 1 read-only BWST2 BWST2 31 1 read-only CAL_FLAG1 CAL_FLAG1 14 1 read-only CAL_FLAG2 CAL_FLAG2 30 1 read-only DMAUDR1 DMAUDR1 13 1 read-write DMAUDR2 DMAUDR2 29 1 read-write DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 read-write n 0x0 0x0 SWTRIG1 SWTRIG1 0 1 write-only SWTRIG2 SWTRIG2 1 1 write-only DAC_VERR DAC_VERR DAC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DCMI Digital camera interface DCMI 0x0 0x0 0x400 registers n DCMI DCMI global interrupt 78 CR DCMI_CR DCMI control register 0x0 32 read-write n 0x0 0x0 BSM BSM 16 2 read-write CAPTURE CAPTURE 0 1 read-write CM CM 1 1 read-write CROP CROP 2 1 read-write EDM EDM 10 2 read-write ENABLE ENABLE 14 1 read-write ESS ESS 4 1 read-write FCRC FCRC 8 2 read-write HSPOL HSPOL 6 1 read-write JPEG JPEG 3 1 read-write LSM LSM 19 1 read-write OEBS OEBS 18 1 read-write OELS OELS 20 1 read-write PCKPOL PCKPOL 5 1 read-write VSPOL VSPOL 7 1 read-write CWSIZE DCMI_CWSIZE DCMI crop window size 0x24 32 read-write n 0x0 0x0 CAPCNT CAPCNT 0 14 read-write VLINE VLINE 16 14 read-write CWSTRT DCMI_CWSTRT DCMI crop window start 0x20 32 read-write n 0x0 0x0 HOFFCNT HOFFCNT 0 14 read-write VST VST 16 13 read-write DR DCMI_DR DCMI data register 0x28 32 read-only n 0x0 0x0 Byte0 Byte0 0 8 read-only Byte1 Byte1 8 8 read-only Byte2 Byte2 16 8 read-only Byte3 Byte3 24 8 read-only ESCR DCMI_ESCR DCMI embedded synchronization code register 0x18 32 read-write n 0x0 0x0 FEC FEC 24 8 read-write FSC FSC 0 8 read-write LEC LEC 16 8 read-write LSC LSC 8 8 read-write ESUR DCMI_ESUR DCMI embedded synchronization unmask register 0x1C 32 read-write n 0x0 0x0 FEU FEU 24 8 read-write FSU FSU 0 8 read-write LEU LEU 16 8 read-write LSU LSU 8 8 read-write ICR DCMI_ICR The DCMI_ICR register is write-only 0x14 32 read-write n 0x0 0x0 ERR_ISC ERR_ISC 2 1 write-only FRAME_ISC FRAME_ISC 0 1 write-only LINE_ISC LINE_ISC 4 1 write-only OVR_ISC OVR_ISC 1 1 write-only VSYNC_ISC VSYNC_ISC 3 1 write-only IER DCMI_IER The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. 0xC 32 read-write n 0x0 0x0 ERR_IE ERR_IE 2 1 read-write FRAME_IE FRAME_IE 0 1 read-write LINE_IE LINE_IE 4 1 read-write OVR_IE OVR_IE 1 1 read-write VSYNC_IE VSYNC_IE 3 1 read-write MIS DCMI_MIS This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set. 0x10 32 read-only n 0x0 0x0 ERR_MIS ERR_MIS 2 1 read-only FRAME_MIS FRAME_MIS 0 1 read-only LINE_MIS LINE_MIS 4 1 read-only OVR_MIS OVR_MIS 1 1 read-only VSYNC_MIS VSYNC_MIS 3 1 read-only RIS DCMI_RIS DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value. 0x8 32 read-only n 0x0 0x0 ERR_RIS ERR_RIS 2 1 read-only FRAME_RIS FRAME_RIS 0 1 read-only LINE_RIS LINE_RIS 4 1 read-only OVR_RIS OVR_RIS 1 1 read-only VSYNC_RIS VSYNC_RIS 3 1 read-only SR DCMI_SR DCMI status register 0x4 32 read-only n 0x0 0x0 FNE FNE 2 1 read-only HSYNC HSYNC 0 1 read-only VSYNC VSYNC 1 1 read-only DDRCTRL DDRCTRL DDRCTRL 0x0 0x0 0x600 registers n ADDRMAP1 DDRCTRL_ADDRMAP1 DDRCTRL address map register 1 0x204 32 read-write n 0x0 0x0 ADDRMAP_BANK_B0 ADDRMAP_BANK_B0 0 6 read-write ADDRMAP_BANK_B1 ADDRMAP_BANK_B1 8 6 read-write ADDRMAP_BANK_B2 ADDRMAP_BANK_B2 16 6 read-write ADDRMAP10 DDRCTRL_ADDRMAP10 DDRCTRL address map register 10 0x228 32 read-write n 0x0 0x0 ADDRMAP_ROW_B6 ADDRMAP_ROW_B6 0 4 read-write ADDRMAP_ROW_B7 ADDRMAP_ROW_B7 8 4 read-write ADDRMAP_ROW_B8 ADDRMAP_ROW_B8 16 4 read-write ADDRMAP_ROW_B9 ADDRMAP_ROW_B9 24 4 read-write ADDRMAP11 DDRCTRL_ADDRMAP11 DDRCTRL address map register 11 0x22C 32 read-write n 0x0 0x0 ADDRMAP_ROW_B10 ADDRMAP_ROW_B10 0 4 read-write ADDRMAP2 DDRCTRL_ADDRMAP2 DDRCTRL address map register 2 0x208 32 read-write n 0x0 0x0 ADDRMAP_COL_B2 ADDRMAP_COL_B2 0 4 read-write ADDRMAP_COL_B3 ADDRMAP_COL_B3 8 4 read-write ADDRMAP_COL_B4 ADDRMAP_COL_B4 16 4 read-write ADDRMAP_COL_B5 ADDRMAP_COL_B5 24 4 read-write ADDRMAP3 DDRCTRL_ADDRMAP3 DDRCTRL address map register 3 0x20C 32 read-write n 0x0 0x0 ADDRMAP_COL_B6 ADDRMAP_COL_B6 0 4 read-write ADDRMAP_COL_B7 ADDRMAP_COL_B7 8 5 read-write ADDRMAP_COL_B8 ADDRMAP_COL_B8 16 5 read-write ADDRMAP_COL_B9 ADDRMAP_COL_B9 24 5 read-write ADDRMAP4 DDRCTRL_ADDRMAP4 DDRCTRL address map register 4 0x210 32 read-write n 0x0 0x0 ADDRMAP_COL_B10 ADDRMAP_COL_B10 0 5 read-write ADDRMAP_COL_B11 ADDRMAP_COL_B11 8 5 read-write ADDRMAP5 DDRCTRL_ADDRMAP5 DDRCTRL address map register 5 0x214 32 read-write n 0x0 0x0 ADDRMAP_ROW_B0 ADDRMAP_ROW_B0 0 4 read-write ADDRMAP_ROW_B1 ADDRMAP_ROW_B1 8 4 read-write ADDRMAP_ROW_B11 ADDRMAP_ROW_B11 24 4 read-write ADDRMAP_ROW_B2_10 ADDRMAP_ROW_B2_10 16 4 read-write ADDRMAP6 DDRCTRL_ADDRMAP6 DDRCTRL address register 6 0x218 32 read-write n 0x0 0x0 ADDRMAP_ROW_B12 ADDRMAP_ROW_B12 0 4 read-write ADDRMAP_ROW_B13 ADDRMAP_ROW_B13 8 4 read-write ADDRMAP_ROW_B14 ADDRMAP_ROW_B14 16 4 read-write ADDRMAP_ROW_B15 ADDRMAP_ROW_B15 24 4 read-write LPDDR3_6GB_12GB LPDDR3_6GB_12GB 31 1 read-write ADDRMAP9 DDRCTRL_ADDRMAP9 DDRCTRL address map register 9 0x224 32 read-write n 0x0 0x0 ADDRMAP_ROW_B2 ADDRMAP_ROW_B2 0 4 read-write ADDRMAP_ROW_B3 ADDRMAP_ROW_B3 8 4 read-write ADDRMAP_ROW_B4 ADDRMAP_ROW_B4 16 4 read-write ADDRMAP_ROW_B5 ADDRMAP_ROW_B5 24 4 read-write CRCPARCTL0 DDRCTRL_CRCPARCTL0 DDRCTRL CRC parity control register 0 0xC0 32 read-write n 0x0 0x0 DFI_ALERT_ERR_CNT_CLR DFI_ALERT_ERR_CNT_CLR 2 1 read-write DFI_ALERT_ERR_INT_CLR DFI_ALERT_ERR_INT_CLR 1 1 read-write DFI_ALERT_ERR_INT_EN DFI_ALERT_ERR_INT_EN 0 1 read-write CRCPARSTAT DDRCTRL_CRCPARSTAT DDRCTRL CRC parity status register 0xCC 32 read-only n 0x0 0x0 DFI_ALERT_ERR_CNT DFI_ALERT_ERR_CNT 0 16 read-only DFI_ALERT_ERR_INT DFI_ALERT_ERR_INT 16 1 read-only DBG0 DDRCTRL_DBG0 DDRCTRL debug register 0 0x300 32 read-write n 0x0 0x0 DIS_COLLISION_PAGE_OPT DIS_COLLISION_PAGE_OPT 4 1 read-write DIS_WC DIS_WC 0 1 read-write DBG1 DDRCTRL_DBG1 DDRCTRL debug register 1 0x304 32 read-write n 0x0 0x0 DIS_DQ DIS_DQ 0 1 read-write DIS_HIF DIS_HIF 1 1 read-write DBGCAM DDRCTRL_DBGCAM DDRCTRL CAM debug register 0x308 32 read-only n 0x0 0x0 DBG_HPR_Q_DEPTH DBG_HPR_Q_DEPTH 0 5 read-only DBG_LPR_Q_DEPTH DBG_LPR_Q_DEPTH 8 5 read-only DBG_RD_Q_EMPTY DBG_RD_Q_EMPTY 25 1 read-only DBG_STALL DBG_STALL 24 1 read-only DBG_WR_Q_EMPTY DBG_WR_Q_EMPTY 26 1 read-only DBG_W_Q_DEPTH DBG_W_Q_DEPTH 16 5 read-only RD_DATA_PIPELINE_EMPTY RD_DATA_PIPELINE_EMPTY 28 1 read-only WR_DATA_PIPELINE_EMPTY WR_DATA_PIPELINE_EMPTY 29 1 read-only DBGCMD DDRCTRL_DBGCMD DDRCTRL command debug register 0x30C 32 read-write n 0x0 0x0 CTRLUPD CTRLUPD 5 1 read-write RANK0_REFRESH RANK0_REFRESH 0 1 read-write ZQ_CALIB_SHORT ZQ_CALIB_SHORT 4 1 read-write DBGSTAT DDRCTRL_DBGSTAT DDRCTRL status debug register 0x310 32 read-only n 0x0 0x0 CTRLUPD_BUSY CTRLUPD_BUSY 5 1 read-only RANK0_REFRESH_BUSY RANK0_REFRESH_BUSY 0 1 read-only ZQ_CALIB_SHORT_BUSY ZQ_CALIB_SHORT_BUSY 4 1 read-only DERATEEN DDRCTRL_DERATEEN DDRCTRL temperature derate enable register 0x20 32 read-write n 0x0 0x0 DERATE_BYTE DERATE_BYTE 4 4 read-write DERATE_ENABLE DERATE_ENABLE 0 1 read-write DERATE_VALUE DERATE_VALUE 1 2 read-write DERATEINT DDRCTRL_DERATEINT DDRCTRL temperature derate interval register 0x24 32 read-write n 0x0 0x0 MR4_READ_INTERVAL MR4_READ_INTERVAL 0 32 read-write DFILPCFG0 DDRCTRL_DFILPCFG0 DDRCTRL low power configuration register 0 0x198 32 read-write n 0x0 0x0 DFI_LP_EN_DPD DFI_LP_EN_DPD 16 1 read-write DFI_LP_EN_PD DFI_LP_EN_PD 0 1 read-write DFI_LP_EN_SR DFI_LP_EN_SR 8 1 read-write DFI_LP_WAKEUP_DPD DFI_LP_WAKEUP_DPD 20 4 read-write DFI_LP_WAKEUP_PD DFI_LP_WAKEUP_PD 4 4 read-write DFI_LP_WAKEUP_SR DFI_LP_WAKEUP_SR 12 4 read-write DFI_TLP_RESP DFI_TLP_RESP 24 5 read-write DFIMISC DDRCTRL_DFIMISC DDRCTRL DFI miscellaneous control register 0x1B0 32 read-write n 0x0 0x0 CTL_IDLE_EN CTL_IDLE_EN 4 1 read-write DFI_FREQUENCY DFI_FREQUENCY 8 5 read-write DFI_INIT_COMPLETE_EN DFI_INIT_COMPLETE_EN 0 1 read-write DFI_INIT_START DFI_INIT_START 5 1 read-write DFIPHYMSTR DDRCTRL_DFIPHYMSTR DDRCTRL DFI PHY master register 0x1C4 32 read-write n 0x0 0x0 DFI_PHYMSTR_EN DFI_PHYMSTR_EN 0 1 read-write DFISTAT DDRCTRL_DFISTAT DDRCTRL DFI status register 0x1BC 32 read-only n 0x0 0x0 DFI_INIT_COMPLETE DFI_INIT_COMPLETE 0 1 read-only DFI_LP_ACK DFI_LP_ACK 1 1 read-only DFITMG0 DDRCTRL_DFITMG0 DDRCTRL DFI timing register 0 0x190 32 read-write n 0x0 0x0 DFI_TPHY_WRDATA DFI_TPHY_WRDATA 8 6 read-write DFI_TPHY_WRLAT DFI_TPHY_WRLAT 0 6 read-write DFI_T_CTRL_DELAY DFI_T_CTRL_DELAY 24 5 read-write DFI_T_RDDATA_EN DFI_T_RDDATA_EN 16 7 read-write DFITMG1 DDRCTRL_DFITMG1 DDRCTRL DFI timing register 1 0x194 32 read-write n 0x0 0x0 DFI_T_DRAM_CLK_DISABLE DFI_T_DRAM_CLK_DISABLE 8 5 read-write DFI_T_DRAM_CLK_ENABLE DFI_T_DRAM_CLK_ENABLE 0 5 read-write DFI_T_WRDATA_DELAY DFI_T_WRDATA_DELAY 16 5 read-write DFIUPD0 DDRCTRL_DFIUPD0 DDRCTRL DFI update register 0 0x1A0 32 read-write n 0x0 0x0 CTRLUPD_PRE_SRX CTRLUPD_PRE_SRX 29 1 read-write DFI_T_CTRLUP_MAX DFI_T_CTRLUP_MAX 16 10 read-write DFI_T_CTRLUP_MIN DFI_T_CTRLUP_MIN 0 10 read-write DIS_AUTO_CTRLUPD DIS_AUTO_CTRLUPD 31 1 read-write DIS_AUTO_CTRLUPD_SRX DIS_AUTO_CTRLUPD_SRX 30 1 read-write DFIUPD1 DDRCTRL_DFIUPD1 DDRCTRL DFI update register 1 0x1A4 32 read-write n 0x0 0x0 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0 8 read-write DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DFI_T_CTRLUPD_INTERVAL_MIN_X1024 16 8 read-write DFIUPD2 DDRCTRL_DFIUPD2 DDRCTRL DFI update register 2 0x1A8 32 read-write n 0x0 0x0 DFI_PHYUPD_EN DFI_PHYUPD_EN 31 1 read-write DIMMCTL DDRCTRL_DIMMCTL DDRCTRL DIMM control register 0xF0 32 read-write n 0x0 0x0 DIMM_ADDR_MIRR_EN DIMM_ADDR_MIRR_EN 1 1 read-write DIMM_STAGGER_CS_EN DIMM_STAGGER_CS_EN 0 1 read-write DRAMTMG0 DDRCTRL_DRAMTMG0 DDRCTRL SDRAM timing register 0 0x100 32 read-write n 0x0 0x0 T_FAW T_FAW 16 6 read-write T_RAS_MAX T_RAS_MAX 8 7 read-write T_RAS_MIN T_RAS_MIN 0 6 read-write WR2PRE WR2PRE 24 7 read-write DRAMTMG1 DDRCTRL_DRAMTMG1 DDRCTRL SDRAM timing register 1 0x104 32 read-write n 0x0 0x0 RD2PRE RD2PRE 8 6 read-write T_RC T_RC 0 7 read-write T_XP T_XP 16 5 read-write DRAMTMG14 DDRCTRL_DRAMTMG14 DDRCTRL SDRAM timing register 14 0x138 32 read-write n 0x0 0x0 T_XSR T_XSR 0 12 read-write DRAMTMG15 DDRCTRL_DRAMTMG15 DDRCTRL SDRAM timing register 15 0x13C 32 read-write n 0x0 0x0 EN_DFI_LP_T_STAB EN_DFI_LP_T_STAB 31 1 read-write T_STAB_X32 T_STAB_X32 0 8 read-write DRAMTMG2 DDRCTRL_DRAMTMG2 DDRCTRL SDRAM timing register 2 0x108 32 read-write n 0x0 0x0 RD2WR RD2WR 8 6 read-write READ_LATENCY READ_LATENCY 16 6 read-write WR2RD WR2RD 0 6 read-write WRITE_LATENCY WRITE_LATENCY 24 6 read-write DRAMTMG3 DDRCTRL_DRAMTMG3 DDRCTRL SDRAM timing register 3 0x10C 32 read-write n 0x0 0x0 T_MOD T_MOD 0 10 read-write T_MRD T_MRD 12 6 read-write T_MRW T_MRW 20 10 read-write DRAMTMG4 DDRCTRL_DRAMTMG4 DDRCTRL SDRAM timing register 4 0x110 32 read-write n 0x0 0x0 T_CCD T_CCD 16 4 read-write T_RCD T_RCD 24 5 read-write T_RP T_RP 0 5 read-write T_RRD T_RRD 8 4 read-write DRAMTMG5 DDRCTRL_DRAMTMG5 DDRCTRL SDRAM timing register 5 0x114 32 read-write n 0x0 0x0 T_CKE T_CKE 0 5 read-write T_CKESR T_CKESR 8 6 read-write T_CKSRE T_CKSRE 16 4 read-write T_CKSRX T_CKSRX 24 4 read-write DRAMTMG6 DDRCTRL_DRAMTMG6 DDRCTRL SDRAM timing register 6 0x118 32 read-write n 0x0 0x0 T_CKCSX T_CKCSX 0 4 read-write T_CKDPDE T_CKDPDE 24 4 read-write T_CKDPDX T_CKDPDX 16 4 read-write DRAMTMG7 DDRCTRL_DRAMTMG7 DDRCTRL SDRAM timing register 7 0x11C 32 read-write n 0x0 0x0 T_CKPDE T_CKPDE 8 4 read-write T_CKPDX T_CKPDX 0 4 read-write DRAMTMG8 DDRCTRL_DRAMTMG8 DDRCTRL SDRAM timing register 8 0x120 32 read-write n 0x0 0x0 T_XS_DLL_X32 T_XS_DLL_X32 8 7 read-write T_XS_X32 T_XS_X32 0 7 read-write HWLPCTL DDRCTRL_HWLPCTL DDRCTRL hardware low power control register 0x38 32 read-write n 0x0 0x0 HW_LP_EN HW_LP_EN 0 1 read-write HW_LP_EXIT_IDLE_EN HW_LP_EXIT_IDLE_EN 1 1 read-write HW_LP_IDLE_X32 HW_LP_IDLE_X32 16 12 read-write INIT0 DDRCTRL_INIT0 DDRCTRL SDRAM initialization register 0 0xD0 32 read-write n 0x0 0x0 POST_CKE_X1024 POST_CKE_X1024 16 10 read-write PRE_CKE_X1024 PRE_CKE_X1024 0 12 read-write SKIP_DRAM_INIT SKIP_DRAM_INIT 30 2 read-write INIT1 DDRCTRL_INIT1 DDRCTRL SDRAM initialization register 1 0xD4 32 read-write n 0x0 0x0 DRAM_RSTN_X1024 DRAM_RSTN_X1024 16 9 read-write PRE_OCD_X32 PRE_OCD_X32 0 4 read-write INIT2 DDRCTRL_INIT2 DDRCTRL SDRAM initialization register 2 0xD8 32 read-write n 0x0 0x0 IDLE_AFTER_RESET_X32 IDLE_AFTER_RESET_X32 8 8 read-write MIN_STABLE_CLOCK_X1 MIN_STABLE_CLOCK_X1 0 4 read-write INIT3 DDRCTRL_INIT3 DDRCTRL SDRAM initialization register 3 0xDC 32 read-write n 0x0 0x0 EMR EMR 0 16 read-write MR MR 16 16 read-write INIT4 DDRCTRL_INIT4 DDRCTRL SDRAM initialization register 4 0xE0 32 read-write n 0x0 0x0 EMR2 EMR2 16 16 read-write EMR3 EMR3 0 16 read-write INIT5 DDRCTRL_INIT5 DDRCTRL SDRAM initialization register 5 0xE4 32 read-write n 0x0 0x0 DEV_ZQINIT_X32 DEV_ZQINIT_X32 16 8 read-write MAX_AUTO_INIT_X1024 MAX_AUTO_INIT_X1024 0 10 read-write MRCTRL0 DDRCTRL_MRCTRL0 Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en 0x10 32 read-write n 0x0 0x0 MR_ADDR MR_ADDR 12 4 read-write MR_RANK MR_RANK 4 1 read-write MR_TYPE MR_TYPE 0 1 read-write MR_WR MR_WR 31 1 read-write MRCTRL1 DDRCTRL_MRCTRL1 DDRCTRL mode register read/write control register 1 0x14 32 read-write n 0x0 0x0 MR_DATA MR_DATA 0 16 read-write MRSTAT DDRCTRL_MRSTAT DDRCTRL mode register read/write status register 0x18 32 read-only n 0x0 0x0 MR_WR_BUSY MR_WR_BUSY 0 1 read-only MSTR DDRCTRL_MSTR DDRCTRL master register 0 0x0 32 read-write n 0x0 0x0 BURSTCHOP BURSTCHOP 9 1 read-write BURST_RDWR BURST_RDWR 16 4 read-write DATA_BUS_WIDTH DATA_BUS_WIDTH 12 2 read-write DDR3 DDR3 0 1 read-write DLL_OFF_MODE DLL_OFF_MODE 15 1 read-write EN_2T_TIMING_MODE EN_2T_TIMING_MODE 10 1 read-write LPDDR2 LPDDR2 2 1 read-write LPDDR3 LPDDR3 3 1 read-write ODTCFG DDRCTRL_ODTCFG DDRCTRL ODT configuration register 0x240 32 read-write n 0x0 0x0 RD_ODT_DELAY RD_ODT_DELAY 2 5 read-write RD_ODT_HOLD RD_ODT_HOLD 8 4 read-write WR_ODT_DELAY WR_ODT_DELAY 16 5 read-write WR_ODT_HOLD WR_ODT_HOLD 24 4 read-write ODTMAP DDRCTRL_ODTMAP DDRCTRL ODT/Rank map register 0x244 32 read-write n 0x0 0x0 RANK0_RD_ODT RANK0_RD_ODT 4 1 read-write RANK0_WR_ODT RANK0_WR_ODT 0 1 read-write PCCFG DDRCTRL_PCCFG DDRCTRL port common configuration register 0x400 32 read-write n 0x0 0x0 BL_EXP_MODE BL_EXP_MODE 8 1 read-write GO2CRITICAL_EN GO2CRITICAL_EN 0 1 read-write PAGEMATCH_LIMIT PAGEMATCH_LIMIT 4 1 read-write PCFGQOS0_0 DDRCTRL_PCFGQOS0_0 DDRCTRL port n read Q0S configuration register 0 0x494 32 read-write n 0x0 0x0 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 read-write RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 read-write RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 read-write B_0x0 LPR and 1: VPR only. 0x0 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 read-write B_0x0 LPR and 1: VPR only. 0x0 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 read-write PCFGQOS0_1 DDRCTRL_PCFGQOS0_1 DDRCTRL port n read Q0S configuration register 0 0x544 32 read-write n 0x0 0x0 RQOS_MAP_LEVEL1 RQOS_MAP_LEVEL1 0 4 read-write RQOS_MAP_LEVEL2 RQOS_MAP_LEVEL2 8 4 read-write RQOS_MAP_REGION0 RQOS_MAP_REGION0 16 2 read-write B_0x0 LPR and 1: VPR only. 0x0 RQOS_MAP_REGION1 RQOS_MAP_REGION1 20 2 read-write B_0x0 LPR and 1: VPR only. 0x0 RQOS_MAP_REGION2 RQOS_MAP_REGION2 24 2 read-write PCFGQOS1_0 DDRCTRL_PCFGQOS1_0 DDRCTRL port n read Q0S configuration register 1 0x498 32 read-write n 0x0 0x0 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 read-write RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 read-write PCFGQOS1_1 DDRCTRL_PCFGQOS1_1 DDRCTRL port n read Q0S configuration register 1 0x548 32 read-write n 0x0 0x0 RQOS_MAP_TIMEOUTB RQOS_MAP_TIMEOUTB 0 11 read-write RQOS_MAP_TIMEOUTR RQOS_MAP_TIMEOUTR 16 11 read-write PCFGR_0 DDRCTRL_PCFGR_0 DDRCTRL port n configuration read register 0x404 32 read-write n 0x0 0x0 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 read-write RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 read-write RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 read-write RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 read-write RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 read-write PCFGR_1 DDRCTRL_PCFGR_1 DDRCTRL port n configuration read register 0x4B4 32 read-write n 0x0 0x0 RDWR_ORDERED_EN RDWR_ORDERED_EN 16 1 read-write RD_PORT_AGING_EN RD_PORT_AGING_EN 12 1 read-write RD_PORT_PAGEMATCH_EN RD_PORT_PAGEMATCH_EN 14 1 read-write RD_PORT_PRIORITY RD_PORT_PRIORITY 0 10 read-write RD_PORT_URGENT_EN RD_PORT_URGENT_EN 13 1 read-write PCFGWQOS0_0 DDRCTRL_PCFGWQOS0_0 DDRCTRL port n write Q0S configuration register 0 0x49C 32 read-write n 0x0 0x0 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 read-write WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 read-write WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 read-write B_0x0 NPW, 1: VPW. 0x0 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 read-write B_0x0 NPW, 1: VPW. 0x0 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 read-write B_0x0 NPW, 1: VPW. 0x0 PCFGWQOS0_1 DDRCTRL_PCFGWQOS0_1 DDRCTRL port n write Q0S configuration register 0 0x54C 32 read-write n 0x0 0x0 WQOS_MAP_LEVEL1 WQOS_MAP_LEVEL1 0 4 read-write WQOS_MAP_LEVEL2 WQOS_MAP_LEVEL2 8 4 read-write WQOS_MAP_REGION0 WQOS_MAP_REGION0 16 2 read-write B_0x0 NPW, 1: VPW. 0x0 WQOS_MAP_REGION1 WQOS_MAP_REGION1 20 2 read-write B_0x0 NPW, 1: VPW. 0x0 WQOS_MAP_REGION2 WQOS_MAP_REGION2 24 2 read-write B_0x0 NPW, 1: VPW. 0x0 PCFGWQOS1_0 DDRCTRL_PCFGWQOS1_0 DDRCTRL port n write Q0S configuration register 1 0x4A0 32 read-write n 0x0 0x0 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 read-write WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 read-write PCFGWQOS1_1 DDRCTRL_PCFGWQOS1_1 DDRCTRL port n write Q0S configuration register 1 0x550 32 read-write n 0x0 0x0 WQOS_MAP_TIMEOUT1 WQOS_MAP_TIMEOUT1 0 11 read-write WQOS_MAP_TIMEOUT2 WQOS_MAP_TIMEOUT2 16 11 read-write PCFGW_0 DDRCTRL_PCFGW_0 DDRCTRL port n configuration write register 0x408 32 read-write n 0x0 0x0 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 read-write WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 read-write WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 read-write WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 read-write PCFGW_1 DDRCTRL_PCFGW_1 DDRCTRL port n configuration write register 0x4B8 32 read-write n 0x0 0x0 WR_PORT_AGING_EN WR_PORT_AGING_EN 12 1 read-write WR_PORT_PAGEMATCH_EN WR_PORT_PAGEMATCH_EN 14 1 read-write WR_PORT_PRIORITY WR_PORT_PRIORITY 0 10 read-write WR_PORT_URGENT_EN WR_PORT_URGENT_EN 13 1 read-write PCTRL_0 DDRCTRL_PCTRL_0 DDRCTRL port n control register 0x490 32 read-write n 0x0 0x0 PORT_EN PORT_EN 0 1 read-write PCTRL_1 DDRCTRL_PCTRL_1 DDRCTRL port n control register 0x540 32 read-write n 0x0 0x0 PORT_EN PORT_EN 0 1 read-write PERFHPR1 DDRCTRL_PERFHPR1 DDRCTRL high priority read CAM register 1 0x25C 32 read-write n 0x0 0x0 HPR_MAX_STARVE HPR_MAX_STARVE 0 16 read-write HPR_XACT_RUN_LENGTH HPR_XACT_RUN_LENGTH 24 8 read-write PERFLPR1 DDRCTRL_PERFLPR1 DDRCTRL low priority read CAM register 1 0x264 32 read-write n 0x0 0x0 LPR_MAX_STARVE LPR_MAX_STARVE 0 16 read-write LPR_XACT_RUN_LENGTH LPR_XACT_RUN_LENGTH 24 8 read-write PERFWR1 DDRCTRL_PERFWR1 DDRCTRL write CAM register 1 0x26C 32 read-write n 0x0 0x0 W_MAX_STARVE W_MAX_STARVE 0 16 read-write W_XACT_RUN_LENGTH W_XACT_RUN_LENGTH 24 8 read-write POISONCFG DDRCTRL_POISONCFG AXI Poison configuration register common for all AXI ports. 0x36C 32 read-write n 0x0 0x0 RD_POISON_INTR_CLR RD_POISON_INTR_CLR 24 1 read-write RD_POISON_INTR_EN RD_POISON_INTR_EN 20 1 read-write RD_POISON_SLVERR_EN RD_POISON_SLVERR_EN 16 1 read-write WR_POISON_INTR_CLR WR_POISON_INTR_CLR 8 1 read-write WR_POISON_INTR_EN WR_POISON_INTR_EN 4 1 read-write WR_POISON_SLVERR_EN WR_POISON_SLVERR_EN 0 1 read-write POISONSTAT DDRCTRL_POISONSTAT DDRCTRL AXI Poison status register 0x370 32 read-only n 0x0 0x0 RD_POISON_INTR_0 RD_POISON_INTR_0 16 1 read-only RD_POISON_INTR_1 RD_POISON_INTR_1 17 1 read-only WR_POISON_INTR_0 WR_POISON_INTR_0 0 1 read-only WR_POISON_INTR_1 WR_POISON_INTR_1 1 1 read-only PSTAT DDRCTRL_PSTAT DDRCTRL port status register 0x3FC 32 read-only n 0x0 0x0 RD_PORT_BUSY_0 RD_PORT_BUSY_0 0 1 read-only RD_PORT_BUSY_1 RD_PORT_BUSY_1 1 1 read-only WR_PORT_BUSY_0 WR_PORT_BUSY_0 16 1 read-only WR_PORT_BUSY_1 WR_PORT_BUSY_1 17 1 read-only PWRCTL DDRCTRL_PWRCTL DDRCTRL low power control register 0x30 32 read-write n 0x0 0x0 DEEPPOWERDOWN_EN DEEPPOWERDOWN_EN 2 1 read-write DIS_CAM_DRAIN_SELFREF DIS_CAM_DRAIN_SELFREF 7 1 read-write EN_DFI_DRAM_CLK_DISABLE EN_DFI_DRAM_CLK_DISABLE 3 1 read-write POWERDOWN_EN POWERDOWN_EN 1 1 read-write SELFREF_EN SELFREF_EN 0 1 read-write SELFREF_SW SELFREF_SW 5 1 read-write PWRTMG DDRCTRL_PWRTMG DDRCTRL low power timing register 0x34 32 read-write n 0x0 0x0 POWERDOWN_TO_X32 POWERDOWN_TO_X32 0 5 read-write SELFREF_TO_X32 SELFREF_TO_X32 16 8 read-write T_DPD_X4096 T_DPD_X4096 8 8 read-write RFSHCTL0 DDRCTRL_RFSHCTL0 DDRCTRL refresh control register 0 0x50 32 read-write n 0x0 0x0 PER_BANK_REFRESH PER_BANK_REFRESH 2 1 read-write REFRESH_BURST REFRESH_BURST 4 5 read-write REFRESH_MARGIN REFRESH_MARGIN 20 4 read-write REFRESH_TO_X32 REFRESH_TO_X32 12 5 read-write RFSHCTL3 DDRCTRL_RFSHCTL3 DDRCTRL refresh control register 3 0x60 32 read-write n 0x0 0x0 DIS_AUTO_REFRESH DIS_AUTO_REFRESH 0 1 read-write REFRESH_UPDATE_LEVEL REFRESH_UPDATE_LEVEL 1 1 read-write RFSHTMG DDRCTRL_RFSHTMG DDRCTRL refresh timing register 0x64 32 read-write n 0x0 0x0 LPDDR3_TREFBW_EN LPDDR3_TREFBW_EN 15 1 read-write T_RFC_MIN T_RFC_MIN 0 10 read-write T_RFC_NOM_X1_SEL T_RFC_NOM_X1_SEL 31 1 read-write T_RFC_NOM_X1_X32 T_RFC_NOM_X1_X32 16 12 read-write SCHED DDRCTRL_SCHED DDRCTRL scheduler control register 0x250 32 read-write n 0x0 0x0 FORCE_LOW_PRI_N FORCE_LOW_PRI_N 0 1 read-write GO2CRITICAL_HYSTERESIS GO2CRITICAL_HYSTERESIS 16 8 read-write LPR_NUM_ENTRIES LPR_NUM_ENTRIES 8 4 read-write PAGECLOSE PAGECLOSE 2 1 read-write PREFER_WRITE PREFER_WRITE 1 1 read-write RDWR_IDLE_GAP RDWR_IDLE_GAP 24 7 read-write SCHED1 DDRCTRL_SCHED1 DDRCTRL scheduler control register 1 0x254 32 read-write n 0x0 0x0 PAGECLOSE_TIMER PAGECLOSE_TIMER 0 8 read-write STAT DDRCTRL_STAT DDRCTRL operating mode status register 0x4 32 read-only n 0x0 0x0 OPERATING_MODE OPERATING_MODE 0 3 read-only SELFREF_CAM_NOT_EMPTY SELFREF_CAM_NOT_EMPTY 12 1 read-only SELFREF_TYPE SELFREF_TYPE 4 2 read-only SWCTL DDRCTRL_SWCTL DDRCTRL software register programming control enable 0x320 32 read-write n 0x0 0x0 SW_DONE SW_DONE 0 1 read-write SWSTAT DDRCTRL_SWSTAT DDRCTRL software register programming control status 0x324 32 read-only n 0x0 0x0 SW_DONE_ACK SW_DONE_ACK 0 1 read-only ZQCTL0 DDRCTRL_ZQCTL0 DDRCTRL ZQ control register 0 0x180 32 read-write n 0x0 0x0 DIS_AUTO_ZQ DIS_AUTO_ZQ 31 1 read-write DIS_SRX_ZQCL DIS_SRX_ZQCL 30 1 read-write T_ZQ_LONG_NOP T_ZQ_LONG_NOP 16 11 read-write T_ZQ_SHORT_NOP T_ZQ_SHORT_NOP 0 10 read-write ZQ_RESISTOR_SHARED ZQ_RESISTOR_SHARED 29 1 read-write ZQCTL1 DDRCTRL_ZQCTL1 DDRCTRL ZQ control register 1 0x184 32 read-write n 0x0 0x0 T_ZQ_RESET_NOP T_ZQ_RESET_NOP 20 10 read-write T_ZQ_SHORT_INTERVAL_X1024 T_ZQ_SHORT_INTERVAL_X1024 0 20 read-write ZQCTL2 DDRCTRL_ZQCTL2 DDRCTRL ZQ control register 2 0x188 32 read-write n 0x0 0x0 ZQ_RESET ZQ_RESET 0 1 read-write ZQSTAT DDRCTRL_ZQSTAT DDRCTRL ZQ status register 0x18C 32 read-only n 0x0 0x0 ZQ_RESET_BUSY ZQ_RESET_BUSY 0 1 read-only DDRPERFM DDRPERFM DDRPERFM 0x0 0x0 0x400 registers n CCR DDRPERFM_CCR Write-only register. A read request returns all zeros 0xC 32 read-write n 0x0 0x0 CCLR CCLR 0 4 write-only TCLR TCLR 31 1 write-only CFG DDRPERFM_CFG DDRPERFM configurationl register 0x4 32 read-write n 0x0 0x0 EN EN 0 4 read-write SEL SEL 16 2 read-write CNT0 DDRPERFM_CNT0 DDRPERFM event counter 0 register 0x60 32 read-only n 0x0 0x0 CNT CNT 0 32 read-only CNT1 DDRPERFM_CNT1 DDRPERFM event counter 1 register 0x68 32 read-only n 0x0 0x0 CNT CNT 0 32 read-only CNT2 DDRPERFM_CNT2 DDRPERFM event counter 2 register 0x70 32 read-only n 0x0 0x0 CNT CNT 0 32 read-only CNT3 DDRPERFM_CNT3 DDRPERFM event counter 3 register 0x78 32 read-only n 0x0 0x0 CNT CNT 0 32 read-only CTL DDRPERFM_CTL Write-only register. A read request returns all zeros. 0x0 32 read-write n 0x0 0x0 START START 0 1 write-only STOP STOP 1 1 write-only HWCFG DDRPERFM_HWCFG DDRPERFM hardware configuration register 0x3F0 32 read-only n 0x0 0x0 NCNT NCNT 0 4 read-only ICR DDRPERFM_ICR Write-only register. A read request returns all zeros 0x18 32 read-write n 0x0 0x0 OVF OVF 0 1 write-only ID DDRPERFM_ID DDRPERFM ID register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only IER DDRPERFM_IER DDRPERFM interrupt enable register 0x10 32 read-write n 0x0 0x0 OVFIE OVFIE 0 1 read-write ISR DDRPERFM_ISR DDRPERFM interrupt status register 0x14 32 read-only n 0x0 0x0 OVFF OVFF 0 1 read-only SID DDRPERFM_SID DDRPERFM magic ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only STATUS DDRPERFM_STATUS DDRPERFM status register 0x8 32 read-only n 0x0 0x0 BUSY BUSY 16 1 read-only COVF COVF 0 4 read-only TOVF TOVF 31 1 read-only TCNT DDRPERFM_TCNT DDRPERFM time counter register 0x20 32 read-only n 0x0 0x0 CNT CNT 0 32 read-only VER DDRPERFM_VER DDRPERFM version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DDRPHYC DDRPHYC DDRPHYC 0x0 0x0 0x298 registers n ACDLLCR DDRPHYC_ACDLLCR ACDLLCR register 0x14 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 read-write DLLDIS DLLDIS 31 1 read-write DLLSRST DLLSRST 30 1 read-write MFBDLY MFBDLY 6 3 read-write MFWDLY MFWDLY 9 3 read-write ACIOCR DDRPHYC_ACIOCR ACIOCR register 0x24 32 read-write n 0x0 0x0 ACIOM ACIOM 0 1 read-write ACODT ACODT 2 1 read-write ACOE ACOE 1 1 read-write ACPDD ACPDD 3 1 read-write ACPDR ACPDR 4 1 read-write ACSR ACSR 30 2 read-write CKODT CKODT 5 3 read-write CKPDD CKPDD 8 3 read-write CKPDR CKPDR 11 3 read-write CSPDD CSPDD 18 1 read-write RANKODT RANKODT 14 1 read-write RANKPDR RANKPDR 22 1 read-write RSTIOM RSTIOM 29 1 read-write RSTODT RSTODT 26 1 read-write RSTPDD RSTPDD 27 1 read-write RSTPDR RSTPDR 28 1 read-write BISTAR0 DDRPHYC_BISTAR0 BISTAR0 register 0x114 32 read-write n 0x0 0x0 BBANK BBANK 28 4 read-write BCOL BCOL 0 12 read-write BROW BROW 12 16 read-write BISTAR1 DDRPHYC_BISTAR1 BISTAR1 register 0x118 16 read-write n 0x0 0x0 BAINC BAINC 4 12 read-write BMRANK BMRANK 2 2 read-write BRANK BRANK 0 2 read-write BISTAR2 DDRPHYC_BISTAR2 BISTAR2 register 0x11C 32 read-write n 0x0 0x0 BMBANK BMBANK 28 4 read-write BMCOL BMCOL 0 12 read-write BMROW BMROW 12 16 read-write BISTBER0 DDRPHYC_BISTBER0 BISTBER0 register 0x12C 32 read-only n 0x0 0x0 ABER ABER 0 32 read-only BISTBER1 DDRPHYC_BISTBER1 BISTBER1 register 0x130 32 read-only n 0x0 0x0 BABER BABER 0 6 read-only CKEBER CKEBER 8 8 read-only CSBER CSBER 16 8 read-only ODTBER ODTBER 24 8 read-only WEBER WEBER 6 2 read-only BISTBER2 DDRPHYC_BISTBER2 BISTBER2 register 0x134 32 read-only n 0x0 0x0 DQBER DQBER 0 32 read-only BISTFWR0 DDRPHYC_BISTFWR0 BISTFWR0 register 0x13C 32 read-only n 0x0 0x0 AWEBS AWEBS 0 16 read-only BAWEBS BAWEBS 16 3 read-only CKEWEBS CKEWEBS 20 4 read-only CSWEBS CSWEBS 24 4 read-only ODTWEBS ODTWEBS 28 4 read-only WEWEBS WEWEBS 19 1 read-only BISTFWR1 DDRPHYC_BISTFWR1 BISTFWR1 register 0x140 32 read-only n 0x0 0x0 CASWEBS CASWEBS 19 1 read-only DMWEBS DMWEBS 16 2 read-only DQWEBS DQWEBS 0 16 read-only PARWEBS PARWEBS 30 1 read-only RASWEBS RASWEBS 18 1 read-only TPDWEBS TPDWEBS 31 1 read-only BISTGSR DDRPHYC_BISTGSR BISTGSR register 0x124 32 read-only n 0x0 0x0 BACERR BACERR 1 1 read-only BDONE BDONE 0 1 read-only BDXERR BDXERR 2 1 read-only CASBER CASBER 30 2 read-only DMBER DMBER 24 4 read-only PARBER PARBER 20 2 read-only RASBER RASBER 28 2 read-only TPDBER TPDBER 22 2 read-only BISTLSR DDRPHYC_BISTLSR BISTLSR register 0x110 32 read-write n 0x0 0x0 BISTLSR BISTLSR 0 32 read-write BISTMSKR0 DDRPHYC_BISTMSKR0 BISTMSKR0 register 0x104 32 read-write n 0x0 0x0 AMSK AMSK 0 16 read-write BAMSK BAMSK 16 3 read-write CKEMSK CKEMSK 20 4 read-write CSMSK CSMSK 24 4 read-write ODTMSK ODTMSK 28 4 read-write WEMSK WEMSK 19 1 read-write BISTMSKR1 DDRPHYC_BISTMSKR1 BISTMSKR1 register 0x108 32 read-write n 0x0 0x0 CASMSK CASMSK 19 1 read-write DMMSK DMMSK 16 2 read-write DQMSK DQMSK 0 16 read-write PARMSK PARMSK 30 1 read-write RASMSK RASMSK 18 1 read-write TPDMASK TPDMASK 31 1 read-write BISTRR DDRPHYC_BISTRR BISTRR register 0x100 32 read-write n 0x0 0x0 BACEN BACEN 15 1 read-write BCKSEL BCKSEL 23 3 read-write BDMEN BDMEN 16 1 read-write BDPAT BDPAT 17 2 read-write BDXEN BDXEN 14 1 read-write BDXSEL BDXSEL 19 4 read-write BINF BINF 4 1 read-write BINST BINST 0 3 read-write BMODE BMODE 3 1 read-write BSCONF BSCONF 13 1 read-write NFAIL NFAIL 5 8 read-write BISTUDPR DDRPHYC_BISTUDPR BISTUDPR register 0x120 32 read-write n 0x0 0x0 BUDP0 BUDP0 0 16 read-write BUDP1 BUDP1 16 16 read-write BISTWCR DDRPHYC_BISTWCR BISTWCR register 0x10C 16 read-write n 0x0 0x0 BWCNT BWCNT 0 16 read-write BISTWCSR DDRPHYC_BISTWCSR BISTWCSR register 0x138 32 read-only n 0x0 0x0 ACWCNT ACWCNT 0 16 read-only DXWCNT DXWCNT 16 16 read-only BISTWER DDRPHYC_BISTWER BISTWER register 0x128 32 read-only n 0x0 0x0 ACWER ACWER 0 16 read-only DXWER DXWER 16 16 read-only DCR DDRPHYC_DCR DCR register 0x30 32 read-write n 0x0 0x0 DDR2T DDR2T 28 1 read-write DDR8BNK DDR8BNK 3 1 read-write DDRMD DDRMD 0 3 read-write DDRTYPE DDRTYPE 8 2 read-write MPRDQ MPRDQ 7 1 read-write NOSRA NOSRA 27 1 read-write PDQ PDQ 4 3 read-write RDIMM RDIMM 30 1 read-write TPD TPD 31 1 read-write UDIMM UDIMM 29 1 read-write DCUAR DDRPHYC_DCUAR DCUAR register 0xC0 16 read-write n 0x0 0x0 ATYPE ATYPE 11 1 read-write B_0x0 Write access 0x0 B_0x1 Read access 0x1 CSADDR CSADDR 4 4 read-write CSEL CSEL 8 2 read-write B_0x0 Command cache 0x0 B_0x1 Expected data cache 0x1 B_0x2 Read data cache 0x2 CWADDR CWADDR 0 4 read-write INCA INCA 10 1 read-write DCUDR DDRPHYC_DCUDR DCUDR register 0xC4 32 read-write n 0x0 0x0 CDATA CDATA 0 32 read-write DCUGCR DDRPHYC_DCUGCR DCUGCR register 0xD0 16 read-write n 0x0 0x0 RCSW RCSW 0 16 read-write DCULR DDRPHYC_DCULR DCULR register 0xCC 32 read-write n 0x0 0x0 IDA IDA 17 1 read-write LCNT LCNT 8 8 read-write LEADDR LEADDR 4 4 read-write LFINF LFINF 16 1 read-write LSADDR LSADDR 0 4 read-write XLEADDR XLEADDR 28 4 read-write DCURR DDRPHYC_DCURR DCURR register 0xC8 32 read-write n 0x0 0x0 DINST DINST 0 4 read-write EADDR EADDR 8 4 read-write NFAIL NFAIL 12 8 read-write RCEN RCEN 22 1 read-write SADDR SADDR 4 4 read-write SCOF SCOF 21 1 read-write SONF SONF 20 1 read-write XCEN XCEN 23 1 read-write DCUSR0 DDRPHYC_DCUSR0 DCUSR0 register 0xD8 8 read-only n 0x0 0x0 CFAIL CFAIL 1 1 read-only CFULL CFULL 2 1 read-only RDONE RDONE 0 1 read-only DCUSR1 DDRPHYC_DCUSR1 DCUSR1 register 0xDC 32 read-only n 0x0 0x0 FLCND FLCND 16 8 read-only LPCNT LPCNT 24 8 read-only RDCNT RDCNT 0 16 read-only DCUTPR DDRPHYC_DCUTPR DCUTPR register 0xD4 32 read-write n 0x0 0x0 TDCUT1 TDCUT1 8 8 read-write TDCUT2 TDCUT2 16 8 read-write TDCUT3 TDCUT3 24 8 read-write TDCUTO TDCUTO 0 8 read-write DLLGCR DDRPHYC_DLLGCR DLLGCR register 0x10 32 read-write n 0x0 0x0 ATC ATC 9 2 read-write BPS200 BPS200 23 1 read-write DLLRSVD2 DLLRSVD2 30 2 read-write DRES DRES 0 2 read-write DTC DTC 6 3 read-write FDTRMSL FDTRMSL 27 2 read-write B_0x0 Nominal delay 0x0 B_0x1 Nominal delay less 10 0x1 B_0x2 Nominal delay more 10 0x2 B_0x3 Nominal delay more 20 0x3 IPUMP IPUMP 2 3 read-write LOCKDET LOCKDET 29 1 read-write MBIAS MBIAS 12 8 read-write SBIAS2_0 SBIAS2_0 20 3 read-write SBIAS5_3 SBIAS5_3 24 3 read-write TESTEN TESTEN 5 1 read-write TESTSW TESTSW 11 1 read-write DSGCR DDRPHYC_DSGCR DSGCR register 0x2C 32 read-write n 0x0 0x0 BDISEN BDISEN 1 1 read-write CKEOE CKEOE 31 1 read-write CKEPDD CKEPDD 16 1 read-write CKOE CKOE 28 1 read-write DQSGE DQSGE 8 3 read-write DQSGX DQSGX 5 3 read-write FXDLAT FXDLAT 12 1 read-write LPDLLPD LPDLLPD 4 1 read-write LPIOPD LPIOPD 3 1 read-write NL2OE NL2OE 25 1 read-write NL2PD NL2PD 24 1 read-write NOBUB NOBUB 11 1 read-write ODTOE ODTOE 29 1 read-write ODTPDD ODTPDD 20 1 read-write PUREN PUREN 0 1 read-write RSTOE RSTOE 30 1 read-write TPDOE TPDOE 27 1 read-write TPDPD TPDPD 26 1 read-write ZUEN ZUEN 2 1 read-write DTAR DDRPHYC_DTAR DTAR register 0x54 32 read-write n 0x0 0x0 DTBANK DTBANK 28 3 read-write DTCOL DTCOL 0 12 read-write DTMPR DTMPR 31 1 read-write DTROW DTROW 12 16 read-write DTDR0 DDRPHYC_DTDR0 DTDR0 register 0x58 32 read-write n 0x0 0x0 DTBYTE0 DTBYTE0 0 8 read-write DTBYTE1 DTBYTE1 8 8 read-write DTBYTE2 DTBYTE2 16 8 read-write DTBYTE3 DTBYTE3 24 8 read-write DTDR1 DDRPHYC_DTDR1 DTDR1 register 0x5C 32 read-write n 0x0 0x0 DTBYTE4 DTBYTE4 0 8 read-write DTBYTE5 DTBYTE5 8 8 read-write DTBYTE6 DTBYTE6 16 8 read-write DTBYTE7 DTBYTE7 24 8 read-write DTPR0 DDRPHYC_DTPR0 DTPR0 register 0x34 32 read-write n 0x0 0x0 TCCD TCCD 31 1 read-write TMRD TMRD 0 2 read-write TRAS TRAS 16 5 read-write TRC TRC 25 6 read-write TRCD TRCD 12 4 read-write TRP TRP 8 4 read-write TRRD TRRD 21 4 read-write TRTP TRTP 2 3 read-write TWTR TWTR 5 3 read-write DTPR1 DDRPHYC_DTPR1 DTPR1 register 0x38 32 read-write n 0x0 0x0 TAOND TAOND 0 2 read-write TDQSCKMAX TDQSCKMAX 27 3 read-write TDQSCKMIN TDQSCKMIN 24 3 read-write TFAW TFAW 3 6 read-write TMOD TMOD 9 2 read-write TRFC TRFC 16 8 read-write TRTODT TRTODT 11 1 read-write TRTW TRTW 2 1 read-write DTPR2 DDRPHYC_DTPR2 DTPR2 register 0x3C 32 read-write n 0x0 0x0 TCKE TCKE 15 4 read-write TDLLK TDLLK 19 10 read-write TXP TXP 10 5 read-write TXS TXS 0 10 read-write DX0DLLCR DDRPHYC_DX0DLLCR DX 0 DLLCR register 0x1CC 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 read-write DLLDIS DLLDIS 31 1 read-write DLLSRST DLLSRST 30 1 read-write MFBDLY MFBDLY 6 3 read-write MFWDLY MFWDLY 9 3 read-write SDLBMODE SDLBMODE 19 1 read-write SDPHASE SDPHASE 14 4 read-write SFBDLY SFBDLY 0 3 read-write SFWDLY SFWDLY 3 3 read-write SSTART SSTART 12 2 read-write DX0DQSTR DDRPHYC_DX0DQSTR DX 0 DQSTR register 0x1D4 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 read-write DQSDLY DQSDLY 20 3 read-write DQSNDLY DQSNDLY 23 3 read-write R0DGPS R0DGPS 12 2 read-write R0DGSL R0DGSL 0 3 read-write DX0DQTR DDRPHYC_DX0DQTR DX 0 DQTR register 0x1D0 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 read-write DQDLY1 DQDLY1 4 4 read-write DQDLY2 DQDLY2 8 4 read-write DQDLY3 DQDLY3 12 4 read-write DQDLY4 DQDLY4 16 4 read-write DQDLY5 DQDLY5 20 4 read-write DQDLY6 DQDLY6 24 4 read-write DQDLY7 DQDLY7 28 4 read-write DX0GCR DDRPHYC_DX0GCR DX 0 GCR register 0x1C0 32 read-write n 0x0 0x0 DQODT DQODT 2 1 read-write DQRTT DQRTT 10 1 read-write DQSODT DQSODT 1 1 read-write DQSRPD DQSRPD 6 1 read-write DQSRTT DQSRTT 9 1 read-write DSEN DSEN 7 2 read-write DXEN DXEN 0 1 read-write DXIOM DXIOM 3 1 read-write DXPDD DXPDD 4 1 read-write DXPDR DXPDR 5 1 read-write R0RVSL R0RVSL 14 3 read-write RTTOAL RTTOAL 13 1 read-write RTTOH RTTOH 11 2 read-write DX0GSR0 DDRPHYC_DX0GSR0 DX 0 GSR0 register 0x1C4 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 read-only DTERR DTERR 4 1 read-only DTIERR DTIERR 8 1 read-only DTPASS DTPASS 13 3 read-only DX0GSR1 DDRPHYC_DX0GSR1 DX 0 GSR1 register 0x1C8 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 read-only DQSDFT DQSDFT 4 2 read-only RVERR RVERR 12 1 read-only RVIERR RVIERR 16 1 read-only RVPASS RVPASS 20 3 read-only DX1DLLCR DDRPHYC_DX1DLLCR DX 1 DLLCR register 0x20C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 read-write DLLDIS DLLDIS 31 1 read-write DLLSRST DLLSRST 30 1 read-write MFBDLY MFBDLY 6 3 read-write MFWDLY MFWDLY 9 3 read-write SDLBMODE SDLBMODE 19 1 read-write SDPHASE SDPHASE 14 4 read-write SFBDLY SFBDLY 0 3 read-write SFWDLY SFWDLY 3 3 read-write SSTART SSTART 12 2 read-write DX1DQSTR DDRPHYC_DX1DQSTR DX 1 DQSTR register 0x214 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 read-write DQSDLY DQSDLY 20 3 read-write DQSNDLY DQSNDLY 23 3 read-write R0DGPS R0DGPS 12 2 read-write R0DGSL R0DGSL 0 3 read-write DX1DQTR DDRPHYC_DX1DQTR DX 1 DQTR register 0x210 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 read-write DQDLY1 DQDLY1 4 4 read-write DQDLY2 DQDLY2 8 4 read-write DQDLY3 DQDLY3 12 4 read-write DQDLY4 DQDLY4 16 4 read-write DQDLY5 DQDLY5 20 4 read-write DQDLY6 DQDLY6 24 4 read-write DQDLY7 DQDLY7 28 4 read-write DX1GCR DDRPHYC_DX1GCR DX 1 GCR register 0x200 32 read-write n 0x0 0x0 DQODT DQODT 2 1 read-write DQRTT DQRTT 10 1 read-write DQSODT DQSODT 1 1 read-write DQSRPD DQSRPD 6 1 read-write DQSRTT DQSRTT 9 1 read-write DSEN DSEN 7 2 read-write DXEN DXEN 0 1 read-write DXIOM DXIOM 3 1 read-write DXPDD DXPDD 4 1 read-write DXPDR DXPDR 5 1 read-write R0RVSL R0RVSL 14 3 read-write RTTOAL RTTOAL 13 1 read-write RTTOH RTTOH 11 2 read-write DX1GSR0 DDRPHYC_DX1GSR0 DX 1 GSR0 register 0x204 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 read-only DTERR DTERR 4 1 read-only DTIERR DTIERR 8 1 read-only DTPASS DTPASS 13 3 read-only DX1GSR1 DDRPHYC_DX1GSR1 DX 1 GSR1 register 0x208 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 read-only DQSDFT DQSDFT 4 2 read-only RVERR RVERR 12 1 read-only RVIERR RVIERR 16 1 read-only RVPASS RVPASS 20 3 read-only DX2DLLCR DDRPHYC_DX2DLLCR DX 2 DLLCR register 0x24C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 read-write DLLDIS DLLDIS 31 1 read-write DLLSRST DLLSRST 30 1 read-write MFBDLY MFBDLY 6 3 read-write MFWDLY MFWDLY 9 3 read-write SDLBMODE SDLBMODE 19 1 read-write SDPHASE SDPHASE 14 4 read-write SFBDLY SFBDLY 0 3 read-write SFWDLY SFWDLY 3 3 read-write SSTART SSTART 12 2 read-write DX2DQSTR DDRPHYC_DX2DQSTR DX 2 DQSTR register 0x254 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 read-write DQSDLY DQSDLY 20 3 read-write DQSNDLY DQSNDLY 23 3 read-write R0DGPS R0DGPS 12 2 read-write R0DGSL R0DGSL 0 3 read-write DX2DQTR DDRPHYC_DX2DQTR DX 2 DQTR register 0x250 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 read-write DQDLY1 DQDLY1 4 4 read-write DQDLY2 DQDLY2 8 4 read-write DQDLY3 DQDLY3 12 4 read-write DQDLY4 DQDLY4 16 4 read-write DQDLY5 DQDLY5 20 4 read-write DQDLY6 DQDLY6 24 4 read-write DQDLY7 DQDLY7 28 4 read-write DX2GCR DDRPHYC_DX2GCR DX 2 GCR register 0x240 32 read-write n 0x0 0x0 DQODT DQODT 2 1 read-write DQRTT DQRTT 10 1 read-write DQSODT DQSODT 1 1 read-write DQSRPD DQSRPD 6 1 read-write DQSRTT DQSRTT 9 1 read-write DSEN DSEN 7 2 read-write DXEN DXEN 0 1 read-write DXIOM DXIOM 3 1 read-write DXPDD DXPDD 4 1 read-write DXPDR DXPDR 5 1 read-write R0RVSL R0RVSL 14 3 read-write RTTOAL RTTOAL 13 1 read-write RTTOH RTTOH 11 2 read-write DX2GSR0 DDRPHYC_DX2GSR0 DX 2 GSR0 register 0x244 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 read-only DTERR DTERR 4 1 read-only DTIERR DTIERR 8 1 read-only DTPASS DTPASS 13 3 read-only DX2GSR1 DDRPHYC_DX2GSR1 DX 2 GSR1 register 0x248 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 read-only DQSDFT DQSDFT 4 2 read-only RVERR RVERR 12 1 read-only RVIERR RVIERR 16 1 read-only RVPASS RVPASS 20 3 read-only DX3DLLCR DDRPHYC_DX3DLLCR DX 3 DLLCR register 0x28C 32 read-write n 0x0 0x0 ATESTEN ATESTEN 18 1 read-write DLLDIS DLLDIS 31 1 read-write DLLSRST DLLSRST 30 1 read-write MFBDLY MFBDLY 6 3 read-write MFWDLY MFWDLY 9 3 read-write SDLBMODE SDLBMODE 19 1 read-write SDPHASE SDPHASE 14 4 read-write SFBDLY SFBDLY 0 3 read-write SFWDLY SFWDLY 3 3 read-write SSTART SSTART 12 2 read-write DX3DQSTR DDRPHYC_DX3DQSTR DX 3 DQSTR register 0x294 32 read-write n 0x0 0x0 DMDLY DMDLY 26 4 read-write DQSDLY DQSDLY 20 3 read-write DQSNDLY DQSNDLY 23 3 read-write R0DGPS R0DGPS 12 2 read-write R0DGSL R0DGSL 0 3 read-write DX3DQTR DDRPHYC_DX3DQTR DX 3 DQTR register 0x290 32 read-write n 0x0 0x0 DQDLY0 DQDLY0 0 4 read-write DQDLY1 DQDLY1 4 4 read-write DQDLY2 DQDLY2 8 4 read-write DQDLY3 DQDLY3 12 4 read-write DQDLY4 DQDLY4 16 4 read-write DQDLY5 DQDLY5 20 4 read-write DQDLY6 DQDLY6 24 4 read-write DQDLY7 DQDLY7 28 4 read-write DX3GCR DDRPHYC_DX3GCR DX 3 GCR register 0x280 32 read-write n 0x0 0x0 DQODT DQODT 2 1 read-write DQRTT DQRTT 10 1 read-write DQSODT DQSODT 1 1 read-write DQSRPD DQSRPD 6 1 read-write DQSRTT DQSRTT 9 1 read-write DSEN DSEN 7 2 read-write DXEN DXEN 0 1 read-write DXIOM DXIOM 3 1 read-write DXPDD DXPDD 4 1 read-write DXPDR DXPDR 5 1 read-write R0RVSL R0RVSL 14 3 read-write RTTOAL RTTOAL 13 1 read-write RTTOH RTTOH 11 2 read-write DX3GSR0 DDRPHYC_DX3GSR0 DX 3 GSR0 register 0x284 16 read-only n 0x0 0x0 DTDONE DTDONE 0 1 read-only DTERR DTERR 4 1 read-only DTIERR DTIERR 8 1 read-only DTPASS DTPASS 13 3 read-only DX3GSR1 DDRPHYC_DX3GSR1 DX 3 GSR1 register 0x288 32 read-only n 0x0 0x0 DFTERR DFTERR 0 1 read-only DQSDFT DQSDFT 4 2 read-only RVERR RVERR 12 1 read-only RVIERR RVIERR 16 1 read-only RVPASS RVPASS 20 3 read-only DXCCR DDRPHYC_DXCCR DXCCR register 0x28 32 read-write n 0x0 0x0 AWDT AWDT 16 1 read-write DQSNRES DQSNRES 8 4 read-write DQSNRST DQSNRST 14 1 read-write DQSRES DQSRES 4 4 read-write DXIOM DXIOM 1 1 read-write DXODT DXODT 0 1 read-write DXPDD DXPDD 2 1 read-write DXPDR DXPDR 3 1 read-write RVSEL RVSEL 15 1 read-write GPR0 DDRPHYC_GPR0 General Purpose Register 0 0x178 32 read-write n 0x0 0x0 GPR0 GPR0 0 32 read-write GPR1 DDRPHYC_GPR1 General Purpose Register register 1 0x17C 32 read-write n 0x0 0x0 GPR1 GPR1 0 32 read-write MR0 DDRPHYC_MR0 MR0 register for DDR3 0x40 16 read-write n 0x0 0x0 BL BL 0 2 read-write BT BT 3 1 read-write CL CL 4 3 read-write CL0 CL0 2 1 read-write DR DR 8 1 read-write PD PD 12 1 read-write RSVD RSVD 13 3 read-write TM TM 7 1 read-write WR WR 9 3 read-write MR1 DDRPHYC_MR1 MR1 register for LPDDR2 0x44 16 read-write n 0x0 0x0 BL BL 0 3 read-write BT BT 3 1 read-write NWR NWR 5 3 read-write WC WC 4 1 read-write MR2 DDRPHYC_MR2 MR2 register for LPDDR2 0x48 16 read-write n 0x0 0x0 RLWL RLWL 0 3 read-write MR3 DDRPHYC_MR3 MR3 register for DDR3 0x4C 8 read-write n 0x0 0x0 MPR MPR 2 1 read-write MPRLOC MPRLOC 0 2 read-write ODTCR DDRPHYC_ODTCR ODTCR register 0x50 32 read-write n 0x0 0x0 RDODT0 RDODT0 0 4 read-write RDODT1 RDODT1 4 4 read-write RDODT2 RDODT2 8 4 read-write RDODT3 RDODT3 12 4 read-write WRODT0 WRODT0 16 4 read-write WRODT1 WRODT1 20 4 read-write WRODT2 WRODT2 24 4 read-write WRODT3 WRODT3 28 4 read-write PGCR DDRPHYC_PGCR PGCR register 0x8 32 read-write n 0x0 0x0 CKDV CKDV 12 2 read-write CKEN CKEN 9 3 read-write CKINV CKINV 14 1 read-write DFTCMP DFTCMP 2 1 read-write DFTLMT DFTLMT 3 2 read-write DQSCFG DQSCFG 1 1 read-write DTOSEL DTOSEL 5 4 read-write IODDRM IODDRM 16 2 read-write IOLB IOLB 15 1 read-write ITMDMD ITMDMD 0 1 read-write LBDQSS LBDQSS 29 1 read-write LBGDQS LBGDQS 30 1 read-write LBMODE LBMODE 31 1 read-write PDDISDX PDDISDX 24 1 read-write RANKEN RANKEN 18 4 read-write RFSHDT RFSHDT 25 4 read-write ZKSEL ZKSEL 22 2 read-write PGSR DDRPHYC_PGSR PGSR register 0xC 32 read-only n 0x0 0x0 DFTERR DFTERR 7 1 read-only DIDONE DIDONE 3 1 read-only DLDONE DLDONE 1 1 read-only DTDONE DTDONE 4 1 read-only DTERR DTERR 5 1 read-only DTIERR DTIERR 6 1 read-only IDONE IDONE 0 1 read-only RVEIRR RVEIRR 9 1 read-only RVERR RVERR 8 1 read-only TQ TQ 31 1 read-only ZCDDONE ZCDDONE 2 1 read-only PIR DDRPHYC_PIR PIR register 0x4 32 read-write n 0x0 0x0 CLRSR CLRSR 28 1 write-only CTLDINIT CTLDINIT 18 1 write-only DLLBYP DLLBYP 17 1 write-only DLLLOCK DLLLOCK 2 1 write-only DLLSRST DLLSRST 1 1 write-only DRAMINIT DRAMINIT 6 1 write-only DRAMRST DRAMRST 5 1 write-only ICPC ICPC 16 1 write-only INIT INIT 0 1 write-only INITBYP INITBYP 31 1 write-only ITMSRST ITMSRST 4 1 write-only LOCKBYP LOCKBYP 29 1 write-only QSTRN QSTRN 7 1 write-only RVTRN RVTRN 8 1 write-only ZCAL ZCAL 3 1 write-only ZCALBYP ZCALBYP 30 1 write-only PTR0 DDRPHYC_PTR0 PTR0 register 0x18 32 read-write n 0x0 0x0 TDLLLOCK TDLLLOCK 6 12 read-write TDLLSRST TDLLSRST 0 6 read-write TITMSRST TITMSRST 18 4 read-write PTR1 DDRPHYC_PTR1 PTR1 register 0x1C 32 read-write n 0x0 0x0 TDINIT0 TDINIT0 0 19 read-write TDINIT1 TDINIT1 19 8 read-write PTR2 DDRPHYC_PTR2 PTR2 register 0x20 32 read-write n 0x0 0x0 TDINIT2 TDINIT2 0 17 read-write TDINIT3 TDINIT3 17 10 read-write RIDR DDRPHYC_RIDR RIDR register 0x0 32 read-only n 0x0 0x0 PHYMDR PHYMDR 16 4 read-only PHYMJR PHYMJR 20 4 read-only PHYMNR PHYMNR 12 4 read-only PUBMDR PUBMDR 4 4 read-only PUBMJR PUBMJR 8 4 read-only PUBMNR PUBMNR 0 4 read-only UDRID UDRID 24 8 read-only ZQ0CR0 DDRPHYC_ZQ0CR0 ZQ0CR0 register 0x180 32 read-write n 0x0 0x0 ZCAL ZCAL 30 1 read-write ZCALBYP ZCALBYP 29 1 read-write ZDATA ZDATA 0 20 read-write ZDEN ZDEN 28 1 read-write ZQPD ZQPD 31 1 read-write ZQ0CR1 DDRPHYC_ZQ0CR1 ZQ0CR1 register 0x184 8 read-write n 0x0 0x0 ZPROG ZPROG 0 8 read-write B_0x1 120ohm 0x1 B_0x5 60ohm 0x5 B_0x8 40ohm 0x8 B_0xB 40ohm 0xB B_0xD 34ohm 0xD ZQ0SR0 DDRPHYC_ZQ0SR0 ZQ0SR0 register 0x188 32 read-only n 0x0 0x0 ZCTRL ZCTRL 0 20 read-only ZDONE ZDONE 31 1 read-only ZERR ZERR 30 1 read-only ZQ0SR1 DDRPHYC_ZQ0SR1 ZQ0SR1 register 0x18C 8 read-only n 0x0 0x0 OPD OPD 4 2 read-only OPU OPU 6 2 read-only ZPD ZPD 0 2 read-only ZPU ZPU 2 2 read-only DFSDM1 DFSDM1 DFSDM1 0x0 0x0 0x800 registers n DFSDM_CH0AWSCDR DFSDM_CH0AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0x8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH0CFGR1 DFSDM_CH0CFGR1 This register specifies the parameters used by channel y. 0x0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH0CFGR2 DFSDM_CH0CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0x4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH0DATINR DFSDM_CH0DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x10 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH0WDATR DFSDM_CH0WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0xC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH1AWSCDR DFSDM_CH1AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0x28 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH1CFGR1 DFSDM_CH1CFGR1 This register specifies the parameters used by channel y. 0x20 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH1CFGR2 DFSDM_CH1CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0x24 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH1DATINR DFSDM_CH1DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x30 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH1WDATR DFSDM_CH1WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0x2C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH2AWSCDR DFSDM_CH2AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0x48 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH2CFGR1 DFSDM_CH2CFGR1 This register specifies the parameters used by channel y. 0x40 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH2CFGR2 DFSDM_CH2CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0x44 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH2DATINR DFSDM_CH2DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x50 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH2WDATR DFSDM_CH2WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0x4C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH3AWSCDR DFSDM_CH3AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0x68 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH3CFGR1 DFSDM_CH3CFGR1 This register specifies the parameters used by channel y. 0x60 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH3CFGR2 DFSDM_CH3CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0x64 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH3DATINR DFSDM_CH3DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x70 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH3WDATR DFSDM_CH3WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0x6C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH4AWSCDR DFSDM_CH4AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0x88 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH4CFGR1 DFSDM_CH4CFGR1 This register specifies the parameters used by channel y. 0x80 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH4CFGR2 DFSDM_CH4CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0x84 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH4DATINR DFSDM_CH4DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0x90 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH4WDATR DFSDM_CH4WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0x8C 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH5AWSCDR DFSDM_CH5AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0xA8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH5CFGR1 DFSDM_CH5CFGR1 This register specifies the parameters used by channel y. 0xA0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH5CFGR2 DFSDM_CH5CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0xA4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH5DATINR DFSDM_CH5DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xB0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH5WDATR DFSDM_CH5WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0xAC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH6AWSCDR DFSDM_CH6AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0xC8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH6CFGR1 DFSDM_CH6CFGR1 This register specifies the parameters used by channel y. 0xC0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH6CFGR2 DFSDM_CH6CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0xC4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH6DATINR DFSDM_CH6DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xD0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH6WDATR DFSDM_CH6WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0xCC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_CH7AWSCDR DFSDM_CH7AWSCDR Short-circuit detector and analog watchdog settings for channel y (y = 0..7) 0xE8 32 read-write n 0x0 0x0 AWFORD AWFORD 22 2 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 AWFOSR AWFOSR 16 5 read-write BKSCD BKSCD 12 4 read-write SCDT SCDT 0 8 read-write DFSDM_CH7CFGR1 DFSDM_CH7CFGR1 This register specifies the parameters used by channel y. 0xE0 32 read-write n 0x0 0x0 CHEN CHEN 7 1 read-write B_0x0 Channel y disabled 0x0 B_0x1 Channel y enabled 0x1 CHINSEL CHINSEL 8 1 read-write B_0x0 Channel inputs are taken from pins of the same channel y. 0x0 B_0x1 Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8). 0x1 CKABEN CKABEN 6 1 read-write B_0x0 Clock absence detector disabled on channel y 0x0 B_0x1 Clock absence detector enabled on channel y 0x1 CKOUTDIV CKOUTDIV 16 8 read-write B_0x0 Output clock generation is disabled (CKOUT signal is set to low state) 0x0 CKOUTSRC CKOUTSRC 30 1 read-write B_0x0 Source for output clock is from system clock 0x0 B_0x1 Source for output clock is from audio clock 0x1 DATMPX DATMPX 12 2 read-write B_0x0 Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 0x0 B_0x1 Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register. 0x1 B_0x2 Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 0x2 DATPACK DATPACK 14 2 read-write B_0x0 Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y. 0x0 B_0x1 Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: 0x1 B_0x2 Dual: input data in DFSDM_CHyDATINR register are stored as two samples: 0x2 DFSDMEN DFSDMEN 31 1 read-write B_0x0 DFSDM interface disabled 0x0 B_0x1 DFSDM interface enabled 0x1 SCDEN SCDEN 5 1 read-write B_0x0 Input channel y will not be guarded by the short-circuit detector 0x0 B_0x1 Input channel y will be continuously guarded by the short-circuit detector 0x1 SITP SITP 0 2 read-write B_0x0 SPI with rising edge to strobe data 0x0 B_0x1 SPI with falling edge to strobe data 0x1 B_0x2 Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1 0x2 B_0x3 Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0 0x3 SPICKSEL SPICKSEL 2 2 read-write B_0x0 clock coming from external CKINy input - sampling point according SITP[1:0] 0x0 B_0x1 clock coming from internal CKOUT output - sampling point according SITP[1:0] 0x1 B_0x2 clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. 0x2 B_0x3 clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. 0x3 DFSDM_CH7CFGR2 DFSDM_CH7CFGR2 This register specifies the parameters used by channel y (y = 0..7). 0xE4 32 read-write n 0x0 0x0 DTRBS DTRBS 3 5 read-write OFFSET OFFSET 8 24 read-write DFSDM_CH7DATINR DFSDM_CH7DATINR This register contains 16-bit input data to be processed by DFSDM filter module. 0xF0 32 read-write n 0x0 0x0 INDAT0 INDAT0 0 16 read-write INDAT1 INDAT1 16 16 read-write DFSDM_CH7WDATR DFSDM_CH7WDATR This register contains the data resulting from the analog watchdog filter associated to the input channel y (y = 0..7). 0xEC 32 read-only n 0x0 0x0 WDATA WDATA 0 16 read-only DFSDM_FLT0AWCFR DFSDM_FLT0AWCFR DFSDM analog watchdog clear flag register 0x12C 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 read-write CLRAWLTF CLRAWLTF 0 8 read-write DFSDM_FLT0AWHTR DFSDM_FLT0AWHTR DFSDM analog watchdog high threshold register 0x120 32 read-write n 0x0 0x0 AWHT AWHT 8 24 read-write BKAWH BKAWH 0 4 read-write DFSDM_FLT0AWLTR DFSDM_FLT0AWLTR DFSDM analog watchdog low threshold register 0x124 32 read-write n 0x0 0x0 AWLT AWLT 8 24 read-write BKAWL BKAWL 0 4 read-write DFSDM_FLT0AWSR DFSDM_FLT0AWSR DFSDM analog watchdog status register 0x128 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 read-only AWLTF AWLTF 0 8 read-only DFSDM_FLT0CNVTIMR DFSDM_FLT0CNVTIMR DFSDM conversion timer register 0x138 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 read-only DFSDM_FLT0CR1 DFSDM_FLT0CR1 DFSDM control register 1 0x100 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 read-write B_0x0 Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0x0 B_0x1 Analog watchdog on channel transceivers value (after watchdog filter) 0x1 DFEN DFEN 0 1 read-write B_0x0 DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 0x0 B_0x1 DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. 0x1 FAST FAST 29 1 read-write B_0x0 Fast conversion mode disabled 0x0 B_0x1 Fast conversion mode enabled 0x1 JDMAEN JDMAEN 5 1 read-write B_0x0 The DMA channel is not enabled to read injected data 0x0 B_0x1 The DMA channel is enabled to read injected data 0x1 JEXTEN JEXTEN 13 2 read-write B_0x0 Trigger detection is disabled 0x0 B_0x1 Each rising edge on the selected trigger makes a request to launch an injected conversion 0x1 B_0x2 Each falling edge on the selected trigger makes a request to launch an injected conversion 0x2 B_0x3 Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 0x3 JEXTSEL JEXTSEL 8 3 read-write JSCAN JSCAN 4 1 read-write B_0x0 One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 0x0 B_0x1 The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. 0x1 JSWSTART JSWSTART 1 1 write-only B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1. 0x1 JSYNC JSYNC 3 1 read-write B_0x0 Do not launch an injected conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 0x1 RCH RCH 24 3 read-write B_0x0 Channel 0 is selected as the regular channel 0x0 B_0x1 Channel 1 is selected as the regular channel 0x1 B_0x7 Channel 7 is selected as the regular channel 0x7 RCONT RCONT 18 1 read-write B_0x0 The regular channel is converted just once for each conversion request 0x0 B_0x1 The regular channel is converted repeatedly after each conversion request 0x1 RDMAEN RDMAEN 21 1 read-write B_0x0 The DMA channel is not enabled to read regular data 0x0 B_0x1 The DMA channel is enabled to read regular data 0x1 RSWSTART RSWSTART 17 1 write-only B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1. 0x1 RSYNC RSYNC 19 1 read-write B_0x0 Do not launch a regular conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 0x1 DFSDM_FLT0CR2 DFSDM_FLT0CR2 DFSDM control register 2 0x104 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 read-write AWDIE AWDIE 4 1 read-write B_0x0 Analog watchdog interrupt is disabled 0x0 B_0x1 Analog watchdog interrupt is enabled 0x1 CKABIE CKABIE 6 1 read-write B_0x0 Detection of channel input clock absence interrupt is disabled 0x0 B_0x1 Detection of channel input clock absence interrupt is enabled 0x1 EXCH EXCH 8 8 read-write JEOCIE JEOCIE 0 1 read-write B_0x0 Injected end of conversion interrupt is disabled 0x0 B_0x1 Injected end of conversion interrupt is enabled 0x1 JOVRIE JOVRIE 2 1 read-write B_0x0 Injected data overrun interrupt is disabled 0x0 B_0x1 Injected data overrun interrupt is enabled 0x1 REOCIE REOCIE 1 1 read-write B_0x0 Regular end of conversion interrupt is disabled 0x0 B_0x1 Regular end of conversion interrupt is enabled 0x1 ROVRIE ROVRIE 3 1 read-write B_0x0 Regular data overrun interrupt is disabled 0x0 B_0x1 Regular data overrun interrupt is enabled 0x1 SCDIE SCDIE 5 1 read-write B_0x0 short-circuit detector interrupt is disabled 0x0 B_0x1 short-circuit detector interrupt is enabled 0x1 DFSDM_FLT0EXMAX DFSDM_FLT0EXMAX DFSDM Extremes detector maximum register 0x130 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 read-only EXMAXCH EXMAXCH 0 3 read-only DFSDM_FLT0EXMIN DFSDM_FLT0EXMIN DFSDM Extremes detector minimum register 0x134 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 read-only EXMINCH EXMINCH 0 3 read-only DFSDM_FLT0FCR DFSDM_FLT0FCR DFSDM filter control register 0x114 32 read-write n 0x0 0x0 FORD FORD 29 3 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 B_0x4 Sinc4 filter type 0x4 B_0x5 Sinc5 filter type 0x5 FOSR FOSR 16 10 read-write IOSR IOSR 0 8 read-write DFSDM_FLT0ICR DFSDM_FLT0ICR DFSDM interrupt flag clear register 0x10C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 read-write CLRJOVRF CLRJOVRF 2 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register 0x1 CLRROVRF CLRROVRF 3 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register 0x1 CLRSCDF CLRSCDF 24 8 read-write DFSDM_FLT0ISR DFSDM_FLT0ISR DFSDM interrupt and status register 0x108 32 read-only n 0x0 0x0 AWDF AWDF 4 1 read-only B_0x0 No Analog watchdog event occurred 0x0 B_0x1 The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. 0x1 CKABF CKABF 16 8 read-only JCIP JCIP 13 1 read-only B_0x0 No request to convert the injected channel group (neither by software nor by trigger) has been issued 0x0 B_0x1 The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection 0x1 JEOCF JEOCF 0 1 read-only B_0x0 No injected conversion has completed 0x0 B_0x1 An injected conversion has completed and its data may be read 0x1 JOVRF JOVRF 2 1 read-only B_0x0 No injected conversion overrun has occurred 0x0 B_0x1 An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns 0x1 RCIP RCIP 14 1 read-only B_0x0 No request to convert the regular channel has been issued 0x0 B_0x1 The conversion of the regular channel is in progress or a request for a regular conversion is pending 0x1 REOCF REOCF 1 1 read-only B_0x0 No regular conversion has completed 0x0 B_0x1 A regular conversion has completed and its data may be read 0x1 ROVRF ROVRF 3 1 read-only B_0x0 No regular conversion overrun has occurred 0x0 B_0x1 A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns 0x1 SCDF SCDF 24 8 read-only DFSDM_FLT0JCHGR DFSDM_FLT0JCHGR DFSDM injected channel group selection register 0x110 32 read-write n 0x0 0x0 JCHG JCHG 0 8 read-write DFSDM_FLT0JDATAR DFSDM_FLT0JDATAR DFSDM data register for injected group 0x118 32 read-only n 0x0 0x0 JDATA JDATA 8 24 read-only JDATACH JDATACH 0 3 read-only DFSDM_FLT0RDATAR DFSDM_FLT0RDATAR DFSDM data register for the regular channel 0x11C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 read-only RDATACH RDATACH 0 3 read-only RPEND RPEND 4 1 read-only DFSDM_FLT1AWCFR DFSDM_FLT1AWCFR DFSDM analog watchdog clear flag register 0x1AC 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 read-write CLRAWLTF CLRAWLTF 0 8 read-write DFSDM_FLT1AWHTR DFSDM_FLT1AWHTR DFSDM analog watchdog high threshold register 0x1A0 32 read-write n 0x0 0x0 AWHT AWHT 8 24 read-write BKAWH BKAWH 0 4 read-write DFSDM_FLT1AWLTR DFSDM_FLT1AWLTR DFSDM analog watchdog low threshold register 0x1A4 32 read-write n 0x0 0x0 AWLT AWLT 8 24 read-write BKAWL BKAWL 0 4 read-write DFSDM_FLT1AWSR DFSDM_FLT1AWSR DFSDM analog watchdog status register 0x1A8 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 read-only AWLTF AWLTF 0 8 read-only DFSDM_FLT1CNVTIMR DFSDM_FLT1CNVTIMR DFSDM conversion timer register 0x1B8 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 read-only DFSDM_FLT1CR1 DFSDM_FLT1CR1 DFSDM control register 1 0x180 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 read-write B_0x0 Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0x0 B_0x1 Analog watchdog on channel transceivers value (after watchdog filter) 0x1 DFEN DFEN 0 1 read-write B_0x0 DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 0x0 B_0x1 DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. 0x1 FAST FAST 29 1 read-write B_0x0 Fast conversion mode disabled 0x0 B_0x1 Fast conversion mode enabled 0x1 JDMAEN JDMAEN 5 1 read-write B_0x0 The DMA channel is not enabled to read injected data 0x0 B_0x1 The DMA channel is enabled to read injected data 0x1 JEXTEN JEXTEN 13 2 read-write B_0x0 Trigger detection is disabled 0x0 B_0x1 Each rising edge on the selected trigger makes a request to launch an injected conversion 0x1 B_0x2 Each falling edge on the selected trigger makes a request to launch an injected conversion 0x2 B_0x3 Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 0x3 JEXTSEL JEXTSEL 8 3 read-write JSCAN JSCAN 4 1 read-write B_0x0 One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 0x0 B_0x1 The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. 0x1 JSWSTART JSWSTART 1 1 write-only B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1. 0x1 JSYNC JSYNC 3 1 read-write B_0x0 Do not launch an injected conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 0x1 RCH RCH 24 3 read-write B_0x0 Channel 0 is selected as the regular channel 0x0 B_0x1 Channel 1 is selected as the regular channel 0x1 B_0x7 Channel 7 is selected as the regular channel 0x7 RCONT RCONT 18 1 read-write B_0x0 The regular channel is converted just once for each conversion request 0x0 B_0x1 The regular channel is converted repeatedly after each conversion request 0x1 RDMAEN RDMAEN 21 1 read-write B_0x0 The DMA channel is not enabled to read regular data 0x0 B_0x1 The DMA channel is enabled to read regular data 0x1 RSWSTART RSWSTART 17 1 write-only B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1. 0x1 RSYNC RSYNC 19 1 read-write B_0x0 Do not launch a regular conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 0x1 DFSDM_FLT1CR2 DFSDM_FLT1CR2 DFSDM control register 2 0x184 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 read-write AWDIE AWDIE 4 1 read-write B_0x0 Analog watchdog interrupt is disabled 0x0 B_0x1 Analog watchdog interrupt is enabled 0x1 CKABIE CKABIE 6 1 read-write B_0x0 Detection of channel input clock absence interrupt is disabled 0x0 B_0x1 Detection of channel input clock absence interrupt is enabled 0x1 EXCH EXCH 8 8 read-write JEOCIE JEOCIE 0 1 read-write B_0x0 Injected end of conversion interrupt is disabled 0x0 B_0x1 Injected end of conversion interrupt is enabled 0x1 JOVRIE JOVRIE 2 1 read-write B_0x0 Injected data overrun interrupt is disabled 0x0 B_0x1 Injected data overrun interrupt is enabled 0x1 REOCIE REOCIE 1 1 read-write B_0x0 Regular end of conversion interrupt is disabled 0x0 B_0x1 Regular end of conversion interrupt is enabled 0x1 ROVRIE ROVRIE 3 1 read-write B_0x0 Regular data overrun interrupt is disabled 0x0 B_0x1 Regular data overrun interrupt is enabled 0x1 SCDIE SCDIE 5 1 read-write B_0x0 short-circuit detector interrupt is disabled 0x0 B_0x1 short-circuit detector interrupt is enabled 0x1 DFSDM_FLT1EXMAX DFSDM_FLT1EXMAX DFSDM Extremes detector maximum register 0x1B0 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 read-only EXMAXCH EXMAXCH 0 3 read-only DFSDM_FLT1EXMIN DFSDM_FLT1EXMIN DFSDM Extremes detector minimum register 0x1B4 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 read-only EXMINCH EXMINCH 0 3 read-only DFSDM_FLT1FCR DFSDM_FLT1FCR DFSDM filter control register 0x194 32 read-write n 0x0 0x0 FORD FORD 29 3 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 B_0x4 Sinc4 filter type 0x4 B_0x5 Sinc5 filter type 0x5 FOSR FOSR 16 10 read-write IOSR IOSR 0 8 read-write DFSDM_FLT1ICR DFSDM_FLT1ICR DFSDM interrupt flag clear register 0x18C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 read-write CLRJOVRF CLRJOVRF 2 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register 0x1 CLRROVRF CLRROVRF 3 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register 0x1 CLRSCDF CLRSCDF 24 8 read-write DFSDM_FLT1ISR DFSDM_FLT1ISR DFSDM interrupt and status register 0x188 32 read-only n 0x0 0x0 AWDF AWDF 4 1 read-only B_0x0 No Analog watchdog event occurred 0x0 B_0x1 The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. 0x1 CKABF CKABF 16 8 read-only JCIP JCIP 13 1 read-only B_0x0 No request to convert the injected channel group (neither by software nor by trigger) has been issued 0x0 B_0x1 The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection 0x1 JEOCF JEOCF 0 1 read-only B_0x0 No injected conversion has completed 0x0 B_0x1 An injected conversion has completed and its data may be read 0x1 JOVRF JOVRF 2 1 read-only B_0x0 No injected conversion overrun has occurred 0x0 B_0x1 An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns 0x1 RCIP RCIP 14 1 read-only B_0x0 No request to convert the regular channel has been issued 0x0 B_0x1 The conversion of the regular channel is in progress or a request for a regular conversion is pending 0x1 REOCF REOCF 1 1 read-only B_0x0 No regular conversion has completed 0x0 B_0x1 A regular conversion has completed and its data may be read 0x1 ROVRF ROVRF 3 1 read-only B_0x0 No regular conversion overrun has occurred 0x0 B_0x1 A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns 0x1 SCDF SCDF 24 8 read-only DFSDM_FLT1JCHGR DFSDM_FLT1JCHGR DFSDM injected channel group selection register 0x190 32 read-write n 0x0 0x0 JCHG JCHG 0 8 read-write DFSDM_FLT1JDATAR DFSDM_FLT1JDATAR DFSDM data register for injected group 0x198 32 read-only n 0x0 0x0 JDATA JDATA 8 24 read-only JDATACH JDATACH 0 3 read-only DFSDM_FLT1RDATAR DFSDM_FLT1RDATAR DFSDM data register for the regular channel 0x19C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 read-only RDATACH RDATACH 0 3 read-only RPEND RPEND 4 1 read-only DFSDM_FLT2AWCFR DFSDM_FLT2AWCFR DFSDM analog watchdog clear flag register 0x22C 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 read-write CLRAWLTF CLRAWLTF 0 8 read-write DFSDM_FLT2AWHTR DFSDM_FLT2AWHTR DFSDM analog watchdog high threshold register 0x220 32 read-write n 0x0 0x0 AWHT AWHT 8 24 read-write BKAWH BKAWH 0 4 read-write DFSDM_FLT2AWLTR DFSDM_FLT2AWLTR DFSDM analog watchdog low threshold register 0x224 32 read-write n 0x0 0x0 AWLT AWLT 8 24 read-write BKAWL BKAWL 0 4 read-write DFSDM_FLT2AWSR DFSDM_FLT2AWSR DFSDM analog watchdog status register 0x228 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 read-only AWLTF AWLTF 0 8 read-only DFSDM_FLT2CNVTIMR DFSDM_FLT2CNVTIMR DFSDM conversion timer register 0x238 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 read-only DFSDM_FLT2CR1 DFSDM_FLT2CR1 DFSDM control register 1 0x200 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 read-write B_0x0 Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0x0 B_0x1 Analog watchdog on channel transceivers value (after watchdog filter) 0x1 DFEN DFEN 0 1 read-write B_0x0 DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 0x0 B_0x1 DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. 0x1 FAST FAST 29 1 read-write B_0x0 Fast conversion mode disabled 0x0 B_0x1 Fast conversion mode enabled 0x1 JDMAEN JDMAEN 5 1 read-write B_0x0 The DMA channel is not enabled to read injected data 0x0 B_0x1 The DMA channel is enabled to read injected data 0x1 JEXTEN JEXTEN 13 2 read-write B_0x0 Trigger detection is disabled 0x0 B_0x1 Each rising edge on the selected trigger makes a request to launch an injected conversion 0x1 B_0x2 Each falling edge on the selected trigger makes a request to launch an injected conversion 0x2 B_0x3 Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 0x3 JEXTSEL JEXTSEL 8 3 read-write JSCAN JSCAN 4 1 read-write B_0x0 One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 0x0 B_0x1 The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. 0x1 JSWSTART JSWSTART 1 1 write-only B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1. 0x1 JSYNC JSYNC 3 1 read-write B_0x0 Do not launch an injected conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 0x1 RCH RCH 24 3 read-write B_0x0 Channel 0 is selected as the regular channel 0x0 B_0x1 Channel 1 is selected as the regular channel 0x1 B_0x7 Channel 7 is selected as the regular channel 0x7 RCONT RCONT 18 1 read-write B_0x0 The regular channel is converted just once for each conversion request 0x0 B_0x1 The regular channel is converted repeatedly after each conversion request 0x1 RDMAEN RDMAEN 21 1 read-write B_0x0 The DMA channel is not enabled to read regular data 0x0 B_0x1 The DMA channel is enabled to read regular data 0x1 RSWSTART RSWSTART 17 1 write-only B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1. 0x1 RSYNC RSYNC 19 1 read-write B_0x0 Do not launch a regular conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 0x1 DFSDM_FLT2CR2 DFSDM_FLT2CR2 DFSDM control register 2 0x204 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 read-write AWDIE AWDIE 4 1 read-write B_0x0 Analog watchdog interrupt is disabled 0x0 B_0x1 Analog watchdog interrupt is enabled 0x1 CKABIE CKABIE 6 1 read-write B_0x0 Detection of channel input clock absence interrupt is disabled 0x0 B_0x1 Detection of channel input clock absence interrupt is enabled 0x1 EXCH EXCH 8 8 read-write JEOCIE JEOCIE 0 1 read-write B_0x0 Injected end of conversion interrupt is disabled 0x0 B_0x1 Injected end of conversion interrupt is enabled 0x1 JOVRIE JOVRIE 2 1 read-write B_0x0 Injected data overrun interrupt is disabled 0x0 B_0x1 Injected data overrun interrupt is enabled 0x1 REOCIE REOCIE 1 1 read-write B_0x0 Regular end of conversion interrupt is disabled 0x0 B_0x1 Regular end of conversion interrupt is enabled 0x1 ROVRIE ROVRIE 3 1 read-write B_0x0 Regular data overrun interrupt is disabled 0x0 B_0x1 Regular data overrun interrupt is enabled 0x1 SCDIE SCDIE 5 1 read-write B_0x0 short-circuit detector interrupt is disabled 0x0 B_0x1 short-circuit detector interrupt is enabled 0x1 DFSDM_FLT2EXMAX DFSDM_FLT2EXMAX DFSDM Extremes detector maximum register 0x230 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 read-only EXMAXCH EXMAXCH 0 3 read-only DFSDM_FLT2EXMIN DFSDM_FLT2EXMIN DFSDM Extremes detector minimum register 0x234 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 read-only EXMINCH EXMINCH 0 3 read-only DFSDM_FLT2FCR DFSDM_FLT2FCR DFSDM filter control register 0x214 32 read-write n 0x0 0x0 FORD FORD 29 3 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 B_0x4 Sinc4 filter type 0x4 B_0x5 Sinc5 filter type 0x5 FOSR FOSR 16 10 read-write IOSR IOSR 0 8 read-write DFSDM_FLT2ICR DFSDM_FLT2ICR DFSDM interrupt flag clear register 0x20C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 read-write CLRJOVRF CLRJOVRF 2 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register 0x1 CLRROVRF CLRROVRF 3 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register 0x1 CLRSCDF CLRSCDF 24 8 read-write DFSDM_FLT2ISR DFSDM_FLT2ISR DFSDM interrupt and status register 0x208 32 read-only n 0x0 0x0 AWDF AWDF 4 1 read-only B_0x0 No Analog watchdog event occurred 0x0 B_0x1 The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. 0x1 CKABF CKABF 16 8 read-only JCIP JCIP 13 1 read-only B_0x0 No request to convert the injected channel group (neither by software nor by trigger) has been issued 0x0 B_0x1 The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection 0x1 JEOCF JEOCF 0 1 read-only B_0x0 No injected conversion has completed 0x0 B_0x1 An injected conversion has completed and its data may be read 0x1 JOVRF JOVRF 2 1 read-only B_0x0 No injected conversion overrun has occurred 0x0 B_0x1 An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns 0x1 RCIP RCIP 14 1 read-only B_0x0 No request to convert the regular channel has been issued 0x0 B_0x1 The conversion of the regular channel is in progress or a request for a regular conversion is pending 0x1 REOCF REOCF 1 1 read-only B_0x0 No regular conversion has completed 0x0 B_0x1 A regular conversion has completed and its data may be read 0x1 ROVRF ROVRF 3 1 read-only B_0x0 No regular conversion overrun has occurred 0x0 B_0x1 A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns 0x1 SCDF SCDF 24 8 read-only DFSDM_FLT2JCHGR DFSDM_FLT2JCHGR DFSDM injected channel group selection register 0x210 32 read-write n 0x0 0x0 JCHG JCHG 0 8 read-write DFSDM_FLT2JDATAR DFSDM_FLT2JDATAR DFSDM data register for injected group 0x218 32 read-only n 0x0 0x0 JDATA JDATA 8 24 read-only JDATACH JDATACH 0 3 read-only DFSDM_FLT2RDATAR DFSDM_FLT2RDATAR DFSDM data register for the regular channel 0x21C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 read-only RDATACH RDATACH 0 3 read-only RPEND RPEND 4 1 read-only DFSDM_FLT3AWCFR DFSDM_FLT3AWCFR DFSDM analog watchdog clear flag register 0x2AC 32 read-write n 0x0 0x0 CLRAWHTF CLRAWHTF 8 8 read-write CLRAWLTF CLRAWLTF 0 8 read-write DFSDM_FLT3AWHTR DFSDM_FLT3AWHTR DFSDM analog watchdog high threshold register 0x2A0 32 read-write n 0x0 0x0 AWHT AWHT 8 24 read-write BKAWH BKAWH 0 4 read-write DFSDM_FLT3AWLTR DFSDM_FLT3AWLTR DFSDM analog watchdog low threshold register 0x2A4 32 read-write n 0x0 0x0 AWLT AWLT 8 24 read-write BKAWL BKAWL 0 4 read-write DFSDM_FLT3AWSR DFSDM_FLT3AWSR DFSDM analog watchdog status register 0x2A8 32 read-only n 0x0 0x0 AWHTF AWHTF 8 8 read-only AWLTF AWLTF 0 8 read-only DFSDM_FLT3CNVTIMR DFSDM_FLT3CNVTIMR DFSDM conversion timer register 0x2B8 32 read-only n 0x0 0x0 CNVCNT CNVCNT 4 28 read-only DFSDM_FLT3CR1 DFSDM_FLT3CR1 DFSDM control register 1 0x280 32 read-write n 0x0 0x0 AWFSEL AWFSEL 30 1 read-write B_0x0 Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 0x0 B_0x1 Analog watchdog on channel transceivers value (after watchdog filter) 0x1 DFEN DFEN 0 1 read-write B_0x0 DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped. 0x0 B_0x1 DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting. 0x1 FAST FAST 29 1 read-write B_0x0 Fast conversion mode disabled 0x0 B_0x1 Fast conversion mode enabled 0x1 JDMAEN JDMAEN 5 1 read-write B_0x0 The DMA channel is not enabled to read injected data 0x0 B_0x1 The DMA channel is enabled to read injected data 0x1 JEXTEN JEXTEN 13 2 read-write B_0x0 Trigger detection is disabled 0x0 B_0x1 Each rising edge on the selected trigger makes a request to launch an injected conversion 0x1 B_0x2 Each falling edge on the selected trigger makes a request to launch an injected conversion 0x2 B_0x3 Both rising edges and falling edges on the selected trigger make requests to launch injected conversions 0x3 JEXTSEL JEXTSEL 8 3 read-write JSCAN JSCAN 4 1 read-write B_0x0 One channel conversion is performed from the injected channel group and next the selected channel from this group is selected. 0x0 B_0x1 The series of conversions for the injected group channels is executed, starting over with the lowest selected channel. 0x1 JSWSTART JSWSTART 1 1 write-only B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 makes a request to convert the channels in the injected conversion group, causing JCIP to become 1 at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing 1 has no effect if JSYNC=1. 0x1 JSYNC JSYNC 3 1 read-write B_0x0 Do not launch an injected conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger 0x1 RCH RCH 24 3 read-write B_0x0 Channel 0 is selected as the regular channel 0x0 B_0x1 Channel 1 is selected as the regular channel 0x1 B_0x7 Channel 7 is selected as the regular channel 0x7 RCONT RCONT 18 1 read-write B_0x0 The regular channel is converted just once for each conversion request 0x0 B_0x1 The regular channel is converted repeatedly after each conversion request 0x1 RDMAEN RDMAEN 21 1 read-write B_0x0 The DMA channel is not enabled to read regular data 0x0 B_0x1 The DMA channel is enabled to read regular data 0x1 RSWSTART RSWSTART 17 1 write-only B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 makes a request to start a conversion on the regular channel and causes RCIP to become 1 . If RCIP=1 already, writing to RSWSTART has no effect. Writing 1 has no effect if RSYNC=1. 0x1 RSYNC RSYNC 19 1 read-write B_0x0 Do not launch a regular conversion synchronously with DFSDM_FLT0 0x0 B_0x1 Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0 0x1 DFSDM_FLT3CR2 DFSDM_FLT3CR2 DFSDM control register 2 0x284 32 read-write n 0x0 0x0 AWDCH AWDCH 16 8 read-write AWDIE AWDIE 4 1 read-write B_0x0 Analog watchdog interrupt is disabled 0x0 B_0x1 Analog watchdog interrupt is enabled 0x1 CKABIE CKABIE 6 1 read-write B_0x0 Detection of channel input clock absence interrupt is disabled 0x0 B_0x1 Detection of channel input clock absence interrupt is enabled 0x1 EXCH EXCH 8 8 read-write JEOCIE JEOCIE 0 1 read-write B_0x0 Injected end of conversion interrupt is disabled 0x0 B_0x1 Injected end of conversion interrupt is enabled 0x1 JOVRIE JOVRIE 2 1 read-write B_0x0 Injected data overrun interrupt is disabled 0x0 B_0x1 Injected data overrun interrupt is enabled 0x1 REOCIE REOCIE 1 1 read-write B_0x0 Regular end of conversion interrupt is disabled 0x0 B_0x1 Regular end of conversion interrupt is enabled 0x1 ROVRIE ROVRIE 3 1 read-write B_0x0 Regular data overrun interrupt is disabled 0x0 B_0x1 Regular data overrun interrupt is enabled 0x1 SCDIE SCDIE 5 1 read-write B_0x0 short-circuit detector interrupt is disabled 0x0 B_0x1 short-circuit detector interrupt is enabled 0x1 DFSDM_FLT3EXMAX DFSDM_FLT3EXMAX DFSDM Extremes detector maximum register 0x2B0 32 read-only n 0x0 0x0 EXMAX EXMAX 8 24 read-only EXMAXCH EXMAXCH 0 3 read-only DFSDM_FLT3EXMIN DFSDM_FLT3EXMIN DFSDM Extremes detector minimum register 0x2B4 32 read-only n 0x0 0x0 EXMIN EXMIN 8 24 read-only EXMINCH EXMINCH 0 3 read-only DFSDM_FLT3FCR DFSDM_FLT3FCR DFSDM filter control register 0x294 32 read-write n 0x0 0x0 FORD FORD 29 3 read-write B_0x0 FastSinc filter type 0x0 B_0x1 Sinc1 filter type 0x1 B_0x2 Sinc2 filter type 0x2 B_0x3 Sinc3 filter type 0x3 B_0x4 Sinc4 filter type 0x4 B_0x5 Sinc5 filter type 0x5 FOSR FOSR 16 10 read-write IOSR IOSR 0 8 read-write DFSDM_FLT3ICR DFSDM_FLT3ICR DFSDM interrupt flag clear register 0x28C 32 read-write n 0x0 0x0 CLRCKABF CLRCKABF 16 8 read-write CLRJOVRF CLRJOVRF 2 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the JOVRF bit in the DFSDM_FLTxISR register 0x1 CLRROVRF CLRROVRF 3 1 read-write B_0x0 Writing 0 has no effect 0x0 B_0x1 Writing 1 clears the ROVRF bit in the DFSDM_FLTxISR register 0x1 CLRSCDF CLRSCDF 24 8 read-write DFSDM_FLT3ISR DFSDM_FLT3ISR DFSDM interrupt and status register 0x288 32 read-only n 0x0 0x0 AWDF AWDF 4 1 read-only B_0x0 No Analog watchdog event occurred 0x0 B_0x1 The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. 0x1 CKABF CKABF 16 8 read-only JCIP JCIP 13 1 read-only B_0x0 No request to convert the injected channel group (neither by software nor by trigger) has been issued 0x0 B_0x1 The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to 1 being written to JSWSTART or to a trigger detection 0x1 JEOCF JEOCF 0 1 read-only B_0x0 No injected conversion has completed 0x0 B_0x1 An injected conversion has completed and its data may be read 0x1 JOVRF JOVRF 2 1 read-only B_0x0 No injected conversion overrun has occurred 0x0 B_0x1 An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already 1 . JDATAR is not affected by overruns 0x1 RCIP RCIP 14 1 read-only B_0x0 No request to convert the regular channel has been issued 0x0 B_0x1 The conversion of the regular channel is in progress or a request for a regular conversion is pending 0x1 REOCF REOCF 1 1 read-only B_0x0 No regular conversion has completed 0x0 B_0x1 A regular conversion has completed and its data may be read 0x1 ROVRF ROVRF 3 1 read-only B_0x0 No regular conversion overrun has occurred 0x0 B_0x1 A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already 1 . RDATAR is not affected by overruns 0x1 SCDF SCDF 24 8 read-only DFSDM_FLT3JCHGR DFSDM_FLT3JCHGR DFSDM injected channel group selection register 0x290 32 read-write n 0x0 0x0 JCHG JCHG 0 8 read-write DFSDM_FLT3JDATAR DFSDM_FLT3JDATAR DFSDM data register for injected group 0x298 32 read-only n 0x0 0x0 JDATA JDATA 8 24 read-only JDATACH JDATACH 0 3 read-only DFSDM_FLT3RDATAR DFSDM_FLT3RDATAR DFSDM data register for the regular channel 0x29C 32 read-only n 0x0 0x0 RDATA RDATA 8 24 read-only RDATACH RDATACH 0 3 read-only RPEND RPEND 4 1 read-only DLYBQS DLYBQS DLYB 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 read-write SEN SEN 1 1 read-write DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DLYBSD1 DLYBQS DLYB 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 read-write SEN SEN 1 1 read-write DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DLYBSD2 DLYBQS DLYB 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 read-write SEN SEN 1 1 read-write DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DLYBSD3 DLYBQS DLYB 0x0 0x0 0x1000 registers n DLYB_CFGR DLYB_CFGR DLYB configuration register 0x4 32 read-write n 0x0 0x0 LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write DLYB_CR DLYB_CR DLYB control register 0x0 32 read-write n 0x0 0x0 DEN DEN 0 1 read-write SEN SEN 1 1 read-write DLYB_IPIDR DLYB_IPIDR DLYB IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only DLYB_SIDR DLYB_SIDR DLYB size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only DLYB_VERR DLYB_VERR DLYB IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only DMA1 DMA controller DMA 0x0 0x0 0x400 registers n HIFCR HIFCR high interrupt flag clear register 0xC 32 read-write n 0x0 0x0 CDMEIF4 Stream x clear direct mode error interrupt flag (x = 7..4) 2 1 CDMEIF5 Stream x clear direct mode error interrupt flag (x = 7..4) 8 1 CDMEIF6 Stream x clear direct mode error interrupt flag (x = 7..4) 18 1 CDMEIF7 Stream x clear direct mode error interrupt flag (x = 7..4) 24 1 CFEIF4 Stream x clear FIFO error interrupt flag (x = 7..4) 0 1 CFEIF5 Stream x clear FIFO error interrupt flag (x = 7..4) 6 1 CFEIF6 Stream x clear FIFO error interrupt flag (x = 7..4) 16 1 CFEIF7 Stream x clear FIFO error interrupt flag (x = 7..4) 22 1 CHTIF4 Stream x clear half transfer interrupt flag (x = 7..4) 4 1 CHTIF5 Stream x clear half transfer interrupt flag (x = 7..4) 10 1 CHTIF6 Stream x clear half transfer interrupt flag (x = 7..4) 20 1 CHTIF7 Stream x clear half transfer interrupt flag (x = 7..4) 26 1 CTCIF4 Stream x clear transfer complete interrupt flag (x = 7..4) 5 1 CTCIF5 Stream x clear transfer complete interrupt flag (x = 7..4) 11 1 CTCIF6 Stream x clear transfer complete interrupt flag (x = 7..4) 21 1 CTCIF7 Stream x clear transfer complete interrupt flag (x = 7..4) 27 1 CTEIF4 Stream x clear transfer error interrupt flag (x = 7..4) 3 1 CTEIF5 Stream x clear transfer error interrupt flag (x = 7..4) 9 1 CTEIF6 Stream x clear transfer error interrupt flag (x = 7..4) 19 1 CTEIF7 Stream x clear transfer error interrupt flag (x = 7..4) 25 1 HISR HISR high interrupt status register 0x4 32 read-only n 0x0 0x0 DMEIF4 Stream x direct mode error interrupt flag (x=7..4) 2 1 DMEIF5 Stream x direct mode error interrupt flag (x=7..4) 8 1 DMEIF6 Stream x direct mode error interrupt flag (x=7..4) 18 1 DMEIF7 Stream x direct mode error interrupt flag (x=7..4) 24 1 FEIF4 Stream x FIFO error interrupt flag (x=7..4) 0 1 FEIF5 Stream x FIFO error interrupt flag (x=7..4) 6 1 FEIF6 Stream x FIFO error interrupt flag (x=7..4) 16 1 FEIF7 Stream x FIFO error interrupt flag (x=7..4) 22 1 HTIF4 Stream x half transfer interrupt flag (x=7..4) 4 1 HTIF5 Stream x half transfer interrupt flag (x=7..4) 10 1 HTIF6 Stream x half transfer interrupt flag (x=7..4) 20 1 HTIF7 Stream x half transfer interrupt flag (x=7..4) 26 1 TCIF4 Stream x transfer complete interrupt flag (x=7..4) 5 1 TCIF5 Stream x transfer complete interrupt flag (x=7..4) 11 1 TCIF6 Stream x transfer complete interrupt flag (x=7..4) 21 1 TCIF7 Stream x transfer complete interrupt flag (x=7..4) 27 1 TEIF4 Stream x transfer error interrupt flag (x=7..4) 3 1 TEIF5 Stream x transfer error interrupt flag (x=7..4) 9 1 TEIF6 Stream x transfer error interrupt flag (x=7..4) 19 1 TEIF7 Stream x transfer error interrupt flag (x=7..4) 25 1 HWCFGR1 HWCFGR1 DMA hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 DMA_DEF0 DMA_DEF0 0 2 DMA_DEF1 DMA_DEF1 4 2 DMA_DEF2 DMA_DEF2 8 2 DMA_DEF3 DMA_DEF3 12 2 DMA_DEF4 DMA_DEF4 16 2 DMA_DEF5 DMA_DEF5 20 2 DMA_DEF6 DMA_DEF6 24 2 DMA_DEF7 DMA_DEF7 28 2 ID ID ID register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 LIFCR LIFCR low interrupt flag clear register 0x8 32 read-write n 0x0 0x0 CDMEIF0 Stream x clear direct mode error interrupt flag (x = 3..0) 2 1 CDMEIF1 Stream x clear direct mode error interrupt flag (x = 3..0) 8 1 CDMEIF2 Stream x clear direct mode error interrupt flag (x = 3..0) 18 1 CDMEIF3 Stream x clear direct mode error interrupt flag (x = 3..0) 24 1 CFEIF0 Stream x clear FIFO error interrupt flag (x = 3..0) 0 1 CFEIF1 Stream x clear FIFO error interrupt flag (x = 3..0) 6 1 CFEIF2 Stream x clear FIFO error interrupt flag (x = 3..0) 16 1 CFEIF3 Stream x clear FIFO error interrupt flag (x = 3..0) 22 1 CHTIF0 Stream x clear half transfer interrupt flag (x = 3..0) 4 1 CHTIF1 Stream x clear half transfer interrupt flag (x = 3..0) 10 1 CHTIF2 Stream x clear half transfer interrupt flag (x = 3..0) 20 1 CHTIF3 Stream x clear half transfer interrupt flag (x = 3..0) 26 1 CTCIF0 Stream x clear transfer complete interrupt flag (x = 3..0) 5 1 CTCIF1 Stream x clear transfer complete interrupt flag (x = 3..0) 11 1 CTCIF2 Stream x clear transfer complete interrupt flag (x = 3..0) 21 1 CTCIF3 Stream x clear transfer complete interrupt flag (x = 3..0) 27 1 CTEIF0 Stream x clear transfer error interrupt flag (x = 3..0) 3 1 CTEIF1 Stream x clear transfer error interrupt flag (x = 3..0) 9 1 CTEIF2 Stream x clear transfer error interrupt flag (x = 3..0) 19 1 CTEIF3 Stream x clear transfer error interrupt flag (x = 3..0) 25 1 LISR LISR low interrupt status register 0x0 32 read-only n 0x0 0x0 DMEIF0 Stream x direct mode error interrupt flag (x=3..0) 2 1 DMEIF1 Stream x direct mode error interrupt flag (x=3..0) 8 1 DMEIF2 Stream x direct mode error interrupt flag (x=3..0) 18 1 DMEIF3 Stream x direct mode error interrupt flag (x=3..0) 24 1 FEIF0 Stream x FIFO error interrupt flag (x=3..0) 0 1 FEIF1 Stream x FIFO error interrupt flag (x=3..0) 6 1 FEIF2 Stream x FIFO error interrupt flag (x=3..0) 16 1 FEIF3 Stream x FIFO error interrupt flag (x=3..0) 22 1 HTIF0 Stream x half transfer interrupt flag (x=3..0) 4 1 HTIF1 Stream x half transfer interrupt flag (x=3..0) 10 1 HTIF2 Stream x half transfer interrupt flag (x=3..0) 20 1 HTIF3 Stream x half transfer interrupt flag (x=3..0) 26 1 TCIF0 Stream x transfer complete interrupt flag (x = 3..0) 5 1 TCIF1 Stream x transfer complete interrupt flag (x = 3..0) 11 1 TCIF2 Stream x transfer complete interrupt flag (x = 3..0) 21 1 TCIF3 Stream x transfer complete interrupt flag (x = 3..0) 27 1 TEIF0 Stream x transfer error interrupt flag (x=3..0) 3 1 TEIF1 Stream x transfer error interrupt flag (x=3..0) 9 1 TEIF2 Stream x transfer error interrupt flag (x=3..0) 19 1 TEIF3 Stream x transfer error interrupt flag (x=3..0) 25 1 S0CR S0CR stream x configuration register 0x10 32 read-write n 0x0 0x0 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S0FCR S0FCR stream x FIFO control register 0x24 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S0M0AR S0M0AR stream x memory 0 address register 0x1C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S0M1AR S0M1AR stream x memory 1 address register 0x20 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S0NDTR S0NDTR stream x number of data register 0x14 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S0PAR S0PAR stream x peripheral address register 0x18 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S1CR S1CR stream x configuration register 0x28 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S1FCR S1FCR stream x FIFO control register 0x3C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S1M0AR S1M0AR stream x memory 0 address register 0x34 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S1M1AR S1M1AR stream x memory 1 address register 0x38 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S1NDTR S1NDTR stream x number of data register 0x2C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S1PAR S1PAR stream x peripheral address register 0x30 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S2CR S2CR stream x configuration register 0x40 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S2FCR S2FCR stream x FIFO control register 0x54 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S2M0AR S2M0AR stream x memory 0 address register 0x4C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S2M1AR S2M1AR stream x memory 1 address register 0x50 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S2NDTR S2NDTR stream x number of data register 0x44 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S2PAR S2PAR stream x peripheral address register 0x48 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S3CR S3CR stream x configuration register 0x58 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S3FCR S3FCR stream x FIFO control register 0x6C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S3M0AR S3M0AR stream x memory 0 address register 0x64 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S3M1AR S3M1AR stream x memory 1 address register 0x68 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S3NDTR S3NDTR stream x number of data register 0x5C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S3PAR S3PAR stream x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S4CR S4CR stream x configuration register 0x70 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S4FCR S4FCR stream x FIFO control register 0x84 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S4M0AR S4M0AR stream x memory 0 address register 0x7C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S4M1AR S4M1AR stream x memory 1 address register 0x80 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S4NDTR S4NDTR stream x number of data register 0x74 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S4PAR S4PAR stream x peripheral address register 0x78 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S5CR S5CR stream x configuration register 0x88 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S5FCR S5FCR stream x FIFO control register 0x9C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S5M0AR S5M0AR stream x memory 0 address register 0x94 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S5M1AR S5M1AR stream x memory 1 address register 0x98 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S5NDTR S5NDTR stream x number of data register 0x8C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S5PAR S5PAR stream x peripheral address register 0x90 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S6CR S6CR stream x configuration register 0xA0 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S6FCR S6FCR stream x FIFO control register 0xB4 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S6M0AR S6M0AR stream x memory 0 address register 0xAC 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S6M1AR S6M1AR stream x memory 1 address register 0xB0 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S6NDTR S6NDTR stream x number of data register 0xA4 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S6PAR S6PAR stream x peripheral address register 0xA8 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S7CR S7CR stream x configuration register 0xB8 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S7FCR S7FCR stream x FIFO control register 0xCC 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S7M0AR S7M0AR stream x memory 0 address register 0xC4 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S7M1AR S7M1AR stream x memory 1 address register 0xC8 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S7NDTR S7NDTR stream x number of data register 0xBC 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S7PAR S7PAR stream x peripheral address register 0xC0 32 read-write n 0x0 0x0 PA Peripheral address 0 32 SIDR SID size IDR register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR VERR version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DMA2 DMA controller DMA 0x0 0x0 0x400 registers n HIFCR HIFCR high interrupt flag clear register 0xC 32 read-write n 0x0 0x0 CDMEIF4 Stream x clear direct mode error interrupt flag (x = 7..4) 2 1 CDMEIF5 Stream x clear direct mode error interrupt flag (x = 7..4) 8 1 CDMEIF6 Stream x clear direct mode error interrupt flag (x = 7..4) 18 1 CDMEIF7 Stream x clear direct mode error interrupt flag (x = 7..4) 24 1 CFEIF4 Stream x clear FIFO error interrupt flag (x = 7..4) 0 1 CFEIF5 Stream x clear FIFO error interrupt flag (x = 7..4) 6 1 CFEIF6 Stream x clear FIFO error interrupt flag (x = 7..4) 16 1 CFEIF7 Stream x clear FIFO error interrupt flag (x = 7..4) 22 1 CHTIF4 Stream x clear half transfer interrupt flag (x = 7..4) 4 1 CHTIF5 Stream x clear half transfer interrupt flag (x = 7..4) 10 1 CHTIF6 Stream x clear half transfer interrupt flag (x = 7..4) 20 1 CHTIF7 Stream x clear half transfer interrupt flag (x = 7..4) 26 1 CTCIF4 Stream x clear transfer complete interrupt flag (x = 7..4) 5 1 CTCIF5 Stream x clear transfer complete interrupt flag (x = 7..4) 11 1 CTCIF6 Stream x clear transfer complete interrupt flag (x = 7..4) 21 1 CTCIF7 Stream x clear transfer complete interrupt flag (x = 7..4) 27 1 CTEIF4 Stream x clear transfer error interrupt flag (x = 7..4) 3 1 CTEIF5 Stream x clear transfer error interrupt flag (x = 7..4) 9 1 CTEIF6 Stream x clear transfer error interrupt flag (x = 7..4) 19 1 CTEIF7 Stream x clear transfer error interrupt flag (x = 7..4) 25 1 HISR HISR high interrupt status register 0x4 32 read-only n 0x0 0x0 DMEIF4 Stream x direct mode error interrupt flag (x=7..4) 2 1 DMEIF5 Stream x direct mode error interrupt flag (x=7..4) 8 1 DMEIF6 Stream x direct mode error interrupt flag (x=7..4) 18 1 DMEIF7 Stream x direct mode error interrupt flag (x=7..4) 24 1 FEIF4 Stream x FIFO error interrupt flag (x=7..4) 0 1 FEIF5 Stream x FIFO error interrupt flag (x=7..4) 6 1 FEIF6 Stream x FIFO error interrupt flag (x=7..4) 16 1 FEIF7 Stream x FIFO error interrupt flag (x=7..4) 22 1 HTIF4 Stream x half transfer interrupt flag (x=7..4) 4 1 HTIF5 Stream x half transfer interrupt flag (x=7..4) 10 1 HTIF6 Stream x half transfer interrupt flag (x=7..4) 20 1 HTIF7 Stream x half transfer interrupt flag (x=7..4) 26 1 TCIF4 Stream x transfer complete interrupt flag (x=7..4) 5 1 TCIF5 Stream x transfer complete interrupt flag (x=7..4) 11 1 TCIF6 Stream x transfer complete interrupt flag (x=7..4) 21 1 TCIF7 Stream x transfer complete interrupt flag (x=7..4) 27 1 TEIF4 Stream x transfer error interrupt flag (x=7..4) 3 1 TEIF5 Stream x transfer error interrupt flag (x=7..4) 9 1 TEIF6 Stream x transfer error interrupt flag (x=7..4) 19 1 TEIF7 Stream x transfer error interrupt flag (x=7..4) 25 1 HWCFGR1 HWCFGR1 DMA hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 DMA_DEF0 DMA_DEF0 0 2 DMA_DEF1 DMA_DEF1 4 2 DMA_DEF2 DMA_DEF2 8 2 DMA_DEF3 DMA_DEF3 12 2 DMA_DEF4 DMA_DEF4 16 2 DMA_DEF5 DMA_DEF5 20 2 DMA_DEF6 DMA_DEF6 24 2 DMA_DEF7 DMA_DEF7 28 2 ID ID ID register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 LIFCR LIFCR low interrupt flag clear register 0x8 32 read-write n 0x0 0x0 CDMEIF0 Stream x clear direct mode error interrupt flag (x = 3..0) 2 1 CDMEIF1 Stream x clear direct mode error interrupt flag (x = 3..0) 8 1 CDMEIF2 Stream x clear direct mode error interrupt flag (x = 3..0) 18 1 CDMEIF3 Stream x clear direct mode error interrupt flag (x = 3..0) 24 1 CFEIF0 Stream x clear FIFO error interrupt flag (x = 3..0) 0 1 CFEIF1 Stream x clear FIFO error interrupt flag (x = 3..0) 6 1 CFEIF2 Stream x clear FIFO error interrupt flag (x = 3..0) 16 1 CFEIF3 Stream x clear FIFO error interrupt flag (x = 3..0) 22 1 CHTIF0 Stream x clear half transfer interrupt flag (x = 3..0) 4 1 CHTIF1 Stream x clear half transfer interrupt flag (x = 3..0) 10 1 CHTIF2 Stream x clear half transfer interrupt flag (x = 3..0) 20 1 CHTIF3 Stream x clear half transfer interrupt flag (x = 3..0) 26 1 CTCIF0 Stream x clear transfer complete interrupt flag (x = 3..0) 5 1 CTCIF1 Stream x clear transfer complete interrupt flag (x = 3..0) 11 1 CTCIF2 Stream x clear transfer complete interrupt flag (x = 3..0) 21 1 CTCIF3 Stream x clear transfer complete interrupt flag (x = 3..0) 27 1 CTEIF0 Stream x clear transfer error interrupt flag (x = 3..0) 3 1 CTEIF1 Stream x clear transfer error interrupt flag (x = 3..0) 9 1 CTEIF2 Stream x clear transfer error interrupt flag (x = 3..0) 19 1 CTEIF3 Stream x clear transfer error interrupt flag (x = 3..0) 25 1 LISR LISR low interrupt status register 0x0 32 read-only n 0x0 0x0 DMEIF0 Stream x direct mode error interrupt flag (x=3..0) 2 1 DMEIF1 Stream x direct mode error interrupt flag (x=3..0) 8 1 DMEIF2 Stream x direct mode error interrupt flag (x=3..0) 18 1 DMEIF3 Stream x direct mode error interrupt flag (x=3..0) 24 1 FEIF0 Stream x FIFO error interrupt flag (x=3..0) 0 1 FEIF1 Stream x FIFO error interrupt flag (x=3..0) 6 1 FEIF2 Stream x FIFO error interrupt flag (x=3..0) 16 1 FEIF3 Stream x FIFO error interrupt flag (x=3..0) 22 1 HTIF0 Stream x half transfer interrupt flag (x=3..0) 4 1 HTIF1 Stream x half transfer interrupt flag (x=3..0) 10 1 HTIF2 Stream x half transfer interrupt flag (x=3..0) 20 1 HTIF3 Stream x half transfer interrupt flag (x=3..0) 26 1 TCIF0 Stream x transfer complete interrupt flag (x = 3..0) 5 1 TCIF1 Stream x transfer complete interrupt flag (x = 3..0) 11 1 TCIF2 Stream x transfer complete interrupt flag (x = 3..0) 21 1 TCIF3 Stream x transfer complete interrupt flag (x = 3..0) 27 1 TEIF0 Stream x transfer error interrupt flag (x=3..0) 3 1 TEIF1 Stream x transfer error interrupt flag (x=3..0) 9 1 TEIF2 Stream x transfer error interrupt flag (x=3..0) 19 1 TEIF3 Stream x transfer error interrupt flag (x=3..0) 25 1 S0CR S0CR stream x configuration register 0x10 32 read-write n 0x0 0x0 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S0FCR S0FCR stream x FIFO control register 0x24 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S0M0AR S0M0AR stream x memory 0 address register 0x1C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S0M1AR S0M1AR stream x memory 1 address register 0x20 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S0NDTR S0NDTR stream x number of data register 0x14 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S0PAR S0PAR stream x peripheral address register 0x18 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S1CR S1CR stream x configuration register 0x28 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S1FCR S1FCR stream x FIFO control register 0x3C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S1M0AR S1M0AR stream x memory 0 address register 0x34 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S1M1AR S1M1AR stream x memory 1 address register 0x38 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S1NDTR S1NDTR stream x number of data register 0x2C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S1PAR S1PAR stream x peripheral address register 0x30 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S2CR S2CR stream x configuration register 0x40 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S2FCR S2FCR stream x FIFO control register 0x54 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S2M0AR S2M0AR stream x memory 0 address register 0x4C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S2M1AR S2M1AR stream x memory 1 address register 0x50 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S2NDTR S2NDTR stream x number of data register 0x44 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S2PAR S2PAR stream x peripheral address register 0x48 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S3CR S3CR stream x configuration register 0x58 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S3FCR S3FCR stream x FIFO control register 0x6C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S3M0AR S3M0AR stream x memory 0 address register 0x64 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S3M1AR S3M1AR stream x memory 1 address register 0x68 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S3NDTR S3NDTR stream x number of data register 0x5C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S3PAR S3PAR stream x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S4CR S4CR stream x configuration register 0x70 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S4FCR S4FCR stream x FIFO control register 0x84 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S4M0AR S4M0AR stream x memory 0 address register 0x7C 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S4M1AR S4M1AR stream x memory 1 address register 0x80 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S4NDTR S4NDTR stream x number of data register 0x74 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S4PAR S4PAR stream x peripheral address register 0x78 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S5CR S5CR stream x configuration register 0x88 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S5FCR S5FCR stream x FIFO control register 0x9C 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S5M0AR S5M0AR stream x memory 0 address register 0x94 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S5M1AR S5M1AR stream x memory 1 address register 0x98 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S5NDTR S5NDTR stream x number of data register 0x8C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S5PAR S5PAR stream x peripheral address register 0x90 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S6CR S6CR stream x configuration register 0xA0 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S6FCR S6FCR stream x FIFO control register 0xB4 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S6M0AR S6M0AR stream x memory 0 address register 0xAC 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S6M1AR S6M1AR stream x memory 1 address register 0xB0 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S6NDTR S6NDTR stream x number of data register 0xA4 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S6PAR S6PAR stream x peripheral address register 0xA8 32 read-write n 0x0 0x0 PA Peripheral address 0 32 S7CR S7CR stream x configuration register 0xB8 32 read-write n 0x0 0x0 ACK ACK 20 1 CIRC Circular mode 8 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 DIR Data transfer direction 6 2 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 HTIE Half transfer interrupt enable 3 1 MBURST Memory burst transfer configuration 23 2 MINC Memory increment mode 10 1 MSIZE Memory data size 13 2 PBURST Peripheral burst transfer configuration 21 2 PFCTRL Peripheral flow controller 5 1 PINC Peripheral increment mode 9 1 PINCOS Peripheral increment offset size 15 1 PL Priority level 16 2 PSIZE Peripheral data size 11 2 TCIE Transfer complete interrupt enable 4 1 TEIE Transfer error interrupt enable 2 1 S7FCR S7FCR stream x FIFO control register 0xCC 32 read-write n 0x0 0x0 DMDIS Direct mode disable 2 1 read-write FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only FTH FIFO threshold selection 0 2 read-write S7M0AR S7M0AR stream x memory 0 address register 0xC4 32 read-write n 0x0 0x0 M0A Memory 0 address 0 32 S7M1AR S7M1AR stream x memory 1 address register 0xC8 32 read-write n 0x0 0x0 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S7NDTR S7NDTR stream x number of data register 0xBC 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 S7PAR S7PAR stream x peripheral address register 0xC0 32 read-write n 0x0 0x0 PA Peripheral address 0 32 SIDR SID size IDR register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR VERR version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DMAMUX1 DMAMUX1 DMAMUX1 0x0 0x0 0x400 registers n C0CR DMAMUX1_C0CR DMAMUX1 request line multiplexer channel 0 configuration register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C10CR DMAMUX1_C10CR DMAMUX1 request line multiplexer channel 10 configuration register 0x28 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C11CR DMAMUX1_C11CR DMAMUX1 request line multiplexer channel 11 configuration register 0x2C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C12CR DMAMUX1_C12CR DMAMUX1 request line multiplexer channel 12 configuration register 0x30 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C13CR DMAMUX1_C13CR DMAMUX1 request line multiplexer channel 13 configuration register 0x34 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C14CR DMAMUX1_C14CR DMAMUX1 request line multiplexer channel 14 configuration register 0x38 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C15CR DMAMUX1_C15CR DMAMUX1 request line multiplexer channel 15 configuration register 0x3C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C1CR DMAMUX1_C1CR DMAMUX1 request line multiplexer channel 1 configuration register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C2CR DMAMUX1_C2CR DMAMUX1 request line multiplexer channel 2 configuration register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C3CR DMAMUX1_C3CR DMAMUX1 request line multiplexer channel 3 configuration register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C4CR DMAMUX1_C4CR DMAMUX1 request line multiplexer channel 4 configuration register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C5CR DMAMUX1_C5CR DMAMUX1 request line multiplexer channel 5 configuration register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C6CR DMAMUX1_C6CR DMAMUX1 request line multiplexer channel 6 configuration register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C7CR DMAMUX1_C7CR DMAMUX1 request line multiplexer channel 7 configuration register 0x1C 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C8CR DMAMUX1_C8CR DMAMUX1 request line multiplexer channel 8 configuration register 0x20 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write C9CR DMAMUX1_C9CR DMAMUX1 request line multiplexer channel 9 configuration register 0x24 32 read-write n 0x0 0x0 DMAREQ_ID DMAREQ_ID 0 7 read-write EGE EGE 9 1 read-write B_0x0 event generation disabled 0x0 B_0x1 event generation enabled 0x1 NBREQ NBREQ 19 5 read-write SE SE 16 1 read-write B_0x0 synchronization disabled 0x0 B_0x1 synchronization enabled 0x1 SOIE SOIE 8 1 read-write B_0x0 interrupt disabled 0x0 B_0x1 interrupt enabled 0x1 SPOL SPOL 17 2 read-write B_0x0 no event. I.e. None synchronization nor detection. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 SYNC_ID SYNC_ID 24 5 read-write CFR DMAMUX1_CFR DMAMUX1 request line multiplexer interrupt clear flag register 0x84 32 read-write n 0x0 0x0 CSOF0 CSOF0 0 1 write-only CSOF1 CSOF1 1 1 write-only CSOF10 CSOF10 10 1 write-only CSOF11 CSOF11 11 1 write-only CSOF12 CSOF12 12 1 write-only CSOF13 CSOF13 13 1 write-only CSOF14 CSOF14 14 1 write-only CSOF15 CSOF15 15 1 write-only CSOF2 CSOF2 2 1 write-only CSOF3 CSOF3 3 1 write-only CSOF4 CSOF4 4 1 write-only CSOF5 CSOF5 5 1 write-only CSOF6 CSOF6 6 1 write-only CSOF7 CSOF7 7 1 write-only CSOF8 CSOF8 8 1 write-only CSOF9 CSOF9 9 1 write-only CSR DMAMUX1_CSR DMAMUX1 request line multiplexer interrupt channel status register 0x80 32 read-only n 0x0 0x0 SOF0 SOF0 0 1 read-only SOF1 SOF1 1 1 read-only SOF10 SOF10 10 1 read-only SOF11 SOF11 11 1 read-only SOF12 SOF12 12 1 read-only SOF13 SOF13 13 1 read-only SOF14 SOF14 14 1 read-only SOF15 SOF15 15 1 read-only SOF2 SOF2 2 1 read-only SOF3 SOF3 3 1 read-only SOF4 SOF4 4 1 read-only SOF5 SOF5 5 1 read-only SOF6 SOF6 6 1 read-only SOF7 SOF7 7 1 read-only SOF8 SOF8 8 1 read-only SOF9 SOF9 9 1 read-only HWCFGR1 DMAMUX_HWCFGR1 DMAMUX hardware configuration 1 register 0x3F0 32 read-only n 0x0 0x0 NUM_DMA_PERIPH_REQ NUM_DMA_PERIPH_REQ 8 8 NUM_DMA_REQGEN NUM_DMA_REQGEN 24 8 NUM_DMA_STREAMS NUM_DMA_STREAMS 0 8 NUM_DMA_TRIG NUM_DMA_TRIG 16 8 HWCFGR2 DMAMUX_HWCFGR2 DMAMUX hardware configuration 2 register 0x3EC 32 read-only n 0x0 0x0 NUM_DMA_EXT_REQ NUM_DMA_EXT_REQ 0 8 IPIDR DMAMUX_IPIDR DMAMUX IP Version Register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 RG0CR DMAMUX1_RG0CR DMAMUX1 request generator channel 0 configuration register 0x100 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG1CR DMAMUX1_RG1CR DMAMUX1 request generator channel 1 configuration register 0x104 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG2CR DMAMUX1_RG2CR DMAMUX1 request generator channel 2 configuration register 0x108 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG3CR DMAMUX1_RG3CR DMAMUX1 request generator channel 3 configuration register 0x10C 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG4CR DMAMUX1_RG4CR DMAMUX1 request generator channel 4 configuration register 0x110 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG5CR DMAMUX1_RG5CR DMAMUX1 request generator channel 5 configuration register 0x114 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG6CR DMAMUX1_RG6CR DMAMUX1 request generator channel 6 configuration register 0x118 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RG7CR DMAMUX1_RG7CR DMAMUX1 request generator channel 7 configuration register 0x11C 32 read-write n 0x0 0x0 GE GE 16 1 read-write B_0x0 DMA request generator channel x disabled 0x0 B_0x1 DMA request generator channel x enabled 0x1 GNBREQ GNBREQ 19 5 read-write GPOL GPOL 17 2 read-write B_0x0 no event. I.e. none trigger detection nor generation. 0x0 B_0x1 rising edge 0x1 B_0x2 falling edge 0x2 B_0x3 rising and falling edge 0x3 OIE OIE 8 1 read-write B_0x0 interrupt on a trigger overrun event occurrence is disabled 0x0 B_0x1 interrupt on a trigger overrun event occurrence is enabled 0x1 SIG_ID SIG_ID 0 3 read-write RGCFR DMAMUX1_RGCFR DMAMUX1 request generator interrupt clear flag register 0x144 32 read-only n 0x0 0x0 COF0 COF0 0 1 read-only COF1 COF1 1 1 read-only COF2 COF2 2 1 read-only COF3 COF3 3 1 read-only COF4 COF4 4 1 read-only COF5 COF5 5 1 read-only COF6 COF6 6 1 read-only COF7 COF7 7 1 read-only RGSR DMAMUX1_RGSR DMAMUX1 request generator interrupt status register 0x140 32 read-only n 0x0 0x0 OF0 OF0 0 1 read-only OF1 OF1 1 1 read-only OF2 OF2 2 1 read-only OF3 OF3 3 1 read-only OF4 OF4 4 1 read-only OF5 OF5 5 1 read-only OF6 OF6 6 1 read-only OF7 OF7 7 1 read-only SIDR DMAMUX_SIDR DMAMUX IP Version Register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR DMAMUX_VERR DMAMUX IP Version Register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 DSI DSI Host DSI 0x0 0x0 0x800 registers n CCR DSI_CCR DSI Host clock control register 0x8 32 read-write n 0x0 0x0 TOCKDIV TOCKDIV 8 8 read-write TXECKDIV TXECKDIV 0 8 read-write CLCR DSI_CLCR DSI Host clock lane configuration register 0x94 32 read-write n 0x0 0x0 ACR ACR 1 1 read-write DPCC DPCC 0 1 read-write CLTCR DSI_CLTCR DSI Host clock lane timer configuration register 0x98 32 read-write n 0x0 0x0 HS2LP_TIME HS2LP_TIME 16 10 read-write LP2HS_TIME LP2HS_TIME 0 10 read-write CMCR DSI_CMCR DSI Host command mode configuration register 0x68 32 read-write n 0x0 0x0 ARE ARE 1 1 read-write DLWTX DLWTX 19 1 read-write DSR0TX DSR0TX 18 1 read-write DSW0TX DSW0TX 16 1 read-write DSW1TX DSW1TX 17 1 read-write GLWTX GLWTX 14 1 read-write GSR0TX GSR0TX 11 1 read-write GSR1TX GSR1TX 12 1 read-write GSR2TX GSR2TX 13 1 read-write GSW0TX GSW0TX 8 1 read-write GSW1TX GSW1TX 9 1 read-write GSW2TX GSW2TX 10 1 read-write MRDPS MRDPS 24 1 read-write TEARE TEARE 0 1 read-write CR DSI_CR DSI Host control register 0x4 32 read-write n 0x0 0x0 EN EN 0 1 read-write DLTCR DSI_DLTCR DSI Host data lane timer configuration register 0x9C 32 read-write n 0x0 0x0 HS2LP_TIME HS2LP_TIME 16 10 read-write LP2HS_TIME LP2HS_TIME 0 10 read-write DLTRCR DSI_DLTRCR DSI Host data lane timer read configuration register 0xF4 32 read-write n 0x0 0x0 MRD_TIME MRD_TIME 0 15 read-write FIR0 DSI_FIR0 DSI Host force interrupt register 0 0xD8 32 read-write n 0x0 0x0 FAE0 FAE0 0 1 write-only FAE1 FAE1 1 1 write-only FAE10 FAE10 10 1 write-only FAE11 FAE11 11 1 write-only FAE12 FAE12 12 1 write-only FAE13 FAE13 13 1 write-only FAE14 FAE14 14 1 write-only FAE15 FAE15 15 1 write-only FAE2 FAE2 2 1 write-only FAE3 FAE3 3 1 write-only FAE4 FAE4 4 1 write-only FAE5 FAE5 5 1 write-only FAE6 FAE6 6 1 write-only FAE7 FAE7 7 1 write-only FAE8 FAE8 8 1 write-only FAE9 FAE9 9 1 write-only FPE0 FPE0 16 1 write-only FPE1 FPE1 17 1 write-only FPE2 FPE2 18 1 write-only FPE3 FPE3 19 1 write-only FPE4 FPE4 20 1 write-only FIR1 DSI_FIR1 DSI Host force interrupt register 1 0xDC 32 read-write n 0x0 0x0 FCRCE FCRCE 4 1 write-only FECCME FECCME 3 1 write-only FECCSE FECCSE 2 1 write-only FEOTPE FEOTPE 6 1 write-only FGCWRE FGCWRE 8 1 write-only FGPRDE FGPRDE 11 1 write-only FGPRXE FGPRXE 12 1 write-only FGPTXE FGPTXE 10 1 write-only FGPWRE FGPWRE 9 1 write-only FLPWRE FLPWRE 7 1 write-only FPSE FPSE 5 1 write-only FTOHSTX FTOHSTX 0 1 write-only FTOLPRX FTOLPRX 1 1 write-only GHCR DSI_GHCR DSI Host generic header configuration register 0x6C 32 read-write n 0x0 0x0 DT DT 0 6 read-write VCID VCID 6 2 read-write WCLSB WCLSB 8 8 read-write WCMSB WCMSB 16 8 read-write GPDR DSI_GPDR DSI Host generic payload data register 0x70 32 read-write n 0x0 0x0 DATA1 DATA1 0 8 read-write DATA2 DATA2 8 8 read-write DATA3 DATA3 16 8 read-write DATA4 DATA4 24 8 read-write GPSR DSI_GPSR DSI Host generic packet status register 0x74 32 read-only n 0x0 0x0 CMDFE CMDFE 0 1 read-only CMDFF CMDFF 1 1 read-only PRDFE PRDFE 4 1 read-only PRDFF PRDFF 5 1 read-only PWRFE PWRFE 2 1 read-only PWRFF PWRFF 3 1 read-only RCB RCB 6 1 read-only GVCIDR DSI_GVCIDR DSI Host generic VCID register 0x30 32 read-only n 0x0 0x0 VCID VCID 0 2 read-only HWCFGR DSI_HWCFGR DSI Host hardware configuration register 0x7F0 32 read-only n 0x0 0x0 FIFOSIZE FIFOSIZE 4 12 read-only TECHNO TECHNO 0 4 read-only IER0 DSI_IER0 DSI Host interrupt enable register 0 0xC4 32 read-write n 0x0 0x0 AE0IE AE0IE 0 1 read-write AE10IE AE10IE 10 1 read-write AE11IE AE11IE 11 1 read-write AE12IE AE12IE 12 1 read-write AE13IE AE13IE 13 1 read-write AE14IE AE14IE 14 1 read-write AE15IE AE15IE 15 1 read-write AE1IE AE1IE 1 1 read-write AE2IE AE2IE 2 1 read-write AE3IE AE3IE 3 1 read-write AE4IE AE4IE 4 1 read-write AE5IE AE5IE 5 1 read-write AE6IE AE6IE 6 1 read-write AE7IE AE7IE 7 1 read-write AE8IE AE8IE 8 1 read-write AE9IE AE9IE 9 1 read-write PE0IE PE0IE 16 1 read-write PE1IE PE1IE 17 1 read-write PE2IE PE2IE 18 1 read-write PE3IE PE3IE 19 1 read-write PE4IE PE4IE 20 1 read-write IER1 DSI_IER1 DSI Host interrupt enable register 1 0xC8 32 read-write n 0x0 0x0 CRCEIE CRCEIE 4 1 read-write ECCMEIE ECCMEIE 3 1 read-write ECCSEIE ECCSEIE 2 1 read-write EOTPEIE EOTPEIE 6 1 read-write GCWREIE GCWREIE 8 1 read-write GPRDEIE GPRDEIE 11 1 read-write GPRXEIE GPRXEIE 12 1 read-write GPTXEIE GPTXEIE 10 1 read-write GPWREIE GPWREIE 9 1 read-write LPWREIE LPWREIE 7 1 read-write PSEIE PSEIE 5 1 read-write TOHSTXIE TOHSTXIE 0 1 read-write TOLPRXIE TOLPRXIE 1 1 read-write IPIDR DSI_IPIDR DSI Host identification register 0x7F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only ISR0 DSI_ISR0 DSI Host interrupt and status register 0 0xBC 32 read-only n 0x0 0x0 AE0 AE0 0 1 read-only AE1 AE1 1 1 read-only AE10 AE10 10 1 read-only AE11 AE11 11 1 read-only AE12 AE12 12 1 read-only AE13 AE13 13 1 read-only AE14 AE14 14 1 read-only AE15 AE15 15 1 read-only AE2 AE2 2 1 read-only AE3 AE3 3 1 read-only AE4 AE4 4 1 read-only AE5 AE5 5 1 read-only AE6 AE6 6 1 read-only AE7 AE7 7 1 read-only AE8 AE8 8 1 read-only AE9 AE9 9 1 read-only PE0 PE0 16 1 read-only PE1 PE1 17 1 read-only PE2 PE2 18 1 read-only PE3 PE3 19 1 read-only PE4 PE4 20 1 read-only ISR1 DSI_ISR1 DSI Host interrupt and status register 1 0xC0 32 read-only n 0x0 0x0 CRCE CRCE 4 1 read-only ECCME ECCME 3 1 read-only ECCSE ECCSE 2 1 read-only EOTPE EOTPE 6 1 read-only GCWRE GCWRE 8 1 read-only GPRDE GPRDE 11 1 read-only GPRXE GPRXE 12 1 read-only GPTXE GPTXE 10 1 read-only GPWRE GPWRE 9 1 read-only LPWRE LPWRE 7 1 read-only PSE PSE 5 1 read-only TOHSTX TOHSTX 0 1 read-only TOLPRX TOLPRX 1 1 read-only LCCCR DSI_LCCCR DSI Host LTDC current color coding register 0x110 32 read-only n 0x0 0x0 COLC COLC 0 4 read-only LPE LPE 8 1 read-only LCCR DSI_LCCR DSI Host LTDC command configuration register 0x64 32 read-write n 0x0 0x0 CMDSIZE CMDSIZE 0 16 read-write LCOLCR DSI_LCOLCR DSI Host LTDC color coding register 0x10 32 read-write n 0x0 0x0 COLC COLC 0 4 read-write LPE LPE 8 1 read-write LCVCIDR DSI_LCVCIDR DSI Host LTDC current VCID register 0x10C 32 read-write n 0x0 0x0 VCID VCID 0 2 read-write LPCR DSI_LPCR DSI Host LTDC polarity configuration register 0x14 32 read-write n 0x0 0x0 DEP DEP 0 1 read-write HSP HSP 2 1 read-write VSP VSP 1 1 read-write LPMCCR DSI_LPMCCR DSI Host low-power mode current configuration register 0x118 32 read-only n 0x0 0x0 LPSIZE LPSIZE 16 8 read-only VLPSIZE VLPSIZE 0 8 read-only LPMCR DSI_LPMCR DSI Host low-power mode configuration register 0x18 32 read-write n 0x0 0x0 LPSIZE LPSIZE 16 8 read-write VLPSIZE VLPSIZE 0 8 read-write LVCIDR DSI_LVCIDR DSI Host LTDC VCID register 0xC 32 read-write n 0x0 0x0 VCID VCID 0 2 read-write MCR DSI_MCR DSI Host mode configuration register 0x34 32 read-write n 0x0 0x0 CMDM CMDM 0 1 read-write PCONFR DSI_PCONFR DSI Host PHY configuration register 0xA4 32 read-write n 0x0 0x0 NL NL 0 2 read-write SW_TIME SW_TIME 8 8 read-write PCR DSI_PCR DSI Host protocol configuration register 0x2C 32 read-write n 0x0 0x0 BTAE BTAE 2 1 read-write CRCRXE CRCRXE 4 1 read-write ECCRXE ECCRXE 3 1 read-write ETRXE ETRXE 1 1 read-write ETTXE ETTXE 0 1 read-write PCTLR DSI_PCTLR DSI Host PHY control register 0xA0 32 read-write n 0x0 0x0 CKE CKE 2 1 read-write DEN DEN 1 1 read-write PSR DSI_PSR DSI Host PHY status register 0xB0 32 read-only n 0x0 0x0 PD PD 1 1 read-only PSS0 PSS0 4 1 read-only PSS1 PSS1 7 1 read-only PSSC PSSC 2 1 read-only RUE0 RUE0 6 1 read-only UAN0 UAN0 5 1 read-only UAN1 UAN1 8 1 read-only UANC UANC 3 1 read-only PTTCR DSI_PTTCR DSI Host PHY TX triggers configuration register 0xAC 32 read-write n 0x0 0x0 TX_TRIG TX_TRIG 0 4 read-write PUCR DSI_PUCR DSI Host PHY ULPS control register 0xA8 32 read-write n 0x0 0x0 UECL UECL 1 1 read-write UEDL UEDL 3 1 read-write URCL URCL 0 1 read-write URDL URDL 2 1 read-write SIDR DSI_SIDR DSI Host size identification register 0x7FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only TCCR0 DSI_TCCR0 DSI Host timeout counter configuration register 0 0x78 32 read-write n 0x0 0x0 HSTX_TOCNT HSTX_TOCNT 16 16 read-write LPRX_TOCNT LPRX_TOCNT 0 16 read-write TCCR1 DSI_TCCR1 DSI Host timeout counter configuration register 1 0x7C 32 read-write n 0x0 0x0 HSRD_TOCNT HSRD_TOCNT 0 16 read-write TCCR2 DSI_TCCR2 DSI Host timeout counter configuration register 2 0x80 32 read-write n 0x0 0x0 LPRD_TOCNT LPRD_TOCNT 0 16 read-write TCCR3 DSI_TCCR3 DSI Host timeout counter configuration register 3 0x84 32 read-write n 0x0 0x0 HSWR_TOCNT HSWR_TOCNT 0 16 read-write PM PM 24 1 read-write TCCR4 DSI_TCCR4 DSI Host timeout counter configuration register 4 0x88 32 read-write n 0x0 0x0 LPWR_TOCNT LPWR_TOCNT 0 16 read-write TCCR5 DSI_TCCR5 DSI Host timeout counter configuration register 5 0x8C 32 read-write n 0x0 0x0 BTA_TOCNT BTA_TOCNT 0 16 read-write VCCCR DSI_VCCCR DSI Host video chunks current configuration register 0x140 32 read-only n 0x0 0x0 NUMC NUMC 0 13 read-only VCCR DSI_VCCR DSI Host video chunks configuration register 0x40 32 read-write n 0x0 0x0 NUMC NUMC 0 13 read-write VERR DSI_VERR DSI Host version register 0x7F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only VHBPCCR DSI_VHBPCCR DSI Host video HBP current configuration register 0x14C 32 read-only n 0x0 0x0 HBP HBP 0 12 read-only VHBPCR DSI_VHBPCR DSI Host video HBP configuration register 0x4C 32 read-write n 0x0 0x0 HBP HBP 0 12 read-write VHSACCR DSI_VHSACCR DSI Host video HSA current configuration register 0x148 32 read-only n 0x0 0x0 HSA HSA 0 12 read-only VHSACR DSI_VHSACR DSI Host video HSA configuration register 0x48 32 read-write n 0x0 0x0 HSA HSA 0 12 read-write VLCCR DSI_VLCCR DSI Host video line current configuration register 0x150 32 read-only n 0x0 0x0 HLINE HLINE 0 15 read-only VLCR DSI_VLCR DSI Host video line configuration register 0x50 32 read-write n 0x0 0x0 HLINE HLINE 0 15 read-write VMCCR DSI_VMCCR DSI Host video mode current configuration register 0x138 32 read-only n 0x0 0x0 FBTAAE FBTAAE 8 1 read-only LPCE LPCE 9 1 read-only LPHBPE LPHBPE 6 1 read-only LPHFE LPHFE 7 1 read-only LPVAE LPVAE 5 1 read-only LPVBPE LPVBPE 3 1 read-only LPVFPE LPVFPE 4 1 read-only LPVSAE LPVSAE 2 1 read-only VMT VMT 0 2 read-only VMCR DSI_VMCR DSI Host video mode configuration register 0x38 32 read-write n 0x0 0x0 FBTAAE FBTAAE 14 1 read-write LPCE LPCE 15 1 read-write LPHBPE LPHBPE 12 1 read-write LPHFPE LPHFPE 13 1 read-write LPVAE LPVAE 11 1 read-write LPVBPE LPVBPE 9 1 read-write LPVFPE LPVFPE 10 1 read-write LPVSAE LPVSAE 8 1 read-write PGE PGE 16 1 read-write PGM PGM 20 1 read-write PGO PGO 24 1 read-write VMT VMT 0 2 read-write VNPCCR DSI_VNPCCR DSI Host video null packet current configuration register 0x144 32 read-only n 0x0 0x0 NPSIZE NPSIZE 0 13 read-only VNPCR DSI_VNPCR DSI Host video null packet configuration register 0x44 32 read-write n 0x0 0x0 NPSIZE NPSIZE 0 13 read-write VPCCR DSI_VPCCR DSI Host video packet current configuration register 0x13C 32 read-only n 0x0 0x0 VPSIZE VPSIZE 0 14 read-only VPCR DSI_VPCR DSI Host video packet configuration register 0x3C 32 read-write n 0x0 0x0 VPSIZE VPSIZE 0 14 read-write VR DSI_VR DSI Host version register 0x0 32 read-only n 0x0 0x0 VERSION VERSION 0 32 read-only VSCR DSI_VSCR DSI Host video shadow control register 0x100 32 read-write n 0x0 0x0 EN EN 0 1 read-write UR UR 8 1 read-write VVACCR DSI_VVACCR DSI Host video VA current configuration register 0x160 32 read-only n 0x0 0x0 VA VA 0 14 read-only VVACR DSI_VVACR DSI Host video VA configuration register 0x60 32 read-write n 0x0 0x0 VA VA 0 14 read-write VVBPCCR DSI_VVBPCCR DSI Host video VBP current configuration register 0x158 32 read-only n 0x0 0x0 VBP VBP 0 10 read-only VVBPCR DSI_VVBPCR DSI Host video VBP configuration register 0x58 32 read-write n 0x0 0x0 VBP VBP 0 10 read-write VVFPCCR DSI_VVFPCCR DSI Host video VFP current configuration register 0x15C 32 read-only n 0x0 0x0 VFP VFP 0 10 read-only VVFPCR DSI_VVFPCR DSI Host video VFP configuration register 0x5C 32 read-write n 0x0 0x0 VFP VFP 0 10 read-write VVSACCR DSI_VVSACCR DSI Host video VSA current configuration register 0x154 32 read-only n 0x0 0x0 VSA VSA 0 10 read-only VVSACR DSI_VVSACR DSI Host video VSA configuration register 0x54 32 read-write n 0x0 0x0 VSA VSA 0 10 read-write WCFGR DSI_WCFGR DSI wrapper configuration register 0x400 32 read-write n 0x0 0x0 AR AR 6 1 read-write COLMUX COLMUX 1 3 read-write DSIM DSIM 0 1 read-write TEPOL TEPOL 5 1 read-write TESRC TESRC 4 1 read-write VSPOL VSPOL 7 1 read-write WCR DSI_WCR DSI wrapper control register 0x404 32 read-write n 0x0 0x0 COLM COLM 0 1 read-write DSIEN DSIEN 3 1 read-write LTDCEN LTDCEN 2 1 read-write SHTDN SHTDN 1 1 read-write WIER DSI_WIER DSI wrapper interrupt enable register 0x408 32 read-write n 0x0 0x0 ERIE ERIE 1 1 read-write PLLLIE PLLLIE 9 1 read-write PLLUIE PLLUIE 10 1 read-write RRIE RRIE 13 1 read-write TEIE TEIE 0 1 read-write WIFCR DSI_WIFCR DSI wrapper interrupt flag clear register 0x410 32 read-write n 0x0 0x0 CERIF CERIF 1 1 write-only CPLLLIF CPLLLIF 9 1 write-only CPLLUIF CPLLUIF 10 1 write-only CRRIF CRRIF 13 1 write-only CTEIF CTEIF 0 1 write-only WISR DSI_WISR DSI wrapper interrupt and status register 0x40C 32 read-only n 0x0 0x0 BUSY BUSY 2 1 read-only ERIF ERIF 1 1 read-only PLLLIF PLLLIF 9 1 read-only PLLLS PLLLS 8 1 read-only PLLUIF PLLUIF 10 1 read-only RRIF RRIF 13 1 read-only RRS RRS 12 1 read-only TEIF TEIF 0 1 read-only WPCR0 DSI_WPCR0 DSI wrapper PHY configuration register 0 0x418 32 read-write n 0x0 0x0 CDOFFDL CDOFFDL 14 1 read-write FTXSMCL FTXSMCL 12 1 read-write FTXSMDL FTXSMDL 13 1 read-write HSICL HSICL 9 1 read-write HSIDL0 HSIDL0 10 1 read-write HSIDL1 HSIDL1 11 1 read-write SWCL SWCL 6 1 read-write SWDL0 SWDL0 7 1 read-write SWDL1 SWDL1 8 1 read-write TDDL TDDL 16 1 read-write UIX4 UIX4 0 6 read-write WPCR1 DSI_WPCR1 This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). 0x41C 32 read-write n 0x0 0x0 HSTXSRDCL HSTXSRDCL 17 1 read-write HSTXSRDDL HSTXSRDDL 19 1 read-write HSTXSRUCL HSTXSRUCL 16 1 read-write HSTXSRUDL HSTXSRUDL 18 1 read-write LPTXSRCL LPTXSRCL 6 2 read-write LPTXSRDL LPTXSRDL 8 2 read-write SDDCCL SDDCCL 12 1 read-write SDDCDL SDDCDL 13 1 read-write SKEWCL SKEWCL 0 2 read-write SKEWDL SKEWDL 2 2 read-write WRPCR DSI_WRPCR DSI wrapper regulator and PLL control register 0x430 32 read-write n 0x0 0x0 BGREN BGREN 28 1 read-write IDF IDF 11 4 read-write NDIV NDIV 2 7 read-write ODF ODF 16 2 read-write PLLEN PLLEN 0 1 read-write REGEN REGEN 24 1 read-write ETH_DMA ETH_DMA Ethernet 0x0 0x0 0x400 registers n ETH_DMAA4DACR ETH_DMAA4DACR AXI4 descriptor ACE control register 0x28 32 read-write n 0x0 0x0 RDP RDP 16 3 RDRC RDRC 8 4 TDWC TDWC 0 4 TDWD TDWD 4 2 WRP WRP 20 3 ETH_DMAA4RxACR ETH_DMAA4RxACR AXI4 receive channel ACE control register 0x24 32 read-write n 0x0 0x0 RDC RDC 24 2 RDWC RDWC 0 4 RHC RHC 16 4 RPC RPC 8 4 ETH_DMAA4TxACR ETH_DMAA4TxACR AXI4 transmit channel ACE control register 0x20 32 read-write n 0x0 0x0 TDRC TDRC 0 4 TEC TEC 8 4 THC THC 16 4 ETH_DMAC0CARxBR ETH_DMACCARxBR Channel current application receive buffer register 0x15C 32 read-only n 0x0 0x0 CURRBUFAPTR Application Receive Buffer Address Pointer 0 32 ETH_DMAC0CARxDR ETH_DMAC0CARxDR Channel 0 current application receive descriptor register DMAC1CATxDR 0x14C 32 read-only n 0x0 0x0 CURRDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC0CATxBR ETH_DMAC0CATxBR Channel 0 current application transmit buffer register 0x154 32 read-only n 0x0 0x0 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 ETH_DMAC0CATxDR ETH_DMAC0CATxDR Channel current application transmit descriptor register 0x144 32 read-only n 0x0 0x0 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC0CR ETH_DMAC0CR Channel 0 control register 0x100 32 read-write n 0x0 0x0 DSL DSL 18 3 MSS MSS 0 14 PBLX8 PBLX8 16 1 ETH_DMAC0IER ETH_DMACIER Channel interrupt enable register 0x134 32 read-write n 0x0 0x0 AIE Abnormal Interrupt Summary Enable 14 1 CDEE Context Descriptor Error Enable 13 1 ERIE Early Receive Interrupt Enable 11 1 ETIE Early Transmit Interrupt Enable 10 1 FBEE Fatal Bus Error Enable 12 1 NIE Normal Interrupt Summary Enable 15 1 RBUE Receive Buffer Unavailable Enable 7 1 RIE Receive Interrupt Enable 6 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 TBUE Transmit Buffer Unavailable Enable 2 1 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 ETH_DMAC0MFCR ETH_DMAC0MFCR Channel missed frame count register 0x16C 32 read-only n 0x0 0x0 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 ETH_DMAC0RxCR ETH_DMAC0RxCR Channel receive control register 0x108 32 read-write n 0x0 0x0 RBSZ Receive Buffer size 1 14 RPF DMA Rx Channel Packet Flush 31 1 RQOS RQOS 24 4 RXPBL RXPBL 16 6 SR Start or Stop Receive Command 0 1 ETH_DMAC0RxDLAR ETH_DMAC0RxDLAR Channel Rx descriptor list address register 0x11C 32 read-write n 0x0 0x0 RDESLA Start of Receive List 3 29 ETH_DMAC0RxDTPR ETH_DMAC0RxDTPR Channel Rx descriptor tail pointer register 0x128 32 read-write n 0x0 0x0 RDT Receive Descriptor Tail Pointer 3 29 ETH_DMAC0RxIWTR ETH_DMAC0RxIWTR Channel Rx interrupt watchdog timer register 0x138 32 read-write n 0x0 0x0 RWT Receive Interrupt Watchdog Timer Count 0 8 ETH_DMAC0RxRLR ETH_DMAC0RxRLR Channel Rx descriptor ring length register 0x130 32 read-write n 0x0 0x0 RDRL Receive Descriptor Ring Length 0 10 ETH_DMAC0SFCSR ETH_DMAC0SFCSR Channel i slot function control status register 0x13C 32 read-write n 0x0 0x0 ASC ASC 1 1 ESC ESC 0 1 RSN RSN 16 4 ETH_DMAC0SR ETH_DMAC0SR Channel status register 0x160 32 read-write n 0x0 0x0 AIS Abnormal Interrupt Summary 14 1 CDE Context Descriptor Error 13 1 ERI Early Receive Interrupt 11 1 ETI Early Transmit Interrupt 10 1 FBE Fatal Bus Error 12 1 NIS Normal Interrupt Summary 15 1 RBU Receive Buffer Unavailable 7 1 REB Rx DMA Error Bits 19 3 RI Receive Interrupt 6 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 TBU Transmit Buffer Unavailable 2 1 TEB Tx DMA Error Bits 16 3 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 ETH_DMAC0TxCR ETH_DMAC0TxCR Channel 0 transmit control register 0x104 32 read-write n 0x0 0x0 OSF OSF 4 1 ST ST 0 1 TCW TCW 1 3 TQOS TQOS 24 4 TSE TSE 12 1 TXPBL TXPBL 16 6 ETH_DMAC0TxDLAR ETH_DMAC0TxDLAR Channel i Tx descriptor list address register 0x114 32 read-write n 0x0 0x0 TDESLA Start of Transmit List 3 29 ETH_DMAC0TxDTPR ETH_DMAC0TxDTPR Channel Tx descriptor tail pointer register 0x120 32 read-write n 0x0 0x0 TDT Transmit Descriptor Tail Pointer 3 29 ETH_DMAC0TxRLR ETH_DMAC0TxRLR Channel Tx descriptor ring length register 0x12C 32 read-write n 0x0 0x0 TDRL Transmit Descriptor Ring Length 0 10 ETH_DMAC1CATxBR ETH_DMAC1CATxBR Channel 0 current application transmit buffer register 0x1D4 32 read-only n 0x0 0x0 CURTBUFAPTR Application Transmit Buffer Address Pointer 0 32 ETH_DMAC1CATxDR ETH_DMAC1CATxDR Channel current application transmit descriptor register 0x1C4 32 read-only n 0x0 0x0 CURTDESAPTR Application Transmit Descriptor Address Pointer 0 32 ETH_DMAC1CR ETH_DMAC1CR Channel 1 control register 0x180 32 read-write n 0x0 0x0 DSL DSL 18 3 MSS MSS 0 14 PBLX8 PBLX8 16 1 ETH_DMAC1IER ETH_DMAC1IER Channel interrupt enable register 0x1B4 32 read-write n 0x0 0x0 AIE Abnormal Interrupt Summary Enable 14 1 CDEE Context Descriptor Error Enable 13 1 ERIE Early Receive Interrupt Enable 11 1 ETIE Early Transmit Interrupt Enable 10 1 FBEE Fatal Bus Error Enable 12 1 NIE Normal Interrupt Summary Enable 15 1 RBUE Receive Buffer Unavailable Enable 7 1 RIE Receive Interrupt Enable 6 1 RSE Receive Stopped Enable 8 1 RWTE Receive Watchdog Timeout Enable 9 1 TBUE Transmit Buffer Unavailable Enable 2 1 TIE Transmit Interrupt Enable 0 1 TXSE Transmit Stopped Enable 1 1 ETH_DMAC1MFCR ETH_DMAC1MFCR Channel missed frame count register 0x1EC 32 read-only n 0x0 0x0 MFC Dropped Packet Counters 0 11 MFCO Overflow status of the MFC Counter 15 1 ETH_DMAC1SFCSR ETH_DMAC1SFCSR Channel i slot function control status register 0x1BC 32 read-write n 0x0 0x0 ASC ASC 1 1 ESC ESC 0 1 RSN RSN 16 4 ETH_DMAC1SR ETH_DMAC1SR Channel status register 0x1E0 32 read-write n 0x0 0x0 AIS Abnormal Interrupt Summary 14 1 CDE Context Descriptor Error 13 1 ERI Early Receive Interrupt 11 1 ETI Early Transmit Interrupt 10 1 FBE Fatal Bus Error 12 1 NIS Normal Interrupt Summary 15 1 RBU Receive Buffer Unavailable 7 1 REB Rx DMA Error Bits 19 3 RI Receive Interrupt 6 1 RPS Receive Process Stopped 8 1 RWT Receive Watchdog Timeout 9 1 TBU Transmit Buffer Unavailable 2 1 TEB Tx DMA Error Bits 16 3 TI Transmit Interrupt 0 1 TPS Transmit Process Stopped 1 1 ETH_DMAC1TxCR ETH_DMAC1TxCR Channel 1 transmit control register 0x184 32 read-write n 0x0 0x0 OSF OSF 4 1 ST ST 0 1 TCW TCW 1 3 TQOS TQOS 24 4 TSE TSE 12 1 TXPBL TXPBL 16 6 ETH_DMAC1TxDLAR ETH_DMAC1TxDLAR Channel i Tx descriptor list address register 0x194 32 read-write n 0x0 0x0 TDESLA Start of Transmit List 3 29 ETH_DMAC1TxDTPR ETH_DMAC1TxDTPR Channel Tx descriptor tail pointer register 0x1A0 32 read-write n 0x0 0x0 TDT Transmit Descriptor Tail Pointer 3 29 ETH_DMAC1TxRLR ETH_DMAC1TxRLR Channel Tx descriptor ring length register 0x1AC 32 read-write n 0x0 0x0 TDRL Transmit Descriptor Ring Length 0 10 ETH_DMADSR ETH_DMADSR Debug status register 0xC 32 read-only n 0x0 0x0 AXRHSTS AXRHSTS 1 1 AXWHSTS AHB Master Write Channel 0 1 RPS0 RPS0 8 4 RPS1 RPS1 16 4 TPS0 TPS0 12 4 TPS1 TPS1 20 4 ETH_DMAISR ETH_DMAISR Interrupt status register 0x8 32 read-only n 0x0 0x0 DC0IS DMA Channel Interrupt Status 0 1 DC1IS DC1IS 1 1 MACIS MAC Interrupt Status 17 1 MTLIS MTL Interrupt Status 16 1 ETH_DMAMR ETH_DMAMR DMA mode register 0x0 32 read-write n 0x0 0x0 INTM Interrupt Mode 16 2 PR Priority ratio 12 3 SWR Software Reset 0 1 TAA TAA 2 3 TXPR Transmit priority 11 1 ETH_DMASBMR ETH_DMASBMR System bus mode register 0x4 32 read-write n 0x0 0x0 AAL Address-Aligned Beats 12 1 BLEN128 BLEN128 6 1 BLEN16 BLEN16 3 1 BLEN256 BLEN256 7 1 BLEN32 BLEN32 4 1 BLEN4 BLEN4 1 1 BLEN64 BLEN64 5 1 BLEN8 BLEN8 2 1 EN_LPI EN_LPI 31 1 FB Fixed Burst Length 0 1 LPI_XIT_PKT LPI_XIT_PKT 30 1 ONEKBBE ONEKBBE 13 1 RD_OSR_LMT RD_OSR_LMT 16 2 WR_OSR_LMT WR_OSR_LMT 24 2 ETH_MAC_MMC ETH_MAC_MMC Ethernet 0x0 0x0 0xBD4 registers n ETH_MAC1USTCR ETH_MAC1USTCR This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially. 0xDC 32 read-write n 0x0 0x0 TIC_1US_CNTR TIC_1US_CNTR 0 12 read-write ETH_MACA0HR ETH_MACA0HR The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain. 0x300 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-only ETH_MACA0LR ETH_MACA0LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x304 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA1HR ETH_MACA1HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x308 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA1LR ETH_MACA1LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x30C 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA2HR ETH_MACA2HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x310 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA2LR ETH_MACA2LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x314 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACA3HR ETH_MACA3HR The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station. 0x318 32 read-write n 0x0 0x0 ADDRHI ADDRHI 0 16 read-write AE AE 31 1 read-write MBC MBC 24 6 read-write SA SA 30 1 read-write ETH_MACA3LR ETH_MACA3LR The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station. 0x31C 32 read-write n 0x0 0x0 ADDRLO ADDRLO 0 32 read-write ETH_MACACR ETH_MACACR The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot. 0xB40 32 read-write n 0x0 0x0 ATSEN0 ATSEN0 4 1 read-write ATSEN1 ATSEN1 5 1 read-write ATSEN2 ATSEN2 6 1 read-write ATSEN3 ATSEN3 7 1 read-write ATSFC ATSFC 0 1 read-write ETH_MACARPAR ETH_MACARPAR The ARP Address register contains the IPv4 Destination Address of the MAC. 0xAE0 32 read-write n 0x0 0x0 ARPPA ARPPA 0 32 read-write ETH_MACATSNR ETH_MACATSNR The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read. 0xB48 32 read-only n 0x0 0x0 AUXTSLO AUXTSLO 0 31 read-only ETH_MACATSSR ETH_MACATSSR The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register. 0xB4C 32 read-only n 0x0 0x0 AUXTSHI AUXTSHI 0 32 read-only ETH_MACCR ETH_MACCR The MAC Configuration Register establishes the operating mode of the MAC. 0x0 32 read-write n 0x0 0x0 ACS ACS 20 1 read-write ARPEN ARPEN 31 1 read-write BE BE 18 1 read-write BL BL 5 2 read-write CST CST 21 1 read-write DC DC 4 1 read-write DCRS DCRS 9 1 read-write DM DM 13 1 read-write DO DO 10 1 read-write DR DR 8 1 read-write ECRSFD ECRSFD 11 1 read-write FES FES 14 1 read-write GPSLCE GPSLCE 23 1 read-write IPC IPC 27 1 read-write IPG IPG 24 3 read-write JD JD 17 1 read-write JE JE 16 1 read-write LM LM 12 1 read-write PRELEN PRELEN 2 2 read-write PS PS 15 1 read-write RE RE 0 1 read-write S2KP S2KP 22 1 read-write SARC SARC 28 3 read-write TE TE 1 1 read-write WD WD 19 1 read-write ETH_MACDR ETH_MACDR The Debug register provides the debug status of various MAC blocks. 0x114 32 read-only n 0x0 0x0 RFCFCSTS RFCFCSTS 1 2 read-only RPESTS RPESTS 0 1 read-only TFCSTS TFCSTS 17 2 read-only TPESTS TPESTS 16 1 read-only ETH_MACECR ETH_MACECR The MAC Extended Configuration Register establishes the operating mode of the MAC. 0x4 32 read-write n 0x0 0x0 DCRCC DCRCC 16 1 read-write EIPG EIPG 25 5 read-write EIPGEN EIPGEN 24 1 read-write GPSL GPSL 0 14 read-write SPEN SPEN 17 1 read-write USP USP 18 1 read-write ETH_MACHT0R ETH_MACHT0R The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x10 32 read-write n 0x0 0x0 HT31T0 HT31T0 0 32 read-write ETH_MACHT1R ETH_MACHT1R The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. 0x14 32 read-write n 0x0 0x0 HT63T32 HT63T32 0 32 read-write ETH_MACHWF1R ETH_MACHWF1R This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x120 32 read-only n 0x0 0x0 ADDR64 ADDR64 14 2 read-only ADVTHWORD ADVTHWORD 13 1 read-only AVSEL AVSEL 20 1 read-only DBGMEMA DBGMEMA 19 1 read-only DCBEN DCBEN 16 1 read-only HASHTBLSZ HASHTBLSZ 24 2 read-only L3L4FNUM L3L4FNUM 27 4 read-only OSTEN OSTEN 11 1 read-only PTOEN PTOEN 12 1 read-only RXFIFOSIZE RXFIFOSIZE 0 5 read-only SPHEN SPHEN 17 1 read-only TSOEN TSOEN 18 1 read-only TXFIFOSIZE TXFIFOSIZE 6 5 read-only ETH_MACHWF2R ETH_MACHWF2R This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. 0x124 32 read-only n 0x0 0x0 AUXSNAPNUM AUXSNAPNUM 28 3 read-only PPSOUTNUM PPSOUTNUM 24 3 read-only RXCHCNT RXCHCNT 12 4 read-only RXQCNT RXQCNT 0 4 read-only TXCHCNT TXCHCNT 18 4 read-only TXQCNT TXQCNT 6 4 read-only ETH_MACIER ETH_MACIER The Interrupt Enable register contains the masks for generating the interrupts. 0xB4 32 read-write n 0x0 0x0 LPIIE LPIIE 5 1 read-write PHYIE PHYIE 3 1 read-write PMTIE PMTIE 4 1 read-write RGSMIIIE RGSMIIIE 0 1 read-write RXSTSIE RXSTSIE 14 1 read-write TSIE TSIE 12 1 read-write TXSTSIE TXSTSIE 13 1 read-write ETH_MACISR ETH_MACISR The Interrupt Status register contains the status of interrupts. 0xB0 32 read-only n 0x0 0x0 LPIIS LPIIS 5 1 read-only MMCIS MMCIS 8 1 read-only MMCRXIS MMCRXIS 9 1 read-only MMCTXIS MMCTXIS 10 1 read-only PHYIS PHYIS 3 1 read-only PMTIS PMTIS 4 1 read-only RGSMIIIS RGSMIIIS 0 1 read-only RXSTSIS RXSTSIS 14 1 read-only TSIS TSIS 12 1 read-only TXSTSIS TXSTSIS 13 1 read-only ETH_MACIVIR ETH_MACIVIR The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls. 0x64 32 read-write n 0x0 0x0 CSVL CSVL 19 1 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write VLT VLT 0 16 read-write VLTI VLTI 20 1 read-write ETH_MACL3A00R ETH_MACL3A00R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x910 32 read-write n 0x0 0x0 L3A00 L3A00 0 32 read-write ETH_MACL3A01R ETH_MACL3A01R For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field. 0x940 32 read-write n 0x0 0x0 L3A01 L3A01 0 32 read-write ETH_MACL3A10R ETH_MACL3A10R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x914 32 read-write n 0x0 0x0 L3A10 L3A10 0 32 read-write ETH_MACL3A11R ETH_MACL3A11R For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field. 0x944 32 read-write n 0x0 0x0 L3A11 L3A11 0 32 read-write ETH_MACL3A20 ETH_MACL3A20 The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x918 32 read-write n 0x0 0x0 L3A20 L3A20 0 32 read-write ETH_MACL3A21R ETH_MACL3A21R The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field. 0x948 32 read-write n 0x0 0x0 L3A21 L3A21 0 32 read-write ETH_MACL3A30 ETH_MACL3A30 The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x91C 32 read-write n 0x0 0x0 L3A30 L3A30 0 32 read-write ETH_MACL3A31R ETH_MACL3A31R The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field. 0x94C 32 read-write n 0x0 0x0 L3A31 L3A31 0 32 read-write ETH_MACL3L4C0R ETH_MACL3L4C0R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration. 0x900 32 read-write n 0x0 0x0 L3DAIM0 L3DAIM0 5 1 read-write L3DAM0 L3DAM0 4 1 read-write L3HDBM0 L3HDBM0 11 5 read-write L3HSBM0 L3HSBM0 6 5 read-write L3PEN0 L3PEN0 0 1 read-write L3SAIM0 L3SAIM0 3 1 read-write L3SAM0 L3SAM0 2 1 read-write L4DPIM0 L4DPIM0 21 1 read-write L4DPM0 L4DPM0 20 1 read-write L4PEN0 L4PEN0 16 1 read-write L4SPIM0 L4SPIM0 19 1 read-write L4SPM0 L4SPM0 18 1 read-write ETH_MACL3L4C1R ETH_MACL3L4C1R The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. 0x930 32 read-write n 0x0 0x0 L3DAIM1 L3DAIM1 5 1 read-write L3DAM1 L3DAM1 4 1 read-write L3HDBM1 L3HDBM1 11 5 read-write L3HSBM1 L3HSBM1 6 5 read-write L3PEN1 L3PEN1 0 1 read-write L3SAIM1 L3SAIM1 3 1 read-write L3SAM1 L3SAM1 2 1 read-write L4DPIM1 L4DPIM1 21 1 read-write L4DPM1 L4DPM1 20 1 read-write L4PEN1 L4PEN1 16 1 read-write L4SPIM1 L4SPIM1 19 1 read-write L4SPM1 L4SPM1 18 1 read-write ETH_MACL4A0R ETH_MACL4A0R Layer4 address filter 0 register 0x904 32 read-write n 0x0 0x0 L4DP0 L4DP0 16 16 read-write L4SP0 L4SP0 0 16 read-write ETH_MACL4A1R ETH_MACL4A1R The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock. 0x934 32 read-write n 0x0 0x0 L4DP1 L4DP1 16 16 read-write L4SP1 L4SP1 0 16 read-write ETH_MACLCSR ETH_MACLCSR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xD0 32 read-write n 0x0 0x0 LPIEN LPIEN 16 1 read-write LPITE LPITE 20 1 read-write LPITXA LPITXA 19 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only RLPIST RLPIST 9 1 read-only TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only TLPIST TLPIST 8 1 read-only ETH_MACLETR ETH_MACLETR The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds. 0xD8 32 read-write n 0x0 0x0 LPIET LPIET 3 17 read-write ETH_MACLMIR ETH_MACLMIR This register contains the periodic intervals for automatic PTP packet generation. 0xBD0 32 read-write n 0x0 0x0 DRSYNCR DRSYNCR 8 3 read-write LMPDRI LMPDRI 24 8 read-write LSI LSI 0 8 read-write ETH_MACLTCR ETH_MACLTCR The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. 0xD4 32 read-write n 0x0 0x0 LST LST 16 10 read-write TWT TWT 0 16 read-write ETH_MACMDIOAR ETH_MACMDIOAR The MDIO Address register controls the management cycles to external PHY through a management interface. 0x200 32 read-write n 0x0 0x0 BTB BTB 26 1 read-write C45E C45E 1 1 read-write CR CR 8 4 read-write GB GB 0 1 read-write GOC GOC 2 2 read-write NTC NTC 12 3 read-write PA PA 21 5 read-write PSE PSE 27 1 read-write RDA RDA 16 5 read-write SKAP SKAP 4 1 read-write ETH_MACMDIODR ETH_MACMDIODR The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register. 0x204 32 read-write n 0x0 0x0 GD GD 0 16 read-write RA RA 16 16 read-write ETH_MACPCSR ETH_MACPCSR The PMT Control and Status Register is present only when you select the PMT module in coreConsultant. 0xC0 32 read-write n 0x0 0x0 GLBLUCAST GLBLUCAST 9 1 read-write MGKPKTEN MGKPKTEN 1 1 read-write MGKPRCVD MGKPRCVD 5 1 read-only PWRDWN PWRDWN 0 1 read-write RWKFILTRST RWKFILTRST 31 1 read-write RWKPFE RWKPFE 10 1 read-write RWKPKTEN RWKPKTEN 2 1 read-write RWKPRCVD RWKPRCVD 6 1 read-only RWKPTR RWKPTR 24 5 read-only ETH_MACPFR ETH_MACPFR The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets. 0x8 32 read-write n 0x0 0x0 DAIF DAIF 3 1 read-write DBF DBF 5 1 read-write DNTU DNTU 21 1 read-write HMC HMC 2 1 read-write HPF HPF 10 1 read-write HUC HUC 1 1 read-write IPFE IPFE 20 1 read-write PCF PCF 6 2 read-write PM PM 4 1 read-write PR PR 0 1 read-write RA RA 31 1 read-write SAF SAF 9 1 read-write SAIF SAIF 8 1 read-write VTFE VTFE 16 1 read-write ETH_MACPHYCSR ETH_MACPHYCSR The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY. 0xF8 32 read-write n 0x0 0x0 FALSCARDET FALSCARDET 21 1 read-only JABTO JABTO 20 1 read-only LNKMOD LNKMOD 16 1 read-only LNKSPEED LNKSPEED 17 2 read-only LNKSTS LNKSTS 19 1 read-only LUD LUD 1 1 read-write TC TC 0 1 read-write ETH_MACPOCR ETH_MACPOCR This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC0 32 read-write n 0x0 0x0 APDREQEN APDREQEN 2 1 read-write APDREQTRIG APDREQTRIG 5 1 read-write ASYNCEN ASYNCEN 1 1 read-write ASYNCTRIG ASYNCTRIG 4 1 read-write DN DN 8 8 read-write DRRDIS DRRDIS 6 1 read-write PTOEN PTOEN 0 1 read-write ETH_MACPPSCR ETH_MACPPSCR The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected. 0xB70 32 read-write n 0x0 0x0 PPSCTRL PPSCTRL 0 4 read-write PPSEN0 PPSEN0 4 1 read-write TRGTMODSEL0 TRGTMODSEL0 5 2 read-write ETH_MACPPSIR ETH_MACPPSIR The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]). 0xB88 32 read-write n 0x0 0x0 PPSINT0 PPSINT0 0 32 read-write ETH_MACPPSTTNR ETH_MACPPSTTNR The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected. 0xB84 32 read-write n 0x0 0x0 TRGTBUSY0 TRGTBUSY0 31 1 read-write TTSL0 TTSL0 0 31 read-write ETH_MACPPSTTSR ETH_MACPPSTTSR The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers. 0xB80 32 read-write n 0x0 0x0 TSTRH0 TSTRH0 0 32 read-write ETH_MACPPSWR ETH_MACPPSWR The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o). 0xB8C 32 read-write n 0x0 0x0 PPSWIDTH0 PPSWIDTH0 0 32 read-write ETH_MACQ0TxFCR ETH_MACQ0TxFCR The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register. 0x70 32 read-write n 0x0 0x0 DZPQ DZPQ 7 1 read-write FCB_BPA FCB_BPA 0 1 read-write PLT PLT 4 3 read-write PT PT 16 16 read-write TFE TFE 1 1 read-write ETH_MACRWKPFR ETH_MACRWKPFR The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. 0xC4 32 read-write n 0x0 0x0 LPIEN LPIEN 16 1 read-write LPITE LPITE 20 1 read-write LPITXA LPITXA 19 1 read-write PLS PLS 17 1 read-write PLSEN PLSEN 18 1 read-write RLPIEN RLPIEN 2 1 read-only RLPIEX RLPIEX 3 1 read-only RLPIST RLPIST 9 1 read-only TLPIEN TLPIEN 0 1 read-only TLPIEX TLPIEX 1 1 read-only TLPIST TLPIST 8 1 read-only ETH_MACRxFCR ETH_MACRxFCR The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet. 0x90 32 read-write n 0x0 0x0 RFE RFE 0 1 read-write UP UP 1 1 read-write ETH_MACRxQC0R ETH_MACRxQC0R The Receive Queue Control 0 register controls the queue management in the MAC Receiver. 0xA0 32 read-write n 0x0 0x0 RXQ0EN RXQ0EN 0 2 read-write RXQ1EN RXQ1EN 2 2 read-write ETH_MACRxQC1R ETH_MACRxQC1R The Receive Queue Control 1 register controls queue 1 management in the MAC receiver. 0xA4 32 read-write n 0x0 0x0 AVCPQ AVCPQ 0 3 read-write AVPTPQ AVPTPQ 4 3 read-write MCBCQ MCBCQ 16 3 read-write MCBCQEN MCBCQEN 20 1 read-write TACPQE TACPQE 21 1 read-write UPQ UPQ 12 3 read-write ETH_MACRxQC2R ETH_MACRxQC2R This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1. 0xA8 32 read-write n 0x0 0x0 PSRQ0 PSRQ0 0 8 read-write PSRQ1 PSRQ1 8 8 read-write ETH_MACRxTxSR ETH_MACRxTxSR The Receive Transmit Status register contains the Receive and Transmit Error status. 0xB8 32 read-only n 0x0 0x0 EXCOL EXCOL 5 1 read-only EXDEF EXDEF 3 1 read-only LCARR LCARR 2 1 read-only LCOL LCOL 4 1 read-only NCARR NCARR 1 1 read-only RWT RWT 8 1 read-only TJT TJT 0 1 read-only ETH_MACSPI0R ETH_MACSPI0R This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC4 32 read-write n 0x0 0x0 SPI0 SPI0 0 32 read-write ETH_MACSPI1R ETH_MACSPI1R This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected. 0xBC8 32 read-write n 0x0 0x0 SPI1 SPI1 0 32 read-write ETH_MACSPI2R ETH_MACSPI2R This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. 0xBCC 32 read-write n 0x0 0x0 SPI2 SPI2 0 16 read-write ETH_MACSSIR ETH_MACSSIR The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow. 0xB04 32 read-write n 0x0 0x0 SNSINC SNSINC 8 8 read-write SSINC SSINC 16 8 read-write ETH_MACSTNR ETH_MACSTNR The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB0C 32 read-only n 0x0 0x0 TSSS TSSS 0 31 read-only ETH_MACSTNUR ETH_MACSTNUR This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input. 0xB14 32 read-write n 0x0 0x0 ADDSUB ADDSUB 31 1 read-write TSSS TSSS 0 31 read-write ETH_MACSTSR ETH_MACSTSR The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB08 32 read-only n 0x0 0x0 TSS TSS 0 32 read-only ETH_MACSTSUR ETH_MACSTSUR The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. 0xB10 32 read-write n 0x0 0x0 TSS TSS 0 32 read-write ETH_MACTSAR ETH_MACTSAR The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows. 0xB18 32 read-write n 0x0 0x0 TSAR TSAR 0 32 read-write ETH_MACTSCR ETH_MACTSCR This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver. 0xB00 32 read-write n 0x0 0x0 AV8021ASMEN AV8021ASMEN 28 1 read-write CSC CSC 19 1 read-only SNAPTYPSEL SNAPTYPSEL 16 2 read-write TSADDREG TSADDREG 5 1 read-write TSCFUPDT TSCFUPDT 1 1 read-write TSCTRLSSR TSCTRLSSR 9 1 read-write TSENA TSENA 0 1 read-write TSENALL TSENALL 8 1 read-write TSENMACADDR TSENMACADDR 18 1 read-write TSEVNTENA TSEVNTENA 14 1 read-write TSINIT TSINIT 2 1 read-write TSIPENA TSIPENA 11 1 read-write TSIPV4ENA TSIPV4ENA 13 1 read-write TSIPV6ENA TSIPV6ENA 12 1 read-write TSMSTRENA TSMSTRENA 15 1 read-write TSUPDT TSUPDT 3 1 read-write TSVER2ENA TSVER2ENA 10 1 read-write TXTSSTSM TXTSSTSM 24 1 read-write ETH_MACTSEACR ETH_MACTSEACR The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages. 0xB54 32 read-write n 0x0 0x0 OSTEAC OSTEAC 0 32 read-write ETH_MACTSECNR ETH_MACTSECNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path. 0xB5C 32 read-write n 0x0 0x0 TSEC TSEC 0 32 read-write ETH_MACTSIACR ETH_MACTSIACR The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages. 0xB50 32 read-write n 0x0 0x0 OSTIAC OSTIAC 0 32 read-write ETH_MACTSICNR ETH_MACTSICNR This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path. 0xB58 32 read-write n 0x0 0x0 TSIC TSIC 0 32 read-write ETH_MACTSSR ETH_MACTSSR The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register. 0xB20 32 read-only n 0x0 0x0 ATSNS ATSNS 25 5 read-only ATSSTM ATSSTM 24 1 read-only ATSSTN ATSSTN 16 4 read-only AUXTSTRIG AUXTSTRIG 2 1 read-only TSSOVF TSSOVF 0 1 read-only TSTARGT0 TSTARGT0 1 1 read-only TSTRGTERR0 TSTRGTERR0 3 1 read-only TXTSSIS TXTSSIS 15 1 read-only ETH_MACTxQPMR ETH_MACTxQPMR The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1. 0x98 32 read-only n 0x0 0x0 PSTQ0 PSTQ0 0 8 read-only PSTQ1 PSTQ1 8 8 read-only ETH_MACTxTSSNR ETH_MACTxTSSNR This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. 0xB30 32 read-only n 0x0 0x0 TXTSSLO TXTSSLO 0 31 read-only TXTSSMIS TXTSSMIS 31 1 read-only ETH_MACTxTSSSR ETH_MACTxTSSSR The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted. 0xB34 32 read-only n 0x0 0x0 TXTSSHI TXTSSHI 0 32 read-only ETH_MACVHTR ETH_MACVHTR When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. 0x58 32 read-write n 0x0 0x0 VLHT VLHT 0 16 read-write ETH_MACVIR ETH_MACVIR The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls. 0x60 32 read-write n 0x0 0x0 CSVL CSVL 19 1 read-write VLC VLC 16 2 read-write VLP VLP 18 1 read-write VLT VLT 0 16 read-write VLTI VLTI 20 1 read-write ETH_MACVR ETH_MACVR The version register identifies the version of the Ethernet peripheral. 0x110 32 read-only n 0x0 0x0 SNPSVER SNPSVER 0 8 read-only USERVER USERVER 8 8 read-only ETH_MACVTR ETH_MACVTR The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets. 0x50 32 read-write n 0x0 0x0 DOVLTC DOVLTC 20 1 read-write EDVLP EDVLP 26 1 read-write EIVLRXS EIVLRXS 31 1 read-write EIVLS EIVLS 28 2 read-write ERIVLT ERIVLT 27 1 read-write ERSVLM ERSVLM 19 1 read-write ESVL ESVL 18 1 read-write ETV ETV 16 1 read-write EVLRXS EVLRXS 24 1 read-write EVLS EVLS 21 2 read-write VL VL 0 16 read-write VTHM VTHM 25 1 read-write VTIM VTIM 17 1 read-write ETH_MACWTR ETH_MACWTR The Watchdog Timeout register controls the watchdog timeout for received packets. 0xC 32 read-write n 0x0 0x0 PWE PWE 8 1 read-write WTO WTO 0 4 read-write MMC_CONTROL MMC_CONTROL This register configures the MMC operating mode. 0x700 32 read-write n 0x0 0x0 CNTFREEZ CNTFREEZ 3 1 read-write CNTPRST CNTPRST 4 1 read-write CNTPRSTLVL CNTPRSTLVL 5 1 read-write CNTRST CNTRST 0 1 read-write CNTSTOPRO CNTSTOPRO 1 1 read-write RSTONRD RSTONRD 2 1 read-write UCDBC UCDBC 8 1 read-write MMC_RX_INTERRUPT MMC_RX_INTERRUPT This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x704 32 read-only n 0x0 0x0 RXALGNERPIS RXALGNERPIS 6 1 read-only RXCRCERPIS RXCRCERPIS 5 1 read-only RXLPITRCIS RXLPITRCIS 27 1 read-only RXLPIUSCIS RXLPIUSCIS 26 1 read-only RXUCGPIS RXUCGPIS 17 1 read-only MMC_RX_INTERRUPT_MASK MMC_RX_INTERRUPT_MASK The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values. 0x70C 32 read-write n 0x0 0x0 RXALGNERPIM RXALGNERPIM 6 1 read-write RXCRCERPIM RXCRCERPIM 5 1 read-write RXLPITRCIM RXLPITRCIM 27 1 read-only RXLPIUSCIM RXLPIUSCIM 26 1 read-write RXUCGPIM RXUCGPIM 17 1 read-write MMC_TX_INTERRUPT MMC_TX_INTERRUPT This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit. 0x708 32 read-only n 0x0 0x0 TXGPKTIS TXGPKTIS 21 1 read-only TXLPITRCIS TXLPITRCIS 27 1 read-only TXLPIUSCIS TXLPIUSCIS 26 1 read-only TXMCOLGPIS TXMCOLGPIS 15 1 read-only TXSCOLGPIS TXSCOLGPIS 14 1 read-only MMC_TX_INTERRUPT_MASK MMC_TX_INTERRUPT_MASK This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration. 0x710 32 read-write n 0x0 0x0 TXGPKTIM TXGPKTIM 21 1 read-write TXLPITRCIM TXLPITRCIM 27 1 read-only TXLPIUSCIM TXLPIUSCIM 26 1 read-write TXMCOLGPIM TXMCOLGPIM 15 1 read-write TXSCOLGPIM TXSCOLGPIM 14 1 read-write RX_ALIGNMENT_ERROR_PACKETS RX_ALIGNMENT_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode. 0x798 32 read-only n 0x0 0x0 RXALGNERR RXALGNERR 0 32 read-only RX_CRC_ERROR_PACKETS RX_CRC_ERROR_PACKETS This register provides the number of packets received by Ethernet peripheral with CRC error. 0x794 32 read-only n 0x0 0x0 RXCRCERR RXCRCERR 0 32 read-only RX_LPI_TRAN_CNTR RX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Rx LPI. 0x7F8 32 read-only n 0x0 0x0 RXLPITRC RXLPITRC 0 32 read-only RX_LPI_USEC_CNTR RX_LPI_USEC_CNTR This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral. 0x7F4 32 read-only n 0x0 0x0 RXLPIUSC RXLPIUSC 0 32 read-only RX_UNICAST_PACKETS_GOOD RX_UNICAST_PACKETS_GOOD This register provides the number of good unicast packets received by Ethernet peripheral. 0x7C4 32 read-only n 0x0 0x0 RXUCASTG RXUCASTG 0 32 read-only TX_LPI_TRAN_CNTR TX_LPI_TRAN_CNTR This register provides the number of times Ethernet peripheral has entered Tx LPI. 0x7F0 32 read-only n 0x0 0x0 TXLPITRC TXLPITRC 0 32 read-only TX_LPI_USEC_CNTR TX_LPI_USEC_CNTR This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral. 0x7EC 32 read-only n 0x0 0x0 TXLPIUSC TXLPIUSC 0 32 read-only TX_MULTIPLE_COLLISION_GOOD_PACKETS TX_MULTIPLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode. 0x750 32 read-only n 0x0 0x0 TXMULTCOLG TXMULTCOLG 0 32 read-only TX_PACKET_COUNT_GOOD TX_PACKET_COUNT_GOOD This register provides the number of good packets transmitted by Ethernet peripheral. 0x768 32 read-only n 0x0 0x0 TXPKTG TXPKTG 0 32 read-only TX_SINGLE_COLLISION_GOOD_PACKETS TX_SINGLE_COLLISION_GOOD_PACKETS This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode. 0x74C 32 read-only n 0x0 0x0 TXSNGLCOLG TXSNGLCOLG 0 32 read-only ETH_MTL ETH_MTL Ethernet 0x0 0x0 0x400 registers n ETH_MTLISR ETH_MTLISR The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC. 0x20 32 read-only n 0x0 0x0 Q0IS Q0IS 0 1 read-only Q1IS Q1IS 1 1 read-only ETH_MTLOMR ETH_MTLOMR The Operating Mode register establishes the Transmit and Receive operating modes and commands. 0x0 32 read-write n 0x0 0x0 CNTCLR CNTCLR 9 1 read-write CNTPRST CNTPRST 8 1 read-write DTXSTS DTXSTS 1 1 read-write RAA RAA 2 1 read-write SCHALG SCHALG 5 2 read-write ETH_MTLQ0ICSR ETH_MTLQ0ICSR Queue 0 interrupt control status Register 0x12C 32 read-write n 0x0 0x0 ABPSIE ABPSIE 9 1 read-write ABPSIS ABPSIS 1 1 read-write RXOIE RXOIE 24 1 read-write RXOVFIS RXOVFIS 16 1 read-write TXUIE TXUIE 8 1 read-write TXUNFIS TXUNFIS 0 1 read-only ETH_MTLQ1ICSR ETH_MTLQ1ICSR Queue 1 interrupt control status Register 0x16C 32 read-write n 0x0 0x0 ABPSIE ABPSIE 9 1 read-write ABPSIS ABPSIS 1 1 read-write RXOIE RXOIE 24 1 read-write RXOVFIS RXOVFIS 16 1 read-write TXUIE TXUIE 8 1 read-write TXUNFIS TXUNFIS 0 1 read-only ETH_MTLRxQ0CR ETH_MTLRxQ0CR Rx queue 0 control register 0x13C 32 read-write n 0x0 0x0 RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only RXQ_WEGT RXQ_WEGT 0 3 read-only ETH_MTLRxQ0DR ETH_MTLRxQ0DR Rx queue i debug register 0x138 32 read-only n 0x0 0x0 PRXQ PRXQ 16 14 read-only RRCSTS RRCSTS 1 2 read-only RWCSTS RWCSTS 0 1 read-only RXQSTS RXQSTS 4 2 read-only ETH_MTLRxQ0MPOCR ETH_MTLRxQ0MPOCR Rx queue 0 missed packet and overflow counter register 0x134 32 read-only n 0x0 0x0 MISCNTOVF MISCNTOVF 27 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only OVFPKTCNT OVFPKTCNT 0 11 read-only ETH_MTLRxQ0OMR ETH_MTLRxQ0OMR Rx queue 0 operating mode register 0x130 32 read-write n 0x0 0x0 DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write FEP FEP 4 1 read-write FUP FUP 3 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only RSF RSF 5 1 read-write RTC RTC 0 2 read-write ETH_MTLRxQ1CR ETH_MTLRxQ1CR Rx queue 1 control register 0x17C 32 read-write n 0x0 0x0 RXQ_FRM_ARBIT RXQ_FRM_ARBIT 3 1 read-only RXQ_WEGT RXQ_WEGT 0 3 read-only ETH_MTLRxQ1DR ETH_MTLRxQ1DR Rx queue i debug register 0x178 32 read-only n 0x0 0x0 PRXQ PRXQ 16 14 read-only RRCSTS RRCSTS 1 2 read-only RWCSTS RWCSTS 0 1 read-only RXQSTS RXQSTS 4 2 read-only ETH_MTLRxQ1MPOCR ETH_MTLRxQ1MPOCR Rx queue 1 missed packet and overflow counter register 0x174 32 read-only n 0x0 0x0 MISCNTOVF MISCNTOVF 27 1 read-only MISPKTCNT MISPKTCNT 16 11 read-only OVFCNTOVF OVFCNTOVF 11 1 read-only OVFPKTCNT OVFPKTCNT 0 11 read-only ETH_MTLRxQ1OMR ETH_MTLRxQ1OMR Rx queue 1 operating mode register 0x170 32 read-write n 0x0 0x0 DIS_TCP_EF DIS_TCP_EF 6 1 read-write EHFC EHFC 7 1 read-write FEP FEP 4 1 read-write FUP FUP 3 1 read-write RFA RFA 8 3 read-write RFD RFD 14 3 read-write RQS RQS 20 4 read-only RSF RSF 5 1 read-write RTC RTC 0 2 read-write ETH_MTLTxQ0DR ETH_MTLTxQ0DR Tx queue 0 underflow register 0x108 32 read-only n 0x0 0x0 PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQPAUSED TXQPAUSED 0 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only ETH_MTLTxQ0ESR ETH_MTLTxQ0ESR Tx queue x ETS status Register 0x114 32 read-only n 0x0 0x0 ABS ABS 0 24 read-only ETH_MTLTxQ0OMR ETH_MTLTxQ0OMR Tx queue 0 operating mode Register 0x100 32 read-write n 0x0 0x0 FTQ FTQ 0 1 read-write TQS TQS 16 9 read-write TSF TSF 1 1 read-write TTC TTC 4 2 read-write TXQEN TXQEN 2 2 read-write ETH_MTLTxQ0UR ETH_MTLTxQ0UR Tx queue 0 underflow register 0x104 32 read-only n 0x0 0x0 UFCNTOVF UFCNTOVF 11 1 read-only UFFRMCNT UFFRMCNT 0 11 read-only ETH_MTLTxQ1DR ETH_MTLTxQ1DR Tx queue 1 underflow register 0x148 32 read-only n 0x0 0x0 PTXQ PTXQ 16 3 read-only STXSTSF STXSTSF 20 3 read-only TRCSTS TRCSTS 1 2 read-only TWCSTS TWCSTS 3 1 read-only TXQPAUSED TXQPAUSED 0 1 read-only TXQSTS TXQSTS 4 1 read-only TXSTSFSTS TXSTSFSTS 5 1 read-only ETH_MTLTxQ1ECR ETH_MTLTxQ1ECR The Queue ETS Control register controls the enhanced transmission selection operation. 0x150 32 read-write n 0x0 0x0 AVALG AVALG 2 1 read-write CC CC 3 1 read-write SLC SLC 4 3 read-write ETH_MTLTxQ1ESR ETH_MTLTxQ1ESR Tx queue x ETS status Register 0x154 32 read-only n 0x0 0x0 ABS ABS 0 24 read-only ETH_MTLTxQ1HCR ETH_MTLTxQ1HCR The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue. 0x160 32 read-write n 0x0 0x0 HC HC 0 29 read-write ETH_MTLTxQ1LCR ETH_MTLTxQ1LCR The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue. 0x164 32 read-write n 0x0 0x0 LC LC 0 29 read-write ETH_MTLTxQ1OMR ETH_MTLTxQ1OMR Tx queue 1 operating mode Register 0x140 32 read-write n 0x0 0x0 FTQ FTQ 0 1 read-write TQS TQS 16 9 read-write TSF TSF 1 1 read-write TTC TTC 4 2 read-write TXQEN TXQEN 2 2 read-write ETH_MTLTxQ1QWR ETH_MTLTxQ1QWR This register provides the average traffic transmitted on queue 1. 0x158 32 read-write n 0x0 0x0 ISCQW ISCQW 0 21 read-write ETH_MTLTxQ1SSCR ETH_MTLTxQ1SSCR The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue. 0x15C 32 read-write n 0x0 0x0 SSC SSC 0 14 read-write ETH_MTLTxQ1UR ETH_MTLTxQ1UR Tx queue 1 underflow register 0x144 32 read-only n 0x0 0x0 UFCNTOVF UFCNTOVF 11 1 read-only UFFRMCNT UFFRMCNT 0 11 read-only ETZPC ETZPC ETZPC 0x0 0x0 0x400 registers n DECPROT0 ETZPC_DECPROT0 ETZPC securable peripheral definition register 0 0x10 32 read-write n 0x0 0x0 decprot0 decprot0 0 2 read-write decprot1 decprot1 2 2 read-write decprot10 decprot10 20 2 read-write decprot11 decprot11 22 2 read-write decprot12 decprot12 24 2 read-write decprot2 decprot2 4 2 read-write decprot3 decprot3 6 2 read-write decprot4 decprot4 8 2 read-write decprot5 decprot5 10 2 read-write decprot6 decprot6 12 2 read-write decprot7 decprot7 14 2 read-write decprot8 decprot8 16 2 read-write decprot9 decprot9 18 2 read-write DECPROT_LOCK0 ETZPC_DECPROT_LOCK0 ETZPC securable peripheral definition register 0 0x20 32 read-write n 0x0 0x0 LOCK0 LOCK0 0 1 read-write LOCK1 LOCK1 1 1 read-write LOCK10 LOCK10 10 1 read-write LOCK11 LOCK11 11 1 read-write LOCK12 LOCK12 12 1 read-write LOCK2 LOCK2 2 1 read-write LOCK3 LOCK3 3 1 read-write LOCK4 LOCK4 4 1 read-write LOCK5 LOCK5 5 1 read-write LOCK6 LOCK6 6 1 read-write LOCK7 LOCK7 7 1 read-write LOCK8 LOCK8 8 1 read-write LOCK9 LOCK9 9 1 read-write HWCFGR ETZPC_HWCFGR ETZPC IP hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CHUNKS1N4 CHUNKS1N4 24 8 read-only NUM_AHB_SEC NUM_AHB_SEC 16 8 read-only NUM_PER_SEC NUM_PER_SEC 8 8 read-only NUM_TZMA NUM_TZMA 0 8 read-only IPIDR ETZPC_IPIDR ETZPC IP version register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only SIDR ETZPC_SIDR ETZPC IP version register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only TZMA0_SIZE ETZPC_TZMA0_SIZE ETZPC ROM secure size definition 0x0 32 read-write n 0x0 0x0 lock lock 31 1 read-write r0size r0size 0 10 read-write TZMA1_SIZE ETZPC_TZMA1_SIZE ETZPC RAM secure size definition 0x4 32 read-write n 0x0 0x0 lock lock 31 1 read-write r0size r0size 0 10 read-write VERR ETZPC_VERR ETZPC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only EXTI External interrupt/event controller EXTI 0x0 0x0 0x400 registers n C2EMR1 C2EMR1 EXTI CPUm wakeup with event mask register 0xC4 32 read-write n 0x0 0x0 EM0 CPU wakeup with interrupt mask on event input 0 1 EM1 CPU wakeup with interrupt mask on event input 1 1 EM10 CPU wakeup with interrupt mask on event input 10 1 EM11 CPU wakeup with interrupt mask on event input 11 1 EM12 CPU wakeup with interrupt mask on event input 12 1 EM13 CPU wakeup with interrupt mask on event input 13 1 EM14 CPU wakeup with interrupt mask on event input 14 1 EM15 CPU wakeup with interrupt mask on event input 15 1 EM17 CPU wakeup with interrupt mask on event input 17 1 EM18 CPU wakeup with interrupt mask on event input 18 1 EM19 CPU wakeup with interrupt mask on event input 19 1 EM2 CPU wakeup with interrupt mask on event input 2 1 EM3 CPU wakeup with interrupt mask on event input 3 1 EM4 CPU wakeup with interrupt mask on event input 4 1 EM5 CPU wakeup with interrupt mask on event input 5 1 EM6 CPU wakeup with interrupt mask on event input 6 1 EM7 CPU wakeup with interrupt mask on event input 7 1 EM8 CPU wakeup with interrupt mask on event input 8 1 EM9 CPU wakeup with interrupt mask on event input 9 1 C2EMR3 C2EMR3 EXTI CPUm wakeup with event mask register 0xE4 32 read-write n 0x0 0x0 EM66 CPU wakeup with interrupt mask on event input 2 1 C2IMR1 C2IMR1 EXTI CPU wakeup with event mask register 0xC0 32 read-write n 0x0 0x0 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM27 CPU wakeup with interrupt mask on event input 27 1 IM28 CPU wakeup with interrupt mask on event input 28 1 IM29 CPU wakeup with interrupt mask on event input 29 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM30 CPU wakeup with interrupt mask on event input 30 1 IM31 CPU wakeup with interrupt mask on event input 31 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 C2IMR2 C2IMR2 EXTI CPUm wakeup with interrupt mask register 0xD0 32 read-write n 0x0 0x0 IM32 CPU wakeup with interrupt mask on event input 0 1 IM33 CPU wakeup with interrupt mask on event input 1 1 IM34 CPU wakeup with interrupt mask on event input 2 1 IM35 CPU wakeup with interrupt mask on event input 3 1 IM36 CPU wakeup with interrupt mask on event input 4 1 IM37 CPU wakeup with interrupt mask on event input 5 1 IM38 CPU wakeup with interrupt mask on event input 6 1 IM39 CPU wakeup with interrupt mask on event input 7 1 IM40 CPU wakeup with interrupt mask on event input 8 1 IM41 CPU wakeup with interrupt mask on event input 9 1 IM42 CPU wakeup with interrupt mask on event input 10 1 IM43 CPU wakeup with interrupt mask on event input 11 1 IM44 CPU wakeup with interrupt mask on event input 12 1 IM45 CPU wakeup with interrupt mask on event input 13 1 IM46 CPU wakeup with interrupt mask on event input 14 1 IM47 CPU wakeup with interrupt mask on event input 15 1 IM48 CPU wakeup with interrupt mask on event input 16 1 IM49 CPU wakeup with interrupt mask on event input 17 1 IM50 CPU wakeup with interrupt mask on event input 18 1 IM51 CPU wakeup with interrupt mask on event input 19 1 IM52 CPU wakeup with interrupt mask on event input 20 1 IM53 CPU wakeup with interrupt mask on event input 21 1 IM54 CPU wakeup with interrupt mask on event input 22 1 IM55 CPU wakeup with interrupt mask on event input 23 1 IM56 CPU wakeup with interrupt mask on event input 24 1 IM57 CPU wakeup with interrupt mask on event input 25 1 IM58 CPU wakeup with interrupt mask on event input 26 1 IM59 CPU wakeup with interrupt mask on event input 27 1 IM60 CPU wakeup with interrupt mask on event input 28 1 IM61 CPU wakeup with interrupt mask on event input 29 1 IM62 CPU wakeup with interrupt mask on event input 30 1 IM63 CPU wakeup with interrupt mask on event input 31 1 C2IMR3 C2IMR3 EXTI CPUm wakeup with interrupt mask register 0xE0 32 read-write n 0x0 0x0 IM64 CPU wakeup with interrupt mask on event input 0 1 IM65 CPU wakeup with interrupt mask on event input 1 1 IM66 CPU wakeup with interrupt mask on event input 2 1 IM67 CPU wakeup with interrupt mask on event input 3 1 IM68 CPU wakeup with interrupt mask on event input 4 1 IM69 CPU wakeup with interrupt mask on event input 5 1 IM70 CPU wakeup with interrupt mask on event input 6 1 IM71 CPU wakeup with interrupt mask on event input 7 1 IM72 CPU wakeup with interrupt mask on event input 8 1 IM73 CPU wakeup with interrupt mask on event input 9 1 IM74 CPU wakeup with interrupt mask on event input 10 1 IM75 CPU wakeup with interrupt mask on event input 11 1 EMR1 EMR1 EXTI CPUm wakeup with event mask register 0x84 32 read-write n 0x0 0x0 EM0 CPU wakeup with interrupt mask on event input 0 1 EM1 CPU wakeup with interrupt mask on event input 1 1 EM10 CPU wakeup with interrupt mask on event input 10 1 EM11 CPU wakeup with interrupt mask on event input 11 1 EM12 CPU wakeup with interrupt mask on event input 12 1 EM13 CPU wakeup with interrupt mask on event input 13 1 EM14 CPU wakeup with interrupt mask on event input 14 1 EM15 CPU wakeup with interrupt mask on event input 15 1 EM17 CPU wakeup with interrupt mask on event input 17 1 EM18 CPU wakeup with interrupt mask on event input 18 1 EM19 CPU wakeup with interrupt mask on event input 19 1 EM2 CPU wakeup with interrupt mask on event input 2 1 EM3 CPU wakeup with interrupt mask on event input 3 1 EM4 CPU wakeup with interrupt mask on event input 4 1 EM5 CPU wakeup with interrupt mask on event input 5 1 EM6 CPU wakeup with interrupt mask on event input 6 1 EM7 CPU wakeup with interrupt mask on event input 7 1 EM8 CPU wakeup with interrupt mask on event input 8 1 EM9 CPU wakeup with interrupt mask on event input 9 1 EMR3 EMR3 EXTI CPUm wakeup with event mask register 0xA4 32 read-write n 0x0 0x0 EM66 CPU wakeup with interrupt mask on event input 2 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 32 read-write n 0x0 0x0 EXTI0_7 GPIO port selection 0 8 EXTI16_23 GPIO port selection 16 8 EXTI24_31 GPIO port selection 24 8 EXTI8_15 GPIO port selection 8 8 FPR1 FPR1 EXTI falling edge pending register 0x10 32 read-write n 0x0 0x0 FPIF0 configurable event inputs x falling edge pending bit. 0 1 FPIF1 configurable event inputs x falling edge pending bit. 1 1 FPIF10 configurable event inputs x falling edge pending bit. 10 1 FPIF11 configurable event inputs x falling edge pending bit. 11 1 FPIF12 configurable event inputs x falling edge pending bit. 12 1 FPIF13 configurable event inputs x falling edge pending bit. 13 1 FPIF14 configurable event inputs x falling edge pending bit. 14 1 FPIF15 configurable event inputs x falling edge pending bit. 15 1 FPIF16 configurable event inputs x falling edge pending bit. 16 1 FPIF2 configurable event inputs x falling edge pending bit. 2 1 FPIF3 configurable event inputs x falling edge pending bit. 3 1 FPIF4 configurable event inputs x falling edge pending bit. 4 1 FPIF5 configurable event inputs x falling edge pending bit. 5 1 FPIF6 configurable event inputs x falling edge pending bit. 6 1 FPIF7 configurable event inputs x falling edge pending bit. 7 1 FPIF8 configurable event inputs x falling edge pending bit. 8 1 FPIF9 configurable event inputs x falling edge pending bit. 9 1 FPR3 FPR3 EXTI falling edge pending register 0x50 32 read-write n 0x0 0x0 FPIF65 FPIF 1 1 FPIF66 FPIF 2 1 FPIF68 FPIF 4 1 FPIF73 FPIF 9 1 FPIF74 FPIF 10 1 FTSR1 FTSR1 EXTI falling trigger selection register 0x4 32 read-write n 0x0 0x0 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 FTSR3 FTSR3 EXTI falling trigger selection register 0x44 32 read-write n 0x0 0x0 FT65 FT 1 1 FT66 FT 2 1 FT68 FT 4 1 FT73 FT 9 1 FT74 FT 10 1 HWCFGR1 HWCFGR1 Hardware configuration registers 0x3F0 32 read-only n 0x0 0x0 CPUEVTEN HW configuration of CPU event output enable 12 4 NBCPUS configuration number of CPUs 8 4 NBEVENTS configuration number of event 0 8 NBIOPORT HW configuration of number of IO ports 16 8 HWCFGR11 HWCFGR11 Hardware configuration registers 0x3C8 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR12 HWCFGR12 Hardware configuration registers 0x3C4 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR13 HWCFGR13 Hardware configuration registers 0x3C0 32 read-only n 0x0 0x0 TZ TZ 0 32 HWCFGR2 HWCFGR2 Hardware configuration registers 0x3EC 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR3 HWCFGR3 Hardware configuration registers 0x3E8 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR4 HWCFGR4 Hardware configuration registers 0x3E4 32 read-write n 0x0 0x0 EVENT_TRG HW configuration event trigger type 0 32 HWCFGR5 HWCFGR5 Hardware configuration registers 0x3E0 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR6 HWCFGR6 Hardware configuration registers 0x3DC 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 HWCFGR7 HWCFGR7 Hardware configuration registers 0x3D8 32 read-write n 0x0 0x0 CPUEVENT HW configuration CPU event generation 0 32 IMR1 IMR1 EXTI CPU wakeup with interrupt mask register 0x80 32 read-write n 0x0 0x0 IM0 CPU wakeup with interrupt mask on event input 0 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM21 CPU wakeup with interrupt mask on event input 21 1 IM22 CPU wakeup with interrupt mask on event input 22 1 IM23 CPU wakeup with interrupt mask on event input 23 1 IM24 CPU wakeup with interrupt mask on event input 24 1 IM25 CPU wakeup with interrupt mask on event input 25 1 IM26 CPU wakeup with interrupt mask on event input 26 1 IM27 CPU wakeup with interrupt mask on event input 27 1 IM28 CPU wakeup with interrupt mask on event input 28 1 IM29 CPU wakeup with interrupt mask on event input 29 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM30 CPU wakeup with interrupt mask on event input 30 1 IM31 CPU wakeup with interrupt mask on event input 31 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IMR2 IMR2 EXTI CPUm wakeup with interrupt mask register 0x90 32 read-write n 0x0 0x0 IM32 CPU wakeup with interrupt mask on event input 0 1 IM33 CPU wakeup with interrupt mask on event input 1 1 IM34 CPU wakeup with interrupt mask on event input 2 1 IM35 CPU wakeup with interrupt mask on event input 3 1 IM36 CPU wakeup with interrupt mask on event input 4 1 IM37 CPU wakeup with interrupt mask on event input 5 1 IM38 CPU wakeup with interrupt mask on event input 6 1 IM39 CPU wakeup with interrupt mask on event input 7 1 IM40 CPU wakeup with interrupt mask on event input 8 1 IM41 CPU wakeup with interrupt mask on event input 9 1 IM42 CPU wakeup with interrupt mask on event input 10 1 IM43 CPU wakeup with interrupt mask on event input 11 1 IM44 CPU wakeup with interrupt mask on event input 12 1 IM45 CPU wakeup with interrupt mask on event input 13 1 IM46 CPU wakeup with interrupt mask on event input 14 1 IM47 CPU wakeup with interrupt mask on event input 15 1 IM48 CPU wakeup with interrupt mask on event input 16 1 IM49 CPU wakeup with interrupt mask on event input 17 1 IM50 CPU wakeup with interrupt mask on event input 18 1 IM51 CPU wakeup with interrupt mask on event input 19 1 IM52 CPU wakeup with interrupt mask on event input 20 1 IM53 CPU wakeup with interrupt mask on event input 21 1 IM54 CPU wakeup with interrupt mask on event input 22 1 IM55 CPU wakeup with interrupt mask on event input 23 1 IM56 CPU wakeup with interrupt mask on event input 24 1 IM57 CPU wakeup with interrupt mask on event input 25 1 IM58 CPU wakeup with interrupt mask on event input 26 1 IM59 CPU wakeup with interrupt mask on event input 27 1 IM60 CPU wakeup with interrupt mask on event input 28 1 IM61 CPU wakeup with interrupt mask on event input 29 1 IM62 CPU wakeup with interrupt mask on event input 30 1 IM63 CPU wakeup with interrupt mask on event input 31 1 IMR3 IMR3 EXTI CPUm wakeup with interrupt mask register 0xA0 32 read-write n 0x0 0x0 IM64 CPU wakeup with interrupt mask on event input 0 1 IM65 CPU wakeup with interrupt mask on event input 1 1 IM66 CPU wakeup with interrupt mask on event input 2 1 IM67 CPU wakeup with interrupt mask on event input 3 1 IM68 CPU wakeup with interrupt mask on event input 4 1 IM69 CPU wakeup with interrupt mask on event input 5 1 IM70 CPU wakeup with interrupt mask on event input 6 1 IM71 CPU wakeup with interrupt mask on event input 7 1 IM72 CPU wakeup with interrupt mask on event input 8 1 IM73 CPU wakeup with interrupt mask on event input 9 1 IM74 CPU wakeup with interrupt mask on event input 10 1 IM75 CPU wakeup with interrupt mask on event input 11 1 IPIDR IPIDR AES identification register 0x3F8 32 read-only n 0x0 0x0 ID Identification code 0 32 RPR1 RPR1 EXTI rising edge pending register 0xC 32 read-write n 0x0 0x0 RPIF0 configurable event inputs x rising edge Pending bit. 0 1 RPIF1 configurable event inputs x rising edge Pending bit. 1 1 RPIF10 configurable event inputs x rising edge Pending bit. 10 1 RPIF11 configurable event inputs x rising edge Pending bit. 11 1 RPIF12 configurable event inputs x rising edge Pending bit. 12 1 RPIF13 configurable event inputs x rising edge Pending bit. 13 1 RPIF14 configurable event inputs x rising edge Pending bit. 14 1 RPIF15 configurable event inputs x rising edge Pending bit. 15 1 RPIF16 configurable event inputs x rising edge Pending bit. 16 1 RPIF2 configurable event inputs x rising edge Pending bit. 2 1 RPIF3 configurable event inputs x rising edge Pending bit. 3 1 RPIF4 configurable event inputs x rising edge Pending bit. 4 1 RPIF5 configurable event inputs x rising edge Pending bit 5 1 RPIF6 configurable event inputs x rising edge Pending bit. 6 1 RPIF7 configurable event inputs x rising edge Pending bit. 7 1 RPIF8 configurable event inputs x rising edge Pending bit. 8 1 RPIF9 configurable event inputs x rising edge Pending bit. 9 1 RPR3 RPR3 EXTI rising edge pending register 0x4C 32 read-write n 0x0 0x0 RPIF65 RPIF 1 1 RPIF66 RPIF 2 1 RPIF68 RPIF 4 1 RPIF73 RPIF 9 1 RPIF74 RPIF 10 1 RTSR1 RTSR1 EXTI rising trigger selection register 0x0 32 read-write n 0x0 0x0 TR0 Rising trigger event configuration bit of Configurable Event input 0 1 TR1 Rising trigger event configuration bit of Configurable Event input 1 1 TR10 Rising trigger event configuration bit of Configurable Event input 10 1 TR11 Rising trigger event configuration bit of Configurable Event input 11 1 TR12 Rising trigger event configuration bit of Configurable Event input 12 1 TR13 Rising trigger event configuration bit of Configurable Event input 13 1 TR14 Rising trigger event configuration bit of Configurable Event input 14 1 TR15 Rising trigger event configuration bit of Configurable Event input 15 1 TR16 Rising trigger event configuration bit of Configurable Event input 16 1 TR2 Rising trigger event configuration bit of Configurable Event input 2 1 TR3 Rising trigger event configuration bit of Configurable Event input 3 1 TR4 Rising trigger event configuration bit of Configurable Event input 4 1 TR5 Rising trigger event configuration bit of Configurable Event input 5 1 TR6 Rising trigger event configuration bit of Configurable Event input 6 1 TR7 Rising trigger event configuration bit of Configurable Event input 7 1 TR8 Rising trigger event configuration bit of Configurable Event input 8 1 TR9 Rising trigger event configuration bit of Configurable Event input 9 1 RTSR3 RTSR3 EXTI rising trigger selection register 0x40 32 read-write n 0x0 0x0 RT65 RT 1 1 RT66 RT 2 1 RT68 RT 4 1 RT73 RT 9 1 RT74 RT 10 1 SIDR SIDR AES size ID register 0x3FC 32 read-only n 0x0 0x0 ID Size Identification code 0 32 SWIER1 SWIER1 EXTI software interrupt event register 0x8 32 read-write n 0x0 0x0 SWIER0 Rising trigger event configuration bit of Configurable Event input 0 1 SWIER1 Rising trigger event configuration bit of Configurable Event input 1 1 SWIER10 Rising trigger event configuration bit of Configurable Event input 10 1 SWIER11 Rising trigger event configuration bit of Configurable Event input 11 1 SWIER12 Rising trigger event configuration bit of Configurable Event input 12 1 SWIER13 Rising trigger event configuration bit of Configurable Event input 13 1 SWIER14 Rising trigger event configuration bit of Configurable Event input 14 1 SWIER15 Rising trigger event configuration bit of Configurable Event input 15 1 SWIER16 Rising trigger event configuration bit of Configurable Event input 16 1 SWIER2 Rising trigger event configuration bit of Configurable Event input 2 1 SWIER3 Rising trigger event configuration bit of Configurable Event input 3 1 SWIER4 Rising trigger event configuration bit of Configurable Event input 4 1 SWIER5 Rising trigger event configuration bit of Configurable Event input 5 1 SWIER6 Rising trigger event configuration bit of Configurable Event input 6 1 SWIER7 Rising trigger event configuration bit of Configurable Event input 7 1 SWIER8 Rising trigger event configuration bit of Configurable Event input 8 1 SWIER9 Rising trigger event configuration bit of Configurable Event input 9 1 SWIER3 SWIER3 EXTI software interrupt event register 0x48 32 read-write n 0x0 0x0 SW65 SW 1 1 SW66 SW 2 1 SW68 SW 4 1 SW73 SW 9 1 SW74 SW 10 1 TZENR1 TZENR1 EXTI TrustZone enable register 0x14 32 read-write n 0x0 0x0 TZEN0 TZEN 0 1 TZEN1 TZEN 1 1 TZEN10 TZEN 10 1 TZEN11 TZEN 11 1 TZEN12 TZEN 12 1 TZEN13 TZEN 13 1 TZEN14 TZEN 14 1 TZEN15 TZEN 15 1 TZEN17 TZEN 17 1 TZEN18 TZEN 18 1 TZEN19 TZEN 19 1 TZEN2 TZEN 2 1 TZEN24 TZEN 24 1 TZEN26 TZEN 26 1 TZEN3 TZEN 3 1 TZEN4 TZEN 4 1 TZEN5 TZEN 5 1 TZEN6 TZEN 6 1 TZEN7 TZEN 7 1 TZEN8 TZEN 8 1 TZEN9 TZEN 9 1 TZENR2 TZENR2 EXTI TrustZone enable register 0x34 32 read-write n 0x0 0x0 TZEN41 TZEN 9 1 TZEN54 TZEN 22 1 TZEN55 TZEN 23 1 TZEN56 TZEN 24 1 TZEN57 TZEN 25 1 TZEN58 TZEN 26 1 TZEN59 TZEN 27 1 TZEN60 TZEN 28 1 VERR VERR AES version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major revision 4 4 MINREV Minor revision 0 4 FDCAN1 FDCAN1 FDCAN 0x0 0x0 0x400 registers n FDCAN_CCCR FDCAN_CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 read-write B_0x0 Normal CAN operation 0x0 B_0x1 Restricted Operation Mode active 0x1 BRSE BRSE 9 1 read-write B_0x0 Bit rate switching for transmissions disabled 0x0 B_0x1 Bit rate switching for transmissions enabled 0x1 CCE CCE 1 1 read-write B_0x0 The CPU has no write access to the protected configuration registers 0x0 B_0x1 The CPU has write access to the protected configuration registers (while CCCR.INIT = 1 ) 0x1 CSA CSA 3 1 read-write B_0x0 No clock stop acknowledged 0x0 B_0x1 FDCAN may be set in power down by stopping APB clock and kernel clock 0x1 CSR CSR 4 1 read-write B_0x0 No clock stop is requested 0x0 B_0x1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set 0x1 DAR DAR 6 1 read-write B_0x0 Automatic retransmission of messages not transmitted successfully enabled 0x0 B_0x1 Automatic retransmission disabled 0x1 EFBI EFBI 13 1 read-write B_0x0 Edge filtering disabled 0x0 B_0x1 Two consecutive dominant tq required to detect an edge for hard synchronization 0x1 FDOE FDOE 8 1 read-write B_0x0 FD operation disabled 0x0 B_0x1 FD operation enabled 0x1 INIT INIT 0 1 read-write B_0x0 Normal Operation 0x0 B_0x1 Initialization is started 0x1 MON MON 5 1 read-write B_0x0 Bus Monitoring Mode is disabled 0x0 B_0x1 Bus Monitoring Mode is enabled 0x1 NISO NISO 15 1 read-write B_0x0 CAN FD frame format according to ISO11898-1 0x0 B_0x1 CAN FD frame format according to Bosch CAN FD Specification V1.0 0x1 PXHD PXHD 12 1 read-write B_0x0 Protocol exception handling enabled 0x0 B_0x1 Protocol exception handling disabled 0x1 TEST TEST 7 1 read-write B_0x0 Normal operation, register TEST holds reset values 0x0 B_0x1 Test Mode, write access to register TEST enabled 0x1 TXP TXP 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 FDCAN_CREL FDCAN_CREL FDCAN Core Release Register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 read-only MON MON 8 8 read-only REL REL 28 4 read-only STEP STEP 24 4 read-only SUBSTEP SUBSTEP 20 4 read-only YEAR YEAR 16 4 read-only FDCAN_DBTP FDCAN_DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 read-write DSJW DSJW 0 4 read-write DTSEG1 DTSEG1 8 5 write-only DTSEG2 DTSEG2 4 4 read-write TDC TDC 23 1 read-only B_0x0 Transceiver Delay Compensation disabled 0x0 B_0x1 Transceiver Delay Compensation enabled 0x1 FDCAN_ECR FDCAN_ECR FDCAN Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CEL 16 8 read-only RP RP 15 1 read-only B_0x0 The Receive Error Counter is below the error passive level of 128 0x0 B_0x1 The Receive Error Counter has reached the error passive level of 128 0x1 TEC TEC 0 8 read-only TREC TREC 8 7 read-only FDCAN_ENDN FDCAN_ENDN FDCAN Core Release Register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 read-only FDCAN_GFC FDCAN_GFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 write-only B_0x0 Accept in Rx FIFO 0 0x0 B_0x1 Accept in Rx FIFO 1 0x1 B_0x2 Reject 0x2 B_0x3 Reject 0x3 ANFS ANFS 4 2 write-only B_0x0 Accept in Rx FIFO 0 0x0 B_0x1 Accept in Rx FIFO 1 0x1 B_0x2 Reject 0x2 B_0x3 Reject 0x3 RRFE RRFE 0 1 read-write B_0x0 Filter remote frames with 29-bit standard IDs 0x0 B_0x1 Reject all remote frames with 29-bit standard IDs 0x1 RRFS RRFS 1 1 read-write B_0x0 Filter remote frames with 11-bit standard IDs 0x0 B_0x1 Reject all remote frames with 11-bit standard IDs 0x1 FDCAN_HPMS FDCAN_HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x94 32 read-only n 0x0 0x0 BIDX BIDX 0 6 read-only FIDX FIDX 8 7 read-only FLST FLST 15 1 read-only B_0x0 Standard Filter List 0x0 B_0x1 Extended Filter List 0x1 MSI MSI 6 2 read-only B_0x0 No FIFO selected 0x0 B_0x1 FIFO overrun 0x1 B_0x2 Message stored in FIFO 0 0x2 B_0x3 Message stored in FIFO 1 0x3 FDCAN_IE FDCAN_IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 read-write BECE BECE 20 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 BEUE BEUE 21 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 BOE BOE 25 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 DRX DRX 19 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 ELOE ELOE 22 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 EPE EPE 23 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 EWE EWE 24 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 HPME HPME 8 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 MRAFE MRAFE 17 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 PEAE PEAE 27 1 read-write PEDE PEDE 28 1 read-write RF0FE RF0FE 2 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0LE RF0LE 3 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0NE RF0NE 0 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0WE RF0WE 1 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1FE RF1FE 6 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1LE RF1LE 7 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1NE RF1NE 4 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1WE RF1WE 5 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TCE TCE 9 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TCFE TCFE 10 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFFE TEFFE 14 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFLE TEFLE 15 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFNE TEFNE 12 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFWE TEFWE 13 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TFEE TFEE 11 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TOOE TOOE 18 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TSWE TSWE 16 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 WDIE WDIE 26 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 FDCAN_ILE FDCAN_ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 read-write B_0x0 Interrupt line fdcan_intr1_it disabled 0x0 B_0x1 Interrupt line fdcan_intr1_it enabled 0x1 EINT1 EINT1 1 1 read-write B_0x0 Interrupt line fdcan_intr0_it disabled 0x0 B_0x1 Interrupt line fdcan_intr0_it enabled 0x1 FDCAN_ILS FDCAN_ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 read-write BECL BECL 20 1 read-write BEUL BEUL 21 1 read-write BOL BOL 25 1 read-write DRXL DRXL 19 1 read-write ELOL ELOL 22 1 read-write EPL EPL 23 1 read-write EWL EWL 24 1 read-write HPML HPML 8 1 read-write MRAFL MRAFL 17 1 read-write PEAL PEAL 27 1 read-write PEDL PEDL 28 1 read-write RF0FL RF0FL 2 1 read-write RF0LL RF0LL 3 1 read-write RF0NL RF0NL 0 1 read-write RF0WL RF0WL 1 1 read-write RF1FL RF1FL 6 1 read-write RF1LL RF1LL 7 1 read-write RF1NL RF1NL 4 1 read-write RF1WL RF1WL 5 1 read-write TCFL TCFL 10 1 read-write TCL TCL 9 1 read-write TEFFL TEFFL 14 1 read-write TEFLL TEFLL 15 1 read-write TEFNL TEFNL 12 1 read-write TEFWL TEFWL 13 1 read-write TFEL TFEL 11 1 read-write TOOL TOOL 18 1 read-write TSWL TSWL 16 1 read-write WDIL WDIL 26 1 read-write FDCAN_IR FDCAN_IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 read-write B_0x0 No access to reserved address occurred 0x0 B_0x1 Access to reserved address occurred 0x1 BO BO 25 1 read-write B_0x0 Bus_Off status unchanged 0x0 B_0x1 Bus_Off status changed 0x1 DRX DRX 19 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 ELO ELO 22 1 read-write B_0x0 CAN Error Logging Counter did not overflow 0x0 B_0x1 Overflow of CAN Error Logging Counter occurred 0x1 EP EP 23 1 read-write B_0x0 Error_Passive status unchanged 0x0 B_0x1 Error_Passive status changed 0x1 EW EW 24 1 read-write B_0x0 Error_Warning status unchanged 0x0 B_0x1 Error_Warning status changed 0x1 HPM HPM 8 1 read-write B_0x0 No high priority message received 0x0 B_0x1 High priority message received 0x1 MRAF MRAF 17 1 read-write B_0x0 No Message RAM access failure occurred 0x0 B_0x1 Message RAM access failure occurred 0x1 PEA PEA 27 1 read-write B_0x0 No protocol error in arbitration phase 0x0 B_0x1 Protocol error in arbitration phase detected (PSR.LEC different from 0,7) 0x1 PED PED 28 1 read-write B_0x0 No protocol error in data phase 0x0 B_0x1 Protocol error in data phase detected (PSR.DLEC different from 0,7) 0x1 RF0F RF0F 2 1 read-write B_0x0 Rx FIFO 0 not full 0x0 B_0x1 Rx FIFO 0 full 0x1 RF0L RF0L 3 1 read-write B_0x0 No Rx FIFO 0 message lost 0x0 B_0x1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x1 RF0N RF0N 0 1 read-write B_0x0 No new message written to Rx FIFO 0 0x0 B_0x1 New message written to Rx FIFO 0 0x1 RF0W RF0W 1 1 read-write B_0x0 Rx FIFO 0 fill level below watermark 0x0 B_0x1 Rx FIFO 0 fill level reached watermark 0x1 RF1F RF1F 6 1 read-write B_0x0 Rx FIFO 1 not full 0x0 B_0x1 Rx FIFO 1 full 0x1 RF1L RF1L 7 1 read-write B_0x0 No Rx FIFO 1 message lost 0x0 B_0x1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x1 RF1N RF1N 4 1 read-write B_0x0 No new message written to Rx FIFO 1 0x0 B_0x1 New message written to Rx FIFO 1 0x1 RF1W RF1W 5 1 read-write B_0x0 Rx FIFO 1 fill level below watermark 0x0 B_0x1 Rx FIFO 1 fill level reached watermark 0x1 TC TC 9 1 read-write B_0x0 No transmission completed 0x0 B_0x1 Transmission completed 0x1 TCF TCF 10 1 read-write B_0x0 No transmission cancellation finished 0x0 B_0x1 Transmission cancellation finished 0x1 TEFF TEFF 14 1 read-write B_0x0 Tx Event FIFO not full 0x0 B_0x1 Tx Event FIFO full 0x1 TEFL TEFL 15 1 read-write B_0x0 No Tx Event FIFO element lost 0x0 B_0x1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero 0x1 TEFN TEFN 12 1 read-write B_0x0 Tx Event FIFO unchanged 0x0 B_0x1 Tx Handler wrote Tx Event FIFO element 0x1 TEFW TEFW 13 1 read-write B_0x0 Tx Event FIFO fill level below watermark 0x0 B_0x1 Tx Event FIFO fill level reached watermark 0x1 TFE TFE 11 1 read-write B_0x0 Tx FIFO non-empty 0x0 B_0x1 Tx FIFO empty 0x1 TOO TOO 18 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 TSW TSW 16 1 read-write B_0x0 No timestamp counter wrap-around 0x0 B_0x1 Timestamp counter wrapped around 0x1 WDI WDI 26 1 read-write B_0x0 No Message RAM Watchdog event occurred 0x0 B_0x1 Message RAM Watchdog event due to missing READY 0x1 FDCAN_NBTP FDCAN_NBTP FDCAN_NBTP 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 read-write NSJW NSJW 25 7 read-write NTSEG1 NTSEG1 8 8 read-write TSEG2 TSEG2 0 7 read-write FDCAN_NDAT1 FDCAN_NDAT1 FDCAN new data 1 register 0x98 32 read-write n 0x0 0x0 ND0 ND0 0 1 ND1 ND1 1 1 ND10 ND10 10 1 ND11 ND11 11 1 ND12 ND12 12 1 ND13 ND13 13 1 ND14 ND14 14 1 ND15 ND15 15 1 ND16 ND16 16 1 ND17 ND17 17 1 ND18 ND18 18 1 ND19 ND19 19 1 ND2 ND2 2 1 ND20 ND20 20 1 ND21 ND21 21 1 ND22 ND22 22 1 ND23 ND23 23 1 ND24 ND24 24 1 ND25 ND25 25 1 ND26 ND26 26 1 ND27 ND27 27 1 ND28 ND28 28 1 ND29 ND29 29 1 ND3 ND3 3 1 ND30 ND30 30 1 ND31 ND31 31 1 ND4 ND4 4 1 ND5 ND5 5 1 ND6 ND6 6 1 ND7 ND7 7 1 ND8 ND8 8 1 ND9 ND9 9 1 FDCAN_NDAT2 FDCAN_NDAT2 FDCAN new data 2 register 0x9C 32 read-write n 0x0 0x0 ND32 ND32 0 1 ND33 ND33 1 1 ND34 ND34 2 1 ND35 ND35 3 1 ND36 ND36 4 1 ND37 ND37 5 1 ND38 ND38 6 1 ND39 ND39 7 1 ND40 ND40 8 1 ND41 ND41 9 1 ND42 ND42 10 1 ND43 ND43 11 1 ND44 ND44 12 1 ND45 ND45 13 1 ND46 ND46 14 1 ND47 ND47 15 1 ND48 ND48 16 1 ND49 ND49 17 1 ND50 ND50 18 1 ND51 ND51 19 1 ND52 ND52 20 1 ND53 ND53 21 1 ND54 ND54 22 1 ND55 ND55 23 1 ND56 ND56 24 1 ND57 ND57 25 1 ND58 ND58 26 1 ND59 ND59 27 1 ND60 ND60 28 1 ND61 ND61 29 1 ND62 ND62 30 1 ND63 ND63 31 1 FDCAN_PSR FDCAN_PSR FDCAN Protocol Status Register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 write-only B_0x0 Synchronizing: node is synchronizing on CAN communication 0x0 B_0x1 Idle: node is neither receiver nor transmitter 0x1 B_0x2 Receiver: node is operating as receiver 0x2 B_0x3 Transmitter: node is operating as transmitter 0x3 BO BO 7 1 read-write B_0x0 The FDCAN is not Bus_Off 0x0 B_0x1 The FDCAN is in Bus_Off state 0x1 DLEC DLEC 8 3 write-only EP EP 5 1 read-write B_0x0 The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 0x0 B_0x1 The FDCAN is in the Error_Passive state 0x1 EW EW 6 1 read-write B_0x0 Both error counters are below the Error_Warning limit of 96 0x0 B_0x1 At least one of error counter has reached the Error_Warning limit of 96 0x1 LEC LEC 0 3 read-write B_0x0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 0x0 B_0x1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 B_0x2 Form Error: A fixed format part of a received frame has the wrong format. 0x2 B_0x3 AckError: The message transmitted by the FDCAN was not acknowledged by another node. 0x3 B_0x4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1 ), but the monitored bus value was dominant. 0x4 B_0x5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0 ), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 0x5 B_0x6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 0x6 B_0x7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7 . When the LEC shows the value 7 , no CAN bus event was detected since the last CPU read access to the Protocol Status Register. 0x7 PXE PXE 14 1 read-write B_0x0 No protocol exception event occurred since last read access 0x0 B_0x1 Protocol exception event occurred 0x1 RBRS RBRS 12 1 read-write B_0x0 Last received FDCAN message did not ha ve its BRS flag set 0x0 B_0x1 Last received FDCAN message had its BRS flag set 0x1 REDL REDL 13 1 read-write B_0x0 Since this bit was reset by the CPU, no FDCAN message has been received 0x0 B_0x1 Message in FDCAN format with EDL flag set has been received 0x1 RESI RESI 11 1 read-write B_0x0 Last received FDCAN message did not have its ESI flag set 0x0 B_0x1 Last received FDCAN message had its ESI flag set 0x1 TDCV TDCV 16 7 read-write FDCAN_RWD FDCAN_RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only FDCAN_RXBC FDCAN_RXBC FDCAN Rx buffer configuration register 0xAC 32 read-write n 0x0 0x0 RBSA RBSA 2 14 read-write FDCAN_RXESC FDCAN_RXESC Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. 0xBC 32 read-only n 0x0 0x0 F0DS F0DS 0 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 F1DS F1DS 4 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 RBDS RBDS 8 3 read-only FDCAN_RXF0A FDCAN_RXF0A CAN Rx FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 0x0 F0AI F0AI 0 6 read-write FDCAN_RXF0C FDCAN_RXF0C FDCAN Rx FIFO Configuration Register 0xA0 32 read-write n 0x0 0x0 F0OM F0OM 31 1 read-write F0S F0S 16 7 read-write F0SA F0SA 2 14 read-write F0WM F0WM 24 7 read-write FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 Status Register 0xA4 32 read-write n 0x0 0x0 F0F F0F 24 1 read-write B_0x0 Rx FIFO 0 not full 0x0 B_0x1 Rx FIFO 0 full 0x1 F0FL F0FL 0 7 read-write F0GI F0GI 8 6 read-write F0PI F0PI 16 6 read-write RF0L RF0L 25 1 read-write B_0x0 No Rx FIFO 0 message lost 0x0 B_0x1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x1 FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 0x0 F1AI F1AI 0 6 read-write FDCAN_RXF1C FDCAN_RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 32 read-write n 0x0 0x0 F1OM F1OM 31 1 read-write F1S F1S 16 7 read-write F1SA F1SA 2 14 read-write F1WM F1WM 24 7 read-write FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 Status Register 0xB4 32 read-only n 0x0 0x0 DMS DMS 30 2 read-only F1F F1F 24 1 read-only B_0x0 Rx FIFO 1 not full 0x0 B_0x1 Rx FIFO 1 full 0x1 F1FL F1FL 0 7 read-only F1GI F1GI 8 6 read-only F1PI F1PI 16 6 read-only RF1L RF1L 25 1 read-only B_0x0 No Rx FIFO 1 message lost 0x0 B_0x1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. 0x1 FDCAN_SIDFC FDCAN_SIDFC Settings for 11-bit standard Message ID filtering.The Standard ID Filter Configuration controls the filter path for standard messages as described in Figure706: Standard Message ID filter path. 0x84 32 read-write n 0x0 0x0 FLSSA FLSSA 2 14 read-write LSS LSS 16 8 read-write B_0x0 No standard Message ID filter 0x0 FDCAN_TDCR FDCAN_TDCR FDCAN Transmitter Delay Compensation Register 0x48 32 read-only n 0x0 0x0 TDCF TDCF 0 7 read-only TDCO TDCO 8 7 read-only FDCAN_TEST FDCAN_TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 read-write B_0x0 Reset value, Loop Back mode is disabled 0x0 B_0x1 Loop Back mode is enabled (see Test modes) 0x1 RX RX 7 1 read-write B_0x0 The CAN bus is dominant (FDCANx_RX = 0 ) 0x0 B_0x1 The CAN bus is recessive (FDCANx_RX = 1 ) 0x1 TX TX 5 2 read-write B_0x0 Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time 0x0 B_0x1 Sample point can be monitored at pin FDCANx_TX 0x1 B_0x2 Dominant ( 0 ) level at pin FDCANx_TX 0x2 B_0x3 Recessive ( 1 ) at pin FDCANx_TX 0x3 FDCAN_TOCC FDCAN_TOCC FDCAN Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 read-write B_0x0 Timeout Counter disabled 0x0 B_0x1 Timeout Counter enabled 0x1 TOP TOP 16 16 read-write TOS TOS 1 2 write-only B_0x0 Continuous operation 0x0 B_0x1 Timeout controlled by Tx Event FIFO 0x1 B_0x2 Timeout controlled by Rx FIFO 0 0x2 B_0x3 Timeout controlled by Rx FIFO 1 0x3 FDCAN_TOCV FDCAN_TOCV FDCAN Timeout Counter Value Register 0x2C 32 read-only n 0x0 0x0 TOC TOC 0 16 read-only FDCAN_TSCC FDCAN_TSCC FDCAN Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 read-write TSS TSS 0 2 read-write B_0x0 Timestamp counter value always 0x0000 0x0 B_0x1 Timestamp counter value incremented according to TCP 0x1 B_0x2 External timestamp counter from TIM3 value used (tim3_cnt[0:15]) 0x2 B_0x3 Same as 00 . 0x3 FDCAN_TSCV FDCAN_TSCV FDCAN Timestamp Counter Value Register 0x24 32 read-only n 0x0 0x0 TSC TSC 0 16 read-only FDCAN_TTCPT FDCAN_TTCPT FDCAN TT Capture Time Register 0x13C 32 read-only n 0x0 0x0 CT Cycle Count Value 0 6 SWV Stop Watch Value 16 16 FDCAN_TTCSM FDCAN_TTCSM FDCAN TT Cycle Sync Mark Register 0x140 32 read-only n 0x0 0x0 CSM Cycle Sync Mark 0 16 FDCAN_TTCTC FDCAN_TTCTC FDCAN TT Cycle Time and Count Register 0x138 32 read-only n 0x0 0x0 CC Cycle Count 16 6 CT Cycle Time 0 16 FDCAN_TTGTP FDCAN_TTGTP FDCAN TT global time preset register 0x118 32 read-write n 0x0 0x0 CTP CTP 16 16 read-write TP TP 0 16 read-write FDCAN_TTIE FDCAN_TTIE FDCAN TT interrupt enable register 0x124 32 read-write n 0x0 0x0 AWE AWE 17 1 read-write CERE CERE 18 1 read-write CSME CSME 2 1 read-write ELCE ELCE 14 1 read-write GTDE GTDE 8 1 read-write GTEE GTEE 9 1 read-write GTWE GTWE 7 1 read-write IWTGE IWTGE 15 1 read-write RTMIE RTMIE 4 1 read-write SBCE SBCE 0 1 read-write SE1E SE1E 12 1 read-write SE2E SE2E 13 1 read-write SMCE SMCE 1 1 read-write SOGE SOGE 3 1 read-write SWEE SWEE 6 1 read-write TTMIE TTMIE 5 1 read-write TXOE TXOE 11 1 read-write TXUE TXUE 10 1 read-write WTE WTE 16 1 read-write FDCAN_TTILS FDCAN_TTILS FDCAN TT interrupt line select register 0x128 32 read-write n 0x0 0x0 AWL AWL 17 1 read-write CERL CERL 18 1 read-write CSML CSML 2 1 read-write ELCL ELCL 14 1 read-write GTDL GTDL 8 1 read-write GTEL GTEL 9 1 read-write GTWL GTWL 7 1 read-write IWTGL IWTGL 15 1 read-write RTMIL RTMIL 4 1 read-write SBCL SBCL 0 1 read-write SE1L SE1L 12 1 read-write SE2L SE2L 13 1 read-write SMCL SMCL 1 1 read-write SOGL SOGL 3 1 read-write SWEL SWEL 6 1 read-write TTMIL TTMIL 5 1 read-write TXOL TXOL 11 1 read-write TXUL TXUL 10 1 read-write WTL WTL 16 1 read-write FDCAN_TTIR FDCAN_TTIR FDCAN TT Interrupt register 0x120 32 read-write n 0x0 0x0 AW AW 17 1 read-write CER CER 18 1 read-write CSM CSM 2 1 read-write ELC ELC 14 1 read-write GTD GTD 8 1 read-write GTE GTE 9 1 read-write GTW GTW 7 1 read-write IWTG IWTG 15 1 read-write RTMI RTMI 4 1 read-write SBC SBC 0 1 read-write SE1 SE1 12 1 read-write SE2 SE2 13 1 read-write SMC SMC 1 1 read-write SOG SOG 3 1 read-write SWE SWE 6 1 read-write TTMI TTMI 5 1 read-write TXO TXO 11 1 read-write TXU TXU 10 1 read-write WT WT 16 1 read-write FDCAN_TTLGT FDCAN_TTLGT FDCAN TT Local and Global Time Register 0x134 32 read-only n 0x0 0x0 GT Global Time 16 16 LT Local Time 0 16 FDCAN_TTMLM FDCAN_TTMLM FDCAN TT matrix limits register 0x10C 32 read-write n 0x0 0x0 CCM CCM 0 6 read-write CSS CSS 6 2 read-write ENTT ENTT 16 12 read-write TXEW TXEW 8 4 read-write FDCAN_TTOCF FDCAN_TTOCF FDCAN TT operation configuration register 0x108 32 read-write n 0x0 0x0 AWL AWL 16 8 read-write ECC ECC 25 1 read-write EECS EECS 15 1 read-write EGTF EGTF 24 1 read-write EVTP EVTP 26 1 read-write GEN GEN 3 1 read-write IRTO IRTO 8 7 read-write LDSDL LDSDL 5 3 read-write OM OM 0 2 read-write TM TM 4 1 read-write FDCAN_TTOCN FDCAN_TTOCN FDCAN TT operation control register 0x114 32 read-write n 0x0 0x0 ECS ECS 1 1 read-write ESCN ESCN 13 1 read-write FGP FGP 10 1 read-write GCS GCS 9 1 read-write LCKC LCKC 15 1 read-write NIG NIG 12 1 read-write RTIE RTIE 5 1 read-write SGT SGT 0 1 read-write SWP SWP 2 1 read-write SWS SWS 3 2 read-write TMC TMC 6 2 read-write TMG TMG 11 1 read-write TTIE TTIE 8 1 read-write FDCAN_TTOST FDCAN_TTOST FDCAN TT Operation Status Register 0x12C 32 read-write n 0x0 0x0 AWE Application Watchdog Event 29 1 EL Error Level 0 2 GFI Gap Finished Indicator. 23 1 GSI Gap Started Indicator. 27 1 GTP Quality of Global Time Phase 6 1 MS Master State. 2 2 QCS Quality of Clock Speed 7 1 RTO Reference Trigger Offset 8 8 SPL Schedule Phase Lock 31 1 SYS Synchronization State 4 2 TMP Time Master Priority 24 3 WECS Wait for External Clock Synchronization 30 1 WFE Wait for Event 28 1 WGTD Wait for Global Time Discontinuity 22 1 FDCAN_TTRMC FDCAN_TTRMC FDCAN TT reference message configuration register 0x104 32 read-write n 0x0 0x0 RID RID 0 29 read-write RMPS RMPS 31 1 read-write XTD XTD 30 1 read-write FDCAN_TTTMC FDCAN_TTTMC FDCAN TT trigger memory configuration register 0x100 32 read-write n 0x0 0x0 TME TME 16 7 read-write TMSA TMSA 2 14 read-write FDCAN_TTTMK FDCAN_TTTMK FDCAN TT time mark register 0x11C 32 read-write n 0x0 0x0 LCKM LCKM 31 1 read-only TICC TICC 16 7 read-write TM TM 0 16 read-write FDCAN_TTTS FDCAN_TTTS FDCAN TT Trigger Select Register 0x300 32 read-write n 0x0 0x0 EVTSEL Event trigger input selection 4 2 SWTDEL Stop watch trigger input selection 0 2 FDCAN_TURCF FDCAN_TURCF FDCAN TUR configuration register 0x110 32 read-write n 0x0 0x0 DC DC 16 15 read-write ELT ELT 31 1 read-write NCL NCL 0 16 read-write FDCAN_TURNA FDCAN_TURNA FDCAN TUR Numerator Actual Register 0x130 32 read-only n 0x0 0x0 NAV Numerator Actual Value 0 18 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx Buffer Add Request Register 0xD0 32 read-write n 0x0 0x0 AR AR 0 32 read-write B_0x0 No transmission request added 0x0 B_0x1 Transmission requested added. 0x1 FDCAN_TXBC FDCAN_TXBC FDCAN Tx Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 0x0 CF CF 0 32 read-only B_0x0 No transmit buffer cancellation 0x0 B_0x1 Transmit buffer cancellation finished 0x1 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 0x0 CFIE CFIE 0 32 read-write B_0x0 Cancellation finished interrupt disabled 0x0 B_0x1 Cancellation finished interrupt enabled 0x1 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 0x0 CR CR 0 32 read-write B_0x0 No cancellation pending 0x0 B_0x1 Cancellation pending 0x1 FDCAN_TXBRP FDCAN_TXBRP FDCAN Tx Buffer Request Pending Register 0xCC 32 read-only n 0x0 0x0 TRP TRP 0 32 read-only B_0x0 No transmission request pending 0x0 B_0x1 Transmission request pending 0x1 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 TIE TIE 0 32 read-write B_0x0 Transmission interrupt disabled 0x0 B_0x1 Transmission interrupt enable 0x1 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 0x0 TO TO 0 32 read-only B_0x0 No transmission occurred 0x0 B_0x1 Transmission occurred 0x1 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 read-write FDCAN_TXEFC FDCAN_TXEFC FDCAN Tx event FIFO configuration register 0xF0 32 read-write n 0x0 0x0 EFS EFS 16 6 EFSA EFSA 2 14 EFWM EFWM 24 6 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx Event FIFO Status Register 0xF4 32 read-only n 0x0 0x0 EFF EFF 24 1 read-only B_0x0 Tx Event FIFO not full 0x0 B_0x1 Tx Event FIFO full 0x1 EFFL EFFL 0 6 read-only EFGI EFGI 8 5 read-only EFPI EFPI 16 5 read-only TEFL TEFL 25 1 read-only FDCAN_TXESC FDCAN_TXESC Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes greater than 8 bytes are intended for CAN FD operation only. 0xC8 32 read-only n 0x0 0x0 TBDS TBDS 0 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 FDCAN_TXFQS FDCAN_TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 read-only TFGI TFGI 8 5 read-only TFQF TFQF 21 1 read-only TFQPI TFQPI 16 5 read-only FDCAN_XIDAM FDCAN_XIDAM FDCAN Extended ID and Mask Register 0x90 32 read-write n 0x0 0x0 EIDM EIDM 0 29 read-write FDCAN_XIDFC FDCAN_XIDFC Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages as described in Figure707: Extended Message ID filter path. 0x88 32 read-write n 0x0 0x0 FLESA FLESA 2 14 read-write LSE LSE 16 8 read-write B_0x0 No standard Message ID filter 0x0 FDCAN2 FDCAN1 FDCAN 0x0 0x0 0x400 registers n FDCAN_CCCR FDCAN_CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 read-write B_0x0 Normal CAN operation 0x0 B_0x1 Restricted Operation Mode active 0x1 BRSE BRSE 9 1 read-write B_0x0 Bit rate switching for transmissions disabled 0x0 B_0x1 Bit rate switching for transmissions enabled 0x1 CCE CCE 1 1 read-write B_0x0 The CPU has no write access to the protected configuration registers 0x0 B_0x1 The CPU has write access to the protected configuration registers (while CCCR.INIT = 1 ) 0x1 CSA CSA 3 1 read-write B_0x0 No clock stop acknowledged 0x0 B_0x1 FDCAN may be set in power down by stopping APB clock and kernel clock 0x1 CSR CSR 4 1 read-write B_0x0 No clock stop is requested 0x0 B_0x1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set 0x1 DAR DAR 6 1 read-write B_0x0 Automatic retransmission of messages not transmitted successfully enabled 0x0 B_0x1 Automatic retransmission disabled 0x1 EFBI EFBI 13 1 read-write B_0x0 Edge filtering disabled 0x0 B_0x1 Two consecutive dominant tq required to detect an edge for hard synchronization 0x1 FDOE FDOE 8 1 read-write B_0x0 FD operation disabled 0x0 B_0x1 FD operation enabled 0x1 INIT INIT 0 1 read-write B_0x0 Normal Operation 0x0 B_0x1 Initialization is started 0x1 MON MON 5 1 read-write B_0x0 Bus Monitoring Mode is disabled 0x0 B_0x1 Bus Monitoring Mode is enabled 0x1 NISO NISO 15 1 read-write B_0x0 CAN FD frame format according to ISO11898-1 0x0 B_0x1 CAN FD frame format according to Bosch CAN FD Specification V1.0 0x1 PXHD PXHD 12 1 read-write B_0x0 Protocol exception handling enabled 0x0 B_0x1 Protocol exception handling disabled 0x1 TEST TEST 7 1 read-write B_0x0 Normal operation, register TEST holds reset values 0x0 B_0x1 Test Mode, write access to register TEST enabled 0x1 TXP TXP 14 1 read-write B_0x0 disabled 0x0 B_0x1 enabled 0x1 FDCAN_CREL FDCAN_CREL FDCAN Core Release Register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 read-only MON MON 8 8 read-only REL REL 28 4 read-only STEP STEP 24 4 read-only SUBSTEP SUBSTEP 20 4 read-only YEAR YEAR 16 4 read-only FDCAN_DBTP FDCAN_DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 read-write DSJW DSJW 0 4 read-write DTSEG1 DTSEG1 8 5 write-only DTSEG2 DTSEG2 4 4 read-write TDC TDC 23 1 read-only B_0x0 Transceiver Delay Compensation disabled 0x0 B_0x1 Transceiver Delay Compensation enabled 0x1 FDCAN_ECR FDCAN_ECR FDCAN Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CEL 16 8 read-only RP RP 15 1 read-only B_0x0 The Receive Error Counter is below the error passive level of 128 0x0 B_0x1 The Receive Error Counter has reached the error passive level of 128 0x1 TEC TEC 0 8 read-only TREC TREC 8 7 read-only FDCAN_ENDN FDCAN_ENDN FDCAN Core Release Register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 read-only FDCAN_GFC FDCAN_GFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 write-only B_0x0 Accept in Rx FIFO 0 0x0 B_0x1 Accept in Rx FIFO 1 0x1 B_0x2 Reject 0x2 B_0x3 Reject 0x3 ANFS ANFS 4 2 write-only B_0x0 Accept in Rx FIFO 0 0x0 B_0x1 Accept in Rx FIFO 1 0x1 B_0x2 Reject 0x2 B_0x3 Reject 0x3 RRFE RRFE 0 1 read-write B_0x0 Filter remote frames with 29-bit standard IDs 0x0 B_0x1 Reject all remote frames with 29-bit standard IDs 0x1 RRFS RRFS 1 1 read-write B_0x0 Filter remote frames with 11-bit standard IDs 0x0 B_0x1 Reject all remote frames with 11-bit standard IDs 0x1 FDCAN_HPMS FDCAN_HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x94 32 read-only n 0x0 0x0 BIDX BIDX 0 6 read-only FIDX FIDX 8 7 read-only FLST FLST 15 1 read-only B_0x0 Standard Filter List 0x0 B_0x1 Extended Filter List 0x1 MSI MSI 6 2 read-only B_0x0 No FIFO selected 0x0 B_0x1 FIFO overrun 0x1 B_0x2 Message stored in FIFO 0 0x2 B_0x3 Message stored in FIFO 1 0x3 FDCAN_IE FDCAN_IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 read-write BECE BECE 20 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 BEUE BEUE 21 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 BOE BOE 25 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 DRX DRX 19 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 ELOE ELOE 22 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 EPE EPE 23 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 EWE EWE 24 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 HPME HPME 8 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 MRAFE MRAFE 17 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 PEAE PEAE 27 1 read-write PEDE PEDE 28 1 read-write RF0FE RF0FE 2 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0LE RF0LE 3 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0NE RF0NE 0 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF0WE RF0WE 1 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1FE RF1FE 6 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1LE RF1LE 7 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1NE RF1NE 4 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 RF1WE RF1WE 5 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TCE TCE 9 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TCFE TCFE 10 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFFE TEFFE 14 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFLE TEFLE 15 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFNE TEFNE 12 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TEFWE TEFWE 13 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TFEE TFEE 11 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TOOE TOOE 18 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 TSWE TSWE 16 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 WDIE WDIE 26 1 read-write B_0x0 Interrupt disabled 0x0 B_0x1 Interrupt enabled 0x1 FDCAN_ILE FDCAN_ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 read-write B_0x0 Interrupt line fdcan_intr1_it disabled 0x0 B_0x1 Interrupt line fdcan_intr1_it enabled 0x1 EINT1 EINT1 1 1 read-write B_0x0 Interrupt line fdcan_intr0_it disabled 0x0 B_0x1 Interrupt line fdcan_intr0_it enabled 0x1 FDCAN_ILS FDCAN_ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 read-write BECL BECL 20 1 read-write BEUL BEUL 21 1 read-write BOL BOL 25 1 read-write DRXL DRXL 19 1 read-write ELOL ELOL 22 1 read-write EPL EPL 23 1 read-write EWL EWL 24 1 read-write HPML HPML 8 1 read-write MRAFL MRAFL 17 1 read-write PEAL PEAL 27 1 read-write PEDL PEDL 28 1 read-write RF0FL RF0FL 2 1 read-write RF0LL RF0LL 3 1 read-write RF0NL RF0NL 0 1 read-write RF0WL RF0WL 1 1 read-write RF1FL RF1FL 6 1 read-write RF1LL RF1LL 7 1 read-write RF1NL RF1NL 4 1 read-write RF1WL RF1WL 5 1 read-write TCFL TCFL 10 1 read-write TCL TCL 9 1 read-write TEFFL TEFFL 14 1 read-write TEFLL TEFLL 15 1 read-write TEFNL TEFNL 12 1 read-write TEFWL TEFWL 13 1 read-write TFEL TFEL 11 1 read-write TOOL TOOL 18 1 read-write TSWL TSWL 16 1 read-write WDIL WDIL 26 1 read-write FDCAN_IR FDCAN_IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 read-write B_0x0 No access to reserved address occurred 0x0 B_0x1 Access to reserved address occurred 0x1 BO BO 25 1 read-write B_0x0 Bus_Off status unchanged 0x0 B_0x1 Bus_Off status changed 0x1 DRX DRX 19 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 ELO ELO 22 1 read-write B_0x0 CAN Error Logging Counter did not overflow 0x0 B_0x1 Overflow of CAN Error Logging Counter occurred 0x1 EP EP 23 1 read-write B_0x0 Error_Passive status unchanged 0x0 B_0x1 Error_Passive status changed 0x1 EW EW 24 1 read-write B_0x0 Error_Warning status unchanged 0x0 B_0x1 Error_Warning status changed 0x1 HPM HPM 8 1 read-write B_0x0 No high priority message received 0x0 B_0x1 High priority message received 0x1 MRAF MRAF 17 1 read-write B_0x0 No Message RAM access failure occurred 0x0 B_0x1 Message RAM access failure occurred 0x1 PEA PEA 27 1 read-write B_0x0 No protocol error in arbitration phase 0x0 B_0x1 Protocol error in arbitration phase detected (PSR.LEC different from 0,7) 0x1 PED PED 28 1 read-write B_0x0 No protocol error in data phase 0x0 B_0x1 Protocol error in data phase detected (PSR.DLEC different from 0,7) 0x1 RF0F RF0F 2 1 read-write B_0x0 Rx FIFO 0 not full 0x0 B_0x1 Rx FIFO 0 full 0x1 RF0L RF0L 3 1 read-write B_0x0 No Rx FIFO 0 message lost 0x0 B_0x1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x1 RF0N RF0N 0 1 read-write B_0x0 No new message written to Rx FIFO 0 0x0 B_0x1 New message written to Rx FIFO 0 0x1 RF0W RF0W 1 1 read-write B_0x0 Rx FIFO 0 fill level below watermark 0x0 B_0x1 Rx FIFO 0 fill level reached watermark 0x1 RF1F RF1F 6 1 read-write B_0x0 Rx FIFO 1 not full 0x0 B_0x1 Rx FIFO 1 full 0x1 RF1L RF1L 7 1 read-write B_0x0 No Rx FIFO 1 message lost 0x0 B_0x1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero 0x1 RF1N RF1N 4 1 read-write B_0x0 No new message written to Rx FIFO 1 0x0 B_0x1 New message written to Rx FIFO 1 0x1 RF1W RF1W 5 1 read-write B_0x0 Rx FIFO 1 fill level below watermark 0x0 B_0x1 Rx FIFO 1 fill level reached watermark 0x1 TC TC 9 1 read-write B_0x0 No transmission completed 0x0 B_0x1 Transmission completed 0x1 TCF TCF 10 1 read-write B_0x0 No transmission cancellation finished 0x0 B_0x1 Transmission cancellation finished 0x1 TEFF TEFF 14 1 read-write B_0x0 Tx Event FIFO not full 0x0 B_0x1 Tx Event FIFO full 0x1 TEFL TEFL 15 1 read-write B_0x0 No Tx Event FIFO element lost 0x0 B_0x1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero 0x1 TEFN TEFN 12 1 read-write B_0x0 Tx Event FIFO unchanged 0x0 B_0x1 Tx Handler wrote Tx Event FIFO element 0x1 TEFW TEFW 13 1 read-write B_0x0 Tx Event FIFO fill level below watermark 0x0 B_0x1 Tx Event FIFO fill level reached watermark 0x1 TFE TFE 11 1 read-write B_0x0 Tx FIFO non-empty 0x0 B_0x1 Tx FIFO empty 0x1 TOO TOO 18 1 read-write B_0x0 No timeout 0x0 B_0x1 Timeout reached 0x1 TSW TSW 16 1 read-write B_0x0 No timestamp counter wrap-around 0x0 B_0x1 Timestamp counter wrapped around 0x1 WDI WDI 26 1 read-write B_0x0 No Message RAM Watchdog event occurred 0x0 B_0x1 Message RAM Watchdog event due to missing READY 0x1 FDCAN_NBTP FDCAN_NBTP FDCAN_NBTP 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 read-write NSJW NSJW 25 7 read-write NTSEG1 NTSEG1 8 8 read-write TSEG2 TSEG2 0 7 read-write FDCAN_NDAT1 FDCAN_NDAT1 FDCAN new data 1 register 0x98 32 read-write n 0x0 0x0 ND0 ND0 0 1 ND1 ND1 1 1 ND10 ND10 10 1 ND11 ND11 11 1 ND12 ND12 12 1 ND13 ND13 13 1 ND14 ND14 14 1 ND15 ND15 15 1 ND16 ND16 16 1 ND17 ND17 17 1 ND18 ND18 18 1 ND19 ND19 19 1 ND2 ND2 2 1 ND20 ND20 20 1 ND21 ND21 21 1 ND22 ND22 22 1 ND23 ND23 23 1 ND24 ND24 24 1 ND25 ND25 25 1 ND26 ND26 26 1 ND27 ND27 27 1 ND28 ND28 28 1 ND29 ND29 29 1 ND3 ND3 3 1 ND30 ND30 30 1 ND31 ND31 31 1 ND4 ND4 4 1 ND5 ND5 5 1 ND6 ND6 6 1 ND7 ND7 7 1 ND8 ND8 8 1 ND9 ND9 9 1 FDCAN_NDAT2 FDCAN_NDAT2 FDCAN new data 2 register 0x9C 32 read-write n 0x0 0x0 ND32 ND32 0 1 ND33 ND33 1 1 ND34 ND34 2 1 ND35 ND35 3 1 ND36 ND36 4 1 ND37 ND37 5 1 ND38 ND38 6 1 ND39 ND39 7 1 ND40 ND40 8 1 ND41 ND41 9 1 ND42 ND42 10 1 ND43 ND43 11 1 ND44 ND44 12 1 ND45 ND45 13 1 ND46 ND46 14 1 ND47 ND47 15 1 ND48 ND48 16 1 ND49 ND49 17 1 ND50 ND50 18 1 ND51 ND51 19 1 ND52 ND52 20 1 ND53 ND53 21 1 ND54 ND54 22 1 ND55 ND55 23 1 ND56 ND56 24 1 ND57 ND57 25 1 ND58 ND58 26 1 ND59 ND59 27 1 ND60 ND60 28 1 ND61 ND61 29 1 ND62 ND62 30 1 ND63 ND63 31 1 FDCAN_PSR FDCAN_PSR FDCAN Protocol Status Register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 write-only B_0x0 Synchronizing: node is synchronizing on CAN communication 0x0 B_0x1 Idle: node is neither receiver nor transmitter 0x1 B_0x2 Receiver: node is operating as receiver 0x2 B_0x3 Transmitter: node is operating as transmitter 0x3 BO BO 7 1 read-write B_0x0 The FDCAN is not Bus_Off 0x0 B_0x1 The FDCAN is in Bus_Off state 0x1 DLEC DLEC 8 3 write-only EP EP 5 1 read-write B_0x0 The FDCAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 0x0 B_0x1 The FDCAN is in the Error_Passive state 0x1 EW EW 6 1 read-write B_0x0 Both error counters are below the Error_Warning limit of 96 0x0 B_0x1 At least one of error counter has reached the Error_Warning limit of 96 0x1 LEC LEC 0 3 read-write B_0x0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 0x0 B_0x1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 B_0x2 Form Error: A fixed format part of a received frame has the wrong format. 0x2 B_0x3 AckError: The message transmitted by the FDCAN was not acknowledged by another node. 0x3 B_0x4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1 ), but the monitored bus value was dominant. 0x4 B_0x5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0 ), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 0x5 B_0x6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 0x6 B_0x7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7 . When the LEC shows the value 7 , no CAN bus event was detected since the last CPU read access to the Protocol Status Register. 0x7 PXE PXE 14 1 read-write B_0x0 No protocol exception event occurred since last read access 0x0 B_0x1 Protocol exception event occurred 0x1 RBRS RBRS 12 1 read-write B_0x0 Last received FDCAN message did not ha ve its BRS flag set 0x0 B_0x1 Last received FDCAN message had its BRS flag set 0x1 REDL REDL 13 1 read-write B_0x0 Since this bit was reset by the CPU, no FDCAN message has been received 0x0 B_0x1 Message in FDCAN format with EDL flag set has been received 0x1 RESI RESI 11 1 read-write B_0x0 Last received FDCAN message did not have its ESI flag set 0x0 B_0x1 Last received FDCAN message had its ESI flag set 0x1 TDCV TDCV 16 7 read-write FDCAN_RWD FDCAN_RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only FDCAN_RXBC FDCAN_RXBC FDCAN Rx buffer configuration register 0xAC 32 read-write n 0x0 0x0 RBSA RBSA 2 14 read-write FDCAN_RXESC FDCAN_RXESC Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only. 0xBC 32 read-only n 0x0 0x0 F0DS F0DS 0 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 F1DS F1DS 4 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 RBDS RBDS 8 3 read-only FDCAN_RXF0A FDCAN_RXF0A CAN Rx FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 0x0 F0AI F0AI 0 6 read-write FDCAN_RXF0C FDCAN_RXF0C FDCAN Rx FIFO Configuration Register 0xA0 32 read-write n 0x0 0x0 F0OM F0OM 31 1 read-write F0S F0S 16 7 read-write F0SA F0SA 2 14 read-write F0WM F0WM 24 7 read-write FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 Status Register 0xA4 32 read-write n 0x0 0x0 F0F F0F 24 1 read-write B_0x0 Rx FIFO 0 not full 0x0 B_0x1 Rx FIFO 0 full 0x1 F0FL F0FL 0 7 read-write F0GI F0GI 8 6 read-write F0PI F0PI 16 6 read-write RF0L RF0L 25 1 read-write B_0x0 No Rx FIFO 0 message lost 0x0 B_0x1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero 0x1 FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 0x0 F1AI F1AI 0 6 read-write FDCAN_RXF1C FDCAN_RXF1C FDCAN Rx FIFO 1 configuration register 0xB0 32 read-write n 0x0 0x0 F1OM F1OM 31 1 read-write F1S F1S 16 7 read-write F1SA F1SA 2 14 read-write F1WM F1WM 24 7 read-write FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 Status Register 0xB4 32 read-only n 0x0 0x0 DMS DMS 30 2 read-only F1F F1F 24 1 read-only B_0x0 Rx FIFO 1 not full 0x0 B_0x1 Rx FIFO 1 full 0x1 F1FL F1FL 0 7 read-only F1GI F1GI 8 6 read-only F1PI F1PI 16 6 read-only RF1L RF1L 25 1 read-only B_0x0 No Rx FIFO 1 message lost 0x0 B_0x1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. 0x1 FDCAN_SIDFC FDCAN_SIDFC Settings for 11-bit standard Message ID filtering.The Standard ID Filter Configuration controls the filter path for standard messages as described in Figure706: Standard Message ID filter path. 0x84 32 read-write n 0x0 0x0 FLSSA FLSSA 2 14 read-write LSS LSS 16 8 read-write B_0x0 No standard Message ID filter 0x0 FDCAN_TDCR FDCAN_TDCR FDCAN Transmitter Delay Compensation Register 0x48 32 read-only n 0x0 0x0 TDCF TDCF 0 7 read-only TDCO TDCO 8 7 read-only FDCAN_TEST FDCAN_TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 read-write B_0x0 Reset value, Loop Back mode is disabled 0x0 B_0x1 Loop Back mode is enabled (see Test modes) 0x1 RX RX 7 1 read-write B_0x0 The CAN bus is dominant (FDCANx_RX = 0 ) 0x0 B_0x1 The CAN bus is recessive (FDCANx_RX = 1 ) 0x1 TX TX 5 2 read-write B_0x0 Reset value , FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time 0x0 B_0x1 Sample point can be monitored at pin FDCANx_TX 0x1 B_0x2 Dominant ( 0 ) level at pin FDCANx_TX 0x2 B_0x3 Recessive ( 1 ) at pin FDCANx_TX 0x3 FDCAN_TOCC FDCAN_TOCC FDCAN Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 read-write B_0x0 Timeout Counter disabled 0x0 B_0x1 Timeout Counter enabled 0x1 TOP TOP 16 16 read-write TOS TOS 1 2 write-only B_0x0 Continuous operation 0x0 B_0x1 Timeout controlled by Tx Event FIFO 0x1 B_0x2 Timeout controlled by Rx FIFO 0 0x2 B_0x3 Timeout controlled by Rx FIFO 1 0x3 FDCAN_TOCV FDCAN_TOCV FDCAN Timeout Counter Value Register 0x2C 32 read-only n 0x0 0x0 TOC TOC 0 16 read-only FDCAN_TSCC FDCAN_TSCC FDCAN Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 read-write TSS TSS 0 2 read-write B_0x0 Timestamp counter value always 0x0000 0x0 B_0x1 Timestamp counter value incremented according to TCP 0x1 B_0x2 External timestamp counter from TIM3 value used (tim3_cnt[0:15]) 0x2 B_0x3 Same as 00 . 0x3 FDCAN_TSCV FDCAN_TSCV FDCAN Timestamp Counter Value Register 0x24 32 read-only n 0x0 0x0 TSC TSC 0 16 read-only FDCAN_TTCPT FDCAN_TTCPT FDCAN TT Capture Time Register 0x13C 32 read-only n 0x0 0x0 CT Cycle Count Value 0 6 SWV Stop Watch Value 16 16 FDCAN_TTCSM FDCAN_TTCSM FDCAN TT Cycle Sync Mark Register 0x140 32 read-only n 0x0 0x0 CSM Cycle Sync Mark 0 16 FDCAN_TTCTC FDCAN_TTCTC FDCAN TT Cycle Time and Count Register 0x138 32 read-only n 0x0 0x0 CC Cycle Count 16 6 CT Cycle Time 0 16 FDCAN_TTGTP FDCAN_TTGTP FDCAN TT global time preset register 0x118 32 read-write n 0x0 0x0 CTP CTP 16 16 read-write TP TP 0 16 read-write FDCAN_TTIE FDCAN_TTIE FDCAN TT interrupt enable register 0x124 32 read-write n 0x0 0x0 AWE AWE 17 1 read-write CERE CERE 18 1 read-write CSME CSME 2 1 read-write ELCE ELCE 14 1 read-write GTDE GTDE 8 1 read-write GTEE GTEE 9 1 read-write GTWE GTWE 7 1 read-write IWTGE IWTGE 15 1 read-write RTMIE RTMIE 4 1 read-write SBCE SBCE 0 1 read-write SE1E SE1E 12 1 read-write SE2E SE2E 13 1 read-write SMCE SMCE 1 1 read-write SOGE SOGE 3 1 read-write SWEE SWEE 6 1 read-write TTMIE TTMIE 5 1 read-write TXOE TXOE 11 1 read-write TXUE TXUE 10 1 read-write WTE WTE 16 1 read-write FDCAN_TTILS FDCAN_TTILS FDCAN TT interrupt line select register 0x128 32 read-write n 0x0 0x0 AWL AWL 17 1 read-write CERL CERL 18 1 read-write CSML CSML 2 1 read-write ELCL ELCL 14 1 read-write GTDL GTDL 8 1 read-write GTEL GTEL 9 1 read-write GTWL GTWL 7 1 read-write IWTGL IWTGL 15 1 read-write RTMIL RTMIL 4 1 read-write SBCL SBCL 0 1 read-write SE1L SE1L 12 1 read-write SE2L SE2L 13 1 read-write SMCL SMCL 1 1 read-write SOGL SOGL 3 1 read-write SWEL SWEL 6 1 read-write TTMIL TTMIL 5 1 read-write TXOL TXOL 11 1 read-write TXUL TXUL 10 1 read-write WTL WTL 16 1 read-write FDCAN_TTIR FDCAN_TTIR FDCAN TT Interrupt register 0x120 32 read-write n 0x0 0x0 AW AW 17 1 read-write CER CER 18 1 read-write CSM CSM 2 1 read-write ELC ELC 14 1 read-write GTD GTD 8 1 read-write GTE GTE 9 1 read-write GTW GTW 7 1 read-write IWTG IWTG 15 1 read-write RTMI RTMI 4 1 read-write SBC SBC 0 1 read-write SE1 SE1 12 1 read-write SE2 SE2 13 1 read-write SMC SMC 1 1 read-write SOG SOG 3 1 read-write SWE SWE 6 1 read-write TTMI TTMI 5 1 read-write TXO TXO 11 1 read-write TXU TXU 10 1 read-write WT WT 16 1 read-write FDCAN_TTLGT FDCAN_TTLGT FDCAN TT Local and Global Time Register 0x134 32 read-only n 0x0 0x0 GT Global Time 16 16 LT Local Time 0 16 FDCAN_TTMLM FDCAN_TTMLM FDCAN TT matrix limits register 0x10C 32 read-write n 0x0 0x0 CCM CCM 0 6 read-write CSS CSS 6 2 read-write ENTT ENTT 16 12 read-write TXEW TXEW 8 4 read-write FDCAN_TTOCF FDCAN_TTOCF FDCAN TT operation configuration register 0x108 32 read-write n 0x0 0x0 AWL AWL 16 8 read-write ECC ECC 25 1 read-write EECS EECS 15 1 read-write EGTF EGTF 24 1 read-write EVTP EVTP 26 1 read-write GEN GEN 3 1 read-write IRTO IRTO 8 7 read-write LDSDL LDSDL 5 3 read-write OM OM 0 2 read-write TM TM 4 1 read-write FDCAN_TTOCN FDCAN_TTOCN FDCAN TT operation control register 0x114 32 read-write n 0x0 0x0 ECS ECS 1 1 read-write ESCN ESCN 13 1 read-write FGP FGP 10 1 read-write GCS GCS 9 1 read-write LCKC LCKC 15 1 read-write NIG NIG 12 1 read-write RTIE RTIE 5 1 read-write SGT SGT 0 1 read-write SWP SWP 2 1 read-write SWS SWS 3 2 read-write TMC TMC 6 2 read-write TMG TMG 11 1 read-write TTIE TTIE 8 1 read-write FDCAN_TTOST FDCAN_TTOST FDCAN TT Operation Status Register 0x12C 32 read-write n 0x0 0x0 AWE Application Watchdog Event 29 1 EL Error Level 0 2 GFI Gap Finished Indicator. 23 1 GSI Gap Started Indicator. 27 1 GTP Quality of Global Time Phase 6 1 MS Master State. 2 2 QCS Quality of Clock Speed 7 1 RTO Reference Trigger Offset 8 8 SPL Schedule Phase Lock 31 1 SYS Synchronization State 4 2 TMP Time Master Priority 24 3 WECS Wait for External Clock Synchronization 30 1 WFE Wait for Event 28 1 WGTD Wait for Global Time Discontinuity 22 1 FDCAN_TTRMC FDCAN_TTRMC FDCAN TT reference message configuration register 0x104 32 read-write n 0x0 0x0 RID RID 0 29 read-write RMPS RMPS 31 1 read-write XTD XTD 30 1 read-write FDCAN_TTTMC FDCAN_TTTMC FDCAN TT trigger memory configuration register 0x100 32 read-write n 0x0 0x0 TME TME 16 7 read-write TMSA TMSA 2 14 read-write FDCAN_TTTMK FDCAN_TTTMK FDCAN TT time mark register 0x11C 32 read-write n 0x0 0x0 LCKM LCKM 31 1 read-only TICC TICC 16 7 read-write TM TM 0 16 read-write FDCAN_TTTS FDCAN_TTTS FDCAN TT Trigger Select Register 0x300 32 read-write n 0x0 0x0 EVTSEL Event trigger input selection 4 2 SWTDEL Stop watch trigger input selection 0 2 FDCAN_TURCF FDCAN_TURCF FDCAN TUR configuration register 0x110 32 read-write n 0x0 0x0 DC DC 16 15 read-write ELT ELT 31 1 read-write NCL NCL 0 16 read-write FDCAN_TURNA FDCAN_TURNA FDCAN TUR Numerator Actual Register 0x130 32 read-only n 0x0 0x0 NAV Numerator Actual Value 0 18 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx Buffer Add Request Register 0xD0 32 read-write n 0x0 0x0 AR AR 0 32 read-write B_0x0 No transmission request added 0x0 B_0x1 Transmission requested added. 0x1 FDCAN_TXBC FDCAN_TXBC FDCAN Tx Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 0x0 CF CF 0 32 read-only B_0x0 No transmit buffer cancellation 0x0 B_0x1 Transmit buffer cancellation finished 0x1 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 0x0 CFIE CFIE 0 32 read-write B_0x0 Cancellation finished interrupt disabled 0x0 B_0x1 Cancellation finished interrupt enabled 0x1 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 0x0 CR CR 0 32 read-write B_0x0 No cancellation pending 0x0 B_0x1 Cancellation pending 0x1 FDCAN_TXBRP FDCAN_TXBRP FDCAN Tx Buffer Request Pending Register 0xCC 32 read-only n 0x0 0x0 TRP TRP 0 32 read-only B_0x0 No transmission request pending 0x0 B_0x1 Transmission request pending 0x1 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 TIE TIE 0 32 read-write B_0x0 Transmission interrupt disabled 0x0 B_0x1 Transmission interrupt enable 0x1 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 0x0 TO TO 0 32 read-only B_0x0 No transmission occurred 0x0 B_0x1 Transmission occurred 0x1 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 read-write FDCAN_TXEFC FDCAN_TXEFC FDCAN Tx event FIFO configuration register 0xF0 32 read-write n 0x0 0x0 EFS EFS 16 6 EFSA EFSA 2 14 EFWM EFWM 24 6 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx Event FIFO Status Register 0xF4 32 read-only n 0x0 0x0 EFF EFF 24 1 read-only B_0x0 Tx Event FIFO not full 0x0 B_0x1 Tx Event FIFO full 0x1 EFFL EFFL 0 6 read-only EFGI EFGI 8 5 read-only EFPI EFPI 16 5 read-only TEFL TEFL 25 1 read-only FDCAN_TXESC FDCAN_TXESC Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes greater than 8 bytes are intended for CAN FD operation only. 0xC8 32 read-only n 0x0 0x0 TBDS TBDS 0 3 read-only B_0x0 8 byte data field 0x0 B_0x1 12 byte data field 0x1 B_0x2 16 byte data field 0x2 B_0x3 20 byte data field 0x3 B_0x4 24 byte data field 0x4 B_0x5 32 byte data field 0x5 B_0x6 48 byte data field 0x6 B_0x7 64 byte data field 0x7 FDCAN_TXFQS FDCAN_TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 read-only TFGI TFGI 8 5 read-only TFQF TFQF 21 1 read-only TFQPI TFQPI 16 5 read-only FDCAN_XIDAM FDCAN_XIDAM FDCAN Extended ID and Mask Register 0x90 32 read-write n 0x0 0x0 EIDM EIDM 0 29 read-write FDCAN_XIDFC FDCAN_XIDFC Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages as described in Figure707: Extended Message ID filter path. 0x88 32 read-write n 0x0 0x0 FLESA FLESA 2 14 read-write LSE LSE 16 8 read-write B_0x0 No standard Message ID filter 0x0 FMC FMC FMC 0x0 0x0 0x1000 registers n FMC FMC global Interrupt 48 BCHDSR0 FMC_BCHDSR0 FMC BCH Decoder Status register 0 0x27C 32 read-only n 0x0 0x0 DEF DEF 1 1 DEN DEN 4 4 DUE DUE 0 1 BCHDSR1 FMC_BCHDSR1 FMC BCH Decoder Status register 0x280 32 read-only n 0x0 0x0 EBP0_13 EBP0_13 0 13 EBP16_28 EBP16_28 13 1 BCHDSR2 FMC_BCHDSR2 FMC BCH Decoder Status register 0x284 32 read-only n 0x0 0x0 EBP0_13 EBP0_13 0 13 EBP16_28 EBP16_28 13 1 BCHDSR3 FMC_BCHDSR3 FMC BCH Decoder Status register 0x288 32 read-only n 0x0 0x0 EBP0_13 EBP0_13 0 13 EBP16_28 EBP16_28 13 1 BCHDSR4 FMC_BCHDSR4 FMC BCH Decoder Status register 0x28C 32 read-only n 0x0 0x0 EBP0_13 EBP0_13 0 13 EBP16_28 EBP16_28 13 1 BCHICR FMC_BCHICR FMC BCH Interrupt Clear Register 0x258 32 write-only n 0x0 0x0 CDEFF CDEFF 2 1 CDERF CDERF 1 1 CDSRF CDSRF 3 1 CDUEF CDUEF 0 1 CEPBRF CEPBRF 4 1 BCHIER FMC_BCHIER FMC BCH Interrupt Enable Register 0x250 32 read-write n 0x0 0x0 DEFIE DEFIE 2 1 DERIE DERIE 1 1 DSRIE DSRIE 3 1 DUEIE DUEIE 0 1 EPBRIE EPBRIE 4 1 BCHISR FMC_BCHISR FMC BCH Interrupt and Status Register 0x254 32 read-only n 0x0 0x0 DEFF DEFF 2 1 DERF DERF 1 1 DSRF DSRF 3 1 DUEF DUEF 0 1 EPBRF EPBRF 4 1 BCHPBR1 FMC_BCHPBR1 FMC BCH Parity Bits Register 1 0x260 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR2 FMC_BCHPBR2 FMC BCH Parity Bits Register 2 0x264 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR3 FMC_BCHPBR3 FMC BCH Parity Bits Register 3 0x268 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCHPBR4 FMC_BCHPBR4 FMC BCH Parity Bits Register 4 0x26C 32 read-only n 0x0 0x0 BCHPB BCHPB 0 32 BCR1 FMC_BCR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x0 32 read-write n 0x0 0x0 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FMCEN FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 NBLSET NBLSET 22 2 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 BCR2 FMC_BCR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x8 32 read-write n 0x0 0x0 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FMCEN FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 NBLSET NBLSET 22 2 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 BCR3 FMC_BCR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x10 32 read-write n 0x0 0x0 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FMCEN FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 NBLSET NBLSET 22 2 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 BCR4 FMC_BCR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 0x18 32 read-write n 0x0 0x0 ASYNCWAIT Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol. 15 1 BURSTEN Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode: 8 1 CBURSTRW Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. 19 1 CCLKEN Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.) 20 1 CPSIZE CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved. 16 3 EXTMOD Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). 14 1 FACCEN Flash access enable This bit enables NOR Flash memory access operations. 6 1 FMCEN FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. 31 1 MBKEN Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus. 0 1 MTYP Memory type These bits define the type of external memory attached to the corresponding memory bank: 2 2 MUXEN Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories: 1 1 MWID Memory data bus width Defines the external memory device width, valid for all type of memories. 4 2 NBLSET NBLSET 22 2 WAITCFG Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 11 1 WAITEN Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode. 13 1 WAITPOL Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode: 9 1 WREN Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC: 12 1 BTR1 FMC_BTR1 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x4 32 read-write n 0x0 0x0 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 BTR2 FMC_BTR2 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0xC 32 read-write n 0x0 0x0 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 1. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 BTR3 FMC_BTR3 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x14 32 read-write n 0x0 0x0 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 BTR4 FMC_BTR4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers). 0x1C 32 read-write n 0x0 0x0 ACCMOD Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. 4 4 ADDSET Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ... 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula) 20 4 DATAST Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care. 8 8 DATLAT Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles 24 4 BWTR1 FMC_BWTR1 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x104 32 read-write n 0x0 0x0 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BWTR2 FMC_BWTR2 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x10C 32 read-write n 0x0 0x0 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BWTR3 FMC_BWTR3 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x114 32 read-write n 0x0 0x0 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 BWTR4 FMC_BWTR4 This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access. 0x11C 32 read-write n 0x0 0x0 ACCMOD Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 28 2 ADDHLD Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 4 4 ADDSET Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 4 BUSTURN Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ... 16 4 DATAHLD DATAHLD 30 2 DATAST Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 8 8 CSQAR1 FMC_CSQAR1 FMC NAND Command Sequencer Address Register 1 0x210 32 read-write n 0x0 0x0 ADDC1 ADDC1 0 8 ADDC2 ADDC2 8 8 ADDC3 ADDC3 16 8 ADDC4 ADDC4 24 8 CSQAR2 FMC_CSQAR2 FMC NAND Command Sequencer Address Register 2 0x214 32 read-write n 0x0 0x0 ADDC5 ADDC5 0 8 SAO SAO 16 16 CSQCFGR1 FMC_CSQCFGR1 FMC NAND Command Sequencer Configuration Register 1 0x204 32 read-write n 0x0 0x0 ACYNBR ACYNBR 4 3 CMD1 CMD1 8 8 CMD1T CMD1T 24 1 CMD2 CMD2 16 8 CMD2EN CMD2EN 1 1 CMD2T CMD2T 25 1 DMADEN DMADEN 2 1 CSQCFGR2 FMC_CSQCFGR2 FMC NAND Command Sequencer Configuration Register 2 0x208 32 read-write n 0x0 0x0 DMASEN DMASEN 2 1 RCMD1 RCMD1 8 8 RCMD1T RCMD1T 24 1 RCMD2 RCMD2 16 8 RCMD2EN RCMD2EN 1 1 RCMD2T RCMD2T 25 1 SQSDTEN SQSDTEN 0 1 CSQCFGR3 FMC_CSQCFGR3 FMC NAND Command Sequencer Configuration Register 3 0x20C 32 read-write n 0x0 0x0 AC1T AC1T 16 1 AC2T AC2T 17 1 AC3T AC3T 18 1 AC4T AC4T 19 1 AC5T AC5T 20 1 RAC1T RAC1T 22 1 RAC2T RAC2T 23 1 SDT SDT 21 1 SNBR SNBR 8 6 CSQCR FMC_CSQCR FMC NAND Command Sequencer Control Register 0x200 32 write-only n 0x0 0x0 CSQSTART CSQSTART 0 1 CSQEMSR FMC_CSQEMSR FMC NAND Command Sequencer Interrupt Status Register 0x230 32 read-only n 0x0 0x0 SEM SEM 0 16 CSQICR FMC_CSQICR FMC NAND Command Sequencer Interrupt Status Register 0x228 32 write-only n 0x0 0x0 CCMDTCF CCMDTCF 4 1 CSCF CSCF 1 1 CSEF CSEF 2 1 CSUEF CSUEF 3 1 CTCF CTCF 0 1 CSQIER FMC_CSQIER FMC NAND Command Sequencer Interrupt Enable Register 0x220 32 read-write n 0x0 0x0 CMDTCIE CMDTCIE 4 1 SCIE SCIE 1 1 SEIE SEIE 2 1 SUEIE SUEIE 3 1 TCIE TCIE 0 1 CSQISR FMC_CSQISR FMC NAND Command Sequencer Interrupt Status Register 0x224 32 read-write n 0x0 0x0 CMDTCF CMDTCF 4 1 SCF SCF 1 1 SEF SEF 2 1 SUEF SUEF 3 1 TCF TCF 0 1 HECCR FMC_HECCR FMC Hamming code ECC result register 0x94 32 read-only n 0x0 0x0 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 HPR FMC_HPR FMC Hamming parity result registers 0x90 32 read-only n 0x0 0x0 HPR HPR 0 32 HWCFGR1 FMC_HWCFGR1 FMC Hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 ID_SIZE ID_SIZE 12 4 NAND_ECC NAND_ECC 4 1 NAND_SEL NAND_SEL 0 1 RA_LN2DPTH RA_LN2DPTH 28 4 SDRAM_SEL SDRAM_SEL 8 1 WA_LN2DPTH WA_LN2DPTH 16 4 WD_LN2DPTH WD_LN2DPTH 20 4 WR_LN2DPTH WR_LN2DPTH 24 4 HWCFGR2 FMC_HWCFGR2 FMC Hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 NAND_BASE NAND_BASE 12 4 NOR_BASE NOR_BASE 4 1 RD_LN2DPTH RD_LN2DPTH 0 4 SDRAM1_BASE SDRAM1_BASE 16 4 SDRAM2_BASE SDRAM2_BASE 20 4 SDRAM_RBASE SDRAM_RBASE 8 1 IDR FMC_IDR FMC Identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 PATT FMC_PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 32 read-write n 0x0 0x0 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 PCR FMC_PCR NAND Flash control registers 0x80 32 read-write n 0x0 0x0 BCHECC BCHECC 24 1 ECCALG ECCALG 8 1 ECCEN ECC computation logic enable bit 6 1 ECCSS ECCSS 17 3 PBKEN NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus 2 1 PWAITEN Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank: 1 1 PWID Data bus width. These bits define the external memory device width. 4 2 TAR ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 13 4 TCLR CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space. 9 4 WEN WEN 25 1 PCSCNTR FMC_PCSCNTR PSRAM Chip Select Counter Register 0x20 32 read-write n 0x0 0x0 CNTB1EN CNTB1EN 16 1 CNTB2EN CNTB2EN 17 1 CNTB3EN CNTB3EN 18 1 CNTB4EN CNTB4EN 19 1 CSCOUNT CSCOUNT 0 16 PMEM FMC_PMEM The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access. 0x88 32 read-write n 0x0 0x0 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 SIDR FMC_SIDR FMC Size Identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SR FMC_SR This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty. 0x84 32 read-write n 0x0 0x0 ISOST ISOST 0 2 read-only NWRF NWRF 6 1 read-only PEF PEF 4 1 read-only VERR FMC_VERR FMC Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 GICC GICC GICC 0x0 0x0 0x2000 registers n ABPR ABPR GICC aliased binary point register 0x1C 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 AEOIR AEOIR GICC aliased end of interrupt register 0x24 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 AHPPIR AHPPIR GICC aliased highest priority pending interrupt register 0x28 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 AIAR AIAR GICC aliased interrupt acknowledge register 0x20 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 APR0 APR0 GICC active priority register 0xD0 32 read-write n 0x0 0x0 APR0 APR0 0 32 BPR BPR GICC binary point register 0x8 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 BPRNS BPRNS GICC binary point (non-secure access) register BPR 0x8 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 CTLR CTLR Control register 0x0 32 read-write n 0x0 0x0 ACKCTL Acknowledge control 2 1 CBPR BPR control 4 1 ENABLEGRP0 Enable group 0 interrupts 0 1 ENABLEGRP1 Enable group 1 interrupts 1 1 EOIMODENS Alias of EOIMODENS from the non-secure copy of this register 10 1 EOIMODES EOI mode for secure accesses 9 1 FIQBYPDISGRP0 FIQ bypass disable for group 0 interrupts 5 1 FIQBYPDISGRP1 Alias of FIQBYPDISGRP1 from the non-secure copy of this register. 7 1 FIQEN FIQ enable for group 0 interrupts 3 1 IRQBYPDISGRP0 IRQ bypass disable for group 0 interrupts 6 1 IRQBYPDISGRP1 Alias of IRQBYPDISGRP1 from the non-secure copy of this register 8 1 CTLRNS CTLRNS GICC control (non-secure access) register CTLR 0x0 32 read-write n 0x0 0x0 ENABLEGRP1 Enable group1 interrupts 0 1 EOIMODENS EOI mode for non- secure accesses 9 1 FIQBYPDISGRP1 FIQ bypass disable for group 1 interrupts 5 1 IRQBYPDISGRP1 IRQ bypass for group 1 interrupts 6 1 DIR DIR GICC deactivate interrupt register 0x1000 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID INTERRUPT_ID 0 10 EOIR EOIR GICC end of interrupt register 0x10 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 HPPIR HPPIR GICC highest priority pending interrupt register 0x18 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 IAR IAR GICC interrupt acknowledge register 0xC 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID The interrupt ID 0 10 IIDR IIDR GICC interface identification register 0xFC 32 read-only n 0x0 0x0 ARCH ARCH 16 4 IMPLEMENTER IMPLEMENTER 0 12 PRODUCTID PRODUCTID 20 12 REVISION REVISION 12 4 NSAPR0 NSAPR0 GICC non-secure active priority register 0xE0 32 read-write n 0x0 0x0 NSAPR0 NSAPR0 0 32 PMR PMR GICC input priority mask register 0x4 32 read-write n 0x0 0x0 PRIORITY priority mask level for the CPU interface 3 5 RPR RPR GICC running priority register 0x14 32 write-only n 0x0 0x0 PRIORITY current running priority on the CPU interface 3 5 GICD GICD GICD 0x0 0x0 0x1000 registers n CIDR0 CIDR0 GICD component ID0 register 0xFF0 32 read-only n 0x0 0x0 CIDR0 component ID0 0 32 CIDR1 CIDR1 GICD component ID1 register 0xFF4 32 read-only n 0x0 0x0 CIDR1 component ID1 0 32 CIDR2 CIDR2 GICD component ID2 register 0xFF8 32 read-only n 0x0 0x0 CIDR2 component ID2 0 32 CIDR3 CIDR3 GICD component ID3 register 0xFFC 32 read-only n 0x0 0x0 CIDR3 component ID3 0 32 CPENDSGIR0 CPENDSGIR0 GICD SGI clear-pending registers 0xF10 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 clear-pending state for SGI 0 2 SGI_CLEAR_PENDING1 clear-pending state for SGI 8 2 SGI_CLEAR_PENDING2 clear-pending state for SGI 16 2 SGI_CLEAR_PENDING3 clear-pending state for SGI 24 2 CPENDSGIR1 CPENDSGIR1 GICD SGI clear-pending registers 0xF14 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 clear-pending state for SGI 0 2 SGI_CLEAR_PENDING1 clear-pending state for SGI 8 2 SGI_CLEAR_PENDING2 clear-pending state for SGI 16 2 SGI_CLEAR_PENDING3 clear-pending state for SGI 24 2 CPENDSGIR2 CPENDSGIR2 GICD SGI clear-pending registers 0xF18 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 clear-pending state for SGI 0 2 SGI_CLEAR_PENDING1 clear-pending state for SGI 8 2 SGI_CLEAR_PENDING2 clear-pending state for SGI 16 2 SGI_CLEAR_PENDING3 clear-pending state for SGI 24 2 CPENDSGIR3 CPENDSGIR3 GICD SGI clear-pending registers 0xF1C 32 read-write n 0x0 0x0 SGI_CLEAR_PENDING0 clear-pending state for SGI 0 2 SGI_CLEAR_PENDING1 clear-pending state for SGI 8 2 SGI_CLEAR_PENDING2 clear-pending state for SGI 16 2 SGI_CLEAR_PENDING3 clear-pending state for SGI 24 2 CTLR GICD_CTLR GICD control register 0x0 32 read-write n 0x0 0x0 ENABLEGRP0 enable group 0 interrupts 0 1 read-write ENABLEGRP1 enable group 1 interrupts 1 1 CTLRNS GICD_CTLRNS GICD control (non-secure access) register GICD_CTLR 0x0 32 read-write n 0x0 0x0 ENABLE Global enable for forwarding pending group 1 interrupts from the GICD to the CPU interfaces 0 1 ICACTIVER0 ICACTIVER0 GICD interrupt clear-active registers 0x380 32 read-write n 0x0 0x0 ICACTIVER0 interrupt clear-active 0 32 ICACTIVER1 ICACTIVER1 GICD interrupt clear-active registers 0x384 32 read-write n 0x0 0x0 ICACTIVER1 interrupt clear-active 0 32 ICACTIVER2 ICACTIVER2 GICD interrupt clear-active registers 0x388 32 read-write n 0x0 0x0 ICACTIVER2 interrupt clear-active 0 32 ICACTIVER3 ICACTIVER3 GICD interrupt clear-active registers 0x38C 32 read-write n 0x0 0x0 ICACTIVER3 interrupt clear-active 0 32 ICACTIVER4 ICACTIVER4 GICD interrupt clear-active registers 0x390 32 read-write n 0x0 0x0 ICACTIVER4 interrupt clear-active 0 32 ICACTIVER5 ICACTIVER5 GICD interrupt clear-active registers 0x394 32 read-write n 0x0 0x0 ICACTIVER5 interrupt clear-active 0 32 ICACTIVER6 ICACTIVER6 GICD interrupt clear-active registers 0x398 32 read-write n 0x0 0x0 ICACTIVER6 interrupt clear-active 0 32 ICACTIVER7 ICACTIVER7 GICD interrupt clear-active registers 0x39C 32 read-write n 0x0 0x0 ICACTIVER7 interrupt clear-active 0 32 ICACTIVER8 ICACTIVER8 GICD interrupt clear-active registers 0x3A0 32 read-write n 0x0 0x0 ICACTIVER8 interrupt clear-active 0 32 ICENABLER0 ICENABLER0 GICD interrupt clear-enable register 0x180 32 read-write n 0x0 0x0 ICENABLER0 interrupt clear-enable 0 0 32 ICENABLER1 ICENABLER1 GICD interrupt clear-enable register 0x184 32 read-write n 0x0 0x0 ICENABLER1 interrupt clear-enable 0 0 32 ICENABLER2 ICENABLER2 GICD interrupt clear-enable register 0x188 32 read-write n 0x0 0x0 ICENABLER2 interrupt clear-enable 0 0 32 ICENABLER3 ICENABLER3 GICD interrupt clear-enable register 0x18C 32 read-write n 0x0 0x0 ICENABLER3 interrupt clear-enable 0 0 32 ICENABLER4 ICENABLER4 GICD interrupt clear-enable register 0x190 32 read-write n 0x0 0x0 ICENABLER4 interrupt clear-enable 0 0 32 ICENABLER5 ICENABLER5 GICD interrupt clear-enable register 0x194 32 read-write n 0x0 0x0 ICENABLER5 interrupt clear-enable 0 0 32 ICENABLER6 ICENABLER6 GICD interrupt clear-enable register 0x198 32 read-write n 0x0 0x0 ICENABLER6 interrupt clear-enable 0 0 32 ICENABLER7 ICENABLER7 GICD interrupt clear-enable register 0x19C 32 read-write n 0x0 0x0 ICENABLER7 interrupt clear-enable 0 0 32 ICENABLER8 ICENABLER8 GICD interrupt clear-enable register 0x1A0 32 read-write n 0x0 0x0 ICENABLER8 interrupt clear-enable 0 0 32 ICFGR0 ICFGR0 GICD interrupt configuration register 0xC00 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR1 ICFGR1 GICD interrupt configuration register 0xC04 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR10 ICFGR10 GICD interrupt configuration register 0xC28 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR11 ICFGR11 GICD interrupt configuration register 0xC2C 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR12 ICFGR12 GICD interrupt configuration register 0xC30 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR13 ICFGR13 GICD interrupt configuration register 0xC34 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR14 ICFGR14 GICD interrupt configuration register 0xC38 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR15 ICFGR15 GICD interrupt configuration register 0xC3C 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR16 ICFGR16 GICD interrupt configuration register 0xC40 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR17 ICFGR17 GICD interrupt configuration register 0xC44 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR2 ICFGR2 GICD interrupt configuration register 0xC08 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR3 ICFGR3 GICD interrupt configuration register 0xC0C 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR4 ICFGR4 GICD interrupt configuration register 0xC10 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR5 ICFGR5 GICD interrupt configuration register 0xC14 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR6 ICFGR6 GICD interrupt configuration register 0xC18 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR7 ICFGR7 GICD interrupt configuration register 0xC1C 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR8 ICFGR8 GICD interrupt configuration register 0xC20 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICFGR9 ICFGR9 GICD interrupt configuration register 0xC24 32 read-write n 0x0 0x0 INT_CONFIG0 interrupt config for interrupt 0 2 INT_CONFIG1 interrupt config for interrupt 2 2 INT_CONFIG10 interrupt config for interrupt 20 2 INT_CONFIG11 interrupt config for interrupt 22 2 INT_CONFIG12 interrupt config for interrupt 24 2 INT_CONFIG13 interrupt config for interrupt 26 2 INT_CONFIG14 interrupt config for interrupt 28 2 INT_CONFIG15 interrupt config for interrupt 30 2 INT_CONFIG2 interrupt config for interrupt 4 2 INT_CONFIG3 interrupt config for interrupt 6 2 INT_CONFIG4 interrupt config for interrupt 8 2 INT_CONFIG5 interrupt config for interrupt 10 2 INT_CONFIG6 interrupt config for interrupt 12 2 INT_CONFIG7 interrupt config for interrupt 14 2 INT_CONFIG8 interrupt config for interrupt 16 2 INT_CONFIG9 interrupt config for interrupt 18 2 ICPENDR0 ICPENDR0 GICD interrupt clear-pending registers 0x280 32 read-write n 0x0 0x0 ICPENDR0 interrupt clear-pending 0 32 ICPENDR1 ICPENDR1 GICD interrupt clear-pending registers 0x284 32 read-write n 0x0 0x0 ICPENDR1 interrupt clear-pending 0 32 ICPENDR2 ICPENDR2 GICD interrupt clear-pending registers 0x288 32 read-write n 0x0 0x0 ICPENDR2 interrupt clear-pending 0 32 ICPENDR3 ICPENDR3 GICD interrupt clear-pending registers 0x28C 32 read-write n 0x0 0x0 ICPENDR3 interrupt clear-pending 0 32 ICPENDR4 ICPENDR4 GICD interrupt clear-pending registers 0x290 32 read-write n 0x0 0x0 ICPENDR4 interrupt clear-pending 0 32 ICPENDR5 ICPENDR5 GICD interrupt clear-pending registers 0x294 32 read-write n 0x0 0x0 ICPENDR5 interrupt clear-pending 0 32 ICPENDR6 ICPENDR6 GICD interrupt clear-pending registers 0x298 32 read-write n 0x0 0x0 ICPENDR6 interrupt clear-pending 0 32 ICPENDR7 ICPENDR7 GICD interrupt clear-pending registers 0x29C 32 read-write n 0x0 0x0 ICPENDR7 interrupt clear-pending 0 32 ICPENDR8 ICPENDR8 GICD interrupt clear-pending registers 0x2A0 32 read-write n 0x0 0x0 ICPENDR8 interrupt clear-pending 0 32 IGROUPR0 GICD_IGROUPR0 GICD interrupt group registers 0x80 32 read-write n 0x0 0x0 IGROUPR0 group of interrupts 0 32 IGROUPR1 GICD_IGROUPR1 GICD interrupt group registers 0x84 32 read-write n 0x0 0x0 IGROUPR1 group of interrupts 0 32 IGROUPR2 GICD_IGROUPR2 GICD interrupt group registers 0x88 32 read-write n 0x0 0x0 IGROUPR2 group of interrupts 0 32 IGROUPR3 GICD_IGROUPR3 GICD interrupt group registers 0x8C 32 read-write n 0x0 0x0 IGROUPR3 group of interrupts 0 32 IGROUPR4 GICD_IGROUPR4 GICD interrupt group registers 0x90 32 read-write n 0x0 0x0 IGROUPR4 group of interrupts 0 32 IGROUPR5 GICD_IGROUPR5 GICD interrupt group registers 0x94 32 read-write n 0x0 0x0 IGROUPR5 group of interrupts 0 32 IGROUPR6 GICD_IGROUPR6 GICD interrupt group registers 0x98 32 read-write n 0x0 0x0 IGROUPR6 group of interrupts 0 32 IGROUPR7 GICD_IGROUPR7 GICD interrupt group registers 0x9C 32 read-write n 0x0 0x0 IGROUPR7 group of interrupts 0 32 IGROUPR8 GICD_IGROUPR8 GICD interrupt group registers 0xA0 32 read-write n 0x0 0x0 IGROUPR8 group of interrupts 0 32 IIDR GICD_IIDR GICD implementer identification register 0x8 32 read-only n 0x0 0x0 IMPLEMENTER GIC implementer 0 12 PRODUCTID product ID of the GIC 24 8 REVISION minor revision number of the GIC 16 4 VARIANT major revision number of the GIC 12 4 IPRIORITYR0 IPRIORITYR0 GICD interrupt priority registers 0x400 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR1 IPRIORITYR1 GICD interrupt priority registers 0x404 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR10 IPRIORITYR10 GICD interrupt priority registers 0x428 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR11 IPRIORITYR11 GICD interrupt priority registers 0x42C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR12 IPRIORITYR12 GICD interrupt priority registers 0x430 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR13 IPRIORITYR13 GICD interrupt priority registers 0x434 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR14 IPRIORITYR14 GICD interrupt priority registers 0x438 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR15 IPRIORITYR15 GICD interrupt priority registers 0x43C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR16 IPRIORITYR16 GICD interrupt priority registers 0x440 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR17 IPRIORITYR17 GICD interrupt priority registers 0x444 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR18 IPRIORITYR18 GICD interrupt priority registers 0x448 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR19 IPRIORITYR19 GICD interrupt priority registers 0x44C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR2 IPRIORITYR2 GICD interrupt priority registers 0x408 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR20 IPRIORITYR20 GICD interrupt priority registers 0x450 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR21 IPRIORITYR21 GICD interrupt priority registers 0x454 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR22 IPRIORITYR22 GICD interrupt priority registers 0x458 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR23 IPRIORITYR23 GICD interrupt priority registers 0x45C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR24 IPRIORITYR24 GICD interrupt priority registers 0x460 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR25 IPRIORITYR25 GICD interrupt priority registers 0x464 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR26 IPRIORITYR26 GICD interrupt priority registers 0x468 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR27 IPRIORITYR27 GICD interrupt priority registers 0x46C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR28 IPRIORITYR28 GICD interrupt priority registers 0x470 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR29 IPRIORITYR29 GICD interrupt priority registers 0x474 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR3 IPRIORITYR3 GICD interrupt priority registers 0x40C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR30 IPRIORITYR30 GICD interrupt priority registers 0x478 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR31 IPRIORITYR31 GICD interrupt priority registers 0x47C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR32 IPRIORITYR32 GICD interrupt priority registers 0x480 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR33 IPRIORITYR33 GICD interrupt priority registers 0x484 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR34 IPRIORITYR34 GICD interrupt priority registers 0x488 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR35 IPRIORITYR35 GICD interrupt priority registers 0x48C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR36 IPRIORITYR36 GICD interrupt priority registers 0x490 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR37 IPRIORITYR37 GICD interrupt priority registers 0x494 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR38 IPRIORITYR38 GICD interrupt priority registers 0x498 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR39 IPRIORITYR39 GICD interrupt priority registers 0x49C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR4 IPRIORITYR4 GICD interrupt priority registers 0x410 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR40 IPRIORITYR40 GICD interrupt priority registers 0x4A0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR41 IPRIORITYR41 GICD interrupt priority registers 0x4A4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR42 IPRIORITYR42 GICD interrupt priority registers 0x4A8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR43 IPRIORITYR43 GICD interrupt priority registers 0x4AC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR44 IPRIORITYR44 GICD interrupt priority registers 0x4B0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR45 IPRIORITYR45 GICD interrupt priority registers 0x4B4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR46 IPRIORITYR46 GICD interrupt priority registers 0x4B8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR47 IPRIORITYR47 GICD interrupt priority registers 0x4BC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR48 IPRIORITYR48 GICD interrupt priority registers 0x4C0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR49 IPRIORITYR49 GICD interrupt priority registers 0x4C4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR5 IPRIORITYR5 GICD interrupt priority registers 0x414 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR50 IPRIORITYR50 GICD interrupt priority registers 0x4C8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR51 IPRIORITYR51 GICD interrupt priority registers 0x4CC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR52 IPRIORITYR52 GICD interrupt priority registers 0x4D0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR53 IPRIORITYR53 GICD interrupt priority registers 0x4D4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR54 IPRIORITYR54 GICD interrupt priority registers 0x4D8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR55 IPRIORITYR55 GICD interrupt priority registers 0x4DC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR56 IPRIORITYR56 GICD interrupt priority registers 0x4E0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR57 IPRIORITYR57 GICD interrupt priority registers 0x4E4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR58 IPRIORITYR58 GICD interrupt priority registers 0x4E8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR59 IPRIORITYR59 GICD interrupt priority registers 0x4EC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR6 IPRIORITYR6 GICD interrupt priority registers 0x418 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR60 IPRIORITYR60 GICD interrupt priority registers 0x4F0 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR61 IPRIORITYR61 GICD interrupt priority registers 0x4F4 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR62 IPRIORITYR62 GICD interrupt priority registers 0x4F8 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR63 IPRIORITYR63 GICD interrupt priority registers 0x4FC 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR64 IPRIORITYR64 GICD interrupt priority registers 0x500 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR65 IPRIORITYR65 GICD interrupt priority registers 0x504 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR66 IPRIORITYR66 GICD interrupt priority registers 0x508 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR67 IPRIORITYR67 GICD interrupt priority registers 0x50C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR68 IPRIORITYR68 GICD interrupt priority registers 0x510 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR69 IPRIORITYR69 GICD interrupt priority registers 0x514 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR7 IPRIORITYR7 GICD interrupt priority registers 0x41C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR70 IPRIORITYR70 GICD interrupt priority registers 0x518 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR71 IPRIORITYR71 GICD interrupt priority registers 0x51C 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR8 IPRIORITYR8 GICD interrupt priority registers 0x420 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 IPRIORITYR9 IPRIORITYR9 GICD interrupt priority registers 0x424 32 read-write n 0x0 0x0 PRIORITY0 priority for interrupt 3 5 PRIORITY1 priority for interrupt 11 5 PRIORITY2 priority for interrupt 19 5 PRIORITY3 priority for interrupt 27 5 ISACTIVER0 ISACTIVER0 GICD interrupt set-active registers 0x12C 32 read-write n 0x0 0x0 ISACTIVER0 interrupt clear-pending 0 32 ISACTIVER1 ISACTIVER1 GICD interrupt set-active registers 0x304 32 read-write n 0x0 0x0 ISACTIVER1 interrupt clear-pending 0 32 ISACTIVER2 ISACTIVER2 GICD interrupt set-active registers 0x308 32 read-write n 0x0 0x0 ISACTIVER2 interrupt clear-pending 0 32 ISACTIVER3 ISACTIVER3 GICD interrupt set-active registers 0x30C 32 read-write n 0x0 0x0 ISACTIVER3 interrupt clear-pending 0 32 ISACTIVER4 ISACTIVER4 GICD interrupt set-active registers 0x310 32 read-write n 0x0 0x0 ISACTIVER4 interrupt clear-pending 0 32 ISACTIVER5 ISACTIVER5 GICD interrupt set-active registers 0x314 32 read-write n 0x0 0x0 ISACTIVER5 interrupt clear-pending 0 32 ISACTIVER6 ISACTIVER6 GICD interrupt set-active registers 0x318 32 read-write n 0x0 0x0 ISACTIVER6 interrupt clear-pending 0 32 ISACTIVER7 ISACTIVER7 GICD interrupt set-active registers 0x31C 32 read-write n 0x0 0x0 ISACTIVER7 interrupt clear-pending 0 32 ISACTIVER8 ISACTIVER8 GICD interrupt set-active registers 0x320 32 read-write n 0x0 0x0 ISACTIVER8 interrupt clear-pending 0 32 ISENABLER0 ISENABLER0 GICD interrupt set-enable register 0x100 32 read-write n 0x0 0x0 ISENABLER0 interrupt set-enable 0 32 ISENABLER1 ISENABLER1 GICD interrupt set-enable register 0x104 32 read-write n 0x0 0x0 ISENABLER1 interrupt set-enable 0 32 ISENABLER2 ISENABLER2 GICD interrupt set-enable register 0x108 32 read-write n 0x0 0x0 ISENABLER2 interrupt set-enable 0 32 ISENABLER3 ISENABLER3 GICD interrupt set-enable register 0x10C 32 read-write n 0x0 0x0 ISENABLER3 interrupt set-enable 0 32 ISENABLER4 ISENABLER4 GICD interrupt set-enable register 0x110 32 read-write n 0x0 0x0 ISENABLER4 interrupt set-enable 0 32 ISENABLER5 ISENABLER5 GICD interrupt set-enable register 0x114 32 read-write n 0x0 0x0 ISENABLER5 interrupt set-enable 0 32 ISENABLER6 ISENABLER6 GICD interrupt set-enable register 0x118 32 read-write n 0x0 0x0 ISENABLER6 interrupt set-enable 0 32 ISENABLER7 ISENABLER7 GICD interrupt set-enable register 0x11C 32 read-write n 0x0 0x0 ISENABLER7 interrupt set-enable 0 32 ISENABLER8 ISENABLER8 GICD interrupt set-enable register 0x120 32 read-write n 0x0 0x0 ISENABLER8 interrupt set-enable 0 32 ISPENDR0 ISPENDR0 GICD interrupt set-pending registers 0x200 32 read-write n 0x0 0x0 ISPENDR0 interrupt set-pending 0 32 ISPENDR1 ISPENDR1 GICD interrupt set-pending registers 0x204 32 read-write n 0x0 0x0 ISPENDR1 interrupt set-pending 0 32 ISPENDR2 ISPENDR2 GICD interrupt set-pending registers 0x208 32 read-write n 0x0 0x0 ISPENDR2 interrupt set-pending 0 32 ISPENDR3 ISPENDR3 GICD interrupt set-pending registers 0x20C 32 read-write n 0x0 0x0 ISPENDR3 interrupt set-pending 0 32 ISPENDR4 ISPENDR4 GICD interrupt set-pending registers 0x210 32 read-write n 0x0 0x0 ISPENDR4 interrupt set-pending 0 32 ISPENDR5 ISPENDR5 GICD interrupt set-pending registers 0x214 32 read-write n 0x0 0x0 ISPENDR5 interrupt set-pending 0 32 ISPENDR6 ISPENDR6 GICD interrupt set-pending registers 0x218 32 read-write n 0x0 0x0 ISPENDR6 interrupt set-pending 0 32 ISPENDR7 ISPENDR7 GICD interrupt set-pending registers 0x21C 32 read-write n 0x0 0x0 ISPENDR7 interrupt set-pending 0 32 ISPENDR8 ISPENDR8 GICD interrupt set-pending registers 0x220 32 read-write n 0x0 0x0 ISPENDR8 interrupt set-pending 0 32 ITARGETSR0 ITARGETSR0 GICD interrupt processor target registers 0x800 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR1 ITARGETSR1 GICD interrupt processor target registers 0x804 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR10 ITARGETSR10 GICD interrupt processor target registers 0x828 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR11 ITARGETSR11 GICD interrupt processor target registers 0x82C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR12 ITARGETSR12 GICD interrupt processor target registers 0x830 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR13 ITARGETSR13 GICD interrupt processor target registers 0x834 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR14 ITARGETSR14 GICD interrupt processor target registers 0x838 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR15 ITARGETSR15 GICD interrupt processor target registers 0x83C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR16 ITARGETSR16 GICD interrupt processor target registers 0x840 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR17 ITARGETSR17 GICD interrupt processor target registers 0x844 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR18 ITARGETSR18 GICD interrupt processor target registers 0x848 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR19 ITARGETSR19 GICD interrupt processor target registers 0x84C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR2 ITARGETSR2 GICD interrupt processor target registers 0x808 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR20 ITARGETSR20 GICD interrupt processor target registers 0x850 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR21 ITARGETSR21 GICD interrupt processor target registers 0x854 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR22 ITARGETSR22 GICD interrupt processor target registers 0x858 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR23 ITARGETSR23 GICD interrupt processor target registers 0x85C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR24 ITARGETSR24 GICD interrupt processor target registers 0x860 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR25 ITARGETSR25 GICD interrupt processor target registers 0x864 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR26 ITARGETSR26 GICD interrupt processor target registers 0x868 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR27 ITARGETSR27 GICD interrupt processor target registers 0x86C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR28 ITARGETSR28 GICD interrupt processor target registers 0x870 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR29 ITARGETSR29 GICD interrupt processor target registers 0x874 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR3 ITARGETSR3 GICD interrupt processor target registers 0x80C 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR30 ITARGETSR30 GICD interrupt processor target registers 0x878 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR31 ITARGETSR31 GICD interrupt processor target registers 0x87C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR32 ITARGETSR32 GICD interrupt processor target registers 0x880 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR33 ITARGETSR33 GICD interrupt processor target registers 0x884 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR34 ITARGETSR34 GICD interrupt processor target registers 0x888 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR35 ITARGETSR35 GICD interrupt processor target registers 0x88C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR36 ITARGETSR36 GICD interrupt processor target registers 0x890 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR37 ITARGETSR37 GICD interrupt processor target registers 0x894 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR38 ITARGETSR38 GICD interrupt processor target registers 0x898 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR39 ITARGETSR39 GICD interrupt processor target registers 0x89C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR4 ITARGETSR4 GICD interrupt processor target registers 0x810 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR40 ITARGETSR40 GICD interrupt processor target registers 0x8A0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR41 ITARGETSR41 GICD interrupt processor target registers 0x8A4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR42 ITARGETSR42 GICD interrupt processor target registers 0x8A8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR43 ITARGETSR43 GICD interrupt processor target registers 0x8AC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR44 ITARGETSR44 GICD interrupt processor target registers 0x8B0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR45 ITARGETSR45 GICD interrupt processor target registers 0x8B4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR46 ITARGETSR46 GICD interrupt processor target registers 0x8B8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR47 ITARGETSR47 GICD interrupt processor target registers 0x8BC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR48 ITARGETSR48 GICD interrupt processor target registers 0x8C0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR49 ITARGETSR49 GICD interrupt processor target registers 0x8C4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR5 ITARGETSR5 GICD interrupt processor target registers 0x814 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR50 ITARGETSR50 GICD interrupt processor target registers 0x8C8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR51 ITARGETSR51 GICD interrupt processor target registers 0x8CC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR52 ITARGETSR52 GICD interrupt processor target registers 0x8D0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR53 ITARGETSR53 GICD interrupt processor target registers 0x8D4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR54 ITARGETSR54 GICD interrupt processor target registers 0x8D8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR55 ITARGETSR55 GICD interrupt processor target registers 0x8DC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR56 ITARGETSR56 GICD interrupt processor target registers 0x8E0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR57 ITARGETSR57 GICD interrupt processor target registers 0x8E4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR58 ITARGETSR58 GICD interrupt processor target registers 0x8E8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR59 ITARGETSR59 GICD interrupt processor target registers 0x8EC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR6 ITARGETSR6 GICD interrupt processor target registers 0x818 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR60 ITARGETSR60 GICD interrupt processor target registers 0x8F0 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR61 ITARGETSR61 GICD interrupt processor target registers 0x8F4 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR62 ITARGETSR62 GICD interrupt processor target registers 0x8F8 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR63 ITARGETSR63 GICD interrupt processor target registers 0x8FC 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR64 ITARGETSR64 GICD interrupt processor target registers 0x900 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR65 ITARGETSR65 GICD interrupt processor target registers 0x904 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR66 ITARGETSR66 GICD interrupt processor target registers 0x908 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR67 ITARGETSR67 GICD interrupt processor target registers 0x90C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR68 ITARGETSR68 GICD interrupt processor target registers 0x910 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR69 ITARGETSR69 GICD interrupt processor target registers 0x914 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR7 ITARGETSR7 GICD interrupt processor target registers 0x81C 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR70 ITARGETSR70 GICD interrupt processor target registers 0x918 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR71 ITARGETSR71 GICD interrupt processor target registers 0x91C 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR8 ITARGETSR8 GICD interrupt processor target registers 0x820 32 read-only n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 ITARGETSR9 ITARGETSR9 GICD interrupt processor target registers 0x824 32 read-write n 0x0 0x0 CPU_TARGETS0 CPU(s) target for interrupt 0 2 CPU_TARGETS1 CPU(s) target for interrupt 8 2 CPU_TARGETS2 CPU(s) target for interrupt 16 2 CPU_TARGETS3 CPU(s) target for interrupt 24 2 PIDR0 PIDR0 GICD peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PIDR0 peripheral ID0 0 32 PIDR1 PIDR1 GICD peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 PIDR1 peripheral ID1 0 32 PIDR2 PIDR2 GICD peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 PIDR2 peripheral ID2 0 32 PIDR3 PIDR3 GICD peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 PIDR3 peripheral ID3 0 32 PIDR4 PIDR4 GICD peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 PIDR4 peripheral ID4 0 32 PIDR5 PIDR5 GICD peripheral ID5 register 0xFD4 32 read-only n 0x0 0x0 PIDR5 peripheral ID5 0 32 PIDR6 PIDR6 GICD peripheral ID6 register 0xFD8 32 read-only n 0x0 0x0 PIDR6 peripheral ID6 0 32 PIDR7 PIDR7 GICD peripheral ID7 register 0xFDC 32 read-only n 0x0 0x0 PIDR7 peripheral ID7 0 32 PPISR PPISR GICD private peripheral interrupt status register 0xD00 32 read-only n 0x0 0x0 PPI0 nFIQ (not used) 12 1 PPI1 secure physical timer event 13 1 PPI2 secure physical timer event 14 1 PPI3 nIRQ (not used) 15 1 PPI4 virtual timer event 11 1 PPI5 hypervisor timer event 10 1 PPI6 virtual maintenance interrupt 9 1 SGIR SGIR GICD software generated interrupt register 0xF00 32 write-only n 0x0 0x0 CPUTARGETLIST CPU target list 16 2 NSATT non-secure attribute 15 1 SGIINTID SGI interrupt ID 0 4 TARGETLISTFILTER target list filter 24 2 SPENDSGIR0 SPENDSGIR0 GICD SGI set-pending registers 0xF20 32 read-write n 0x0 0x0 SGI_SET_PENDING0 clear-pending state for SGI 0 2 SGI_SET_PENDING1 clear-pending state for SGI 8 2 SGI_SET_PENDING2 clear-pending state for SGI 16 2 SGI_SET_PENDING3 clear-pending state for SGI 24 2 SPENDSGIR1 SPENDSGIR1 GICD SGI set-pending registers 0xF24 32 read-write n 0x0 0x0 SGI_SET_PENDING0 clear-pending state for SGI 0 2 SGI_SET_PENDING1 clear-pending state for SGI 8 2 SGI_SET_PENDING2 clear-pending state for SGI 16 2 SGI_SET_PENDING3 clear-pending state for SGI 24 2 SPENDSGIR2 SPENDSGIR2 GICD SGI set-pending registers 0xF28 32 read-write n 0x0 0x0 SGI_SET_PENDING0 clear-pending state for SGI 0 2 SGI_SET_PENDING1 clear-pending state for SGI 8 2 SGI_SET_PENDING2 clear-pending state for SGI 16 2 SGI_SET_PENDING3 clear-pending state for SGI 24 2 SPENDSGIR3 SPENDSGIR3 GICD SGI set-pending registers 0xF2C 32 read-write n 0x0 0x0 SGI_SET_PENDING0 clear-pending state for SGI 0 2 SGI_SET_PENDING1 clear-pending state for SGI 8 2 SGI_SET_PENDING2 clear-pending state for SGI 16 2 SGI_SET_PENDING3 clear-pending state for SGI 24 2 SPISR0 SPISR0 GICD shared peripheral interrupt registers 0xD04 32 read-only n 0x0 0x0 SPISR0 shared peripheral interrupt 0 32 SPISR1 SPISR1 GICD shared peripheral interrupt registers 0xD08 32 read-only n 0x0 0x0 SPISR1 shared peripheral interrupt 0 32 SPISR2 SPISR2 GICD shared peripheral interrupt registers 0xD0C 32 read-only n 0x0 0x0 SPISR2 shared peripheral interrupt 0 32 SPISR3 SPISR3 GICD shared peripheral interrupt registers 0xD10 32 read-only n 0x0 0x0 SPISR3 shared peripheral interrupt 0 32 SPISR4 SPISR4 GICD shared peripheral interrupt registers 0xD14 32 read-only n 0x0 0x0 SPISR4 shared peripheral interrupt 0 32 SPISR5 SPISR5 GICD shared peripheral interrupt registers 0xD18 32 read-only n 0x0 0x0 SPISR5 shared peripheral interrupt 0 32 SPISR6 SPISR6 GICD shared peripheral interrupt registers 0xD1C 32 read-only n 0x0 0x0 SPISR6 shared peripheral interrupt 0 32 SPISR7 SPISR7 GICD shared peripheral interrupt registers 0xD20 32 read-only n 0x0 0x0 SPISR7 shared peripheral interrupt 0 32 TYPER GICD_TYPER GICD interrupt controller type register 0x4 32 read-only n 0x0 0x0 CPUNUMBER number of processors interfaces 5 3 ITLINESNUMBER number of interrupt lines 0 5 LSPI lockable shared peripheral interrupt 11 5 SECURITYEXTN security extension 10 1 GICH GICH GICH 0x0 0x0 0x2000 registers n APR0 APR0 GICH active priority register 0xF0 32 read-only n 0x0 0x0 APR0 active priority 0 32 EISR0 EISR0 GICH end of interrupt status register 0x20 32 read-only n 0x0 0x0 EISR0 end of interrupt status 0 32 ELSR0 ELSR0 GICH empty list status register 0x30 32 read-only n 0x0 0x0 ELSR0 end of interrupt status 0 32 HCR HCR GICH hypervisor control register 0x0 32 read-write n 0x0 0x0 EN global enable bit for the virtual CPU interface 0 1 EOICOUNT end-of-interrupt counter 27 5 LRENPIE list register entry not present interrupt enable 2 1 NPIE no pending interrupt enable 3 1 UIE underflow interrupt enable 1 1 VGRP0DIE virtual machine disable group 0interrupt enable 5 1 VGRP0EIE virtual machine enable group 0interrupt enable 4 1 VGRP1DIE virtual machine disable group 1 interrupt enable 7 1 VGRP1EIE virtual machine enable group 1 interrupt enable 6 1 LR0 LR0 GICH list register 0x100 32 read-write n 0x0 0x0 GRP1 Indicates whether this virtual interrupt is a group 1 virtual interrupt 30 1 HW hardware interrupt 31 1 PHYSICALID physical ID 10 10 PRIORITY priority of the interrupt 23 5 STATE state of the interrupt 28 2 VIRTUALID virtual ID 0 10 LR1 LR1 GICH list register 0x104 32 read-write n 0x0 0x0 GRP1 Indicates whether this virtual interrupt is a group 1 virtual interrupt 30 1 HW hardware interrupt 31 1 PHYSICALID physical ID 10 10 PRIORITY priority of the interrupt 23 5 STATE state of the interrupt 28 2 VIRTUALID virtual ID 0 10 LR2 LR2 GICH list register 0x108 32 read-write n 0x0 0x0 GRP1 Indicates whether this virtual interrupt is a group 1 virtual interrupt 30 1 HW hardware interrupt 31 1 PHYSICALID physical ID 10 10 PRIORITY priority of the interrupt 23 5 STATE state of the interrupt 28 2 VIRTUALID virtual ID 0 10 LR3 LR3 GICH list register 0x10C 32 read-write n 0x0 0x0 GRP1 Indicates whether this virtual interrupt is a group 1 virtual interrupt 30 1 HW hardware interrupt 31 1 PHYSICALID physical ID 10 10 PRIORITY priority of the interrupt 23 5 STATE state of the interrupt 28 2 VIRTUALID virtual ID 0 10 MISR MISR GICH maintenance interrupt status register 0x10 32 read-only n 0x0 0x0 EOI End of interrupt maintenance interrupt 0 1 LRENP list register entry not present maintenance interrupt 2 1 NP no pending maintenance interrupt 3 1 U underflow maintenance interrupt 1 1 VGRP0D disabled group 0 maintenance interrupt 5 1 VGRP0E enabled group 0 maintenance interrupt 4 1 VGRP1D disabled group 1 maintenance interrupt 7 1 VGRP1E enabled group 1 maintenance interrupt 6 1 VMCR VMCR GICH virtual machine control register 0x8 32 read-write n 0x0 0x0 VEM alias of GICV_CTLR.EOIMODE 9 1 VMABP alias of GICV_ABPR.BINARY_POINT 18 3 VMACKCTL alias of GICV_CTLR.ACKCTL 2 1 VMBP alias of GICV_BPR.BINARY_POINT 21 3 VMCBPR alias of GICV_CTLR.CBPR 4 1 VMFIQEN alias of GICV_CTLR.FIQEN 3 1 VMGRP0EN alias of GICV_CTLR.ENABLEGRP0 0 1 VMGRP1EN alias of GICV_CTLR.ENABLEGRP1 1 1 VMPRIMASK alias of GICV_PMR.PRIORITY 27 5 VTR VTR GICH VGIC type register 0x4 32 read-only n 0x0 0x0 LISTREGS list registers 0 5 PREBITS preemption bits 26 3 PRIBITS priority bits 29 3 GICV GICV GICV 0x0 0x0 0x2000 registers n ABPR ABPR GICV VM aliased binary point register 0x1C 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 AEOIR AEOIR GICV VM aliased end of interrupt register 0x24 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 AHPPIR AHPPIR GICV VM aliased highest priority pending interrupt register 0x28 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID PENDINTID 0 10 AIAR AIAR GICV VM aliased interrupt register 0x20 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID The interrupt ID 0 10 APR0 APR0 GICV VM active priority register 0xD0 32 read-write n 0x0 0x0 APR0 APR0 0 32 BPR BPR GICV VM binary point register 0x8 32 read-write n 0x0 0x0 BINARY_POINT BINARY_POINT 0 3 CTLR CTLR GICV virtual machine control register 0x0 32 read-write n 0x0 0x0 ACKCTL acknowledge control 2 1 CBPR BPR control 4 1 ENABLEGRP0 ENABLEGRP0 0 1 ENABLEGRP1 ENABLEGRP1 1 1 EOIMODE end of interrupt mode 9 1 FIQEN FIQ enable for group 0 interrupts 3 1 DIR DIR GICV VM deactivate interrupt register 0x1000 32 write-only n 0x0 0x0 IIDR IIDR 0 32 EOIR EOIR GICV VM end of interrupt register 0x10 32 write-only n 0x0 0x0 CPUID CPUID 10 1 EOIINTID EOIINTID 0 10 HPPIR HPPIR GICV VM highest priority pending interrupt register 0x18 32 read-only n 0x0 0x0 CPUID CPUID 10 1 PENDINTID The virtual interrupt ID of the highest priority pending virtual interrupt 0 10 IAR IAR GICV VM interrupt acknowledge register 0xC 32 read-only n 0x0 0x0 CPUID CPUID 10 1 INTERRUPT_ID The interrupt ID 0 10 IIDR IIDR GICV VM CPU interface identification register 0xFC 32 read-only n 0x0 0x0 IIDR IIDR 0 32 PMR PMR GICV VM priority mask register 0x4 32 read-write n 0x0 0x0 PRIORITY priority mask level for the virtual CPU interface 3 5 RPR RPR GICV VM running priority register 0x14 32 read-only n 0x0 0x0 PRIORITY current running priority on the virtual CPU interface 3 5 GPIOA General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOB General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOC General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOD General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOE General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOF General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOG General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOH General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOI General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOJ General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOK General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only GPIOZ General-purpose I/Os GPIO 0x0 0x0 0x400 registers n GPIOx_AFRH GPIOx_AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFR10 AFR10 8 4 read-write AFR11 AFR11 12 4 read-write AFR12 AFR12 16 4 read-write AFR13 AFR13 20 4 read-write AFR14 AFR14 24 4 read-write AFR15 AFR15 28 4 read-write AFR8 AFR8 0 4 read-write AFR9 AFR9 4 4 read-write GPIOx_AFRL GPIOx_AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFR0 AFR0 0 4 read-write AFR1 AFR1 4 4 read-write AFR2 AFR2 8 4 read-write AFR3 AFR3 12 4 read-write AFR4 AFR4 16 4 read-write AFR5 AFR5 20 4 read-write AFR6 AFR6 24 4 read-write AFR7 AFR7 28 4 read-write GPIOx_BSRR GPIOx_BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 BR0 16 1 write-only BR1 BR1 17 1 write-only BR10 BR10 26 1 write-only BR11 BR11 27 1 write-only BR12 BR12 28 1 write-only BR13 BR13 29 1 write-only BR14 BR14 30 1 write-only BR15 BR15 31 1 write-only BR2 BR2 18 1 write-only BR3 BR3 19 1 write-only BR4 BR4 20 1 write-only BR5 BR5 21 1 write-only BR6 BR6 22 1 write-only BR7 BR7 23 1 write-only BR8 BR8 24 1 write-only BR9 BR9 25 1 write-only BS0 BS0 0 1 write-only BS1 BS1 1 1 write-only BS10 BS10 10 1 write-only BS11 BS11 11 1 write-only BS12 BS12 12 1 write-only BS13 BS13 13 1 write-only BS14 BS14 14 1 write-only BS15 BS15 15 1 write-only BS2 BS2 2 1 write-only BS3 BS3 3 1 write-only BS4 BS4 4 1 write-only BS5 BS5 5 1 write-only BS6 BS6 6 1 write-only BS7 BS7 7 1 write-only BS8 BS8 8 1 write-only BS9 BS9 9 1 write-only GPIOx_IDR GPIOx_IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 IDR0 0 1 read-only IDR1 IDR1 1 1 read-only IDR10 IDR10 10 1 read-only IDR11 IDR11 11 1 read-only IDR12 IDR12 12 1 read-only IDR13 IDR13 13 1 read-only IDR14 IDR14 14 1 read-only IDR15 IDR15 15 1 read-only IDR2 IDR2 2 1 read-only IDR3 IDR3 3 1 read-only IDR4 IDR4 4 1 read-only IDR5 IDR5 5 1 read-only IDR6 IDR6 6 1 read-only IDR7 IDR7 7 1 read-only IDR8 IDR8 8 1 read-only IDR9 IDR9 9 1 read-only GPIOx_IPIDR GPIOx_IPIDR GPIO identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only GPIOx_LCKR GPIOx_LCKR This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). 0x1C 32 read-write n 0x0 0x0 LCK0 LCK0 0 1 read-write LCK1 LCK1 1 1 read-write LCK10 LCK10 10 1 read-write LCK11 LCK11 11 1 read-write LCK12 LCK12 12 1 read-write LCK13 LCK13 13 1 read-write LCK14 LCK14 14 1 read-write LCK15 LCK15 15 1 read-write LCK2 LCK2 2 1 read-write LCK3 LCK3 3 1 read-write LCK4 LCK4 4 1 read-write LCK5 LCK5 5 1 read-write LCK6 LCK6 6 1 read-write LCK7 LCK7 7 1 read-write LCK8 LCK8 8 1 read-write LCK9 LCK9 9 1 read-write LCKK LCKK 16 1 read-write GPIOx_MODER GPIOx_MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 MODER0 0 2 read-write MODER1 MODER1 2 2 read-write MODER10 MODER10 20 2 read-write MODER11 MODER11 22 2 read-write MODER12 MODER12 24 2 read-write MODER13 MODER13 26 2 read-write MODER14 MODER14 28 2 read-write MODER15 MODER15 30 2 read-write MODER2 MODER2 4 2 read-write MODER3 MODER3 6 2 read-write MODER4 MODER4 8 2 read-write MODER5 MODER5 10 2 read-write MODER6 MODER6 12 2 read-write MODER7 MODER7 14 2 read-write MODER8 MODER8 16 2 read-write MODER9 MODER9 18 2 read-write GPIOx_ODR GPIOx_ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 read-write ODR1 ODR1 1 1 read-write ODR10 ODR10 10 1 read-write ODR11 ODR11 11 1 read-write ODR12 ODR12 12 1 read-write ODR13 ODR13 13 1 read-write ODR14 ODR14 14 1 read-write ODR15 ODR15 15 1 read-write ODR2 ODR2 2 1 read-write ODR3 ODR3 3 1 read-write ODR4 ODR4 4 1 read-write ODR5 ODR5 5 1 read-write ODR6 ODR6 6 1 read-write ODR7 ODR7 7 1 read-write ODR8 ODR8 8 1 read-write ODR9 ODR9 9 1 read-write GPIOx_OSPEEDR GPIOx_OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 OSPEEDR0 0 2 read-write OSPEEDR1 OSPEEDR1 2 2 read-write OSPEEDR10 OSPEEDR10 20 2 read-write OSPEEDR11 OSPEEDR11 22 2 read-write OSPEEDR12 OSPEEDR12 24 2 read-write OSPEEDR13 OSPEEDR13 26 2 read-write OSPEEDR14 OSPEEDR14 28 2 read-write OSPEEDR15 OSPEEDR15 30 2 read-write OSPEEDR2 OSPEEDR2 4 2 read-write OSPEEDR3 OSPEEDR3 6 2 read-write OSPEEDR4 OSPEEDR4 8 2 read-write OSPEEDR5 OSPEEDR5 10 2 read-write OSPEEDR6 OSPEEDR6 12 2 read-write OSPEEDR7 OSPEEDR7 14 2 read-write OSPEEDR8 OSPEEDR8 16 2 read-write OSPEEDR9 OSPEEDR9 18 2 read-write GPIOx_OTYPER GPIOx_OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 OT0 0 1 read-write OT1 OT1 1 1 read-write OT10 OT10 10 1 read-write OT11 OT11 11 1 read-write OT12 OT12 12 1 read-write OT13 OT13 13 1 read-write OT14 OT14 14 1 read-write OT15 OT15 15 1 read-write OT2 OT2 2 1 read-write OT3 OT3 3 1 read-write OT4 OT4 4 1 read-write OT5 OT5 5 1 read-write OT6 OT6 6 1 read-write OT7 OT7 7 1 read-write OT8 OT8 8 1 read-write OT9 OT9 9 1 read-write GPIOx_PUPDR GPIOx_PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 PUPDR0 0 2 read-write PUPDR1 PUPDR1 2 2 read-write PUPDR10 PUPDR10 20 2 read-write PUPDR11 PUPDR11 22 2 read-write PUPDR12 PUPDR12 24 2 read-write PUPDR13 PUPDR13 26 2 read-write PUPDR14 PUPDR14 28 2 read-write PUPDR15 PUPDR15 30 2 read-write PUPDR2 PUPDR2 4 2 read-write PUPDR3 PUPDR3 6 2 read-write PUPDR4 PUPDR4 8 2 read-write PUPDR5 PUPDR5 10 2 read-write PUPDR6 PUPDR6 12 2 read-write PUPDR7 PUPDR7 14 2 read-write PUPDR8 PUPDR8 16 2 read-write PUPDR9 PUPDR9 18 2 read-write GPIOx_SIDR GPIOx_SIDR GPIO size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only GPIOx_VERR GPIOx_VERR GPIO version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only HASH1 Hash processor HASH 0x0 0x0 0x400 registers n HASH_RNG HASH and RNG 80 CR CR control register 0x0 32 read-write n 0x0 0x0 ALGO0 Algorithm selection 7 1 read-write ALGO1 ALGO 18 1 read-write DATATYPE Data type selection 4 2 read-write DINNE DIN not empty 12 1 read-only DMAE DMA enable 3 1 read-write INIT Initialize message digest calculation 2 1 write-only LKEY Long key selection 16 1 read-write MDMAT Multiple DMA Transfers 13 1 read-write MODE Mode selection 6 1 read-write NBW Number of words already pushed 8 4 read-only CSR0 CSR0 context swap registers 0xF8 32 read-write n 0x0 0x0 CSR0 CSR0 0 32 CSR1 CSR1 context swap registers 0xFC 32 read-write n 0x0 0x0 CSR1 CSR1 0 32 CSR10 CSR10 context swap registers 0x120 32 read-write n 0x0 0x0 CSR10 CSR10 0 32 CSR11 CSR11 context swap registers 0x124 32 read-write n 0x0 0x0 CSR11 CSR11 0 32 CSR12 CSR12 context swap registers 0x128 32 read-write n 0x0 0x0 CSR12 CSR12 0 32 CSR13 CSR13 context swap registers 0x12C 32 read-write n 0x0 0x0 CSR13 CSR13 0 32 CSR14 CSR14 context swap registers 0x130 32 read-write n 0x0 0x0 CSR14 CSR14 0 32 CSR15 CSR15 context swap registers 0x134 32 read-write n 0x0 0x0 CSR15 CSR15 0 32 CSR16 CSR16 context swap registers 0x138 32 read-write n 0x0 0x0 CSR16 CSR16 0 32 CSR17 CSR17 context swap registers 0x13C 32 read-write n 0x0 0x0 CSR17 CSR17 0 32 CSR18 CSR18 context swap registers 0x140 32 read-write n 0x0 0x0 CSR18 CSR18 0 32 CSR19 CSR19 context swap registers 0x144 32 read-write n 0x0 0x0 CSR19 CSR19 0 32 CSR2 CSR2 context swap registers 0x100 32 read-write n 0x0 0x0 CSR2 CSR2 0 32 CSR20 CSR20 context swap registers 0x148 32 read-write n 0x0 0x0 CSR20 CSR20 0 32 CSR21 CSR21 context swap registers 0x14C 32 read-write n 0x0 0x0 CSR21 CSR21 0 32 CSR22 CSR22 context swap registers 0x150 32 read-write n 0x0 0x0 CSR22 CSR22 0 32 CSR23 CSR23 context swap registers 0x154 32 read-write n 0x0 0x0 CSR23 CSR23 0 32 CSR24 CSR24 context swap registers 0x158 32 read-write n 0x0 0x0 CSR24 CSR24 0 32 CSR25 CSR25 context swap registers 0x15C 32 read-write n 0x0 0x0 CSR25 CSR25 0 32 CSR26 CSR26 context swap registers 0x160 32 read-write n 0x0 0x0 CSR26 CSR26 0 32 CSR27 CSR27 context swap registers 0x164 32 read-write n 0x0 0x0 CSR27 CSR27 0 32 CSR28 CSR28 context swap registers 0x168 32 read-write n 0x0 0x0 CSR28 CSR28 0 32 CSR29 CSR29 context swap registers 0x16C 32 read-write n 0x0 0x0 CSR29 CSR29 0 32 CSR3 CSR3 context swap registers 0x104 32 read-write n 0x0 0x0 CSR3 CSR3 0 32 CSR30 CSR30 context swap registers 0x170 32 read-write n 0x0 0x0 CSR30 CSR30 0 32 CSR31 CSR31 context swap registers 0x174 32 read-write n 0x0 0x0 CSR31 CSR31 0 32 CSR32 CSR32 context swap registers 0x178 32 read-write n 0x0 0x0 CSR32 CSR32 0 32 CSR33 CSR33 context swap registers 0x17C 32 read-write n 0x0 0x0 CSR33 CSR33 0 32 CSR34 CSR34 context swap registers 0x180 32 read-write n 0x0 0x0 CSR34 CSR34 0 32 CSR35 CSR35 context swap registers 0x184 32 read-write n 0x0 0x0 CSR35 CSR35 0 32 CSR36 CSR36 context swap registers 0x188 32 read-write n 0x0 0x0 CSR36 CSR36 0 32 CSR37 CSR37 context swap registers 0x18C 32 read-write n 0x0 0x0 CSR37 CSR37 0 32 CSR38 CSR38 context swap registers 0x190 32 read-write n 0x0 0x0 CSR38 CSR38 0 32 CSR39 CSR39 context swap registers 0x194 32 read-write n 0x0 0x0 CSR39 CSR39 0 32 CSR4 CSR4 context swap registers 0x108 32 read-write n 0x0 0x0 CSR4 CSR4 0 32 CSR40 CSR40 context swap registers 0x198 32 read-write n 0x0 0x0 CSR40 CSR40 0 32 CSR41 CSR41 context swap registers 0x19C 32 read-write n 0x0 0x0 CSR41 CSR41 0 32 CSR42 CSR42 context swap registers 0x1A0 32 read-write n 0x0 0x0 CSR42 CSR42 0 32 CSR43 CSR43 context swap registers 0x1A4 32 read-write n 0x0 0x0 CSR43 CSR43 0 32 CSR44 CSR44 context swap registers 0x1A8 32 read-write n 0x0 0x0 CSR44 CSR44 0 32 CSR45 CSR45 context swap registers 0x1AC 32 read-write n 0x0 0x0 CSR45 CSR45 0 32 CSR46 CSR46 context swap registers 0x1B0 32 read-write n 0x0 0x0 CSR46 CSR46 0 32 CSR47 CSR47 context swap registers 0x1B4 32 read-write n 0x0 0x0 CSR47 CSR47 0 32 CSR48 CSR48 context swap registers 0x1B8 32 read-write n 0x0 0x0 CSR48 CSR48 0 32 CSR49 CSR49 context swap registers 0x1BC 32 read-write n 0x0 0x0 CSR49 CSR49 0 32 CSR5 CSR5 context swap registers 0x10C 32 read-write n 0x0 0x0 CSR5 CSR5 0 32 CSR50 CSR50 context swap registers 0x1C0 32 read-write n 0x0 0x0 CSR50 CSR50 0 32 CSR51 CSR51 context swap registers 0x1C4 32 read-write n 0x0 0x0 CSR51 CSR51 0 32 CSR52 CSR52 context swap registers 0x1C8 32 read-write n 0x0 0x0 CSR52 CSR52 0 32 CSR53 CSR53 context swap registers 0x1CC 32 read-write n 0x0 0x0 CSR53 CSR53 0 32 CSR6 CSR6 context swap registers 0x110 32 read-write n 0x0 0x0 CSR6 CSR6 0 32 CSR7 CSR7 context swap registers 0x114 32 read-write n 0x0 0x0 CSR7 CSR7 0 32 CSR8 CSR8 context swap registers 0x118 32 read-write n 0x0 0x0 CSR8 CSR8 0 32 CSR9 CSR9 context swap registers 0x11C 32 read-write n 0x0 0x0 CSR9 CSR9 0 32 DIN DIN data input register 0x4 32 read-write n 0x0 0x0 DATAIN Data input 0 32 HASH_HR0 HASH_HR0 HASH digest register 0x310 32 read-only n 0x0 0x0 H0 H0 0 32 HASH_HR1 HASH_HR1 read-only 0x314 32 read-only n 0x0 0x0 H1 H1 0 32 HASH_HR2 HASH_HR2 read-only 0x318 32 read-only n 0x0 0x0 H2 H2 0 32 HASH_HR3 HASH_HR3 read-only 0x31C 32 read-only n 0x0 0x0 H3 H3 0 32 HASH_HR4 HASH_HR4 read-only 0x320 32 read-only n 0x0 0x0 H4 H4 0 32 HASH_HR5 HASH_HR5 read-only 0x324 32 read-only n 0x0 0x0 H5 H5 0 32 HASH_HR6 HASH_HR6 read-only 0x328 32 read-only n 0x0 0x0 H6 H6 0 32 HASH_HR7 HASH_HR7 read-only 0x32C 32 read-only n 0x0 0x0 H7 H7 0 32 HR0 HR0 digest registers 0xC 32 read-only n 0x0 0x0 H0 H0 0 32 HR1 HR1 digest registers 0x10 32 read-only n 0x0 0x0 H1 H1 0 32 HR2 HR2 digest registers 0x14 32 read-only n 0x0 0x0 H2 H2 0 32 HR3 HR3 digest registers 0x18 32 read-only n 0x0 0x0 H3 H3 0 32 HR4 HR4 digest registers 0x1C 32 read-only n 0x0 0x0 H4 H4 0 32 HWCFGR HWCFGR HASH Hardware Configuration Register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 ID ID HASH Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 IMR IMR interrupt enable register 0x20 32 read-write n 0x0 0x0 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 MID MID HASH Hardware Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 SR SR status register 0x24 32 read-write n 0x0 0x0 BUSY Busy bit 3 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write DMAS DMA Status 2 1 read-only STR STR start register 0x8 32 read-write n 0x0 0x0 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write VER VER HASH Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 HASH2 Hash processor HASH 0x0 0x0 0x400 registers n CR CR control register 0x0 32 read-write n 0x0 0x0 ALGO0 Algorithm selection 7 1 read-write ALGO1 ALGO 18 1 read-write DATATYPE Data type selection 4 2 read-write DINNE DIN not empty 12 1 read-only DMAE DMA enable 3 1 read-write INIT Initialize message digest calculation 2 1 write-only LKEY Long key selection 16 1 read-write MDMAT Multiple DMA Transfers 13 1 read-write MODE Mode selection 6 1 read-write NBW Number of words already pushed 8 4 read-only CSR0 CSR0 context swap registers 0xF8 32 read-write n 0x0 0x0 CSR0 CSR0 0 32 CSR1 CSR1 context swap registers 0xFC 32 read-write n 0x0 0x0 CSR1 CSR1 0 32 CSR10 CSR10 context swap registers 0x120 32 read-write n 0x0 0x0 CSR10 CSR10 0 32 CSR11 CSR11 context swap registers 0x124 32 read-write n 0x0 0x0 CSR11 CSR11 0 32 CSR12 CSR12 context swap registers 0x128 32 read-write n 0x0 0x0 CSR12 CSR12 0 32 CSR13 CSR13 context swap registers 0x12C 32 read-write n 0x0 0x0 CSR13 CSR13 0 32 CSR14 CSR14 context swap registers 0x130 32 read-write n 0x0 0x0 CSR14 CSR14 0 32 CSR15 CSR15 context swap registers 0x134 32 read-write n 0x0 0x0 CSR15 CSR15 0 32 CSR16 CSR16 context swap registers 0x138 32 read-write n 0x0 0x0 CSR16 CSR16 0 32 CSR17 CSR17 context swap registers 0x13C 32 read-write n 0x0 0x0 CSR17 CSR17 0 32 CSR18 CSR18 context swap registers 0x140 32 read-write n 0x0 0x0 CSR18 CSR18 0 32 CSR19 CSR19 context swap registers 0x144 32 read-write n 0x0 0x0 CSR19 CSR19 0 32 CSR2 CSR2 context swap registers 0x100 32 read-write n 0x0 0x0 CSR2 CSR2 0 32 CSR20 CSR20 context swap registers 0x148 32 read-write n 0x0 0x0 CSR20 CSR20 0 32 CSR21 CSR21 context swap registers 0x14C 32 read-write n 0x0 0x0 CSR21 CSR21 0 32 CSR22 CSR22 context swap registers 0x150 32 read-write n 0x0 0x0 CSR22 CSR22 0 32 CSR23 CSR23 context swap registers 0x154 32 read-write n 0x0 0x0 CSR23 CSR23 0 32 CSR24 CSR24 context swap registers 0x158 32 read-write n 0x0 0x0 CSR24 CSR24 0 32 CSR25 CSR25 context swap registers 0x15C 32 read-write n 0x0 0x0 CSR25 CSR25 0 32 CSR26 CSR26 context swap registers 0x160 32 read-write n 0x0 0x0 CSR26 CSR26 0 32 CSR27 CSR27 context swap registers 0x164 32 read-write n 0x0 0x0 CSR27 CSR27 0 32 CSR28 CSR28 context swap registers 0x168 32 read-write n 0x0 0x0 CSR28 CSR28 0 32 CSR29 CSR29 context swap registers 0x16C 32 read-write n 0x0 0x0 CSR29 CSR29 0 32 CSR3 CSR3 context swap registers 0x104 32 read-write n 0x0 0x0 CSR3 CSR3 0 32 CSR30 CSR30 context swap registers 0x170 32 read-write n 0x0 0x0 CSR30 CSR30 0 32 CSR31 CSR31 context swap registers 0x174 32 read-write n 0x0 0x0 CSR31 CSR31 0 32 CSR32 CSR32 context swap registers 0x178 32 read-write n 0x0 0x0 CSR32 CSR32 0 32 CSR33 CSR33 context swap registers 0x17C 32 read-write n 0x0 0x0 CSR33 CSR33 0 32 CSR34 CSR34 context swap registers 0x180 32 read-write n 0x0 0x0 CSR34 CSR34 0 32 CSR35 CSR35 context swap registers 0x184 32 read-write n 0x0 0x0 CSR35 CSR35 0 32 CSR36 CSR36 context swap registers 0x188 32 read-write n 0x0 0x0 CSR36 CSR36 0 32 CSR37 CSR37 context swap registers 0x18C 32 read-write n 0x0 0x0 CSR37 CSR37 0 32 CSR38 CSR38 context swap registers 0x190 32 read-write n 0x0 0x0 CSR38 CSR38 0 32 CSR39 CSR39 context swap registers 0x194 32 read-write n 0x0 0x0 CSR39 CSR39 0 32 CSR4 CSR4 context swap registers 0x108 32 read-write n 0x0 0x0 CSR4 CSR4 0 32 CSR40 CSR40 context swap registers 0x198 32 read-write n 0x0 0x0 CSR40 CSR40 0 32 CSR41 CSR41 context swap registers 0x19C 32 read-write n 0x0 0x0 CSR41 CSR41 0 32 CSR42 CSR42 context swap registers 0x1A0 32 read-write n 0x0 0x0 CSR42 CSR42 0 32 CSR43 CSR43 context swap registers 0x1A4 32 read-write n 0x0 0x0 CSR43 CSR43 0 32 CSR44 CSR44 context swap registers 0x1A8 32 read-write n 0x0 0x0 CSR44 CSR44 0 32 CSR45 CSR45 context swap registers 0x1AC 32 read-write n 0x0 0x0 CSR45 CSR45 0 32 CSR46 CSR46 context swap registers 0x1B0 32 read-write n 0x0 0x0 CSR46 CSR46 0 32 CSR47 CSR47 context swap registers 0x1B4 32 read-write n 0x0 0x0 CSR47 CSR47 0 32 CSR48 CSR48 context swap registers 0x1B8 32 read-write n 0x0 0x0 CSR48 CSR48 0 32 CSR49 CSR49 context swap registers 0x1BC 32 read-write n 0x0 0x0 CSR49 CSR49 0 32 CSR5 CSR5 context swap registers 0x10C 32 read-write n 0x0 0x0 CSR5 CSR5 0 32 CSR50 CSR50 context swap registers 0x1C0 32 read-write n 0x0 0x0 CSR50 CSR50 0 32 CSR51 CSR51 context swap registers 0x1C4 32 read-write n 0x0 0x0 CSR51 CSR51 0 32 CSR52 CSR52 context swap registers 0x1C8 32 read-write n 0x0 0x0 CSR52 CSR52 0 32 CSR53 CSR53 context swap registers 0x1CC 32 read-write n 0x0 0x0 CSR53 CSR53 0 32 CSR6 CSR6 context swap registers 0x110 32 read-write n 0x0 0x0 CSR6 CSR6 0 32 CSR7 CSR7 context swap registers 0x114 32 read-write n 0x0 0x0 CSR7 CSR7 0 32 CSR8 CSR8 context swap registers 0x118 32 read-write n 0x0 0x0 CSR8 CSR8 0 32 CSR9 CSR9 context swap registers 0x11C 32 read-write n 0x0 0x0 CSR9 CSR9 0 32 DIN DIN data input register 0x4 32 read-write n 0x0 0x0 DATAIN Data input 0 32 HASH_HR0 HASH_HR0 HASH digest register 0x310 32 read-only n 0x0 0x0 H0 H0 0 32 HASH_HR1 HASH_HR1 read-only 0x314 32 read-only n 0x0 0x0 H1 H1 0 32 HASH_HR2 HASH_HR2 read-only 0x318 32 read-only n 0x0 0x0 H2 H2 0 32 HASH_HR3 HASH_HR3 read-only 0x31C 32 read-only n 0x0 0x0 H3 H3 0 32 HASH_HR4 HASH_HR4 read-only 0x320 32 read-only n 0x0 0x0 H4 H4 0 32 HASH_HR5 HASH_HR5 read-only 0x324 32 read-only n 0x0 0x0 H5 H5 0 32 HASH_HR6 HASH_HR6 read-only 0x328 32 read-only n 0x0 0x0 H6 H6 0 32 HASH_HR7 HASH_HR7 read-only 0x32C 32 read-only n 0x0 0x0 H7 H7 0 32 HR0 HR0 digest registers 0xC 32 read-only n 0x0 0x0 H0 H0 0 32 HR1 HR1 digest registers 0x10 32 read-only n 0x0 0x0 H1 H1 0 32 HR2 HR2 digest registers 0x14 32 read-only n 0x0 0x0 H2 H2 0 32 HR3 HR3 digest registers 0x18 32 read-only n 0x0 0x0 H3 H3 0 32 HR4 HR4 digest registers 0x1C 32 read-only n 0x0 0x0 H4 H4 0 32 HWCFGR HWCFGR HASH Hardware Configuration Register 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 ID ID HASH Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 IMR IMR interrupt enable register 0x20 32 read-write n 0x0 0x0 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 MID MID HASH Hardware Magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 SR SR status register 0x24 32 read-write n 0x0 0x0 BUSY Busy bit 3 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write DMAS DMA Status 2 1 read-only STR STR start register 0x8 32 read-write n 0x0 0x0 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write VER VER HASH Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 HDP HDP HDP 0x0 0x0 0x400 registers n CTRL HDP_CTRL HDP Control 0x0 32 read-write n 0x0 0x0 EN EN 0 1 read-write GPOCLR HDP_GPOCLR HDP GPO clear 0x18 32 read-write n 0x0 0x0 HDPGPOCLR HDPGPOCLR 0 8 write-only GPOSET HDP_GPOSET HDP GPO set 0x14 32 read-write n 0x0 0x0 HDPGPOSET HDPGPOSET 0 8 write-only GPOVAL HDP_GPOVAL HDP GPO value 0x1C 32 read-write n 0x0 0x0 HDPGPOVAL HDPGPOVAL 0 8 read-write IPIDR HDP_IPIDR HDP IP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only MUX HDP_MUX HDP multiplexing 0x4 32 read-write n 0x0 0x0 MUX0 MUX0 0 4 read-write MUX1 MUX1 4 4 read-write MUX2 MUX2 8 4 read-write MUX3 MUX3 12 4 read-write MUX4 MUX4 16 4 read-write MUX5 MUX5 20 4 read-write MUX6 MUX6 24 4 read-write MUX7 MUX7 28 4 read-write SIDR HDP_SIDR HDP size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only VAL HDP_VAL HDP value 0x10 32 read-only n 0x0 0x0 HDPVAL HDPVAL 0 8 read-only VERR HDP_VERR HDP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only HSEM HSEM HSEM 0x0 0x0 0x400 registers n HSEM0 HSEM global interrupt 1 125 C1ICR HSEM_C1ICR HSEM Interrupt clear register 0x104 32 write-only n 0x0 0x0 ISC0 Interrupt(N) semaphore n clear bit 0 1 ISC1 Interrupt(N) semaphore n clear bit 1 1 ISC10 Interrupt(N) semaphore n clear bit 10 1 ISC11 Interrupt(N) semaphore n clear bit 11 1 ISC12 Interrupt(N) semaphore n clear bit 12 1 ISC13 Interrupt(N) semaphore n clear bit 13 1 ISC14 Interrupt(N) semaphore n clear bit 14 1 ISC15 Interrupt(N) semaphore n clear bit 15 1 ISC16 Interrupt(N) semaphore n clear bit 16 1 ISC17 Interrupt(N) semaphore n clear bit 17 1 ISC18 Interrupt(N) semaphore n clear bit 18 1 ISC19 Interrupt(N) semaphore n clear bit 19 1 ISC2 Interrupt(N) semaphore n clear bit 2 1 ISC20 Interrupt(N) semaphore n clear bit 20 1 ISC21 Interrupt(N) semaphore n clear bit 21 1 ISC22 Interrupt(N) semaphore n clear bit 22 1 ISC23 Interrupt(N) semaphore n clear bit 23 1 ISC24 Interrupt(N) semaphore n clear bit 24 1 ISC25 Interrupt(N) semaphore n clear bit 25 1 ISC26 Interrupt(N) semaphore n clear bit 26 1 ISC27 Interrupt(N) semaphore n clear bit 27 1 ISC28 Interrupt(N) semaphore n clear bit 28 1 ISC29 Interrupt(N) semaphore n clear bit 29 1 ISC3 Interrupt(N) semaphore n clear bit 3 1 ISC30 Interrupt(N) semaphore n clear bit 30 1 ISC31 Interrupt(N) semaphore n clear bit 31 1 ISC4 Interrupt(N) semaphore n clear bit 4 1 ISC5 Interrupt(N) semaphore n clear bit 5 1 ISC6 Interrupt(N) semaphore n clear bit 6 1 ISC7 Interrupt(N) semaphore n clear bit 7 1 ISC8 Interrupt(N) semaphore n clear bit 8 1 ISC9 Interrupt(N) semaphore n clear bit 9 1 C1IER HSEM_C1IER HSEM Interrupt enable register 0x100 32 read-write n 0x0 0x0 ISE0 Interrupt semaphore n enable bit 0 1 ISE1 Interrupt semaphore n enable bit 1 1 ISE10 Interrupt semaphore n enable bit 10 1 ISE11 Interrupt semaphore n enable bit 11 1 ISE12 Interrupt semaphore n enable bit 12 1 ISE13 Interrupt semaphore n enable bit 13 1 ISE14 Interrupt semaphore n enable bit 14 1 ISE15 Interrupt semaphore n enable bit 15 1 ISE16 Interrupt semaphore n enable bit 16 1 ISE17 Interrupt semaphore n enable bit 17 1 ISE18 Interrupt semaphore n enable bit 18 1 ISE19 Interrupt semaphore n enable bit 19 1 ISE2 Interrupt semaphore n enable bit 2 1 ISE20 Interrupt semaphore n enable bit 20 1 ISE21 Interrupt semaphore n enable bit 21 1 ISE22 Interrupt semaphore n enable bit 22 1 ISE23 Interrupt semaphore n enable bit 23 1 ISE24 Interrupt semaphore n enable bit 24 1 ISE25 Interrupt semaphore n enable bit 25 1 ISE26 Interrupt semaphore n enable bit 26 1 ISE27 Interrupt semaphore n enable bit 27 1 ISE28 Interrupt semaphore n enable bit 28 1 ISE29 Interrupt semaphore n enable bit 29 1 ISE3 Interrupt semaphore n enable bit 3 1 ISE30 Interrupt semaphore n enable bit 30 1 ISE31 Interrupt(N) semaphore n enable bit. 31 1 ISE4 Interrupt semaphore n enable bit 4 1 ISE5 Interrupt semaphore n enable bit 5 1 ISE6 Interrupt semaphore n enable bit 6 1 ISE7 Interrupt semaphore n enable bit 7 1 ISE8 Interrupt semaphore n enable bit 8 1 ISE9 Interrupt semaphore n enable bit 9 1 C1ISR HSEM_C1ISR HSEM Interrupt status register 0x108 32 read-only n 0x0 0x0 ISF0 Interrupt(N) semaphore n status bit before enable (mask) 0 1 ISF1 Interrupt(N) semaphore n status bit before enable (mask) 1 1 ISF10 Interrupt(N) semaphore n status bit before enable (mask) 10 1 ISF11 Interrupt(N) semaphore n status bit before enable (mask) 11 1 ISF12 Interrupt(N) semaphore n status bit before enable (mask) 12 1 ISF13 Interrupt(N) semaphore n status bit before enable (mask) 13 1 ISF14 Interrupt(N) semaphore n status bit before enable (mask) 14 1 ISF15 Interrupt(N) semaphore n status bit before enable (mask) 15 1 ISF16 Interrupt(N) semaphore n status bit before enable (mask) 16 1 ISF17 Interrupt(N) semaphore n status bit before enable (mask) 17 1 ISF18 Interrupt(N) semaphore n status bit before enable (mask) 18 1 ISF19 Interrupt(N) semaphore n status bit before enable (mask) 19 1 ISF2 Interrupt(N) semaphore n status bit before enable (mask) 2 1 ISF20 Interrupt(N) semaphore n status bit before enable (mask) 20 1 ISF21 Interrupt(N) semaphore n status bit before enable (mask) 21 1 ISF22 Interrupt(N) semaphore n status bit before enable (mask) 22 1 ISF23 Interrupt(N) semaphore n status bit before enable (mask) 23 1 ISF24 Interrupt(N) semaphore n status bit before enable (mask) 24 1 ISF25 Interrupt(N) semaphore n status bit before enable (mask) 25 1 ISF26 Interrupt(N) semaphore n status bit before enable (mask) 26 1 ISF27 Interrupt(N) semaphore n status bit before enable (mask) 27 1 ISF28 Interrupt(N) semaphore n status bit before enable (mask) 28 1 ISF29 Interrupt(N) semaphore n status bit before enable (mask) 29 1 ISF3 Interrupt(N) semaphore n status bit before enable (mask) 3 1 ISF30 Interrupt(N) semaphore n status bit before enable (mask) 30 1 ISF31 Interrupt(N) semaphore n status bit before enable (mask) 31 1 ISF4 Interrupt(N) semaphore n status bit before enable (mask) 4 1 ISF5 Interrupt(N) semaphore n status bit before enable (mask) 5 1 ISF6 Interrupt(N) semaphore n status bit before enable (mask) 6 1 ISF7 Interrupt(N) semaphore n status bit before enable (mask) 7 1 ISF8 Interrupt(N) semaphore n status bit before enable (mask) 8 1 ISF9 Interrupt(N) semaphore n status bit before enable (mask) 9 1 C1MISR HSEM_C1MISR HSEM Masked interrupt status register 0x10C 32 read-only n 0x0 0x0 MISF0 masked interrupt(N) semaphore n status bit after enable (mask) 0 1 MISF1 masked interrupt(N) semaphore n status bit after enable (mask) 1 1 MISF10 masked interrupt(N) semaphore n status bit after enable (mask) 10 1 MISF11 masked interrupt(N) semaphore n status bit after enable (mask) 11 1 MISF12 masked interrupt(N) semaphore n status bit after enable (mask) 12 1 MISF13 masked interrupt(N) semaphore n status bit after enable (mask) 13 1 MISF14 masked interrupt(N) semaphore n status bit after enable (mask) 14 1 MISF15 masked interrupt(N) semaphore n status bit after enable (mask) 15 1 MISF16 masked interrupt(N) semaphore n status bit after enable (mask) 16 1 MISF17 masked interrupt(N) semaphore n status bit after enable (mask) 17 1 MISF18 masked interrupt(N) semaphore n status bit after enable (mask) 18 1 MISF19 masked interrupt(N) semaphore n status bit after enable (mask) 19 1 MISF2 masked interrupt(N) semaphore n status bit after enable (mask) 2 1 MISF20 masked interrupt(N) semaphore n status bit after enable (mask) 20 1 MISF21 masked interrupt(N) semaphore n status bit after enable (mask) 21 1 MISF22 masked interrupt(N) semaphore n status bit after enable (mask) 22 1 MISF23 masked interrupt(N) semaphore n status bit after enable (mask) 23 1 MISF24 masked interrupt(N) semaphore n status bit after enable (mask) 24 1 MISF25 masked interrupt(N) semaphore n status bit after enable (mask) 25 1 MISF26 masked interrupt(N) semaphore n status bit after enable (mask) 26 1 MISF27 masked interrupt(N) semaphore n status bit after enable (mask) 27 1 MISF28 masked interrupt(N) semaphore n status bit after enable (mask) 28 1 MISF29 masked interrupt(N) semaphore n status bit after enable (mask) 29 1 MISF3 masked interrupt(N) semaphore n status bit after enable (mask) 3 1 MISF30 masked interrupt(N) semaphore n status bit after enable (mask) 30 1 MISF31 masked interrupt(N) semaphore n status bit after enable (mask) 31 1 MISF4 masked interrupt(N) semaphore n status bit after enable (mask) 4 1 MISF5 masked interrupt(N) semaphore n status bit after enable (mask) 5 1 MISF6 masked interrupt(N) semaphore n status bit after enable (mask) 6 1 MISF7 masked interrupt(N) semaphore n status bit after enable (mask) 7 1 MISF8 masked interrupt(N) semaphore n status bit after enable (mask) 8 1 MISF9 masked interrupt(N) semaphore n status bit after enable (mask) 9 1 C2ICR HSEM_C2ICR HSEM Interrupt clear register 0x114 32 write-only n 0x0 0x0 ISC0 Interrupt(N) semaphore n clear bit 0 1 ISC1 Interrupt(N) semaphore n clear bit 1 1 ISC10 Interrupt(N) semaphore n clear bit 10 1 ISC11 Interrupt(N) semaphore n clear bit 11 1 ISC12 Interrupt(N) semaphore n clear bit 12 1 ISC13 Interrupt(N) semaphore n clear bit 13 1 ISC14 Interrupt(N) semaphore n clear bit 14 1 ISC15 Interrupt(N) semaphore n clear bit 15 1 ISC16 Interrupt(N) semaphore n clear bit 16 1 ISC17 Interrupt(N) semaphore n clear bit 17 1 ISC18 Interrupt(N) semaphore n clear bit 18 1 ISC19 Interrupt(N) semaphore n clear bit 19 1 ISC2 Interrupt(N) semaphore n clear bit 2 1 ISC20 Interrupt(N) semaphore n clear bit 20 1 ISC21 Interrupt(N) semaphore n clear bit 21 1 ISC22 Interrupt(N) semaphore n clear bit 22 1 ISC23 Interrupt(N) semaphore n clear bit 23 1 ISC24 Interrupt(N) semaphore n clear bit 24 1 ISC25 Interrupt(N) semaphore n clear bit 25 1 ISC26 Interrupt(N) semaphore n clear bit 26 1 ISC27 Interrupt(N) semaphore n clear bit 27 1 ISC28 Interrupt(N) semaphore n clear bit 28 1 ISC29 Interrupt(N) semaphore n clear bit 29 1 ISC3 Interrupt(N) semaphore n clear bit 3 1 ISC30 Interrupt(N) semaphore n clear bit 30 1 ISC31 Interrupt(N) semaphore n clear bit 31 1 ISC4 Interrupt(N) semaphore n clear bit 4 1 ISC5 Interrupt(N) semaphore n clear bit 5 1 ISC6 Interrupt(N) semaphore n clear bit 6 1 ISC7 Interrupt(N) semaphore n clear bit 7 1 ISC8 Interrupt(N) semaphore n clear bit 8 1 ISC9 Interrupt(N) semaphore n clear bit 9 1 C2IER HSEM_C2IER HSEM Interrupt enable register 0x110 32 read-write n 0x0 0x0 ISE0 Interrupt semaphore n enable bit 0 1 ISE1 Interrupt semaphore n enable bit 1 1 ISE10 Interrupt semaphore n enable bit 10 1 ISE11 Interrupt semaphore n enable bit 11 1 ISE12 Interrupt semaphore n enable bit 12 1 ISE13 Interrupt semaphore n enable bit 13 1 ISE14 Interrupt semaphore n enable bit 14 1 ISE15 Interrupt semaphore n enable bit 15 1 ISE16 Interrupt semaphore n enable bit 16 1 ISE17 Interrupt semaphore n enable bit 17 1 ISE18 Interrupt semaphore n enable bit 18 1 ISE19 Interrupt semaphore n enable bit 19 1 ISE2 Interrupt semaphore n enable bit 2 1 ISE20 Interrupt semaphore n enable bit 20 1 ISE21 Interrupt semaphore n enable bit 21 1 ISE22 Interrupt semaphore n enable bit 22 1 ISE23 Interrupt semaphore n enable bit 23 1 ISE24 Interrupt semaphore n enable bit 24 1 ISE25 Interrupt semaphore n enable bit 25 1 ISE26 Interrupt semaphore n enable bit 26 1 ISE27 Interrupt semaphore n enable bit 27 1 ISE28 Interrupt semaphore n enable bit 28 1 ISE29 Interrupt semaphore n enable bit 29 1 ISE3 Interrupt semaphore n enable bit 3 1 ISE30 Interrupt semaphore n enable bit 30 1 ISE31 Interrupt(N) semaphore n enable bit. 31 1 ISE4 Interrupt semaphore n enable bit 4 1 ISE5 Interrupt semaphore n enable bit 5 1 ISE6 Interrupt semaphore n enable bit 6 1 ISE7 Interrupt semaphore n enable bit 7 1 ISE8 Interrupt semaphore n enable bit 8 1 ISE9 Interrupt semaphore n enable bit 9 1 C2ISR HSEM_C2ISR HSEM Interrupt status register 0x118 32 read-only n 0x0 0x0 ISF0 Interrupt(N) semaphore n status bit before enable (mask) 0 1 ISF1 Interrupt(N) semaphore n status bit before enable (mask) 1 1 ISF10 Interrupt(N) semaphore n status bit before enable (mask) 10 1 ISF11 Interrupt(N) semaphore n status bit before enable (mask) 11 1 ISF12 Interrupt(N) semaphore n status bit before enable (mask) 12 1 ISF13 Interrupt(N) semaphore n status bit before enable (mask) 13 1 ISF14 Interrupt(N) semaphore n status bit before enable (mask) 14 1 ISF15 Interrupt(N) semaphore n status bit before enable (mask) 15 1 ISF16 Interrupt(N) semaphore n status bit before enable (mask) 16 1 ISF17 Interrupt(N) semaphore n status bit before enable (mask) 17 1 ISF18 Interrupt(N) semaphore n status bit before enable (mask) 18 1 ISF19 Interrupt(N) semaphore n status bit before enable (mask) 19 1 ISF2 Interrupt(N) semaphore n status bit before enable (mask) 2 1 ISF20 Interrupt(N) semaphore n status bit before enable (mask) 20 1 ISF21 Interrupt(N) semaphore n status bit before enable (mask) 21 1 ISF22 Interrupt(N) semaphore n status bit before enable (mask) 22 1 ISF23 Interrupt(N) semaphore n status bit before enable (mask) 23 1 ISF24 Interrupt(N) semaphore n status bit before enable (mask) 24 1 ISF25 Interrupt(N) semaphore n status bit before enable (mask) 25 1 ISF26 Interrupt(N) semaphore n status bit before enable (mask) 26 1 ISF27 Interrupt(N) semaphore n status bit before enable (mask) 27 1 ISF28 Interrupt(N) semaphore n status bit before enable (mask) 28 1 ISF29 Interrupt(N) semaphore n status bit before enable (mask) 29 1 ISF3 Interrupt(N) semaphore n status bit before enable (mask) 3 1 ISF30 Interrupt(N) semaphore n status bit before enable (mask) 30 1 ISF31 Interrupt(N) semaphore n status bit before enable (mask) 31 1 ISF4 Interrupt(N) semaphore n status bit before enable (mask) 4 1 ISF5 Interrupt(N) semaphore n status bit before enable (mask) 5 1 ISF6 Interrupt(N) semaphore n status bit before enable (mask) 6 1 ISF7 Interrupt(N) semaphore n status bit before enable (mask) 7 1 ISF8 Interrupt(N) semaphore n status bit before enable (mask) 8 1 ISF9 Interrupt(N) semaphore n status bit before enable (mask) 9 1 C2MISR HSEM_C2MISR HSEM Masked interrupt status register 0x11C 32 read-only n 0x0 0x0 MISF0 masked interrupt(N) semaphore n status bit after enable (mask) 0 1 MISF1 masked interrupt(N) semaphore n status bit after enable (mask) 1 1 MISF10 masked interrupt(N) semaphore n status bit after enable (mask) 10 1 MISF11 masked interrupt(N) semaphore n status bit after enable (mask) 11 1 MISF12 masked interrupt(N) semaphore n status bit after enable (mask) 12 1 MISF13 masked interrupt(N) semaphore n status bit after enable (mask) 13 1 MISF14 masked interrupt(N) semaphore n status bit after enable (mask) 14 1 MISF15 masked interrupt(N) semaphore n status bit after enable (mask) 15 1 MISF16 masked interrupt(N) semaphore n status bit after enable (mask) 16 1 MISF17 masked interrupt(N) semaphore n status bit after enable (mask) 17 1 MISF18 masked interrupt(N) semaphore n status bit after enable (mask) 18 1 MISF19 masked interrupt(N) semaphore n status bit after enable (mask) 19 1 MISF2 masked interrupt(N) semaphore n status bit after enable (mask) 2 1 MISF20 masked interrupt(N) semaphore n status bit after enable (mask) 20 1 MISF21 masked interrupt(N) semaphore n status bit after enable (mask) 21 1 MISF22 masked interrupt(N) semaphore n status bit after enable (mask) 22 1 MISF23 masked interrupt(N) semaphore n status bit after enable (mask) 23 1 MISF24 masked interrupt(N) semaphore n status bit after enable (mask) 24 1 MISF25 masked interrupt(N) semaphore n status bit after enable (mask) 25 1 MISF26 masked interrupt(N) semaphore n status bit after enable (mask) 26 1 MISF27 masked interrupt(N) semaphore n status bit after enable (mask) 27 1 MISF28 masked interrupt(N) semaphore n status bit after enable (mask) 28 1 MISF29 masked interrupt(N) semaphore n status bit after enable (mask) 29 1 MISF3 masked interrupt(N) semaphore n status bit after enable (mask) 3 1 MISF30 masked interrupt(N) semaphore n status bit after enable (mask) 30 1 MISF31 masked interrupt(N) semaphore n status bit after enable (mask) 31 1 MISF4 masked interrupt(N) semaphore n status bit after enable (mask) 4 1 MISF5 masked interrupt(N) semaphore n status bit after enable (mask) 5 1 MISF6 masked interrupt(N) semaphore n status bit after enable (mask) 6 1 MISF7 masked interrupt(N) semaphore n status bit after enable (mask) 7 1 MISF8 masked interrupt(N) semaphore n status bit after enable (mask) 8 1 MISF9 masked interrupt(N) semaphore n status bit after enable (mask) 9 1 CR HSEM_CR HSEM Clear register 0x140 32 read-write n 0x0 0x0 COREID MasterID of semaphores to be cleared 8 4 KEY Semaphore clear Key 16 16 HWCFGR1 HSEM_HWCFGR1 HSEM Hardware Configuration Register 1 0x3F0 32 read-only n 0x0 0x0 NBINT NBINT 8 4 NBSEM NBSEM 0 8 HWCFGR2 HSEM_HWCFGR2 HSEM Hardware Configuration Register 2 0x3EC 32 read-only n 0x0 0x0 MASTERID1 MASTERID1 0 4 MASTERID2 MASTERID2 4 4 MASTERID3 MASTERID3 8 4 MASTERID4 MASTERID4 12 4 IPIDR HSEM_IPIDR HSEM IP Version Register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 KEYR HSEM_KEYR HSEM Interrupt clear register 0x144 32 read-write n 0x0 0x0 KEY Semaphore Clear Key 16 16 R0 HSEM_R0 HSEM register HSEM_R0 HSEM_R31 0x0 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R1 HSEM_R1 HSEM register HSEM_R0 HSEM_R31 0x4 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R10 HSEM_R10 HSEM register HSEM_R0 HSEM_R31 0x28 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R11 HSEM_R11 HSEM register HSEM_R0 HSEM_R31 0x2C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R12 HSEM_R12 HSEM register HSEM_R0 HSEM_R31 0x30 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R13 HSEM_R13 HSEM register HSEM_R0 HSEM_R31 0x34 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R14 HSEM_R14 HSEM register HSEM_R0 HSEM_R31 0x38 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R15 HSEM_R15 HSEM register HSEM_R0 HSEM_R31 0x3C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R16 HSEM_R16 HSEM register HSEM_R0 HSEM_R31 0x40 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R17 HSEM_R17 HSEM register HSEM_R0 HSEM_R31 0x44 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R18 HSEM_R18 HSEM register HSEM_R0 HSEM_R31 0x48 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R19 HSEM_R19 HSEM register HSEM_R0 HSEM_R31 0x4C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R2 HSEM_R2 HSEM register HSEM_R0 HSEM_R31 0x8 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R20 HSEM_R20 HSEM register HSEM_R0 HSEM_R31 0x50 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R21 HSEM_R21 HSEM register HSEM_R0 HSEM_R31 0x54 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R22 HSEM_R22 HSEM register HSEM_R0 HSEM_R31 0x58 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R23 HSEM_R23 HSEM register HSEM_R0 HSEM_R31 0x5C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R24 HSEM_R24 HSEM register HSEM_R0 HSEM_R31 0x60 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R25 HSEM_R25 HSEM register HSEM_R0 HSEM_R31 0x64 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R26 HSEM_R26 HSEM register HSEM_R0 HSEM_R31 0x68 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R27 HSEM_R27 HSEM register HSEM_R0 HSEM_R31 0x6C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R28 HSEM_R28 HSEM register HSEM_R0 HSEM_R31 0x70 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R29 HSEM_R29 HSEM register HSEM_R0 HSEM_R31 0x74 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R3 HSEM_R3 HSEM register HSEM_R0 HSEM_R31 0xC 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R30 HSEM_R30 HSEM register HSEM_R0 HSEM_R31 0x78 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R31 HSEM_R31 HSEM register HSEM_R0 HSEM_R31 0x7C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R4 HSEM_R4 HSEM register HSEM_R0 HSEM_R31 0x10 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R5 HSEM_R5 HSEM register HSEM_R0 HSEM_R31 0x14 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R6 HSEM_R6 HSEM register HSEM_R0 HSEM_R31 0x18 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R7 HSEM_R7 HSEM register HSEM_R0 HSEM_R31 0x1C 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R8 HSEM_R8 HSEM register HSEM_R0 HSEM_R31 0x20 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 R9 HSEM_R9 HSEM register HSEM_R0 HSEM_R31 0x24 32 read-write n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR0 HSEM_RLR0 HSEM Read lock register 0x80 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR1 HSEM_RLR1 HSEM Read lock register 0x84 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR10 HSEM_RLR10 HSEM Read lock register 0xA8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR11 HSEM_RLR11 HSEM Read lock register 0xAC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR12 HSEM_RLR12 HSEM Read lock register 0xB0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR13 HSEM_RLR13 HSEM Read lock register 0xB4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR14 HSEM_RLR14 HSEM Read lock register 0xB8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR15 HSEM_RLR15 HSEM Read lock register 0xBC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR16 HSEM_RLR16 HSEM Read lock register 0xC0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR17 HSEM_RLR17 HSEM Read lock register 0xC4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR18 HSEM_RLR18 HSEM Read lock register 0xC8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR19 HSEM_RLR19 HSEM Read lock register 0xCC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR2 HSEM_RLR2 HSEM Read lock register 0x88 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR20 HSEM_RLR20 HSEM Read lock register 0xD0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR21 HSEM_RLR21 HSEM Read lock register 0xD4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR22 HSEM_RLR22 HSEM Read lock register 0xD8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR23 HSEM_RLR23 HSEM Read lock register 0xDC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR24 HSEM_RLR24 HSEM Read lock register 0xE0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR25 HSEM_RLR25 HSEM Read lock register 0xE4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR26 HSEM_RLR26 HSEM Read lock register 0xE8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR27 HSEM_RLR27 HSEM Read lock register 0xEC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR28 HSEM_RLR28 HSEM Read lock register 0xF0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR29 HSEM_RLR29 HSEM Read lock register 0xF4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR3 HSEM_RLR3 HSEM Read lock register 0x8C 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR30 HSEM_RLR30 HSEM Read lock register 0xF8 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 8 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 4 RLR31 HSEM_RLR31 HSEM Read lock register 0xFC 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR4 HSEM_RLR4 HSEM Read lock register 0x90 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR5 HSEM_RLR5 HSEM Read lock register 0x94 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR6 HSEM_RLR6 HSEM Read lock register 0x98 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR7 HSEM_RLR7 HSEM Read lock register 0x9C 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR8 HSEM_RLR8 HSEM Read lock register 0xA0 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 RLR9 HSEM_RLR9 HSEM Read lock register 0xA4 32 read-only n 0x0 0x0 COREID Semaphore MasterID 8 4 LOCK Lock indication 31 1 PROCID Semaphore ProcessID 0 8 SIDR HSEM_SIDR HSEM IP Version Register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR HSEM_VERR HSEM IP Version Register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 I2C1 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C2 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C3 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C4 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C5 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C6 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OA1_0 Interface address 0 1 OA1_7_1 Interface address 1 7 OA1_8_9 Interface address 8 2 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 IPCC IPCC IPCC 0x0 0x0 0x400 registers n C1CR C1CR IPCC Processor 1 control register 0x0 32 read-write n 0x0 0x0 RXOIE RXOIE 0 1 TXFIE TXFIE 16 1 C1MR C1MR IPCC Processor 1 mask register 0x4 32 read-write n 0x0 0x0 CH1FM CH1FM 16 1 CH1OM CH1OM 0 1 CH2FM CH2FM 17 1 CH2OM CH2OM 1 1 C1SCR C1SCR IPCC Processor 1 status set clear register 0x8 32 read-write n 0x0 0x0 CH1C CH1C 0 1 CH1S CH1S 16 1 CH2C CH2C 1 1 CH2S CH2S 17 1 C1TOC2SR C1TOC2SR IPCC processor 1 to processor 2 status register 0xC 32 read-only n 0x0 0x0 CH1F CH1F 0 1 CH2F CH2F 1 1 C2CR C2CR IPCC Processor 2 control register 0x10 32 read-write n 0x0 0x0 RXOIE RXOIE 0 1 TXFIE TXFIE 1 1 C2MR C2MR IPCC Processor 2 mask register 0x14 32 read-write n 0x0 0x0 CH1FM CH1FM 16 1 CH1OM CH1OM 0 1 CH2FM CH2FM 17 1 CH2OM CH2OM 1 1 C2SCR C2SCR IPCC Processor 2 status set clear register 0x18 32 read-write n 0x0 0x0 CH1C CH1C 0 1 CH1S CH1S 16 1 CH2C CH2C 1 1 CH2S CH2S 17 1 C2TOC1SR C2TOC1SR IPCC processor 2 to processor 1 status register 0x1C 32 read-only n 0x0 0x0 CH1F CH1F 0 1 CH2F CH2F 1 1 HWCFGR HWCFGR hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CHANNELS CHANNELS 0 8 ID ID ID register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 SID SID size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 VERR VERR version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 IWDG1 IWDG1 IWDG 0x0 0x0 0x400 registers n IWDG_HWCFGR IWDG_HWCFGR IWDG hardware configuration register 0x3F0 32 read-only n 0x0 0x0 PR_DEFAULT PR_DEFAULT 4 4 read-only WINDOW WINDOW 0 4 read-only IWDG_IDR IWDG_IDR IWDG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only IWDG_KR IWDG_KR Key register 0x0 32 read-write n 0x0 0x0 KEY KEY 0 16 write-only IWDG_PR IWDG_PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR PR 0 3 read-write IWDG_RLR IWDG_RLR Reload register 0x8 32 read-write n 0x0 0x0 RL RL 0 12 read-write IWDG_SIDR IWDG_SIDR IWDG size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only IWDG_SR IWDG_SR Status register 0xC 32 read-only n 0x0 0x0 PVU PVU 0 1 read-only RVU RVU 1 1 read-only WVU WVU 2 1 read-only IWDG_VERR IWDG_VERR IWDG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only IWDG_WINR IWDG_WINR Window register 0x10 32 read-write n 0x0 0x0 WIN WIN 0 12 read-write LPTIM1 LPTIM1 LPTIMER 0x0 0x0 0x400 registers n LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 read-write LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 read-write CKPOL CKPOL 1 2 read-write CKSEL CKSEL 0 1 read-write COUNTMODE COUNTMODE 23 1 read-write ENC ENC 24 1 read-write PRELOAD PRELOAD 22 1 read-write PRESC PRESC 9 3 read-write TIMOUT TIMOUT 19 1 read-write TRGFLT TRGFLT 6 2 read-write TRIGEN TRIGEN 17 2 read-write TRIGSEL TRIGSEL 13 3 read-write WAVE WAVE 20 1 read-write WAVPOL WAVPOL 21 1 read-write LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 read-write IN2SEL IN2SEL 4 2 read-write LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 read-write LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 read-only LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 read-write COUNTRST COUNTRST 3 1 read-write ENABLE ENABLE 0 1 read-write RSTARE RSTARE 4 1 write-only SNGSTRT SNGSTRT 1 1 read-write LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 read-write n 0x0 0x0 ARRMCF ARRMCF 1 1 write-only ARROKCF ARROKCF 4 1 write-only CMPMCF CMPMCF 0 1 write-only CMPOKCF CMPOKCF 3 1 write-only DOWNCF DOWNCF 6 1 write-only EXTTRIGCF EXTTRIGCF 2 1 write-only UPCF UPCF 5 1 write-only LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 read-write ARROKIE ARROKIE 4 1 read-write CMPMIE CMPMIE 0 1 read-write CMPOKIE CMPOKIE 3 1 read-write DOWNIE DOWNIE 6 1 read-write EXTTRIGIE EXTTRIGIE 2 1 read-write UPIE UPIE 5 1 read-write LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 read-only ARROK ARROK 4 1 read-only CMPM CMPM 0 1 read-only CMPOK CMPOK 3 1 read-only DOWN DOWN 6 1 read-only EXTTRIG EXTTRIG 2 1 read-only UP UP 5 1 read-only LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 read-only LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 read-only LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only LPTIM2 LPTIM1 LPTIMER 0x0 0x0 0x400 registers n LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 read-write LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 read-write CKPOL CKPOL 1 2 read-write CKSEL CKSEL 0 1 read-write COUNTMODE COUNTMODE 23 1 read-write ENC ENC 24 1 read-write PRELOAD PRELOAD 22 1 read-write PRESC PRESC 9 3 read-write TIMOUT TIMOUT 19 1 read-write TRGFLT TRGFLT 6 2 read-write TRIGEN TRIGEN 17 2 read-write TRIGSEL TRIGSEL 13 3 read-write WAVE WAVE 20 1 read-write WAVPOL WAVPOL 21 1 read-write LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 read-write IN2SEL IN2SEL 4 2 read-write LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 read-write LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 read-only LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 read-write COUNTRST COUNTRST 3 1 read-write ENABLE ENABLE 0 1 read-write RSTARE RSTARE 4 1 write-only SNGSTRT SNGSTRT 1 1 read-write LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 read-write n 0x0 0x0 ARRMCF ARRMCF 1 1 write-only ARROKCF ARROKCF 4 1 write-only CMPMCF CMPMCF 0 1 write-only CMPOKCF CMPOKCF 3 1 write-only DOWNCF DOWNCF 6 1 write-only EXTTRIGCF EXTTRIGCF 2 1 write-only UPCF UPCF 5 1 write-only LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 read-write ARROKIE ARROKIE 4 1 read-write CMPMIE CMPMIE 0 1 read-write CMPOKIE CMPOKIE 3 1 read-write DOWNIE DOWNIE 6 1 read-write EXTTRIGIE EXTTRIGIE 2 1 read-write UPIE UPIE 5 1 read-write LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 read-only ARROK ARROK 4 1 read-only CMPM CMPM 0 1 read-only CMPOK CMPOK 3 1 read-only DOWN DOWN 6 1 read-only EXTTRIG EXTTRIG 2 1 read-only UP UP 5 1 read-only LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 read-only LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 read-only LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only LPTIM3 LPTIM1 LPTIMER 0x0 0x0 0x400 registers n LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 read-write LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 read-write CKPOL CKPOL 1 2 read-write CKSEL CKSEL 0 1 read-write COUNTMODE COUNTMODE 23 1 read-write ENC ENC 24 1 read-write PRELOAD PRELOAD 22 1 read-write PRESC PRESC 9 3 read-write TIMOUT TIMOUT 19 1 read-write TRGFLT TRGFLT 6 2 read-write TRIGEN TRIGEN 17 2 read-write TRIGSEL TRIGSEL 13 3 read-write WAVE WAVE 20 1 read-write WAVPOL WAVPOL 21 1 read-write LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 read-write IN2SEL IN2SEL 4 2 read-write LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 read-write LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 read-only LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 read-write COUNTRST COUNTRST 3 1 read-write ENABLE ENABLE 0 1 read-write RSTARE RSTARE 4 1 write-only SNGSTRT SNGSTRT 1 1 read-write LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 read-write n 0x0 0x0 ARRMCF ARRMCF 1 1 write-only ARROKCF ARROKCF 4 1 write-only CMPMCF CMPMCF 0 1 write-only CMPOKCF CMPOKCF 3 1 write-only DOWNCF DOWNCF 6 1 write-only EXTTRIGCF EXTTRIGCF 2 1 write-only UPCF UPCF 5 1 write-only LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 read-write ARROKIE ARROKIE 4 1 read-write CMPMIE CMPMIE 0 1 read-write CMPOKIE CMPOKIE 3 1 read-write DOWNIE DOWNIE 6 1 read-write EXTTRIGIE EXTTRIGIE 2 1 read-write UPIE UPIE 5 1 read-write LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 read-only ARROK ARROK 4 1 read-only CMPM CMPM 0 1 read-only CMPOK CMPOK 3 1 read-only DOWN DOWN 6 1 read-only EXTTRIG EXTTRIG 2 1 read-only UP UP 5 1 read-only LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 read-only LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 read-only LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only LPTIM4 LPTIM1 LPTIMER 0x0 0x0 0x400 registers n LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 read-write LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 read-write CKPOL CKPOL 1 2 read-write CKSEL CKSEL 0 1 read-write COUNTMODE COUNTMODE 23 1 read-write ENC ENC 24 1 read-write PRELOAD PRELOAD 22 1 read-write PRESC PRESC 9 3 read-write TIMOUT TIMOUT 19 1 read-write TRGFLT TRGFLT 6 2 read-write TRIGEN TRIGEN 17 2 read-write TRIGSEL TRIGSEL 13 3 read-write WAVE WAVE 20 1 read-write WAVPOL WAVPOL 21 1 read-write LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 read-write IN2SEL IN2SEL 4 2 read-write LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 read-write LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 read-only LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 read-write COUNTRST COUNTRST 3 1 read-write ENABLE ENABLE 0 1 read-write RSTARE RSTARE 4 1 write-only SNGSTRT SNGSTRT 1 1 read-write LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 read-write n 0x0 0x0 ARRMCF ARRMCF 1 1 write-only ARROKCF ARROKCF 4 1 write-only CMPMCF CMPMCF 0 1 write-only CMPOKCF CMPOKCF 3 1 write-only DOWNCF DOWNCF 6 1 write-only EXTTRIGCF EXTTRIGCF 2 1 write-only UPCF UPCF 5 1 write-only LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 read-write ARROKIE ARROKIE 4 1 read-write CMPMIE CMPMIE 0 1 read-write CMPOKIE CMPOKIE 3 1 read-write DOWNIE DOWNIE 6 1 read-write EXTTRIGIE EXTTRIGIE 2 1 read-write UPIE UPIE 5 1 read-write LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 read-only ARROK ARROK 4 1 read-only CMPM CMPM 0 1 read-only CMPOK CMPOK 3 1 read-only DOWN DOWN 6 1 read-only EXTTRIG EXTTRIG 2 1 read-only UP UP 5 1 read-only LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 read-only LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 read-only LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only LPTIM5 LPTIM1 LPTIMER 0x0 0x0 0x400 registers n LPTIM_ARR LPTIM_ARR LPTIM autoreload register 0x18 32 read-write n 0x0 0x0 ARR ARR 0 16 read-write LPTIM_CFGR LPTIM_CFGR LPTIM configuration register 0xC 32 read-write n 0x0 0x0 CKFLT CKFLT 3 2 read-write CKPOL CKPOL 1 2 read-write CKSEL CKSEL 0 1 read-write COUNTMODE COUNTMODE 23 1 read-write ENC ENC 24 1 read-write PRELOAD PRELOAD 22 1 read-write PRESC PRESC 9 3 read-write TIMOUT TIMOUT 19 1 read-write TRGFLT TRGFLT 6 2 read-write TRIGEN TRIGEN 17 2 read-write TRIGSEL TRIGSEL 13 3 read-write WAVE WAVE 20 1 read-write WAVPOL WAVPOL 21 1 read-write LPTIM_CFGR2 LPTIM_CFGR2 LPTIM configuration register 2 0x24 32 read-write n 0x0 0x0 IN1SEL IN1SEL 0 2 read-write IN2SEL IN2SEL 4 2 read-write LPTIM_CMP LPTIM_CMP LPTIM compare register 0x14 32 read-write n 0x0 0x0 CMP CMP 0 16 read-write LPTIM_CNT LPTIM_CNT LPTIM counter register 0x1C 32 read-only n 0x0 0x0 CNT CNT 0 16 read-only LPTIM_CR LPTIM_CR LPTIM control register 0x10 32 read-write n 0x0 0x0 CNTSTRT CNTSTRT 2 1 read-write COUNTRST COUNTRST 3 1 read-write ENABLE ENABLE 0 1 read-write RSTARE RSTARE 4 1 write-only SNGSTRT SNGSTRT 1 1 read-write LPTIM_ICR LPTIM_ICR LPTIM interrupt clear register 0x4 32 read-write n 0x0 0x0 ARRMCF ARRMCF 1 1 write-only ARROKCF ARROKCF 4 1 write-only CMPMCF CMPMCF 0 1 write-only CMPOKCF CMPOKCF 3 1 write-only DOWNCF DOWNCF 6 1 write-only EXTTRIGCF EXTTRIGCF 2 1 write-only UPCF UPCF 5 1 write-only LPTIM_IER LPTIM_IER LPTIM interrupt enable register 0x8 32 read-write n 0x0 0x0 ARRMIE ARRMIE 1 1 read-write ARROKIE ARROKIE 4 1 read-write CMPMIE CMPMIE 0 1 read-write CMPOKIE CMPOKIE 3 1 read-write DOWNIE DOWNIE 6 1 read-write EXTTRIGIE EXTTRIGIE 2 1 read-write UPIE UPIE 5 1 read-write LPTIM_ISR LPTIM_ISR LPTIM interrupt and status register 0x0 32 read-only n 0x0 0x0 ARRM ARRM 1 1 read-only ARROK ARROK 4 1 read-only CMPM CMPM 0 1 read-only CMPOK CMPOK 3 1 read-only DOWN DOWN 6 1 read-only EXTTRIG EXTTRIG 2 1 read-only UP UP 5 1 read-only LPTIM_PIDR LPTIM_PIDR LPTIM peripheral type identification register 0x3F8 32 read-only n 0x0 0x0 P_ID P_ID 0 32 read-only LPTIM_SIDR LPTIM_SIDR LPTIM registers map size identification register 0x3FC 32 read-only n 0x0 0x0 S_ID S_ID 0 32 read-only LPTIM_VERR LPTIM_VERR LPTIM peripheral version identification register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only LTDC LCD-TFT Controller LTDC 0x0 0x0 0x1000 registers n AWCR LTDC_AWCR This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration. 0x10 32 read-write n 0x0 0x0 AAH AAH 0 12 read-write AAW AAW 16 12 read-write BCCR LTDC_BCCR This register defines the background color (RGB888). 0x2C 32 read-write n 0x0 0x0 BCBLUE BCBLUE 0 8 read-write BCGREEN BCGREEN 8 8 read-write BCRED BCRED 16 8 read-write BPCR LTDC_BPCR This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration. 0xC 32 read-write n 0x0 0x0 AHBP AHBP 16 12 read-write AVBP AVBP 0 12 read-write CDSR LTDC_CDSR This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high. 0x48 32 read-only n 0x0 0x0 HDES HDES 1 1 read-only HSYNCS HSYNCS 3 1 read-only VDES VDES 0 1 read-only VSYNCS VSYNCS 2 1 read-only CPSR LTDC_CPSR LTDC current position status register 0x44 32 read-only n 0x0 0x0 CXPOS CXPOS 16 16 read-only CYPOS CYPOS 0 16 read-only GC1R LTDC_GC1R LTDC global configuration 1 register 0x1C 32 read-only n 0x0 0x0 BBEN BBEN 23 1 read-only BCP BCP 22 1 read-only BMEN BMEN 31 1 read-only DT DT 14 2 read-only DWP DWP 28 1 read-only GCT GCT 17 3 read-only IPP IPP 26 1 read-only LNIP LNIP 24 1 read-only PRBEN PRBEN 12 1 read-only SHREN SHREN 21 1 read-only SPP SPP 27 1 read-only STREN STREN 29 1 read-only TP TP 25 1 read-only WBCH WBCH 0 4 read-only WGCH WGCH 4 4 read-only WRCH WRCH 8 4 read-only GC2R LTDC_GC2R LTDC global configuration 2 register 0x20 32 read-only n 0x0 0x0 BW BW 4 3 read-only DPAEN DPAEN 3 1 read-only DVAEN DVAEN 2 1 read-only EDCA EDCA 7 1 read-only EDCEN EDCEN 0 1 read-only STSAEN STSAEN 1 1 read-only GCR LTDC_GCR This register defines the global configuration of the LCD-TFT controller. 0x18 32 read-write n 0x0 0x0 DBW DBW 4 3 read-only DEN DEN 16 1 read-write DEPOL DEPOL 29 1 read-write DGW DGW 8 3 read-only DRW DRW 12 3 read-only HSPOL HSPOL 31 1 read-write LTDCEN LTDCEN 0 1 read-write PCPOL PCPOL 28 1 read-write VSPOL VSPOL 30 1 read-write ICR LTDC_ICR LTDC Interrupt Clear Register 0x3C 32 read-write n 0x0 0x0 CFUIF CFUIF 1 1 write-only CLIF CLIF 0 1 write-only CRRIF CRRIF 3 1 write-only CTERRIF CTERRIF 2 1 write-only IDR LTDC_IDR LTDC identification register 0x0 32 read-only n 0x0 0x0 MAJVER MAJVER 16 8 read-only MINVER MINVER 8 8 read-only REV REV 0 8 read-only IER LTDC_IER This register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x34 32 read-write n 0x0 0x0 FUIE FUIE 1 1 read-write LIE LIE 0 1 read-write RRIE RRIE 3 1 read-write TERRIE TERRIE 2 1 read-write ISR LTDC_ISR This register returns the interrupt status flag. 0x38 32 read-only n 0x0 0x0 FUIF FUIF 1 1 read-only LIF LIF 0 1 read-only RRIF RRIF 3 1 read-only TERRIF TERRIF 2 1 read-only L1BFCR LTDC_L1BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0xA0 32 read-write n 0x0 0x0 BF1 BF1 8 3 read-write BF2 BF2 0 3 read-write L1CACR LTDC_L1CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x98 32 read-write n 0x0 0x0 CONSTA CONSTA 0 8 read-write L1CFBAR LTDC_L1CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0xAC 32 read-write n 0x0 0x0 CFBADD CFBADD 0 32 read-write L1CFBLNR LTDC_L1CFBLNR This register defines the number of lines in the color frame buffer. 0xB4 32 read-write n 0x0 0x0 CFBLNBR CFBLNBR 0 12 read-write L1CFBLR LTDC_L1CFBLR This register defines the color frame buffer line length and pitch. 0xB0 32 read-write n 0x0 0x0 CFBLL CFBLL 0 14 read-write CFBP CFBP 16 14 read-write L1CKCR LTDC_L1CKCR This register defines the color key value (RGB), that is used by the color keying. 0x90 32 read-write n 0x0 0x0 CKBLUE CKBLUE 0 8 read-write CKGREEN CKGREEN 8 8 read-write CKRED CKRED 16 8 read-write L1CLUTWR LTDC_L1CLUTWR This register defines the CLUT address and the RGB value. 0xC4 32 write-only n 0x0 0x0 BLUE BLUE 0 8 write-only CLUTADD CLUTADD 24 8 write-only GREEN GREEN 8 8 write-only RED RED 16 8 write-only L1CR LTDC_L1CR LTDC layer 1 control register 0x84 32 read-write n 0x0 0x0 CLUTEN CLUTEN 4 1 read-write COLKEN COLKEN 1 1 read-write LEN LEN 0 1 read-write L1DCCR LTDC_L1DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x9C 32 read-write n 0x0 0x0 DCALPHA DCALPHA 24 8 read-write DCBLUE DCBLUE 0 8 read-write DCGREEN DCGREEN 8 8 read-write DCRED DCRED 16 8 read-write L1PFCR LTDC_L1PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x94 32 read-write n 0x0 0x0 PF PF 0 3 read-write L1WHPCR LTDC_L1WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register. 0x88 32 read-write n 0x0 0x0 WHSPPOS WHSPPOS 16 12 read-write WHSTPOS WHSTPOS 0 12 read-write L1WVPCR LTDC_L1WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x8C 32 read-write n 0x0 0x0 WVSPPOS WVSPPOS 16 12 read-write WVSTPOS WVSTPOS 0 12 read-write L2BFCR LTDC_L2BFCR This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color 0x120 32 read-write n 0x0 0x0 BF1 BF1 8 3 read-write BF2 BF2 0 3 read-write L2CACR LTDC_L2CACR This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register. 0x118 32 read-write n 0x0 0x0 CONSTA CONSTA 0 8 read-write L2CFBAR LTDC_L2CFBAR This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer. 0x12C 32 read-write n 0x0 0x0 CFBADD CFBADD 0 32 read-write L2CFBLNR LTDC_L2CFBLNR This register defines the number of lines in the color frame buffer. 0x134 32 read-write n 0x0 0x0 CFBLNBR CFBLNBR 0 12 read-write L2CFBLR LTDC_L2CFBLR This register defines the color frame buffer line length and pitch. 0x130 32 read-write n 0x0 0x0 CFBLL CFBLL 0 14 read-write CFBP CFBP 16 14 read-write L2CKCR LTDC_L2CKCR This register defines the color key value (RGB), that is used by the color keying. 0x110 32 read-write n 0x0 0x0 CKBLUE CKBLUE 0 8 read-write CKGREEN CKGREEN 8 8 read-write CKRED CKRED 16 8 read-write L2CLUTWR LTDC_L2CLUTWR This register defines the CLUT address and the RGB value. 0x144 32 write-only n 0x0 0x0 BLUE BLUE 0 8 write-only CLUTADD CLUTADD 24 8 write-only GREEN GREEN 8 8 write-only RED RED 16 8 write-only L2CR LTDC_L2CR LTDC layer 2 control register 0x104 32 read-write n 0x0 0x0 CLUTEN CLUTEN 4 1 read-write COLKEN COLKEN 1 1 read-write LEN LEN 0 1 read-write L2DCCR LTDC_L2DCCR This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color. 0x11C 32 read-write n 0x0 0x0 DCALPHA DCALPHA 24 8 read-write DCBLUE DCBLUE 0 8 read-write DCGREEN DCGREEN 8 8 read-write DCRED DCRED 16 8 read-write L2PFCR LTDC_L2PFCR This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB). 0x114 32 read-write n 0x0 0x0 PF PF 0 3 read-write L2WHPCR LTDC_L2WHPCR This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[10:0] bits in the LTDC_AWCR register. 0x108 32 read-write n 0x0 0x0 WHSPPOS WHSPPOS 16 12 read-write WHSTPOS WHSTPOS 0 12 read-write L2WVPCR LTDC_L2WVPCR This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register. 0x10C 32 read-write n 0x0 0x0 WVSPPOS WVSPPOS 16 12 read-write WVSTPOS WVSTPOS 0 12 read-write LCR LTDC_LCR LDTC layer count register 0x4 32 read-only n 0x0 0x0 LNBR LNBR 0 8 read-only LIPCR LTDC_LIPCR This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure120. 0x40 32 read-write n 0x0 0x0 LIPOS LIPOS 0 12 read-write SRCR LTDC_SRCR This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR. 0x24 32 read-write n 0x0 0x0 IMR IMR 0 1 read-write VBR VBR 1 1 read-write SSCR LTDC_SSCR This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration. 0x8 32 read-write n 0x0 0x0 HSW HSW 16 12 read-write VSH VSH 0 12 read-write TWCR LTDC_TWCR This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure120 and Section19.4: LTDC programmable parameters for an example of configuration. 0x14 32 read-write n 0x0 0x0 TOTALH TOTALH 0 12 read-write TOTALW TOTALW 16 12 read-write MDIOS MDIOS MDIOS 0x0 0x0 0x400 registers n CLRFR MDIOS_CLRFR MDIOS clear flag register 0x18 32 read-write n 0x0 0x0 CPERF CPERF 0 1 read-write CSERF CSERF 1 1 read-write CTERF CTERF 2 1 read-write CR MDIOS_CR MDIOS configuration register 0x0 32 read-write n 0x0 0x0 DPC DPC 7 1 read-write EIE EIE 3 1 read-write EN EN 0 1 read-write PORT_ADDRESS PORT_ADDRESS 8 5 read-write RDIE RDIE 2 1 read-write WRIE WRIE 1 1 read-write CRDFR MDIOS_CRDFR MDIOS clear read flag register 0x10 32 read-write n 0x0 0x0 CRDF CRDF 0 32 read-write CWRFR MDIOS_CWRFR MDIOS clear write flag register 0x8 32 read-write n 0x0 0x0 CWRF CWRF 0 32 read-write DINR0 MDIOS_DINR0 MDIOS input data register 0x100 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR1 MDIOS_DINR1 MDIOS input data register 0x104 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR10 MDIOS_DINR10 MDIOS input data register 0x128 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR11 MDIOS_DINR11 MDIOS input data register 0x12C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR12 MDIOS_DINR12 MDIOS input data register 0x130 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR13 MDIOS_DINR13 MDIOS input data register 0x134 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR14 MDIOS_DINR14 MDIOS input data register 0x138 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR15 MDIOS_DINR15 MDIOS input data register 0x13C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR16 MDIOS_DINR16 MDIOS input data register 0x140 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR17 MDIOS_DINR17 MDIOS input data register 0x144 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR18 MDIOS_DINR18 MDIOS input data register 0x148 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR19 MDIOS_DINR19 MDIOS input data register 0x14C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR2 MDIOS_DINR2 MDIOS input data register 0x108 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR20 MDIOS_DINR20 MDIOS input data register 0x150 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR21 MDIOS_DINR21 MDIOS input data register 0x154 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR22 MDIOS_DINR22 MDIOS input data register 0x158 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR23 MDIOS_DINR23 MDIOS input data register 0x15C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR24 MDIOS_DINR24 MDIOS input data register 0x160 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR25 MDIOS_DINR25 MDIOS input data register 0x164 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR26 MDIOS_DINR26 MDIOS input data register 0x168 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR27 MDIOS_DINR27 MDIOS input data register 0x16C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR28 MDIOS_DINR28 MDIOS input data register 0x170 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR29 MDIOS_DINR29 MDIOS input data register 0x174 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR3 MDIOS_DINR3 MDIOS input data register 0x10C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR30 MDIOS_DINR30 MDIOS input data register 0x178 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR31 MDIOS_DINR31 MDIOS input data register 0x17C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR4 MDIOS_DINR4 MDIOS input data register 0x110 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR5 MDIOS_DINR5 MDIOS input data register 0x114 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR6 MDIOS_DINR6 MDIOS input data register 0x118 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR7 MDIOS_DINR7 MDIOS input data register 0x11C 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR8 MDIOS_DINR8 MDIOS input data register 0x120 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DINR9 MDIOS_DINR9 MDIOS input data register 0x124 32 read-only n 0x0 0x0 DIN DIN 0 16 read-only DOUTR0 MDIOS_DOUTR0 MDIOS input data register 0x180 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR1 MDIOS_DOUTR1 MDIOS input data register 0x184 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR10 MDIOS_DOUTR10 MDIOS output data register 0x1A8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR11 MDIOS_DOUTR11 MDIOS output data register 0x1AC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR12 MDIOS_DOUTR12 MDIOS output data register 0x1B0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR13 MDIOS_DOUTR13 MDIOS output data register 0x1B4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR14 MDIOS_DOUTR14 MDIOS output data register 0x1B8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR15 MDIOS_DOUTR15 MDIOS output data register 0x1BC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR16 MDIOS_DOUTR16 MDIOS output data register 0x1C0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR17 MDIOS_DOUTR17 MDIOS output data register 0x1C4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR18 MDIOS_DOUTR18 MDIOS output data register 0x1C8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR19 MDIOS_DOUTR19 MDIOS output data register 0x1CC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR2 MDIOS_DOUTR2 MDIOS output data register 0x188 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR20 MDIOS_DOUTR20 MDIOS output data register 0x1D0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR21 MDIOS_DOUTR21 MDIOS output data register 0x1D4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR22 MDIOS_DOUTR22 MDIOS output data register 0x1D8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR23 MDIOS_DOUTR23 MDIOS output data register 0x1DC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR24 MDIOS_DOUTR24 MDIOS output data register 0x1E0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR25 MDIOS_DOUTR25 MDIOS output data register 0x1E4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR26 MDIOS_DOUTR26 MDIOS output data register 0x1E8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR27 MDIOS_DOUTR27 MDIOS output data register 0x1EC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR28 MDIOS_DOUTR28 MDIOS output data register 0x1F0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR29 MDIOS_DOUTR29 MDIOS output data register 0x1F4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR3 MDIOS_DOUTR3 MDIOS output data register 0x18C 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR30 MDIOS_DOUTR30 MDIOS output data register 0x1F8 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR31 MDIOS_DOUTR31 MDIOS output data register 0x1FC 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR4 MDIOS_DOUTR4 MDIOS output data register 0x190 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR5 MDIOS_DOUTR5 MDIOS output data register 0x194 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR6 MDIOS_DOUTR6 MDIOS output data register 0x198 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR7 MDIOS_DOUTR7 MDIOS output data register 0x19C 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR8 MDIOS_DOUTR8 MDIOS output data register 0x1A0 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only DOUTR9 MDIOS_DOUTR9 MDIOS output data register 0x1A4 32 read-only n 0x0 0x0 DOUT DOUT 0 16 read-only HWCFGR MDIOS_HWCFGR MDIOS HW configuration register 0x3F0 32 read-only n 0x0 0x0 NBREG NBREG 0 8 read-only IPIDR MDIOS_IPIDR MDIOS identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only RDFR MDIOS_RDFR MDIOS read flag register 0xC 32 read-only n 0x0 0x0 RDF RDF 0 32 read-only SIDR MDIOS_SIDR MDIOS size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SR MDIOS_SR MDIOS status register 0x14 32 read-only n 0x0 0x0 PERF PERF 0 1 read-only SERF SERF 1 1 read-only TERF TERF 2 1 read-only VERR MDIOS_VERR MDIOS version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only WRFR MDIOS_WRFR MDIOS write flag register 0x4 32 read-only n 0x0 0x0 WRF WRF 0 32 read-only MDMA MDMA MDMA 0x0 0x0 0x1000 registers n C0BNDTR MDMA_C0BNDTR MDMA Channel 0 block number of data register 0x54 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C0BRUR MDMA_C0BRUR MDMA channel 0 Block Repeat address Update register 0x60 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C0CR MDMA_C0CR This register is used to control the concerned channel. 0x4C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C0DAR MDMA_C0DAR MDMA channel 0 destination address register 0x5C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C0ESR MDMA_C0ESR MDMA Channel 0 error status register 0x48 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C0IFCR MDMA_C0IFCR MDMA channel 0 interrupt flag clear register 0x44 32 read-write n 0x0 0x0 CBRTIF0 CBRTIF0 2 1 write-only CBTIF0 CBTIF0 3 1 write-only CCTCIF0 CCTCIF0 1 1 write-only CLTCIF0 CLTCIF0 4 1 write-only CTEIF0 CTEIF0 0 1 write-only C0ISR MDMA_C0ISR MDMA channel 0 interrupt/status register 0x40 32 read-only n 0x0 0x0 BRTIF0 BRTIF0 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF0 BTIF0 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA0 CRQA0 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF0 CTCIF0 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF0 TCIF0 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF0 TEIF0 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C0LAR MDMA_C0LAR MDMA channel 0 Link Address register 0x64 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C0MAR MDMA_C0MAR MDMA channel 0 Mask address register 0x70 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C0MDR MDMA_C0MDR MDMA channel 0 Mask Data register 0x74 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C0SAR MDMA_C0SAR MDMA channel 0 source address register 0x58 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C0TBR MDMA_C0TBR MDMA channel 0 Trigger and Bus selection Register 0x68 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C0TCR MDMA_C0TCR This register is used to configure the concerned channel. 0x50 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C10BNDTR MDMA_C10BNDTR MDMA Channel 10 block number of data register 0x2D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C10BRUR MDMA_C10BRUR MDMA channel 10 Block Repeat address Update register 0x2E0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C10CR MDMA_C10CR This register is used to control the concerned channel. 0x2CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C10DAR MDMA_C10DAR MDMA channel 10 destination address register 0x2DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C10ESR MDMA_C10ESR MDMA Channel 10 error status register 0x2C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C10IFCR MDMA_C10IFCR MDMA channel 10 interrupt flag clear register 0x2C4 32 read-write n 0x0 0x0 CBRTIF10 CBRTIF10 2 1 write-only CBTIF10 CBTIF10 3 1 write-only CCTCIF10 CCTCIF10 1 1 write-only CLTCIF10 CLTCIF10 4 1 write-only CTEIF10 CTEIF10 0 1 write-only C10ISR MDMA_C10ISR MDMA channel 10 interrupt/status register 0x2C0 32 read-only n 0x0 0x0 BRTIF10 BRTIF10 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF10 BTIF10 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA10 CRQA10 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF10 CTCIF10 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF10 TCIF10 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF10 TEIF10 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C10LAR MDMA_C10LAR MDMA channel 10 Link Address register 0x2E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C10MAR MDMA_C10MAR MDMA channel 10 Mask address register 0x2F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C10MDR MDMA_C10MDR MDMA channel 10 Mask Data register 0x2F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C10SAR MDMA_C10SAR MDMA channel 10 source address register 0x2D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C10TBR MDMA_C10TBR MDMA channel 10 Trigger and Bus selection Register 0x2E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C10TCR MDMA_C10TCR This register is used to configure the concerned channel. 0x2D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C11BNDTR MDMA_C11BNDTR MDMA Channel 11 block number of data register 0x314 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C11BRUR MDMA_C11BRUR MDMA channel 11 Block Repeat address Update register 0x320 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C11CR MDMA_C11CR This register is used to control the concerned channel. 0x30C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C11DAR MDMA_C11DAR MDMA channel 11 destination address register 0x31C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C11ESR MDMA_C11ESR MDMA Channel 11 error status register 0x308 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C11IFCR MDMA_C11IFCR MDMA channel 11 interrupt flag clear register 0x304 32 read-write n 0x0 0x0 CBRTIF11 CBRTIF11 2 1 write-only CBTIF11 CBTIF11 3 1 write-only CCTCIF11 CCTCIF11 1 1 write-only CLTCIF11 CLTCIF11 4 1 write-only CTEIF11 CTEIF11 0 1 write-only C11ISR MDMA_C11ISR MDMA channel 11 interrupt/status register 0x300 32 read-only n 0x0 0x0 BRTIF11 BRTIF11 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF11 BTIF11 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA11 CRQA11 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF11 CTCIF11 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF11 TCIF11 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF11 TEIF11 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C11LAR MDMA_C11LAR MDMA channel 11 Link Address register 0x324 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C11MAR MDMA_C11MAR MDMA channel 11 Mask address register 0x330 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C11MDR MDMA_C11MDR MDMA channel 11 Mask Data register 0x334 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C11SAR MDMA_C11SAR MDMA channel 11 source address register 0x318 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C11TBR MDMA_C11TBR MDMA channel 11 Trigger and Bus selection Register 0x328 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C11TCR MDMA_C11TCR This register is used to configure the concerned channel. 0x310 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C12BNDTR MDMA_C12BNDTR MDMA Channel 12 block number of data register 0x354 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C12BRUR MDMA_C12BRUR MDMA channel 12 Block Repeat address Update register 0x360 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C12CR MDMA_C12CR This register is used to control the concerned channel. 0x34C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C12DAR MDMA_C12DAR MDMA channel 12 destination address register 0x35C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C12ESR MDMA_C12ESR MDMA Channel 12 error status register 0x348 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C12IFCR MDMA_C12IFCR MDMA channel 12 interrupt flag clear register 0x344 32 read-write n 0x0 0x0 CBRTIF12 CBRTIF12 2 1 write-only CBTIF12 CBTIF12 3 1 write-only CCTCIF12 CCTCIF12 1 1 write-only CLTCIF12 CLTCIF12 4 1 write-only CTEIF12 CTEIF12 0 1 write-only C12ISR MDMA_C12ISR MDMA channel 12 interrupt/status register 0x340 32 read-only n 0x0 0x0 BRTIF12 BRTIF12 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF12 BTIF12 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA12 CRQA12 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF12 CTCIF12 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF12 TCIF12 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF12 TEIF12 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C12LAR MDMA_C12LAR MDMA channel 12 Link Address register 0x364 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C12MAR MDMA_C12MAR MDMA channel 12 Mask address register 0x370 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C12MDR MDMA_C12MDR MDMA channel 12 Mask Data register 0x374 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C12SAR MDMA_C12SAR MDMA channel 12 source address register 0x358 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C12TBR MDMA_C12TBR MDMA channel 12 Trigger and Bus selection Register 0x368 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C12TCR MDMA_C12TCR This register is used to configure the concerned channel. 0x350 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C13BNDTR MDMA_C13BNDTR MDMA Channel 13 block number of data register 0x394 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C13BRUR MDMA_C13BRUR MDMA channel 13 Block Repeat address Update register 0x3A0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C13CR MDMA_C13CR This register is used to control the concerned channel. 0x38C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C13DAR MDMA_C13DAR MDMA channel 13 destination address register 0x39C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C13ESR MDMA_C13ESR MDMA Channel 13 error status register 0x388 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C13IFCR MDMA_C13IFCR MDMA channel 13 interrupt flag clear register 0x384 32 read-write n 0x0 0x0 CBRTIF13 CBRTIF13 2 1 write-only CBTIF13 CBTIF13 3 1 write-only CCTCIF13 CCTCIF13 1 1 write-only CLTCIF13 CLTCIF13 4 1 write-only CTEIF13 CTEIF13 0 1 write-only C13ISR MDMA_C13ISR MDMA channel 13 interrupt/status register 0x380 32 read-only n 0x0 0x0 BRTIF13 BRTIF13 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF13 BTIF13 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA13 CRQA13 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF13 CTCIF13 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF13 TCIF13 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF13 TEIF13 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C13LAR MDMA_C13LAR MDMA channel 13 Link Address register 0x3A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C13MAR MDMA_C13MAR MDMA channel 13 Mask address register 0x3B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C13MDR MDMA_C13MDR MDMA channel 13 Mask Data register 0x3B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C13SAR MDMA_C13SAR MDMA channel 13 source address register 0x398 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C13TBR MDMA_C13TBR MDMA channel 13 Trigger and Bus selection Register 0x3A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C13TCR MDMA_C13TCR This register is used to configure the concerned channel. 0x390 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C14BNDTR MDMA_C14BNDTR MDMA Channel 14 block number of data register 0x3D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C14BRUR MDMA_C14BRUR MDMA channel 14 Block Repeat address Update register 0x3E0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C14CR MDMA_C14CR This register is used to control the concerned channel. 0x3CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C14DAR MDMA_C14DAR MDMA channel 14 destination address register 0x3DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C14ESR MDMA_C14ESR MDMA Channel 14 error status register 0x3C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C14IFCR MDMA_C14IFCR MDMA channel 14 interrupt flag clear register 0x3C4 32 read-write n 0x0 0x0 CBRTIF14 CBRTIF14 2 1 write-only CBTIF14 CBTIF14 3 1 write-only CCTCIF14 CCTCIF14 1 1 write-only CLTCIF14 CLTCIF14 4 1 write-only CTEIF14 CTEIF14 0 1 write-only C14ISR MDMA_C14ISR MDMA channel 14 interrupt/status register 0x3C0 32 read-only n 0x0 0x0 BRTIF14 BRTIF14 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF14 BTIF14 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA14 CRQA14 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF14 CTCIF14 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF14 TCIF14 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF14 TEIF14 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C14LAR MDMA_C14LAR MDMA channel 14 Link Address register 0x3E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C14MAR MDMA_C14MAR MDMA channel 14 Mask address register 0x3F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C14MDR MDMA_C14MDR MDMA channel 14 Mask Data register 0x3F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C14SAR MDMA_C14SAR MDMA channel 14 source address register 0x3D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C14TBR MDMA_C14TBR MDMA channel 14 Trigger and Bus selection Register 0x3E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C14TCR MDMA_C14TCR This register is used to configure the concerned channel. 0x3D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C15BNDTR MDMA_C15BNDTR MDMA Channel 15 block number of data register 0x414 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C15BRUR MDMA_C15BRUR MDMA channel 15 Block Repeat address Update register 0x420 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C15CR MDMA_C15CR This register is used to control the concerned channel. 0x40C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C15DAR MDMA_C15DAR MDMA channel 15 destination address register 0x41C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C15ESR MDMA_C15ESR MDMA Channel 15 error status register 0x408 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C15IFCR MDMA_C15IFCR MDMA channel 15 interrupt flag clear register 0x404 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C15ISR MDMA_C15ISR MDMA channel 15 interrupt/status register 0x400 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C15LAR MDMA_C15LAR MDMA channel 15 Link Address register 0x424 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C15MAR MDMA_C15MAR MDMA channel 15 Mask address register 0x430 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C15MDR MDMA_C15MDR MDMA channel 15 Mask Data register 0x434 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C15SAR MDMA_C15SAR MDMA channel 15 source address register 0x418 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C15TBR MDMA_C15TBR MDMA channel 15 Trigger and Bus selection Register 0x428 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C15TCR MDMA_C15TCR This register is used to configure the concerned channel. 0x410 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C16BNDTR MDMA_C16BNDTR MDMA Channel block number of data register 0x454 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C16BRUR MDMA_C16BRUR MDMA channel Block Repeat address Update register 0x460 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C16CR MDMA_C16CR This register is used to control the concerned channel. 0x44C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C16DAR MDMA_C16DAR MDMA channel destination address register 0x45C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C16ESR MDMA_C16ESR MDMA Channel 16 error status register 0x448 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C16IFCR MDMA_C16IFCR MDMA channel 16 interrupt flag clear register 0x444 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C16ISR MDMA_C16ISR MDMA channel 16 interrupt/status register 0x440 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C16LAR MDMA_C16LAR MDMA channel Link Address register 0x464 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C16MAR MDMA_C16MAR MDMA channel Mask address register 0x470 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C16MDR MDMA_C16MDR MDMA channel Mask Data register 0x474 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C16SAR MDMA_C16SAR MDMA channel source address register 0x458 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C16TBR MDMA_C16TBR MDMA channel Trigger and Bus selection Register 0x468 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C16TCR MDMA_C16TCR This register is used to configure the concerned channel. 0x450 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C17BNDTR MDMA_C17BNDTR MDMA Channel block number of data register 0x494 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C17BRUR MDMA_C17BRUR MDMA channel Block Repeat address Update register 0x4A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C17CR MDMA_C17CR This register is used to control the concerned channel. 0x48C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C17DAR MDMA_C17DAR MDMA channel destination address register 0x49C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C17ESR MDMA_C17ESR MDMA Channel 17 error status register 0x488 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C17IFCR MDMA_C17IFCR MDMA channel 17 interrupt flag clear register 0x484 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C17ISR MDMA_C17ISR MDMA channel 17 interrupt/status register 0x480 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C17LAR MDMA_C17LAR MDMA channel Link Address register 0x4A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C17MAR MDMA_C17MAR MDMA channel Mask address register 0x4B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C17MDR MDMA_C17MDR MDMA channel Mask Data register 0x4B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C17SAR MDMA_C17SAR MDMA channel source address register 0x498 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C17TBR MDMA_C17TBR MDMA channel Trigger and Bus selection Register 0x4A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C17TCR MDMA_C17TCR This register is used to configure the concerned channel. 0x490 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C18BNDTR MDMA_C18BNDTR MDMA Channel block number of data register 0x4D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C18BRUR MDMA_C18BRUR MDMA channel Block Repeat address Update register 0x4E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C18CR MDMA_C18CR This register is used to control the concerned channel. 0x4CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C18DAR MDMA_C18DAR MDMA channel destination address register 0x4DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C18ESR MDMA_C18ESR MDMA Channel 18 error status register 0x4C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C18IFCR MDMA_C18IFCR MDMA channel 18 interrupt flag clear register 0x4C4 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C18ISR MDMA_C18ISR MDMA channel 18 interrupt/status register 0x4C0 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C18LAR MDMA_C18LAR MDMA channel Link Address register 0x4E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C18MAR MDMA_C18MAR MDMA channel Mask address register 0x4F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C18MDR MDMA_C18MDR MDMA channel Mask Data register 0x4F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C18SAR MDMA_C18SAR MDMA channel source address register 0x4D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C18TBR MDMA_C18TBR MDMA channel Trigger and Bus selection Register 0x4E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C18TCR MDMA_C18TCR This register is used to configure the concerned channel. 0x4D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C19BNDTR MDMA_C19BNDTR MDMA Channel block number of data register 0x514 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C19BRUR MDMA_C19BRUR MDMA channel Block Repeat address Update register 0x520 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C19CR MDMA_C19CR This register is used to control the concerned channel. 0x50C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C19DAR MDMA_C19DAR MDMA channel destination address register 0x51C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C19ESR MDMA_C19ESR MDMA Channel 19 error status register 0x508 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C19IFCR MDMA_C19IFCR MDMA channel 19 interrupt flag clear register 0x504 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C19ISR MDMA_C19ISR MDMA channel 19 interrupt/status register 0x500 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C19LAR MDMA_C19LAR MDMA channel Link Address register 0x524 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C19MAR MDMA_C19MAR MDMA channel Mask address register 0x530 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C19MDR MDMA_C19MDR MDMA channel Mask Data register 0x534 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C19SAR MDMA_C19SAR MDMA channel source address register 0x518 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C19TBR MDMA_C19TBR MDMA channel Trigger and Bus selection Register 0x528 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C19TCR MDMA_C19TCR This register is used to configure the concerned channel. 0x510 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C1BNDTR MDMA_C1BNDTR MDMA Channel 1 block number of data register 0x94 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C1BRUR MDMA_C1BRUR MDMA channel 1 Block Repeat address Update register 0xA0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C1CR MDMA_C1CR This register is used to control the concerned channel. 0x8C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C1DAR MDMA_C1DAR MDMA channel 1 destination address register 0x9C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C1ESR MDMA_C1ESR MDMA Channel 1 error status register 0x88 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C1IFCR MDMA_C1IFCR MDMA channel 1 interrupt flag clear register 0x84 32 read-write n 0x0 0x0 CBRTIF1 CBRTIF1 2 1 write-only CBTIF1 CBTIF1 3 1 write-only CCTCIF1 CCTCIF1 1 1 write-only CLTCIF1 CLTCIF1 4 1 write-only CTEIF1 CTEIF1 0 1 write-only C1ISR MDMA_C1ISR MDMA channel 1 interrupt/status register 0x80 32 read-only n 0x0 0x0 BRTIF1 BRTIF1 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF1 BTIF1 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA1 CRQA1 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF1 CTCIF1 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF1 TCIF1 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF1 TEIF1 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C1LAR MDMA_C1LAR MDMA channel 1 Link Address register 0xA4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C1MAR MDMA_C1MAR MDMA channel 1 Mask address register 0xB0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C1MDR MDMA_C1MDR MDMA channel 1 Mask Data register 0xB4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C1SAR MDMA_C1SAR MDMA channel 1 source address register 0x98 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C1TBR MDMA_C1TBR MDMA channel 1 Trigger and Bus selection Register 0xA8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C1TCR MDMA_C1TCR This register is used to configure the concerned channel. 0x90 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C20BNDTR MDMA_C20BNDTR MDMA Channel block number of data register 0x554 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C20BRUR MDMA_C20BRUR MDMA channel Block Repeat address Update register 0x560 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C20CR MDMA_C20CR This register is used to control the concerned channel. 0x54C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C20DAR MDMA_C20DAR MDMA channel destination address register 0x55C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C20ESR MDMA_C20ESR MDMA Channel 20 error status register 0x548 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C20IFCR MDMA_C20IFCR MDMA channel 20 interrupt flag clear register 0x544 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C20ISR MDMA_C20ISR MDMA channel 20 interrupt/status register 0x540 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C20LAR MDMA_C20LAR MDMA channel Link Address register 0x564 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C20MAR MDMA_C20MAR MDMA channel Mask address register 0x570 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C20MDR MDMA_C20MDR MDMA channel Mask Data register 0x574 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C20SAR MDMA_C20SAR MDMA channel source address register 0x558 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C20TBR MDMA_C20TBR MDMA channel Trigger and Bus selection Register 0x568 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C20TCR MDMA_C20TCR This register is used to configure the concerned channel. 0x550 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C21BNDTR MDMA_C21BNDTR MDMA Channel block number of data register 0x594 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C21BRUR MDMA_C21BRUR MDMA channel Block Repeat address Update register 0x5A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C21CR MDMA_C21CR This register is used to control the concerned channel. 0x58C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C21DAR MDMA_C21DAR MDMA channel destination address register 0x59C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C21ESR MDMA_C21ESR MDMA Channel 21 error status register 0x588 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C21IFCR MDMA_C21IFCR MDMA channel 21 interrupt flag clear register 0x584 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C21ISR MDMA_C21ISR MDMA channel 21 interrupt/status register 0x580 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C21LAR MDMA_C21LAR MDMA channel Link Address register 0x5A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C21MAR MDMA_C21MAR MDMA channel Mask address register 0x5B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C21MDR MDMA_C21MDR MDMA channel Mask Data register 0x5B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C21SAR MDMA_C21SAR MDMA channel source address register 0x598 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C21TBR MDMA_C21TBR MDMA channel Trigger and Bus selection Register 0x5A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C21TCR MDMA_C21TCR This register is used to configure the concerned channel. 0x590 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C22BNDTR MDMA_C22BNDTR MDMA Channel block number of data register 0x5D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C22BRUR MDMA_C22BRUR MDMA channel Block Repeat address Update register 0x5E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C22CR MDMA_C22CR This register is used to control the concerned channel. 0x5CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C22DAR MDMA_C22DAR MDMA channel destination address register 0x5DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C22ESR MDMA_C22ESR MDMA Channel 22 error status register 0x5C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C22IFCR MDMA_C22IFCR MDMA channel 22 interrupt flag clear register 0x5C4 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C22ISR MDMA_C22ISR MDMA channel 22 interrupt/status register 0x5C0 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C22LAR MDMA_C22LAR MDMA channel Link Address register 0x5E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C22MAR MDMA_C22MAR MDMA channel Mask address register 0x5F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C22MDR MDMA_C22MDR MDMA channel Mask Data register 0x5F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C22SAR MDMA_C22SAR MDMA channel source address register 0x5D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C22TBR MDMA_C22TBR MDMA channel Trigger and Bus selection Register 0x5E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C22TCR MDMA_C22TCR This register is used to configure the concerned channel. 0x5D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C23BNDTR MDMA_C23BNDTR MDMA Channel block number of data register 0x614 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C23BRUR MDMA_C23BRUR MDMA channel Block Repeat address Update register 0x620 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C23CR MDMA_C23CR This register is used to control the concerned channel. 0x60C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C23DAR MDMA_C23DAR MDMA channel destination address register 0x61C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C23ESR MDMA_C23ESR MDMA Channel 23 error status register 0x608 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C23IFCR MDMA_C23IFCR MDMA channel 23 interrupt flag clear register 0x604 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C23ISR MDMA_C23ISR MDMA channel 23 interrupt/status register 0x600 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C23LAR MDMA_C23LAR MDMA channel Link Address register 0x624 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C23MAR MDMA_C23MAR MDMA channel Mask address register 0x630 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C23MDR MDMA_C23MDR MDMA channel Mask Data register 0x634 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C23SAR MDMA_C23SAR MDMA channel source address register 0x618 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C23TBR MDMA_C23TBR MDMA channel Trigger and Bus selection Register 0x628 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C23TCR MDMA_C23TCR This register is used to configure the concerned channel. 0x610 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C24BNDTR MDMA_C24BNDTR MDMA Channel block number of data register 0x654 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C24BRUR MDMA_C24BRUR MDMA channel Block Repeat address Update register 0x660 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C24CR MDMA_C24CR This register is used to control the concerned channel. 0x64C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C24DAR MDMA_C24DAR MDMA channel destination address register 0x65C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C24ESR MDMA_C24ESR MDMA Channel 24 error status register 0x648 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C24IFCR MDMA_C24IFCR MDMA channel 24 interrupt flag clear register 0x644 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C24ISR MDMA_C24ISR MDMA channel 24 interrupt/status register 0x640 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C24LAR MDMA_C24LAR MDMA channel Link Address register 0x664 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C24MAR MDMA_C24MAR MDMA channel Mask address register 0x670 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C24MDR MDMA_C24MDR MDMA channel Mask Data register 0x674 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C24SAR MDMA_C24SAR MDMA channel source address register 0x658 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C24TBR MDMA_C24TBR MDMA channel Trigger and Bus selection Register 0x668 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C24TCR MDMA_C24TCR This register is used to configure the concerned channel. 0x650 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C25BNDTR MDMA_C25BNDTR MDMA Channel block number of data register 0x694 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C25BRUR MDMA_C25BRUR MDMA channel Block Repeat address Update register 0x6A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C25CR MDMA_C25CR This register is used to control the concerned channel. 0x68C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C25DAR MDMA_C25DAR MDMA channel destination address register 0x69C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C25ESR MDMA_C25ESR MDMA Channel 25 error status register 0x688 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C25IFCR MDMA_C25IFCR MDMA channel 25 interrupt flag clear register 0x684 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C25ISR MDMA_C25ISR MDMA channel 25 interrupt/status register 0x680 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C25LAR MDMA_C25LAR MDMA channel Link Address register 0x6A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C25MAR MDMA_C25MAR MDMA channel Mask address register 0x6B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C25MDR MDMA_C25MDR MDMA channel Mask Data register 0x6B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C25SAR MDMA_C25SAR MDMA channel source address register 0x698 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C25TBR MDMA_C25TBR MDMA channel Trigger and Bus selection Register 0x6A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C25TCR MDMA_C25TCR This register is used to configure the concerned channel. 0x690 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C26BNDTR MDMA_C26BNDTR MDMA Channel block number of data register 0x6D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C26BRUR MDMA_C26BRUR MDMA channel Block Repeat address Update register 0x6E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C26CR MDMA_C26CR This register is used to control the concerned channel. 0x6CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C26DAR MDMA_C26DAR MDMA channel destination address register 0x6DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C26ESR MDMA_C26ESR MDMA Channel 26 error status register 0x6C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C26IFCR MDMA_C26IFCR MDMA channel 26 interrupt flag clear register 0x6C4 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C26ISR MDMA_C26ISR MDMA channel 26 interrupt/status register 0x6C0 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C26LAR MDMA_C26LAR MDMA channel Link Address register 0x6E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C26MAR MDMA_C26MAR MDMA channel Mask address register 0x6F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C26MDR MDMA_C26MDR MDMA channel Mask Data register 0x6F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C26SAR MDMA_C26SAR MDMA channel source address register 0x6D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C26TBR MDMA_C26TBR MDMA channel Trigger and Bus selection Register 0x6E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C26TCR MDMA_C26TCR This register is used to configure the concerned channel. 0x6D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C27BNDTR MDMA_C27BNDTR MDMA Channel block number of data register 0x714 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C27BRUR MDMA_C27BRUR MDMA channel Block Repeat address Update register 0x720 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C27CR MDMA_C27CR This register is used to control the concerned channel. 0x70C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C27DAR MDMA_C27DAR MDMA channel destination address register 0x71C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C27ESR MDMA_C27ESR MDMA Channel 27 error status register 0x708 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C27IFCR MDMA_C27IFCR MDMA channel 27 interrupt flag clear register 0x704 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C27ISR MDMA_C27ISR MDMA channel 27 interrupt/status register 0x700 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C27LAR MDMA_C27LAR MDMA channel Link Address register 0x724 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C27MAR MDMA_C27MAR MDMA channel Mask address register 0x730 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C27MDR MDMA_C27MDR MDMA channel Mask Data register 0x734 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C27SAR MDMA_C27SAR MDMA channel source address register 0x718 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C27TBR MDMA_C27TBR MDMA channel Trigger and Bus selection Register 0x728 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C27TCR MDMA_C27TCR This register is used to configure the concerned channel. 0x710 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C28BNDTR MDMA_C28BNDTR MDMA Channel block number of data register 0x754 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C28BRUR MDMA_C28BRUR MDMA channel Block Repeat address Update register 0x760 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C28CR MDMA_C28CR This register is used to control the concerned channel. 0x74C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C28DAR MDMA_C28DAR MDMA channel destination address register 0x75C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C28ESR MDMA_C28ESR MDMA Channel 28 error status register 0x748 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C28IFCR MDMA_C28IFCR MDMA channel 28 interrupt flag clear register 0x744 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C28ISR MDMA_C28ISR MDMA channel 28 interrupt/status register 0x740 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C28LAR MDMA_C28LAR MDMA channel Link Address register 0x764 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C28MAR MDMA_C28MAR MDMA channel Mask address register 0x770 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C28MDR MDMA_C28MDR MDMA channel Mask Data register 0x774 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C28SAR MDMA_C28SAR MDMA channel source address register 0x758 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C28TBR MDMA_C28TBR MDMA channel Trigger and Bus selection Register 0x768 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C28TCR MDMA_C28TCR This register is used to configure the concerned channel. 0x750 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C29BNDTR MDMA_C29BNDTR MDMA Channel block number of data register 0x794 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C29BRUR MDMA_C29BRUR MDMA channel Block Repeat address Update register 0x7A0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C29CR MDMA_C29CR This register is used to control the concerned channel. 0x78C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C29DAR MDMA_C29DAR MDMA channel destination address register 0x79C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C29ESR MDMA_C29ESR MDMA Channel 29 error status register 0x788 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C29IFCR MDMA_C29IFCR MDMA channel 29 interrupt flag clear register 0x784 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C29ISR MDMA_C29ISR MDMA channel 29 interrupt/status register 0x780 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C29LAR MDMA_C29LAR MDMA channel Link Address register 0x7A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C29MAR MDMA_C29MAR MDMA channel Mask address register 0x7B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C29MDR MDMA_C29MDR MDMA channel Mask Data register 0x7B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C29SAR MDMA_C29SAR MDMA channel source address register 0x798 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C29TBR MDMA_C29TBR MDMA channel Trigger and Bus selection Register 0x7A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C29TCR MDMA_C29TCR This register is used to configure the concerned channel. 0x790 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C2BNDTR MDMA_C2BNDTR MDMA Channel 2 block number of data register 0xD4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C2BRUR MDMA_C2BRUR MDMA channel 2 Block Repeat address Update register 0xE0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C2CR MDMA_C2CR This register is used to control the concerned channel. 0xCC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C2DAR MDMA_C2DAR MDMA channel 2 destination address register 0xDC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C2ESR MDMA_C2ESR MDMA Channel 2 error status register 0xC8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C2IFCR MDMA_C2IFCR MDMA channel 2 interrupt flag clear register 0xC4 32 read-write n 0x0 0x0 CBRTIF2 CBRTIF2 2 1 write-only CBTIF2 CBTIF2 3 1 write-only CCTCIF2 CCTCIF2 1 1 write-only CLTCIF2 CLTCIF2 4 1 write-only CTEIF2 CTEIF2 0 1 write-only C2ISR MDMA_C2ISR MDMA channel 2 interrupt/status register 0xC0 32 read-only n 0x0 0x0 BRTIF2 BRTIF2 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF2 BTIF2 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA2 CRQA2 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF2 CTCIF2 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF2 TCIF2 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF2 TEIF2 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C2LAR MDMA_C2LAR MDMA channel 2 Link Address register 0xE4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C2MAR MDMA_C2MAR MDMA channel 2 Mask address register 0xF0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C2MDR MDMA_C2MDR MDMA channel 2 Mask Data register 0xF4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C2SAR MDMA_C2SAR MDMA channel 2 source address register 0xD8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C2TBR MDMA_C2TBR MDMA channel 2 Trigger and Bus selection Register 0xE8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C2TCR MDMA_C2TCR This register is used to configure the concerned channel. 0xD0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C30BNDTR MDMA_C30BNDTR MDMA Channel block number of data register 0x7D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C30BRUR MDMA_C30BRUR MDMA channel Block Repeat address Update register 0x7E0 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C30CR MDMA_C30CR This register is used to control the concerned channel. 0x7CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C30DAR MDMA_C30DAR MDMA channel destination address register 0x7DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C30ESR MDMA_C30ESR MDMA Channel 30 error status register 0x7C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C30IFCR MDMA_C30IFCR MDMA channel 30 interrupt flag clear register 0x7C4 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C30ISR MDMA_C30ISR MDMA channel 30 interrupt/status register 0x7C0 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C30LAR MDMA_C30LAR MDMA channel Link Address register 0x7E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C30MAR MDMA_C30MAR MDMA channel Mask address register 0x7F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C30MDR MDMA_C30MDR MDMA channel Mask Data register 0x7F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C30SAR MDMA_C30SAR MDMA channel source address register 0x7D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C30TBR MDMA_C30TBR MDMA channel Trigger and Bus selection Register 0x7E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C30TCR MDMA_C30TCR This register is used to configure the concerned channel. 0x7D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C31BNDTR MDMA_C31BNDTR MDMA Channel block number of data register 0x814 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C31BRUR MDMA_C31BRUR MDMA channel Block Repeat address Update register 0x820 32 read-write n 0x0 0x0 DUV DUV 16 16 SUV SUV 0 16 C31CR MDMA_C31CR This register is used to control the concerned channel. 0x80C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C31DAR MDMA_C31DAR MDMA channel destination address register 0x81C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C31ESR MDMA_C31ESR MDMA Channel 31 error status register 0x808 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C31IFCR MDMA_C31IFCR MDMA channel 31 interrupt flag clear register 0x804 32 read-write n 0x0 0x0 CBRTIF15 CBRTIF15 2 1 write-only CBTIF15 CBTIF15 3 1 write-only CCTCIF15 CCTCIF15 1 1 write-only CLTCIF15 CLTCIF15 4 1 write-only CTEIF15 CTEIF15 0 1 write-only C31ISR MDMA_C31ISR MDMA channel 31 interrupt/status register 0x800 32 read-only n 0x0 0x0 BRTIF15 BRTIF15 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF15 BTIF15 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA15 CRQA15 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF15 CTCIF15 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF15 TCIF15 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF15 TEIF15 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C31LAR MDMA_C31LAR MDMA channel Link Address register 0x824 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C31MAR MDMA_C31MAR MDMA channel Mask address register 0x830 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C31MDR MDMA_C31MDR MDMA channel Mask Data register 0x834 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C31SAR MDMA_C31SAR MDMA channel source address register 0x818 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C31TBR MDMA_C31TBR MDMA channel Trigger and Bus selection Register 0x828 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C31TCR MDMA_C31TCR This register is used to configure the concerned channel. 0x810 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C3BNDTR MDMA_C3BNDTR MDMA Channel 3 block number of data register 0x114 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C3BRUR MDMA_C3BRUR MDMA channel 3 Block Repeat address Update register 0x120 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C3CR MDMA_C3CR This register is used to control the concerned channel. 0x10C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C3DAR MDMA_C3DAR MDMA channel 3 destination address register 0x11C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C3ESR MDMA_C3ESR MDMA Channel 3 error status register 0x108 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C3IFCR MDMA_C3IFCR MDMA channel 3 interrupt flag clear register 0x104 32 read-write n 0x0 0x0 CBRTIF3 CBRTIF3 2 1 write-only CBTIF3 CBTIF3 3 1 write-only CCTCIF3 CCTCIF3 1 1 write-only CLTCIF3 CLTCIF3 4 1 write-only CTEIF3 CTEIF3 0 1 write-only C3ISR MDMA_C3ISR MDMA channel 3 interrupt/status register 0x100 32 read-only n 0x0 0x0 BRTIF3 BRTIF3 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF3 BTIF3 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA3 CRQA3 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF3 CTCIF3 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF3 TCIF3 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF3 TEIF3 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C3LAR MDMA_C3LAR MDMA channel 3 Link Address register 0x124 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C3MAR MDMA_C3MAR MDMA channel 3 Mask address register 0x130 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C3MDR MDMA_C3MDR MDMA channel 3 Mask Data register 0x134 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C3SAR MDMA_C3SAR MDMA channel 3 source address register 0x118 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C3TBR MDMA_C3TBR MDMA channel 3 Trigger and Bus selection Register 0x128 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C3TCR MDMA_C3TCR This register is used to configure the concerned channel. 0x110 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C4BNDTR MDMA_C4BNDTR MDMA Channel 4 block number of data register 0x154 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C4BRUR MDMA_C4BRUR MDMA channel 4 Block Repeat address Update register 0x160 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C4CR MDMA_C4CR This register is used to control the concerned channel. 0x14C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C4DAR MDMA_C4DAR MDMA channel 4 destination address register 0x15C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C4ESR MDMA_C4ESR MDMA Channel 4 error status register 0x148 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C4IFCR MDMA_C4IFCR MDMA channel 4 interrupt flag clear register 0x144 32 read-write n 0x0 0x0 CBRTIF4 CBRTIF4 2 1 write-only CBTIF4 CBTIF4 3 1 write-only CCTCIF4 CCTCIF4 1 1 write-only CLTCIF4 CLTCIF4 4 1 write-only CTEIF4 CTEIF4 0 1 write-only C4ISR MDMA_C4ISR MDMA channel 4 interrupt/status register 0x140 32 read-only n 0x0 0x0 BRTIF4 BRTIF4 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF4 BTIF4 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA4 CRQA4 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF4 CTCIF4 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF4 TCIF4 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF4 TEIF4 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C4LAR MDMA_C4LAR MDMA channel 4 Link Address register 0x164 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C4MAR MDMA_C4MAR MDMA channel 4 Mask address register 0x170 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C4MDR MDMA_C4MDR MDMA channel 4 Mask Data register 0x174 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C4SAR MDMA_C4SAR MDMA channel 4 source address register 0x158 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C4TBR MDMA_C4TBR MDMA channel 4 Trigger and Bus selection Register 0x168 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C4TCR MDMA_C4TCR This register is used to configure the concerned channel. 0x150 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C5BNDTR MDMA_C5BNDTR MDMA Channel 5 block number of data register 0x194 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C5BRUR MDMA_C5BRUR MDMA channel 5 Block Repeat address Update register 0x1A0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C5CR MDMA_C5CR This register is used to control the concerned channel. 0x18C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C5DAR MDMA_C5DAR MDMA channel 5 destination address register 0x19C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C5ESR MDMA_C5ESR MDMA Channel 5 error status register 0x188 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C5IFCR MDMA_C5IFCR MDMA channel 5 interrupt flag clear register 0x184 32 read-write n 0x0 0x0 CBRTIF5 CBRTIF5 2 1 write-only CBTIF5 CBTIF5 3 1 write-only CCTCIF5 CCTCIF5 1 1 write-only CLTCIF5 CLTCIF5 4 1 write-only CTEIF5 CTEIF5 0 1 write-only C5ISR MDMA_C5ISR MDMA channel 5 interrupt/status register 0x180 32 read-only n 0x0 0x0 BRTIF5 BRTIF5 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF5 BTIF5 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA5 CRQA5 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF5 CTCIF5 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF5 TCIF5 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF5 TEIF5 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C5LAR MDMA_C5LAR MDMA channel 5 Link Address register 0x1A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C5MAR MDMA_C5MAR MDMA channel 5 Mask address register 0x1B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C5MDR MDMA_C5MDR MDMA channel 5 Mask Data register 0x1B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C5SAR MDMA_C5SAR MDMA channel 5 source address register 0x198 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C5TBR MDMA_C5TBR MDMA channel 5 Trigger and Bus selection Register 0x1A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C5TCR MDMA_C5TCR This register is used to configure the concerned channel. 0x190 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C6BNDTR MDMA_C6BNDTR MDMA Channel 6 block number of data register 0x1D4 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C6BRUR MDMA_C6BRUR MDMA channel 6 Block Repeat address Update register 0x1E0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C6CR MDMA_C6CR This register is used to control the concerned channel. 0x1CC 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C6DAR MDMA_C6DAR MDMA channel 6 destination address register 0x1DC 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C6ESR MDMA_C6ESR MDMA Channel 6 error status register 0x1C8 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C6IFCR MDMA_C6IFCR MDMA channel 6 interrupt flag clear register 0x1C4 32 read-write n 0x0 0x0 CBRTIF6 CBRTIF6 2 1 write-only CBTIF6 CBTIF6 3 1 write-only CCTCIF6 CCTCIF6 1 1 write-only CLTCIF6 CLTCIF6 4 1 write-only CTEIF6 CTEIF6 0 1 write-only C6ISR MDMA_C6ISR MDMA channel 6 interrupt/status register 0x1C0 32 read-only n 0x0 0x0 BRTIF6 BRTIF6 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF6 BTIF6 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA6 CRQA6 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF6 CTCIF6 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF6 TCIF6 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF6 TEIF6 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C6LAR MDMA_C6LAR MDMA channel 6 Link Address register 0x1E4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C6MAR MDMA_C6MAR MDMA channel 6 Mask address register 0x1F0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C6MDR MDMA_C6MDR MDMA channel 6 Mask Data register 0x1F4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C6SAR MDMA_C6SAR MDMA channel 6 source address register 0x1D8 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C6TBR MDMA_C6TBR MDMA channel 6 Trigger and Bus selection Register 0x1E8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C6TCR MDMA_C6TCR This register is used to configure the concerned channel. 0x1D0 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C7BNDTR MDMA_C7BNDTR MDMA Channel 7 block number of data register 0x214 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C7BRUR MDMA_C7BRUR MDMA channel 7 Block Repeat address Update register 0x220 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C7CR MDMA_C7CR This register is used to control the concerned channel. 0x20C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C7DAR MDMA_C7DAR MDMA channel 7 destination address register 0x21C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C7ESR MDMA_C7ESR MDMA Channel 7 error status register 0x208 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C7IFCR MDMA_C7IFCR MDMA channel 7 interrupt flag clear register 0x204 32 read-write n 0x0 0x0 CBRTIF7 CBRTIF7 2 1 write-only CBTIF7 CBTIF7 3 1 write-only CCTCIF7 CCTCIF7 1 1 write-only CLTCIF7 CLTCIF7 4 1 write-only CTEIF7 CTEIF7 0 1 write-only C7ISR MDMA_C7ISR MDMA channel 7 interrupt/status register 0x200 32 read-only n 0x0 0x0 BRTIF7 BRTIF7 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF7 BTIF7 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA7 CRQA7 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF7 CTCIF7 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF7 TCIF7 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF7 TEIF7 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C7LAR MDMA_C7LAR MDMA channel 7 Link Address register 0x224 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C7MAR MDMA_C7MAR MDMA channel 7 Mask address register 0x230 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C7MDR MDMA_C7MDR MDMA channel 7 Mask Data register 0x234 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C7SAR MDMA_C7SAR MDMA channel 7 source address register 0x218 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C7TBR MDMA_C7TBR MDMA channel 7 Trigger and Bus selection Register 0x228 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C7TCR MDMA_C7TCR This register is used to configure the concerned channel. 0x210 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C8BNDTR MDMA_C8BNDTR MDMA Channel 8 block number of data register 0x254 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C8BRUR MDMA_C8BRUR MDMA channel 8 Block Repeat address Update register 0x260 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C8CR MDMA_C8CR This register is used to control the concerned channel. 0x24C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C8DAR MDMA_C8DAR MDMA channel 8 destination address register 0x25C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C8ESR MDMA_C8ESR MDMA Channel 8 error status register 0x248 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C8IFCR MDMA_C8IFCR MDMA channel 8 interrupt flag clear register 0x244 32 read-write n 0x0 0x0 CBRTIF8 CBRTIF8 2 1 write-only CBTIF8 CBTIF8 3 1 write-only CCTCIF8 CCTCIF8 1 1 write-only CLTCIF8 CLTCIF8 4 1 write-only CTEIF8 CTEIF8 0 1 write-only C8ISR MDMA_C8ISR MDMA channel 8 interrupt/status register 0x240 32 read-only n 0x0 0x0 BRTIF8 BRTIF8 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF8 BTIF8 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA8 CRQA8 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF8 CTCIF8 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF8 TCIF8 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF8 TEIF8 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C8LAR MDMA_C8LAR MDMA channel 8 Link Address register 0x264 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C8MAR MDMA_C8MAR MDMA channel 8 Mask address register 0x270 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C8MDR MDMA_C8MDR MDMA channel 8 Mask Data register 0x274 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C8SAR MDMA_C8SAR MDMA channel 8 source address register 0x258 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C8TBR MDMA_C8TBR MDMA channel 8 Trigger and Bus selection Register 0x268 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C8TCR MDMA_C8TCR This register is used to configure the concerned channel. 0x250 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 C9BNDTR MDMA_C9BNDTR MDMA Channel 9 block number of data register 0x294 32 read-write n 0x0 0x0 BNDT BNDT 0 17 read-write BRC BRC 20 12 read-write BRDUM BRDUM 19 1 read-write B_0x0 At the end of a Block transfer, the DAR register will be updated by adding the DUV to the current DAR value (current Destination Address) 0x0 B_0x1 At the end of a block transfer, the DAR register will be updated by subtracting the DUV from the current DAR value (current Destination Address) 0x1 BRSUM BRSUM 18 1 read-write B_0x0 At the end of a block transfer, the SAR register will be updated by adding the SUV to the current SAR value (current Source Address) 0x0 B_0x1 At the end of a block transfer, the SAR register will be updated by subtracting the SUV from the current SAR value (current Source Address) 0x1 C9BRUR MDMA_C9BRUR MDMA channel 9 Block Repeat address Update register 0x2A0 32 read-write n 0x0 0x0 DUV DUV 16 16 read-write SUV SUV 0 16 read-write C9CR MDMA_C9CR This register is used to control the concerned channel. 0x28C 32 read-write n 0x0 0x0 BEX BEX 12 1 read-write B_0x0 Little endianess preserved for bytes 0x0 B_0x1 byte order exchanged in each half-word 0x1 BRTIE BRTIE 3 1 read-write B_0x0 BT interrupt disabled 0x0 B_0x1 BT interrupt enabled 0x1 BTIE BTIE 4 1 read-write B_0x0 BT complete interrupt disabled 0x0 B_0x1 BT complete interrupt enabled 0x1 CTCIE CTCIE 2 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 EN EN 0 1 read-write B_0x0 Channel disabled 0x0 B_0x1 Channel enabled 0x1 HEX HEX 13 1 read-write B_0x0 Little endianess preserved for half words 0x0 B_0x1 half-word order exchanged in each word 0x1 PL PL 6 2 read-write B_0x0 Low 0x0 B_0x1 Medium 0x1 B_0x2 High 0x2 B_0x3 Very high 0x3 SWRQ SWRQ 16 1 write-only TCIE TCIE 5 1 read-write B_0x0 TC interrupt disabled 0x0 B_0x1 TC interrupt enabled 0x1 TEIE TEIE 1 1 read-write B_0x0 TE interrupt disabled 0x0 B_0x1 TE interrupt enabled 0x1 WEX WEX 14 1 read-write B_0x0 Little endianess preserved for words 0x0 B_0x1 word order exchanged in double word 0x1 C9DAR MDMA_C9DAR MDMA channel 9 destination address register 0x29C 32 read-write n 0x0 0x0 DAR DAR 0 32 read-write C9ESR MDMA_C9ESR MDMA Channel 9 error status register 0x288 32 read-only n 0x0 0x0 ASE ASE 10 1 read-only B_0x0 No address/size error. 0x0 B_0x1 Programmed address is not coherent with the data size. 0x1 BSE BSE 11 1 read-only B_0x0 No block size error. 0x0 B_0x1 Programmed block size is not an integer multiple of the data size. 0x1 TEA TEA 0 7 read-only TED TED 7 1 read-only B_0x0 The last transfer error on the channel was a related to a read access. 0x0 B_0x1 The last transfer error on the channel was a related to a write access. 0x1 TELD TELD 8 1 read-only B_0x0 No link data read access error. 0x0 B_0x1 The last transfer error on the channel was a related to a read of the Link Data structure. 0x1 TEMD TEMD 9 1 read-only B_0x0 No mask write access error. 0x0 B_0x1 The last transfer error on the channel was a related to a write of the Mask Data. 0x1 C9IFCR MDMA_C9IFCR MDMA channel 9 interrupt flag clear register 0x284 32 read-write n 0x0 0x0 CBRTIF9 CBRTIF9 2 1 write-only CBTIF9 CBTIF9 3 1 write-only CCTCIF9 CCTCIF9 1 1 write-only CLTCIF9 CLTCIF9 4 1 write-only CTEIF9 CTEIF9 0 1 write-only C9ISR MDMA_C9ISR MDMA channel 9 interrupt/status register 0x280 32 read-only n 0x0 0x0 BRTIF9 BRTIF9 2 1 read-only B_0x0 No block repeat transfer complete event on channel x 0x0 B_0x1 A block repeat transfer complete event occurred on channel x 0x1 BTIF9 BTIF9 3 1 read-only B_0x0 No block transfer complete event on channel x 0x0 B_0x1 A block transfer complete event occurred on channel x 0x1 CRQA9 CRQA9 16 1 read-only B_0x0 The MDMA transfer RQ is inactive for channel x. 0x0 B_0x1 The MDMA transfer RQ is active for channel x 0x1 CTCIF9 CTCIF9 1 1 read-only B_0x0 No channel transfer complete event on channel x 0x0 B_0x1 A channel transfer complete event occurred on channel x 0x1 TCIF9 TCIF9 4 1 read-only B_0x0 No buffer transfer complete event on channel x 0x0 B_0x1 A buffer transfer complete event occurred on channel x 0x1 TEIF9 TEIF9 0 1 read-only B_0x0 No transfer error on stream x 0x0 B_0x1 A transfer error occurred on stream x 0x1 C9LAR MDMA_C9LAR MDMA channel 9 Link Address register 0x2A4 32 read-write n 0x0 0x0 LAR LAR 0 32 read-write C9MAR MDMA_C9MAR MDMA channel 9 Mask address register 0x2B0 32 read-write n 0x0 0x0 MAR MAR 0 32 read-write C9MDR MDMA_C9MDR MDMA channel 9 Mask Data register 0x2B4 32 read-write n 0x0 0x0 MDR MDR 0 32 read-write C9SAR MDMA_C9SAR MDMA channel 9 source address register 0x298 32 read-write n 0x0 0x0 SAR SAR 0 32 read-write C9TBR MDMA_C9TBR MDMA channel 9 Trigger and Bus selection Register 0x2A8 32 read-write n 0x0 0x0 DBUS DBUS 17 1 read-write B_0x0 The system/AXI bus is used as destination (write operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as destination (write operation) on channel x. 0x1 SBUS SBUS 16 1 read-write B_0x0 The system/AXI bus is used as source (read operation) on channel x. 0x0 B_0x1 The AHB bus/TCM is used as source (read operation) on channel x. 0x1 TSEL TSEL 0 6 read-write C9TCR MDMA_C9TCR This register is used to configure the concerned channel. 0x290 32 read-write n 0x0 0x0 BWM BWM 31 1 read-write B_0x0 The destination write operation is non-bufferable. 0x0 B_0x1 The destination write operation is bufferable. 0x1 DBURST DBURST 15 3 read-write B_0x0 single transfer N: burst of 2^N beats These bits are protected and can be written only if EN is 0 0x0 DINC DINC 2 2 read-write B_0x0 Destination address pointer is fixed 0x0 B_0x2 Destination address pointer is incremented after each data transfer (increment is done according to DINCOS) 0x2 B_0x3 Destination address pointer is decremented after each data transfer (increment is done according to DINCOS) 0x3 DINCOS DINCOS 10 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 DSIZE DSIZE 6 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 PAM PAM 26 2 read-write B_0x0 Right Aligned - only the LSBs part of the Source is written to the destination address 0x0 B_0x1 Right Aligned, Sign extended 0x1 B_0x2 Left Aligned - only the MSBs part of the Source is written to the destination address 0x2 PKE PKE 25 1 read-write B_0x0 The source data is written to the destination as is. 0x0 B_0x1 The source data is packed/un-packed into the destination data size. All data are right aligned, in Little Endian mode. 0x1 SBURST SBURST 12 3 read-write B_0x0 single transfer N: burst of 2^N beats 0x0 SINC SINC 0 2 read-write B_0x0 Source address pointer is fixed 0x0 B_0x2 Source address pointer is incremented after each data transfer (increment is done according to SINCOS) 0x2 B_0x3 Source address pointer is decremented after each data transfer (increment is done according to SINCOS) 0x3 SINCOS SINCOS 8 2 read-write B_0x0 byte (8-bit) 0x0 B_0x1 half-word (16-bit) 0x1 B_0x2 word (32-bit) 0x2 B_0x3 Double-Word (64-bit) - 0x3 SSIZE SSIZE 4 2 read-write B_0x0 Byte (8-bit) 0x0 B_0x1 Half-word (16-bit) 0x1 B_0x2 Word (32-bit) 0x2 B_0x3 Double-Word (64-bit) 0x3 SWRM SWRM 30 1 read-write B_0x0 HW request are taken into account: the transfer is initiated as defined by TRGM value and acknowledged by the MDMA ACKx signal. 0x0 B_0x1 HW request are ignored. Transfer is trigerred by SW writing 1 to the SWRQ bit. 0x1 TLEN TLEN 18 7 read-write TRGM TRGM 28 2 read-write B_0x0 Each MDMA request (SW or HW) triggers a buffer transfer 0x0 B_0x1 Each MDMA request (SW or HW) triggers a block transfer 0x1 B_0x2 Each MDMA request (SW or HW) triggers a repeated block transfer (if the block repeat is 0, a single block is transferred) 0x2 B_0x3 Each MDMA request (SW or HW) triggers the transfer of the whole data for the respective channel (e.g. linked list) until the channel reach the end and it is disabled. 0x3 GISR0 MDMA_GISR0 MDMA Global Interrupt/Status Register 0x0 32 read-only n 0x0 0x0 GIF0 GIF0 0 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF1 GIF1 1 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF10 GIF10 10 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF11 GIF11 11 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF12 GIF12 12 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF13 GIF13 13 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF14 GIF14 14 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF15 GIF15 15 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF2 GIF2 2 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF3 GIF3 3 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 GIF4 GIF4 4 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF5 GIF5 5 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF6 GIF6 6 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF7 GIF7 7 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF8 GIF8 8 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF9 GIF9 9 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 SGISR0 MDMA_SGISR0 MDMA secure global interrupt/status register 0x8 32 read-only n 0x0 0x0 GIF0 GIF0 0 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF1 GIF1 1 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF10 GIF10 10 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF11 GIF11 11 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF12 GIF12 12 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF13 GIF13 13 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF14 GIF14 14 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF15 GIF15 15 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF16 GIF16 16 1 GIF17 GIF17 17 1 GIF18 GIF18 18 1 GIF19 GIF19 19 1 GIF2 GIF2 2 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF20 GIF20 20 1 GIF21 GIF21 21 1 GIF22 GIF22 22 1 GIF23 GIF23 23 1 GIF24 GIF24 24 1 GIF25 GIF25 25 1 GIF26 GIF26 26 1 GIF27 GIF27 27 1 GIF28 GIF28 28 1 GIF29 GIF29 29 1 GIF3 GIF3 3 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF30 GIF30 30 1 GIF31 GIF31 31 1 GIF4 GIF4 4 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF5 GIF5 5 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF6 GIF6 6 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF7 GIF7 7 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF8 GIF8 8 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 GIF9 GIF9 9 1 read-only B_0x0 No interrupt generated by channel x 0x0 B_0x1 Interrupt generated by channel x 0x1 PWR PWR PWR 0x0 0x0 0x400 registers n CR1 PWR_CR1 Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access will generate a bus error. Secure and non-secure read accesses are granted and return the register value. 0x0 32 read-write n 0x0 0x0 ALS ALS 17 2 read-write AVDEN AVDEN 16 1 read-write DBP DBP 8 1 read-write LPCFG LPCFG 1 1 read-write LPDS LPDS 0 1 read-write LVDS LVDS 2 1 read-write PLS PLS 5 3 read-write PVDEN PVDEN 4 1 read-write CR2 PWR_CR2 Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there will be no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access will generate a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x8 32 read-write n 0x0 0x0 BREN BREN 0 1 read-write BRRDY BRRDY 16 1 read-only MONEN MONEN 4 1 read-write RREN RREN 1 1 read-write RRRDY RRRDY 17 1 read-only TEMPH TEMPH 23 1 read-only TEMPL TEMPL 22 1 read-only VBATH VBATH 21 1 read-only VBATL VBATL 20 1 read-only CR3 PWR_CR3 Not reset by wakeup from Standby mode and Application reset (NRST, IWDG, ...) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access will generate a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0xC 32 read-write n 0x0 0x0 DDRRETEN DDRRETEN 12 1 read-write DDRSRDIS DDRSRDIS 11 1 read-write DDRSREN DDRSREN 10 1 read-write POPL POPL 17 5 read-write REG11EN REG11EN 30 1 read-write REG11RDY REG11RDY 31 1 read-only REG18EN REG18EN 28 1 read-write REG18RDY REG18RDY 29 1 read-only USB33DEN USB33DEN 24 1 read-write USB33RDY USB33RDY 26 1 read-only VBE VBE 8 1 read-write VBRS VBRS 9 1 read-write CSR1 PWR_CSR1 Reset on any system reset. 0x4 32 read-only n 0x0 0x0 AVDO AVDO 16 1 read-only PVDO PVDO 4 1 read-only ID PWR_ID PWR IP identification register 0x3F8 32 read-only n 0x0 0x0 IPID IPID 0 32 read-only MCUCR PWR_MCUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x14 32 read-write n 0x0 0x0 CSSF CSSF 9 1 read-write DEEPSLEEP DEEPSLEEP 15 1 read-only PDDS PDDS 0 1 read-write SBF SBF 6 1 read-only STOPF STOPF 5 1 read-only MCUWKUPENR PWR_MCUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x2C 32 read-write n 0x0 0x0 WKUPEN1 WKUPEN1 0 1 read-write WKUPEN2 WKUPEN2 1 1 read-write WKUPEN3 WKUPEN3 2 1 read-write WKUPEN4 WKUPEN4 3 1 read-write WKUPEN5 WKUPEN5 4 1 read-write WKUPEN6 WKUPEN6 5 1 read-write MPUCR PWR_MPUCR See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access will generate a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x10 32 read-write n 0x0 0x0 CSSF CSSF 9 1 read-write CSTBYDIS CSTBYDIS 3 1 read-write PDDS PDDS 0 1 read-write SBF SBF 6 1 read-only SBFMPU SBFMPU 7 1 read-only STANDBYWFIL2 STANDBYWFIL2 15 1 read-only STOPF STOPF 5 1 read-only MPUWKUPENR PWR_MPUWKUPENR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access will be discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x28 32 read-write n 0x0 0x0 WKUPEN1 WKUPEN1 0 1 read-write WKUPEN2 WKUPEN2 1 1 read-write WKUPEN3 WKUPEN3 2 1 read-write WKUPEN4 WKUPEN4 3 1 read-write WKUPEN5 WKUPEN5 4 1 read-write WKUPEN6 WKUPEN6 5 1 read-write SID PWR_SID PWR size ID register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only VER PWR_VER PWR IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only WKUPCR PWR_WKUPCR Not reset by wakeup from Standby mode, but by any application reset (NRST, IWDG, ...). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access will complete after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs will be discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error will be generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed. 0x20 32 read-write n 0x0 0x0 WKUPC1 WKUPC1 0 1 read-write WKUPC2 WKUPC2 1 1 read-write WKUPC3 WKUPC3 2 1 read-write WKUPC4 WKUPC4 3 1 read-write WKUPC5 WKUPC5 4 1 read-write WKUPC6 WKUPC6 5 1 read-write WKUPP1 WKUPP1 8 1 read-write WKUPP2 WKUPP2 9 1 read-write WKUPP3 WKUPP3 10 1 read-write WKUPP4 WKUPP4 11 1 read-write WKUPP5 WKUPP5 12 1 read-write WKUPP6 WKUPP6 13 1 read-write WKUPPUPD1 WKUPPUPD1 16 2 read-write WKUPPUPD2 WKUPPUPD2 18 2 read-write WKUPPUPD3 WKUPPUPD3 20 2 read-write WKUPPUPD4 WKUPPUPD4 22 2 read-write WKUPPUPD5 WKUPPUPD5 24 2 read-write WKUPPUPD6 WKUPPUPD6 26 2 read-write WKUPFR PWR_WKUPFR Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) 0x24 32 read-only n 0x0 0x0 WKUPF1 WKUPF1 0 1 read-only WKUPF2 WKUPF2 1 1 read-only WKUPF3 WKUPF3 2 1 read-only WKUPF4 WKUPF4 3 1 read-only WKUPF5 WKUPF5 4 1 read-only WKUPF6 WKUPF6 5 1 read-only QUADSPI QUADSPI QUADSPI 0x0 0x0 0x1000 registers n ABR QUADSPI_ABR QUADSPI alternate bytes registers 0x1C 32 read-write n 0x0 0x0 ALTERNATE ALTERNATE 0 32 read-write AR QUADSPI_AR QUADSPI address register 0x18 32 read-write n 0x0 0x0 ADDRESS ADDRESS 0 32 read-write CCR QUADSPI_CCR QUADSPI communication configuration register 0x14 32 read-write n 0x0 0x0 ABMODE ABMODE 14 2 read-write ABSIZE ABSIZE 16 2 read-write ADMODE ADMODE 10 2 read-write ADSIZE ADSIZE 12 2 read-write DCYC DCYC 18 5 read-write DDRM DDRM 31 1 read-write DHHC DHHC 30 1 read-write DMODE DMODE 24 2 read-write FMODE FMODE 26 2 read-write FRCM FRCM 29 1 read-write IMODE IMODE 8 2 read-write INSTRUCTION INSTRUCTION 0 8 read-write SIOO SIOO 28 1 read-write CR QUADSPI_CR QUADSPI control register 0x0 32 read-write n 0x0 0x0 ABORT ABORT 1 1 read-write APMS APMS 22 1 read-write DFM DFM 6 1 read-write DMAEN DMAEN 2 1 read-write EN EN 0 1 read-write FSEL FSEL 7 1 read-write FTHRES FTHRES 8 4 read-write FTIE FTIE 18 1 read-write PMM PMM 23 1 read-write PRESCALER PRESCALER 24 8 read-write SMIE SMIE 19 1 read-write SSHIFT SSHIFT 4 1 read-write TCEN TCEN 3 1 read-write TCIE TCIE 17 1 read-write TEIE TEIE 16 1 read-write TOIE TOIE 20 1 read-write DCR QUADSPI_DCR QUADSPI device configuration register 0x4 32 read-write n 0x0 0x0 CKMODE CKMODE 0 1 read-write CSHT CSHT 8 3 read-write FSIZE FSIZE 16 5 read-write DLR QUADSPI_DLR QUADSPI data length register 0x10 32 read-write n 0x0 0x0 DL DL 0 32 read-write DR QUADSPI_DR QUADSPI data register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write FCR QUADSPI_FCR QUADSPI flag clear register 0xC 32 read-write n 0x0 0x0 CSMF CSMF 3 1 write-only CTCF CTCF 1 1 write-only CTEF CTEF 0 1 write-only CTOF CTOF 4 1 write-only HWCFGR QUADSPI_HWCFGR QUADSPI HW configuration register 0x3F0 32 read-only n 0x0 0x0 FIFOPTR FIFOPTR 4 4 read-only FIFOSIZE FIFOSIZE 0 4 read-only IDLENGTH IDLENGTH 12 4 read-only PRESCVAL PRESCVAL 8 4 read-only IPIDR QUADSPI_IPIDR QUADSPI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only LPTR QUADSPI_LPTR QUADSPI low-power timeout register 0x30 32 read-write n 0x0 0x0 TIMEOUT TIMEOUT 0 16 read-write PIR QUADSPI_PIR QUADSPI polling interval register 0x2C 32 read-write n 0x0 0x0 INTERVAL INTERVAL 0 16 read-write PSMAR QUADSPI_PSMAR QUADSPI polling status match register 0x28 32 read-write n 0x0 0x0 MATCH MATCH 0 32 read-write PSMKR QUADSPI_PSMKR QUADSPI polling status mask register 0x24 32 read-write n 0x0 0x0 MASK MASK 0 32 read-write SIDR QUADSPI_SIDR QUADSPI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SR QUADSPI_SR QUADSPI status register 0x8 32 read-only n 0x0 0x0 BUSY BUSY 5 1 read-only FLEVEL FLEVEL 8 5 read-only FTF FTF 2 1 read-only SMF SMF 3 1 read-only TCF TCF 1 1 read-only TEF TEF 0 1 read-only TOF TOF 4 1 read-only VERR QUADSPI_VERR QUADSPI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only RCC RCC RCC 0x0 0x0 0x1000 registers n ADCCKSELR RCC_ADCCKSELR This register is used to control the selection of the kernel clock for the ADC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x928 32 read-write n 0x0 0x0 ADCSRC ADCSRC 0 2 read-write B_0x0 pll4_q_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 per_ck clock selected as kernel peripheral clock 0x1 AHB2RSTCLRR RCC_AHB2RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x99C 32 read-write n 0x0 0x0 ADC12RST ADC12RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 DMA1RST DMA1RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 DMA2RST DMA2RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 DMAMUXRST DMAMUXRST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SDMMC3RST SDMMC3RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 USBORST USBORST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 AHB2RSTSETR RCC_AHB2RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x998 32 read-write n 0x0 0x0 ADC12RST ADC12RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DMA1RST DMA1RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DMA2RST DMA2RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DMAMUXRST DMAMUXRST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SDMMC3RST SDMMC3RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USBORST USBORST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 AHB3RSTCLRR RCC_AHB3RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x9A4 32 read-write n 0x0 0x0 CRC2RST CRC2RST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 CRYP2RST CRYP2RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 DCMIRST DCMIRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 HASH2RST HASH2RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 HSEMRST HSEMRST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 IPCCRST IPCCRST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 RNG2RST RNG2RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 AHB3RSTSETR RCC_AHB3RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x9A0 32 read-write n 0x0 0x0 CRC2RST CRC2RST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 CRYP2RST CRYP2RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DCMIRST DCMIRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 HASH2RST HASH2RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 HSEMRST HSEMRST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 IPCCRST IPCCRST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 RNG2RST RNG2RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 AHB4RSTCLRR RCC_AHB4RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x9AC 32 read-write n 0x0 0x0 GPIOARST GPIOARST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOBRST GPIOBRST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOCRST GPIOCRST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIODRST GPIODRST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOERST GPIOERST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOFRST GPIOFRST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOGRST GPIOGRST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOHRST GPIOHRST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOIRST GPIOIRST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOJRST GPIOJRST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOKRST GPIOKRST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 AHB4RSTSETR RCC_AHB4RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x9A8 32 read-write n 0x0 0x0 GPIOARST GPIOARST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOBRST GPIOBRST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOCRST GPIOCRST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIODRST GPIODRST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOERST GPIOERST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOFRST GPIOFRST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOGRST GPIOGRST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOHRST GPIOHRST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOIRST GPIOIRST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOJRST GPIOJRST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOKRST GPIOKRST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 AHB5RSTCLRR RCC_AHB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x194 32 read-write n 0x0 0x0 AXIMCRST AXIMCRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 CRYP1RST CRYP1RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 GPIOZRST GPIOZRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 HASH1RST HASH1RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 RNG1RST RNG1RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 AHB5RSTSETR RCC_AHB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x190 32 read-write n 0x0 0x0 AXIMCRST AXIMCRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 CRYP1RST CRYP1RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPIOZRST GPIOZRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 HASH1RST HASH1RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 RNG1RST RNG1RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 AHB6RSTCLRR RCC_AHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x19C 32 read-write n 0x0 0x0 CRC1RST CRC1RST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 ETHMACRST ETHMACRST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 FMCRST FMCRST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 QSPIRST QSPIRST 14 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SDMMC1RST SDMMC1RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SDMMC2RST SDMMC2RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 USBHRST USBHRST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 AHB6RSTSETR RCC_AHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x198 32 read-write n 0x0 0x0 CRC1RST CRC1RST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 ETHMACRST ETHMACRST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 FMCRST FMCRST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 GPURST GPURST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is on-going 0x1 QSPIRST QSPIRST 14 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SDMMC1RST SDMMC1RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SDMMC2RST SDMMC2RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USBHRST USBHRST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 APB1DIVR RCC_APB1DIVR This register is used to control the APB1 clock prescaler. Please refer to section Section1.4.6.3: Sub-System Clock Generation for additional information. 0x834 32 read-write n 0x0 0x0 APB1DIV APB1DIV 0 3 read-write B_0x0 mlhclk (default after reset) 0x0 B_0x1 mlhclk / 2 0x1 B_0x2 mlhclk / 4 0x2 B_0x3 mlhclk / 8 0x3 B_0x4 mlhclk / 16 0x4 APB1DIVRDY APB1DIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 APB1RSTCLRR RCC_APB1RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x984 32 read-write n 0x0 0x0 CECRST CECRST 27 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 DAC12RST DAC12RST 29 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 I2C1RST I2C1RST 21 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 I2C2RST I2C2RST 22 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 I2C3RST I2C3RST 23 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 I2C5RST I2C5RST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 LPTIM1RST LPTIM1RST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 MDIOSRST MDIOSRST 31 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 SPDIFRST SPDIFRST 26 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 SPI2RST SPI2RST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 SPI3RST SPI3RST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM12RST TIM12RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM13RST TIM13RST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM14RST TIM14RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM2RST TIM2RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM3RST TIM3RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM4RST TIM4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM5RST TIM5RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM6RST TIM6RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 TIM7RST TIM7RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 UART4RST UART4RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 UART5RST UART5RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 UART7RST UART7RST 18 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 UART8RST UART8RST 19 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 USART2RST USART2RST 14 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 USART3RST USART3RST 15 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing release the block reset, reading means that the block reset is asserted 0x1 APB1RSTSETR RCC_APB1RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x980 32 read-write n 0x0 0x0 CECRST CECRST 27 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DAC12RST DAC12RST 29 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 I2C1RST I2C1RST 21 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 I2C2RST I2C2RST 22 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 I2C3RST I2C3RST 23 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 I2C5RST I2C5RST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 LPTIM1RST LPTIM1RST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 MDIOSRST MDIOSRST 31 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPDIFRST SPDIFRST 26 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI2RST SPI2RST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI3RST SPI3RST 12 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM12RST TIM12RST 6 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM13RST TIM13RST 7 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM14RST TIM14RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM2RST TIM2RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM3RST TIM3RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM4RST TIM4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM5RST TIM5RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM6RST TIM6RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM7RST TIM7RST 5 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 UART4RST UART4RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 UART5RST UART5RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 UART7RST UART7RST 18 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 UART8RST UART8RST 19 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USART2RST USART2RST 14 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USART3RST USART3RST 15 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 APB2DIVR RCC_APB2DIVR This register is used to control the APB2 clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. 0x838 32 read-write n 0x0 0x0 APB2DIV APB2DIV 0 3 read-write B_0x0 mlhclk (default after reset) 0x0 B_0x1 mlhclk / 2 0x1 B_0x2 mlhclk / 4 0x2 B_0x3 mlhclk / 8 0x3 B_0x4 mlhclk / 16 0x4 APB2DIVRDY APB2DIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 APB2RSTCLRR RCC_APB2RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x98C 32 read-write n 0x0 0x0 DFSDMRST DFSDMRST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 FDCANRST FDCANRST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SAI1RST SAI1RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SAI2RST SAI2RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SAI3RST SAI3RST 18 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SPI1RST SPI1RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SPI4RST SPI4RST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SPI5RST SPI5RST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TIM15RST TIM15RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TIM16RST TIM16RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TIM17RST TIM17RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TIM1RST TIM1RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TIM8RST TIM8RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 USART6RST USART6RST 13 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 APB2RSTSETR RCC_APB2RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x988 32 read-write n 0x0 0x0 DFSDMRST DFSDMRST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 FDCANRST FDCANRST 24 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SAI1RST SAI1RST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SAI2RST SAI2RST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SAI3RST SAI3RST 18 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI1RST SPI1RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI4RST SPI4RST 9 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI5RST SPI5RST 10 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM15RST TIM15RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM16RST TIM16RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM17RST TIM17RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM1RST TIM1RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TIM8RST TIM8RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USART6RST USART6RST 13 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 APB3DIVR RCC_APB3DIVR This register is used to control the APB3 clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. 0x83C 32 read-write n 0x0 0x0 APB3DIV APB3DIV 0 3 read-write B_0x0 hclk (default after reset) 0x0 B_0x1 hclk / 2 0x1 B_0x2 hclk / 4 0x2 B_0x3 hclk / 8 0x3 APB3DIVRDY APB3DIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 APB3RSTCLRR RCC_APB3RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x994 32 read-write n 0x0 0x0 LPTIM2RST LPTIM2RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 LPTIM3RST LPTIM3RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 LPTIM4RST LPTIM4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 LPTIM5RST LPTIM5RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 PMBCTRLRST PMBCTRLRST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SAI4RST SAI4RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SYSCFGRST SYSCFGRST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TMPSENSRST TMPSENSRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 VREFRST VREFRST 13 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 APB3RSTSETR RCC_APB3RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x990 32 read-write n 0x0 0x0 LPTIM2RST LPTIM2RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 LPTIM3RST LPTIM3RST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 LPTIM4RST LPTIM4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 LPTIM5RST LPTIM5RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 PMBCTRLRST PMBCTRLRST 17 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SAI4RST SAI4RST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SYSCFGRST SYSCFGRST 11 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TMPSENSRST TMPSENSRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 VREFRST VREFRST 13 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 APB4DIVR RCC_APB4DIVR This register is used to control the APB4 clock divider. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x3C 32 read-write n 0x0 0x0 APB4DIV APB4DIV 0 3 read-write B_0x0 aclk (default after reset) 0x0 B_0x1 aclk / 2 0x1 B_0x2 aclk / 4 0x2 B_0x3 aclk / 8 0x3 APB4DIVRDY APB4DIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 APB4RSTCLRR RCC_APB4RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. 0x184 32 read-write n 0x0 0x0 DDRPERFMRST DDRPERFMRST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 DSIRST DSIRST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 LTDCRST LTDCRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 USBPHYRST USBPHYRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 APB4RSTSETR RCC_APB4RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x180 32 read-write n 0x0 0x0 DDRPERFMRST DDRPERFMRST 8 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 DSIRST DSIRST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 LTDCRST LTDCRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USBPHYRST USBPHYRST 16 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 APB5DIVR RCC_APB5DIVR This register is used to control the APB5 clock divider. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x40 32 read-write n 0x0 0x0 APB5DIV APB5DIV 0 3 read-write B_0x0 aclk (default after reset) 0x0 B_0x1 aclk / 2 0x1 B_0x2 aclk / 4 0x2 B_0x3 aclk / 8 0x3 APB5DIVRDY APB5DIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 APB5RSTCLRR RCC_APB5RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x18C 32 read-write n 0x0 0x0 I2C4RST I2C4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 I2C6RST I2C6RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 SPI6RST SPI6RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 STGENRST STGENRST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 USART1RST USART1RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 APB5RSTSETR RCC_APB5RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x188 32 read-write n 0x0 0x0 I2C4RST I2C4RST 2 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 I2C6RST I2C6RST 3 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 SPI6RST SPI6RST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 STGENRST STGENRST 20 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 USART1RST USART1RST 4 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 ASSCKSELR RCC_ASSCKSELR This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x24 32 read-write n 0x0 0x0 AXISSRC AXISSRC 0 3 read-write B_0x0 HSI selected as system clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as system clock (hse_ck) 0x1 B_0x2 PLL2 selected as system clock (pll2_p_ck) 0x2 AXISSRCRDY AXISSRCRDY 31 1 read-only B_0x0 The AXI sub-system switch is not ready or in positions higher than : no clock is generated on its output 0x0 B_0x1 The AXI sub-system switch is ready: the clock switch is selecting the clock given by AXISSRC field. (default after reset) 0x1 AXIDIVR RCC_AXIDIVR This register is used to control the AXI Matrix clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x30 32 read-write n 0x0 0x0 AXIDIV AXIDIV 0 3 read-write B_0x0 axiss_ck (default after reset) 0x0 B_0x1 axiss_ck / 2 0x1 B_0x2 axiss_ck / 3 0x2 AXIDIVRDY AXIDIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 BDCR RCC_BDCR This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section1.3.5: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode. 0x140 32 read-write n 0x0 0x0 LSEBYP LSEBYP 1 1 read-write B_0x0 LSE oscillator not bypassed (default after backup domain reset) 0x0 B_0x1 LSE oscillator bypassed 0x1 LSECSSD LSECSSD 9 1 read-only B_0x0 No failure detected on 32 kHz oscillator (default after backup domain reset) 0x0 B_0x1 Failure detected on 32 kHz oscillator 0x1 LSECSSON LSECSSON 8 1 read-write B_0x0 Clock Security System on 32 kHz oscillator OFF (default after backup domain reset) 0x0 B_0x1 Clock Security System on 32 kHz oscillator ON 0x1 LSEDRV LSEDRV 4 2 read-write B_0x0 Lowest drive (default after backup domain reset) 0x0 B_0x1 Medium low drive 0x1 B_0x2 Medium high drive 0x2 B_0x3 Highest drive 0x3 LSEON LSEON 0 1 read-write B_0x0 LSE oscillator OFF (default after backup domain reset) 0x0 B_0x1 LSE oscillator ON 0x1 LSERDY LSERDY 2 1 read-only B_0x0 LSE oscillator not ready (default after backup domain reset) 0x0 B_0x1 LSE oscillator ready 0x1 RTCCKEN RTCCKEN 20 1 read-write B_0x0 rtc_ck clock is disabled (default after backup domain reset) 0x0 B_0x1 rtc_ck clock enabled 0x1 RTCSRC RTCSRC 16 2 read-write B_0x0 No clock (default after backup domain reset) 0x0 B_0x1 LSE clock used as RTC clock 0x1 B_0x2 LSI clock used as RTC clock 0x2 B_0x3 HSE clock divided by RTCDIV value is used as RTC clock 0x3 VSWRST VSWRST 31 1 read-write B_0x0 Reset not activated (default after backup domain reset) 0x0 B_0x1 Resets the entire VSW domain 0x1 BR_RSTSCLRR RCC_BR_RSTSCLRR This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .The application running on MPU shall not use this register to define the reset source, the register RCC_MP_RSTSR must be used instead.Please refer to Section1.3.12: Reset Source Identification for details.This register is located into VDD domain, and is reset by por_rst reset. If TZEN = , this register can only be modified in secure mode. 0x400 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 read-write B_0x0 Writing has no effect, reading means that no BOR reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the BORRSTF flag, reading means that a BOR reset occurred 0x1 HCSSRSTF HCSSRSTF 3 1 read-write B_0x0 Writing has no effect, reading means that no HSE CSS reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the HCSSRSTF flag, reading means that a HSE CSS reset occurred 0x1 IWDG1RSTF IWDG1RSTF 8 1 read-write B_0x0 Writing has no effect, reading means that no IWDG1 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the IWDG1RSTF flag, reading means that a IWDG1 reset occurred 0x1 IWDG2RSTF IWDG2RSTF 9 1 read-write B_0x0 Writing has no effect, reading means that no IWDG2 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the IWDG2RSTF flag, reading means that a IWDG2 reset occurred 0x1 MCSYSRSTF MCSYSRSTF 7 1 read-write B_0x0 Writing has no effect, reading means that no system reset generated by the MCU occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the MCURSTF flag, reading means that a system reset generated by the MCU occurred 0x1 MPSYSRSTF MPSYSRSTF 6 1 read-write B_0x0 Writing has no effect, reading means that no system reset generated by the MPU occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the MCURSTF flag, reading means that a system reset generated by the MPU occurred 0x1 PADRSTF PADRSTF 2 1 read-write B_0x0 Writing has no effect, reading means that no PAD reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the PADRSTF flag, reading means that a PAD reset occurred 0x1 PORRSTF PORRSTF 0 1 read-write B_0x0 Writing has no effect, reading means that no POR/PDR reset occurred 0x0 B_0x1 Writing clears the PORRSTF flag, reading means that a POR/PDR reset occurred (default after por_rst reset) 0x1 VCORERSTF VCORERSTF 4 1 read-write B_0x0 Writing has no effect, reading means that VDD_CORE is not the origin of the reset 0x0 B_0x1 Writing clears the VCORERSTF flag, reading means that VDD_CORE is the origin of the reset (default after por_rst reset) 0x1 WWDG1RSTF WWDG1RSTF 10 1 read-write B_0x0 Writing has no effect, reading means that no WWDG1 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the WWDG1RSTF flag, reading means that a WWDG1 reset occurred 0x1 CECCKSELR RCC_CECCKSELR This register is used to control the selection of the kernel clock for the CEC-HDMI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x918 32 read-write n 0x0 0x0 CECSRC CECSRC 0 2 read-write B_0x0 lse_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 lsi_ck clock selected as kernel peripheral clock 0x1 B_0x2 csi_ker_ck/122 clock selected as kernel peripheral clock 0x2 CPERCKSELR RCC_CPERCKSELR This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Please refer to Section1.4.10.1: Clock Enabling Delays. 0xD0 32 read-write n 0x0 0x0 CKPERSRC CKPERSRC 0 2 read-write B_0x0 hsi_ker_ck clock selected (default after reset) 0x0 B_0x1 csi_ker_ck clock selected 0x1 B_0x2 hse_ker_ck clock selected 0x2 B_0x3 Clock disabled 0x3 CSICFGR RCC_CSICFGR This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x1C 32 read-write n 0x0 0x0 CSICAL CSICAL 16 8 read-only CSITRIM CSITRIM 8 5 read-write DBGCFGR RCC_DBGCFGR This is register contains the enable control of the debug and trace function, and the clock divider for the trace function. 0x80C 32 read-write n 0x0 0x0 DBGCKEN DBGCKEN 8 1 read-write B_0x0 The enabling of the clock for the debug function is controlled by cdbgwrupreq signal from DAP. (default after reset) 0x0 B_0x1 The clock for the debug function is enabled 0x1 DBGRST DBGRST 12 1 read-write B_0x0 The trace and debug parts are not reset. (default after reset) 0x0 B_0x1 The trace and debug parts are under reset. 0x1 TRACECKEN TRACECKEN 9 1 read-write B_0x0 The clock for the trace function is disabled (default after reset) 0x0 B_0x1 The clock for the trace function is enabled 0x1 TRACEDIV TRACEDIV 0 3 read-write B_0x0 aclk 0x0 B_0x1 aclk / 2 (default after reset) 0x1 B_0x2 aclk / 4 0x2 B_0x3 aclk / 8 0x3 DDRITFCR RCC_DDRITFCR This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode. 0xD8 32 read-write n 0x0 0x0 AXIDCGEN AXIDCGEN 8 1 read-write B_0x0 means that the dynamic clock gating of AXIDCG[2:1] is disabled during MPU CRUN, 0x0 B_0x1 means that the dynamic clock gating of AXIDCG{2:1] is enabled during MPU CRUN 0x1 DDRC1EN DDRC1EN 0 1 read-write B_0x0 Means that the DDRC peripheral clocks are disabled 0x0 B_0x1 Means that the DDRC peripheral clocks are enabled 0x1 DDRC1LPEN DDRC1LPEN 1 1 read-write B_0x0 means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 means that the peripheral clocks are enabled in CSLEEP 0x1 DDRC2EN DDRC2EN 2 1 read-write B_0x0 Means that the DDRC peripheral clocks are disabled 0x0 B_0x1 Means that the DDRC peripheral clocks are enabled 0x1 DDRC2LPEN DDRC2LPEN 3 1 read-write B_0x0 means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 means that the peripheral clocks are enabled in CSLEEP 0x1 DDRCAPBEN DDRCAPBEN 6 1 read-write B_0x0 means that the APB clock is disabled 0x0 B_0x1 means that the APB clock is enabled 0x1 DDRCAPBLPEN DDRCAPBLPEN 7 1 read-write B_0x0 means that the APB clock is disabled in CSLEEP 0x0 B_0x1 means that the APB clock is enabled in CSLEEP 0x1 DDRCAPBRST DDRCAPBRST 14 1 read-write B_0x0 does not reset the DDRC APB interface 0x0 B_0x1 resets the DDRC APB interface 0x1 DDRCAXIRST DDRCAXIRST 15 1 read-write B_0x0 does not reset the DDRC AXI interface 0x0 B_0x1 resets the DDRC AXI interface 0x1 DDRCKMOD DDRCKMOD 20 3 read-write B_0x0 Normal mode: the gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. The gating of the ddrc_ker_ckg clock depends on the DDRCxEN, DDRCxLPEN and MPU mode. This mode must be selected during DDRC and DDRPHYC initialization phase, and if the application is using the software self-refresh (SSR). 0x0 B_0x1 Automatic Self-Refresh mode (ASR1): the clock ddrc_ker_ckg is gated automatically according to cactive_ddrc signal. The gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. 0x1 B_0x2 Hardware Self-Refresh mode (HSR1): the gating of the ddrc_ker_ckg clock is controlled by the AXI-Low-Power interface connected to the DDRC. The gating of the dphy_ker_ck clock depends on the DDRPHYCEN, DDRPHYCLPEN and MPU mode. 0x2 B_0x5 Full Automatic Self-Refresh mode (ASR2): the clocks ddrc_ker_ckg and dphy_ker_ck are gated automatically according to cactive_ddrc signal. 0x5 B_0x6 Full Hardware Self-Refresh mode (HSR2): the gating of ddrc_ker_ckg and dphy_ker_ck clocks are controlled by the AXI-Low-Power interface connected to the DDRC. 0x6 DDRCORERST DDRCORERST 16 1 read-write B_0x0 does not reset the DDRC core 0x0 B_0x1 resets the DDRC core 0x1 DDRPHYCAPBEN DDRPHYCAPBEN 9 1 read-write B_0x0 means that the APB clock is disabled 0x0 B_0x1 means that the APB clock is enabled 0x1 DDRPHYCAPBLPEN DDRPHYCAPBLPEN 10 1 read-write B_0x0 means that the APB clock is disabled in CSLEEP 0x0 B_0x1 means that the APB clock is enabled in CSLEEP 0x1 DDRPHYCEN DDRPHYCEN 4 1 read-write B_0x0 means that the peripheral clocks are disabled 0x0 B_0x1 means that the peripheral clocks are enabled 0x1 DDRPHYCLPEN DDRPHYCLPEN 5 1 read-write B_0x0 means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 means that the peripheral clocks are enabled in CSLEEP 0x1 DFILP_WIDTH DFILP_WIDTH 25 3 read-write B_0x0 Bypass, delay disabled 0x0 B_0x1 Forces a delay of 160 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 120 and 160 MHz. 0x1 B_0x2 Forces a delay of 224 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 160 and 220 MHz. 0x2 B_0x3 Forces a delay of 320 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 220 and 320 MHz. 0x3 B_0x4 Forces a delay of 416 x Tdphy_ker_ck to be used when Fdphy_ker_ck is between 320 and 410 MHz. 0x4 DPHYAPBRST DPHYAPBRST 17 1 read-write B_0x0 does not reset the DDRPHYC APB interface 0x0 B_0x1 resets the DDRPHYC APB interface 0x1 DPHYCTLRST DPHYCTLRST 19 1 read-write B_0x0 does not reset the DDRPHYC Control 0x0 B_0x1 resets the DDRPHYC Control 0x1 DPHYRST DPHYRST 18 1 read-write B_0x0 does not reset the DDRPHYC 0x0 B_0x1 resets the DDRPHYC 0x1 GSKPCTRL GSKPCTRL 24 1 read-write B_0x0 The GSKP block is providing the clock phy_out_ck (provided by the DDRPHYC) 0x0 B_0x1 The GSKP block is providing the clock dphy_ker_ck (provided by the RCC) 0x1 GSKPMOD GSKPMOD 23 1 read-write B_0x0 The GSKP block is controlled by the GSKPCTRL bit. 0x0 B_0x1 The GSKP block is controlled automatically by the DFI. 0x1 GSKP_DUR GSKP_DUR 28 4 read-write B_0x0 Sets a delay of 32 x Tdphy_ker_ck 0x0 B_0x1 Sets a delay of 2 x 32 x Tdphy_ker_ck 0x1 B_0x2 Sets a delay of 3 x 32 x Tdphy_ker_ck 0x2 B_0xF Sets a delay of 16 x 32 x Tdphy_ker_ck 0xF KERDCG_DLY KERDCG_DLY 11 3 read-write B_0x0 1 period of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg. 0x0 B_0x1 3 periods of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg. 0x1 B_0x7 15 periods of ddrc_ker_ck between cactive_ddrc falling edge and the gating of ddrc_ker_ckg. 0x7 DSICKSELR RCC_DSICKSELR This register is used to control the selection of the kernel clock for the DSI block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x924 32 read-write n 0x0 0x0 DSISRC DSISRC 0 1 read-write B_0x0 DSI clock from PHY is selected as DSI byte lane clock (default after reset) 0x0 B_0x1 pll4_p_ck clock selected as DSI byte lane clock 0x1 ETHCKSELR RCC_ETHCKSELR This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8FC 32 read-write n 0x0 0x0 ETHPTPDIV ETHPTPDIV 4 4 read-write B_0x0 bypass (default after reset) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF ETHSRC ETHSRC 0 2 read-write B_0x0 pll4_p_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 FDCANCKSELR RCC_FDCANCKSELR This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x90C 32 read-write n 0x0 0x0 FDCANSRC FDCANSRC 0 2 read-write B_0x0 hse_ker_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll4_q_ck clock selected as kernel peripheral clock 0x2 FMCCKSELR RCC_FMCCKSELR This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x904 32 read-write n 0x0 0x0 FMCSRC FMCSRC 0 2 read-write B_0x0 aclk clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll4_p_ck clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 HSICFGR RCC_HSICFGR This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x18 32 read-write n 0x0 0x0 HSICAL HSICAL 16 12 read-only HSIDIV HSIDIV 0 2 read-write B_0x0 Division by 1, hsi_ck (hsi_ker_ck) = 64 MHz (default after reset) 0x0 B_0x1 Division by 2, hsi_ck (hsi_ker_ck) = 32 MHz 0x1 B_0x2 Division by 4, hsi_ck (hsi_ker_ck) = 16 MHz 0x2 B_0x3 Division by 8, hsi_ck (hsi_ker_ck) = 8 MHz 0x3 HSITRIM HSITRIM 8 7 read-write B_0x0 bsec_hsi_cal[11:0] (default after reset) 0x0 B_0x3E bsec_hsi_cal[11:0] + 62 0x3E B_0x3F bsec_hsi_cal[11:0] + 63 0x3F B_0x40 bsec_hsi_cal[11:0] - 64 0x40 B_0x41 bsec_hsi_cal[11:0] - 63 0x41 I2C12CKSELR RCC_I2C12CKSELR This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8C0 32 read-write n 0x0 0x0 I2C12SRC I2C12SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 I2C35CKSELR RCC_I2C35CKSELR This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8C4 32 read-write n 0x0 0x0 I2C35SRC I2C35SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 I2C4CKSELR RCC_I2C4CKSELR This register is used to control the selection of the kernel clock for the I2C4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode. 0xC0 32 read-write n 0x0 0x0 I2C46SRC I2C46SRC 0 3 read-write B_0x0 pclk5 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 IDR RCC_IDR This register gives the unique identifier of the RCC 0xFF8 32 read-only n 0x0 0x0 ID ID 0 32 read-only LPTIM1CKSELR RCC_LPTIM1CKSELR This register is used to control the selection of the kernel clock for the LPTIM1 block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x934 32 read-write n 0x0 0x0 LPTIM1SRC LPTIM1SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_p_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll3_q_ck clock selected as kernel peripheral clock 0x2 B_0x3 lse_ck clock selected as kernel peripheral clock 0x3 B_0x4 lsi_ck clock selected as kernel peripheral clock 0x4 B_0x5 per_ck clock selected as kernel peripheral clock 0x5 LPTIM23CKSELR RCC_LPTIM23CKSELR This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x930 32 read-write n 0x0 0x0 LPTIM23SRC LPTIM23SRC 0 3 read-write B_0x0 pclk3 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 per_ck clock selected as kernel peripheral clock 0x2 B_0x3 lse_ck clock selected as kernel peripheral clock 0x3 B_0x4 lsi_ck clock selected as kernel peripheral clock 0x4 LPTIM45CKSELR RCC_LPTIM45CKSELR This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x92C 32 read-write n 0x0 0x0 LPTIM45SRC LPTIM45SRC 0 3 read-write B_0x0 pclk3 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_p_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll3_q_ck clock selected as kernel peripheral clock 0x2 B_0x3 lse_ck clock selected as kernel peripheral clock 0x3 B_0x4 lsi_ck clock selected as kernel peripheral clock 0x4 B_0x5 per_ck clock selected as kernel peripheral clock 0x5 MCO1CFGR RCC_MCO1CFGR This register is used to select the clock generated on MCO1 output. 0x800 32 read-write n 0x0 0x0 MCO1DIV MCO1DIV 4 4 read-write B_0x0 bypass (default after reset) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF MCO1ON MCO1ON 12 1 read-write B_0x0 The MCO1 output is disabled 0x0 B_0x1 The MCO1 output is enabled 0x1 MCO1SEL MCO1SEL 0 3 read-write B_0x0 HSI clock selected (hsi_ck) (default after reset) 0x0 B_0x1 HSE clock selected (hse_ck) 0x1 B_0x2 CSI clock selected (csi_ck) 0x2 B_0x3 LSI clock selected (lsi_ck) 0x3 B_0x4 LSE oscillator clock selected (lse_ck) 0x4 MCO2CFGR RCC_MCO2CFGR This register is used to select the clock generated on MCO2 output. 0x804 32 read-write n 0x0 0x0 MCO2DIV MCO2DIV 4 4 read-write B_0x0 bypass (default after reset) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF MCO2ON MCO2ON 12 1 read-write B_0x0 The MCO2 output is disabled 0x0 B_0x1 The MCO2 output is enabled 0x1 MCO2SEL MCO2SEL 0 3 read-write B_0x0 MPU clock selected (mpuss_ck) (default after reset) 0x0 B_0x1 AXI clock selected (axiss_ck) 0x1 B_0x2 MCU clock selected (mcuss_ck) 0x2 B_0x3 PLL4 clock selected (pll4_p_ck) 0x3 B_0x4 HSE clock selected (hse_ck) 0x4 B_0x5 HSI clock selected (hsi_ck) 0x5 MCUDIVR RCC_MCUDIVR This register is used to control the MCU sub-system clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x830 32 read-write n 0x0 0x0 MCUDIV MCUDIV 0 4 read-write B_0x0 mcuss_ck not divided (default after reset) 0x0 B_0x1 mcuss_ck divided by 2 0x1 B_0x2 mcuss_ck divided by 4 0x2 B_0x3 mcuss_ck divided by 8 0x3 B_0x4 mcuss_ck divided by 16 0x4 B_0x5 mcuss_ck divided by 32 0x5 B_0x6 mcuss_ck divided by 64 0x6 B_0x7 mcuss_ck divided by 128 0x7 B_0x8 mcuss_ck divided by 256 0x8 MCUDIVRDY MCUDIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 MC_AHB2ENCLRR RCC_MC_AHB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA9C 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA1EN DMA1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA2EN DMA2EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMAMUXEN DMAMUXEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC3EN SDMMC3EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBOEN USBOEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB2ENSETR RCC_MC_AHB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA98 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA1EN DMA1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA2EN DMA2EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMAMUXEN DMAMUXEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC3EN SDMMC3EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBOEN USBOEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB2LPENCLRR RCC_MC_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB9C 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA1LPEN DMA1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA2LPEN DMA2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMAMUXLPEN DMAMUXLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC3LPEN SDMMC3LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBOLPEN USBOLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB2LPENSETR RCC_MC_AHB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB98 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA1LPEN DMA1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA2LPEN DMA2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMAMUXLPEN DMAMUXLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC3LPEN SDMMC3LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBOLPEN USBOLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB3ENCLRR RCC_MC_AHB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAA4 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP2EN CRYP2EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DCMIEN DCMIEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH2EN HASH2EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HSEMEN HSEMEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IPCCEN IPCCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG2EN RNG2EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB3ENSETR RCC_MC_AHB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAA0 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP2EN CRYP2EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DCMIEN DCMIEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH2EN HASH2EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HSEMEN HSEMEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IPCCEN IPCCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG2EN RNG2EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB3LPENCLRR RCC_MC_AHB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBA4 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 CRYP2LPEN CRYP2LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DCMILPEN DCMILPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH2LPEN HASH2LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HSEMLPEN HSEMLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IPCCLPEN IPCCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG2LPEN RNG2LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB3LPENSETR RCC_MC_AHB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBA0 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 CRYP2LPEN CRYP2LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DCMILPEN DCMILPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH2LPEN HASH2LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HSEMLPEN HSEMLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IPCCLPEN IPCCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG2LPEN RNG2LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB4ENCLRR RCC_MC_AHB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAAC 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOBEN GPIOBEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOCEN GPIOCEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIODEN GPIODEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOEEN GPIOEEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOFEN GPIOFEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOGEN GPIOGEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOHEN GPIOHEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOIEN GPIOIEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOJEN GPIOJEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOKEN GPIOKEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB4ENSETR RCC_MC_AHB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAA8 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOBEN GPIOBEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOCEN GPIOCEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIODEN GPIODEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOEEN GPIOEEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOFEN GPIOFEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOGEN GPIOGEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOHEN GPIOHEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOIEN GPIOIEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOJEN GPIOJEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOKEN GPIOKEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB4LPENCLRR RCC_MC_AHB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBAC 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOBLPEN GPIOBLPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOCLPEN GPIOCLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIODLPEN GPIODLPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOELPEN GPIOELPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOFLPEN GPIOFLPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOGLPEN GPIOGLPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOHLPEN GPIOHLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOILPEN GPIOILPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOJLPEN GPIOJLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOKLPEN GPIOKLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB4LPENSETR RCC_MC_AHB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBA8 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOBLPEN GPIOBLPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOCLPEN GPIOCLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIODLPEN GPIODLPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOELPEN GPIOELPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOFLPEN GPIOFLPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOGLPEN GPIOGLPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOHLPEN GPIOHLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOILPEN GPIOILPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOJLPEN GPIOJLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOKLPEN GPIOKLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB5ENCLRR RCC_MC_AHB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x294 32 read-write n 0x0 0x0 BKPSRAMEN BKPSRAMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP1EN CRYP1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOZEN GPIOZEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH1EN HASH1EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG1EN RNG1EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB5ENSETR RCC_MC_AHB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x290 32 read-write n 0x0 0x0 BKPSRAMEN BKPSRAMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP1EN CRYP1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOZEN GPIOZEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH1EN HASH1EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG1EN RNG1EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB5LPENCLRR RCC_MC_AHB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x394 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the clock in CSLEEP, reading means that the clock is enabled in CSLEEP 0x1 CRYP1LPEN CRYP1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOZLPEN GPIOZLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH1LPEN HASH1LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG1LPEN RNG1LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB5LPENSETR RCC_MC_AHB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x390 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clock in CSLEEP, reading means that the clock is enabled in CSLEEP 0x1 CRYP1LPEN CRYP1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOZLPEN GPIOZLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH1LPEN HASH1LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG1LPEN RNG1LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB6ENCLRR RCC_MC_AHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x29C 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 ETHCKEN ETHCKEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled 0x0 B_0x1 Writing disables the eth_ker_ck clock, reading means that the eth_ker_ck clock is enabled 0x1 ETHMACEN ETHMACEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clock is disabled 0x0 B_0x1 Writing disables the bus interface clock, reading means that the bus interface clock is enabled 0x1 ETHRXEN ETHRXEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled 0x0 B_0x1 Writing disables the reception clock, reading means that the reception clock is enabled 0x1 ETHTXEN ETHTXEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled 0x0 B_0x1 Writing disables the transmission clock, reading means that the transmission clock is enabled 0x1 FMCEN FMCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPUEN GPUEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 QSPIEN QSPIEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC1EN SDMMC1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC2EN SDMMC2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBHEN USBHEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB6ENSETR RCC_MC_AHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x298 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 ETHCKEN ETHCKEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled 0x0 B_0x1 Writing enables the eth_ker_ck clock, reading means that the eth_ker_ck clock is enabled 0x1 ETHMACEN ETHMACEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clock is disabled 0x0 B_0x1 Writing enables the bus interface clock, reading means that the bus interface clock is enabled 0x1 ETHRXEN ETHRXEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled 0x0 B_0x1 Writing enables the reception clock, reading means that the reception clock is enabled 0x1 ETHTXEN ETHTXEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled 0x0 B_0x1 Writing enables the transmission clock, reading means that the transmission clock is enabled 0x1 FMCEN FMCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPUEN GPUEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 QSPIEN QSPIEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC1EN SDMMC1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC2EN SDMMC2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBHEN USBHEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_AHB6LPENCLRR RCC_MC_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x39C 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 ETHCKLPEN ETHCKLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the eth_ker_ck clock in CSLEEP, reading means that the eth_ker_ck clock is enabled in CSLEEP 0x1 ETHMACLPEN ETHMACLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the bus interface clocks in CSLEEP, reading means that the bus interface clocks are enabled in CSLEEP 0x1 ETHRXLPEN ETHRXLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the reception clock in CSLEEP, reading means that the reception clock is enabled in CSLEEP 0x1 ETHSTPEN ETHSTPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the ETH RX and TX kernel clocks are gated in CSTOP 0x0 B_0x1 Writing disabled the ETH RX and TX kernel clocks in CSTOP, reading means that the ETH RX and TX kernel clocks are enabled in CSTOP 0x1 ETHTXLPEN ETHTXLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the transmission clock in CSLEEP, reading means that the transmission clock is enabled in CSLEEP 0x1 FMCLPEN FMCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPULPEN GPULPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 QSPILPEN QSPILPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC1LPEN SDMMC1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC2LPEN SDMMC2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBHLPEN USBHLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AHB6LPENSETR RCC_MC_AHB6LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x398 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 ETHCKLPEN ETHCKLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the eth_ker_ck clock in CSLEEP, reading means that the eth_ker_ck clock is enabled in CSLEEP 0x1 ETHMACLPEN ETHMACLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the bus interface clocks in CSLEEP, reading means that the bus interface clocks are enabled in CSLEEP 0x1 ETHRXLPEN ETHRXLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the reception clock in CSLEEP, reading means that the reception clock is enabled in CSLEEP 0x1 ETHSTPEN ETHSTPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the ETH RX and TX kernel clocks are gated in CSTOP 0x0 B_0x1 Writing enables the ETH RX and TX kernel clocks in CSTOP, reading means that the ETH RX and TX kernel clocks are enabled in CSTOP 0x1 ETHTXLPEN ETHTXLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the transmission clock in CSLEEP, reading means that the transmission clock is enabled in CSLEEP 0x1 FMCLPEN FMCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPULPEN GPULPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 QSPILPEN QSPILPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC1LPEN SDMMC1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC2LPEN SDMMC2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBHLPEN USBHLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB1ENCLRR RCC_MC_APB1ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . 0xA84 32 read-write n 0x0 0x0 CECEN CECEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DAC12EN DAC12EN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C1EN I2C1EN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C2EN I2C2EN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C3EN I2C3EN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C5EN I2C5EN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM1EN LPTIM1EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDIOSEN MDIOSEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPDIFEN SPDIFEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI2EN SPI2EN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI3EN SPI3EN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM12EN TIM12EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM13EN TIM13EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM14EN TIM14EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM2EN TIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM3EN TIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM4EN TIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM5EN TIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM6EN TIM6EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM7EN TIM7EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART4EN UART4EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART5EN UART5EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART7EN UART7EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART8EN UART8EN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART2EN USART2EN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART3EN USART3EN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB1ENSETR RCC_MC_APB1ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . 0xA80 32 read-write n 0x0 0x0 CECEN CECEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DAC12EN DAC12EN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C1EN I2C1EN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C2EN I2C2EN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C3EN I2C3EN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C5EN I2C5EN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM1EN LPTIM1EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDIOSEN MDIOSEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPDIFEN SPDIFEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI2EN SPI2EN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI3EN SPI3EN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM12EN TIM12EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM13EN TIM13EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM14EN TIM14EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM2EN TIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM3EN TIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM4EN TIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM5EN TIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM6EN TIM6EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM7EN TIM7EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART4EN UART4EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART5EN UART5EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART7EN UART7EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART8EN UART8EN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART2EN USART2EN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART3EN USART3EN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 WWDG1EN WWDG1EN 28 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB1LPENCLRR RCC_MC_APB1LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding peripherals located into the APB1 bus. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB84 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DAC12LPEN DAC12LPEN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C1LPEN I2C1LPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C2LPEN I2C2LPEN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C3LPEN I2C3LPEN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C5LPEN I2C5LPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM1LPEN LPTIM1LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDIOSLPEN MDIOSLPEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPDIFLPEN SPDIFLPEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI2LPEN SPI2LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI3LPEN SPI3LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM12LPEN TIM12LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM13LPEN TIM13LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM14LPEN TIM14LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM2LPEN TIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM3LPEN TIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM4LPEN TIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM5LPEN TIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM6LPEN TIM6LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM7LPEN TIM7LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART4LPEN UART4LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART5LPEN UART5LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART7LPEN UART7LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART8LPEN UART8LPEN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART2LPEN USART2LPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART3LPEN USART3LPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 WWDG1LPEN WWDG1LPEN 28 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB1LPENSETR RCC_MC_APB1LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB80 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DAC12LPEN DAC12LPEN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C1LPEN I2C1LPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C2LPEN I2C2LPEN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C3LPEN I2C3LPEN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C5LPEN I2C5LPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM1LPEN LPTIM1LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDIOSLPEN MDIOSLPEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPDIFLPEN SPDIFLPEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI2LPEN SPI2LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI3LPEN SPI3LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM12LPEN TIM12LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM13LPEN TIM13LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM14LPEN TIM14LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM2LPEN TIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM3LPEN TIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM4LPEN TIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM5LPEN TIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM6LPEN TIM6LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM7LPEN TIM7LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART4LPEN UART4LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART5LPEN UART5LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART7LPEN UART7LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART8LPEN UART8LPEN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART2LPEN USART2LPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART3LPEN USART3LPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 WWDG1LPEN WWDG1LPEN 28 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB2ENCLRR RCC_MC_APB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA8C 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DFSDMEN DFSDMEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 FDCANEN FDCANEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI1EN SAI1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI2EN SAI2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI3EN SAI3EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI1EN SPI1EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI4EN SPI4EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI5EN SPI5EN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM15EN TIM15EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM16EN TIM16EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM17EN TIM17EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM1EN TIM1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM8EN TIM8EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART6EN USART6EN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB2ENSETR RCC_MC_APB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA88 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DFSDMEN DFSDMEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 FDCANEN FDCANEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI1EN SAI1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI2EN SAI2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI3EN SAI3EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI1EN SPI1EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI4EN SPI4EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI5EN SPI5EN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM15EN TIM15EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM16EN TIM16EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM17EN TIM17EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM1EN TIM1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM8EN TIM8EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART6EN USART6EN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB2LPENCLRR RCC_MC_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB8C 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DFSDMLPEN DFSDMLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 FDCANLPEN FDCANLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI1LPEN SAI1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI2LPEN SAI2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI3LPEN SAI3LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI1LPEN SPI1LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI4LPEN SPI4LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI5LPEN SPI5LPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM15LPEN TIM15LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM16LPEN TIM16LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM17LPEN TIM17LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM1LPEN TIM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM8LPEN TIM8LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART6LPEN USART6LPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB2LPENSETR RCC_MC_APB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB88 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DFSDMLPEN DFSDMLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 FDCANLPEN FDCANLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI1LPEN SAI1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI2LPEN SAI2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI3LPEN SAI3LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI1LPEN SPI1LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI4LPEN SPI4LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI5LPEN SPI5LPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM15LPEN TIM15LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM16LPEN TIM16LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM17LPEN TIM17LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM1LPEN TIM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM8LPEN TIM8LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART6LPEN USART6LPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB3ENCLRR RCC_MC_APB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA94 32 read-write n 0x0 0x0 HDPEN HDPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM2EN LPTIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM3EN LPTIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM4EN LPTIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM5EN LPTIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 PMBCTRLEN PMBCTRLEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI4EN SAI4EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SYSCFGEN SYSCFGEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TMPSENSEN TMPSENSEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 VREFEN VREFEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB3ENSETR RCC_MC_APB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA90 32 read-write n 0x0 0x0 HDPEN HDPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM2EN LPTIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM3EN LPTIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM4EN LPTIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM5EN LPTIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 PMBCTRLEN PMBCTRLEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI4EN SAI4EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SYSCFGEN SYSCFGEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TMPSENSEN TMPSENSEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 VREFEN VREFEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB3LPENCLRR RCC_MC_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB94 32 read-write n 0x0 0x0 LPTIM2LPEN LPTIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM3LPEN LPTIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM4LPEN LPTIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM5LPEN LPTIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 PMBCTRLLPEN PMBCTRLLPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI4LPEN SAI4LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SYSCFGLPEN SYSCFGLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TMPSENSLPEN TMPSENSLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 VREFLPEN VREFLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB3LPENSETR RCC_MC_APB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB90 32 read-write n 0x0 0x0 LPTIM2LPEN LPTIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM3LPEN LPTIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM4LPEN LPTIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM5LPEN LPTIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 PMBCTRLLPEN PMBCTRLLPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI4LPEN SAI4LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SYSCFGLPEN SYSCFGLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TMPSENSLPEN TMPSENSLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 VREFLPEN VREFLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB4ENCLRR RCC_MC_APB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x284 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing disables the APB clock, reading means that the APB clock is enabled 0x1 DSIEN DSIEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LTDCEN LTDCEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENROEN STGENROEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBPHYEN USBPHYEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB4ENSETR RCC_MC_APB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x280 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing enables the APB clock, reading means that the APB clock is enabled 0x1 DSIEN DSIEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LTDCEN LTDCEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENROEN STGENROEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBPHYEN USBPHYEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB4LPENCLRR RCC_MC_APB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x384 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 DSILPEN DSILPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LTDCLPEN LTDCLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROLPEN STGENROLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROSTPEN STGENROSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing disables the clock in CSTOP, reading means that the clock are enabled in CSTOP 0x1 USBPHYLPEN USBPHYLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB4LPENSETR RCC_MC_APB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x380 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 DSILPEN DSILPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LTDCLPEN LTDCLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROLPEN STGENROLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROSTPEN STGENROSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing enables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 USBPHYLPEN USBPHYLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB5ENCLRR RCC_MC_APB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x28C 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C4EN I2C4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C6EN I2C6EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RTCAPBEN RTCAPBEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI6EN SPI6EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENEN STGENEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TZC1EN TZC1EN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 0x0 B_0x1 Writing disables the AXI port 1 peripheral clocks, reading means that the peripheral clocks are enabled for AXI port 1 0x1 TZC2EN TZC2EN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 0x0 B_0x1 Writing disables the AXI port 2 peripheral clocks, reading means that the peripheral clocks are enabled for AXI port 2 0x1 TZPCEN TZPCEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART1EN USART1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB5ENSETR RCC_MC_APB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x288 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C4EN I2C4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C6EN I2C6EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RTCAPBEN RTCAPBEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI6EN SPI6EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENEN STGENEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TZC1EN TZC1EN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc1 clocks, reading means that the clocks are enabled for AXI port 1 0x1 TZC2EN TZC2EN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc2 clocks, reading means that the clocks are enabled for AXI port 2 0x1 TZPCEN TZPCEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART1EN USART1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MC_APB5LPENCLRR RCC_MC_APB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x38C 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C4LPEN I2C4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C6LPEN I2C6LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RTCAPBLPEN RTCAPBLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI6LPEN SPI6LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENLPEN STGENLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENSTPEN STGENSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing disables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 TZC1LPEN TZC1LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 in CSLEEP 0x0 B_0x1 Writing disables the AXI port 1 peripheral clocks in CSLEEP, reading means that the clocks are enabled for AXI port 1 in CSLEEP 0x1 TZC2LPEN TZC2LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 in CSLEEP 0x0 B_0x1 Writing disables the AXI port 2 peripheral clocks in CSLEEP, reading means that the clocks are enabled for AXI port 2 in CSLEEP 0x1 TZPCLPEN TZPCLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART1LPEN USART1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_APB5LPENSETR RCC_MC_APB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x388 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C4LPEN I2C4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C6LPEN I2C6LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RTCAPBLPEN RTCAPBLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI6LPEN SPI6LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENLPEN STGENLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENSTPEN STGENSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing enables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 TZC1LPEN TZC1LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 in CSLEEP 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc1 clocks in CSLEEP, reading means that the clocks are enabled for AXI port 1 in CSLEEP 0x1 TZC2LPEN TZC2LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 in CSLEEP 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc2 clocks in CSLEEP, reading means that the clocks are enabled for AXI port 2 in CSLEEP 0x1 TZPCLPEN TZPCLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART1LPEN USART1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MC_AXIMENCLRR RCC_MC_AXIMENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAB4 32 read-write n 0x0 0x0 SYSRAMEN SYSRAMEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MCU 0x0 B_0x1 Writing deallocates the memory to the MCU, reading means that the memory is allocated to the MCU. 0x1 MC_AXIMENSETR RCC_MC_AXIMENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAB0 32 read-write n 0x0 0x0 SYSRAMEN SYSRAMEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MCU 0x0 B_0x1 Writing allocates the memory to the MCU, reading means that the memory is allocated to the MCU. 0x1 MC_AXIMLPENCLRR RCC_MC_AXIMLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBB4 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MC_AXIMLPENSETR RCC_MC_AXIMLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBB0 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface clock is enabled in CSLEEP 0x1 MC_CIER RCC_MC_CIER This register shall be used by the MCU to control the interrupt source enable. Please refer to Section1.5: RCC Interrupts for more details. 0xC14 32 read-write n 0x0 0x0 CSIRDYIE CSIRDYIE 4 1 read-write B_0x0 CSI ready interrupt disabled (default after reset) 0x0 B_0x1 CSI ready interrupt enabled 0x1 HSERDYIE HSERDYIE 3 1 read-write B_0x0 HSE ready interrupt disabled (default after reset) 0x0 B_0x1 HSE ready interrupt enabled 0x1 HSIRDYIE HSIRDYIE 2 1 read-write B_0x0 HSI ready interrupt disabled (default after reset) 0x0 B_0x1 HSI ready interrupt enabled 0x1 LSECSSIE LSECSSIE 16 1 read-write B_0x0 LSE CSS interrupt disabled (default after reset) 0x0 B_0x1 LSE CSS interrupt enabled 0x1 LSERDYIE LSERDYIE 1 1 read-write B_0x0 LSE ready interrupt disabled (default after reset) 0x0 B_0x1 LSE ready interrupt enabled 0x1 LSIRDYIE LSIRDYIE 0 1 read-write B_0x0 LSI ready interrupt disabled (default after reset) 0x0 B_0x1 LSI ready interrupt enabled 0x1 PLL1DYIE PLL1DYIE 8 1 read-write B_0x0 PLL1 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL1 lock interrupt enabled 0x1 PLL2DYIE PLL2DYIE 9 1 read-write B_0x0 PLL2 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL2 lock interrupt enabled 0x1 PLL3DYIE PLL3DYIE 10 1 read-write B_0x0 PLL3 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL3 lock interrupt enabled 0x1 PLL4DYIE PLL4DYIE 11 1 read-write B_0x0 PLL4 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL4 lock interrupt enabled 0x1 WKUPIE WKUPIE 20 1 read-write B_0x0 Wake-up interrupt disabled (default after reset) 0x0 B_0x1 Wake-up interrupt enabled 0x1 MC_CIFR RCC_MC_CIFR This register shall be used by the MCU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Please refer to Section1.5: RCC Interrupts for more details. 0xC18 32 read-write n 0x0 0x0 CSIRDYF CSIRDYF 4 1 read-write B_0x0 No clock ready interrupt caused by the CSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the CSI, writing clears this flag 0x1 HSERDYF HSERDYF 3 1 read-write B_0x0 No clock ready interrupt caused by the HSE (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the HSE, writing clears this flag 0x1 HSIRDYF HSIRDYF 2 1 read-write B_0x0 No clock ready interrupt caused by the HSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the HSI, writing clears this flag 0x1 LSECSSF LSECSSF 16 1 read-write B_0x0 No failure detected on the external 32 kHz oscillator (default after reset) 0x0 B_0x1 A failure is detected on the external 32 kHz oscillator, writing clears this flag 0x1 LSERDYF LSERDYF 1 1 read-write B_0x0 No clock ready interrupt caused by the LSE (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the LSE, writing clears this flag 0x1 LSIRDYF LSIRDYF 0 1 read-write B_0x0 No clock ready interrupt caused by the LSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the LSI, writing clears this flag 0x1 PLL1DYF PLL1DYF 8 1 read-write B_0x0 No clock ready interrupt caused by PLL1 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL1 lock, writing clears this flag 0x1 PLL2DYF PLL2DYF 9 1 read-write B_0x0 No clock ready interrupt caused by PLL2 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL2 lock, writing clears this flag 0x1 PLL3DYF PLL3DYF 10 1 read-write B_0x0 No clock ready interrupt caused by PLL3 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL3 lock, writing clears this flag 0x1 PLL4DYF PLL4DYF 11 1 read-write B_0x0 No clock ready interrupt caused by PLL4 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL4 lock, writing clears this flag 0x1 WKUPF WKUPF 20 1 read-write B_0x0 No wake-up interrupt pending (default after reset) 0x0 B_0x1 Wake-up interrupt pending, writing clears this flag 0x1 MC_MLAHBENCLRR RCC_MC_MLAHBENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xABC 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MCU 0x0 B_0x1 Writing deallocates the memory to the MCU, reading means that the memory is allocated to the MCU. 0x1 MC_MLAHBENSETR RCC_MC_MLAHBENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xAB8 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MCU 0x0 B_0x1 Writing allocates the memory to the MCU, reading means that the memory is allocated to the MCU. 0x1 MC_MLAHBLPENCLRR RCC_MC_MLAHBLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBBC 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM1LPEN SRAM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM2LPEN SRAM2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM3LPEN SRAM3LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MC_MLAHBLPENSETR RCC_MC_MLAHBLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xBB8 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM1LPEN SRAM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM2LPEN SRAM2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP. 0x1 SRAM3LPEN SRAM3LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MC_RSTSCLRR RCC_MC_RSTSCLRR This register is used by the MCU to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Please refer to Section1.3.12: Reset Source Identification for details.This register is located into VDD domain, and is reset by por_rst reset. 0xC00 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 read-write B_0x0 Writing has no effect, reading means that no BOR reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the BORRSTF flag, reading means that a BOR reset occurred 0x1 HCSSRSTF HCSSRSTF 3 1 read-write B_0x0 Writing has no effect, reading means that no HSE CSS reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the HCSSRSTF flag, reading means that a HSE CSS reset occurred 0x1 IWDG1RSTF IWDG1RSTF 8 1 read-write B_0x0 Writing has no effect, reading means that no IWDG1 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the IWDG1RSTF flag, reading means that a IWDG1 reset occurred 0x1 IWDG2RSTF IWDG2RSTF 9 1 read-write B_0x0 Writing has no effect, reading means that no IWDG2 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the IWDG2RSTF flag, reading means that a IWDG2 reset occurred 0x1 MCSYSRSTF MCSYSRSTF 7 1 read-write B_0x0 Writing has no effect, reading means that no system reset generated by the MCU occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the MCURSTF flag, reading means that a system reset generated by the MCU occurred 0x1 MCURSTF MCURSTF 5 1 read-write B_0x0 Writing has no effect, reading means that no MCU reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the MCURSTF flag, reading means that a MCU reset occurred 0x1 MPSYSRSTF MPSYSRSTF 6 1 read-write B_0x0 Writing has no effect, reading means that no system reset generated by the MPU occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the MCURSTF flag, reading means that a system reset generated by the MPU occurred 0x1 PADRSTF PADRSTF 2 1 read-write B_0x0 Writing has no effect, reading means that no PAD reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the PADRSTF flag, reading means that a PAD reset occurred 0x1 PORRSTF PORRSTF 0 1 read-write B_0x0 Writing has no effect, reading means that no POR/PDR reset occurred 0x0 B_0x1 Writing clears the PORRSTF flag, reading means that a POR/PDR reset occurred (default after por_rst reset) 0x1 VCORERSTF VCORERSTF 4 1 read-write B_0x0 Writing has no effect, reading means that VDD_CORE is not the origin of the reset 0x0 B_0x1 Writing clears the VCORERSTF flag, reading means that VDD_CORE is the origin of the reset (default after por_rst reset) 0x1 WWDG1RSTF WWDG1RSTF 10 1 read-write B_0x0 Writing has no effect, reading means that no WWDG1 reset occurred (default after por_rst reset) 0x0 B_0x1 Writing clears the WWDG1RSTF flag, reading means that a WWDG1 reset occurred 0x1 MPCKDIVR RCC_MPCKDIVR This register is used to control the MPU clock prescaler. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. If TZEN = , this register can only be modified in secure mode. 0x2C 32 read-write n 0x0 0x0 MPUDIV MPUDIV 0 3 read-write B_0x0 The MPUDIV is disabled; i.e. no clock generated 0x0 B_0x1 The mpuss_ck is equal to pll1_p_ck divided by 2 (default after reset) 0x1 B_0x2 The mpuss_ck is equal to pll1_p_ck divided by 4 0x2 B_0x3 The mpuss_ck is equal to pll1_p_ck divided by 8 0x3 MPUDIVRDY MPUDIVRDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 MPCKSELR RCC_MPCKSELR This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x20 32 read-write n 0x0 0x0 MPUSRC MPUSRC 0 2 read-write B_0x0 HSI selected as system clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as system clock (hse_ck) 0x1 B_0x2 PLL1 selected as system clock (pll1_p_ck) 0x2 B_0x3 PLL1 via MPUDIV is selected as system clock (pll1_p_ck / 2 MPUDIV). 0x3 MPUSRCRDY MPUSRCRDY 31 1 read-only B_0x0 The MPU switch is not ready: no clock is generated on its output 0x0 B_0x1 The MPU switch is ready: the clock switch is selecting the clock given by MPUSRC field. (default after reset) 0x1 MP_AHB2ENCLRR RCC_MP_AHB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA1C 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA1EN DMA1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA2EN DMA2EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMAMUXEN DMAMUXEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC3EN SDMMC3EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBOEN USBOEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB2ENSETR RCC_MP_AHB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA18 32 read-write n 0x0 0x0 ADC12EN ADC12EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA1EN DMA1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMA2EN DMA2EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DMAMUXEN DMAMUXEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC3EN SDMMC3EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBOEN USBOEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB2LPENCLRR RCC_MP_AHB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB1C 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA1LPEN DMA1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA2LPEN DMA2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMAMUXLPEN DMAMUXLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC3LPEN SDMMC3LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBOLPEN USBOLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB2LPENSETR RCC_MP_AHB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB18 32 read-write n 0x0 0x0 ADC12LPEN ADC12LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA1LPEN DMA1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMA2LPEN DMA2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DMAMUXLPEN DMAMUXLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC3LPEN SDMMC3LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBOLPEN USBOLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB3ENCLRR RCC_MP_AHB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA24 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP2EN CRYP2EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DCMIEN DCMIEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH2EN HASH2EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HSEMEN HSEMEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IPCCEN IPCCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG2EN RNG2EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB3ENSETR RCC_MP_AHB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA20 32 read-write n 0x0 0x0 CRC2EN CRC2EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP2EN CRYP2EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DCMIEN DCMIEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH2EN HASH2EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HSEMEN HSEMEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IPCCEN IPCCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG2EN RNG2EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB3LPENCLRR RCC_MP_AHB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB24 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 CRYP2LPEN CRYP2LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DCMILPEN DCMILPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH2LPEN HASH2LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HSEMLPEN HSEMLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IPCCLPEN IPCCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG2LPEN RNG2LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB3LPENSETR RCC_MP_AHB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB20 32 read-write n 0x0 0x0 CRC2LPEN CRC2LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 CRYP2LPEN CRYP2LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DCMILPEN DCMILPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH2LPEN HASH2LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HSEMLPEN HSEMLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IPCCLPEN IPCCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG2LPEN RNG2LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB4ENCLRR RCC_MP_AHB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA2C 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOBEN GPIOBEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOCEN GPIOCEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIODEN GPIODEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOEEN GPIOEEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOFEN GPIOFEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOGEN GPIOGEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOHEN GPIOHEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOIEN GPIOIEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOJEN GPIOJEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOKEN GPIOKEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB4ENSETR RCC_MP_AHB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA28 32 read-write n 0x0 0x0 GPIOAEN GPIOAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOBEN GPIOBEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOCEN GPIOCEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIODEN GPIODEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOEEN GPIOEEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOFEN GPIOFEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOGEN GPIOGEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOHEN GPIOHEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOIEN GPIOIEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOJEN GPIOJEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOKEN GPIOKEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB4LPENCLRR RCC_MP_AHB4LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB2C 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOBLPEN GPIOBLPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOCLPEN GPIOCLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIODLPEN GPIODLPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOELPEN GPIOELPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOFLPEN GPIOFLPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOGLPEN GPIOGLPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOHLPEN GPIOHLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOILPEN GPIOILPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOJLPEN GPIOJLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOKLPEN GPIOKLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB4LPENSETR RCC_MP_AHB4LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB28 32 read-write n 0x0 0x0 GPIOALPEN GPIOALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOBLPEN GPIOBLPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOCLPEN GPIOCLPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIODLPEN GPIODLPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOELPEN GPIOELPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOFLPEN GPIOFLPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOGLPEN GPIOGLPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOHLPEN GPIOHLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOILPEN GPIOILPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOJLPEN GPIOJLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOKLPEN GPIOKLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB5ENCLRR RCC_MP_AHB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x214 32 read-write n 0x0 0x0 AXIMCEN AXIMCEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 BKPSRAMEN BKPSRAMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP1EN CRYP1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOZEN GPIOZEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH1EN HASH1EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG1EN RNG1EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB5ENSETR RCC_MP_AHB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x210 32 read-write n 0x0 0x0 AXIMCEN AXIMCEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 BKPSRAMEN BKPSRAMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 CRYP1EN CRYP1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPIOZEN GPIOZEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 HASH1EN HASH1EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 RNG1EN RNG1EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB5LPENCLRR RCC_MP_AHB5LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x314 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the clock in CSLEEP, reading means that the clock is enabled in CSLEEP 0x1 CRYP1LPEN CRYP1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOZLPEN GPIOZLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH1LPEN HASH1LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG1LPEN RNG1LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB5LPENSETR RCC_MP_AHB5LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x310 32 read-write n 0x0 0x0 BKPSRAMLPEN BKPSRAMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clock in CSLEEP, reading means that the clock is enabled in CSLEEP 0x1 CRYP1LPEN CRYP1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPIOZLPEN GPIOZLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 HASH1LPEN HASH1LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 RNG1LPEN RNG1LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB6ENCLRR RCC_MP_AHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x21C 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 ETHCKEN ETHCKEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled 0x0 B_0x1 Writing disables the eth_ker_ck clock, reading means that the eth_ker_ck clock is enabled 0x1 ETHMACEN ETHMACEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clock is disabled 0x0 B_0x1 Writing disables the bus interface clock, reading means that the bus interface clock is enabled 0x1 ETHRXEN ETHRXEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled 0x0 B_0x1 Writing disables the reception clock, reading means that the reception clock is enabled 0x1 ETHTXEN ETHTXEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled 0x0 B_0x1 Writing disables the transmission clock, reading means that the transmission clock is enabled 0x1 FMCEN FMCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPUEN GPUEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 QSPIEN QSPIEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC1EN SDMMC1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC2EN SDMMC2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBHEN USBHEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB6ENSETR RCC_MP_AHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x218 32 read-write n 0x0 0x0 CRC1EN CRC1EN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 ETHCKEN ETHCKEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled 0x0 B_0x1 Writing enables the eth_ker_ck clock, reading means that the eth_ker_ck clock is enabled 0x1 ETHMACEN ETHMACEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clock is disabled 0x0 B_0x1 Writing enables the bus interface clock, reading means that the bus interface clock is enabled 0x1 ETHRXEN ETHRXEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled 0x0 B_0x1 Writing enables the reception clock, reading means that the reception clock is enabled 0x1 ETHTXEN ETHTXEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled 0x0 B_0x1 Writing enables the transmission clock, reading means that the transmission clock is enabled 0x1 FMCEN FMCEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 GPUEN GPUEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 QSPIEN QSPIEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC1EN SDMMC1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SDMMC2EN SDMMC2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBHEN USBHEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_AHB6LPENCLRR RCC_MP_AHB6LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x31C 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 ETHCKLPEN ETHCKLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the eth_ker_ck clock in CSLEEP, reading means that the eth_ker_ck clock is enabled in CSLEEP 0x1 ETHMACLPEN ETHMACLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the bus interface clocks in CSLEEP, reading means that the bus interface clocks are enabled in CSLEEP 0x1 ETHRXLPEN ETHRXLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the reception clock in CSLEEP, reading means that the reception clock is enabled in CSLEEP 0x1 ETHSTPEN ETHSTPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the ETH RX and TX kernel clocks are gated in CSTOP 0x0 B_0x1 Writing disabled the ETH RX and TX kernel clocks in CSTOP, reading means that the ETH RX and TX kernel clocks are enabled in CSTOP 0x1 ETHTXLPEN ETHTXLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the transmission clock in CSLEEP, reading means that the transmission clock is enabled in CSLEEP 0x1 FMCLPEN FMCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPULPEN GPULPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 QSPILPEN QSPILPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC1LPEN SDMMC1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC2LPEN SDMMC2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBHLPEN USBHLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_AHB6LPENSETR RCC_MP_AHB6LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x318 32 read-write n 0x0 0x0 CRC1LPEN CRC1LPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 ETHCKLPEN ETHCKLPEN 7 1 read-write B_0x0 Writing has no effect, reading means that eth_ker_ck clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the eth_ker_ck clock in CSLEEP, reading means that the eth_ker_ck clock is enabled in CSLEEP 0x1 ETHMACLPEN ETHMACLPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the bus interface clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the bus interface clocks in CSLEEP, reading means that the bus interface clocks are enabled in CSLEEP 0x1 ETHRXLPEN ETHRXLPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the reception clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the reception clock in CSLEEP, reading means that the reception clock is enabled in CSLEEP 0x1 ETHSTPEN ETHSTPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the ETH RX and TX kernel clocks are gated in CSTOP 0x0 B_0x1 Writing enables the ETH RX and TX kernel clocks in CSTOP, reading means that the ETH RX and TX kernel clocks are enabled in CSTOP 0x1 ETHTXLPEN ETHTXLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the transmission clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the transmission clock in CSLEEP, reading means that the transmission clock is enabled in CSLEEP 0x1 FMCLPEN FMCLPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 GPULPEN GPULPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 QSPILPEN QSPILPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC1LPEN SDMMC1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SDMMC2LPEN SDMMC2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USBHLPEN USBHLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB1ENCLRR RCC_MP_APB1ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to . 0xA04 32 read-write n 0x0 0x0 CECEN CECEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DAC12EN DAC12EN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C1EN I2C1EN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C2EN I2C2EN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C3EN I2C3EN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C5EN I2C5EN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM1EN LPTIM1EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDIOSEN MDIOSEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPDIFEN SPDIFEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI2EN SPI2EN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI3EN SPI3EN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM12EN TIM12EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM13EN TIM13EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM14EN TIM14EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM2EN TIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM3EN TIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM4EN TIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM5EN TIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM6EN TIM6EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM7EN TIM7EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART4EN UART4EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART5EN UART5EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART7EN UART7EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART8EN UART8EN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART2EN USART2EN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART3EN USART3EN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB1ENSETR RCC_MP_APB1ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective value of the corresponding bits. Writing a sets the corresponding bit to . 0xA00 32 read-write n 0x0 0x0 CECEN CECEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DAC12EN DAC12EN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C1EN I2C1EN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C2EN I2C2EN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C3EN I2C3EN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C5EN I2C5EN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM1EN LPTIM1EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MDIOSEN MDIOSEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPDIFEN SPDIFEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI2EN SPI2EN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI3EN SPI3EN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM12EN TIM12EN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM13EN TIM13EN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM14EN TIM14EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM2EN TIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM3EN TIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM4EN TIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM5EN TIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM6EN TIM6EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM7EN TIM7EN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART4EN UART4EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART5EN UART5EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART7EN UART7EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 UART8EN UART8EN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART2EN USART2EN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART3EN USART3EN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB1LPENCLRR RCC_MP_APB1LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bits of the corresponding peripherals located into the APB1 bus. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB04 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DAC12LPEN DAC12LPEN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C1LPEN I2C1LPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C2LPEN I2C2LPEN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C3LPEN I2C3LPEN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C5LPEN I2C5LPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM1LPEN LPTIM1LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDIOSLPEN MDIOSLPEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPDIFLPEN SPDIFLPEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI2LPEN SPI2LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI3LPEN SPI3LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM12LPEN TIM12LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM13LPEN TIM13LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM14LPEN TIM14LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM2LPEN TIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM3LPEN TIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM4LPEN TIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM5LPEN TIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM6LPEN TIM6LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM7LPEN TIM7LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART4LPEN UART4LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART5LPEN UART5LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART7LPEN UART7LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART8LPEN UART8LPEN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART2LPEN USART2LPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART3LPEN USART3LPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB1LPENSETR RCC_MP_APB1LPENSETR This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB00 32 read-write n 0x0 0x0 CECLPEN CECLPEN 27 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DAC12LPEN DAC12LPEN 29 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C1LPEN I2C1LPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C2LPEN I2C2LPEN 22 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C3LPEN I2C3LPEN 23 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C5LPEN I2C5LPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM1LPEN LPTIM1LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MDIOSLPEN MDIOSLPEN 31 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPDIFLPEN SPDIFLPEN 26 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI2LPEN SPI2LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI3LPEN SPI3LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM12LPEN TIM12LPEN 6 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM13LPEN TIM13LPEN 7 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM14LPEN TIM14LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM2LPEN TIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM3LPEN TIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM4LPEN TIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM5LPEN TIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM6LPEN TIM6LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM7LPEN TIM7LPEN 5 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART4LPEN UART4LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART5LPEN UART5LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART7LPEN UART7LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 UART8LPEN UART8LPEN 19 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART2LPEN USART2LPEN 14 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART3LPEN USART3LPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB2ENCLRR RCC_MP_APB2ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA0C 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DFSDMEN DFSDMEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 FDCANEN FDCANEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI1EN SAI1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI2EN SAI2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI3EN SAI3EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI1EN SPI1EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI4EN SPI4EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI5EN SPI5EN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM15EN TIM15EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM16EN TIM16EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM17EN TIM17EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM1EN TIM1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM8EN TIM8EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART6EN USART6EN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB2ENSETR RCC_MP_APB2ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA08 32 read-write n 0x0 0x0 ADFSDMEN ADFSDMEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 DFSDMEN DFSDMEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 FDCANEN FDCANEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI1EN SAI1EN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI2EN SAI2EN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI3EN SAI3EN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI1EN SPI1EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI4EN SPI4EN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI5EN SPI5EN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM15EN TIM15EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM16EN TIM16EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM17EN TIM17EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM1EN TIM1EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TIM8EN TIM8EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART6EN USART6EN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB2LPENCLRR RCC_MP_APB2LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB0C 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DFSDMLPEN DFSDMLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 FDCANLPEN FDCANLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI1LPEN SAI1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI2LPEN SAI2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI3LPEN SAI3LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI1LPEN SPI1LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI4LPEN SPI4LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI5LPEN SPI5LPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM15LPEN TIM15LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM16LPEN TIM16LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM17LPEN TIM17LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM1LPEN TIM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM8LPEN TIM8LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART6LPEN USART6LPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB2LPENSETR RCC_MP_APB2LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB08 32 read-write n 0x0 0x0 ADFSDMLPEN ADFSDMLPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 DFSDMLPEN DFSDMLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 FDCANLPEN FDCANLPEN 24 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI1LPEN SAI1LPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI2LPEN SAI2LPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI3LPEN SAI3LPEN 18 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI1LPEN SPI1LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI4LPEN SPI4LPEN 9 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI5LPEN SPI5LPEN 10 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM15LPEN TIM15LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM16LPEN TIM16LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM17LPEN TIM17LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM1LPEN TIM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TIM8LPEN TIM8LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART6LPEN USART6LPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB3ENCLRR RCC_MP_APB3ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA14 32 read-write n 0x0 0x0 HDPEN HDPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM2EN LPTIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM3EN LPTIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM4EN LPTIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM5EN LPTIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 PMBCTRLEN PMBCTRLEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI4EN SAI4EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SYSCFGEN SYSCFGEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TMPSENSEN TMPSENSEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 VREFEN VREFEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB3ENSETR RCC_MP_APB3ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA10 32 read-write n 0x0 0x0 HDPEN HDPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM2EN LPTIM2EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM3EN LPTIM3EN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM4EN LPTIM4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 LPTIM5EN LPTIM5EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 PMBCTRLEN PMBCTRLEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SAI4EN SAI4EN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SYSCFGEN SYSCFGEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TMPSENSEN TMPSENSEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 VREFEN VREFEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB3LPENCLRR RCC_MP_APB3LPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB14 32 read-write n 0x0 0x0 LPTIM2LPEN LPTIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM3LPEN LPTIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM4LPEN LPTIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM5LPEN LPTIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 PMBCTRLLPEN PMBCTRLLPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI4LPEN SAI4LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SYSCFGLPEN SYSCFGLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TMPSENSLPEN TMPSENSLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 VREFLPEN VREFLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB3LPENSETR RCC_MP_APB3LPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB10 32 read-write n 0x0 0x0 LPTIM2LPEN LPTIM2LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM3LPEN LPTIM3LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM4LPEN LPTIM4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 LPTIM5LPEN LPTIM5LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 PMBCTRLLPEN PMBCTRLLPEN 17 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SAI4LPEN SAI4LPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SYSCFGLPEN SYSCFGLPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 TMPSENSLPEN TMPSENSLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 VREFLPEN VREFLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB4ENCLRR RCC_MP_APB4ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x204 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing disables the APB clock, reading means that the APB clock is enabled 0x1 DSIEN DSIEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IWDG2APBEN IWDG2APBEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing disables the APB clock, reading means that the APB clock is enabled 0x1 LTDCEN LTDCEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENROEN STGENROEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBPHYEN USBPHYEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB4ENSETR RCC_MP_APB4ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x200 32 read-write n 0x0 0x0 DDRPERFMEN DDRPERFMEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing enables the APB clock, reading means that the APB clock is enabled 0x1 DSIEN DSIEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IWDG2APBEN IWDG2APBEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing enables the APB clock, reading means that the APB clock is enabled 0x1 LTDCEN LTDCEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENROEN STGENROEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USBPHYEN USBPHYEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB4LPENCLRR RCC_MP_APB4LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x304 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 DSILPEN DSILPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IWDG2APBLPEN IWDG2APBLPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 LTDCLPEN LTDCLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROLPEN STGENROLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROSTPEN STGENROSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing disables the clock in CSTOP, reading means that the clock are enabled in CSTOP 0x1 USBPHYLPEN USBPHYLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB4LPENSETR RCC_MP_APB4LPENSETR This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0x300 32 read-write n 0x0 0x0 DDRPERFMLPEN DDRPERFMLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 DSILPEN DSILPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IWDG2APBLPEN IWDG2APBLPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 LTDCLPEN LTDCLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROLPEN STGENROLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENROSTPEN STGENROSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing enables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 USBPHYLPEN USBPHYLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB5ENCLRR RCC_MP_APB5ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x20C 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C4EN I2C4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C6EN I2C6EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IWDG1APBEN IWDG1APBEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing disables the APB clock, reading means that the APB clock is enabled 0x1 RTCAPBEN RTCAPBEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI6EN SPI6EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENEN STGENEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TZC1EN TZC1EN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 0x0 B_0x1 Writing disables the AXI port 1 peripheral clocks, reading means that the peripheral clocks are enabled for AXI port 1 0x1 TZC2EN TZC2EN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 0x0 B_0x1 Writing disables the AXI port 2 peripheral clocks, reading means that the peripheral clocks are enabled for AXI port 2 0x1 TZPCEN TZPCEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART1EN USART1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB5ENSETR RCC_MP_APB5ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x208 32 read-write n 0x0 0x0 BSECEN BSECEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C4EN I2C4EN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 I2C6EN I2C6EN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 IWDG1APBEN IWDG1APBEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled 0x0 B_0x1 Writing enables the APB clock, reading means that the APB clock is enabled 0x1 RTCAPBEN RTCAPBEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 SPI6EN SPI6EN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 STGENEN STGENEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 TZC1EN TZC1EN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc1 clocks, reading means that the clocks are enabled for AXI port 1 0x1 TZC2EN TZC2EN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc2 clocks, reading means that the clocks are enabled for AXI port 2 0x1 TZPCEN TZPCEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 USART1EN USART1EN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_APB5LPENCLRR RCC_MP_APB5LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x30C 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C4LPEN I2C4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C6LPEN I2C6LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IWDG1APBLPEN IWDG1APBLPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 RTCAPBLPEN RTCAPBLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI6LPEN SPI6LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENLPEN STGENLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENSTPEN STGENSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing disables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 TZC1LPEN TZC1LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 in CSLEEP 0x0 B_0x1 Writing disables the AXI port 1 peripheral clocks in CSLEEP, reading means that the clocks are enabled for AXI port 1 in CSLEEP 0x1 TZC2LPEN TZC2LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 in CSLEEP 0x0 B_0x1 Writing disables the AXI port 2 peripheral clocks in CSLEEP, reading means that the clocks are enabled for AXI port 2 in CSLEEP 0x1 TZPCLPEN TZPCLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART1LPEN USART1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APB5LPENSETR RCC_MP_APB5LPENSETR This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x308 32 read-write n 0x0 0x0 BSECLPEN BSECLPEN 16 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C4LPEN I2C4LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 I2C6LPEN I2C6LPEN 3 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 IWDG1APBLPEN IWDG1APBLPEN 15 1 read-write B_0x0 Writing has no effect, reading means that the APB clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the APB clock in CSLEEP, reading means that the APB clock is enabled in CSLEEP 0x1 RTCAPBLPEN RTCAPBLPEN 8 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 SPI6LPEN SPI6LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENLPEN STGENLPEN 20 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 STGENSTPEN STGENSTPEN 21 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSTOP 0x0 B_0x1 Writing enables the peripheral clocks in CSTOP, reading means that the peripheral clocks are enabled in CSTOP 0x1 TZC1LPEN TZC1LPEN 11 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 1 in CSLEEP 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc1 clocks in CSLEEP, reading means that the clocks are enabled for AXI port 1 in CSLEEP 0x1 TZC2LPEN TZC2LPEN 12 1 read-write B_0x0 Writing has no effect, reading means that the clocks are disabled for AXI port 2 in CSLEEP 0x0 B_0x1 Writing enables the pclk5 and aclk_tzc2 clocks in CSLEEP, reading means that the clocks are enabled for AXI port 2 in CSLEEP 0x1 TZPCLPEN TZPCLPEN 13 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 USART1LPEN USART1LPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_APRSTCR RCC_MP_APRSTCR This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode. 0x110 32 read-write n 0x0 0x0 RDCTLEN RDCTLEN 0 1 read-write B_0x0 The RDCTL control block is bypassed (default after reset) 0x0 B_0x1 The RDCTL control block is enabled. 0x1 RSTTO RSTTO 8 7 read-write B_0x0 The timeout function is disabled (default after reset) 0x0 B_0x1 The timeout is set to 2 x 2HSIDIV us 0x1 B_0x7F The timeout is set to 128 x 2HSIDIV us 0x7F MP_APRSTSR RCC_MP_APRSTSR This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode. 0x114 32 read-only n 0x0 0x0 RSTTOV RSTTOV 8 7 read-only MP_AXIMLPENCLRR RCC_MP_AXIMLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB34 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MP_AXIMLPENSETR RCC_MP_AXIMLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB30 32 read-write n 0x0 0x0 SYSRAMLPEN SYSRAMLPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface clock is enabled in CSLEEP 0x1 MP_BOOTCR RCC_MP_BOOTCR This register is used to control the HOLD boot function when the system exits from STANDBY. Please refer to Section1.3.13.5: MCU HOLD_BOOT After Processor Reset. This register is reset when a system reset occurs, but not when the circuit exits from STANDBY (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU. 0x100 32 read-write n 0x0 0x0 MCU_BEN MCU_BEN 0 1 read-write B_0x0 The MCU will remain on HOLD_BOOT when the system exits from STANDBY 0x0 B_0x1 The MCU is allowed to restart when the system exits from STANDBY 0x1 MPU_BEN MPU_BEN 1 1 read-write B_0x0 The MPU will remain on CSTANDBY when the system exits from STANDBY 0x0 B_0x1 The MPU is allowed to restart when the system exits from STANDBY 0x1 MP_CIER RCC_MP_CIER This register shall be used by the MPU to control the interrupt source enable. Please refer to Section1.5: RCC Interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x414 32 read-write n 0x0 0x0 CSIRDYIE CSIRDYIE 4 1 read-write B_0x0 CSI ready interrupt disabled (default after reset) 0x0 B_0x1 CSI ready interrupt enabled 0x1 HSERDYIE HSERDYIE 3 1 read-write B_0x0 HSE ready interrupt disabled (default after reset) 0x0 B_0x1 HSE ready interrupt enabled 0x1 HSIRDYIE HSIRDYIE 2 1 read-write B_0x0 HSI ready interrupt disabled (default after reset) 0x0 B_0x1 HSI ready interrupt enabled 0x1 LSECSSIE LSECSSIE 16 1 read-write B_0x0 LSE CSS interrupt disabled (default after reset) 0x0 B_0x1 LSE CSS interrupt enabled 0x1 LSERDYIE LSERDYIE 1 1 read-write B_0x0 LSE ready interrupt disabled (default after reset) 0x0 B_0x1 LSE ready interrupt enabled 0x1 LSIRDYIE LSIRDYIE 0 1 read-write B_0x0 LSI ready interrupt disabled (default after reset) 0x0 B_0x1 LSI ready interrupt enabled 0x1 PLL1DYIE PLL1DYIE 8 1 read-write B_0x0 PLL1 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL1 lock interrupt enabled 0x1 PLL2DYIE PLL2DYIE 9 1 read-write B_0x0 PLL2 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL2 lock interrupt enabled 0x1 PLL3DYIE PLL3DYIE 10 1 read-write B_0x0 PLL3 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL3 lock interrupt enabled 0x1 PLL4DYIE PLL4DYIE 11 1 read-write B_0x0 PLL4 lock interrupt disabled (default after reset) 0x0 B_0x1 PLL4 lock interrupt enabled 0x1 WKUPIE WKUPIE 20 1 read-write B_0x0 Wake-up interrupt disabled (default after reset) 0x0 B_0x1 Wake-up interrupt enabled 0x1 MP_CIFR RCC_MP_CIFR This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Please refer to Section1.5: RCC Interrupts for more details. If TZEN = , this register can only be modified in secure mode. 0x418 32 read-write n 0x0 0x0 CSIRDYF CSIRDYF 4 1 read-write B_0x0 No clock ready interrupt caused by the CSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the CSI, writing clears this flag 0x1 HSERDYF HSERDYF 3 1 read-write B_0x0 No clock ready interrupt caused by the HSE (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the HSE, writing clears this flag 0x1 HSIRDYF HSIRDYF 2 1 read-write B_0x0 No clock ready interrupt caused by the HSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the HSI, writing clears this flag 0x1 LSECSSF LSECSSF 16 1 read-write B_0x0 No failure detected on the external 32 kHz oscillator (default after reset) 0x0 B_0x1 A failure is detected on the external 32 kHz oscillator, writing clears this flag 0x1 LSERDYF LSERDYF 1 1 read-write B_0x0 No clock ready interrupt caused by the LSE (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the LSE, writing clears this flag 0x1 LSIRDYF LSIRDYF 0 1 read-write B_0x0 No clock ready interrupt caused by the LSI (default after reset) 0x0 B_0x1 Clock ready interrupt caused by the LSI, writing clears this flag 0x1 PLL1DYF PLL1DYF 8 1 read-write B_0x0 No clock ready interrupt caused by PLL1 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL1 lock, writing clears this flag 0x1 PLL2DYF PLL2DYF 9 1 read-write B_0x0 No clock ready interrupt caused by PLL2 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL2 lock, writing clears this flag 0x1 PLL3DYF PLL3DYF 10 1 read-write B_0x0 No clock ready interrupt caused by PLL3 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL3 lock, writing clears this flag 0x1 PLL4DYF PLL4DYF 11 1 read-write B_0x0 No clock ready interrupt caused by PLL4 lock (default after reset) 0x0 B_0x1 Clock ready interrupt caused by PLL4 lock, writing clears this flag 0x1 WKUPF WKUPF 20 1 read-write B_0x0 No wake-up interrupt pending (default after reset) 0x0 B_0x1 Wake-up interrupt pending, writing clears this flag 0x1 MP_GCR RCC_MP_GCR The register contains global control bits. If TZEN = , this register can only be modified in secure mode. 0x10C 32 read-write n 0x0 0x0 BOOT_MCU BOOT_MCU 0 1 read-write B_0x0 The MCU will be set in HOLD_BOOT when the next MCU core reset occurs. (default after reset) 0x0 B_0x1 The MCU will not be in HOLD_BOOT mode when the next MCU core reset occurs. 0x1 MP_GRSTCSETR RCC_MP_GRSTCSETR This register is used by the MPU in order to generate either a MCU reset or a system reset. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. 0x404 32 read-write n 0x0 0x0 MCURST MCURST 1 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing generate a reset of the MCU core, reading means that the block reset is asserted 0x1 MPSYSRST MPSYSRST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing generate a system reset, see Figure2. 0x1 MP_IWDGFZCLRR RCC_MP_IWDGFZCLRR This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x410 32 read-write n 0x0 0x0 FZ_IWDG1 FZ_IWDG1 0 1 read-write B_0x0 Writing has no effect, reading means that the IWDG1 clock is not frozen (default after reset) 0x0 B_0x1 Writing unfreeze the IWDG1 clock, reading means that the IWDG1 clock is frozen 0x1 FZ_IWDG2 FZ_IWDG2 1 1 read-write B_0x0 Writing has no effect, reading means that the IWDG2 clock is not frozen (default after reset) 0x0 B_0x1 Writing unfreeze the IWDG2 clock, reading means that the IWDG2 clock is frozen 0x1 MP_IWDGFZSETR RCC_MP_IWDGFZSETR This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x40C 32 read-write n 0x0 0x0 FZ_IWDG1 FZ_IWDG1 0 1 read-write B_0x0 Writing has no effect, reading means that the IWDG1 clock is not frozen (default after reset) 0x0 B_0x1 Writing freeze the IWDG1 clock, reading means that the IWDG1 clock is frozen 0x1 FZ_IWDG2 FZ_IWDG2 1 1 read-write B_0x0 Writing has no effect, reading means that the IWDG2 clock is not frozen (default after reset) 0x0 B_0x1 Writing freeze the IWDG2 clock, reading means that the IWDG2 clock is frozen 0x1 MP_MLAHBENCLRR RCC_MP_MLAHBENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA3C 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MPU 0x0 B_0x1 Writing deallocates the memory to the MPU, reading means that the memory is allocated to the MPU. 0x1 MP_MLAHBENSETR RCC_MP_MLAHBENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xA38 32 read-write n 0x0 0x0 RETRAMEN RETRAMEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory is not allocated by the MPU 0x0 B_0x1 Writing allocates the memory to the MPU, reading means that the memory is allocated to the MPU. 0x1 MP_MLAHBLPENCLRR RCC_MP_MLAHBLPENCLRR This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB3C 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM1LPEN SRAM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM2LPEN SRAM2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM3LPEN SRAM3LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing disables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MP_MLAHBLPENSETR RCC_MP_MLAHBLPENSETR This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . 0xB38 32 read-write n 0x0 0x0 RETRAMLPEN RETRAMLPEN 4 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM1LPEN SRAM1LPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 SRAM2LPEN SRAM2LPEN 1 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP. 0x1 SRAM3LPEN SRAM3LPEN 2 1 read-write B_0x0 Writing has no effect, reading means that the memory interface clock is disabled in CSLEEP 0x0 B_0x1 Writing enables the memory interface clock in CSLEEP, reading means that the memory interface is enabled in CSLEEP 0x1 MP_RSTSR RCC_MP_RSTSR This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from STANDBY or CSTANDBY.The flags can be cleared by simply writing them to . Please refer to Section1.3.12: Reset Source Identification for details.The register is located in VDD_CORE.If TZEN = , this register can only be modified in secure mode. 0x408 32 read-write n 0x0 0x0 BORRSTF BORRSTF 1 1 read-write B_0x0 No BOR reset occurred 0x0 B_0x1 A BOR reset occurred 0x1 CSTDBYRSTF CSTDBYRSTF 12 1 read-write B_0x0 MPU has not been in CSTANDBY mode 0x0 B_0x1 MPU has been in CSTANDBY mode 0x1 HCSSRSTF HCSSRSTF 3 1 read-write B_0x0 No HSE CSS reset occurred 0x0 B_0x1 A HSE CSS reset occurred 0x1 IWDG1RSTF IWDG1RSTF 8 1 read-write B_0x0 No IWDG1 reset occurred 0x0 B_0x1 An IWDG1 reset occurred 0x1 IWDG2RSTF IWDG2RSTF 9 1 read-write B_0x0 No IWDG2 reset occurred 0x0 B_0x1 An IWDG2 reset occurred 0x1 MCSYSRSTF MCSYSRSTF 7 1 read-write B_0x0 No system reset generated by the MCU occurred 0x0 B_0x1 A system reset generated by the MCU occurred 0x1 MPSYSRSTF MPSYSRSTF 6 1 read-write B_0x0 No system reset generated by the MPU occurred 0x0 B_0x1 A system reset generated by the MPU occurred 0x1 PADRSTF PADRSTF 2 1 read-write B_0x0 No PAD reset occurred 0x0 B_0x1 A PAD reset occurred 0x1 PORRSTF PORRSTF 0 1 read-write B_0x0 No POR/PDR reset occurred 0x0 B_0x1 A POR/PDR reset occurred 0x1 SPARE SPARE 13 3 read-write STDBYRSTF STDBYRSTF 11 1 read-write B_0x0 System has not been in STANDBY mode 0x0 B_0x1 System has been in STANDBY mode 0x1 VCORERSTF VCORERSTF 4 1 read-write B_0x0 VDD_CORE is not the origin of the reset 0x0 B_0x1 VDD_CORE is the origin of the reset 0x1 MP_SREQCLRR RCC_MP_SREQCLRR Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x108 32 read-write n 0x0 0x0 STPREQ_P0 STPREQ_P0 0 1 read-write B_0x0 Writing has no effect, reading means that the MPU processor number 0 does not allow the MPU domain to go to CSTOP 0x0 B_0x1 Writing clears the STPREQ_P0 bit, reading means that the MPU processor number 0 allows the MPU domain to go to CSTOP 0x1 STPREQ_P1 STPREQ_P1 1 1 read-write B_0x0 Writing has no effect, reading means that the MPU processor number 1 does not allow the MPU domain to go to CSTOP 0x0 B_0x1 Writing clears the STPREQ_P1 bit, reading means that the MPU processor number 1 allows the MPU domain to go to CSTOP 0x1 MP_SREQSETR RCC_MP_SREQSETR Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode. 0x104 32 read-write n 0x0 0x0 STPREQ_P0 STPREQ_P0 0 1 read-write B_0x0 Writing has no effect, reading means that the MPU processor number 0 does not allow the MPU domain to go to CSTOP 0x0 B_0x1 Writing clears the STPREQ_P0 bit, reading means that the MPU processor number 0 allows the MPU domain to go to CSTOP 0x1 STPREQ_P1 STPREQ_P1 1 1 read-write B_0x0 Writing has no effect, reading means that the MPU processor number 1 does not allow the MPU domain to go to CSTOP 0x0 B_0x1 Writing sets the STPREQ_P1 bit, reading means that the MPU processor number 1 allows the MPU domain to go to CSTOP 0x1 MP_TZAHB6ENCLRR RCC_MP_TZAHB6ENCLRR This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x224 32 read-write n 0x0 0x0 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing disables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_TZAHB6ENSETR RCC_MP_TZAHB6ENSETR This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x220 32 read-write n 0x0 0x0 MDMAEN MDMAEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled 0x0 B_0x1 Writing enables the peripheral clocks, reading means that the peripheral clocks are enabled 0x1 MP_TZAHB6LPENCLRR RCC_MP_TZAHB6LPENCLRR This register is used by the MPU in order to clear the PERxLPEN bit of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x324 32 read-write n 0x0 0x0 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing disables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MP_TZAHB6LPENSETR RCC_MP_TZAHB6LPENSETR This register is used by the MPU in order to set the PERxLPEN bit of the corresponding peripheral to . Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode. 0x320 32 read-write n 0x0 0x0 MDMALPEN MDMALPEN 0 1 read-write B_0x0 Writing has no effect, reading means that the peripheral clocks are disabled in CSLEEP 0x0 B_0x1 Writing enables the peripheral clocks in CSLEEP, reading means that the peripheral clocks are enabled in CSLEEP 0x1 MSSCKSELR RCC_MSSCKSELR This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x48 32 read-write n 0x0 0x0 MCUSSRC MCUSSRC 0 3 read-write B_0x0 HSI selected as system clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as system clock (hse_ck) 0x1 B_0x2 CSI selected as system clock (csi_ck) 0x2 B_0x3 PLL3 selected as system clock (pll3_p_ck) 0x3 MCUSSRCRDY MCUSSRCRDY 31 1 read-only B_0x0 The MCU sub-system switch is not ready or in positions higher than : no clock is generated on its output 0x0 B_0x1 The MCU sub-system switch is ready: the clock switch is selecting the clock given by MCUSSRC field. (default after reset) 0x1 OCENCLRR RCC_OCENCLRR This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x10 32 read-write n 0x0 0x0 CSIKERON CSIKERON 5 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the CSIKERON bit 0x1 CSION CSION 4 1 read-write B_0x0 CSI is OFF 0x0 B_0x1 Clear the CSION bit 0x1 DIGBYP DIGBYP 7 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the DIGBYP bit (analog bypass) 0x1 HSEBYP HSEBYP 10 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the HSEBYP bit 0x1 HSEKERON HSEKERON 9 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the HSEKERON bit 0x1 HSEON HSEON 8 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the HSEON bit 0x1 HSIKERON HSIKERON 1 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the HSIKERON bit 0x1 HSION HSION 0 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the HSION bit 0x1 OCENSETR RCC_OCENSETR This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xC 32 read-write n 0x0 0x0 CSIKERON CSIKERON 5 1 read-write B_0x0 No effect 0x0 B_0x1 Set the CSIKERON bit 0x1 CSION CSION 4 1 read-write B_0x0 No effect 0x0 B_0x1 Set the CSION bit 0x1 DIGBYP DIGBYP 7 1 read-write B_0x0 No effect 0x0 B_0x1 Set DIGBYP bit (digital bypass) 0x1 HSEBYP HSEBYP 10 1 read-write B_0x0 No effect 0x0 B_0x1 Set the HSEBYP bit 0x1 HSECSSON HSECSSON 11 1 read-write B_0x0 Reading means that the Clock Security System on HSE is OFF (default after reset) 0x0 B_0x1 Writing enables the Clock Security System on HSE, reading means that the Clock Security System on HSE is ON 0x1 HSEKERON HSEKERON 9 1 read-write B_0x0 No effect 0x0 B_0x1 Set the HSEKERON bit 0x1 HSEON HSEON 8 1 read-write B_0x0 No effect 0x0 B_0x1 Set HSEON bit 0x1 HSIKERON HSIKERON 1 1 read-write B_0x0 No effect 0x0 B_0x1 Set the HSIKERON bit 0x1 HSION HSION 0 1 read-write B_0x0 No effect 0x0 B_0x1 Set the HSION bit 0x1 OCRDYR RCC_OCRDYR This is a read-only access register, It contains the status flags of oscillators. Writing has no effect. 0x808 32 read-only n 0x0 0x0 AXICKRDY AXICKRDY 24 1 read-only B_0x0 axiss_ck clock is not available (default after reset) 0x0 B_0x1 axiss_ck clock is available 0x1 CKREST CKREST 25 1 read-only B_0x0 The clock restore process is not on-going (default after reset) 0x0 B_0x1 The clock restore process is on-going 0x1 CSIRDY CSIRDY 4 1 read-only B_0x0 CSI clock is not ready (default after reset) 0x0 B_0x1 CSI clock is ready 0x1 HSERDY HSERDY 8 1 read-only B_0x0 HSE clock is not ready (default after reset) 0x0 B_0x1 HSE clock is ready 0x1 HSIDIVRDY HSIDIVRDY 2 1 read-only B_0x0 the new division ratio is not yet propagated to hsi_ck (hsi_ker_ck) (default after reset) 0x0 B_0x1 the hsi_ck (hsi_ker_ck) clock frequency reflects the new HSIDIV value 0x1 HSIRDY HSIRDY 0 1 read-only B_0x0 HSI clock is not ready (default after reset) 0x0 B_0x1 HSI clock is ready 0x1 MPUCKRDY MPUCKRDY 23 1 read-only B_0x0 mpuss_ck clock is not available (default after reset) 0x0 B_0x1 mpuss_ck clock is available 0x1 PLL1CFGR1 RCC_PLL1CFGR1 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x84 32 read-write n 0x0 0x0 DIVM1 DIVM1 16 6 read-write B_0x0 bypass 0x0 B_0x1 division by 2 (default after reset) 0x1 B_0x2 division by 3 0x2 B_0x3F division by 64 0x3F DIVN DIVN 0 9 read-write B_0x18 Division ratio is 25 0x18 B_0x19 Division ratio is 26 0x19 B_0x31 Division ratio is 50 (default after reset) 0x31 B_0x63 Division ratio is 100 0x63 PLL1CFGR2 RCC_PLL1CFGR2 This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x88 32 read-write n 0x0 0x0 DIVP DIVP 0 7 read-write B_0x0 pll1_p_ck = fout1_ck (default after reset) 0x0 B_0x1 pll1_p_ck = fout1_ck / 2 0x1 B_0x2 pll1_p_ck = fout1_ck / 3 0x2 B_0x7F pll1_p_ck = fout1_ck / 128 0x7F DIVQ DIVQ 8 7 read-write B_0x0 pll1_q_ck = fout1_ck 0x0 B_0x1 pll1_q_ck = fout1_ck / 2 (default after reset) 0x1 B_0x2 pll1_q_ck = fout1_ck / 3 0x2 B_0x7F pll1_q_ck = fout1_ck / 128 0x7F DIVR DIVR 16 7 read-write B_0x0 pll1_r_ck = fout1_ck 0x0 B_0x1 pll1_r_ck = fout1_ck / 2 (default after reset) 0x1 B_0x2 pll1_r_ck = fout1_ck / 3 0x2 B_0x7F pll1_r_ck = fout1_ck / 128 0x7F PLL1CR RCC_PLL1CR This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x80 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write B_0x0 pll1_p_ck output is disabled (default after reset) 0x0 B_0x1 pll1_p_ck output is enabled 0x1 DIVQEN DIVQEN 5 1 read-write B_0x0 pll1_q_ck output is disabled (default after reset) 0x0 B_0x1 pll1_q_ck output is enabled 0x1 DIVREN DIVREN 6 1 read-write B_0x0 pll1_r_ck output is disabled (default after reset) 0x0 B_0x1 pll1_r_ck output is enabled 0x1 PLL1RDY PLL1RDY 1 1 read-only B_0x0 PLL1 unlocked (default after reset) 0x0 B_0x1 PLL1 locked 0x1 PLLON PLLON 0 1 read-write B_0x0 PLL1 OFF (default after reset) 0x0 B_0x1 PLL1 is ON, and ref1_ck is provided to the PLL1 0x1 SSCG_CTRL SSCG_CTRL 2 1 read-write B_0x0 Clock Spreading Generator disabled (default after reset) 0x0 B_0x1 Clock Spreading Generator enabled 0x1 PLL1CSGR RCC_PLL1CSGR This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x90 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 read-write MOD_PER MOD_PER 0 13 read-write RPDFN_DIS RPDFN_DIS 14 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 SSCG_MODE SSCG_MODE 15 1 read-write B_0x0 Center-spread modulation selected (default after reset) 0x0 B_0x1 Down-spread modulation selected 0x1 TPDFN_DIS TPDFN_DIS 13 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 PLL1FRACR RCC_PLL1FRACR This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x8C 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 read-write FRACV FRACV 3 13 read-write PLL2CFGR1 RCC_PLL2CFGR1 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x98 32 read-write n 0x0 0x0 DIVM2 DIVM2 16 6 read-write B_0x0 bypass 0x0 B_0x1 division by 2 (default after reset) 0x1 B_0x2 division by 3 0x2 B_0x3F division by 64 0x3F DIVN DIVN 0 9 read-write B_0x18 Division ratio is 25 0x18 B_0x19 Division ratio is 26 0x19 B_0x31 Division ratio is 50 0x31 B_0x63 Division ratio is 100 (default after reset) 0x63 PLL2CFGR2 RCC_PLL2CFGR2 This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x9C 32 read-write n 0x0 0x0 DIVP DIVP 0 7 read-write B_0x0 pll2_p_ck = fout2_ck 0x0 B_0x1 pll2_p_ck = fout2_ck / 2 (default after reset) 0x1 B_0x2 pll2_p_ck = fout2_ck / 3 0x2 B_0x7F pll2_p_ck = fout2_ck / 128 0x7F DIVQ DIVQ 8 7 read-write B_0x0 pll2_q_ck = fout2_ck 0x0 B_0x1 pll2_q_ck = fout2_ck / 2 (default after reset) 0x1 B_0x2 pll2_q_ck = fout2_ck / 3 0x2 B_0x7F pll2_q_ck = fout2_ck / 128 0x7F DIVR DIVR 16 7 read-write B_0x0 pll2_r_ck = fout2_ck 0x0 B_0x1 pll2_r_ck = fout2_ck / 2 (default after reset) 0x1 B_0x2 pll2_r_ck = fout2_ck / 3 0x2 B_0x7F pll2_r_ck = fout2_ck / 128 0x7F PLL2CR RCC_PLL2CR This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x94 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write B_0x0 pll2_p_ck output is disabled (default after reset) 0x0 B_0x1 pll2_p_ck output is enabled 0x1 DIVQEN DIVQEN 5 1 read-write B_0x0 pll2_q_ck output is disabled (default after reset) 0x0 B_0x1 pll2_q_ck output is enabled 0x1 DIVREN DIVREN 6 1 read-write B_0x0 pll2_r_ck output is disabled (default after reset) 0x0 B_0x1 pll2_r_ck output is enabled 0x1 PLL2RDY PLL2RDY 1 1 read-only B_0x0 PLL2 unlocked (default after reset) 0x0 B_0x1 PLL2 locked 0x1 PLLON PLLON 0 1 read-write B_0x0 PLL2 OFF (default after reset) 0x0 B_0x1 PLL2 ON, and ref2_ck is provided to the PLL2 0x1 SSCG_CTRL SSCG_CTRL 2 1 read-write B_0x0 Clock Spreading Generator disabled (default after reset) 0x0 B_0x1 Clock Spreading Generator enabled 0x1 PLL2CSGR RCC_PLL2CSGR This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA4 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 read-write MOD_PER MOD_PER 0 13 read-write RPDFN_DIS RPDFN_DIS 14 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 SSCG_MODE SSCG_MODE 15 1 read-write B_0x0 Center-spread modulation selected (default after reset) 0x0 B_0x1 Down-spread modulation selected 0x1 TPDFN_DIS TPDFN_DIS 13 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 PLL2FRACR RCC_PLL2FRACR This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0xA0 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 read-write FRACV FRACV 3 13 read-write PLL3CFGR1 RCC_PLL3CFGR1 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x884 32 read-write n 0x0 0x0 DIVM3 DIVM3 16 6 read-write B_0x0 bypass 0x0 B_0x1 division by 2 (default after reset) 0x1 B_0x2 division by 3 0x2 B_0x3F division by 64 0x3F DIVN DIVN 0 9 read-write B_0x18 Division ratio is 25 0x18 B_0x19 Division ratio is 26 0x19 B_0x1A Division ratio is 27 0x1A B_0x31 Division ratio is 50 (default after reset) 0x31 B_0xC7 Division ratio is 200 0xC7 IFRGE IFRGE 24 2 read-write PLL3CFGR2 RCC_PLL3CFGR2 This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x888 32 read-write n 0x0 0x0 DIVP DIVP 0 7 read-write B_0x0 pll3_p_ck = vco3_ck 0x0 B_0x1 pll3_p_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_p_ck = vco3_ck / 3 0x2 B_0x7F pll3_p_ck = vco3_ck / 128 0x7F DIVQ DIVQ 8 7 read-write B_0x0 pll3_q_ck = vco3_ck 0x0 B_0x1 pll3_q_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_q_ck = vco3_ck / 3 0x2 B_0x7F pll3_q_ck = vco3_ck / 128 0x7F DIVR DIVR 16 7 read-write B_0x0 pll3_r_ck = vco3_ck 0x0 B_0x1 pll3_r_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_r_ck = vco3_ck / 3 0x2 B_0x7F pll3_r_ck = vco3_ck / 128 0x7F PLL3CR RCC_PLL3CR This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x880 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write B_0x0 pll3_p_ck output is disabled (default after reset) 0x0 B_0x1 pll3_p_ck output is enabled 0x1 DIVQEN DIVQEN 5 1 read-write B_0x0 pll3_q_ck output is disabled (default after reset) 0x0 B_0x1 pll3_q_ck output is enabled 0x1 DIVREN DIVREN 6 1 read-write B_0x0 pll3_r_ck output is disabled (default after reset) 0x0 B_0x1 pll3_r_ck output is enabled 0x1 PLL3RDY PLL3RDY 1 1 read-only B_0x0 PLL3 unlocked (default after reset) 0x0 B_0x1 PLL3 locked 0x1 PLLON PLLON 0 1 read-write B_0x0 PLL3 OFF (default after reset) 0x0 B_0x1 PLL3 ON, and ref3_ck is provided to the PLL3 0x1 SSCG_CTRL SSCG_CTRL 2 1 read-write B_0x0 Clock Spreading Generator disabled (default after reset) 0x0 B_0x1 Clock Spreading Generator enabled 0x1 PLL3CSGR RCC_PLL3CSGR This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x890 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 read-write MOD_PER MOD_PER 0 13 read-write RPDFN_DIS RPDFN_DIS 14 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 SSCG_MODE SSCG_MODE 15 1 read-write B_0x0 Center-spread modulation selected (default after reset) 0x0 B_0x1 Down-spread modulation selected 0x1 TPDFN_DIS TPDFN_DIS 13 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 PLL3FRACR RCC_PLL3FRACR This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x88C 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 read-write FRACV FRACV 3 13 read-write PLL4CFGR1 RCC_PLL4CFGR1 This register is used to configure the PLL4. 0x898 32 read-write n 0x0 0x0 DIVM4 DIVM4 16 6 read-write B_0x0 bypass 0x0 B_0x1 division by 2 (default after reset) 0x1 B_0x2 division by 3 0x2 B_0x3F division by 64 0x3F DIVN DIVN 0 9 read-write B_0x18 Division ratio is 25 0x18 B_0x19 Division ratio is 26 0x19 B_0x1A Division ratio is 27 0x1A B_0x31 Division ratio is 50 (default after reset) 0x31 B_0xC7 Division ratio is 200 0xC7 IFRGE IFRGE 24 2 read-write PLL4CFGR2 RCC_PLL4CFGR2 This register is used to configure the PLL4. 0x89C 32 read-write n 0x0 0x0 DIVP DIVP 0 7 read-write B_0x0 pll4_p_ck = vco4_ck 0x0 B_0x1 pll4_p_ck = vco4_ck / 2 (default after reset) 0x1 B_0x2 pll4_p_ck = vco4_ck / 3 0x2 B_0x7F pll4_p_ck = vco4_ck / 128 0x7F DIVQ DIVQ 8 7 read-write B_0x0 pll4_q_ck = vco4_ck 0x0 B_0x1 pll4_q_ck = vco4_ck / 2 (default after reset) 0x1 B_0x2 pll4_q_ck = vco4_ck / 3 0x2 B_0x7F pll4_q_ck = vco4_ck / 128 0x7F DIVR DIVR 16 7 read-write B_0x0 pll4_r_ck = vco4_ck 0x0 B_0x1 pll4_r_ck = vco4_ck / 2 (default after reset) 0x1 B_0x2 pll4_r_ck = vco4_ck / 3 0x2 B_0x7F pll4_r_ck = vco4_ck / 128 0x7F PLL4CR RCC_PLL4CR This register is used to control the PLL4. 0x894 32 read-write n 0x0 0x0 DIVPEN DIVPEN 4 1 read-write B_0x0 pll4_p_ck output is disabled (default after reset) 0x0 B_0x1 pll4_p_ck output is enabled 0x1 DIVQEN DIVQEN 5 1 read-write B_0x0 pll4_q_ck output is disabled (default after reset) 0x0 B_0x1 pll4_q_ck output is enabled 0x1 DIVREN DIVREN 6 1 read-write B_0x0 pll4_r_ck output is disabled (default after reset) 0x0 B_0x1 pll4_r_ck output is enabled 0x1 PLL4RDY PLL4RDY 1 1 read-only B_0x0 PLL4 unlocked (default after reset) 0x0 B_0x1 PLL4 locked 0x1 PLLON PLLON 0 1 read-write B_0x0 PLL4 OFF (default after reset) 0x0 B_0x1 PLL4 ON, and ref4_ck is provided to the PLL4 0x1 SSCG_CTRL SSCG_CTRL 2 1 read-write B_0x0 Clock Spreading Generator disabled (default after reset) 0x0 B_0x1 Clock Spreading Generator enabled 0x1 PLL4CSGR RCC_PLL4CSGR This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Please refer to Section1.4.5.4: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x8A4 32 read-write n 0x0 0x0 INC_STEP INC_STEP 16 15 read-write MOD_PER MOD_PER 0 13 read-write RPDFN_DIS RPDFN_DIS 14 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 SSCG_MODE SSCG_MODE 15 1 read-write B_0x0 Center-spread modulation selected (default after reset) 0x0 B_0x1 Down-spread modulation selected 0x1 TPDFN_DIS TPDFN_DIS 13 1 read-write B_0x0 Dithering noise injection enabled (default after reset) 0x0 B_0x1 Dithering noise injection disabled 0x1 PLL4FRACR RCC_PLL4FRACR This register is used to fine-tune the frequency of the PLL4 VCO. 0x8A0 32 read-write n 0x0 0x0 FRACLE FRACLE 16 1 read-write FRACV FRACV 3 13 read-write PWRLPDLYCR RCC_PWRLPDLYCR This register is used to program the delay between the moment where the system exits from STOP and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode. 0x41C 32 read-write n 0x0 0x0 MCTMPSKP MCTMPSKP 24 1 read-write B_0x0 The clock restore sequence of the MCU waits for the PWR_LP delay before activating power consuming elements (default after reset) 0x0 B_0x1 The clock restore sequence of the MCU runs the PWR_LP delay but did not wait for the delay to elapse before activating power consuming elements 0x1 PWRLP_DLY PWRLP_DLY 0 22 read-write B_0x0 The PWR_LP delay is bypassed (default after reset) 0x0 B_0x1 A PWR_LP delay of one period of HSI (at 64 MHz) is observed 0x1 B_0x3FFFFF A PWR_LP delay of about 65.5 milliseconds is observed 0x3FFFFF QSPICKSELR RCC_QSPICKSELR This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x900 32 read-write n 0x0 0x0 QSPISRC QSPISRC 0 2 read-write B_0x0 aclk clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll4_p_ck clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 RCK12SELR RCC_RCK12SELR This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details. 0x28 32 read-write n 0x0 0x0 PLL12SRC PLL12SRC 0 2 read-write B_0x0 HSI selected as PLL clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as PLL clock (hse_ck) 0x1 PLL12SRCRDY PLL12SRCRDY 31 1 read-only B_0x0 The PLL12 switch is not ready or in position : no clock is generated on its output 0x0 B_0x1 The PLL12 switch is ready: the clock switch is selecting the clock given by PLL12SRC field. (default after reset) 0x1 RCK3SELR RCC_RCK3SELR This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode. 0x820 32 read-write n 0x0 0x0 PLL3SRC PLL3SRC 0 2 read-write B_0x0 HSI selected as PLL clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as PLL clock (hse_ck) 0x1 B_0x2 CSI selected as PLL clock (csi_ck) 0x2 B_0x3 No clock send to DIVMx divider and PLLs 0x3 PLL3SRCRDY PLL3SRCRDY 31 1 read-only B_0x0 The PLL3 switch is not ready or in position : no clock is generated on its output 0x0 B_0x1 The PLL3 switch is ready: the clock switch is selecting the clock given by PLL3SRC field. (default after reset) 0x1 RCK4SELR RCC_RCK4SELR This register is used to select the reference clock for PLL4. 0x824 32 read-write n 0x0 0x0 PLL4SRC PLL4SRC 0 2 read-write B_0x0 HSI selected as PLL clock (hsi_ck) (default after reset) 0x0 B_0x1 HSE selected as PLL clock (hse_ck) 0x1 B_0x2 CSI selected as PLL clock (csi_ck) 0x2 B_0x3 Signal I2S_CKIN used as reference clock 0x3 PLL4SRCRDY PLL4SRCRDY 31 1 read-only B_0x0 The PLL4 switch is not ready or in position : no clock is generated on its output 0x0 B_0x1 The PLL4 switch is ready: the clock switch is selecting the clock given by PLL4SRC field. (default after reset) 0x1 RDLSICR RCC_RDLSICR This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode. 0x144 32 read-write n 0x0 0x0 EADLY EADLY 24 3 read-write B_0x0 10 ms (default after reset) 0x0 B_0x1 No extra delay added by the BOOTROM 0x1 B_0x2 100 us 0x2 B_0x3 200 us 0x3 B_0x4 500 us 0x4 B_0x5 1 ms 0x5 B_0x6 2 ms 0x6 B_0x7 5 ms 0x7 LSION LSION 0 1 read-write B_0x0 LSI oscillator OFF (default after reset) 0x0 B_0x1 LSI oscillator ON 0x1 LSIRDY LSIRDY 1 1 read-only B_0x0 LSI oscillator not ready (default after reset) 0x0 B_0x1 LSI oscillator ready 0x1 MRD MRD 16 5 read-write B_0x0 NRST low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset) 0x0 B_0x1 The guaranteed NRST low pulse duration is about 1 ms (1 x 32 lsi_ck cycles), 0x1 B_0x1F The guaranteed NRST low pulse duration is about 31 ms (31 x 32 lsi_ck cycles). 0x1F B_0x2 The guaranteed NRST low pulse duration is about 2 ms (2 x 32 lsi_ck cycles), 0x2 SPARE SPARE 27 5 read-write RNG1CKSELR RCC_RNG1CKSELR This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode. 0xCC 32 read-write n 0x0 0x0 RNG1SRC RNG1SRC 0 2 read-write B_0x0 csi_ker_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 lse_ck clock selected as kernel peripheral clock 0x2 B_0x3 lsi_ck clock selected as kernel peripheral clock 0x3 RNG2CKSELR RCC_RNG2CKSELR This register is used to control the selection of the kernel clock for the RNG2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. 0x920 32 read-write n 0x0 0x0 RNG2SRC RNG2SRC 0 2 read-write B_0x0 csi_ker_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 lse_ck clock selected as kernel peripheral clock 0x2 B_0x3 lsi_ck clock selected as kernel peripheral clock 0x3 RTCDIVR RCC_RTCDIVR This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode. 0x44 32 read-write n 0x0 0x0 RTCDIV RTCDIV 0 6 read-write B_0x0 HSE (default after reset) 0x0 B_0x1 HSE/2 0x1 B_0x2 HSE/3 0x2 B_0x3 HSE/4 0x3 B_0x3E HSE/63 0x3E B_0x3F HSE/64 0x3F SAI1CKSELR RCC_SAI1CKSELR This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8C8 32 read-write n 0x0 0x0 SAI1SRC SAI1SRC 0 3 read-write B_0x0 pll4_q_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 SAI2CKSELR RCC_SAI2CKSELR This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8CC 32 read-write n 0x0 0x0 SAI2SRC SAI2SRC 0 3 read-write B_0x0 pll4_q_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 B_0x4 spdif_ck_symb clock from SPDIFRX selected as kernel peripheral clock 0x4 SAI3CKSELR RCC_SAI3CKSELR This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8D0 32 read-write n 0x0 0x0 SAI3SRC SAI3SRC 0 3 read-write B_0x0 pll4_q_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 SAI4CKSELR RCC_SAI4CKSELR This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8D4 32 read-write n 0x0 0x0 SAI4SRC SAI4SRC 0 3 read-write B_0x0 pll4_q_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 SDMMC12CKSELR RCC_SDMMC12CKSELR This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8F4 32 read-write n 0x0 0x0 SDMMC12SRC SDMMC12SRC 0 3 read-write B_0x0 hclk6 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll4_p_ck clock selected as kernel peripheral clock 0x2 B_0x3 hsi_ker_ck clock selected as kernel peripheral clock 0x3 SDMMC3CKSELR RCC_SDMMC3CKSELR This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8F8 32 read-write n 0x0 0x0 SDMMC3SRC SDMMC3SRC 0 3 read-write B_0x0 hclk2 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 pll4_p_ck clock selected as kernel peripheral clock 0x2 B_0x3 hsi_ker_ck clock selected as kernel peripheral clock 0x3 SIDR RCC_SIDR This register gives the decoding space, which is for the RCC of 4 kB. 0xFFC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SPDIFCKSELR RCC_SPDIFCKSELR This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x914 32 read-write n 0x0 0x0 SPDIFSRC SPDIFSRC 0 2 read-write B_0x0 pll4_p_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 SPI2S1CKSELR RCC_SPI2S1CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8D8 32 read-write n 0x0 0x0 SPI1SRC SPI1SRC 0 3 read-write B_0x0 pll4_p_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 SPI2S23CKSELR RCC_SPI2S23CKSELR This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8DC 32 read-write n 0x0 0x0 SPI23SRC SPI23SRC 0 3 read-write B_0x0 pll4_p_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 I2S_CKIN clock selected as kernel peripheral clock 0x2 B_0x3 per_ck clock selected as kernel peripheral clock 0x3 SPI45CKSELR RCC_SPI45CKSELR This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8E0 32 read-write n 0x0 0x0 SPI45SRC SPI45SRC 0 3 read-write B_0x0 pclk2 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 SPI6CKSELR RCC_SPI6CKSELR This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode. 0xC4 32 read-write n 0x0 0x0 SPI6SRC SPI6SRC 0 3 read-write B_0x0 pclk5 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 B_0x5 pll3_q_ck clock selected as kernel peripheral clock 0x5 STGENCKSELR RCC_STGENCKSELR This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode. 0xD4 32 read-write n 0x0 0x0 STGENSRC STGENSRC 0 2 read-write B_0x0 hsi_ker_ck clock selected (default after reset) 0x0 B_0x1 hse_ker_ck clock selected 0x1 TIMG1PRER RCC_TIMG1PRER This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. 0x828 32 read-write n 0x0 0x0 TIMG1PRE TIMG1PRE 0 1 read-write B_0x0 The Timers kernel clock is equal to mlhclk if APB1DIV is corresponding to a division by 1 or 2, else it is equal to 2 x Fpclk1 (default after reset) 0x0 B_0x1 The Timers kernel clock is equal to mlhclk if APB1DIV is corresponding to division by 1, 2 or 4, else it is equal to 4 x Fpclk1 0x1 TIMG1PRERDY TIMG1PRERDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 TIMG2PRER RCC_TIMG2PRER This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Please refer to Section1.4.6.3: Sub-System Clock Generation for additional information. 0x82C 32 read-write n 0x0 0x0 TIMG2PRE TIMG2PRE 0 1 read-write B_0x0 The Timers kernel clock is equal to mlhclk if APB2DIV is corresponding to a division by 1 or 2, else it is equal to 2 x Fpclk2 (default after reset) 0x0 B_0x1 The Timers kernel clock is equal to mlhclk if APB2DIV is corresponding to division by 1, 2 or 4, else it is equal to 4 x Fpclk2 0x1 TIMG2PRERDY TIMG2PRERDY 31 1 read-only B_0x0 The new division factor is not yet taken into account. 0x0 B_0x1 The new division factor is taken into account. (default after reset) 0x1 TZAHB6RSTCLRR RCC_TZAHB6RSTCLRR This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A4 32 read-write n 0x0 0x0 MDMARST MDMARST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing releases the block reset, reading means that the block reset is asserted 0x1 TZAHB6RSTSETR RCC_TZAHB6RSTSETR This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode. 0x1A0 32 read-write n 0x0 0x0 MDMARST MDMARST 0 1 read-write B_0x0 Writing has no effect, reading means that the block reset is released 0x0 B_0x1 Writing asserts the block reset, reading means that the block reset is asserted 0x1 TZCR RCC_TZCR This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode. 0x0 32 read-write n 0x0 0x0 MCKPROT MCKPROT 1 1 read-write B_0x0 The registers controlling mcuss_ck clock are not protected 0x0 B_0x1 The registers controlling mcuss_ck clock are protected, (default after reset). 0x1 TZEN TZEN 0 1 read-write B_0x0 No protection 0x0 B_0x1 TrustZone enabled (default after reset). 0x1 UART1CKSELR RCC_UART1CKSELR This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. If TZEN = , this register can only be modified in secure mode. 0xC8 32 read-write n 0x0 0x0 UART1SRC UART1SRC 0 3 read-write B_0x0 pclk5 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll3_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 pll4_q_ck clock selected as kernel peripheral clock 0x4 B_0x5 hse_ker_ck clock selected as kernel peripheral clock 0x5 UART24CKSELR RCC_UART24CKSELR This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8E8 32 read-write n 0x0 0x0 UART24SRC UART24SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 UART35CKSELR RCC_UART35CKSELR This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8EC 32 read-write n 0x0 0x0 UART35SRC UART35SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 UART6CKSELR RCC_UART6CKSELR This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8E4 32 read-write n 0x0 0x0 UART6SRC UART6SRC 0 3 read-write B_0x0 pclk2 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 UART78CKSELR RCC_UART78CKSELR This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x8F0 32 read-write n 0x0 0x0 UART78SRC UART78SRC 0 3 read-write B_0x0 pclk1 clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_q_ck clock selected as kernel peripheral clock 0x1 B_0x2 hsi_ker_ck clock selected as kernel peripheral clock 0x2 B_0x3 csi_ker_ck clock selected as kernel peripheral clock 0x3 B_0x4 hse_ker_ck clock selected as kernel peripheral clock 0x4 USBCKSELR RCC_USBCKSELR This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG. It also controls the pre-divider for the reference clock for the USBPHY. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to insure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section1.4.10.1: Clock Enabling Delays. 0x91C 32 read-write n 0x0 0x0 USBOSRC USBOSRC 4 1 read-write B_0x0 pll4_r_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 clock provided by the USB PHY (rcc_ck_usbo_48m) selected as kernel peripheral clock 0x1 USBPHYSRC USBPHYSRC 0 2 read-write B_0x0 hse_ker_ck clock selected as kernel peripheral clock (default after reset) 0x0 B_0x1 pll4_r_ck clock selected as kernel peripheral clock 0x1 B_0x2 hse_ker_ck/2 clock selected as kernel peripheral clock 0x2 VERR RCC_VERR This register gives the IP version 0xFF4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only RNG1 RNG1 RNG1 0x0 0x0 0x400 registers n RNG_CR RNG_CR RNG control register 0x0 32 read-write n 0x0 0x0 CED CED 5 1 read-write IE IE 3 1 read-write RNGEN RNGEN 2 1 read-write RNG_DR RNG_DR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty. The content of this register is valid when DRDY, even if RNGEN 0x8 32 read-only n 0x0 0x0 RNDATA RNDATA 0 32 read-only RNG_ID RNG_ID RNG Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only RNG_MID RNG_MID RNG hardware magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 read-only RNG_SR RNG_SR RNG status register 0x4 32 read-write n 0x0 0x0 CECS CECS 1 1 read-only CEIS CEIS 5 1 read-write DRDY DRDY 0 1 read-only SECS SECS 2 1 read-only SEIS SEIS 6 1 read-write RNG_VER RNG_VER RNG Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 read-only RNG2 RNG1 RNG1 0x0 0x0 0x400 registers n RNG_CR RNG_CR RNG control register 0x0 32 read-write n 0x0 0x0 CED CED 5 1 read-write IE IE 3 1 read-write RNGEN RNGEN 2 1 read-write RNG_DR RNG_DR The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 216 periods of AHB clock if the output FIFO is empty. The content of this register is valid when DRDY, even if RNGEN 0x8 32 read-only n 0x0 0x0 RNDATA RNDATA 0 32 read-only RNG_ID RNG_ID RNG Identification 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only RNG_MID RNG_MID RNG hardware magic ID 0x3FC 32 read-only n 0x0 0x0 MID MID 0 32 read-only RNG_SR RNG_SR RNG status register 0x4 32 read-write n 0x0 0x0 CECS CECS 1 1 read-only CEIS CEIS 5 1 read-write DRDY DRDY 0 1 read-only SECS SECS 2 1 read-only SEIS SEIS 6 1 read-write RNG_VER RNG_VER RNG Version Register 0x3F4 32 read-only n 0x0 0x0 VER VER 0 8 read-only RTC RTC register bank RTC 0x0 0x0 0x400 registers n ALRMAR RTC_ALRMAR This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x40 32 read-write n 0x0 0x0 DT DT 28 2 read-write DU DU 24 4 read-write HT HT 20 2 read-write HU HU 16 4 read-write MNT MNT 12 3 read-write MNU MNU 8 4 read-write MSK1 MSK1 7 1 read-write MSK2 MSK2 15 1 read-write MSK3 MSK3 23 1 read-write MSK4 MSK4 31 1 read-write PM PM 22 1 read-write ST ST 4 3 read-write SU SU 0 4 read-write WDSEL WDSEL 30 1 read-write ALRMASSR RTC_ALRMASSR This register can be written only when ALRAWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x44 32 read-write n 0x0 0x0 MASKSS MASKSS 24 4 read-write SS SS 0 15 read-write ALRMBR RTC_ALRMBR This register can be written only when ALRBWF is set to 1 in RTC_ICSR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x48 32 read-write n 0x0 0x0 DT DT 28 2 read-write DU DU 24 4 read-write HT HT 20 2 read-write HU HU 16 4 read-write MNT MNT 12 3 read-write MNU MNU 8 4 read-write MSK1 MSK1 7 1 read-write MSK2 MSK2 15 1 read-write MSK3 MSK3 23 1 read-write MSK4 MSK4 31 1 read-write PM PM 22 1 read-write ST ST 4 3 read-write SU SU 0 4 read-write WDSEL WDSEL 30 1 read-write ALRMBSSR RTC_ALRMBSSR This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section: RTC register write protection. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x4C 32 read-write n 0x0 0x0 MASKSS MASKSS 24 4 read-write SS SS 0 15 read-write CALR RTC_CALR This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x28 32 read-write n 0x0 0x0 CALM CALM 0 9 read-write CALP CALP 15 1 read-write CALW16 CALW16 13 1 read-write CALW8 CALW8 14 1 read-write CFGR RTC_CFGR RTC configuration register 0x60 32 read-write n 0x0 0x0 LSCOEN LSCOEN 1 2 read-write OUT2_RMP OUT2_RMP 0 1 read-write CR RTC_CR This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x18 32 read-write n 0x0 0x0 ADD1H ADD1H 16 1 write-only ALRAE ALRAE 8 1 read-write ALRAIE ALRAIE 12 1 read-write ALRBE ALRBE 9 1 read-write ALRBIE ALRBIE 13 1 read-write BKP BKP 18 1 read-write BYPSHAD BYPSHAD 5 1 read-write COE COE 23 1 read-write COSEL COSEL 19 1 read-write FMT FMT 6 1 read-write ITSE ITSE 24 1 read-write OSEL OSEL 21 2 read-write OUT2EN OUT2EN 31 1 read-write POL POL 20 1 read-write REFCKON REFCKON 4 1 read-write SUB1H SUB1H 17 1 write-only TAMPALRM_PU TAMPALRM_PU 29 1 read-write TAMPALRM_TYPE TAMPALRM_TYPE 30 1 read-write TAMPOE TAMPOE 26 1 read-write TAMPTS TAMPTS 25 1 read-write TSE TSE 11 1 read-write TSEDGE TSEDGE 3 1 read-write TSIE TSIE 15 1 read-write WUCKSEL WUCKSEL 0 3 read-write WUTE WUTE 10 1 read-write WUTIE WUTIE 14 1 read-write DR RTC_DR The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page632 and Reading the calendar on page633. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x4 32 read-write n 0x0 0x0 DT DT 4 2 read-write DU DU 0 4 read-write MT MT 12 1 read-write MU MU 8 4 read-write WDU WDU 13 3 read-write YT YT 20 4 read-write YU YU 16 4 read-write HWCFGR RTC_HWCFGR RTC hardware configuration register 0x3F0 32 read-only n 0x0 0x0 ALARMB ALARMB 0 4 read-only OPTIONREG_OUT OPTIONREG_OUT 16 8 read-only SMOOTH_CALIB SMOOTH_CALIB 8 4 read-only TIMESTAMP TIMESTAMP 12 4 read-only TRUST_ZONE TRUST_ZONE 24 4 read-only WAKEUP WAKEUP 4 4 read-only ICSR RTC_ICSR This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0xC 32 read-write n 0x0 0x0 ALRAWF ALRAWF 0 1 read-only ALRBWF ALRBWF 1 1 read-only INIT INIT 7 1 read-write INITF INITF 6 1 read-only INITS INITS 4 1 read-only RECALPF RECALPF 16 1 read-only RSF RSF 5 1 read-write SHPF SHPF 3 1 read-only WUTWF WUTWF 2 1 read-only IPIDR RTC_IPIDR RTC identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only MISR RTC_MISR RTC non-secure masked interrupt status register 0x54 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 read-only ALRBMF ALRBMF 1 1 read-only ITSMF ITSMF 5 1 read-only TSMF TSMF 3 1 read-only TSOVMF TSOVMF 4 1 read-only WUTMF WUTMF 2 1 read-only PRER RTC_PRER This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page632. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x10 32 read-write n 0x0 0x0 PREDIV_A PREDIV_A 16 7 read-write PREDIV_S PREDIV_S 0 15 read-write SCR RTC_SCR This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x5C 32 read-write n 0x0 0x0 CALRAF CALRAF 0 1 write-only CALRBF CALRBF 1 1 write-only CITSF CITSF 5 1 write-only CTSF CTSF 3 1 write-only CTSOVF CTSOVF 4 1 write-only CWUTF CWUTF 2 1 write-only SHIFTR RTC_SHIFTR This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x2C 32 read-write n 0x0 0x0 ADD1S ADD1S 31 1 write-only SUBFS SUBFS 0 15 write-only SIDR RTC_SIDR RTC size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SMCR RTC_SMCR This register can be written only when the APB access is secure. 0x20 32 read-write n 0x0 0x0 ALRADPROT ALRADPROT 0 1 read-write ALRBDPROT ALRBDPROT 1 1 read-write CALDPROT CALDPROT 13 1 read-write DECPROT DECPROT 15 1 read-write INITDPROT INITDPROT 14 1 read-write TSDPROT TSDPROT 3 1 read-write WUTDPROT WUTDPROT 2 1 read-write SMISR RTC_SMISR This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x58 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 read-only ALRBMF ALRBMF 1 1 read-only ITSMF ITSMF 5 1 read-only TSMF TSMF 3 1 read-only TSOVMF TSOVMF 4 1 read-only WUTMF WUTMF 2 1 read-only SR RTC_SR This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x50 32 read-only n 0x0 0x0 ALRAF ALRAF 0 1 read-only ALRBF ALRBF 1 1 read-only ITSF ITSF 5 1 read-only TSF TSF 3 1 read-only TSOVF TSOVF 4 1 read-only WUTF WUTF 2 1 read-only SSR RTC_SSR RTC sub second register 0x8 32 read-only n 0x0 0x0 SS SS 0 16 read-only TR RTC_TR The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page632 and Reading the calendar on page633. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be write-protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x0 32 read-write n 0x0 0x0 HT HT 20 2 read-write HU HU 16 4 read-write MNT MNT 12 3 read-write MNU MNU 8 4 read-write PM PM 22 1 read-write ST ST 4 3 read-write SU SU 0 4 read-write TSDR RTC_TSDR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x34 32 read-only n 0x0 0x0 DT DT 4 2 read-only DU DU 0 4 read-only MT MT 12 1 read-only MU MU 8 4 read-only WDU WDU 13 3 read-only TSSSR RTC_TSSSR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x38 32 read-only n 0x0 0x0 SS SS 0 16 read-only TSTR RTC_TSTR The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x30 32 read-only n 0x0 0x0 HT HT 20 2 read-only HU HU 16 4 read-only MNT MNT 12 3 read-only MNU MNU 8 4 read-only PM PM 22 1 read-only ST ST 4 3 read-only SU SU 0 4 read-only VERR RTC_VERR RTC version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only WPR RTC_WPR RTC write protection register 0x24 32 read-write n 0x0 0x0 KEY KEY 0 8 write-only WUTR RTC_WUTR This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page632. This register can be protected against non-secure access. Refer to Section23.3.4: RTC secure protection modes. 0x14 32 read-write n 0x0 0x0 WUT WUT 0 16 read-write SAI1 SAI SAI 0x0 0x0 0x400 registers n SAI4 SAI4 global interrupt 146 SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in AC97 and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in AC97 and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IDR SAI_IDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 Clock enable of bitstream clock number 2 9 1 CKEN3 Clock enable of bitstream clock number 3 10 1 CKEN4 Clock enable of bitstream clock number 4 11 1 MICNBR Number of microphones 4 2 PDMEN PDM enable 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L Delay line for first microphone of pair 3 16 3 DLYM3R Delay line for second microphone of pair 3 20 3 DLYM4L Delay line for first microphone of pair 4 24 3 DLYM4R Delay line for second microphone of pair 4 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI2 SAI SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in AC97 and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in AC97 and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IDR SAI_IDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 Clock enable of bitstream clock number 2 9 1 CKEN3 Clock enable of bitstream clock number 3 10 1 CKEN4 Clock enable of bitstream clock number 4 11 1 MICNBR Number of microphones 4 2 PDMEN PDM enable 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L Delay line for first microphone of pair 3 16 3 DLYM3R Delay line for second microphone of pair 3 20 3 DLYM4L Delay line for first microphone of pair 4 24 3 DLYM4R Delay line for second microphone of pair 4 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI3 SAI SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in AC97 and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in AC97 and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IDR SAI_IDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 Clock enable of bitstream clock number 2 9 1 CKEN3 Clock enable of bitstream clock number 3 10 1 CKEN4 Clock enable of bitstream clock number 4 11 1 MICNBR Number of microphones 4 2 PDMEN PDM enable 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L Delay line for first microphone of pair 3 16 3 DLYM3R Delay line for second microphone of pair 3 20 3 DLYM4L Delay line for first microphone of pair 4 24 3 DLYM4R Delay line for second microphone of pair 4 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SAI4 SAI SAI 0x0 0x0 0x400 registers n SAI_ACLRFR SAI_ACLRFR Clear flag register 0x1C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_ACR1 SAI_ACR1 Configuration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_ACR2 SAI_ACR2 Configuration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_ADR SAI_ADR Data register 0x20 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_AFRCR SAI_AFRCR This register has no meaning in AC97 and SPDIF audio protocol 0xC 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_AIM SAI_AIM Interrupt mask register 2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_ASLOTR SAI_ASLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_ASR SAI_ASR Status register 0x18 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_BCLRFR SAI_BCLRFR Clear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0. 5 1 CCNRDY Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0. 4 1 CLFSDET Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0. 6 1 CMUTEDET Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0. 1 1 COVRUDR Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0. 0 1 CWCKCFG Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0. 2 1 SAI_BCR1 SAI_BCR1 Configuration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol. 9 1 DMAEN DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode. 17 1 DS Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled. 5 3 LSBFIRST Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first. 8 1 MCKDIV Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula: 20 6 MCKEN MCKEN 27 1 MODE SAIx audio block mode immediately 0 2 MONO Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details. 12 1 NOMCK No divider 19 1 OSR Oversampling ratio for master clock 26 1 OUTDRIV Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration. 13 1 PRTCFG Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled. 2 2 SAIXEN Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit. 16 1 SYNCEN Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled. 10 2 SAI_BCR2 SAI_BCR2 Configuration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected. 14 2 read-write CPL Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm. 13 1 read-write FFLUSH FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled. 3 1 write-only FTH FIFO threshold. This bit is set and cleared by software. 0 3 read-write MUTE Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 5 1 read-write MUTECNT Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details. 7 6 read-write MUTEVAL Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks. 6 1 read-write TRIS Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details. 4 1 read-write SAI_BDR SAI_BDR Data register 0x40 32 read-write n 0x0 0x0 DATA Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty. 0 32 SAI_BFRCR SAI_BFRCR This register has no meaning in AC97 and SPDIF audio protocol 0x2C 32 read-write n 0x0 0x0 FRL Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. 0 8 read-write FSALL Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled. 8 7 read-write FSDEF Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled. 16 1 read-only FSOFF Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 18 1 read-write FSPOL Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled. 17 1 read-write SAI_BIM SAI_BIM Interrupt mask register 2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 5 1 CNRDYIE Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver. 4 1 FREQIE FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode, 3 1 LFSDETIE Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master. 6 1 MUTEDETIE Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode. 1 1 OVRUDRIE Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set. 0 1 WCKCFGIE Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes. 2 1 SAI_BSLOTR SAI_BSLOTR This register has no meaning in AC97 and SPDIF audio protocol 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 0 5 NBSLOT Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 8 4 SLOTEN Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 16 16 SLOTSZ Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode. 6 2 SAI_BSR SAI_BSR Status register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register. 5 1 CNRDY Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register. 4 1 FLVL FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver: 16 3 FREQ FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register. 3 1 LFSDET Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register 6 1 MUTEDET Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register. 1 1 OVRUDR Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register. 0 1 WCKCFG Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register. 2 1 SAI_GCR SAI_GCR Global configuration register 0x0 32 read-write n 0x0 0x0 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs These bits are set and cleared by software. 4 2 SAI_HWCFGR SAI_HWCFGR SAI hardware configuration register 0x3F0 32 read-only n 0x0 0x0 FIFO_SIZE FIFO_SIZE 0 8 OPTION_REGOUT OPTION_REGOUT 12 8 SPDIF_PDM SPDIF_PDM 8 4 SAI_IDR SAI_IDR SAI identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 SAI_PDMCR SAI_PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 Clock enable of bitstream clock number 2 9 1 CKEN3 Clock enable of bitstream clock number 3 10 1 CKEN4 Clock enable of bitstream clock number 4 11 1 MICNBR Number of microphones 4 2 PDMEN PDM enable 0 1 SAI_PDMDLY SAI_PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L Delay line for first microphone of pair 3 16 3 DLYM3R Delay line for second microphone of pair 3 20 3 DLYM4L Delay line for first microphone of pair 4 24 3 DLYM4R Delay line for second microphone of pair 4 28 3 SAI_SIDR SAI_SIDR SAI size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 SAI_VERR SAI_VERR SAI version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 MINREV MINREV 0 4 SDMMC1 SDMMC1 SDMMC 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) 18 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN Enable boot mode procedure. 15 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 SDMMC_FIFOR SDMMC_FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 SDMMC_ID SDMMC_ID SDMMC IP identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID SDMMC IP identification. 0 32 SDMMC_IDMABASE0R SDMMC_IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 SDMMC_IDMABASE1R SDMMC_IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 32 read-write n 0x0 0x0 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 SM SM 16 1 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 see Table 432 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 see Table404. 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 see Table404. 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 see Table404. 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR SDMMC command response register 0x10 32 read-only n 0x0 0x0 RESPCMD Response command index 0 6 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 SDMMC_VER SDMMC_VER SDMMC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV IP major revision number. 4 4 MINREV IP minor revision number. 0 4 SDMMC2 SDMMC1 SDMMC 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) 18 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN Enable boot mode procedure. 15 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 SDMMC_FIFOR SDMMC_FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 SDMMC_ID SDMMC_ID SDMMC IP identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID SDMMC IP identification. 0 32 SDMMC_IDMABASE0R SDMMC_IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 SDMMC_IDMABASE1R SDMMC_IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 32 read-write n 0x0 0x0 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 SM SM 16 1 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 see Table 432 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 see Table404. 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 see Table404. 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 see Table404. 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR SDMMC command response register 0x10 32 read-only n 0x0 0x0 RESPCMD Response command index 0 6 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 SDMMC_VER SDMMC_VER SDMMC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV IP major revision number. 4 4 MINREV IP minor revision number. 0 4 SDMMC3 SDMMC1 SDMMC 0x0 0x0 0x1000 registers n SDMMC_ACKTIMER SDMMC_ACKTIMER The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set. 0x40 32 read-write n 0x0 0x0 ACKTIME Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods. 0 25 SDMMC_ARGR SDMMC_ARGR The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message. 0x8 32 read-write n 0x0 0x0 CMDARG Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register. 0 32 SDMMC_CLKCR SDMMC_CLKCR The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width. 0x4 32 read-write n 0x0 0x0 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 19 1 CLKDIV Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.. 0 10 DDR Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0) 18 1 HWFC_EN Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11. 17 1 NEGEDGE SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. 16 1 PWRSAV Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 12 1 SELCLKRX Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 20 2 WIDBUS Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 14 2 SDMMC_CMDR SDMMC_CMDR The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM). 0xC 32 read-write n 0x0 0x0 BOOTEN Enable boot mode procedure. 15 1 BOOTMODE Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0) 14 1 CMDINDEX Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message. 0 6 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent. 7 1 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1. 16 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent. 6 1 CPSMEN Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0. 12 1 DTHOLD Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state. 13 1 WAITINT CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode. 10 1 WAITPEND CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card. 11 1 WAITRESP Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response. 8 2 SDMMC_DCNTR SDMMC_DCNTR The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set. 0x30 32 read-only n 0x0 0x0 DATACOUNT Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect. 0 25 SDMMC_DCTRL SDMMC_DCTRL The SDMMC_DCTRL register control the data path state machine (DPSM). 0x2C 32 read-write n 0x0 0x0 BOOTACKEN Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 12 1 DBLOCKSIZE Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) 4 4 DTDIR Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 DTEN Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. 0 1 DTMODE Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 2 2 FIFORST FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. 13 1 RWMOD Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 10 1 RWSTART Read wait start. If this bit is set, read wait operation starts. 8 1 RWSTOP Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. 9 1 SDIOEN SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. 11 1 SDMMC_DLENR SDMMC_DLENR The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 0x28 32 read-write n 0x0 0x0 DATALENGTH Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0. 0 25 SDMMC_DTIMER SDMMC_DTIMER The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 0x24 32 read-write n 0x0 0x0 DATATIME Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods. 0 32 SDMMC_FIFOR SDMMC_FIFOR The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated. 0x80 32 read-write n 0x0 0x0 FIFODATA Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words. 0 32 SDMMC_ICR SDMMC_ICR The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register. 0x38 32 read-write n 0x0 0x0 ACKFAILC ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag. 23 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag. 24 1 BUSYD0ENDC BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag. 21 1 CCRCFAILC CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag. 0 1 CKSTOPC CKSTOP flag clear bit Set by software to clear the CKSTOP flag. 26 1 CMDRENDC CMDREND flag clear bit Set by software to clear the CMDREND flag. 6 1 CMDSENTC CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 7 1 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 2 1 DABORTC DABORT flag clear bit Set by software to clear the DABORT flag. 11 1 DATAENDC DATAEND flag clear bit Set by software to clear the DATAEND flag. 8 1 DBCKENDC DBCKEND flag clear bit Set by software to clear the DBCKEND flag. 10 1 DCRCFAILC DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 1 1 DHOLDC DHOLD flag clear bit Set by software to clear the DHOLD flag. 9 1 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag. 3 1 IDMABTCC IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag. 28 1 IDMATEC IDMA transfer error clear bit Set by software to clear the IDMATE flag. 27 1 RXOVERRC RXOVERR flag clear bit Set by software to clear the RXOVERR flag. 5 1 SDIOITC SDIOIT flag clear bit Set by software to clear the SDIOIT flag. 22 1 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag. 4 1 VSWENDC VSWEND flag clear bit Set by software to clear the VSWEND flag. 25 1 SDMMC_ID SDMMC_ID SDMMC IP identification register 0x3F8 32 read-only n 0x0 0x0 IP_ID SDMMC IP identification. 0 32 SDMMC_IDMABASE0R SDMMC_IDMABASE0R The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration. 0x58 32 read-write n 0x0 0x0 IDMABASE0 Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1). 0 32 SDMMC_IDMABASE1R SDMMC_IDMABASE1R The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address. 0x5C 32 read-write n 0x0 0x0 IDMABASE1 Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0). 0 32 SDMMC_IDMABSIZER SDMMC_IDMABSIZER The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration. 0x54 32 read-write n 0x0 0x0 IDMABNDT Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0). 5 8 SDMMC_IDMACTRLR SDMMC_IDMACTRLR The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. 0x50 32 read-write n 0x0 0x0 IDMABACT Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware. 2 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 SDMMC_MASKR SDMMC_MASKR The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. 0x3C 32 read-write n 0x0 0x0 ACKFAILIE Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail. 23 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout. 24 1 BUSYD0ENDIE BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response. 21 1 CCRCFAILIE Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure. 0 1 CKSTOPIE Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped. 26 1 CMDRENDIE Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 6 1 CMDSENTIE Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 7 1 CTIMEOUTIE Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout. 2 1 DABORTIE Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted. 11 1 DATAENDIE Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 8 1 DBCKENDIE Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 10 1 DCRCFAILIE Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure. 1 1 DHOLDIE Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state. 9 1 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout. 3 1 IDMABTCIE IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer. 28 1 RXFIFOFIE Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 15 1 RXOVERRIE Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error. 5 1 SDIOITIE SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 22 1 TXFIFOEIE Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 18 1 TXFIFOHEIE Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 14 1 TXUNDERRIE Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error. 4 1 VSWENDIE Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion. 25 1 SDMMC_POWER SDMMC_POWER SDMMC power control register 0x0 32 read-write n 0x0 0x0 DIRPOL Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). 4 1 PWRCTRL SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11. 0 2 SM SM 16 1 VSWITCH Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence: 2 1 VSWITCHEN Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response: 3 1 SDMMC_RESP1R SDMMC_RESP1R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x14 32 read-only n 0x0 0x0 CARDSTATUS1 see Table 432 0 32 SDMMC_RESP2R SDMMC_RESP2R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x18 32 read-only n 0x0 0x0 CARDSTATUS2 see Table404. 0 32 SDMMC_RESP3R SDMMC_RESP3R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x1C 32 read-only n 0x0 0x0 CARDSTATUS3 see Table404. 0 32 SDMMC_RESP4R SDMMC_RESP4R The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. 0x20 32 read-only n 0x0 0x0 CARDSTATUS4 see Table404. 0 32 SDMMC_RESPCMDR SDMMC_RESPCMDR SDMMC command response register 0x10 32 read-only n 0x0 0x0 RESPCMD Response command index 0 6 SDMMC_STAR SDMMC_STAR The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO) 0x34 32 read-only n 0x0 0x0 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 23 1 ACKTIMEOUT Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 24 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt. 20 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 21 1 CCRCFAIL Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 0 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 26 1 CMDREND Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 6 1 CMDSENT Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 7 1 CPSMACT Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 13 1 CTIMEOUT Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods. 2 1 DABORT Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 11 1 DATAEND Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 8 1 DBCKEND Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 10 1 DCRCFAIL Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 1 1 DHOLD Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 9 1 DPSMACT Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt. 12 1 DTIMEOUT Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 3 1 IDMABTC IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 28 1 IDMATE IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 27 1 RXFIFOE Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full. 19 1 RXFIFOF Receive FIFO full This bit is cleared when one FIFO location becomes empty. 17 1 RXFIFOHF Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty. 15 1 RXOVERR Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 5 1 SDIOIT SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 22 1 TXFIFOE Transmit FIFO empty This bit is cleared when one FIFO location becomes full. 18 1 TXFIFOF Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty. 16 1 TXFIFOHE Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full. 14 1 TXUNDERR Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 4 1 VSWEND Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. 25 1 SDMMC_VER SDMMC_VER SDMMC IP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV IP major revision number. 4 4 MINREV IP minor revision number. 0 4 SPDIFRX SPDIFRX SPDIFRX 0x0 0x0 0x400 registers n CR SPDIFRX_CR Control register 0x0 32 read-write n 0x0 0x0 CBDMAEN CBDMAEN 10 1 read-write CHSEL CHSEL 11 1 read-write CKSBKPEN CKSBKPEN 21 1 read-write CKSEN CKSEN 20 1 read-write CUMSK CUMSK 8 1 read-write DRFMT DRFMT 4 2 read-write INSEL INSEL 16 3 read-write NBTR NBTR 12 2 read-write PMSK PMSK 6 1 read-write PTMSK PTMSK 9 1 read-write RXDMAEN RXDMAEN 2 1 read-write RXSTEO RXSTEO 3 1 read-write SPDIFRXEN SPDIFRXEN 0 2 read-write VMSK VMSK 7 1 read-write WFA WFA 14 1 read-write CSR SPDIFRX_CSR Channel status register 0x14 32 read-only n 0x0 0x0 CS CS 16 8 read-only SOB SOB 24 1 read-only USR USR 0 16 read-only DIR SPDIFRX_DIR Debug information register 0x18 32 read-only n 0x0 0x0 THI THI 0 13 read-only TLO TLO 16 13 read-only DR1 SPDIFRX_DR1 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00: 0x10 32 read-only n 0x0 0x0 C C 27 1 read-only DR DR 0 24 read-only PE PE 24 1 read-only PT PT 28 2 read-only U U 26 1 read-only V V 25 1 read-only DR2 SPDIFRX_DR2 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00: SPDIFRX_DR1 0x10 32 read-only n 0x0 0x0 C C 3 1 read-only DR DR 8 24 read-only PE PE 0 1 read-only PT PT 4 2 read-only U U 2 1 read-only V V 1 1 read-only DR3 SPDIFRX_DR3 This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 0b00: SPDIFRX_DR1 0x10 32 read-only n 0x0 0x0 DRNL1 DRNL1 0 16 read-only DRNL2 DRNL2 16 16 read-only IFCR SPDIFRX_IFCR Interrupt flag clear register 0xC 32 read-write n 0x0 0x0 OVRCF OVRCF 3 1 write-only PERRCF PERRCF 2 1 write-only SBDCF SBDCF 4 1 write-only SYNCDCF SYNCDCF 5 1 write-only IMR SPDIFRX_IMR Interrupt mask register 0x4 32 read-write n 0x0 0x0 CSRNEIE CSRNEIE 1 1 read-write IFEIE IFEIE 6 1 read-write OVRIE OVRIE 3 1 read-write PERRIE PERRIE 2 1 read-write RXNEIE RXNEIE 0 1 read-write SBLKIE SBLKIE 4 1 read-write SYNCDIE SYNCDIE 5 1 read-write IPIDR SPDIFRX_IPIDR SPDIFRX identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only SIDR SPDIFRX_SIDR SPDIFRX size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SR SPDIFRX_SR Status register 0x8 32 read-only n 0x0 0x0 CSRNE CSRNE 1 1 read-only FERR FERR 6 1 read-only OVR OVR 3 1 read-only PERR PERR 2 1 read-only RXNE RXNE 0 1 read-only SBD SBD 4 1 read-only SERR SERR 7 1 read-only SYNCD SYNCD 5 1 read-only TERR TERR 8 1 read-only WIDTH5 WIDTH5 16 15 read-only VERR SPDIFRX_VERR SPDIFRX version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only SPI1 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI2 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI3 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI4 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI5 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 SPI6 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n CFG1 CFG1 SPI configuration register 1 0x8 32 read-write n 0x0 0x0 CRCEN CRCEN 22 1 CRCSIZE CRCSIZE 16 5 DSIZE DSIZE 0 5 FTHLV FTHLV 5 4 MBR MBR 28 3 RXDMAEN RXDMAEN 14 1 TXDMAEN TXDMAEN 15 1 UDRCFG UDRCFG 9 2 UDRDET UDRDET 11 2 CFG2 CFG2 SPI configuration register 2 0xC 32 read-write n 0x0 0x0 AFCNTR AFCNTR 31 1 COMM COMM 17 2 CPHA CPHA 24 1 CPOL CPOL 25 1 IOSWP IOSWP 15 1 LSBFRST LSBFRST 23 1 MASTER MASTER 22 1 MIDI MIDI 4 4 MSSI MSSI 0 4 SP SP 19 3 SSIOP SSIOP 28 1 SSM SSM 26 1 SSOE SSOE 29 1 SSOM SSOM 30 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 CRC33_17 CRC33_17 13 1 CSTART CSTART 9 1 CSUSP CSUSP 10 1 HDDIR HDDIR 11 1 IOLOCK IOLOCK 16 1 MASRX MASRX 8 1 RCRCINI RCRCINI 14 1 SPE SPE 0 1 SSI SSI 12 1 TCRCINI TCRCINI 15 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TSER TSER 16 16 TSIZE TSIZE 0 16 CRCPOLY CRCPOLY SPI polynomial register 0x40 32 read-write n 0x0 0x0 CRCPOLY CRCPOLY 0 32 HWCFGR HWCFGR SPI/I2S hardware configuration register 0x3F0 32 read-only n 0x0 0x0 CRCCFG CRCCFG 8 4 DSCFG DSCFG 16 4 I2SCFG I2SCFG 12 4 RXFCFG RXFCFG 4 4 TXFCFG TXFCFG 0 4 I2SCGFR I2SCGFR SPI/I2S configuration register 0x50 32 read-write n 0x0 0x0 CHLEN CHLEN 10 1 CKPOL CKPOL 11 1 DATFMT DATFMT 14 1 DATLEN DATLEN 8 2 FIXCH FIXCH 12 1 I2SCFG I2SCFG 1 3 I2SDIV I2SDIV 16 8 I2SMOD I2SMOD 0 1 I2SSTD I2SSTD 4 2 MCKOE MCKOE 25 1 ODD ODD 24 1 PCMSYNC PCMSYNC 7 1 WSINV WSINV 13 1 IER IER SPI/I2S interrupt enable register 0x10 32 read-write n 0x0 0x0 CRCEIE CRCEIE 7 1 DXPIE DXPIE 2 1 EOTIE EOTIE 3 1 MODFIE MODFIE 9 1 OVRIE OVRIE 6 1 RXPIE RXPIE 0 1 TIFREIE TIFREIE 8 1 TSERFIE TSERFIE 10 1 TXPIE TXPIE 1 1 TXTFIE TXTFIE 4 1 UDRIE UDRIE 5 1 IFCR IFCR SPI/I2S interrupt/status flags clear register 0x18 32 read-write n 0x0 0x0 CRCEC CRCEC 7 1 EOTC EOTC 3 1 MODFC MODFC 9 1 OVRC OVRC 6 1 SUSPC SUSPC 11 1 TIFREC TIFREC 8 1 TSERFC TSERFC 10 1 TXTFC TXTFC 4 1 UDRC UDRC 5 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 RXCRC RXCRC SPI receiver CRC register 0x48 32 read-write n 0x0 0x0 RXCRC RXCRC 0 32 RXDR RXDR SPI/I2S receive data register 0x30 32 read-only n 0x0 0x0 RXDR RXDR 0 32 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 SR SR status register 0x14 32 read-only n 0x0 0x0 CRCE CRCE 7 1 CTSIZE CTSIZE 16 16 DXP DXP 2 1 EOT EOT 3 1 MODF MODF 9 1 OVR OVR 6 1 RXP RXP 0 1 RXPLVL RXPLVL 13 2 RXWNE RXWNE 15 1 SUSP SUSP 11 1 TIFRE TIFRE 8 1 TSERF TSERF 10 1 TXC TXC 12 1 TXP TXP 1 1 TXTF TXTF 4 1 UDR UDR 5 1 TXCRC TXCRC SPI transmitter CRC register 0x44 32 read-write n 0x0 0x0 TXCRC TXCRC 0 32 TXDR TXDR SPI/I2S transmit data register 0x20 32 write-only n 0x0 0x0 TXDR TXDR 0 32 UDRDR UDRDR SPI underrun data register 0x4C 32 read-write n 0x0 0x0 UDRDR UDRDR 0 32 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 STGEN STGEN STGEN 0x0 0x0 0x1000 registers n STGENC_CIDR0 STGENC_CIDR0 STGENC component ID0 register 0xFF0 32 read-only n 0x0 0x0 PRMBL_0 PRMBL_0 0 8 read-only STGENC_CIDR1 STGENC_CIDR1 STGENC component ID1 register 0xFF4 32 read-only n 0x0 0x0 CLASS CLASS 4 4 read-only PRMBL_1 PRMBL_1 0 4 read-only STGENC_CIDR2 STGENC_CIDR2 STGENC component ID2 register 0xFF8 32 read-only n 0x0 0x0 PRMBL_2 PRMBL_2 0 8 read-only STGENC_CIDR3 STGENC_CIDR3 STGENC component ID3 register 0xFFC 32 read-only n 0x0 0x0 PRMBL_3 PRMBL_3 0 8 read-only STGENC_CNTCR STGENC_CNTCR STGENC control register 0x0 32 read-write n 0x0 0x0 EN EN 0 1 read-write HLTDBG HLTDBG 1 1 read-write STGENC_CNTCVL STGENC_CNTCVL the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0x8 32 read-write n 0x0 0x0 CNTCVL_L_32 CNTCVL_L_32 0 32 read-write STGENC_CNTCVU STGENC_CNTCVU the control interface must clear the STGENC_CNTCR.EN bit before writing to this register. 0xC 32 read-write n 0x0 0x0 CNTCVU_U_32 CNTCVU_U_32 0 32 read-write STGENC_CNTFID0 STGENC_CNTFID0 the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x20 32 read-write n 0x0 0x0 FREQ FREQ 0 32 read-write STGENC_CNTSR STGENC_CNTSR STGENC status register 0x4 32 read-only n 0x0 0x0 EN EN 0 1 read-only HLTDBG HLTDBG 1 1 read-only STGENC_PIDR0 STGENC_PIDR0 STGENC peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PART_0 PART_0 0 8 read-only STGENC_PIDR1 STGENC_PIDR1 STGENC peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 DES_0 DES_0 4 4 read-only PART_1 PART_1 0 4 read-only STGENC_PIDR2 STGENC_PIDR2 STGENC peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 DES_1 DES_1 0 3 read-only JEDEC JEDEC 3 1 read-only REVISION REVISION 4 4 read-only STGENC_PIDR3 STGENC_PIDR3 STGENC peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 CMOD CMOD 0 4 read-only REVAND REVAND 4 4 read-only STGENC_PIDR4 STGENC_PIDR4 STGENC peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 DES_2 DES_2 0 4 read-only SIZE SIZE 4 4 read-only STGENC_PIDR5 STGENC_PIDR5 STGENC peripheral ID5 register 0xFD4 32 read-only n 0x0 0x0 PIDR5 PIDR5 0 32 read-only STGENC_PIDR6 STGENC_PIDR6 STGENC peripheral ID6 register 0xFD8 32 read-only n 0x0 0x0 PIDR6 PIDR6 0 32 read-only STGENC_PIDR7 STGENC_PIDR7 STGENC peripheral ID7 register 0xFDC 32 read-only n 0x0 0x0 PIDR7 PIDR7 0 32 read-only STGENR STGENR STGENR 0x0 0x0 0x1000 registers n CIDR0 STGENR_CIDR0 STGENR component ID0 register 0xFF0 32 read-only n 0x0 0x0 PRMBL_0 PRMBL_0 0 8 read-only CIDR1 STGENR_CIDR1 STGENR component ID1 register 0xFF4 32 read-only n 0x0 0x0 CLASS CLASS 4 4 read-only PRMBL_1 PRMBL_1 0 4 read-only CIDR2 STGENR_CIDR2 STGENR component ID2 register 0xFF8 32 read-only n 0x0 0x0 PRMBL_2 PRMBL_2 0 8 read-only CIDR3 STGENR_CIDR3 STGENR component ID3 register 0xFFC 32 read-only n 0x0 0x0 PRMBL_3 PRMBL_3 0 8 read-only CNTCVL STGENR_CNTCVL the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x0 32 read-only n 0x0 0x0 CNTCVL_L_32 CNTCVL_L_32 0 32 read-only CNTCVU STGENR_CNTCVU the control interface must clear the STGEN_CNTCR.EN bit before writing to this register. 0x4 32 read-only n 0x0 0x0 CNTCVU_U_32 CNTCVU_U_32 0 32 read-only PIDR0 STGENR_PIDR0 STGENR peripheral ID0 register 0xFE0 32 read-only n 0x0 0x0 PART_0 PART_0 0 8 read-only PIDR1 STGENR_PIDR1 STGENR peripheral ID1 register 0xFE4 32 read-only n 0x0 0x0 DES_0 DES_0 4 4 read-only PART_1 PART_1 0 4 read-only PIDR2 STGENR_PIDR2 STGENR peripheral ID2 register 0xFE8 32 read-only n 0x0 0x0 DES_1 DES_1 0 3 read-only JEDEC JEDEC 3 1 read-only REVISION REVISION 4 4 read-only PIDR3 STGENR_PIDR3 STGENR peripheral ID3 register 0xFEC 32 read-only n 0x0 0x0 CMOD CMOD 0 4 read-only REVAND REVAND 4 4 read-only PIDR4 STGENR_PIDR4 STGENR peripheral ID4 register 0xFD0 32 read-only n 0x0 0x0 DES_2 DES_2 0 4 read-only SIZE SIZE 4 4 read-only PIDR5 STGENR_PIDR5 STGENR peripheral ID5 register 0xFD4 32 read-only n 0x0 0x0 PIDR5 PIDR5 0 32 read-only PIDR6 STGENR_PIDR6 STGENR peripheral ID6 register 0xFD8 32 read-only n 0x0 0x0 PIDR6 PIDR6 0 32 read-only PIDR7 STGENR_PIDR7 STGENR peripheral ID7 register 0xFDC 32 read-only n 0x0 0x0 PIDR7 PIDR7 0 32 read-only SYSCFG SYSCFG SYSCFG 0x0 0x0 0x400 registers n BOOTR SYSCFG_BOOTR This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. ) 0x0 32 read-write n 0x0 0x0 BOOT0 BOOT0 0 1 read-only BOOT0_PD BOOT0_PD 4 1 read-write BOOT1 BOOT1 1 1 read-only BOOT1_PD BOOT1_PD 5 1 read-write BOOT2 BOOT2 2 1 read-only BOOT2_PD BOOT2_PD 6 1 read-write CBR SYSCFG_CBR SYSCFG control timer break register 0x24 32 read-write n 0x0 0x0 CLL CLL 0 1 read-write PVDL PVDL 2 1 read-write CMPCR SYSCFG_CMPCR SYSCFG compensation cell control register 0x20 32 read-write n 0x0 0x0 ANSRC ANSRC 24 4 read-only APSRC APSRC 28 4 read-only CMP_PD CMP_PD 0 1 read-write RANSRC RANSRC 16 4 read-write RAPSRC RAPSRC 20 4 read-write READY READY 8 1 read-only SW_CTRL SW_CTRL 1 1 read-write ICNR SYSCFG_ICNR SYSCFG interconnect control register 0x1C 32 read-write n 0x0 0x0 AXI_M0 AXI_M0 0 1 read-write AXI_M1 AXI_M1 1 1 read-write AXI_M10 AXI_M10 10 1 read-write AXI_M2 AXI_M2 2 1 read-write AXI_M3 AXI_M3 3 1 read-write AXI_M5 AXI_M5 5 1 read-write AXI_M6 AXI_M6 6 1 read-write AXI_M7 AXI_M7 7 1 read-write AXI_M8 AXI_M8 8 1 read-write AXI_M9 AXI_M9 9 1 read-write IOCTRLR SYSCFG_IOCTRLR SYSCFG IO control register 0x18 32 read-write n 0x0 0x0 HSLVEN_ETH HSLVEN_ETH 2 1 HSLVEN_QUADSPI HSLVEN_QUADSPI 1 1 HSLVEN_SDMMC HSLVEN_SDMMC 3 1 HSLVEN_SPI HSLVEN_SPI 4 1 HSLVEN_TRACE HSLVEN_TRACE 0 1 IPIDR SYSCFG_IPIDR SYSCFG identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only PMCR SYSCFG_PMCR SYSCFG peripheral mode configuration register 0x4 32 read-write n 0x0 0x0 ANA0_SEL ANA0_SEL 24 1 read-write ANA1_SEL ANA1_SEL 25 1 read-write ANASWVDD ANASWVDD 9 1 read-write EN_BOOSTER EN_BOOSTER 8 1 read-write ETH_CLK_SEL ETH_CLK_SEL 16 1 read-write ETH_REF_CLK_SEL ETH_REF_CLK_SEL 17 1 read-write ETH_SEL ETH_SEL 21 3 read-write ETH_SELMII ETH_SELMII 20 1 read-write I2C1_FMP I2C1_FMP 0 1 read-write I2C2_FMP I2C2_FMP 1 1 read-write I2C3_FMP I2C3_FMP 2 1 read-write I2C4_FMP I2C4_FMP 3 1 read-write I2C5_FMP I2C5_FMP 4 1 read-write I2C6_FMP I2C6_FMP 5 1 read-write SIDR SYSCFG_SIDR SYSCFG size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only VERR SYSCFG_VERR SYSCFG version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only TAMP TAMP TAMP 0x0 0x0 0x400 registers n ATCR1 TAMP_ATCR1 This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x10 32 read-write n 0x0 0x0 ATCKSEL ATCKSEL 16 3 read-write ATOSEL1 ATOSEL1 8 2 read-write ATOSEL2 ATOSEL2 10 2 read-write ATOSEL3 ATOSEL3 12 2 read-write ATOSHARE ATOSHARE 30 1 read-write ATPER ATPER 24 3 read-write FLTEN FLTEN 31 1 read-write TAMP1AM TAMP1AM 0 1 read-write TAMP2AM TAMP2AM 1 1 read-write TAMP3AM TAMP3AM 2 1 read-write ATOR TAMP_ATOR This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x18 32 read-only n 0x0 0x0 INITS INITS 15 1 read-only PRNG PRNG 0 8 read-only SEEDF SEEDF 14 1 read-only ATSEEDR TAMP_ATSEEDR This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x14 32 write-only n 0x0 0x0 SEED SEED 0 32 write-only BKP0R TAMP_BKP0R TAMP backup 0 register 0x100 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP10R TAMP_BKP10R TAMP backup 10 register 0x128 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP11R TAMP_BKP11R TAMP backup 11 register 0x12C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP12R TAMP_BKP12R TAMP backup 12 register 0x130 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP13R TAMP_BKP13R TAMP backup 13 register 0x134 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP14R TAMP_BKP14R TAMP backup 14 register 0x138 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP15R TAMP_BKP15R TAMP backup 15 register 0x13C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP16R TAMP_BKP16R TAMP backup 16 register 0x140 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP17R TAMP_BKP17R TAMP backup 17 register 0x144 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP18R TAMP_BKP18R TAMP backup 18 register 0x148 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP19R TAMP_BKP19R TAMP backup 19 register 0x14C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP1R TAMP_BKP1R TAMP backup 1 register 0x104 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP20R TAMP_BKP20R TAMP backup 20 register 0x150 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP21R TAMP_BKP21R TAMP backup 21 register 0x154 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP22R TAMP_BKP22R TAMP backup 22 register 0x158 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP23R TAMP_BKP23R TAMP backup 23 register 0x15C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP24R TAMP_BKP24R TAMP backup 24 register 0x160 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP25R TAMP_BKP25R TAMP backup 25 register 0x164 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP26R TAMP_BKP26R TAMP backup 26 register 0x168 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP27R TAMP_BKP27R TAMP backup 27 register 0x16C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP28R TAMP_BKP28R TAMP backup 28 register 0x170 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP29R TAMP_BKP29R TAMP backup 29 register 0x174 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP2R TAMP_BKP2R TAMP backup 2 register 0x108 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP30R TAMP_BKP30R TAMP backup 30 register 0x178 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP31R TAMP_BKP31R TAMP backup 31 register 0x17C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP3R TAMP_BKP3R TAMP backup 3 register 0x10C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP4R TAMP_BKP4R TAMP backup 4 register 0x110 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP5R TAMP_BKP5R TAMP backup 5 register 0x114 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP6R TAMP_BKP6R TAMP backup 6 register 0x118 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP7R TAMP_BKP7R TAMP backup 7 register 0x11C 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP8R TAMP_BKP8R TAMP backup 8 register 0x120 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write BKP9R TAMP_BKP9R TAMP backup 9 register 0x124 32 read-write n 0x0 0x0 BKP BKP 0 32 read-write CFGR TAMP_CFGR TAMP configuration register 0x50 32 read-write n 0x0 0x0 OUT3_RMP OUT3_RMP 0 1 read-write COUNTR TAMP_COUNTR TAMP monotonic counter register 0x40 32 read-only n 0x0 0x0 COUNT COUNT 0 32 read-only CR1 TAMP_CR1 This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x0 32 read-write n 0x0 0x0 ITAMP1E ITAMP1E 16 1 read-write ITAMP2E ITAMP2E 17 1 read-write ITAMP3E ITAMP3E 18 1 read-write ITAMP4E ITAMP4E 19 1 read-write ITAMP5E ITAMP5E 20 1 read-write ITAMP8E ITAMP8E 23 1 read-write TAMP1E TAMP1E 0 1 read-write TAMP2E TAMP2E 1 1 read-write TAMP3E TAMP3E 2 1 read-write CR2 TAMP_CR2 This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x4 32 read-write n 0x0 0x0 TAMP1MSK TAMP1MSK 16 1 read-write TAMP1NOER TAMP1NOER 0 1 read-write TAMP1TRG TAMP1TRG 24 1 read-write TAMP2MSK TAMP2MSK 17 1 read-write TAMP2NOER TAMP2NOER 1 1 read-write TAMP2TRG TAMP2TRG 25 1 read-write TAMP3MSK TAMP3MSK 18 1 read-write TAMP3NOER TAMP3NOER 2 1 read-write TAMP3TRG TAMP3TRG 26 1 read-write FLTCR TAMP_FLTCR This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0xC 32 read-write n 0x0 0x0 TAMPFLT TAMPFLT 3 2 read-write TAMPFREQ TAMPFREQ 0 3 read-write TAMPPRCH TAMPPRCH 5 2 read-write TAMPPUDIS TAMPPUDIS 7 1 read-write HWCFGR1 TAMP_HWCFGR1 TAMP hardware configuration register 1 0x3F0 32 read-only n 0x0 0x0 ACTIVE_TAMPER ACTIVE_TAMPER 12 4 read-only BACKUP_REGS BACKUP_REGS 0 8 read-only INT_TAMPER INT_TAMPER 16 16 read-only TAMPER TAMPER 8 4 read-only HWCFGR2 TAMP_HWCFGR2 TAMP hardware configuration register 2 0x3EC 32 read-only n 0x0 0x0 OPTIONREG_OUT OPTIONREG_OUT 0 8 read-only TRUST_ZONE TRUST_ZONE 8 4 read-only IER TAMP_IER This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x2C 32 read-write n 0x0 0x0 ITAMP1IE ITAMP1IE 16 1 read-write ITAMP2IE ITAMP2IE 17 1 read-write ITAMP3IE ITAMP3IE 18 1 read-write ITAMP4IE ITAMP4IE 19 1 read-write ITAMP5IE ITAMP5IE 20 1 read-write ITAMP8IE ITAMP8IE 23 1 read-write TAMP1IE TAMP1IE 0 1 read-write TAMP2IE TAMP2IE 1 1 read-write TAMP3IE TAMP3IE 2 1 read-write IPIDR TAMP_IPIDR TAMP identification register 0x3F8 32 read-only n 0x0 0x0 ID ID 0 32 read-only MISR TAMP_MISR TAMP non-secure masked interrupt status register 0x34 32 read-only n 0x0 0x0 ITAMP1MF ITAMP1MF 16 1 read-only ITAMP2MF ITAMP2MF 17 1 read-only ITAMP3MF ITAMP3MF 18 1 read-only ITAMP4MF ITAMP4MF 19 1 read-only ITAMP5MF ITAMP5MF 20 1 read-only ITAMP8MF ITAMP8MF 23 1 read-only TAMP1MF TAMP1MF 0 1 read-only TAMP2MF TAMP2MF 1 1 read-only TAMP3MF TAMP3MF 2 1 read-only SCR TAMP_SCR TAMP status clear register 0x3C 32 read-write n 0x0 0x0 CITAMP1F CITAMP1F 16 1 write-only CITAMP2F CITAMP2F 17 1 write-only CITAMP3F CITAMP3F 18 1 write-only CITAMP4F CITAMP4F 19 1 write-only CITAMP5F CITAMP5F 20 1 write-only CITAMP8F CITAMP8F 23 1 write-only CTAMP1F CTAMP1F 0 1 write-only CTAMP2F CTAMP2F 1 1 write-only CTAMP3F CTAMP3F 2 1 write-only SIDR TAMP_SIDR TAMP size identification register 0x3FC 32 read-only n 0x0 0x0 SID SID 0 32 read-only SMCR TAMP_SMCR This register can be written only when the APB access is secure. 0x20 32 read-write n 0x0 0x0 BKPRWDPROT BKPRWDPROT 0 8 read-write BKPWDPROT BKPWDPROT 16 8 read-write TAMPDPROT TAMPDPROT 31 1 read-write SMISR TAMP_SMISR TAMP secure masked interrupt status register 0x38 32 read-only n 0x0 0x0 ITAMP1MF ITAMP1MF 16 1 read-only ITAMP2MF ITAMP2MF 17 1 read-only ITAMP3MF ITAMP3MF 18 1 read-only ITAMP4MF ITAMP4MF 19 1 read-only ITAMP5MF ITAMP5MF 20 1 read-only ITAMP8MF ITAMP8MF 23 1 read-only TAMP1MF TAMP1MF 0 1 read-only TAMP2MF TAMP2MF 1 1 read-only TAMP3MF TAMP3MF 2 1 read-only SR TAMP_SR This register can be protected against non-secure access. Refer to Section24.3.3: TAMP secure protection modes. 0x30 32 read-only n 0x0 0x0 ITAMP1F ITAMP1F 16 1 read-only ITAMP2F ITAMP2F 17 1 read-only ITAMP3F ITAMP3F 18 1 read-only ITAMP4F ITAMP4F 19 1 read-only ITAMP5F ITAMP5F 20 1 read-only ITAMP8F ITAMP8F 23 1 read-only TAMP1F TAMP1F 0 1 read-only TAMP2F TAMP2F 1 1 read-only TAMP3F TAMP3F 2 1 read-only VERR TAMP_VERR TAMP version register 0x3F4 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only TEMP TEMP TEMP 0x0 0x0 0x400 registers n CFGR1 TEMP_CFGR1 DTS_CFGR1 is the configuration register for temperature sensor 1. 0x0 32 read-write n 0x0 0x0 HSREF_CLK_DIV HSREF_CLK_DIV 24 7 read-write Q_MEAS_opt Q_MEAS_opt 21 1 read-write REFCLK_SEL REFCLK_SEL 20 1 read-write TS1_EN TS1_EN 0 1 read-write TS1_INTRIG_SEL TS1_INTRIG_SEL 8 4 read-write TS1_SMP_TIME TS1_SMP_TIME 16 4 read-write TS1_START TS1_START 4 1 read-write DR TEMP_DR The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency. 0x1C 32 read-write n 0x0 0x0 TS1_MFREQ TS1_MFREQ 0 16 read-write ICIFR TEMP_ICIFR DTS_ICIFR is the control register for the interrupt flags. 0x28 32 read-write n 0x0 0x0 TS1_CAITEF TS1_CAITEF 4 1 read-write TS1_CAITHF TS1_CAITHF 6 1 read-write TS1_CAITLF TS1_CAITLF 5 1 read-write TS1_CITEF TS1_CITEF 0 1 read-write TS1_CITHF TS1_CITHF 2 1 read-write TS1_CITLF TS1_CITLF 1 1 read-write ITENR TEMP_ITENR Temperature sensor interrupt enable register 0x24 32 read-write n 0x0 0x0 TS1_AITEEN TS1_AITEEN 4 1 read-write TS1_AITHEN TS1_AITHEN 6 1 read-write TS1_AITLEN TS1_AITLEN 5 1 read-write TS1_ITEEN TS1_ITEEN 0 1 read-write TS1_ITHEN TS1_ITHEN 2 1 read-write TS1_ITLEN TS1_ITLEN 1 1 read-write ITR1 TEMP_ITR1 DTS_ITR1 contains the threshold values for sensor 1. 0x14 32 read-write n 0x0 0x0 TS1_HITTHD TS1_HITTHD 16 16 read-write TS1_LITTHD TS1_LITTHD 0 16 read-write OR TEMP_OR The DTS_OR contains general-purpose option bits. 0x2C 32 read-write n 0x0 0x0 TS_Op0 TS_Op0 0 1 read-write TS_Op1 TS_Op1 1 1 read-write TS_Op10 TS_Op10 10 1 read-write TS_Op11 TS_Op11 11 1 read-write TS_Op12 TS_Op12 12 1 read-write TS_Op13 TS_Op13 13 1 read-write TS_Op14 TS_Op14 14 1 read-write TS_Op15 TS_Op15 15 1 read-write TS_Op16 TS_Op16 16 1 read-write TS_Op17 TS_Op17 17 1 read-write TS_Op18 TS_Op18 18 1 read-write TS_Op19 TS_Op19 19 1 read-write TS_Op2 TS_Op2 2 1 read-write TS_Op20 TS_Op20 20 1 read-write TS_Op21 TS_Op21 21 1 read-write TS_Op22 TS_Op22 22 1 read-write TS_Op23 TS_Op23 23 1 read-write TS_Op24 TS_Op24 24 1 read-write TS_Op25 TS_Op25 25 1 read-write TS_Op26 TS_Op26 26 1 read-write TS_Op27 TS_Op27 27 1 read-write TS_Op28 TS_Op28 28 1 read-write TS_Op29 TS_Op29 29 1 read-write TS_Op3 TS_Op3 3 1 read-write TS_Op30 TS_Op30 30 1 read-write TS_Op31 TS_Op31 31 1 read-write TS_Op4 TS_Op4 4 1 read-write TS_Op5 TS_Op5 5 1 read-write TS_Op6 TS_Op6 6 1 read-write TS_Op7 TS_Op7 7 1 read-write TS_Op8 TS_Op8 8 1 read-write TS_Op9 TS_Op9 9 1 read-write RAMPVALR TEMP_RAMPVALR The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed. 0x10 32 read-only n 0x0 0x0 TS1_RAMP_COEFF TS1_RAMP_COEFF 0 16 read-only SR TEMP_SR Temperature sensor status register 0x20 32 read-only n 0x0 0x0 TS1_AITEF TS1_AITEF 4 1 read-only TS1_AITHF TS1_AITHF 6 1 read-only TS1_AITLF TS1_AITLF 5 1 read-only TS1_ITEF TS1_ITEF 0 1 read-only TS1_ITHF TS1_ITHF 2 1 read-only TS1_ITLF TS1_ITLF 1 1 read-only TS1_RDY TS1_RDY 15 1 read-only T0VALR1 TEMP_T0VALR1 DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed. 0x8 32 read-only n 0x0 0x0 TS1_FMT0 TS1_FMT0 0 16 read-only TS1_T0 TS1_T0 16 2 read-only TIM1 TIM1 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 DMA address for full transfer 0x60 32 read-write n 0x0 0x0 BKDF1BK0E BKDF1BK0E 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 TIMx_AF2 TIMx_AF2 DMA address for full transfer 0x64 32 read-write n 0x0 0x0 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INE BRK2 BKIN input enable 0 1 BK2INP BRK2 BKIN input polarity 9 1 TIMx_ARR TIMx_ARR TIM1/TIM8 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BK2BID BK2BID 29 1 read-write BK2DSRM BK2DSRM 27 1 read-write BK2E BK2E 24 1 read-write BK2F BK2F 20 4 read-write BK2P BK2P 25 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (output mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (output mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCMR3 TIMx_CCMR2 capture/compare mode register 3 (output mode) 0x54 32 read-write n 0x0 0x0 OC5CE Output compare 3 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_3 OC5M_3 16 1 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_3 OC6M_3 24 1 OC6PE Output compare 6 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 TIM1/TIM8 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CCR2 TIMx_CCR2 TIM1/TIM8 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 read-write TIMx_CCR3 TIMx_CCR3 TIM1/TIM8 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 read-write TIMx_CCR4 TIMx_CCR4 TIM1/TIM8 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 read-write TIMx_CCR5 TIMx_CCR5 TIM1/TIM8 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 read-write GC5C1 GC5C1 29 1 read-write GC5C2 GC5C2 30 1 read-write GC5C3 GC5C3 31 1 read-write TIMx_CCR6 TIMx_CCR6 TIM1/TIM8 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 read-write TIMx_CNT TIMx_CNT TIM1/TIM8 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM1/TIM8 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM1/TIM8 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write MMS MMS 4 3 read-write MMS2 MMS2 20 4 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write OIS2 OIS2 10 1 read-write OIS2N OIS2N 11 1 read-write OIS3 OIS3 12 1 read-write OIS3N OIS3N 13 1 read-write OIS4 OIS4 14 1 read-write OIS5 OIS5 16 1 read-write OIS6 OIS6 18 1 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIM1/TIM8 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM1/TIM8 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 TIMx_EGR TIMx_EGR TIM1/TIM8 event generation register 0x14 32 write-only n 0x0 0x0 B2G B2G 8 1 write-only BG BG 7 1 write-only CC1G CC1G 1 1 write-only CC2G CC2G 2 1 write-only CC3G CC3G 3 1 write-only CC4G CC4G 4 1 write-only COMG COMG 5 1 write-only TG TG 6 1 write-only UG UG 0 1 write-only TIMx_PSC TIMx_PSC TIM1/TIM8 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM1/TIM8 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 read-write TIMx_SMCR TIMx_SMCR TIM1/TIM8 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 read-write ETF ETF 8 4 read-write ETP ETP 15 1 read-write ETPS ETPS 12 2 read-write MSM MSM 7 1 read-write SMS SMS 0 3 read-write SMS_3 SMS_3 16 1 read-write TS TS 4 3 read-write TS_4_3 TS_4_3 20 2 read-write TIMx_SR TIMx_SR TIM1/TIM8 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 read-write BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write CC5IF CC5IF 16 1 read-write CC6IF CC6IF 17 1 read-write COMIF COMIF 5 1 read-write SBIF SBIF 13 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIM1 timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TIM12 TIM12 TIMER 0x0 0x0 0x400 registers n TIMx_ARR TIMx_ARR TIM12 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_CCER TIMx_CCER TIM12 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 TIM12 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CCR2 TIMx_CCR2 TIM12 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 read-write TIMx_CNT TIMx_CNT TIM12 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-write TIMx_CR1 TIMx_CR1 TIM12 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_DIER TIMx_DIER TIM12 Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1IE CC1IE 1 1 read-write CC2IE CC2IE 2 1 read-write TIE TIE 6 1 read-write UIE UIE 0 1 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIM12 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TIMx_SR TIMx_SR TIM12 status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TIM13 TIM13 TIMER 0x0 0x0 0x400 registers n TIMx_ARR TIMx_ARR TIMx auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 TIMx_CCR1 TIMx_CCR1 TIMx capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIMx counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_DIER TIMx_DIER TIMx DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1IE CC1IE 1 1 read-write UIE UIE 0 1 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM14 TIM13 TIMER 0x0 0x0 0x400 registers n TIMx_ARR TIMx_ARR TIMx auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 TIMx_CCR1 TIMx_CCR1 TIMx capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIMx counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_DIER TIMx_DIER TIMx DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1IE CC1IE 1 1 read-write UIE UIE 0 1 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM15 TIM15 TIMER 0x0 0x0 0x400 registers n AF1 TIM15_AF1 TIM15 alternate register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK0E BKDF1BK0E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write ARR TIM15_ARR TIM15 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write CCER TIM15_CCER TIM15 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CCR1 TIM15_CCR1 TIM15 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write CCR2 TIM15_CCR2 TIM15 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 read-write CNT TIM15_CNT TIM15 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 TIM15_CR1 TIM15 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write CR2 TIM15_CR2 TIM15 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write MMS MMS 4 3 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write OIS2 OIS2 10 1 read-write TI1S TI1S 7 1 read-write DCR TIM15_DCR TIM15 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write DIER TIM15_DIER TIM15 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write DMAR TIM15_DMAR TIM15 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write PSC TIM15_PSC TIM15 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write RCR TIM15_RCR TIM15 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write SR TIM15_SR TIM15 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write COMIF COMIF 5 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_BDTR TIMx_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 BG BG 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 COMG COMG 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TISEL TIM15_TISEL TIM15 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TIM16 TIM16 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIM17_AF1 TIM17 alternate function register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK2E BKDF1BK2E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write TIMx_ARR TIMx_ARR TIM16/TIM17 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER TIM16/TIM17 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCR1 TIMx_CCR1 TIM16/TIM17 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIM16/TIM17 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM16/TIM17 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM16/TIM17 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write TIMx_DCR TIMx_DCR TIM16/TIM17 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM16/TIM17 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIM16/TIM17 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIM16/TIM17 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM16/TIM17 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write TIMx_SR TIMx_SR TIM16/TIM17 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write COMIF COMIF 5 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIM17_TISEL TIM17 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM17 TIM16 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIM17_AF1 TIM17 alternate function register 1 0x60 32 read-write n 0x0 0x0 BKDF1BK2E BKDF1BK2E 8 1 read-write BKINE BKINE 0 1 read-write BKINP BKINP 9 1 read-write TIMx_ARR TIMx_ARR TIM16/TIM17 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER TIM16/TIM17 capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NE CC1NE 2 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write TIMx_CCR1 TIMx_CCR1 TIM16/TIM17 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CNT TIMx_CNT TIM16/TIM17 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM16/TIM17 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM16/TIM17 control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write TIMx_DCR TIMx_DCR TIM16/TIM17 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM16/TIM17 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIM16/TIM17 DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIM16/TIM17 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM16/TIM17 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 8 read-write TIMx_SR TIMx_SR TIM16/TIM17 status register 0x10 16 read-write n 0x0 0x0 BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write COMIF COMIF 5 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIM17_TISEL TIM17 input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TIM2 TIM2 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4NP CC4NP 15 1 read-write CC4P CC4P 13 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (input mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 TIMx_CCR2 TIMx_CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 TIMx_CCR3 TIMx_CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 TIMx_CCR4 TIMx_CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 TIMx_CNT TIMx_CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIMx control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write MMS MMS 4 3 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIMx DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIMx DMA/Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIMx DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TI3SEL TI3SEL 16 4 read-write TI4SEL TI4SEL 24 4 read-write TIM3 TIM2 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4NP CC4NP 15 1 read-write CC4P CC4P 13 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (input mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 TIMx_CCR2 TIMx_CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 TIMx_CCR3 TIMx_CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 TIMx_CCR4 TIMx_CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 TIMx_CNT TIMx_CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIMx control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write MMS MMS 4 3 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIMx DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIMx DMA/Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIMx DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TI3SEL TI3SEL 16 4 read-write TI4SEL TI4SEL 24 4 read-write TIM4 TIM2 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4NP CC4NP 15 1 read-write CC4P CC4P 13 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (input mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 TIMx_CCR2 TIMx_CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 TIMx_CCR3 TIMx_CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 TIMx_CCR4 TIMx_CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 TIMx_CNT TIMx_CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIMx control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write MMS MMS 4 3 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIMx DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIMx DMA/Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIMx DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TI3SEL TI3SEL 16 4 read-write TI4SEL TI4SEL 24 4 read-write TIM5 TIM2 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 ETRSEL External trigger source selection 14 4 TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 TIMx_CCER TIMx_CCER TIMx capture/compare enable register 0x20 16 read-write n 0x0 0x0 CC1E CC1E 0 1 read-write CC1NP CC1NP 3 1 read-write CC1P CC1P 1 1 read-write CC2E CC2E 4 1 read-write CC2NP CC2NP 7 1 read-write CC2P CC2P 5 1 read-write CC3E CC3E 8 1 read-write CC3NP CC3NP 11 1 read-write CC3P CC3P 9 1 read-write CC4E CC4E 12 1 read-write CC4NP CC4NP 15 1 read-write CC4P CC4P 13 1 read-write TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (input mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (input mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 TIMx_CCR2 TIMx_CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 TIMx_CCR3 TIMx_CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 TIMx_CCR4 TIMx_CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 TIMx_CNT TIMx_CNT counter 0x24 32 read-write n 0x0 0x0 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 TIMx_CR1 TIMx_CR1 TIMx control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIMx control register 2 0x4 16 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write MMS MMS 4 3 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIMx DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIMx DMA/Interrupt enable register 0xC 16 read-write n 0x0 0x0 CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR TIMx DMA address for full transfer 0x4C 16 read-write n 0x0 0x0 DMAB DMAB 0 16 read-write TIMx_EGR TIMx_EGR event generation register 0x14 32 write-only n 0x0 0x0 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 TG Trigger generation 6 1 UG Update generation 0 1 TIMx_PSC TIMx_PSC TIMx prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_SMCR TIMx_SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection 20 2 TIMx_SR TIMx_SR TIMx status register 0x10 16 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIMx timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 read-write TI2SEL TI2SEL 8 4 read-write TI3SEL TI3SEL 16 4 read-write TI4SEL TI4SEL 24 4 read-write TIM6 TIM6 TIMER 0x0 0x0 0x400 registers n TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 TIMx_CNT TIMx_CNT TIM6/TIM7 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM6/TIM7 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM6/TIM7 control register 2 0x4 32 read-write n 0x0 0x0 MMS MMS 4 3 read-write TIMx_DIER TIMx_DIER TIM6/TIM7 DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE UDE 8 1 read-only UIE UIE 0 1 read-write TIMx_EGR TIMx_EGR TIM6/TIM7 event generation register 0x14 32 read-write n 0x0 0x0 UG UG 0 1 read-write TIMx_PSC TIMx_PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 TIMx_SR TIMx_SR TIM6/TIM7 status register 0x10 32 read-write n 0x0 0x0 UIF UIF 0 1 read-write TIM7 TIM6 TIMER 0x0 0x0 0x400 registers n TIMx_ARR TIMx_ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 TIMx_CNT TIMx_CNT TIM6/TIM7 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM6/TIM7 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM6/TIM7 control register 2 0x4 32 read-write n 0x0 0x0 MMS MMS 4 3 read-write TIMx_DIER TIMx_DIER TIM6/TIM7 DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE UDE 8 1 read-only UIE UIE 0 1 read-write TIMx_EGR TIMx_EGR TIM6/TIM7 event generation register 0x14 32 read-write n 0x0 0x0 UG UG 0 1 read-write TIMx_PSC TIMx_PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 TIMx_SR TIMx_SR TIM6/TIM7 status register 0x10 32 read-write n 0x0 0x0 UIF UIF 0 1 read-write TIM8 TIM1 TIMER 0x0 0x0 0x400 registers n TIMx_AF1 TIMx_AF1 DMA address for full transfer 0x60 32 read-write n 0x0 0x0 BKDF1BK0E BKDF1BK0E 8 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 TIMx_AF2 TIMx_AF2 DMA address for full transfer 0x64 32 read-write n 0x0 0x0 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INE BRK2 BKIN input enable 0 1 BK2INP BRK2 BKIN input polarity 9 1 TIMx_ARR TIMx_ARR TIM1/TIM8 auto-reload register 0x2C 16 read-write n 0x0 0x0 ARR ARR 0 16 read-write TIMx_BDTR TIMx_BDTR As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. 0x44 32 read-write n 0x0 0x0 AOE AOE 14 1 read-write BK2BID BK2BID 29 1 read-write BK2DSRM BK2DSRM 27 1 read-write BK2E BK2E 24 1 read-write BK2F BK2F 20 4 read-write BK2P BK2P 25 1 read-write BKBID BKBID 28 1 read-write BKDSRM BKDSRM 26 1 read-write BKE BKE 12 1 read-write BKF BKF 16 4 read-write BKP BKP 13 1 read-write DTG DTG 0 8 read-write LOCK LOCK 8 2 read-write MOE MOE 15 1 read-write OSSI OSSI 10 1 read-write OSSR OSSR 11 1 read-write TIMx_CCER TIMx_CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 TIMx_CCMR1_Input TIMx_CCMR1_Input capture/compare mode register 1 (output mode) TIMx_CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 TIMx_CCMR1_Output TIMx_CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 TIMx_CCMR2_Input TIMx_CCMR2_Input capture/compare mode register 2 (output mode) TIMx_CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 TIMx_CCMR2_Output TIMx_CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 TIMx_CCMR3 TIMx_CCMR2 capture/compare mode register 3 (output mode) 0x54 32 read-write n 0x0 0x0 OC5CE Output compare 3 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_3 OC5M_3 16 1 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_3 OC6M_3 24 1 OC6PE Output compare 6 preload enable 11 1 TIMx_CCR1 TIMx_CCR1 TIM1/TIM8 capture/compare register 1 0x34 16 read-write n 0x0 0x0 CCR1 CCR1 0 16 read-write TIMx_CCR2 TIMx_CCR2 TIM1/TIM8 capture/compare register 2 0x38 16 read-write n 0x0 0x0 CCR2 CCR2 0 16 read-write TIMx_CCR3 TIMx_CCR3 TIM1/TIM8 capture/compare register 3 0x3C 16 read-write n 0x0 0x0 CCR3 CCR3 0 16 read-write TIMx_CCR4 TIMx_CCR4 TIM1/TIM8 capture/compare register 4 0x40 16 read-write n 0x0 0x0 CCR4 CCR4 0 16 read-write TIMx_CCR5 TIMx_CCR5 TIM1/TIM8 capture/compare register 5 0x58 32 read-write n 0x0 0x0 CCR5 CCR5 0 16 read-write GC5C1 GC5C1 29 1 read-write GC5C2 GC5C2 30 1 read-write GC5C3 GC5C3 31 1 read-write TIMx_CCR6 TIMx_CCR6 TIM1/TIM8 capture/compare register 6 0x5C 16 read-write n 0x0 0x0 CCR6 CCR6 0 16 read-write TIMx_CNT TIMx_CNT TIM1/TIM8 counter 0x24 32 read-write n 0x0 0x0 CNT CNT 0 16 read-write UIFCPY UIFCPY 31 1 read-only TIMx_CR1 TIMx_CR1 TIM1/TIM8 control register 1 0x0 16 read-write n 0x0 0x0 ARPE ARPE 7 1 read-write CEN CEN 0 1 read-write CKD CKD 8 2 read-write CMS CMS 5 2 read-write DIR DIR 4 1 read-write OPM OPM 3 1 read-write UDIS UDIS 1 1 read-write UIFREMAP UIFREMAP 11 1 read-write URS URS 2 1 read-write TIMx_CR2 TIMx_CR2 TIM1/TIM8 control register 2 0x4 32 read-write n 0x0 0x0 CCDS CCDS 3 1 read-write CCPC CCPC 0 1 read-write CCUS CCUS 2 1 read-write MMS MMS 4 3 read-write MMS2 MMS2 20 4 read-write OIS1 OIS1 8 1 read-write OIS1N OIS1N 9 1 read-write OIS2 OIS2 10 1 read-write OIS2N OIS2N 11 1 read-write OIS3 OIS3 12 1 read-write OIS3N OIS3N 13 1 read-write OIS4 OIS4 14 1 read-write OIS5 OIS5 16 1 read-write OIS6 OIS6 18 1 read-write TI1S TI1S 7 1 read-write TIMx_DCR TIMx_DCR TIM1/TIM8 DMA control register 0x48 16 read-write n 0x0 0x0 DBA DBA 0 5 read-write DBL DBL 8 5 read-write TIMx_DIER TIMx_DIER TIM1/TIM8 DMA/interrupt enable register 0xC 16 read-write n 0x0 0x0 BIE BIE 7 1 read-write CC1DE CC1DE 9 1 read-write CC1IE CC1IE 1 1 read-write CC2DE CC2DE 10 1 read-write CC2IE CC2IE 2 1 read-write CC3DE CC3DE 11 1 read-write CC3IE CC3IE 3 1 read-write CC4DE CC4DE 12 1 read-write CC4IE CC4IE 4 1 read-write COMDE COMDE 13 1 read-write COMIE COMIE 5 1 read-write TDE TDE 14 1 read-write TIE TIE 6 1 read-write UDE UDE 8 1 read-write UIE UIE 0 1 read-write TIMx_DMAR TIMx_DMAR DMA address for full transfer 0x4C 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 16 TIMx_EGR TIMx_EGR TIM1/TIM8 event generation register 0x14 32 write-only n 0x0 0x0 B2G B2G 8 1 write-only BG BG 7 1 write-only CC1G CC1G 1 1 write-only CC2G CC2G 2 1 write-only CC3G CC3G 3 1 write-only CC4G CC4G 4 1 write-only COMG COMG 5 1 write-only TG TG 6 1 write-only UG UG 0 1 write-only TIMx_PSC TIMx_PSC TIM1/TIM8 prescaler 0x28 16 read-write n 0x0 0x0 PSC PSC 0 16 read-write TIMx_RCR TIMx_RCR TIM1/TIM8 repetition counter register 0x30 16 read-write n 0x0 0x0 REP REP 0 16 read-write TIMx_SMCR TIMx_SMCR TIM1/TIM8 slave mode control register 0x8 32 read-write n 0x0 0x0 ECE ECE 14 1 read-write ETF ETF 8 4 read-write ETP ETP 15 1 read-write ETPS ETPS 12 2 read-write MSM MSM 7 1 read-write SMS SMS 0 3 read-write SMS_3 SMS_3 16 1 read-write TS TS 4 3 read-write TS_4_3 TS_4_3 20 2 read-write TIMx_SR TIMx_SR TIM1/TIM8 status register 0x10 32 read-write n 0x0 0x0 B2IF B2IF 8 1 read-write BIF BIF 7 1 read-write CC1IF CC1IF 1 1 read-write CC1OF CC1OF 9 1 read-write CC2IF CC2IF 2 1 read-write CC2OF CC2OF 10 1 read-write CC3IF CC3IF 3 1 read-write CC3OF CC3OF 11 1 read-write CC4IF CC4IF 4 1 read-write CC4OF CC4OF 12 1 read-write CC5IF CC5IF 16 1 read-write CC6IF CC6IF 17 1 read-write COMIF COMIF 5 1 read-write SBIF SBIF 13 1 read-write TIF TIF 6 1 read-write UIF UIF 0 1 read-write TIMx_TISEL TIMx_TISEL TIM1 timer input selection register 0x68 32 read-write n 0x0 0x0 TI1SEL TI1SEL 0 4 TI2SEL TI2SEL 8 4 TI3SEL TI3SEL 16 4 TI4SEL TI4SEL 24 4 TZC TZC TZC 0x0 0x0 0x1000 registers n ACTION ACTION TZC action register 0x4 32 read-write n 0x0 0x0 REACTION_VALUE Permission failure reaction 0 2 BUILD_CONFIG BUILD_CONFIG TZC configuration register 0x0 32 read-write n 0x0 0x0 ADDRESS_WIDTH ADDRESS WIDTH 8 6 NO_OF_FILTERS Number of filters 24 2 NO_OF_REGIONS Number fo regions 0 5 CID0 CID0 TZC component ID 0 register 0xFF0 32 read-only n 0x0 0x0 COMP_ID_0 Component ID 0 0 8 CID1 CID1 TZC component ID 1 register 0xFF4 32 read-only n 0x0 0x0 COMP_ID_1 Component ID 1 0 8 CID2 CID2 TZC component ID 2 register 0xFF8 32 read-only n 0x0 0x0 COMP_ID_2 Component ID 2 0 8 CID3 CID3 TZC component ID 3 register 0xFFC 32 read-only n 0x0 0x0 COMP_ID_3 Component ID 3 0 8 FAIL_ADDRESS_LOW0 FAIL_ADDRESS_LOW0 TZC fail address low register0 0x20 32 read-only n 0x0 0x0 ADDR_STATUS_LOW Fail address low bits 0 32 FAIL_ADDRESS_LOW1 FAIL_ADDRESS_LOW1 TZC fail address low register1 0x30 32 read-only n 0x0 0x0 ADDR_STATUS_LOW Fail address low bits 0 32 FAIL_CONTROL0 FAIL_CONTROL0 TZC fail control register 0 0x28 32 read-only n 0x0 0x0 DIRECTION Access failure direction 24 1 NON_SECURE Non-secure access failure 21 1 PRIVILEGE Privilege access failure 20 1 FAIL_CONTROL1 FAIL_CONTROL1 TZC fail control register 1 0x38 32 read-only n 0x0 0x0 DIRECTION Access failure direction 24 1 NON_SECURE Non-secure access failure 21 1 PRIVILEGE Privilege access failure 20 1 FAIL_ID0 FAIL_ID0 TZC fail ID register 0 0x2C 32 read-only n 0x0 0x0 ID AXI fail ID 0 11 FAIL_ID1 FAIL_ID1 TZC fail ID register 1 0x3C 32 read-only n 0x0 0x0 ID AXI fail ID 0 11 GATE_KEEPER GATE_KEEPER TZC gate keeper register 0x8 32 read-write n 0x0 0x0 OPENREQ Gate keeper open request 0 2 OPENSTAT Gate keeper status for each filter 16 2 INT_CLEAR INT_CLEAR TZC interrupt clear register 0x14 32 write-only n 0x0 0x0 CLEAR Filter interrupt clear 0 2 INT_STATUS INT_STATUS TZC interrupt status register 0x10 32 read-only n 0x0 0x0 OVERLAP Overlap violation for each filter 16 2 OVERRUN Permission failure overrun 8 2 STATUS Interrupt status for each filter 0 1 PID0 PID0 TZC peripheral ID 0 register 0xFE0 32 read-only n 0x0 0x0 PER_ID_0 Peripheral ID 0 0 8 PID1 PID1 TZC peripheral ID 1 register 0xFE4 32 read-only n 0x0 0x0 PER_ID_1 Peripheral ID 1 0 8 PID2 PID2 TZC peripheral ID 2 register 0xFE8 32 read-only n 0x0 0x0 PER_ID_2 Peripheral ID 2 0 8 PID3 PID3 TZC peripheral ID 3 register 0xFEC 32 read-only n 0x0 0x0 PER_ID_3 Peripheral ID 3 0 8 PID4 PID4 TZC peripheral ID 4 register 0xFD0 32 read-only n 0x0 0x0 PER_ID_4 Peripheral ID 4 0 8 PID5 PID5 TZC peripheral ID 5 register 0xFD4 32 read-only n 0x0 0x0 PER_ID_5 Peripheral ID 5 0 8 PID6 PID6 TZC peripheral ID 6 register 0xFD8 32 read-only n 0x0 0x0 PER_ID_6 Peripheral ID 6 0 8 PID7 PID7 TZC peripheral ID 7 register 0xFDC 32 read-only n 0x0 0x0 PER_ID_7 Peripheral ID 7 0 8 REGION_ATTRIBUTE0 REGION_ATTRIBUTE0 TZC region 0 attribute register 0x110 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE1 REGION_ATTRIBUTE1 TZC region 2 attribute register 0x130 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE2 REGION_ATTRIBUTE2 TZC region 2 attribute register 0x150 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE3 REGION_ATTRIBUTE3 TZC region 3 attribute register 0x170 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE4 REGION_ATTRIBUTE4 TZC region 4 attribute register 0x190 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE5 REGION_ATTRIBUTE5 TZC region 5 attribute register 0x1B0 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE6 REGION_ATTRIBUTE6 TZC region 6 attribute register 0x1D0 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE7 REGION_ATTRIBUTE7 TZC region 7 attribute register 0x1F0 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_ATTRIBUTE8 REGION_ATTRIBUTE8 TZC region 8 attribute register 0x210 32 read-write n 0x0 0x0 FILTER_EN Region enable for each filter 0 2 S_RD_EN Secure global read enable 30 1 S_WR_EN Secure global write enable 31 1 REGION_BASE_LOW0 REGION_BASE_LOW0 TZC region 0 base address low register 0x100 32 read-only n 0x0 0x0 BASE_ADDRESS_LOW base address bits 12 20 REGION_BASE_LOW1 REGION_BASE_LOW1 TZC region 1 ID access register 0x120 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW2 REGION_BASE_LOW2 TZC region 2 ID access register 0x140 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW3 REGION_BASE_LOW3 TZC region 3 ID access register 0x160 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW4 REGION_BASE_LOW4 TZC region 4 ID access register 0x180 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW5 REGION_BASE_LOW5 TZC region 5 ID access register 0x1A0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW6 REGION_BASE_LOW6 TZC region 6 ID access register 0x1C0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW7 REGION_BASE_LOW7 TZC region 7 ID access register 0x1E0 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_BASE_LOW8 REGION_BASE_LOW8 TZC region 8 ID access register 0x200 32 read-write n 0x0 0x0 BASE_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_ID_ACCESS0 REGION_ID_ACCESS0 TZC region 0 ID access register 0x114 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS1 REGION_ID_ACCESS1 TZC region 1 ID access register 0x134 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS2 REGION_ID_ACCESS2 TZC region 2 ID access register 0x154 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS3 REGION_ID_ACCESS3 TZC region 3 ID access register 0x174 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS4 REGION_ID_ACCESS4 TZC region 4 ID access register 0x194 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS5 REGION_ID_ACCESS5 TZC region 5 ID access register 0x1B4 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS6 REGION_ID_ACCESS6 TZC region 6 ID access register 0x1D4 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS7 REGION_ID_ACCESS7 TZC region 7 ID access register 0x1F4 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_ID_ACCESS8 REGION_ID_ACCESS8 TZC region 8 ID access register 0x214 32 read-write n 0x0 0x0 NSAID_RD_EN Region enable for each filter 0 16 NSAID_WR_EN Secure global write enable 16 16 REGION_TOP_LOW0 REGION_TOP_LOW0 TZC region 0 top address low register 0x108 32 read-only n 0x0 0x0 TOP_ADDRESS_LOW Top address bits 12 20 REGION_TOP_LOW1 REGION_TOP_LOW1 TZC regions 1 top address low register 0x128 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW2 REGION_TOP_LOW2 TZC regions 2 top address low register 0x148 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW3 REGION_TOP_LOW3 TZC regions 3 top address low register 0x168 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW4 REGION_TOP_LOW4 TZC regions 4 top address low register 0x188 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW5 REGION_TOP_LOW5 TZC regions 5 top address low register 0x1A8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW6 REGION_TOP_LOW6 TZC regions 6 top address low register 0x1C8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW7 REGION_TOP_LOW7 TZC regions 7 top address low register 0x1E8 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 REGION_TOP_LOW8 REGION_TOP_LOW8 TZC regions 8 top address low register 0x208 32 read-write n 0x0 0x0 TOP_ADDRESS_LOW Base address bits[31:12] for region 12 20 SPECULATION_CTRL SPECULATION_CTRL TZC speculation control register 0xC 32 read-write n 0x0 0x0 READSPEC_DISABLE Read access speculation disable 0 1 WRITESPEC_DISABLE Write access speculation disable 1 1 UART4 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART5 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART7 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 UART8 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART3 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USART6 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR_0_3 BRR_0_3 0 4 BRR_4_15 BRR_4_15 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT DEAT 21 5 DEDT DEDT 16 5 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFO mode enable 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFIFO Full interrupt enable 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFIFO empty interrupt enable 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD Auto baud rate mode 21 2 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS When the DSI_NSS bit is set, the NSS pin input will be ignored 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN Synchronous Slave mode enable 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG Receive FIFO threshold configuration 25 3 RXFTIE RXFIFO threshold interrupt enable 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE Tr Complete before guard time, interrupt enable 24 1 TXFTCFG TXFIFO threshold configuration 29 3 TXFTIE threshold interrupt enable 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 HWCFGR1 HWCFGR1 USART Hardware Configuration register 1 0x3F0 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 CFG3 CFG3 8 4 CFG4 CFG4 12 4 CFG5 CFG5 16 4 CFG6 CFG6 20 4 CFG7 CFG7 24 4 CFG8 CFG8 28 4 HWCFGR2 HWCFGR2 USART Hardware Configuration register 2 0x3EC 32 read-only n 0x0 0x0 CFG1 CFG1 0 4 CFG2 CFG2 4 4 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF Transmission complete before Guard time clear flag 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFIFO empty clear flag 5 1 UDRCF SPI slave underrun clear flag 13 1 WUCF Wakeup from Stop mode clear flag 20 1 IPIDR IPIDR EXTI Identification register 0x3F8 32 read-only n 0x0 0x0 IPID IP Identification 0 32 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFIFO Full 24 1 RXFT RXFIFO threshold flag 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT Transmission complete before guard time flag 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFIFO Empty 23 1 TXFT TXFIFO threshold flag 27 1 UDR SPI slave underrun error flag 13 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER Clock prescaler 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 SIDR SIDR EXTI Size ID register 0x3FC 32 read-only n 0x0 0x0 SID Size Identification 0 32 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 VERR VERR EXTI IP Version register 0x3F4 32 read-only n 0x0 0x0 MAJREV Major Revision number 4 4 MINREV Minor Revision number 0 4 USBPHYC USBPHYC USBPHYC 0x0 0x0 0x1000 registers n MISC USBPHYC_MISC This register is used to control the switch between controllers for the HS PHY. 0x8 32 read-write n 0x0 0x0 PPCKDIS PPCKDIS 1 2 read-write SWITHOST SWITHOST 0 1 read-write PLL USBPHYC_PLL This register is used to control the PLL of the HS PHY. 0x0 32 read-write n 0x0 0x0 PLLDITHEN0 PLLDITHEN0 30 1 read-write PLLDITHEN1 PLLDITHEN1 31 1 read-write PLLEN PLLEN 26 1 read-write PLLFRACCTL PLLFRACCTL 29 1 read-write PLLFRACIN PLLFRACIN 10 16 read-write PLLNDIV PLLNDIV 0 7 read-write PLLODF PLLODF 7 3 read-write PLLSTRB PLLSTRB 27 1 read-write PLLSTRBYP PLLSTRBYP 28 1 read-write TUNE1 USBPHYC_TUNE1 This register is used to control the tune interface of the HS PHY, port #x. 0x10C 32 read-write n 0x0 0x0 FSDRVRFADJ FSDRVRFADJ 7 1 read-write HDRXGNEQEN HDRXGNEQEN 22 1 read-write HSDRVCHKITRM HSDRVCHKITRM 9 4 read-write HSDRVCHKZTRM HSDRVCHKZTRM 13 2 read-write HSDRVCURINCR HSDRVCURINCR 6 1 read-write HSDRVDCCUR HSDRVDCCUR 4 1 read-write HSDRVDCLEV HSDRVDCLEV 5 1 read-write HSDRVRFRED HSDRVRFRED 8 1 read-write HSDRVSLEW HSDRVSLEW 3 1 read-write HSFALLPREEM HSFALLPREEM 25 1 read-write HSRXOFF HSRXOFF 23 2 read-write INCURREN INCURREN 0 1 read-write INCURRINT INCURRINT 1 1 read-write LFSCAPEN LFSCAPEN 2 1 read-write OTPCOMP OTPCOMP 15 5 read-write SHTCCTCTLPROT SHTCCTCTLPROT 26 1 read-write SQLCHCTL SQLCHCTL 20 2 read-write STAGSEL STAGSEL 27 1 read-write TUNE2 USBPHYC_TUNE2 This register is used to control the tune interface of the HS PHY, port #x. 0x20C 32 read-write n 0x0 0x0 FSDRVRFADJ FSDRVRFADJ 7 1 read-write HDRXGNEQEN HDRXGNEQEN 22 1 read-write HSDRVCHKITRM HSDRVCHKITRM 9 4 read-write HSDRVCHKZTRM HSDRVCHKZTRM 13 2 read-write HSDRVCURINCR HSDRVCURINCR 6 1 read-write HSDRVDCCUR HSDRVDCCUR 4 1 read-write HSDRVDCLEV HSDRVDCLEV 5 1 read-write HSDRVRFRED HSDRVRFRED 8 1 read-write HSDRVSLEW HSDRVSLEW 3 1 read-write HSFALLPREEM HSFALLPREEM 25 1 read-write HSRXOFF HSRXOFF 23 2 read-write INCURREN INCURREN 0 1 read-write INCURRINT INCURRINT 1 1 read-write LFSCAPEN LFSCAPEN 2 1 read-write OTPCOMP OTPCOMP 15 5 read-write SHTCCTCTLPROT SHTCCTCTLPROT 26 1 read-write SQLCHCTL SQLCHCTL 20 2 read-write STAGSEL STAGSEL 27 1 read-write VERR USBPHYC_VERR This register defines the version of this IP. 0xFFC 32 read-only n 0x0 0x0 MAJREV MAJREV 4 4 read-only MINREV MINREV 0 4 read-only VREFBUF VREFBUF VREFBUF 0x0 0x0 0x400 registers n CCR VREFBUF_CCR VREFBUF calibration control register 0x4 32 read-write n 0x0 0x0 TRIM TRIM 0 6 read-write CSR VREFBUF_CSR VREFBUF control and status register 0x0 32 read-write n 0x0 0x0 ENVR ENVR 0 1 read-write HIZ HIZ 1 1 read-write VRR VRR 3 1 read-only VRS VRS 4 3 read-write WWDG1 WWDG1 WWDG 0x0 0x0 0x400 registers n WWDG_CFR WWDG_CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI EWI 9 1 read-write W W 0 7 read-write WDGTB WDGTB 11 3 read-write WWDG_CR WWDG_CR Control register 0x0 32 read-write n 0x0 0x0 T T 0 7 read-write WDGA WDGA 7 1 read-write WWDG_SR WWDG_SR Status register 0x8 32 read-write n 0x0 0x0 EWIF EWIF 0 1 read-write WWDG2 WWDG1 WWDG 0x0 0x0 0x400 registers n WWDG_CFR WWDG_CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI EWI 9 1 read-write W W 0 7 read-write WDGTB WDGTB 11 3 read-write WWDG_CR WWDG_CR Control register 0x0 32 read-write n 0x0 0x0 T T 0 7 read-write WDGA WDGA 7 1 read-write WWDG_SR WWDG_SR Status register 0x8 32 read-write n 0x0 0x0 EWIF EWIF 0 1 read-write