STMicroelectronics STM32W108 2024.05.01 STM32W108 false 8 32 ADC Analog to Digital Converter ADC 0x0 0x0 0x2815 registers n ADC_IRQ ADC Interrupt 11 ADC ADC Interrupt 11 CR ADC_CR ADC control register 0x27F4 32 read-write n 0x0 0x0 ADON ADON 0 1 CHSELN CHSELN 3 4 CHSELP CHSELP 7 4 CLK CLK 2 1 HVSELN HVSELN 11 1 HVSELP HVSELP 12 1 SMP SMP 13 3 DMACNDTR ADC_DMACNDTR ADC DMA count number of data transferred register 0x2814 32 read-only n 0x0 0x0 CNDT CNDT 0 13 DMACR ADC_DMACR ADC DMA control register 0x2800 32 read-write n 0x0 0x0 AUTOWRAP Selects DMA mode 1 1 read-write LOAD Loads the DMA buffer 0 1 read-write RST Write 1 to reset the ADC DMA 4 1 write-only DMAMNAR ADC_DMAMNAR ADC DMA memory next address register 0x2810 32 read-only n 0x0 0x0 MNA MNA 1 13 DMAMSAR ADC_DMAMSAR ADC DMA memory start address register 0x2808 32 read-write n 0x0 0x0 MSA MSA 0 13 DMANDTR ADC_DMANDTR ADC DMA number of data to transfer register 0x280C 32 read-write n 0x0 0x0 NDT NDT 0 13 DMASR ADC_DMASR ADC DMA status register 0x2804 32 read-only n 0x0 0x0 ACT ACT 0 1 AOVF AOVF 1 1 GAINR ADC_GAINR ADC gain register 0x27FC 32 read-write n 0x0 0x0 GAIN GAIN 0 16 IER ADC_IER ADC interrupt enable register 0x40 32 read-write n 0x0 0x0 DMABFIE DMABFIE 2 1 DMABHFIE DMABHFIE 1 1 DMAOVFIE DMAOVFIE 4 1 SATIE SATIE 3 1 ISR ADC_ISR ADC interrupt status register 0x0 32 read-write n 0x0 0x0 DMABF DMABF 2 1 DMABHF DMABHF 1 1 DMAOVF DMAOVF 4 1 SAT SAT 3 1 OFFSETR ADC_OFFSETR ADC offset register 0x27F8 32 read-write n 0x0 0x0 OFFSET OFFSET 0 16 CLK Clock CLK 0x0 0x0 0x4025 registers n CPUCR CLK_CPUCR Clock source select register 0x4018 32 read-write n 0x0 0x0 SW2 12MHz/24MHz is selected 0 1 DITHERCR CLK_DITHERCR Clock dither control register 0x4010 32 read-write n 0x0 0x0 DIS Dither disable 0 1 HSECR1 CLK_HSECR1 HSE Clock (24MHz) control register 1 0x3FFC 32 read-write n 0x0 0x0 BIASTRIM Bias trim setting for 24MHz oscillator 0 4 HSECR2 CLK_HSECR2 HSE Clock (24MHz) control register 2 0x4014 32 read-write n 0x0 0x0 EN MHz crystal oscillator is main clock 1 1 SW1 OSCHF/XTAL is selected 0 1 HSICR CLK_HSICR HSI Clock (12MHz) trim register 0x4000 32 read-write n 0x0 0x0 TUNE Frequency trim setting for HF RC oscillator 0 5 LSI10KCR CLK_LSI10KCR LSI Clock (10KHz) control register 0x4 32 read-write n 0x0 0x0 TUNE Tune value for clkrc 0 4 LSI1KCR CLK_LSI1KCR LSI Clock (1KHz) control register 0x8 32 read-write n 0x0 0x0 CALINT Divider value integer portion 11 15 CLKFRAC Divider value fractional portion 0 11 PERIODCR CLK_PERIODCR Clock period control register 0x4008 32 read-write n 0x0 0x0 MODE Sets clock to be measured by CLK_PERIOD 0 2 PERIODSR CLK_PERIODSR Clock period status register 0x400C 32 read-only n 0x0 0x0 PERIOD Clock period measurement 0 16 SLEEPCR CLK_SLEEPCR Sleep timer control register 0x0 32 read-write n 0x0 0x0 LSEEN Enables 32kHz external XTAL 0 1 LSI10KEN Enables 10kHz internal RC during deep 1 1 EXTI External interrupt/event controller EXTI 0x0 0x0 0x1405 registers n EXTIA_IRQ EXTI port A interrupt 12 EXTIA EXTI port A interrupt 12 EXTIB_IRQ EXTI port B interrupt 13 EXTIB EXTI port B interrupt 13 EXTIC_IRQ EXTI port C interrupt 14 EXTIC EXTI port C interrupt 14 EXTID_IRQ EXTI port D interrupt 15 EXTID EXTI port D interrupt 15 EXTIA_TSR EXTIA_TSR EXTIA trigger source register 0x4C 32 read-write n 0x0 0x0 FILTEN FILTEN 8 1 INTMOD INTMOD 5 3 EXTIB_TSR EXTIB_TSR EXTIB trigger source register 0x50 32 read-write n 0x0 0x0 FILTEN FILTEN 8 1 INTMOD INTMOD 5 3 EXTIC_CR EXTIC_CR EXTIC configuration register 0x1400 32 read-write n 0x0 0x0 GPIO_SEL GPIO_SEL 0 5 EXTIC_TSR EXTIC_TSR EXTIC trigger source register 0x54 32 read-write n 0x0 0x0 FILTEN FILTEN 8 1 INTMOD INTMOD 5 3 EXTID_CR EXTID_CR EXTID configuration register 0x1404 32 read-write n 0x0 0x0 GPIO_SEL GPIO_SEL 0 5 EXTID_TSR EXTID_TSR EXTID trigger source register 0x58 32 read-write n 0x0 0x0 FILTEN FILTEN 8 1 INTMOD INTMOD 5 3 PR EXTI_PR EXTI pending register 0x0 32 read-write n 0x0 0x0 FLASH FLASH FLASH 0x0 0x0 0x43D4 registers n ACR FLASH_ACR FLASH access control register 0x3FD4 32 read-write n 0x0 0x0 HLFCYA HLFCYA 3 1 read-write LATENCY LATENCY 0 3 read-write PRFTBE PRFTBE 4 1 read-write PRFTBS Prefetch Status 5 1 read-only AR FLASH_AR FLASH address register 0x3FE8 32 read-write n 0x0 0x0 FAR FAR 0 32 CLKER FLASH_CLKER FLASH controller clock enable register 0x0 32 read-write n 0x0 0x0 EN EN 0 1 CLKSR FLASH_CLKSR FLASH controller clock status register 0x4 32 read-write n 0x0 0x0 ACK ACK 0 1 BSY BSY 1 1 CR FLASH_CR FLASH control register 0x3FE4 32 read-write n 0x0 0x0 EOPIE EOPIE 12 1 ERRIE ERRIE 10 1 LOCK LOCK 7 1 MER MER 2 1 OPTER OPTER 5 1 OPTPG OPTPG 4 1 OPTWRE OPTWRE 9 1 PER PER 1 1 PG PG 0 1 STRT STRT 6 1 KEYR FLASH_KEYR FLASH key register 0x3FD8 32 write-only n 0x0 0x0 FKEYR FKEYR 0 32 OBR FLASH_OBR FLASH option bytes register 0x3FF0 32 read-only n 0x0 0x0 OPTERR OPTERR 0 1 RDPRT RDPRT 1 1 OPTKEYR FLASH_OPTKEYR FLASH OPT key register 0x3FDC 32 write-only n 0x0 0x0 OPTKEYR OPTKEYR 0 32 SR FLASH_SR FLASH status register 0x3FE0 32 read-write n 0x0 0x0 BSY BSY 0 1 write-only EOP EOP 5 1 read-write PGERR PGERR 2 1 read-write WRPRTERR WRPRTERR 4 1 read-write WRPR FLASH_WRPR FLASH write protection register 0x3FF4 32 read-only n 0x0 0x0 WRP WRP 0 32 GPIOA General purpose I/Os GPIO 0x0 0x0 0x400 registers n BRR GPIOA_BRR Port A output clear register 0x14 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BSR GPIOA_BSR Port A bit set register 0x10 32 read-write n 0x0 0x0 BS0 BS0 0 1 BS1 BS1 1 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 CRH GPIOA_CRH Port A configuration register (High) 0x4 32 read-write n 0x0 0x0 CNFMODE4 CNFMODE4 0 4 CNFMODE5 CNFMODE5 4 4 CNFMODE6 CNFMODE6 8 4 CNFMODE7 CNFMODE7 12 4 CRL GPIOA_CRL Port A configuration register (Low) 0x0 32 read-write n 0x0 0x0 CNFMODE0 CNFMODE0 0 4 CNFMODE1 CNFMODE1 4 4 CNFMODE2 CNFMODE2 8 4 CNFMODE3 CNFMODE3 12 4 IDR GPIOA_IDR Port A input data register 0x8 32 read-write n 0x0 0x0 IDR0 IDR0 0 1 IDR1 IDR1 1 1 IDR2 IDR2 2 1 IDR3 IDR3 3 1 IDR4 IDR4 4 1 IDR5 IDR5 5 1 IDR6 IDR6 6 1 IDR7 IDR7 7 1 ODR GPIOA_ODR Port A output data register 0xC 32 read-write n 0x0 0x0 ODR0 ODR0 0 1 ODR1 ODR1 1 1 ODR2 ODR2 2 1 ODR3 ODR3 3 1 ODR4 ODR4 4 1 ODR5 ODR5 5 1 ODR6 ODR6 6 1 ODR7 ODR7 7 1 GPIOB General purpose I/Os GPIO 0x0 0x0 0x400 registers n BRR GPIOB_BRR Port B output clear register 0x14 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BSR GPIOB_BSR Port B bit set register 0x10 32 read-write n 0x0 0x0 BS0 BS0 0 1 BS1 BS1 1 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 CRH GPIOB_CRH Port B configuration register (High) 0x4 32 read-write n 0x0 0x0 CNFMODE4 CNFMODE4 0 4 CNFMODE5 CNFMODE5 4 4 CNFMODE6 CNFMODE6 8 4 CNFMODE7 CNFMODE7 12 4 CRL GPIOB_CRL Port B configuration register (Low) 0x0 32 read-write n 0x0 0x0 CNFMODE0 CNFMODE0 0 4 CNFMODE1 CNFMODE1 4 4 CNFMODE2 CNFMODE2 8 4 CNFMODE3 CNFMODE3 12 4 IDR GPIOB_IDR Port B input data register 0x8 32 read-write n 0x0 0x0 ID0 ID0 0 1 ID1 ID1 1 1 ID2 ID2 2 1 ID3 ID3 3 1 ID4 ID4 4 1 ID5 ID5 5 1 ID6 ID6 6 1 ID7 ID7 7 1 ODR GPIOB_ODR Port B output data register 0xC 32 read-write n 0x0 0x0 OD0 OD0 0 1 OD1 OD1 1 1 OD2 OD2 2 1 OD3 OD3 3 1 OD4 OD4 4 1 OD5 OD5 5 1 OD6 OD6 6 1 OD7 OD7 7 1 GPIOC General purpose I/Os GPIO 0x0 0x0 0x400 registers n BRR GPIOC_BRR Port C output clear register 0x14 32 write-only n 0x0 0x0 BR0 BR0 0 1 BR1 BR1 1 1 BR2 BR2 2 1 BR3 BR3 3 1 BR4 BR4 4 1 BR5 BR5 5 1 BR6 BR6 6 1 BR7 BR7 7 1 BSR GPIOC_BSR Port B bit set register 0x10 32 read-write n 0x0 0x0 BS0 BS0 0 1 BS1 BS1 1 1 BS2 BS2 2 1 BS3 BS3 3 1 BS4 BS4 4 1 BS5 BS5 5 1 BS6 BS6 6 1 BS7 BS7 7 1 CRH GPIOC_CRH Port C configuration register (High) 0x4 32 read-write n 0x0 0x0 CNFMODE4 CNFMODE4 0 4 CNFMODE5 CNFMODE5 4 4 CNFMODE6 CNFMODE6 8 4 CNFMODE7 CNFMODE7 12 4 CRL GPIOC_CRL Port C configuration register (Low) 0x0 32 read-write n 0x0 0x0 CNFMODE0 CNFMODE0 0 4 CNFMODE1 CNFMODE1 4 4 CNFMODE2 CNFMODE2 8 4 CNFMODE3 CNFMODE3 12 4 IDR GPIOC_IDR Port C input data register 0x8 32 read-write n 0x0 0x0 ID0 ID0 0 1 ID1 ID1 1 1 ID2 ID2 2 1 ID3 ID3 3 1 ID4 ID4 4 1 ID5 ID5 5 1 ID6 ID6 6 1 ID7 ID7 7 1 ODR GPIOC_ODR Port C output data register 0xC 32 read-write n 0x0 0x0 OD0 OD0 0 1 OD1 OD1 1 1 OD2 OD2 2 1 OD3 OD3 3 1 OD4 OD4 4 1 OD5 OD5 5 1 OD6 OD6 6 1 OD7 OD7 7 1 GPIO_DBG General purpose I/Os GPIO 0x0 0x0 0x7BDD registers n GPIO_DBGCR GPIO_DBGCR GPIO debug configuration register 0x7BD8 32 read-write n 0x0 0x0 DBGDIS DBGDIS 5 1 EXTREGEN EXTREGEN 4 1 GPIO_DBGSR GPIO_DBGSR GPIO debug status register 0x7BDC 32 read-only n 0x0 0x0 BOOTMODE BOOTMODE 3 1 FORCEDBG FORCEDBG 1 1 SWEN SWEN 0 1 GPIO_PCTRACECR GPIO_PCTRACECR Clock PC trace register 0x0 32 read-write n 0x0 0x0 SEL selects PC_TRACE source on bb_debug GPIO pins 0 1 MAC_TIM MAC timer TIM 0x0 0x0 0x55 registers n 0x0 0x55 registers n MAC_TIM_IRQ MAC Timer Interrupt 8 MAC_TIM MAC Timer Interrupt 8 MACTMR_CNTR MACTMR_CNTR MACTMR counter register 0x0 32 read-write n 0x0 0x0 CNT MAC timer count 0 20 MACTMR_CR MACTMR_CR MACTMR configuration register 0x54 32 read-write n 0x0 0x0 EN MAC timer enable 0 1 RST MAC timer reset 1 1 MEM Memory Control registers RAM 0x0 0x0 0x29 registers n 0x0 0x29 registers n DMAPROTR1 DMAPROTR1 DMA protection register1 0x20 32 read-only n 0x0 0x0 ADDRESS DMA protection fault, faulting address 0 14 OFFSET offset in RAM 14 18 DMAPROTR2 DMAPROTR2 DMA protection register2 0x24 32 read-only n 0x0 0x0 CHANNEL DMA protection fault, faulting channel 0 3 RAMCR RAMCR Memory configuration register 0x28 32 read-write n 0x0 0x0 WEN Makes all RAM write access 2 1 RAMPROTR1 RAMPROTR1 Memory protection register1 0x0 32 read-write n 0x0 0x0 RAMPROT1 RAMPROT1 0 32 RAMPROTR2 RAMPROTR2 Memory protection register2 0x4 32 read-write n 0x0 0x0 RAMPROT2 RAMPROT2 0 32 RAMPROTR3 RAMPROTR3 Memory protection register3 0x8 32 read-write n 0x0 0x0 RAMPROT3 RAMPROT1 0 32 RAMPROTR4 RAMPROTR4 Memory protection register4 0xC 32 read-write n 0x0 0x0 RAMPROT4 RAMPROT4 0 32 RAMPROTR5 RAMPROTR5 Memory protection register5 0x10 32 read-write n 0x0 0x0 RAMPROT5 RAMPROT5 0 32 RAMPROTR6 RAMPROTR6 Memory protection register6 0x14 32 read-write n 0x0 0x0 RAMPROT6 RAMPROT6 0 32 RAMPROTR7 RAMPROTR7 Memory protection register7 0x18 32 read-write n 0x0 0x0 RAMPROT7 RAMPROT7 0 32 RAMPROTR8 RAMPROTR8 Memory protection register8 0x1C 32 read-write n 0x0 0x0 RAMPROT8 RAMPROT8 0 32 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x1001 registers n IABR0 IABR0 Interrupt Active Bit Register 0x300 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x180 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x280 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICTR ICTR Interrupt Controller Type Register 0x4 32 read-only n 0x0 0x0 INTLINESNUM Total number of interrupt lines in groups 0 4 IPR0 IPR0 Interrupt Priority Register 0x400 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x404 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x408 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x40C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x410 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER0 ISER0 Interrupt Set-Enable Register 0x100 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x200 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 STIR STIR Software Triggered Interrupt Register 0xF00 32 write-only n 0x0 0x0 INTID interrupt to be triggered 0 9 PWR Power control PWR 0x0 0x0 0xBC19 registers n CPWRUPREQSR PWR_CPWRUPREQSR PWR_CPWRUPREQSR 0x30 32 read-only n 0x0 0x0 REQ REQ 0 1 CSYSPWRUPACKCR PWR_CSYSPWRUPACKCR PWR_CSYSPWRUPACKCR 0x3C 32 read-only n 0x0 0x0 INHIBIT INHIBIT 0 1 CSYSPWRUPACKSR PWR_CSYSPWRUPACKSR PWR_CSYSPWRUPACKSR 0x38 32 read-only n 0x0 0x0 ACK ACK 0 1 CSYSPWRUPREQSR PWR_CSYSPWRUPREQSR PWR_CSYSPWRUPREQSR 0x34 32 read-only n 0x0 0x0 REQ REQ 0 1 DSLEEPCR1 PWR_DSLEEPCR1 PWR_DSLEEPCR1 0x0 32 read-write n 0x0 0x0 PWR_CSYSPWRUPACKCR PWR_CSYSPWRUPACKCR 1 1 DSLEEPCR2 PWR_DSLEEPCR2 PWR_DSLEEPCR2 0x10 32 read-write n 0x0 0x0 MODE MODE 0 1 VREGCR PWR_VREGCR Voltage regulator Control register 0x14 32 read-write n 0x0 0x0 PWR_VREGCR_1V2EN 1V2 direct controle of regulator on/off 4 1 PWR_VREGCR_1V2TRIM 1V2 regulator trim value 0 3 PWR_VREGCR_1V8EN 1V8 direct controle of regulator on/off 11 1 PWR_VREGCR_1V8TRIM 1V8 regulator trim value 7 3 PWR_VREGCR_VREFEN VREF on/off 15 1 WAKECR1 PWR_WAKECR1 PWR_WAKECR1 0x1C 32 read-write n 0x0 0x0 COMPA COMPA 4 1 COMPB COMPB 5 1 CORE CORE 7 1 CPWRRUPREQ CPWRRUPREQ 8 1 CSYSPWRUPREQ CSYSPWRUPREQ 9 1 IRQD IRQD 3 1 SC1 SC1 1 1 SC2 SC2 2 1 WAKEEN WAKEEN 0 1 WRAP WRAP 6 1 WAKECR2 PWR_WAKECR2 PWR_WAKECR2 0x20 32 write-only n 0x0 0x0 COREWAKE COREWAKE 5 1 WAKEFILTR PWR_WAKEFILTR Wake filter register 0xBC18 32 read-write n 0x0 0x0 GPIO Enable filter on GPIO wakeup sources enabled by the PWR_WAKEPxR registers 0 1 IRQD Enable filter on GPIO wakeup source EXTI D 3 1 SC1 Enable filter on GPIO wakeup source SC1 (PB2) 1 1 SC2 Enable filter on GPIO wakeup source SC2 (PA2) 2 1 WAKEPAR PWR_WAKEPAR Wake GPIO Port A register 0xBC04 32 read-write n 0x0 0x0 PA0 PA0 0 1 PA1 PA1 1 1 PA2 PA2 2 1 PA3 PA3 3 1 PA4 PA4 4 1 PA5 PA5 5 1 PA6 PA6 6 1 PA7 PA7 7 1 WAKEPBR PWR_WAKEPBR Wake GPIO Port B register 0xBC08 32 read-write n 0x0 0x0 PB0 PB0 0 1 PB1 PB1 1 1 PB2 PB2 2 1 PB3 PB3 3 1 PB4 PB4 4 1 PB5 PB5 5 1 PB6 PB6 6 1 PB7 PB7 7 1 WAKEPCR PWR_WAKEPCR Wake GPIO Port C register 0xBC0C 32 read-write n 0x0 0x0 PC0 PC0 0 1 PC1 PC1 1 1 PC2 PC2 2 1 PC3 PC3 3 1 PC4 PC4 4 1 PC5 PC5 5 1 PC6 PC6 6 1 PC7 PC7 7 1 WAKESR PWR_WAKESR PWR_WAKESR 0x24 32 read-write n 0x0 0x0 ARQD ARQD 3 1 COMPA COMPA 4 1 COMPB COMPB 5 1 CORE CORE 7 1 CPWRRUPREQ CPWRRUPREQ 8 1 CSYSPWRUPREQ CSYSPWRUPREQ 9 1 GPIOPIN GPIOPIN 0 1 IRQD IRQD 3 1 SC1 SC1 1 1 SC2 SC2 2 1 WRAP WRAP 6 1 RST Reset event RST 0x0 0x0 0x1 registers n SR RST_SR Reset Status Register 0x0 32 read-only n 0x0 0x0 LKUP LKUP 7 1 OBFAIL OBFAIL 6 1 PIN PIN 2 1 PWRHV PWRHV 0 1 PWRLV PWRLV 1 1 SWRST SWRST 4 1 WDG WDG 3 1 WKUP WKUP 5 1 SC1 Serial controller 1 SerialControll 0x0 0x0 0x205D registers n SC1_IRQ Serial Controller 1 Interrupt 5 SC1 Serial Controller 1 Interrupt 5 CR SC1_CR Serial controller control register 0x204C 32 read-write n 0x0 0x0 MODE MODE 0 2 CRR1 SC1_CRR1 Serial controller clock rate register 0x2058 32 read-write n 0x0 0x0 LIN LIN 0 4 CRR2 SC1_CRR2 Serial controller clock rate register 2 0x205C 32 read-write n 0x0 0x0 EXP EXP 0 4 DR SC1_DR Serial control Data register 0x2034 32 read-write n 0x0 0x0 DR DR 0 8 ICR SC1_ICR Serial controller interrupt control register 0x4C 32 read-write n 0x0 0x0 IDLELEVEL IDLELEVEL 2 1 RXNELEVEL RXNELEVEL 0 1 TXELEVEL TXELEVEL 1 1 IER SC1_IER Serial controller interrupt enable register 0x40 32 read-write n 0x0 0x0 BRFIE BRFIE 5 1 BTFIE BTFIE 6 1 CMDFINIE CMDFINIE 7 1 FEIE FEIE 13 1 IDLEIE IDLEIE 2 1 NACKIE NACKIE 8 1 OVRIE OVRIE 3 1 PEIE PEIE 14 1 RXNEIE RXNEIE 0 1 RXULODAIE RXULODAIE 9 1 RXULODBIE RXULODBIE 10 1 TXEIE TXEIE 1 1 TXULODAIE TXULODAIE 11 1 TXULODBIE TXULODBIE 12 1 UDRIE UDRIE 4 1 ISR SC1_ISR Serial controller interrupt status register 0x0 32 read-write n 0x0 0x0 BRF BRF 5 1 BTF BTF 6 1 CMDFIN CMDFIN 7 1 FE FE 13 1 IDLE IDLE 2 1 NACK NACK 8 1 OVR OVR 3 1 PE PE 14 1 RXNE RXNE 0 1 RXULODA RXULODA 9 1 RXULODB RXULODB 10 1 TXE TXE 1 1 TXULODA TXULODA 11 1 TXULODB TXULODB 12 1 UDR UDR 4 1 SC1_DMA Serial controller 1 (Direct memory access) SerialControll 0x0 0x0 0x71 registers n SC1_DMACR SC1_DMACR Serial controller DMA control register 0x30 32 read-write n 0x0 0x0 RXLODA RXLODA 0 1 read-write RXLODB RXLODB 1 1 read-write RXRST RXRST 4 1 write-only TXLODA TXLODA 2 1 read-write TXLODB TXLODB 3 1 read-write TXRST TXRST 5 1 write-only SC1_DMARXBEGADDAR SC1_DMARXBEGADDAR Serial controller receive DMA begin address channel A register 0x0 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMARXBEGADDBR SC1_DMARXBEGADDBR Serial controller receive DMA begin address channel B register 0x8 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMARXCNTAR SC1_DMARXCNTAR Serial controller receive DMA counter channel A register 0x20 32 read-write n 0x0 0x0 CNT CNT 0 13 SC1_DMARXCNTBR SC1_DMARXCNTBR Serial controller receive DMA count channel B register 0x24 32 read-write n 0x0 0x0 CNT CNT 0 13 SC1_DMARXCNTSAVEDR SC1_DMARXCNTSAVEDR Serial controller receive DMA saved counter channel B register 0x70 32 read-only n 0x0 0x0 CNT CNT 0 13 SC1_DMARXENDADDAR SC1_DMARXENDADDAR Serial controller receive DMA end address channel A register 0x4 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMARXENDADDBR SC1_DMARXENDADDBR Serial controller receive DMA end address channel B register 0xC 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMARXERRAR SC1_DMARXERRAR Serial controller receive DMA channel A first error register 0x34 32 read-only n 0x0 0x0 ADD ADD 0 13 SC1_DMARXERRBR SC1_DMARXERRBR Serial controller receive DMA channel B first error register 0x38 32 read-only n 0x0 0x0 ADD ADD 0 13 SC1_DMASR SC1_DMASR Serial controller DMA status register 0x2C 32 read-only n 0x0 0x0 FEA FEA 8 1 FEB FEB 9 1 NSSS NSSS 10 3 OVRA OVRA 4 1 OVRB OVRB 5 1 PEA PEA 6 1 PEB PEB 7 1 RXAACK RXAACK 0 1 RXBACK RXBACK 1 1 TXAACK TXAACK 2 1 TXBACK TXBACK 3 1 SC1_DMATXBEGADDAR SC1_DMATXBEGADDAR Serial controller transmit DMA begin address channel A register 0x10 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMATXBEGADDBR SC1_DMATXBEGADDBR Serial controller transmit DMA begin address channel B register 0x18 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMATXCNTR SC1_DMATXCNTR Serial controller transmit DMA counter register 0x28 32 read-only n 0x0 0x0 CNT CNT 0 13 SC1_DMATXENDADDAR SC1_DMATXENDADDAR Serial controller transmit DMA end address channel A register 0x14 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_DMATXENDADDBR SC1_DMATXENDADDBR Serial controller transmit DMA end address channel B 0x1C 32 read-write n 0x0 0x0 ADD ADD 0 13 SC1_I2C Serial controller 1 (Serial peripheral interface) SerialControll 0x0 0x0 0xD registers n SC1_I2CCR1 SC1_I2CCR1 Serial controller I2C control register 1 0x8 32 read-write n 0x0 0x0 BRE BRE 0 1 BTE BTE 1 1 START START 2 1 STOP STOP 3 1 SC1_I2CCR2 SC1_I2CCR2 Serial controller I2C control register 2 0xC 32 read-write n 0x0 0x0 ACK ACK 0 1 SC1_I2CSR SC1_I2CSR Serial controller I2C status register 0x0 32 read-only n 0x0 0x0 BRF BRF 2 1 BTF BTF 1 1 CMDFIN CMDFIN 3 1 NACK NACK 0 1 SC1_SPI Serial controller 1 (Serial peripheral interface) SerialControll 0x0 0x0 0x19 registers n 0x0 0x19 registers n SC1_SPICR SC1_SPICR Serial controller SPI control register 0x18 32 read-write n 0x0 0x0 CPHA CPHA 1 1 CPOL CPOL 0 1 LSBFIRST LSBFIRST 2 1 MSTR MSTR 4 1 RPTEN RPTEN 3 1 RXMODE RXMODE 5 1 SC1_SPISR SC1_SPISR Serial controller SPI status register 0x0 32 read-only n 0x0 0x0 IDLE IDLE 3 1 OVF OVF 0 1 RXNE RXNE 1 1 TXE TXE 2 1 SC1_UART Serial controller 1 (Universal Asynchronous Receiver/Transmitter) SerialControll 0x0 0x0 0x25 registers n SC1_UARTBRR1 SC1_UARTBRR1 Serial controller UART baud rate register 1 0x20 32 read-write n 0x0 0x0 N N 0 16 SC1_UARTBRR2 SC1_UARTBRR2 Serial controller UART baud rate register 2 0x24 32 read-write n 0x0 0x0 F F 0 1 SC1_UARTCR SC1_UARTCR Serial controller UART control register 0x14 32 read-write n 0x0 0x0 AHFCE AHFCE 6 1 HFCE HFCE 5 1 M M 1 1 nRTS nRTS 0 1 PCE PCE 3 1 PS PS 4 1 STOP STOP 2 1 SC1_UARTSR SC1_UARTSR Serial controller UART status register 0x0 32 read-only n 0x0 0x0 CTS CTS 0 1 FE FE 4 1 IDLE IDLE 6 1 OVR OVR 3 1 PE PE 5 1 RXNE RXNE 1 1 TXE TXE 2 1 SC2 Serial controller 2 SerialControll 0x0 0x0 0x1859 registers n SC2_IRQ Serial Controller 2 Interrupt 6 SC2 Serial Controller 2 Interrupt 6 CR SC2_CR Serial controller control register 0x1848 32 read-write n 0x0 0x0 MODE MODE 0 2 CRR1 SC2_CRR1 Serial controller clock rate register 1 0x1854 32 read-write n 0x0 0x0 LIN LIN 0 4 CRR2 SC2_CRR2 Serial controller clock rate register 2 0x1858 32 read-write n 0x0 0x0 EXP EXP 0 4 DR SC2_DR Serial controller data register 0x1830 32 read-write n 0x0 0x0 DR DR 0 8 ICR SC2_ICR Serial controller interrupt control register 0x4C 32 read-write n 0x0 0x0 IDLELEVEL IDLELEVEL 2 1 RXNELEVEL RXNELEVEL 0 1 TXELEVEL TXELEVEL 1 1 IER SC2_IER Serial controller interrupt enable register 0x40 32 read-write n 0x0 0x0 BRFIE BRFIE 5 1 BTFIE BTFIE 6 1 CMDFINIE CMDFINIE 7 1 FEIE FEIE 13 1 IDLEIE IDLEIE 2 1 NACKIE NACKIE 8 1 OVRIE OVRIE 3 1 PEIE PEIE 14 1 RXNEIE RXNEIE 0 1 RXULODAIE RXULODAIE 9 1 RXULODBIE RXULODBIE 10 1 TXEIE TXEIE 1 1 TXULODAIE TXULODAIE 11 1 TXULODBIE TXULODBIE 12 1 UDRIE UDRIE 4 1 ISR SC2_ISR Serial controller interrupt status register 0x0 32 read-write n 0x0 0x0 BRF BRF 5 1 BTF BTF 6 1 CMDFIN CMDFIN 7 1 FE FE 13 1 IDLE IDLE 2 1 NACK NACK 8 1 OVR OVR 3 1 PE PE 14 1 RXNE RXNE 0 1 RXULODA RXULODA 9 1 RXULODB RXULODB 10 1 TXE TXE 1 1 TXULODA TXULODA 11 1 TXULODB TXULODB 12 1 UDR UDR 4 1 SC2_DMA Serial controller 2 (Direct memory access) SerialControll 0x0 0x0 0x71 registers n SC2_DMACR SC2_DMACR Serial controller DMA control register 0x30 32 read-write n 0x0 0x0 RXLODA RXLODA 0 1 read-write RXLODB RXLODB 1 1 read-write RXRST RXRST 4 1 write-only TXLODA TXLODA 2 1 read-write TXLODB TXLODB 3 1 read-write TXRST TXRST 5 1 write-only SC2_DMARXBEGADDAR SC2_DMARXBEGADDAR Serial controller receive DMA begin address channel A register 0x0 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMARXBEGADDBR SC2_DMARXBEGADDBR Serial controller receive DMA begin address channel B register 0x8 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMARXCNTAR SC2_DMARXCNTAR Serial controller receive DMA counter channel A register 0x20 32 read-write n 0x0 0x0 CNT CNT 0 13 SC2_DMARXCNTBR SC2_DMARXCNTBR Serial controller receive DMA count channel B register 0x24 32 read-write n 0x0 0x0 CNT CNT 0 13 SC2_DMARXCNTSAVEDR SC2_DMARXCNTSAVEDR Serial controller receive DMA saved counter channel B register 0x70 32 read-only n 0x0 0x0 CNT CNT 0 13 SC2_DMARXENDADDAR SC2_DMARXENDADDAR Serial controller receive DMA end address channel A register 0x4 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMARXENDADDBR SC2_DMARXENDADDBR Serial controller receive DMA end address channel B register 0xC 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMARXERRAR SC2_DMARXERRAR Serial controller receive DMA channel A first error register 0x34 32 read-only n 0x0 0x0 ADD ADD 0 13 SC2_DMARXERRBR SC2_DMARXERRBR Serial controller receive DMA channel B first error register 0x38 32 read-only n 0x0 0x0 ADD ADD 0 13 SC2_DMASR SC2_DMASR Serial controller DMA status register 0x2C 32 read-only n 0x0 0x0 FEA FEA 8 1 FEB FEB 9 1 NSSS NSSS 10 3 OVRA OVRA 4 1 OVRB OVRB 5 1 PEA PEA 6 1 PEB PEB 7 1 RXAACK RXAACK 0 1 RXBACK RXBACK 1 1 TXAACK TXAACK 2 1 TXBACK TXBACK 3 1 SC2_DMATXBEGADDAR SC2_DMATXBEGADDAR Serial controller transmit DMA begin address channel A register 0x10 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMATXBEGADDBR SC2_DMATXBEGADDBR Serial controller transmit DMA begin address channel B register 0x18 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMATXCNTR SC2_DMATXCNTR Serial controller transmit DMA counter register 0x28 32 read-only n 0x0 0x0 CNT CNT 0 13 SC2_DMATXENDADDAR SC2_DMATXENDADDAR Serial controller transmit DMA end address channel A register 0x14 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_DMATXENDADDBR SC2_DMATXENDADDBR Serial controller transmit DMA end address channel B register 0x1C 32 read-write n 0x0 0x0 ADD ADD 0 13 SC2_I2C Serial controller 2 (Serial peripheral interface) SerialControll 0x0 0x0 0xD registers n SC2_I2CCR1 SC2_I2CCR1 Serial controller I2C control register 1 0x8 32 read-write n 0x0 0x0 BRE BRE 0 1 BTE BTE 1 1 START START 2 1 STOP STOP 3 1 SC2_I2CCR2 SC2_I2CCR2 Serial controller I2C control register 2 0xC 32 read-write n 0x0 0x0 ACK ACK 0 1 SC2_I2CSR SC2_I2CSR Serial controller I2C status register 0x0 32 read-only n 0x0 0x0 BRF BRF 2 1 BTF BTF 1 1 CMDFIN CMDFIN 3 1 NACK NACK 0 1 SC2_SPI Serial controller 2 (Serial peripheral interface) SerialControll 0x0 0x0 0x19 registers n SC2_SPICR SC2_SPICR Serial controller SPI control register 0x18 32 read-write n 0x0 0x0 CPHA CPHA 1 1 CPOL CPOL 0 1 LSBFIRST LSBFIRST 2 1 MSTR MSTR 4 1 RPTEN RPTEN 3 1 RXMODE RXMODE 5 1 SC2_SPISR SC2_SPISR Serial controller SPI status register 0x0 32 read-only n 0x0 0x0 IDLE IDLE 3 1 OVF OVF 0 1 RXNE RXNE 1 1 TXE TXE 2 1 SLPTMR Sleep timer SLPTMR 0x0 0x0 0x4049 registers n SLPTIM_IRQ Sleep Timer Interrupt 4 SLPTIM Sleep Timer Interrupt 4 CMPAH SLPTMR_CMPAH SLPTMR compare A high register 0xC 32 read-write n 0x0 0x0 CMPAH CMPAH 0 16 CMPAL SLPTMR_CMPAL SLPTMR compare A low register 0x10 32 read-write n 0x0 0x0 CMPAL CMPAL 0 16 CMPBH SLPTMR_CMPBH SLPTMR compare B high register 0x14 32 read-write n 0x0 0x0 CMPBH CMPBH 0 16 CMPBL SLPTMR_CMPBL SLPTMR compare B low register 0x18 32 read-write n 0x0 0x0 CMPBL CMPBL 0 16 CNTH SLPTMR_CNTH SLPTMR counter high register 0x4 32 read-only n 0x0 0x0 CNTH CNTH 0 16 CNTL SLPTMR_CNTL SLPTMR counter high register 0x8 32 read-only n 0x0 0x0 CNTL CNTL 0 16 CR SLPTMR_CR SLPTMR configuration register 0x0 32 read-write n 0x0 0x0 CLKSEL CLKSEL 0 1 DBGP DBGP 10 1 EN EN 11 1 PSC PSC 4 4 REVERSE REVERSE 12 1 IER SLPTMR_IER SLPTMR interrupt enable register 0x4048 32 read-write n 0x0 0x0 CMPA CMPA 1 1 CMPB CMPB 2 1 WRAP WRAP 0 1 IFR SLPTMR_IFR SLPTMR force interrupts register 0x4014 32 read-write n 0x0 0x0 CMPA CMPA 1 1 CMPB CMPB 2 1 OW OW 0 1 ISR SLPTMR_ISR SLPTMR interrupt status register 0x4008 32 read-write n 0x0 0x0 CMPA CMPA 1 1 CMPB CMPB 2 1 OW OW 0 1 TIM1 General purpose timer 1 TIM 0x0 0x0 0x3851 registers n TIM1_IRQ Timer 1 Interrupt 0 TIM1 Timer 1 Interrupt 0 ARR TIM1_ARR TIM auto-reload register 0x382C 32 read-write n 0x0 0x0 ARR ARR 0 16 CCER TIM1_CCER TIM capture/compare enable register 0x3820 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CCMR1_Input TIM1_CCMR1_Input capture/compare mode register 1 (Input mode) 0x3818 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR1_Output TIM1_CCMR1_Output capture/compare mode register 1 (output mode) TIM1_CCMR1_Input 0x3818 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 OC1FE OC1FE 2 1 OC1M OC1M 4 3 OC1PE OC1PE 3 1 OC2FE OC2FE 10 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 CCMR2_Input TIM1_CCMR2_Input capture/compare mode register 2 (input mode) 0x381C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR2_Output TIM1_CCMR2_Output capture/compare mode register 2 (output mode) TIM1_CCMR2_Input 0x381C 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 OC3FE OC3FE 2 1 OC3M OC3M 4 3 OC3PE OC3PE 3 1 OC4FE OC4FE 10 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 CCR1 TIM1_CCR1 IM capture/compare register 1 0x3834 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR2 TIM1_CCR2 TIM capture/compare register 2 0x3838 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR3 TIM1_CCR3 TIM capture/compare register 3 0x383C 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR4 TIM1_CCR4 TIM capture/compare register 4 0x3840 32 read-write n 0x0 0x0 CCR CCR 0 16 CNT TIM1_CNT TIM counter register 0x3824 32 read-write n 0x0 0x0 CNT CNT 0 16 CR1 TIM1_CR1 control register 1 0x3800 32 read-write n 0x0 0x0 ARBE ARBE 7 1 CEN CEN 0 1 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 URS URS 2 1 CR2 TIM1_CR2 control register 2 0x3804 32 read-write n 0x0 0x0 MMS MMS 4 3 TI1S TI1S 7 1 EGR TIM1_EGR TIM event generation register 0x3814 32 write-only n 0x0 0x0 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 TG TG 6 1 UG UG 0 1 IER TIM1_IER TIM Interrupt Enable Register 0x40 32 read-write n 0x0 0x0 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 TIE TIE 6 1 UIE UIE 0 1 ISR TIM1_ISR TIM Interrupt Status Register 0x0 32 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC2IF CC2IF 2 1 read-write CC3IF CC3IF 3 1 read-write CC4IF CC4IF 4 1 read-write RSVD RSVD 8 5 read-only TIF TIF 6 1 read-write UIF UIF 0 1 read-write MISSR TIM1_MISSR TIM interrupt missed register 0x18 32 read-write n 0x0 0x0 CC1IM CC1IM 9 1 read-write CC2IM CC2IM 10 1 read-write CC3IM CC3IM 11 1 read-write CC4IM CC4IM 12 1 read-write RSVD RSVD 0 7 read-only OR TIM1_OR TIM option register 0x3850 32 read-write n 0x0 0x0 CLKMSKEN CLKMSKEN 2 1 EXTRIGSEL EXTRIGSEL 0 2 ORRSVD ORRSVD 3 1 PSC TIM1_PSC TIM prescaler register 0x3828 32 read-write n 0x0 0x0 PSC PSC 0 16 SMCR TIM1_SMCR slave Mode Control register 0x3808 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 TS TS 4 3 TIM2 General purpose timer 2 TIM 0x0 0x0 0x484D registers n TIM2_IRQ Timer 2 Interrupt 1 TIM2 Timer 2 Interrupt 1 ARR TIM2_ARR TIM auto-reload register 0x4828 32 read-write n 0x0 0x0 ARR ARR 0 16 CCER TIM2_CCER TIM capture/compare enable register 0x481C 32 read-write n 0x0 0x0 CC1E CC1E 0 1 CC1P CC1P 1 1 CC2E CC2E 4 1 CC2P CC2P 5 1 CC3E CC3E 8 1 CC3P CC3P 9 1 CC4E CC4E 12 1 CC4P CC4P 13 1 CCMR1_Input TIM2_CCMR1_Input capture/compare mode register 1 (Input mode) 0x4814 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 IC1F IC1F 4 4 IC1PSC IC1PSC 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR1_Output TIM2_CCMR1_Output capture/compare mode register 1 (output mode) TIM2_CCMR1_Input 0x4814 32 read-write n 0x0 0x0 CC1S CC1S 0 2 CC2S CC2S 8 2 OC1FE OC1FE 2 1 OC1M OC1M 4 3 OC1PE OC1PE 3 1 OC2FE OC2FE 10 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 CCMR2_Input TIM2_CCMR2_Input capture/compare mode register 2 (input mode) 0x4818 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 IC3F IC3F 4 4 IC3PSC IC3PSC 2 2 IC4F IC4F 12 4 IC4PSC IC4PSC 10 2 CCMR2_Output TIM2_CCMR2_Output capture/compare mode register 2 (output mode) TIM2_CCMR2_Input 0x4818 32 read-write n 0x0 0x0 CC3S CC3S 0 2 CC4S CC4S 8 2 OC3FE OC3FE 2 1 OC3M OC3M 4 3 OC3PE OC3PE 3 1 OC4FE OC4FE 10 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 CCR1 TIM2_CCR1 TIM capture/compare register 1 0x4830 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR2 TIM2_CCR2 TIM capture/compare register 2 0x4834 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR3 TIM2_CCR3 TIM capture/compare register 3 0x4838 32 read-write n 0x0 0x0 CCR CCR 0 16 CCR4 TIM2_CCR4 TIM capture/compare register 4 0x483C 32 read-write n 0x0 0x0 CCR CCR 0 16 CNT TIM2_CNT TIM counter register 0x4820 32 read-write n 0x0 0x0 CNT CNT 0 16 CR1 TIM2_CR1 control register 1 0x47FC 32 read-write n 0x0 0x0 ARBE ARBE 7 1 CEN CEN 0 1 CMS CMS 5 2 DIR DIR 4 1 OPM OPM 3 1 UDIS UDIS 1 1 URS URS 2 1 CR2 TIM2_CR2 control register 1 0x4800 32 read-write n 0x0 0x0 MMS MMS 4 3 TI1S TI1S 7 1 EGR TIM2_EGR TIM event generation register 0x4810 32 write-only n 0x0 0x0 CC1G CC1G 1 1 CC2G CC2G 2 1 CC3G CC3G 3 1 CC4G CC4G 4 1 TG TG 6 1 UG UG 0 1 IER TIM2_IER TIM Interrupt Enable Register 0x40 32 read-write n 0x0 0x0 CC1IE CC1IE 1 1 CC2IE CC2IE 2 1 CC3IE CC3IE 3 1 CC4IE CC4IE 4 1 TIE TIE 6 1 UIE UIE 0 1 ISR TIM2_ISR TIM Interrupt Status Register 0x0 32 read-write n 0x0 0x0 CC1IF CC1IF 1 1 read-write CC2IF CC2IF 2 1 read-write CC3IF CC3IF 3 1 read-write CC4IF CC4IF 4 1 read-write RSVD RSVD 8 5 read-only TIF TIF 6 1 read-write UIF UIF 0 1 read-write MISSR TIM2_MISSR TIM interrupt missed register 0x18 32 read-write n 0x0 0x0 CC1IM CC1IM 9 1 read-write CC2IM CC2IM 10 1 read-write CC3IM CC3IM 11 1 read-write CC4IM CC4IM 12 1 read-write RSVD RSVD 0 7 read-only OR TIM2_OR TIM option register 0x484C 32 read-write n 0x0 0x0 CLKMSKEN CLKMSKEN 2 1 EXTRIGSEL EXTRIGSEL 0 2 ORRSVD ORRSVD 3 1 REMAPC1 REMAPC1 4 1 REMAPC2 REMAPC2 5 1 REMAPC3 REMAPC3 6 1 REMAPC4 REMAPC4 7 1 PSC TIM2_PSC TIM prescaler register 0x4824 32 read-write n 0x0 0x0 PSC PSC 0 16 SMCR TIM2_SMCR TIM slave Mode Control register 0x4804 32 read-write n 0x0 0x0 ECE ECE 14 1 ETF ETF 8 4 ETP ETP 15 1 ETPS ETPS 12 2 MSM MSM 7 1 SMS SMS 0 3 TS TS 4 3 WDG Watchdog timer WDG 0x0 0x0 0x9 registers n 0x0 0x9 registers n CR WDG_CR WDG configuration register 0x0 32 read-write n 0x0 0x0 WDGDIS WDGDIS 1 1 WDGEN WDGEN 0 1 KICKSR WDG_KICKSR WDG kick-start register 0x8 32 write-only n 0x0 0x0 KS KS 0 16 KR WDG_KR WDG key register 0x4 32 write-only n 0x0 0x0 KEY KEY 0 16