STMicroelectronics
STM32WL5x_CM0P
2024.04.27
STM32WL5x_CM0P
CM0
r0p1
little
true
4
false
8
32
ADC
Analog to digital convertor
ADC
0x0
0x0
0x400
registers
n
ADC_COMP_DAC
ADC and DAC global interrupt,COMP1 and COMP2 interrupt through EXTI
7
AWD1TR
ADC_AWD1TR
ADC watchdog threshold register
0x20
32
read-write
n
0x0
0x0
HT1
HT1
16
12
LT1
LT1
0
12
AWD2CR
ADC_AWD2CR
ADC Analog Watchdog 2 Configuration register
0xA0
32
read-write
n
0x0
0x0
AWD2CH
AWD2CH
0
18
AWD2TR
ADC_AWD2TR
ADC watchdog threshold register
0x24
32
read-write
n
0x0
0x0
HT2
HT2
16
12
LT2
LT2
0
12
AWD3CR
ADC_AWD3CR
ADC Analog Watchdog 3 Configuration register
0xA4
32
read-write
n
0x0
0x0
AWD3CH
AWD3CH
0
18
AWD3TR
ADC_AWD3TR
ADC watchdog threshold register
0x2C
32
read-write
n
0x0
0x0
HT3
HT3
16
12
LT3
LT3
0
12
CALFACT
ADC_CALFACT
ADC Calibration factor
0xB4
32
read-write
n
0x0
0x0
CALFACT
CALFACT
0
7
CCR
ADC_CCR
ADC common configuration register
0x308
32
read-write
n
0x0
0x0
PRESC0
PRESC0
18
1
PRESC1
PRESC1
19
1
PRESC2
PRESC2
20
1
PRESC3
PRESC3
21
1
TSEN
TSEN
23
1
VBATEN
VBATEN
24
1
VREFEN
VREFEN
22
1
CFGR1
ADC_CFGR1
ADC configuration register 1
0xC
32
read-write
n
0x0
0x0
ALIGN
ALIGN
5
1
AUTOFF
AUTOFF
15
1
AWD1CH
AWD1CH
26
5
AWD1EN
AWD1EN
23
1
AWD1SGL
AWD1SGL
22
1
CHSELRMOD
CHSELRMOD
21
1
CONT
CONT
13
1
DISCEN
DISCEN
16
1
DMACFG
DMACFG
1
1
DMAEN
DMAEN
0
1
EXTEN
EXTEN
10
2
EXTSEL
EXTSEL
6
3
OVRMOD
OVRMOD
12
1
RES
RES
3
2
SCANDIR
SCANDIR
2
1
WAIT
WAIT
14
1
CFGR2
ADC_CFGR2
ADC configuration register 2
0x10
32
read-write
n
0x0
0x0
CKMODE
CKMODE
30
2
LFTRIG
LFTRIG
29
1
OVSE
OVSE
0
1
OVSR0
OVSR0
2
1
OVSR1
OVSR1
3
1
OVSR2
OVSR2
4
1
OVSS0
OVSS0
5
1
OVSS1
OVSS1
6
1
OVSS2
OVSS2
7
1
OVSS3
OVSS3
8
1
TOVS
TOVS
9
1
CHSELR0
ADC_CHSELR0
channel selection register
0x28
32
read-write
n
0x0
0x0
CHSEL
CHSEL
0
18
CHSELR1
ADC_CHSELR1
channel selection register
ADC_CHSELR0
0x28
32
read-write
n
0x0
0x0
SQ1
SQ1
0
4
SQ2
SQ2
4
4
SQ3
SQ3
8
4
SQ4
SQ4
12
4
SQ5
SQ5
16
4
SQ6
SQ6
20
4
SQ7
SQ7
24
4
SQ8
SQ8
28
4
CR
ADC_CR
ADC control register
0x8
32
read-write
n
0x0
0x0
ADCAL
ADCAL
31
1
ADDIS
ADDIS
1
1
ADEN
ADEN
0
1
ADSTART
ADSTART
2
1
ADSTP
ADSTP
4
1
ADVREGEN
ADVREGEN
28
1
DR
ADC_DR
ADC data register
0x40
32
read-only
n
0x0
0x0
DATA
DATA
0
16
IER
ADC_IER
ADC interrupt enable register
0x4
32
read-write
n
0x0
0x0
ADRDYIE
ADRDYIE
0
1
AWD1IE
AWD1IE
7
1
AWD2IE
AWD2IE
8
1
AWD3IE
AWD3IE
9
1
CCRDYIE
CCRDYIE
13
1
EOCALIE
EOCALIE
11
1
EOCIE
EOCIE
2
1
EOSIE
EOSIE
3
1
EOSMPIE
EOSMPIE
1
1
OVRIE
OVRIE
4
1
ISR
ADC_ISR
ADC interrupt and status register
0x0
32
read-write
n
0x0
0x0
ADRDY
ADRDY
0
1
AWD1
AWD1
7
1
AWD2
AWD2
8
1
AWD3
AWD3
9
1
CCRDY
CCRDY
13
1
EOC
EOC
2
1
EOCAL
EOCAL
11
1
EOS
EOS
3
1
EOSMP
EOSMP
1
1
OVR
OVR
4
1
SMPR
ADC_SMPR
ADC sampling time register
0x14
32
read-write
n
0x0
0x0
SMP1
SMP1
0
3
SMP2
SMP2
4
3
SMPSEL
SMPSEL
8
18
AES
Advanced encryption standard hardware accelerator 1
AES
0x0
0x0
0x400
registers
n
AES_PKA
AES global interrupt , Private key accelerator interrupt
21
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
CCFC
Computation Complete Flag Clear
7
1
CCFIE
CCF flag interrupt enable
9
1
CHMOD10
AES chaining mode Bit1 Bit0
5
2
CHMOD2
AES chaining mode Bit2
16
1
DATATYPE
Data type selection (for data in and data out to/from the cryptographic block)
1
2
DMAINEN
Enable DMA management of data input phase
11
1
DMAOUTEN
Enable DMA management of data output phase
12
1
EN
AES enable
0
1
ERRC
Error clear
8
1
ERRIE
Error interrupt enable
10
1
GCMPH
Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected
13
2
KEYSIZE
Key size selection
18
1
MODE
AES operating mode
3
2
NPBLB
Number of padding bytes in last block of payload
20
4
DINR
DINR
data input register
0x8
32
read-write
n
0x0
0x0
AES_DINR
Data Input Register
0
32
DOUTR
DOUTR
data output register
0xC
32
read-only
n
0x0
0x0
AES_DOUTR
Data output register
0
32
IVR0
IVR0
initialization vector register 0
0x20
32
read-write
n
0x0
0x0
AES_IVR0
initialization vector register (LSB IVR [31:0])
0
32
IVR1
IVR1
initialization vector register 1
0x24
32
read-write
n
0x0
0x0
AES_IVR1
Initialization Vector Register (IVR [63:32])
0
32
IVR2
IVR2
initialization vector register 2
0x28
32
read-write
n
0x0
0x0
AES_IVR2
Initialization Vector Register (IVR [95:64])
0
32
IVR3
IVR3
initialization vector register 3
0x2C
32
read-write
n
0x0
0x0
AES_IVR3
Initialization Vector Register (MSB IVR [127:96])
0
32
KEYR0
KEYR0
key register 0
0x10
32
write-only
n
0x0
0x0
AES_KEYR0
Data Output Register (LSB key [31:0])
0
32
KEYR1
KEYR1
key register 1
0x14
32
write-only
n
0x0
0x0
AES_KEYR1
AES key register (key [63:32])
0
32
KEYR2
KEYR2
key register 2
0x18
32
write-only
n
0x0
0x0
AES_KEYR2
AES key register (key [95:64])
0
32
KEYR3
KEYR3
key register 3
0x1C
32
write-only
n
0x0
0x0
AES_KEYR3
AES key register (MSB key [127:96])
0
32
KEYR4
KEYR4
key register 4
0x30
32
write-only
n
0x0
0x0
AES_KEYR4
AES key register (MSB key [159:128])
0
32
KEYR5
KEYR5
key register 5
0x34
32
write-only
n
0x0
0x0
AES_KEYR5
AES key register (MSB key [191:160])
0
32
KEYR6
KEYR6
key register 6
0x38
32
write-only
n
0x0
0x0
AES_KEYR6
AES key register (MSB key [223:192])
0
32
KEYR7
KEYR7
key register 7
0x3C
32
write-only
n
0x0
0x0
AES_KEYR7
AES key register (MSB key [255:224])
0
32
SR
SR
status register
0x4
32
read-only
n
0x0
0x0
BUSY
Busy flag
3
1
CCF
Computation complete flag
0
1
RDERR
Read error flag
1
1
WRERR
Write error flag
2
1
SUSP0R
SUSP0R
AES suspend register 0
0x40
32
read-write
n
0x0
0x0
AES_SUSP0R
AES suspend register 0
0
32
SUSP1R
SUSP1R
AES suspend register 1
0x44
32
read-write
n
0x0
0x0
AES_SUSP1R
AES suspend register 1
0
32
SUSP2R
SUSP2R
AES suspend register 2
0x48
32
read-write
n
0x0
0x0
AES_SUSP2R
AES suspend register 2
0
32
SUSP3R
SUSP3R
AES suspend register 3
0x4C
32
read-write
n
0x0
0x0
AES_SUSP3R
AES suspend register 3
0
32
SUSP4R
SUSP4R
AES suspend register 4
0x50
32
read-write
n
0x0
0x0
AES_SUSP4R
AES suspend register 4
0
32
SUSP5R
SUSP5R
AES suspend register 5
0x54
32
read-write
n
0x0
0x0
AES_SUSP5R
AES suspend register 5
0
32
SUSP6R
SUSP6R
AES suspend register 6
0x58
32
read-write
n
0x0
0x0
AES_SUSP6R
AES suspend register 6
0
32
SUSP7R
SUSP7R
AES suspend register 7
0x5C
32
read-write
n
0x0
0x0
AES_SUSP7R
AES suspend register 7
0
32
COMP
Comparator
COMP
0x0
0x0
0x200
registers
n
COMP1_CSR
COMP1_CSR
COMP1_CSR
0x0
32
read-write
n
0x0
0x0
BLANKING
Comparator 1 blanking source selection bits
18
3
read-write
BRGEN
Scaler bridge enable
22
1
read-write
EN
Comparator 1 enable bit
0
1
read-write
HYST
Comparator 1 hysteresis selection bits
16
2
read-write
INMESEL
comparator 1 input minus extended selection bits.
25
2
read-write
INMSEL
Comparator 1 input minus selection bits
4
3
read-write
INPSEL
Comparator1 input plus selection bit
7
2
read-write
LOCK
COMP1_CSR register lock bit
31
1
read-write
POLARITY
Comparator 1 polarity selection bit
15
1
read-write
PWRMODE
Power Mode of the comparator 1
2
2
read-write
SCALEN
Voltage scaler enable bit
23
1
read-write
VALUE
Comparator 1 output status bit
30
1
read-only
COMP2_CSR
COMP2_CSR
COMP2_CSR
0x4
32
read-write
n
0x0
0x0
BLANKING
Comparator 2 blanking source selection bits
18
3
read-write
BRGEN
Scaler bridge enable
22
1
read-write
EN
Comparator 2 enable bit
0
1
read-write
HYST
Comparator 2 hysteresis selection bits
16
2
read-write
INMESEL
comparator 2 input minus extended selection bits.
25
2
read-write
INMSEL
Comparator 2 input minus selection bits
4
3
read-write
INPSEL
Comparator 1 input plus selection bit
7
2
read-write
LOCK
CSR register lock bit
31
1
read-write
POLARITY
Comparator 2 polarity selection bit
15
1
read-write
PWRMODE
Power Mode of the comparator 2
2
2
read-write
SCALEN
Voltage scaler enable bit
23
1
read-write
VALUE
Comparator 2 output status bit
30
1
read-only
WINMODE
Windows mode selection bit
9
1
read-write
CRC
Cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CR
CR
Control register
0x8
32
read-write
n
0x0
0x0
POLYSIZE
Polynomial size
3
2
RESET
RESET bit
0
1
REV_IN
Reverse input data
5
2
REV_OUT
Reverse output data
7
1
DR
DR
Data register
0x0
32
read-write
n
0x0
0x0
DR
Data register bits
0
32
IDR
IDR
Independent data register
0x4
32
read-write
n
0x0
0x0
IDR
General-purpose 32-bit data register bits
0
32
INIT
INIT
Initial CRC value
0x10
32
read-write
n
0x0
0x0
CRC_INIT
Programmable initial CRC value
0
32
POL
POL
polynomial
0x14
32
read-write
n
0x0
0x0
POL
Programmable polynomial
0
32
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
CCR
CCR
calibration control register
0x38
32
read-write
n
0x0
0x0
OTRIM1
DAC Channel 1 offset trimming value
0
5
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
CEN1
DAC Channel 1 calibration enable
14
1
DMAEN1
DAC channel1 DMA enable
12
1
DMAUDRIE1
DAC channel1 DMA Underrun Interrupt enable
13
1
EN1
DAC channel1 enable
0
1
MAMP1
DAC channel1 mask/amplitude selector
8
4
TEN1
DAC channel1 trigger enable
1
1
TSEL10
TSEL10
2
1
TSEL11
TSEL11
3
1
TSEL12
TSEL12
4
1
TSEL13
DAC channel1 trigger selection
5
1
WAVE1
DAC channel1 noise/triangle wave generation enable
6
2
DHR12L1
DHR12L1
channel1 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12LD
DHR12LD
Dual DAC 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit left-aligned data
4
12
DHR12R1
DHR12R1
channel1 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR12RD
DHR12RD
Dual DAC 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 12-bit right-aligned data
0
12
DHR8R1
DHR8R1
channel1 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DHR8RD
DHR8RD
Dual DAC 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DACC1DHR
DAC channel1 8-bit right-aligned data
0
8
DOR1
DOR1
DAC channel1 data output register
0x2C
32
read-only
n
0x0
0x0
DACC1DOR
DACC1DOR
0
12
MCR
MCR
mode control register
0x3C
32
read-write
n
0x0
0x0
MODE1
DAC Channel 1 mode
0
3
SHHR
SHHR
Sample and Hold hold time register
0x48
32
read-write
n
0x0
0x0
THOLD1
DAC Channel 1 hold Time (only valid in Sample and Hold mode)
0
10
SHRR
SHRR
Sample and Hold refresh time register
0x4C
32
read-write
n
0x0
0x0
TREFRESH1
DAC Channel 1 refresh Time (only valid in Sample and Hold mode)
0
8
SHSR1
SHSR1
Sample and Hold sample time register 1
0x40
32
read-write
n
0x0
0x0
TSAMPLE1
DAC Channel 1 sample Time (only valid in Sample and Hold mode)
0
10
SR
SR
status register
0x34
32
read-write
n
0x0
0x0
BWST1
DAC Channel 1 busy writing sample time flag
15
1
read-only
CAL_FLAG1
DAC Channel 1 calibration offset status
14
1
read-only
DMAUDR1
DAC channel1 DMA underrun flag
13
1
read-write
SWTRGR
SWTRGR
software trigger register
0x4
32
read-write
n
0x0
0x0
SWTRIG1
DAC channel1 software trigger
0
1
write-only
DMA1
Direct memory access controller
DMA
0x0
0x0
0x400
registers
n
DMA1_CH3_1
DMA1 channel 3:1 secure and non-secure interrupt (C2IMR2[2:0])
8
DMA1_CH7_4
DMA1 channel 7:4 secure and non-secure interrupt (C2IMR2[6:3])
9
CCR1
CCR1
channel x configuration register
0x8
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR2
CCR2
channel x configuration register
0x1C
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR3
CCR3
channel x configuration register
0x30
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR4
CCR4
channel x configuration register
0x44
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR5
CCR5
channel x configuration register
0x58
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR6
CCR6
channel x configuration register
0x6C
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR7
CCR7
channel x configuration register
0x80
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CMAR1
CMAR1
channel x memory address register
0x14
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR2
CMAR2
channel x memory address register
0x28
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR3
CMAR3
channel x memory address register
0x3C
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR4
CMAR4
channel x memory address register
0x50
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR5
CMAR5
channel x memory address register
0x64
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR6
CMAR6
channel x memory address register
0x78
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR7
CMAR7
channel x memory address register
0x8C
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CNDTR1
CNDTR1
channel x number of data to transfer register
0xC
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR2
CNDTR2
channel x number of data to transfer register
0x20
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR3
CNDTR3
channel x number of data to transfer register
0x34
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR4
CNDTR4
channel x number of data to transfer register
0x48
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR5
CNDTR5
channel x number of data to transfer register
0x5C
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR6
CNDTR6
channel x number of data to transfer register
0x70
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR7
CNDTR7
channel x number of data to transfer register
0x84
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CPAR1
CPAR1
channel x peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR2
CPAR2
channel x peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR3
CPAR3
channel x peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR4
CPAR4
channel x peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR5
CPAR5
channel x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR6
CPAR6
channel x peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR7
CPAR7
channel x peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
IFCR
IFCR
interrupt flag clear register
0x4
32
write-only
n
0x0
0x0
GIF1
global interrupt flag clear for channel 1
0
1
GIF2
global interrupt flag clear for channel 2
4
1
GIF3
global interrupt flag clear for channel 3
8
1
GIF4
global interrupt flag clear for channel 4
12
1
GIF5
global interrupt flag clear for channel 5
16
1
GIF6
global interrupt flag clear for channel 6
20
1
GIF7
global interrupt flag clear for channel 7
24
1
HTIF1
half transfer flag clear for channel 1
2
1
HTIF2
half transfer flag clear for channel 2
6
1
HTIF3
half transfer flag clear for channel 3
10
1
HTIF4
half transfer flag clear for channel 4
14
1
HTIF5
half transfer flag clear for channel 5
18
1
HTIF6
half transfer flag clear for channel 6
22
1
HTIF7
half transfer flag clear for channel 7
26
1
TCIF1
transfer complete flag clear for channel 1
1
1
TCIF2
transfer complete flag clear for channel 2
5
1
TCIF3
transfer complete flag clear for channel 3
9
1
TCIF4
transfer complete flag clear for channel 4
13
1
TCIF5
transfer complete flag clear for channel 5
17
1
TCIF6
transfer complete flag clear for channel 6
21
1
TCIF7
transfer complete flag clear for channel 7
25
1
TEIF1
transfer error flag clear for channel 1
3
1
TEIF2
transfer error flag clear for channel 2
7
1
TEIF3
transfer error flag clear for channel 3
11
1
TEIF4
transfer error flag clear for channel 4
15
1
TEIF5
transfer error flag clear for channel 5
19
1
TEIF6
transfer error flag clear for channel 6
23
1
TEIF7
transfer error flag clear for channel 7
27
1
ISR
ISR
interrupt status register
0x0
32
read-only
n
0x0
0x0
GIF1
global interrupt flag for channel 1
0
1
GIF2
global interrupt flag for channel 2
4
1
GIF3
global interrupt flag for channel 3
8
1
GIF4
global interrupt flag for channel 4
12
1
GIF5
global interrupt flag for channel 5
16
1
GIF6
global interrupt flag for channel 6
20
1
GIF7
global interrupt flag for channel 7
24
1
HTIF1
half transfer (HT) flag for channel 1
2
1
HTIF2
half transfer (HT) flag for channel 2
6
1
HTIF3
half transfer (HT) flag for channel 3
10
1
HTIF4
half transfer (HT) flag for channel 4
14
1
HTIF5
half transfer (HT) flag for channel 5
18
1
HTIF6
half transfer (HT) flag for channel 6
22
1
HTIF7
half transfer (HT) flag for channel 7
26
1
TCIF1
transfer complete (TC) flag for channel 1
1
1
TCIF2
transfer complete (TC) flag for channel 2
5
1
TCIF3
transfer complete (TC) flag for channel 3
9
1
TCIF4
transfer complete (TC) flag for channel 4
13
1
TCIF5
transfer complete (TC) flag for channel 5
17
1
TCIF6
transfer complete (TC) flag for channel 6
21
1
TCIF7
transfer complete (TC) flag for channel 7
25
1
TEIF1
transfer error (TE) flag for channel 1
3
1
TEIF2
transfer error (TE) flag for channel 2
7
1
TEIF3
transfer error (TE) flag for channel 3
11
1
TEIF4
transfer error (TE) flag for channel 4
15
1
TEIF5
transfer error (TE) flag for channel 5
19
1
TEIF6
transfer error (TE) flag for channel 6
23
1
TEIF7
transfer error (TE) flag for channel 7
27
1
DMA2
Direct memory access controller
DMA
0x0
0x0
0x400
registers
n
DMA2_CH7_1_DMAMUX1_OVR
DMA2 channel 7:1 secure and non-secure interrupt (C2IMR2[14:8]),DMAMUX1 overrun interrupt (C2IMR2[15])
10
CCR1
CCR1
channel x configuration register
0x8
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR2
CCR2
channel x configuration register
0x1C
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR3
CCR3
channel x configuration register
0x30
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR4
CCR4
channel x configuration register
0x44
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR5
CCR5
channel x configuration register
0x58
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR6
CCR6
channel x configuration register
0x6C
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CCR7
CCR7
channel x configuration register
0x80
32
read-write
n
0x0
0x0
CIRC
circular mode
5
1
DIR
data transfer direction
4
1
DSEC
ecurity of the DMA transfer to the destination
19
1
EN
channel enable
0
1
HTIE
half transfer interrupt enable
2
1
MEM2MEM
memory-to-memory mode
14
1
MINC
memory increment mode
7
1
MSIZE
memory size
10
2
PINC
peripheral increment mode
6
1
PL
priority level
12
2
PRIV
rivileged mode
20
1
PSIZE
peripheral size
8
2
SECM
ecure mode
17
1
SSEC
ecurity of the DMA transfer from the source
18
1
TCIE
transfer complete interrupt enable
1
1
TEIE
transfer error interrupt enable
3
1
CMAR1
CMAR1
channel x memory address register
0x14
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR2
CMAR2
channel x memory address register
0x28
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR3
CMAR3
channel x memory address register
0x3C
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR4
CMAR4
channel x memory address register
0x50
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR5
CMAR5
channel x memory address register
0x64
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR6
CMAR6
channel x memory address register
0x78
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CMAR7
CMAR7
channel x memory address register
0x8C
32
read-write
n
0x0
0x0
MA
peripheral address
0
32
CNDTR1
CNDTR1
channel x number of data to transfer register
0xC
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR2
CNDTR2
channel x number of data to transfer register
0x20
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR3
CNDTR3
channel x number of data to transfer register
0x34
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR4
CNDTR4
channel x number of data to transfer register
0x48
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR5
CNDTR5
channel x number of data to transfer register
0x5C
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR6
CNDTR6
channel x number of data to transfer register
0x70
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CNDTR7
CNDTR7
channel x number of data to transfer register
0x84
32
read-write
n
0x0
0x0
NDT
number of data to transfer (0 to 218 - 1)
0
18
CPAR1
CPAR1
channel x peripheral address register
0x10
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR2
CPAR2
channel x peripheral address register
0x24
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR3
CPAR3
channel x peripheral address register
0x38
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR4
CPAR4
channel x peripheral address register
0x4C
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR5
CPAR5
channel x peripheral address register
0x60
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR6
CPAR6
channel x peripheral address register
0x74
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
CPAR7
CPAR7
channel x peripheral address register
0x88
32
read-write
n
0x0
0x0
PA
peripheral address
0
32
IFCR
IFCR
interrupt flag clear register
0x4
32
write-only
n
0x0
0x0
GIF1
global interrupt flag clear for channel 1
0
1
GIF2
global interrupt flag clear for channel 2
4
1
GIF3
global interrupt flag clear for channel 3
8
1
GIF4
global interrupt flag clear for channel 4
12
1
GIF5
global interrupt flag clear for channel 5
16
1
GIF6
global interrupt flag clear for channel 6
20
1
GIF7
global interrupt flag clear for channel 7
24
1
HTIF1
half transfer flag clear for channel 1
2
1
HTIF2
half transfer flag clear for channel 2
6
1
HTIF3
half transfer flag clear for channel 3
10
1
HTIF4
half transfer flag clear for channel 4
14
1
HTIF5
half transfer flag clear for channel 5
18
1
HTIF6
half transfer flag clear for channel 6
22
1
HTIF7
half transfer flag clear for channel 7
26
1
TCIF1
transfer complete flag clear for channel 1
1
1
TCIF2
transfer complete flag clear for channel 2
5
1
TCIF3
transfer complete flag clear for channel 3
9
1
TCIF4
transfer complete flag clear for channel 4
13
1
TCIF5
transfer complete flag clear for channel 5
17
1
TCIF6
transfer complete flag clear for channel 6
21
1
TCIF7
transfer complete flag clear for channel 7
25
1
TEIF1
transfer error flag clear for channel 1
3
1
TEIF2
transfer error flag clear for channel 2
7
1
TEIF3
transfer error flag clear for channel 3
11
1
TEIF4
transfer error flag clear for channel 4
15
1
TEIF5
transfer error flag clear for channel 5
19
1
TEIF6
transfer error flag clear for channel 6
23
1
TEIF7
transfer error flag clear for channel 7
27
1
ISR
ISR
interrupt status register
0x0
32
read-only
n
0x0
0x0
GIF1
global interrupt flag for channel 1
0
1
GIF2
global interrupt flag for channel 2
4
1
GIF3
global interrupt flag for channel 3
8
1
GIF4
global interrupt flag for channel 4
12
1
GIF5
global interrupt flag for channel 5
16
1
GIF6
global interrupt flag for channel 6
20
1
GIF7
global interrupt flag for channel 7
24
1
HTIF1
half transfer (HT) flag for channel 1
2
1
HTIF2
half transfer (HT) flag for channel 2
6
1
HTIF3
half transfer (HT) flag for channel 3
10
1
HTIF4
half transfer (HT) flag for channel 4
14
1
HTIF5
half transfer (HT) flag for channel 5
18
1
HTIF6
half transfer (HT) flag for channel 6
22
1
HTIF7
half transfer (HT) flag for channel 7
26
1
TCIF1
transfer complete (TC) flag for channel 1
1
1
TCIF2
transfer complete (TC) flag for channel 2
5
1
TCIF3
transfer complete (TC) flag for channel 3
9
1
TCIF4
transfer complete (TC) flag for channel 4
13
1
TCIF5
transfer complete (TC) flag for channel 5
17
1
TCIF6
transfer complete (TC) flag for channel 6
21
1
TCIF7
transfer complete (TC) flag for channel 7
25
1
TEIF1
transfer error (TE) flag for channel 1
3
1
TEIF2
transfer error (TE) flag for channel 2
7
1
TEIF3
transfer error (TE) flag for channel 3
11
1
TEIF4
transfer error (TE) flag for channel 4
15
1
TEIF5
transfer error (TE) flag for channel 5
19
1
TEIF6
transfer error (TE) flag for channel 6
23
1
TEIF7
transfer error (TE) flag for channel 7
27
1
DMAMUX
DMA request multiplexer
DMAMUX
0x0
0x0
0x400
registers
n
C0CR
C0CR
request line multiplexer channel x configuration register
0x0
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C10CR
C10CR
C10CR
0x28
32
read-write
n
0x0
0x0
DMAREQ_ID
DMAREQ_ID
0
8
EGE
EGE
9
1
NBREQ
NBREQ
19
5
SE
SE
16
1
SOIE
SOIE
8
1
SPOL
SPOL
17
2
SYNC_ID
SYNC_ID
24
5
C11CR
C11CR
C11CR
0x2C
32
read-write
n
0x0
0x0
DMAREQ_ID
DMAREQ_ID
0
8
EGE
EGE
9
1
NBREQ
NBREQ
19
5
SE
SE
16
1
SOIE
SOIE
8
1
SPOL
SPOL
17
2
SYNC_ID
SYNC_ID
24
5
C12CR
C12CR
C12CR
0x30
32
read-write
n
0x0
0x0
DMAREQ_ID
DMAREQ_ID
0
8
EGE
EGE
9
1
NBREQ
NBREQ
19
5
SE
SE
16
1
SOIE
SOIE
8
1
SPOL
SPOL
17
2
SYNC_ID
SYNC_ID
24
5
C13CR
C13CR
C13CR
0x34
32
read-write
n
0x0
0x0
DMAREQ_ID
DMAREQ_ID
0
8
EGE
EGE
9
1
NBREQ
NBREQ
19
5
SE
SE
16
1
SOIE
SOIE
8
1
SPOL
SPOL
17
2
SYNC_ID
SYNC_ID
24
5
C1CR
C1CR
request line multiplexer channel x configuration register
0x4
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C2CR
C2CR
request line multiplexer channel x configuration register
0x8
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C3CR
C3CR
request line multiplexer channel x configuration register
0xC
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C4CR
C4CR
request line multiplexer channel x configuration register
0x10
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C5CR
C5CR
request line multiplexer channel x configuration register
0x14
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C6CR
C6CR
request line multiplexer channel x configuration register
0x18
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C7CR
C7CR
request line multiplexer channel x configuration register
0x1C
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C8CR
C8CR
request line multiplexer channel x configuration register
0x20
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
C9CR
C9CR
request line multiplexer channel x configuration register
0x24
32
read-write
n
0x0
0x0
DMAREQ_ID
DMA request identification
0
8
EGE
Event generation enable
9
1
NBREQ
Number of DMA requests minus 1 to forward
19
5
SE
Synchronization enable
16
1
SOIE
Synchronization overrun interrupt enable
8
1
SPOL
Synchronization polarity
17
2
SYNC_ID
Synchronization identification
24
5
CCFR
CCFR
request line multiplexer interrupt channel clear flag register
0x84
32
write-only
n
0x0
0x0
CSOF0
CSOF0
0
1
CSOF1
CSOF1
1
1
CSOF10
CSOF10
10
1
CSOF11
CSOF11
11
1
CSOF12
CSOF12
12
1
CSOF13
CSOF13
13
1
CSOF2
CSOF2
2
1
CSOF3
CSOF3
3
1
CSOF4
CSOF4
4
1
CSOF5
CSOF5
5
1
CSOF6
CSOF6
6
1
CSOF7
CSOF7
7
1
CSOF8
CSOF8
8
1
CSOF9
CSOF9
9
1
CSR
CSR
request line multiplexer interrupt channel status register
0x80
32
read-only
n
0x0
0x0
SOF0
SOF0
0
1
SOF1
SOF1
1
1
SOF10
SOF10
10
1
SOF11
SOF11
11
1
SOF12
SOF12
12
1
SOF13
Synchronization overrun event flag
13
1
SOF2
SOF2
2
1
SOF3
SOF3
3
1
SOF4
SOF4
4
1
SOF5
SOF5
5
1
SOF6
SOF6
6
1
SOF7
SOF7
7
1
SOF8
SOF8
8
1
SOF9
SOF9
9
1
RG0CR
RG0CR
request generator channel x configuration register
0x100
32
read-write
n
0x0
0x0
GE
DMA request generator channel x enable
16
1
GNBREQ
Number of DMA requests to be generated (minus 1)
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG1CR
RG1CR
request generator channel x configuration register
0x104
32
read-write
n
0x0
0x0
GE
DMA request generator channel x enable
16
1
GNBREQ
Number of DMA requests to be generated (minus 1)
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG2CR
RG2CR
request generator channel x configuration register
0x108
32
read-write
n
0x0
0x0
GE
DMA request generator channel x enable
16
1
GNBREQ
Number of DMA requests to be generated (minus 1)
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RG3CR
RG3CR
request generator channel x configuration register
0x10C
32
read-write
n
0x0
0x0
GE
DMA request generator channel x enable
16
1
GNBREQ
Number of DMA requests to be generated (minus 1)
19
5
GPOL
DMA request generator trigger polarity
17
2
OIE
Trigger overrun interrupt enable
8
1
SIG_ID
Signal identification
0
5
RGCFR
RGCFR
request generator interrupt clear flag register
0x144
32
write-only
n
0x0
0x0
COF0
COF0
0
1
COF1
COF1
1
1
COF2
COF2
2
1
COF3
Clear trigger overrun event flag
3
1
RGSR
RGSR
request generator interrupt status register
0x140
32
read-only
n
0x0
0x0
OF0
OF0
0
1
OF1
OF1
1
1
OF2
OF2
2
1
OF3
Trigger overrun event flag
3
1
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
PVD_PVM_3
PVD through EXTI[16], PVM[3] through EXTI[34]
1
EXTI1_0
EXTI line 0 interrupt through EXTI
4
EXTI3_2
EXTI line 1 interrupt through EXTI
5
EXTI15_4
EXTI line 2 interrupt through EXTI
6
Radio_IRQ_Busy
Radio IRQs, RFBUSY interrupt through EXTI
31
C1EMR1
C1EMR1
event mask register
0x84
32
read-write
n
0x0
0x0
EM0
Wakeup with event generation Mask on Event input
0
1
EM1
Wakeup with event generation Mask on Event input
1
1
EM10
Wakeup with event generation Mask on Event input
10
1
EM11
Wakeup with event generation Mask on Event input
11
1
EM12
Wakeup with event generation Mask on Event input
12
1
EM13
Wakeup with event generation Mask on Event input
13
1
EM14
Wakeup with event generation Mask on Event input
14
1
EM15
Wakeup with event generation Mask on Event input
15
1
EM17
Wakeup with event generation Mask on Event input
17
1
EM18
Wakeup with event generation Mask on Event input
18
1
EM19
Wakeup with event generation Mask on Event input
19
1
EM2
Wakeup with event generation Mask on Event input
2
1
EM20
Wakeup with event generation Mask on Event input
20
1
EM21
Wakeup with event generation Mask on Event input
21
1
EM22
Wakeup with event generation Mask on Event input
22
1
EM3
Wakeup with event generation Mask on Event input
3
1
EM4
Wakeup with event generation Mask on Event input
4
1
EM5
Wakeup with event generation Mask on Event input
5
1
EM6
Wakeup with event generation Mask on Event input
6
1
EM7
Wakeup with event generation Mask on Event input
7
1
EM8
Wakeup with event generation Mask on Event input
8
1
EM9
Wakeup with event generation Mask on Event input
9
1
C1EMR2
C1EMR2
wakeup with event mask register
0x94
32
read-write
n
0x0
0x0
EM40
Wakeup with event generation Mask on Event input
8
1
EM41
Wakeup with event generation Mask on Event input
9
1
C1IMR1
C1IMR1
interrupt mask register
0x80
32
read-write
n
0x0
0x0
IM
wakeup with interrupt Mask on event input
0
32
C1IMR2
C1IMR2
wakeup with interrupt mask register
0x90
32
read-write
n
0x0
0x0
IM34
wakeup with interrupt mask on event input
2
1
IM36
wakeup with interrupt mask on event input
4
1
IM37
wakeup with interrupt mask on event input
5
1
IM38
wakeup with interrupt mask on event input
6
1
IM39
wakeup with interrupt mask on event input
7
1
IM40
wakeup with interrupt mask on event input
8
1
IM41
wakeup with interrupt mask on event input
9
1
IM42
wakeup with interrupt mask on event input
10
1
IM43
wakeup with interrupt mask on event input
11
1
IM44
wakeup with interrupt mask on event input
12
1
IM45
wakeup with interrupt mask on event input
13
1
IM46
wakeup with interrupt mask on event input
14
1
C2EMR1
C2EMR1
event mask register
0xC4
32
read-write
n
0x0
0x0
EM0
Wakeup with event generation Mask on Event input
0
1
EM1
Wakeup with event generation Mask on Event input
1
1
EM10
Wakeup with event generation Mask on Event input
10
1
EM11
Wakeup with event generation Mask on Event input
11
1
EM12
Wakeup with event generation Mask on Event input
12
1
EM13
Wakeup with event generation Mask on Event input
13
1
EM14
Wakeup with event generation Mask on Event input
14
1
EM15
Wakeup with event generation Mask on Event input
15
1
EM17
Wakeup with event generation Mask on Event input
17
1
EM18
Wakeup with event generation Mask on Event input
18
1
EM19
Wakeup with event generation Mask on Event input
19
1
EM2
Wakeup with event generation Mask on Event input
2
1
EM20
Wakeup with event generation Mask on Event input
20
1
EM21
Wakeup with event generation Mask on Event input
21
1
EM22
Wakeup with event generation Mask on Event input
22
1
EM3
Wakeup with event generation Mask on Event input
3
1
EM4
Wakeup with event generation Mask on Event input
4
1
EM5
Wakeup with event generation Mask on Event input
5
1
EM6
Wakeup with event generation Mask on Event input
6
1
EM7
Wakeup with event generation Mask on Event input
7
1
EM8
Wakeup with event generation Mask on Event input
8
1
EM9
Wakeup with event generation Mask on Event input
9
1
C2EMR2
C2EMR2
wakeup with event mask register
0xD4
32
read-write
n
0x0
0x0
EM40
Wakeup with event generation Mask on Event input
8
1
EM41
Wakeup with event generation Mask on Event input
9
1
C2IMR1
C2IMR1
interrupt mask register
0xC0
32
read-write
n
0x0
0x0
IM
wakeup with interrupt Mask on Event input
0
32
C2IMR2
C2IMR2
wakeup with interrupt mask register
0xD0
32
read-write
n
0x0
0x0
IM34
wakeup with interrupt mask on event input
2
1
IM36
wakeup with interrupt mask on event input
4
1
IM37
wakeup with interrupt mask on event input
5
1
IM38
wakeup with interrupt mask on event input
6
1
IM39
wakeup with interrupt mask on event input
7
1
IM40
wakeup with interrupt mask on event input
8
1
IM41
wakeup with interrupt mask on event input
9
1
IM42
wakeup with interrupt mask on event input
10
1
IM43
wakeup with interrupt mask on event input
11
1
IM44
wakeup with interrupt mask on event input
12
1
IM45
wakeup with interrupt mask on event input
13
1
IM46
wakeup with interrupt mask on event input
14
1
FTSR1
FTSR1
falling trigger selection register
0x4
32
read-write
n
0x0
0x0
FT
Falling trigger event configuration bit of Configurable Event input
0
17
FT21
Falling trigger event configuration bit of Configurable Event input
21
2
FTSR2
FTSR2
falling trigger selection register
0x24
32
read-write
n
0x0
0x0
FT34
Falling trigger event configuration bit of Configurable Event input
2
1
FT40
Falling trigger event configuration bit of Configurable Event input
8
1
FT41
Falling trigger event configuration bit of Configurable Event input
9
1
FT45
Falling trigger event configuration bit of Configurable Event input
13
1
PR1
PR1
EXTI pending register
0xC
32
read-write
n
0x0
0x0
PIF
Configurable event inputs Pending bit
0
17
PIF21
Configurable event inputs Pending bit
21
2
PR2
PR2
pending register
0x2C
32
read-write
n
0x0
0x0
PIF34
Configurable event inputs 33 Pending bit.
2
1
PIF40
Configurable event inputs 40_41 Pending bit.
8
1
PIF41
Configurable event inputs 40_41 Pending bit.
9
1
PIF45
Configurable event inputs 45 Pending bit.
13
1
RTSR1
RTSR1
rising trigger selection register
0x0
32
read-write
n
0x0
0x0
RT
Rising trigger event configuration bit of Configurable Event input
0
17
RT21
Rising trigger event configuration bit of Configurable Event input
21
2
RTSR2
RTSR2
rising trigger selection register
0x20
32
read-write
n
0x0
0x0
RT34
Rising trigger event configuration bit of Configurable Event input
2
1
RT40
Rising trigger event configuration bit of Configurable Event input
8
1
RT41
Rising trigger event configuration bit of Configurable Event input
9
1
RT45
Rising trigger event configuration bit of Configurable Event input
13
1
SWIER1
SWIER1
software interrupt event register
0x8
32
read-write
n
0x0
0x0
SWI
Software interrupt on event
0
17
SWI21
Software interrupt on event
21
2
SWIER2
SWIER2
software interrupt event register
0x28
32
read-write
n
0x0
0x0
SWI34
Software interrupt on event
2
1
SWI40
Software interrupt on event
8
1
SWI41
Software interrupt on event
9
1
SWI45
Software interrupt on event 45
13
1
FLASH
Flash
Flash
0x0
0x0
0x400
registers
n
FLASH_RCC_C1SEV
Flash memory global interrupt and Flash memory ECC single error interrupt,RCC global interrupt,CPU1 SEV through EXTI
3
ACR
ACR
Access control register
0x0
32
read-write
n
0x0
0x0
DCEN
Data cache enable
10
1
DCRST
Data cache reset
12
1
EMPTY
Flash User area empty
16
1
ICEN
Instruction cache enable
9
1
ICRST
Instruction cache reset
11
1
LATENCY
Latency
0
3
PES
CPU1 programm erase suspend request
15
1
PRFTEN
Prefetch enable
8
1
ACR2
ACR2
Flash access control register 2
0x4
32
read-write
n
0x0
0x0
C2SWDBGEN
CPU2 Software debug enable
2
1
HDPADIS
Flash user hide protection area access disable
1
1
PRIVMODE
CFI privileged mode enable
0
1
C2ACR
C2ACR
Flash CPU2 access control register
0x5C
32
read-write
n
0x0
0x0
ICEN
CPU2 Instruction cache enable
9
1
ICRST
CPU2 Instruction cache reset
11
1
PES
CPU2 program / erase suspend request
15
1
PRFTEN
CPU2 Prefetch enable
8
1
C2CR
C2CR
Flash CPU2 control register
0x64
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
24
1
ERRIE
Error interrupt enable
25
1
FSTPG
Fast programming
18
1
MER
Mass erase
2
1
PER
Page erase
1
1
PG
Programming
0
1
PNB
Page number selection
3
7
RDERRIE
RDERRIE
26
1
STRT
Start
16
1
C2SR
C2SR
Flash CPU2 status register
0x60
32
read-write
n
0x0
0x0
BSY
BSY
16
1
read-only
CFGBSY
CFGBSY
18
1
read-only
EOP
End of operation
0
1
read-write
FASTERR
Fast programming error
9
1
read-write
MISERR
Fast programming data miss error
8
1
read-write
OPERR
Operation error
1
1
read-write
PESD
PESD
19
1
read-only
PGAERR
PGAERR
5
1
read-write
PGSERR
Programming sequence error
7
1
read-write
PROGERR
Programming error
3
1
read-write
RDERR
PCROP read error
14
1
read-write
SIZERR
Size error
6
1
read-write
WRPERR
WRPERR
4
1
read-write
CR
CR
Flash control register
0x14
32
read-write
n
0x0
0x0
EOPIE
End of operation interrupt enable
24
1
ERRIE
Error interrupt enable
25
1
FSTPG
Fast programming
18
1
LOCK
FLASH_CR Lock
31
1
MER
Mass erase
2
1
OBL_LAUNCH
Force the option byte loading
27
1
OPTLOCK
Options Lock
30
1
OPTSTRT
Options modification start
17
1
PER
Page erase
1
1
PG
Programming
0
1
PNB
Page number
3
7
RDERRIE
PCROP read error interrupt enable
26
1
STRT
Start
16
1
ECCR
ECCR
Flash ECC register
0x18
32
read-write
n
0x0
0x0
ADDR_ECC
ECC fail address
0
17
read-only
CPUID
CPU identification
26
3
read-only
ECCC
ECC correction
30
1
read-write
ECCCIE
ECC correction interrupt enable
24
1
read-write
ECCD
ECC detection
31
1
read-write
SYSF_ECC
System Flash ECC fail
20
1
read-only
IPCCBR
IPCCBR
Flash IPCC data buffer address register
0x3C
32
read-write
n
0x0
0x0
IPCCDBA
IPCCDBA
0
14
KEYR
KEYR
Flash key register
0x8
32
write-only
n
0x0
0x0
KEY
KEY
0
32
OPTKEYR
OPTKEYR
Option byte key register
0xC
32
write-only
n
0x0
0x0
OPTKEY
Option byte key
0
32
OPTR
OPTR
Flash option register
0x20
32
read-write
n
0x0
0x0
BOOT_LOCK
CPU1 CM4 Unique Boot entry enable option bit
30
1
BOR_LEV
BOR reset Level
9
3
C2BOOT_LOCK
CPU2 CM0+ Unique Boot entry enable option bit
31
1
ESE
System security enabled flag
8
1
IWDG_STDBY
Independent watchdog counter freeze in Standby mode
18
1
IWDG_STOP
Independent watchdog counter freeze in Stop mode
17
1
IWDG_SW
Independent watchdog selection
16
1
nBOOT0
nBOOT0 option bit
27
1
nBOOT1
Boot configuration
23
1
nRST_SHDW
nRSTSHDW
14
1
nRST_STDBY
nRST_STDBY
13
1
nRST_STOP
nRST_STOP
12
1
nSWBOOT0
Software BOOT0 selection
26
1
RDP
Read protection level
0
8
SRAM2_PE
SRAM2 parity check enable
24
1
SRAM2_RST
SRAM2 Erase when system reset
25
1
WWDG_SW
Window watchdog selection
19
1
PCROP1AER
PCROP1AER
Flash PCROP zone A End address register
0x28
32
read-write
n
0x0
0x0
PCROP1A_END
PCROP area end offset
0
8
read-write
PCROP_RDP
PCROP area preserved when RDP level decreased
31
1
read-write
PCROP1ASR
PCROP1ASR
Flash PCROP zone A Start address register
0x24
32
read-write
n
0x0
0x0
PCROP1A_STRT
PCROP1A area start offset
0
8
PCROP1BER
PCROP1BER
Flash PCROP zone B End address register
0x38
32
read-write
n
0x0
0x0
PCROP1B_END
PCROP1B area end offset
0
8
PCROP1BSR
PCROP1BSR
Flash PCROP zone B Start address register
0x34
32
read-write
n
0x0
0x0
PCROP1B_STRT
Bank 1 WRP second area B end offset
0
8
SFR
SFR
Flash secure Flash start address register
0x80
32
read-write
n
0x0
0x0
DDS
DDS
12
1
FSD
Flash security disabled
7
1
HDPAD
User Flash hide protection area disabled
23
1
HDPSA
User Flash hide protection area start address
16
7
SFSA
Secure Flash start address
0
7
SUBGHSPISD
sub-GHz radio SPI security disable
31
1
SR
SR
Status register
0x10
32
read-write
n
0x0
0x0
BSY
Busy
16
1
read-only
CFGBSY
Programming or erase configuration busy
18
1
read-only
EOP
End of operation
0
1
read-write
FASTERR
Fast programming error
9
1
read-write
MISERR
Fast programming data miss error
8
1
read-write
OPERR
Operation error
1
1
read-write
OPTVERR
Option validity error
15
1
read-write
OPTVN
User Option OPTIVAL indication
13
1
read-only
PESD
Programming / erase operation suspended
19
1
read-only
PGAERR
Programming alignment error
5
1
read-write
PGSERR
Programming sequence error
7
1
read-write
PROGERR
Programming error
3
1
read-write
RDERR
PCROP read error
14
1
read-write
SIZERR
Size error
6
1
read-write
WRPERR
Write protected error
4
1
read-write
SRRVR
SRRVR
Flash secure SRAM start address and CPU2 reset vector register
0x84
32
read-write
n
0x0
0x0
BRSD
backup SRAM2 security disable
23
1
C2OPT
C2OPT
31
1
NBRSD
NBRSD
30
1
SBRSA
Secure backup SRAM2 start address
18
5
SBRV
CPU2 boot reset vector
0
16
SNBRSA
Secure non-backup SRAM1 start address
25
5
WRP1AR
WRP1AR
Flash WRP area A address register
0x2C
32
read-write
n
0x0
0x0
WRP1A_END
Bank 1 WRP first area A end offset
16
7
WRP1A_STRT
Bank 1 WRP first area start offset
0
7
WRP1BR
WRP1BR
Flash WRP area B address register
0x30
32
read-write
n
0x0
0x0
WRP1B_END
Bank 1 WRP second area B start offset
16
7
WRP1B_STRT
Bank 1 WRP second area B end offset
0
7
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
read-write
n
0x0
0x0
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
MODER0
0
2
MODER1
MODER1
2
2
MODER10
MODER10
20
2
MODER11
MODER11
22
2
MODER12
MODER12
24
2
MODER13
MODER13
26
2
MODER14
MODER14
28
2
MODER15
MODER15
30
2
MODER2
MODER2
4
2
MODER3
MODER3
6
2
MODER4
MODER4
8
2
MODER5
MODER5
10
2
MODER6
MODER6
12
2
MODER7
MODER7
14
2
MODER8
MODER8
16
2
MODER9
MODER9
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
read-write
n
0x0
0x0
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR10
Port Reset bit
10
1
BR11
Port Reset bit
11
1
BR12
Port Reset bit
12
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BR7
Port Reset bit
7
1
BR8
Port Reset bit
8
1
BR9
Port Reset bit
9
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR10
Port x reset bit y (y = 0..15)
26
1
BR11
Port x reset bit y (y = 0..15)
27
1
BR12
Port x reset bit y (y = 0..15)
28
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BR7
Port x reset bit y (y = 0..15)
23
1
BR8
Port x reset bit y (y = 0..15)
24
1
BR9
Port x reset bit y (y = 0..15)
25
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS10
Port x set bit y (y= 0..15)
10
1
BS11
Port x set bit y (y= 0..15)
11
1
BS12
Port x set bit y (y= 0..15)
12
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
BS7
Port x set bit y (y= 0..15)
7
1
BS8
Port x set bit y (y= 0..15)
8
1
BS9
Port x set bit y (y= 0..15)
9
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR10
Port input data (y = 0..15)
10
1
IDR11
Port input data (y = 0..15)
11
1
IDR12
Port input data (y = 0..15)
12
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
IDR7
Port input data (y = 0..15)
7
1
IDR8
Port input data (y = 0..15)
8
1
IDR9
Port input data (y = 0..15)
9
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK10
Port x lock bit y (y= 0..15)
10
1
LCK11
Port x lock bit y (y= 0..15)
11
1
LCK12
Port x lock bit y (y= 0..15)
12
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCK7
Port x lock bit y (y= 0..15)
7
1
LCK8
Port x lock bit y (y= 0..15)
8
1
LCK9
Port x lock bit y (y= 0..15)
9
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER10
Port x configuration bits (y = 0..15)
20
2
MODER11
Port x configuration bits (y = 0..15)
22
2
MODER12
Port x configuration bits (y = 0..15)
24
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
MODER7
Port x configuration bits (y = 0..15)
14
2
MODER8
Port x configuration bits (y = 0..15)
16
2
MODER9
Port x configuration bits (y = 0..15)
18
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR10
Port output data (y = 0..15)
10
1
ODR11
Port output data (y = 0..15)
11
1
ODR12
Port output data (y = 0..15)
12
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
ODR7
Port output data (y = 0..15)
7
1
ODR8
Port output data (y = 0..15)
8
1
ODR9
Port output data (y = 0..15)
9
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR10
Port x configuration bits (y = 0..15)
20
2
OSPEEDR11
Port x configuration bits (y = 0..15)
22
2
OSPEEDR12
Port x configuration bits (y = 0..15)
24
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OSPEEDR7
Port x configuration bits (y = 0..15)
14
2
OSPEEDR8
Port x configuration bits (y = 0..15)
16
2
OSPEEDR9
Port x configuration bits (y = 0..15)
18
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT10
Port x configuration bits (y = 0..15)
10
1
OT11
Port x configuration bits (y = 0..15)
11
1
OT12
Port x configuration bits (y = 0..15)
12
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
OT7
Port x configuration bits (y = 0..15)
7
1
OT8
Port x configuration bits (y = 0..15)
8
1
OT9
Port x configuration bits (y = 0..15)
9
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR10
Port x configuration bits (y = 0..15)
20
2
PUPDR11
Port x configuration bits (y = 0..15)
22
2
PUPDR12
Port x configuration bits (y = 0..15)
24
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
PUPDR7
Port x configuration bits (y = 0..15)
14
2
PUPDR8
Port x configuration bits (y = 0..15)
16
2
PUPDR9
Port x configuration bits (y = 0..15)
18
2
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL0
Alternate function selection for port x bit y (y = 0..7)
0
4
AFRL1
Alternate function selection for port x bit y (y = 0..7)
4
4
AFRL2
Alternate function selection for port x bit y (y = 0..7)
8
4
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
AFRL4
Alternate function selection for port x bit y (y = 0..7)
16
4
AFRL5
Alternate function selection for port x bit y (y = 0..7)
20
4
AFRL6
Alternate function selection for port x bit y (y = 0..7)
24
4
AFRL7
Alternate function selection for port x bit y (y = 0..7)
28
4
BRR
BRR
GPIO port bit reset register
0x28
32
read-write
n
0x0
0x0
BR0
Port Reset bit
0
1
BR1
Port Reset bit
1
1
BR13
Port Reset bit
13
1
BR14
Port Reset bit
14
1
BR15
Port Reset bit
15
1
BR2
Port Reset bit
2
1
BR3
Port Reset bit
3
1
BR4
Port Reset bit
4
1
BR5
Port Reset bit
5
1
BR6
Port Reset bit
6
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR0
Port x set bit y (y= 0..15)
16
1
BR1
Port x reset bit y (y = 0..15)
17
1
BR13
Port x reset bit y (y = 0..15)
29
1
BR14
Port x reset bit y (y = 0..15)
30
1
BR15
Port x reset bit y (y = 0..15)
31
1
BR2
Port x reset bit y (y = 0..15)
18
1
BR3
Port x reset bit y (y = 0..15)
19
1
BR4
Port x reset bit y (y = 0..15)
20
1
BR5
Port x reset bit y (y = 0..15)
21
1
BR6
Port x reset bit y (y = 0..15)
22
1
BS0
Port x set bit y (y= 0..15)
0
1
BS1
Port x set bit y (y= 0..15)
1
1
BS13
Port x set bit y (y= 0..15)
13
1
BS14
Port x set bit y (y= 0..15)
14
1
BS15
Port x set bit y (y= 0..15)
15
1
BS2
Port x set bit y (y= 0..15)
2
1
BS3
Port x set bit y (y= 0..15)
3
1
BS4
Port x set bit y (y= 0..15)
4
1
BS5
Port x set bit y (y= 0..15)
5
1
BS6
Port x set bit y (y= 0..15)
6
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR0
Port input data (y = 0..15)
0
1
IDR1
Port input data (y = 0..15)
1
1
IDR13
Port input data (y = 0..15)
13
1
IDR14
Port input data (y = 0..15)
14
1
IDR15
Port input data (y = 0..15)
15
1
IDR2
Port input data (y = 0..15)
2
1
IDR3
Port input data (y = 0..15)
3
1
IDR4
Port input data (y = 0..15)
4
1
IDR5
Port input data (y = 0..15)
5
1
IDR6
Port input data (y = 0..15)
6
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK0
Port x lock bit y (y= 0..15)
0
1
LCK1
Port x lock bit y (y= 0..15)
1
1
LCK13
Port x lock bit y (y= 0..15)
13
1
LCK14
Port x lock bit y (y= 0..15)
14
1
LCK15
Port x lock bit y (y= 0..15)
15
1
LCK2
Port x lock bit y (y= 0..15)
2
1
LCK3
Port x lock bit y (y= 0..15)
3
1
LCK4
Port x lock bit y (y= 0..15)
4
1
LCK5
Port x lock bit y (y= 0..15)
5
1
LCK6
Port x lock bit y (y= 0..15)
6
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER0
Port x configuration bits (y = 0..15)
0
2
MODER1
Port x configuration bits (y = 0..15)
2
2
MODER13
Port x configuration bits (y = 0..15)
26
2
MODER14
Port x configuration bits (y = 0..15)
28
2
MODER15
Port x configuration bits (y = 0..15)
30
2
MODER2
Port x configuration bits (y = 0..15)
4
2
MODER3
Port x configuration bits (y = 0..15)
6
2
MODER4
Port x configuration bits (y = 0..15)
8
2
MODER5
Port x configuration bits (y = 0..15)
10
2
MODER6
Port x configuration bits (y = 0..15)
12
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR0
Port output data (y = 0..15)
0
1
ODR1
Port output data (y = 0..15)
1
1
ODR13
Port output data (y = 0..15)
13
1
ODR14
Port output data (y = 0..15)
14
1
ODR15
Port output data (y = 0..15)
15
1
ODR2
Port output data (y = 0..15)
2
1
ODR3
Port output data (y = 0..15)
3
1
ODR4
Port output data (y = 0..15)
4
1
ODR5
Port output data (y = 0..15)
5
1
ODR6
Port output data (y = 0..15)
6
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR0
Port x configuration bits (y = 0..15)
0
2
OSPEEDR1
Port x configuration bits (y = 0..15)
2
2
OSPEEDR13
Port x configuration bits (y = 0..15)
26
2
OSPEEDR14
Port x configuration bits (y = 0..15)
28
2
OSPEEDR15
Port x configuration bits (y = 0..15)
30
2
OSPEEDR2
Port x configuration bits (y = 0..15)
4
2
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OSPEEDR4
Port x configuration bits (y = 0..15)
8
2
OSPEEDR5
Port x configuration bits (y = 0..15)
10
2
OSPEEDR6
Port x configuration bits (y = 0..15)
12
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT0
Port x configuration bits (y = 0..15)
0
1
OT1
Port x configuration bits (y = 0..15)
1
1
OT13
Port x configuration bits (y = 0..15)
13
1
OT14
Port x configuration bits (y = 0..15)
14
1
OT15
Port x configuration bits (y = 0..15)
15
1
OT2
Port x configuration bits (y = 0..15)
2
1
OT3
Port x configuration bits (y = 0..15)
3
1
OT4
Port x configuration bits (y = 0..15)
4
1
OT5
Port x configuration bits (y = 0..15)
5
1
OT6
Port x configuration bits (y = 0..15)
6
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR0
Port x configuration bits (y = 0..15)
0
2
PUPDR1
Port x configuration bits (y = 0..15)
2
2
PUPDR13
Port x configuration bits (y = 0..15)
26
2
PUPDR14
Port x configuration bits (y = 0..15)
28
2
PUPDR15
Port x configuration bits (y = 0..15)
30
2
PUPDR2
Port x configuration bits (y = 0..15)
4
2
PUPDR3
Port x configuration bits (y = 0..15)
6
2
PUPDR4
Port x configuration bits (y = 0..15)
8
2
PUPDR5
Port x configuration bits (y = 0..15)
10
2
PUPDR6
Port x configuration bits (y = 0..15)
12
2
GPIOH
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFRH
AFRH
GPIO alternate function high register
0x24
32
read-write
n
0x0
0x0
AFRH10
Alternate function selection for port x bit y (y = 8..15)
8
4
AFRH11
Alternate function selection for port x bit y (y = 8..15)
12
4
AFRH12
Alternate function selection for port x bit y (y = 8..15)
16
4
AFRH13
Alternate function selection for port x bit y (y = 8..15)
20
4
AFRH14
Alternate function selection for port x bit y (y = 8..15)
24
4
AFRH15
Alternate function selection for port x bit y (y = 8..15)
28
4
AFRH8
Alternate function selection for port x bit y (y = 8..15)
0
4
AFRH9
Alternate function selection for port x bit y (y = 8..15)
4
4
AFRL
AFRL
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
AFRL3
Alternate function selection for port x bit y (y = 0..7)
12
4
BRR
BRR
GPIO port bit reset register
0x28
32
read-write
n
0x0
0x0
BR3
Port Reset bit
3
1
BSRR
BSRR
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BR3
Port x reset bit y (y = 0..15)
19
1
BS3
Port x set bit y (y= 0..15)
3
1
IDR
IDR
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
IDR3
Port input data (y = 0..15)
3
1
LCKR
LCKR
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LCK3
Port x lock bit y (y= 0..15)
3
1
LCKK
Port x lock bit y (y= 0..15)
16
1
MODER
MODER
GPIO port mode register
0x0
32
read-write
n
0x0
0x0
MODER3
Port x configuration bits (y = 0..15)
6
2
ODR
ODR
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
ODR3
Port output data (y = 0..15)
3
1
OSPEEDR
OSPEEDR
GPIO port output speed register
0x8
32
read-write
n
0x0
0x0
OSPEEDR3
Port x configuration bits (y = 0..15)
6
2
OTYPER
OTYPER
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OT3
Port x configuration bits (y = 0..15)
3
1
PUPDR
PUPDR
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUPDR3
Port x configuration bits (y = 0..15)
6
2
HSEM
Hardware semaphore
HSEM
0x0
0x0
0x400
registers
n
HSEM
Semaphore interrupt 1 to CPU2
19
C1ICR
HSEM_C1ICR
HSEM Interrupt clear register
0x104
32
read-write
n
0x0
0x0
ISC0
Interrupt(N) semaphore n clear bit
0
1
ISC1
Interrupt(N) semaphore n clear bit
1
1
ISC10
Interrupt(N) semaphore n clear bit
10
1
ISC11
Interrupt(N) semaphore n clear bit
11
1
ISC12
Interrupt(N) semaphore n clear bit
12
1
ISC13
Interrupt(N) semaphore n clear bit
13
1
ISC14
Interrupt(N) semaphore n clear bit
14
1
ISC15
Interrupt(N) semaphore n clear bit
15
1
ISC2
Interrupt(N) semaphore n clear bit
2
1
ISC3
Interrupt(N) semaphore n clear bit
3
1
ISC4
Interrupt(N) semaphore n clear bit
4
1
ISC5
Interrupt(N) semaphore n clear bit
5
1
ISC6
Interrupt(N) semaphore n clear bit
6
1
ISC7
Interrupt(N) semaphore n clear bit
7
1
ISC8
Interrupt(N) semaphore n clear bit
8
1
ISC9
Interrupt(N) semaphore n clear bit
9
1
C1IER
HSEM_C1IER
HSEM Interrupt enable register
0x100
32
read-write
n
0x0
0x0
ISE0
Interrupt semaphore n enable bit
0
1
ISE1
Interrupt semaphore n enable bit
1
1
ISE10
Interrupt semaphore n enable bit
10
1
ISE11
Interrupt semaphore n enable bit
11
1
ISE12
Interrupt semaphore n enable bit
12
1
ISE13
Interrupt semaphore n enable bit
13
1
ISE14
Interrupt semaphore n enable bit
14
1
ISE15
Interrupt semaphore n enable bit
15
1
ISE2
Interrupt semaphore n enable bit
2
1
ISE3
Interrupt semaphore n enable bit
3
1
ISE4
Interrupt semaphore n enable bit
4
1
ISE5
Interrupt semaphore n enable bit
5
1
ISE6
Interrupt semaphore n enable bit
6
1
ISE7
Interrupt semaphore n enable bit
7
1
ISE8
Interrupt semaphore n enable bit
8
1
ISE9
Interrupt semaphore n enable bit
9
1
C1ISR
HSEM_C1ISR
HSEM Interrupt status register
0x108
32
read-only
n
0x0
0x0
ISF0
Interrupt(N) semaphore n status bit before enable (mask)
0
1
ISF1
Interrupt(N) semaphore n status bit before enable (mask)
1
1
ISF10
Interrupt(N) semaphore n status bit before enable (mask)
10
1
ISF11
Interrupt(N) semaphore n status bit before enable (mask)
11
1
ISF12
Interrupt(N) semaphore n status bit before enable (mask)
12
1
ISF13
Interrupt(N) semaphore n status bit before enable (mask)
13
1
ISF14
Interrupt(N) semaphore n status bit before enable (mask)
14
1
ISF15
Interrupt(N) semaphore n status bit before enable (mask)
15
1
ISF2
Interrupt(N) semaphore n status bit before enable (mask)
2
1
ISF3
Interrupt(N) semaphore n status bit before enable (mask)
3
1
ISF4
Interrupt(N) semaphore n status bit before enable (mask)
4
1
ISF5
Interrupt(N) semaphore n status bit before enable (mask)
5
1
ISF6
Interrupt(N) semaphore n status bit before enable (mask)
6
1
ISF7
Interrupt(N) semaphore n status bit before enable (mask)
7
1
ISF8
Interrupt(N) semaphore n status bit before enable (mask)
8
1
ISF9
Interrupt(N) semaphore n status bit before enable (mask)
9
1
C1MISR
HSEM_C1MISR
HSEM Masked interrupt status register
0x10C
32
read-only
n
0x0
0x0
MISF0
masked interrupt(N) semaphore n status bit after enable (mask)
0
1
MISF1
masked interrupt(N) semaphore n status bit after enable (mask)
1
1
MISF10
masked interrupt(N) semaphore n status bit after enable (mask)
10
1
MISF11
masked interrupt(N) semaphore n status bit after enable (mask)
11
1
MISF12
masked interrupt(N) semaphore n status bit after enable (mask)
12
1
MISF13
masked interrupt(N) semaphore n status bit after enable (mask)
13
1
MISF14
masked interrupt(N) semaphore n status bit after enable (mask)
14
1
MISF15
masked interrupt(N) semaphore n status bit after enable (mask)
15
1
MISF2
masked interrupt(N) semaphore n status bit after enable (mask)
2
1
MISF3
masked interrupt(N) semaphore n status bit after enable (mask)
3
1
MISF4
masked interrupt(N) semaphore n status bit after enable (mask)
4
1
MISF5
masked interrupt(N) semaphore n status bit after enable (mask)
5
1
MISF6
masked interrupt(N) semaphore n status bit after enable (mask)
6
1
MISF7
masked interrupt(N) semaphore n status bit after enable (mask)
7
1
MISF8
masked interrupt(N) semaphore n status bit after enable (mask)
8
1
MISF9
masked interrupt(N) semaphore n status bit after enable (mask)
9
1
C2ICR
HSEM_C2ICR
HSEM Interrupt clear register
0x114
32
read-only
n
0x0
0x0
ISC0
Interrupt(N) semaphore n clear bit
0
1
ISC1
Interrupt(N) semaphore n clear bit
1
1
ISC10
Interrupt(N) semaphore n clear bit
10
1
ISC11
Interrupt(N) semaphore n clear bit
11
1
ISC12
Interrupt(N) semaphore n clear bit
12
1
ISC13
Interrupt(N) semaphore n clear bit
13
1
ISC14
Interrupt(N) semaphore n clear bit
14
1
ISC15
Interrupt(N) semaphore n clear bit
15
1
ISC2
Interrupt(N) semaphore n clear bit
2
1
ISC3
Interrupt(N) semaphore n clear bit
3
1
ISC4
Interrupt(N) semaphore n clear bit
4
1
ISC5
Interrupt(N) semaphore n clear bit
5
1
ISC6
Interrupt(N) semaphore n clear bit
6
1
ISC7
Interrupt(N) semaphore n clear bit
7
1
ISC8
Interrupt(N) semaphore n clear bit
8
1
ISC9
Interrupt(N) semaphore n clear bit
9
1
C2IER
HSEM_C2IER
HSEM Interrupt enable register
0x110
32
read-write
n
0x0
0x0
ISE0
Interrupt semaphore n enable bit
0
1
ISE1
Interrupt semaphore n enable bit
1
1
ISE10
Interrupt semaphore n enable bit
10
1
ISE11
Interrupt semaphore n enable bit
11
1
ISE12
Interrupt semaphore n enable bit
12
1
ISE13
Interrupt semaphore n enable bit
13
1
ISE14
Interrupt semaphore n enable bit
14
1
ISE15
Interrupt semaphore n enable bit
15
1
ISE2
Interrupt semaphore n enable bit
2
1
ISE3
Interrupt semaphore n enable bit
3
1
ISE4
Interrupt semaphore n enable bit
4
1
ISE5
Interrupt semaphore n enable bit
5
1
ISE6
Interrupt semaphore n enable bit
6
1
ISE7
Interrupt semaphore n enable bit
7
1
ISE8
Interrupt semaphore n enable bit
8
1
ISE9
Interrupt semaphore n enable bit
9
1
C2ISR
HSEM_C2ISR
HSEM Interrupt status register
0x118
32
read-only
n
0x0
0x0
ISF0
Interrupt(N) semaphore n status bit before enable (mask)
0
1
ISF1
Interrupt(N) semaphore n status bit before enable (mask)
1
1
ISF10
Interrupt(N) semaphore n status bit before enable (mask)
10
1
ISF11
Interrupt(N) semaphore n status bit before enable (mask)
11
1
ISF12
Interrupt(N) semaphore n status bit before enable (mask)
12
1
ISF13
Interrupt(N) semaphore n status bit before enable (mask)
13
1
ISF14
Interrupt(N) semaphore n status bit before enable (mask)
14
1
ISF15
Interrupt(N) semaphore n status bit before enable (mask)
15
1
ISF2
Interrupt(N) semaphore n status bit before enable (mask)
2
1
ISF3
Interrupt(N) semaphore n status bit before enable (mask)
3
1
ISF4
Interrupt(N) semaphore n status bit before enable (mask)
4
1
ISF5
Interrupt(N) semaphore n status bit before enable (mask)
5
1
ISF6
Interrupt(N) semaphore n status bit before enable (mask)
6
1
ISF7
Interrupt(N) semaphore n status bit before enable (mask)
7
1
ISF8
Interrupt(N) semaphore n status bit before enable (mask)
8
1
ISF9
Interrupt(N) semaphore n status bit before enable (mask)
9
1
C2MISR
HSEM_C2MISR
HSEM Masked interrupt status register
0x11C
32
read-only
n
0x0
0x0
MISF0
masked interrupt(N) semaphore n status bit after enable (mask)
0
1
MISF1
masked interrupt(N) semaphore n status bit after enable (mask)
1
1
MISF10
masked interrupt(N) semaphore n status bit after enable (mask)
10
1
MISF11
masked interrupt(N) semaphore n status bit after enable (mask)
11
1
MISF12
masked interrupt(N) semaphore n status bit after enable (mask)
12
1
MISF13
masked interrupt(N) semaphore n status bit after enable (mask)
13
1
MISF14
masked interrupt(N) semaphore n status bit after enable (mask)
14
1
MISF15
masked interrupt(N) semaphore n status bit after enable (mask)
15
1
MISF2
masked interrupt(N) semaphore n status bit after enable (mask)
2
1
MISF3
masked interrupt(N) semaphore n status bit after enable (mask)
3
1
MISF4
masked interrupt(N) semaphore n status bit after enable (mask)
4
1
MISF5
masked interrupt(N) semaphore n status bit after enable (mask)
5
1
MISF6
masked interrupt(N) semaphore n status bit after enable (mask)
6
1
MISF7
masked interrupt(N) semaphore n status bit after enable (mask)
7
1
MISF8
masked interrupt(N) semaphore n status bit after enable (mask)
8
1
MISF9
masked interrupt(N) semaphore n status bit after enable (mask)
9
1
CR
HSEM_CR
HSEM Clear register
0x140
32
write-only
n
0x0
0x0
COREID
COREID
8
4
KEY
Semaphore clear Key
16
16
KEYR
HSEM_KEYR
HSEM Interrupt clear register
0x144
32
read-write
n
0x0
0x0
KEY
Semaphore Clear Key
16
16
R0
HSEM_R0
HSEM register HSEM_R0 HSEM_R31
0x0
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R1
HSEM_R1
HSEM register HSEM_R0 HSEM_R31
0x4
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R10
HSEM_R10
HSEM register HSEM_R0 HSEM_R31
0x28
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R11
HSEM_R11
HSEM register HSEM_R0 HSEM_R31
0x2C
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R12
HSEM_R12
HSEM register HSEM_R0 HSEM_R31
0x30
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R13
HSEM_R13
HSEM register HSEM_R0 HSEM_R31
0x34
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R14
HSEM_R14
HSEM register HSEM_R0 HSEM_R31
0x38
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R15
HSEM_R15
HSEM register HSEM_R0 HSEM_R31
0x3C
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R2
HSEM_R2
HSEM register HSEM_R0 HSEM_R31
0x8
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R3
HSEM_R3
HSEM register HSEM_R0 HSEM_R31
0xC
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R4
HSEM_R4
HSEM register HSEM_R0 HSEM_R31
0x10
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R5
HSEM_R5
HSEM register HSEM_R0 HSEM_R31
0x14
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R6
HSEM_R6
HSEM register HSEM_R0 HSEM_R31
0x18
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R7
HSEM_R7
HSEM register HSEM_R0 HSEM_R31
0x1C
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R8
HSEM_R8
HSEM register HSEM_R0 HSEM_R31
0x20
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
R9
HSEM_R9
HSEM register HSEM_R0 HSEM_R31
0x24
32
read-write
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR0
HSEM_RLR0
HSEM Read lock register
0x80
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR1
HSEM_RLR1
HSEM Read lock register
0x84
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR10
HSEM_RLR10
HSEM Read lock register
0xA8
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR11
HSEM_RLR11
HSEM Read lock register
0xAC
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR12
HSEM_RLR12
HSEM Read lock register
0xB0
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR13
HSEM_RLR13
HSEM Read lock register
0xB4
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR14
HSEM_RLR14
HSEM Read lock register
0xB8
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR15
HSEM_RLR15
HSEM Read lock register
0xBC
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR2
HSEM_RLR2
HSEM Read lock register
0x88
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR3
HSEM_RLR3
HSEM Read lock register
0x8C
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR4
HSEM_RLR4
HSEM Read lock register
0x90
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR5
HSEM_RLR5
HSEM Read lock register
0x94
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR6
HSEM_RLR6
HSEM Read lock register
0x98
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR7
HSEM_RLR7
HSEM Read lock register
0x9C
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR8
HSEM_RLR8
HSEM Read lock register
0xA0
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
RLR9
HSEM_RLR9
HSEM Read lock register
0xA4
32
read-only
n
0x0
0x0
COREID
COREID
8
4
LOCK
Lock indication
31
1
PROCID
Semaphore ProcessID
0
8
I2C1
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV_I2C1_ER
I2C1 event interrupt,I2C1 error interrupt
22
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
I2C2
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C2_EV_I2C2_ER
I2C2 event interrupt , I2C2 error interrupt
23
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
I2C3
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C3_EV_I2C3_ER
I2C3 event interrupt , I2C2 error interrupt
24
CR1
CR1
Control register 1
0x0
32
read-write
n
0x0
0x0
ADDRIE
Address match interrupt enable (slave only)
3
1
ALERTEN
SMBUS alert enable
22
1
ANFOFF
Analog noise filter OFF
12
1
DNF
Digital noise filter
8
4
ERRIE
Error interrupts enable
7
1
GCEN
General call enable
19
1
NACKIE
Not acknowledge received interrupt enable
4
1
NOSTRETCH
Clock stretching disable
17
1
PE
Peripheral enable
0
1
PECEN
PEC enable
23
1
RXDMAEN
DMA reception requests enable
15
1
RXIE
RX Interrupt enable
2
1
SBC
Slave byte control
16
1
SMBDEN
SMBus Device Default address enable
21
1
SMBHEN
SMBus Host address enable
20
1
STOPIE
STOP detection Interrupt enable
5
1
TCIE
Transfer Complete interrupt enable
6
1
TXDMAEN
DMA transmission requests enable
14
1
TXIE
TX Interrupt enable
1
1
WUPEN
Wakeup from STOP enable
18
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD10
10-bit addressing mode (master mode)
11
1
AUTOEND
Automatic end mode (master mode)
25
1
HEAD10R
10-bit address header only read direction (master receiver mode)
12
1
NACK
NACK generation (slave mode)
15
1
NBYTES
Number of bytes
16
8
PECBYTE
Packet error checking byte
26
1
RD_WRN
Transfer direction (master mode)
10
1
RELOAD
NBYTES reload mode
24
1
SADD
Slave address bit (master mode)
0
10
START
Start generation
13
1
STOP
Stop generation (master mode)
14
1
ICR
ICR
Interrupt clear register
0x1C
32
write-only
n
0x0
0x0
ADDRCF
Address Matched flag clear
3
1
ALERTCF
Alert flag clear
13
1
ARLOCF
Arbitration lost flag clear
9
1
BERRCF
Bus error flag clear
8
1
NACKCF
Not Acknowledge flag clear
4
1
OVRCF
Overrun/Underrun flag clear
10
1
PECCF
PEC Error flag clear
11
1
STOPCF
Stop detection flag clear
5
1
TIMOUTCF
Timeout detection flag clear
12
1
ISR
ISR
Interrupt and Status register
0x18
32
read-write
n
0x0
0x0
ADDCODE
Address match code (Slave mode)
17
7
read-only
ADDR
Address matched (slave mode)
3
1
read-only
ALERT
SMBus alert
13
1
read-only
ARLO
Arbitration lost
9
1
read-only
BERR
Bus error
8
1
read-only
BUSY
Bus busy
15
1
read-only
DIR
Transfer direction (Slave mode)
16
1
read-only
NACKF
Not acknowledge received flag
4
1
read-only
OVR
Overrun/Underrun (slave mode)
10
1
read-only
PECERR
PEC Error in reception
11
1
read-only
RXNE
Receive data register not empty (receivers)
2
1
read-only
STOPF
Stop detection flag
5
1
read-only
TC
Transfer Complete (master mode)
6
1
read-only
TCR
Transfer Complete Reload
7
1
read-only
TIMEOUT
Timeout or t_low detection flag
12
1
read-only
TXE
Transmit data register empty (transmitters)
0
1
read-write
TXIS
Transmit interrupt status (transmitters)
1
1
read-write
OAR1
OAR1
Own address register 1
0x8
32
read-write
n
0x0
0x0
OA1
Interface address
0
10
OA1EN
Own Address 1 enable
15
1
OA1MODE
Own Address 1 10-bit mode
10
1
OAR2
OAR2
Own address register 2
0xC
32
read-write
n
0x0
0x0
OA2
Interface address
1
7
OA2EN
Own Address 2 enable
15
1
OA2MSK
Own Address 2 masks
8
3
PECR
PECR
PEC register
0x20
32
read-only
n
0x0
0x0
PEC
Packet error checking register
0
8
RXDR
RXDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data
0
8
TIMEOUTR
TIMEOUTR
Status register 1
0x14
32
read-write
n
0x0
0x0
TEXTEN
Extended clock timeout enable
31
1
TIDLE
Idle clock timeout detection
12
1
TIMEOUTA
Bus timeout A
0
12
TIMEOUTB
Bus timeout B
16
12
TIMOUTEN
Clock timeout enable
15
1
TIMINGR
TIMINGR
Timing register
0x10
32
read-write
n
0x0
0x0
PRESC
Timing prescaler
28
4
SCLDEL
Data setup time
20
4
SCLH
SCL high period (master mode)
8
8
SCLL
SCL low period (master mode)
0
8
SDADEL
Data hold time
16
4
TXDR
TXDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
IPCC
Inter Processor communication controller
IPCC
0x0
0x0
0x400
registers
n
IPCC_C2_RX_IT_IPCC_C2_TX_IT
IPCC CPU2 RX occupied interrupt, IPCC CPU2 TX free interrupt
18
C1CR
IPCC_C1CR
IPCC Processor 1 control register
0x0
32
read-write
n
0x0
0x0
RXOIE
RXOIE
0
1
TXFIE
TXFIE
16
1
C1MR
IPCC_C1MR
IPCC Processor 1 mask register
0x4
32
read-write
n
0x0
0x0
CH1FM
CH1FM
16
1
CH1OM
CH1OM
0
1
CH2FM
CH2FM
17
1
CH2OM
CH2OM
1
1
CH3FM
CH3FM
18
1
CH3OM
CH3OM
2
1
CH4FM
CH4FM
19
1
CH4OM
CH4OM
3
1
CH5FM
CH5FM
20
1
CH5OM
CH5OM
4
1
CH6FM
CH6FM
21
1
CH6OM
CH6OM
5
1
C1SCR
IPCC_C1SCR
Reading this register will always return 0x0000 0000.
0x8
32
read-write
n
0x0
0x0
CH1C
CH1C
0
1
CH1S
CH1S
16
1
CH2C
CH2C
1
1
CH2S
CH2S
17
1
CH3C
CH3C
2
1
CH3S
CH3S
18
1
CH4C
CH4C
3
1
CH4S
CH4S
19
1
CH5C
CH5C
4
1
CH5S
CH5S
20
1
CH6C
CH6C
5
1
CH6S
CH6S
21
1
C1TOC2SR
IPCC_C1TOC2SR
IPCC processor 1 to processor 2 status register
0xC
32
read-only
n
0x0
0x0
CH1F
CH1F
0
1
CH2F
CH2F
1
1
CH3F
CH3F
2
1
CH4F
CH4F
3
1
CH5F
CH5F
4
1
CH6F
CH6F
5
1
C2CR
IPCC_C2CR
IPCC Processor 2 control register
0x10
32
read-write
n
0x0
0x0
RXOIE
RXOIE
0
1
TXFIE
TXFIE
16
1
C2MR
IPCC_C2MR
IPCC Processor 2 mask register
0x14
32
read-write
n
0x0
0x0
CH1FM
CH1FM
16
1
CH1OM
CH1OM
0
1
CH2FM
CH2FM
17
1
CH2OM
CH2OM
1
1
CH3FM
CH3FM
18
1
CH3OM
CH3OM
2
1
CH4FM
CH4FM
19
1
CH4OM
CH4OM
3
1
CH5FM
CH5FM
20
1
CH5OM
CH5OM
4
1
CH6FM
CH6FM
21
1
CH6OM
CH6OM
5
1
C2SCR
IPCC_C2SCR
Reading this register will always return 0x0000 0000.
0x18
32
read-write
n
0x0
0x0
CH1C
CH1C
0
1
CH1S
CH1S
16
1
CH2C
CH2C
1
1
CH2S
CH2S
17
1
CH3C
CH3C
2
1
CH3S
CH3S
18
1
CH4C
CH4C
3
1
CH4S
CH4S
19
1
CH5C
CH5C
4
1
CH5S
CH5S
20
1
CH6C
CH6C
5
1
CH6S
CH6S
21
1
C2TOC1SR
IPCC_C2TOC1SR
IPCC processor 2 to processor 1 status register
0x1C
32
read-only
n
0x0
0x0
CH1F
CH1F
0
1
CH2F
CH2F
1
1
CH3F
CH3F
2
1
CH4F
CH4F
3
1
CH5F
CH5F
4
1
CH6F
CH6F
5
1
HWCFGR
IPCC_HWCFGR
IPCC Hardware configuration register
0x3F0
32
read-only
n
0x0
0x0
CHANNELS
CHANNELS
0
8
IPIDR
IPCC_IPIDR
IPCC IP Identification register
0x3F8
32
read-only
n
0x0
0x0
ID
ID
0
32
SIDR
IPCC_SIDR
IPCC Size ID register
0x3FC
32
read-only
n
0x0
0x0
SID
SID
0
32
VERR
IPCC_VERR
IPCC IP Version register
0x3F4
32
read-only
n
0x0
0x0
MAJREV
MAJREV
4
4
MINREV
MINREV
0
4
IWDG
Independent watchdog
IWDG
0x0
0x0
0x400
registers
n
KR
KR
Key register
0x0
32
write-only
n
0x0
0x0
KEY
Key value (write only, read 0x0000)
0
16
PR
PR
Prescaler register
0x4
32
read-write
n
0x0
0x0
PR
Prescaler divider
0
3
RLR
RLR
Reload register
0x8
32
read-write
n
0x0
0x0
RL
Watchdog counter reload value
0
12
SR
SR
Status register
0xC
32
read-only
n
0x0
0x0
PVU
Watchdog prescaler value update
0
1
RVU
Watchdog counter reload value update
1
1
WVU
Watchdog counter window value update
2
1
WINR
WINR
Window register
0x10
32
read-write
n
0x0
0x0
WIN
Watchdog counter window value
0
12
LPTIM1
Low-power timer
LPTIM
0x0
0x0
0x400
registers
n
LPTIM1
LPtimer 1 global interrupt
11
ARR
ARR
autoreload register
0x18
32
read-write
n
0x0
0x0
ARR
Auto reload value
0
16
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0x0
CKFLT
CKFLT
3
2
CKPOL
CKPOL
1
2
CKSEL
CKSEL
0
1
COUNTMODE
COUNTMODE
23
1
ENC
ENC
24
1
PRELOAD
PRELOAD
22
1
PRESC
PRESC
9
3
TIMOUT
TIMOUT
19
1
TRGFLT
TRGFLT
6
2
TRIGEN
TRIGEN
17
2
TRIGSEL
TRIGSEL
13
3
WAVE
WAVE
20
1
WAVPOL
WAVPOL
21
1
CMP
CMP
compare register
0x14
32
read-write
n
0x0
0x0
CMP
CMP
0
16
CNT
CNT
counter register
0x1C
32
read-only
n
0x0
0x0
CNT
Counter value
0
16
CR
CR
control register
0x10
32
read-write
n
0x0
0x0
CNTSTRT
CNTSTRT
2
1
COUNTRST
COUNTRST
3
1
ENABLE
ENABLE
0
1
RSTARE
RSTARE
4
1
SNGSTRT
SNGSTRT
1
1
ICR
ICR
interrupt clear register
0x4
32
write-only
n
0x0
0x0
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
REPOKCF
Repetition register update OK clear flag
8
1
UECF
Update event clear flag
7
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
interrupt enable register
0x8
32
read-write
n
0x0
0x0
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
REPOKIE
Repetition register update OK interrupt Enable
8
1
UEIE
Update event interrupt enable
7
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
interrupt and status register
0x0
32
read-only
n
0x0
0x0
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
REPOK
Repetition register update Ok
8
1
UE
LPTIM update event occurred
7
1
UP
Counter direction change down to up
5
1
OR
LPTIM1_OR
option register
0x20
32
read-write
n
0x0
0x0
OR_0
Option register bit 0
0
1
OR_1
Option register bit 1
1
1
RCR
RCR
repetition register
0x28
32
read-write
n
0x0
0x0
REP
Repetition register value
0
8
LPTIM2
Low-power timer
LPTIM
0x0
0x0
0x400
registers
n
LPTIM2
LPtimer 2 global interrupt
12
ARR
ARR
autoreload register
0x18
32
read-write
n
0x0
0x0
ARR
Auto reload value
0
16
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0x0
CKFLT
CKFLT
3
2
CKPOL
CKPOL
1
2
CKSEL
CKSEL
0
1
COUNTMODE
COUNTMODE
23
1
ENC
ENC
24
1
PRELOAD
PRELOAD
22
1
PRESC
PRESC
9
3
TIMOUT
TIMOUT
19
1
TRGFLT
TRGFLT
6
2
TRIGEN
TRIGEN
17
2
TRIGSEL
TRIGSEL
13
3
WAVE
WAVE
20
1
WAVPOL
WAVPOL
21
1
CMP
CMP
compare register
0x14
32
read-write
n
0x0
0x0
CMP
CMP
0
16
CNT
CNT
counter register
0x1C
32
read-only
n
0x0
0x0
CNT
Counter value
0
16
CR
CR
control register
0x10
32
read-write
n
0x0
0x0
CNTSTRT
CNTSTRT
2
1
COUNTRST
COUNTRST
3
1
ENABLE
ENABLE
0
1
RSTARE
RSTARE
4
1
SNGSTRT
SNGSTRT
1
1
ICR
ICR
interrupt clear register
0x4
32
write-only
n
0x0
0x0
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
REPOKCF
Repetition register update OK clear flag
8
1
UECF
Update event clear flag
7
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
interrupt enable register
0x8
32
read-write
n
0x0
0x0
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
REPOKIE
Repetition register update OK interrupt Enable
8
1
UEIE
Update event interrupt enable
7
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
interrupt and status register
0x0
32
read-only
n
0x0
0x0
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
REPOK
Repetition register update Ok
8
1
UE
LPTIM update event occurred
7
1
UP
Counter direction change down to up
5
1
OR
LPTIM2_OR
option register
0x20
32
read-write
n
0x0
0x0
OR_0
Option register bit 0
0
1
OR_1
Option register bit 1
1
1
RCR
RCR
repetition register
0x28
32
read-write
n
0x0
0x0
REP
Repetition register value
0
8
LPTIM3
Low-power timer
LPTIM
0x0
0x0
0x400
registers
n
LPTIM3
LPtimer 3 global interrupt
13
ARR
ARR
autoreload register
0x18
32
read-write
n
0x0
0x0
ARR
Auto reload value
0
16
CFGR
CFGR
configuration register
0xC
32
read-write
n
0x0
0x0
CKFLT
CKFLT
3
2
CKPOL
CKPOL
1
2
CKSEL
CKSEL
0
1
COUNTMODE
COUNTMODE
23
1
ENC
ENC
24
1
PRELOAD
PRELOAD
22
1
PRESC
PRESC
9
3
TIMOUT
TIMOUT
19
1
TRGFLT
TRGFLT
6
2
TRIGEN
TRIGEN
17
2
TRIGSEL
TRIGSEL
13
3
WAVE
WAVE
20
1
WAVPOL
WAVPOL
21
1
CMP
CMP
compare register
0x14
32
read-write
n
0x0
0x0
CMP
CMP
0
16
CNT
CNT
counter register
0x1C
32
read-only
n
0x0
0x0
CNT
Counter value
0
16
CR
CR
control register
0x10
32
read-write
n
0x0
0x0
CNTSTRT
CNTSTRT
2
1
COUNTRST
COUNTRST
3
1
ENABLE
ENABLE
0
1
RSTARE
RSTARE
4
1
SNGSTRT
SNGSTRT
1
1
ICR
ICR
interrupt clear register
0x4
32
write-only
n
0x0
0x0
ARRMCF
Autoreload match Clear Flag
1
1
ARROKCF
Autoreload register update OK Clear Flag
4
1
CMPMCF
compare match Clear Flag
0
1
CMPOKCF
Compare register update OK Clear Flag
3
1
DOWNCF
Direction change to down Clear Flag
6
1
EXTTRIGCF
External trigger valid edge Clear Flag
2
1
REPOKCF
Repetition register update OK clear flag
8
1
UECF
Update event clear flag
7
1
UPCF
Direction change to UP Clear Flag
5
1
IER
IER
interrupt enable register
0x8
32
read-write
n
0x0
0x0
ARRMIE
Autoreload match Interrupt Enable
1
1
ARROKIE
Autoreload register update OK Interrupt Enable
4
1
CMPMIE
Compare match Interrupt Enable
0
1
CMPOKIE
Compare register update OK Interrupt Enable
3
1
DOWNIE
Direction change to down Interrupt Enable
6
1
EXTTRIGIE
External trigger valid edge Interrupt Enable
2
1
REPOKIE
Repetition register update OK interrupt Enable
8
1
UEIE
Update event interrupt enable
7
1
UPIE
Direction change to UP Interrupt Enable
5
1
ISR
ISR
interrupt and status register
0x0
32
read-only
n
0x0
0x0
ARRM
Autoreload match
1
1
ARROK
Autoreload register update OK
4
1
CMPM
Compare match
0
1
CMPOK
Compare register update OK
3
1
DOWN
Counter direction change up to down
6
1
EXTTRIG
External trigger edge event
2
1
REPOK
Repetition register update Ok
8
1
UE
LPTIM update event occurred
7
1
UP
Counter direction change down to up
5
1
OR
LPTIM3_OR
option register
0x20
32
read-write
n
0x0
0x0
OR_0
Option register bit 0
0
1
OR_1
Option register bit 1
1
1
RCR
RCR
repetition register
0x28
32
read-write
n
0x0
0x0
REP
Repetition register value
0
8
LPUART
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
LPUART1
LPUART1 global interrupt
29
BRR
BRR
Baud rate register
0xC
32
read-write
n
0x0
0x0
BRR
BRR
0
20
CR1_disabled
CR1_disabled
Control register 1
CR1_enabled
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT
DEAT
21
5
DEDT
DEDT
16
5
FIFOEN
FIFOEN
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RXFNEIE
RXFIFO not empty interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
Transmit data register empty
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR1_enabled
CR1_enabled
Control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT
DEAT
21
5
DEDT
DEDT
16
5
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M0
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
RXNE interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXFEIE
TXFIFO empty interrupt enable
30
1
TXFNFIE
interrupt enable
7
1
UE
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
Control register 2
0x4
32
read-write
n
0x0
0x0
ADD
Address of the LPUART node
24
8
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
DATAINV
Binary data inversion
18
1
MSBFIRST
Most significant bit first
19
1
RXINV
RX pin active level inversion
16
1
STOP
STOP bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
Control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
OVRDIS
Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
threshold interrupt enable
23
1
WUFIE
Wakeup from Stop mode interrupt enable
22
1
WUS
Wakeup from Stop mode interrupt flag selection
20
2
ICR
ICR
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
NECF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
TCCF
Transmission complete clear flag
6
1
WUCF
Wakeup from Stop mode clear flag
20
1
ISR_disabled
ISR_disabled
Interrupt and status register
ISR_enabled
0x1C
32
read-only
n
0x0
0x0
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
FE
FE
1
1
IDLE
IDLE
4
1
NE
NE
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RWU
RWU
19
1
RXFNE
RXFNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXE
TXE
7
1
WUF
WUF
20
1
ISR_enabled
ISR_enabled
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
FE
FE
1
1
IDLE
IDLE
4
1
NE
NE
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RWU
RWU
19
1
RXFF
RXFIFO Full
24
1
RXFNE
RXFNE
5
1
RXFT
RXFIFO threshold flag
26
1
SBKF
SBKF
18
1
TC
TC
6
1
TEACK
TEACK
21
1
TXFE
TXFIFO Empty
23
1
TXFNF
TXFNF
7
1
TXFT
TXFIFO threshold flag
27
1
WUF
WUF
20
1
PRESC
PRESC
Prescaler register
0x2C
32
read-write
n
0x0
0x0
PRESCALER
Clock prescaler
0
4
RDR
RDR
Receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
Request register
0x18
32
write-only
n
0x0
0x0
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
TDR
TDR
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
MPU
Memory protection unit
MPU
0x0
0x0
0x15
registers
n
CTRL
MPU_CTRL
MPU control register
0x4
32
read-only
n
0x0
0x0
ENABLE
Enables the MPU
0
1
HFNMIENA
Enables the operation of MPU during hard fault
1
1
PRIVDEFENA
Enable priviliged software access to default memory map
2
1
RASR
MPU_RASR
MPU region attribute and size register
0x10
32
read-write
n
0x0
0x0
AP
Access permission
24
3
B
memory attribute
16
1
C
memory attribute
17
1
ENABLE
Region enable bit.
0
1
S
Shareable memory attribute
18
1
SIZE
Size of the MPU protection region
1
5
SRD
Subregion disable bits
8
8
TEX
memory attribute
19
3
XN
Instruction access disable bit
28
1
RBAR
MPU_RBAR
MPU region base address register
0xC
32
read-write
n
0x0
0x0
ADDR
Region base address field
5
27
REGION
MPU region field
0
4
VALID
MPU region number valid
4
1
RNR
MPU_RNR
MPU region number register
0x8
32
read-write
n
0x0
0x0
REGION
MPU region
0
8
TYPER
MPU_TYPER
MPU type register
0x0
32
read-only
n
0x0
0x0
DREGION
Number of MPU data regions
8
8
IREGION
Number of MPU instruction regions
16
8
SEPARATE
Separate flag
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x355
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x200
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x204
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register
0x300
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x304
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x308
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x30C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x310
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x314
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x318
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x31C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x320
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
NVIC_STIR
Nested vectored interrupt controller
NVIC
0x0
0x0
0x5
registers
n
STIR
STIR
Software trigger interrupt register
0x0
32
read-write
n
0x0
0x0
INTID
Software generated interrupt ID
0
9
PKA
Public key accelerator
PKA
0x0
0x0
0x2000
registers
n
CLRFR
CLRFR
clear flag register
0x8
32
write-only
n
0x0
0x0
ADDRERRFC
Clear Address error flag
20
1
PROCENDFC
Clear PKA End of Operation flag
17
1
RAMERRFC
Clear PKA RAM error flag
19
1
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
ADDRERRIE
Address error interrupt enable
20
1
EN
PKA enable.
0
1
MODE
PKA operation code
8
6
PROCENDIE
PROCENDIE
17
1
RAMERRIE
RAM error interrupt enable
19
1
START
start the operation
1
1
SR
SR
status register
0x4
32
read-only
n
0x0
0x0
ADDRERRF
Address error flag
20
1
BUSY
PKA operation is in progressThis bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started.
16
1
PROCENDF
PKA End of Operation flag
17
1
RAMERRF
PKA RAM error flag
19
1
PWR
Power control
PWR
0x0
0x0
0x400
registers
n
C2CR1
C2CR1
Power CPU2 control register 1 [dual core device only]
0x80
32
read-write
n
0x0
0x0
FPDR
Flash memory power down mode during LPRun for CPU2
4
1
FPDS
Flash memory power down mode during LPSleep for CPU2
5
1
LPMS
Low-power mode selection for CPU2
0
3
C2CR3
C2CR3
Power CPU2 control register 3 [dual core device only]
0x84
32
read-write
n
0x0
0x0
APC
Apply pull-up and pull-down configuration for CPU2
10
1
EIWUL
Enable internal wakeup line for CPU2
15
1
EWPVD
Enable wakeup PVD for CPU2
8
1
EWRFBUSY
EWRFBUSY
11
1
EWRFIRQ
akeup for CPU2
13
1
EWUP1
Enable Wakeup pin WKUP1 for CPU2
0
1
EWUP2
Enable Wakeup pin WKUP2 for CPU2
1
1
EWUP3
Enable Wakeup pin WKUP3 for CPU2
2
1
CR1
CR1
Power control register 1
0x0
32
read-write
n
0x0
0x0
DBP
Disable backup domain write protection
8
1
FPDR
Flash memory power down mode during LPRun for CPU1
4
1
FPDS
Flash memory power down mode during LPSleep for CPU1
5
1
LPMS
Low-power mode selection for CPU1
0
3
LPR
Low-power run
14
1
SUBGHZSPINSSSEL
sub-GHz SPI NSS source select
3
1
VOS
Voltage scaling range selection
9
2
CR2
CR2
Power control register 2
0x4
32
read-write
n
0x0
0x0
PLS
Power voltage detector level selection.
1
3
PVDE
Power voltage detector enable
0
1
PVME3
Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
6
1
CR3
CR3
Power control register 3
0x8
32
read-write
n
0x0
0x0
APC
Apply pull-up and pull-down configuration from CPU1
10
1
EC2H
nable CPU2 Hold interrupt for CPU1
14
1
EIWUL
Enable internal wakeup line for CPU1
15
1
EULPEN
Ultra-low-power enable
7
1
EWPVD
Enable wakeup PVD for CPU1
8
1
EWRFBUSY
Enable Radio BUSY Wakeup from Standby for CPU1
11
1
EWRFIRQ
akeup for CPU1
13
1
EWUP1
Enable Wakeup pin WKUP1 for CPU1
0
1
EWUP2
Enable Wakeup pin WKUP2 for CPU1
1
1
EWUP3
Enable Wakeup pin WKUP3 for CPU1
2
1
RRS
SRAM2 retention in Standby mode
9
1
CR4
CR4
Power control register 4
0xC
32
read-write
n
0x0
0x0
C2BOOT
oot CPU2 after reset or wakeup from Stop or Standby modes.
15
1
VBE
VBAT battery charging enable
8
1
VBRS
VBAT battery charging resistor selection
9
1
WP1
Wakeup pin WKUP1 polarity
0
1
WP2
Wakeup pin WKUP2 polarity
1
1
WP3
Wakeup pin WKUP3 polarity
2
1
WRFBUSYP
Wakeup Radio BUSY polarity
11
1
CR5
CR5
Power control register 5
0x1C
32
read-write
n
0x0
0x0
RFEOLEN
Enable Radio End Of Life detector enabled
14
1
SMPSEN
Enable SMPS Step Down converter SMPS mode enabled.
15
1
EXTSCR
EXTSCR
Power extended status and status clear register
0x88
32
read-write
n
0x0
0x0
C1CSSF
Clear CPU1 Stop Standby flags
0
1
write-only
C1DS
CPU1 deepsleep mode
14
1
read-only
C1SBF
System Standby flag for CPU1. (no core states retained)
8
1
read-only
C1STOP2F
System Stop2 flag for CPU1. (partial core states retained)
9
1
read-only
C1STOPF
System Stop0, 1 flag for CPU1. (All core states retained)
10
1
read-only
C2CSSF
lear CPU2 Stop Standby flags
1
1
write-only
C2DS
PU2 deepsleep mode
15
1
read-only
C2SBF
ystem Standby flag for CPU2. (no core states retained)
11
1
read-only
C2STOP2F
ystem Stop2 flag for CPU2. (partial core states retained)
12
1
read-only
C2STOPF
ystem Stop0, 1 flag for CPU2. (All core states retained)
13
1
read-only
PDCRA
PDCRA
Power Port A pull-down control register
0x24
32
read-write
n
0x0
0x0
PD0
PD0
0
1
PD1
PD1
1
1
PD10
PD10
10
1
PD11
PD11
11
1
PD12
Port PA[y] pull-down (y=0 to 12)
12
1
PD13
PD13
13
1
PD14
ull-down
14
1
PD15
PD15
15
1
PD2
PD2
2
1
PD3
PD3
3
1
PD4
PD4
4
1
PD5
PD5
5
1
PD6
PD6
6
1
PD7
PD7
7
1
PD8
PD8
8
1
PD9
PD9
9
1
PDCRB
PDCRB
Power Port B pull-down control register
0x2C
32
read-write
n
0x0
0x0
PD0
PD0
0
1
PD1
PD1
1
1
PD10
PD10
10
1
PD11
PD11
11
1
PD12
PD12
12
1
PD13
PD13
13
1
PD14
PD14
14
1
PD15
Port PB[y] pull-down (y=5 to 15)
15
1
PD2
PD2
2
1
PD3
Port PB[y] pull-down (y=0 to 3)
3
1
PD4
PD4
4
1
PD5
PD5
5
1
PD6
PD6
6
1
PD7
PD7
7
1
PD8
PD8
8
1
PD9
PD9
9
1
PDCRC
PDCRC
Power Port C pull-down control register
0x34
32
read-write
n
0x0
0x0
PD0
PD0
0
1
PD1
PD1
1
1
PD13
PD13
13
1
PD14
PD14
14
1
PD15
Port PC[y] pull-down (y=13 to 15)
15
1
PD2
PD2
2
1
PD3
PD3
3
1
PD4
PD4
4
1
PD5
PD5
5
1
PD6
PD6
6
1
PDCRH
PDCRH
Power Port H pull-down control register
0x5C
32
read-write
n
0x0
0x0
PD3
pull-down
3
1
PUCRA
PUCRA
Power Port A pull-up control register
0x20
32
read-write
n
0x0
0x0
PU0
PU0
0
1
PU1
PU1
1
1
PU10
PU10
10
1
PU11
PU11
11
1
PU12
PU12
12
1
PU13
Port PA[y] pull-up bit y (y=0 to 13)
13
1
PU14
PU14
14
1
PU15
Port PA15 pull-up
15
1
PU2
PU2
2
1
PU3
PU3
3
1
PU4
PU4
4
1
PU5
PU5
5
1
PU6
PU6
6
1
PU7
PU7
7
1
PU8
PU8
8
1
PU9
PU9
9
1
PUCRB
PUCRB
Power Port B pull-up control register
0x28
32
read-write
n
0x0
0x0
PU0
PU0
0
1
PU1
PU1
1
1
PU10
PU10
10
1
PU11
PU11
11
1
PU12
PU12
12
1
PU13
PU13
13
1
PU14
PU14
14
1
PU15
Port PB[y] pull-up (y=0 to 15)
15
1
PU2
PU2
2
1
PU3
PU3
3
1
PU4
PU4
4
1
PU5
PU5
5
1
PU6
PU6
6
1
PU7
PU7
7
1
PU8
PU8
8
1
PU9
PU9
9
1
PUCRC
PUCRC
Power Port C pull-up control register
0x30
32
read-write
n
0x0
0x0
PU0
PU0
0
1
PU1
PU1
1
1
PU13
PU13
13
1
PU14
PU14
14
1
PU15
Port PC[y] pull-up (y=13 to 15)
15
1
PU2
PU2
2
1
PU3
PU3
3
1
PU4
PU4
4
1
PU5
PU5
5
1
PU6
PU6
6
1
PUCRH
PUCRH
Power Port H pull-up control register
0x58
32
read-write
n
0x0
0x0
PU3
pull-up
3
1
RSSCMDR
RSSCMDR
RSS Command register [dual core device only]
0x98
32
read-write
n
0x0
0x0
RSSCMD
RSS command
0
8
SCR
SCR
Power status clear register
0x18
32
write-only
n
0x0
0x0
CC2HF
lear CPU2 Hold interrupt flag
14
1
CWPVDF
Clear wakeup PVD interrupt flag
8
1
CWRFBUSYF
Clear wakeup Radio BUSY flag
11
1
CWUF1
Clear wakeup flag 1
0
1
CWUF2
Clear wakeup flag 2
1
1
CWUF3
Clear wakeup flag 3
2
1
SECCFGR
SECCFGR
Power security configuration register [dual core device only]
0x8C
32
read-write
n
0x0
0x0
C2EWILA
wakeup on CPU2 illegal access interrupt enable
15
1
SR1
SR1
Power status register 1
0x10
32
read-only
n
0x0
0x0
C2HF
PU2 Hold interrupt flag
14
1
WPVDF
Wakeup PVD flag
8
1
WRFBUSYF
Radio BUSY wakeup flag
11
1
WUF1
Wakeup flag 1
0
1
WUF2
Wakeup flag 2
1
1
WUF3
Wakeup flag 3
2
1
WUFI
Internal wakeup interrupt flag
15
1
SR2
SR2
Power status register 2
0x14
32
read-only
n
0x0
0x0
C2BOOTS
PU2 boot/wakeup request source information
0
1
FLASHRDY
Flash ready
7
1
LDORDY
LDO ready flag
4
1
PVDO
Power voltage detector output
11
1
PVMO3
Peripheral voltage monitoring output: VDDA vs. 1.62 V
14
1
REGLPF
regulator1 low power flag
9
1
REGLPS
regulator1 started
8
1
REGMRS
regulator2 low power flag
6
1
RFBUSYMS
Radio BUSY masked signal status
2
1
RFBUSYS
Radio BUSY signal status
1
1
RFEOLF
Radio end of life flag
5
1
SMPSRDY
SMPS ready flag
3
1
VOSF
Voltage scaling flag
10
1
SUBGHZSPICR
SUBGHZSPICR
Power SPI3 control register
0x90
32
read-write
n
0x0
0x0
NSS
sub-GHz SPI NSS control
15
1
RCC
Reset and clock control
RCC
0x0
0x0
0x400
registers
n
AHB1ENR
AHB1ENR
AHB1 peripheral clock enable register
0x48
32
read-write
n
0x0
0x0
CRCEN
CPU1 CRC clock enable
12
1
DMA1EN
CPU1 DMA1 clock enable
0
1
DMA2EN
CPU1 DMA2 clock enable
1
1
DMAMUX1EN
CPU1 DMAMUX1 clock enable
2
1
AHB1RSTR
AHB1RSTR
AHB1 peripheral reset register
0x28
32
read-write
n
0x0
0x0
CRCRST
CRC reset
12
1
DMA1RST
DMA1 reset
0
1
DMA2RST
DMA2 reset
1
1
DMAMUX1RST
DMAMUX1 reset
2
1
AHB1SMENR
AHB1SMENR
AHB1 peripheral clocks enable in Sleep modes register
0x68
32
read-write
n
0x0
0x0
CRCSMEN
CRC clock enable during CPU1 CSleep mode.
12
1
DMA1SMEN
DMA1 clock enable during CPU1 CSleep mode.
0
1
DMA2SMEN
DMA2 clock enable during CPU1 CSleep mode
1
1
DMAMUX1SMEN
DMAMUX1 clock enable during CPU1 CSleep mode.
2
1
AHB2ENR
AHB2ENR
AHB2 peripheral clock enable register
0x4C
32
read-write
n
0x0
0x0
GPIOAEN
CPU1 IO port A clock enable
0
1
GPIOBEN
CPU1 IO port B clock enable
1
1
GPIOCEN
CPU1 IO port C clock enable
2
1
GPIOHEN
CPU1 IO port H clock enable
7
1
AHB2RSTR
AHB2RSTR
AHB2 peripheral reset register
0x2C
32
read-write
n
0x0
0x0
GPIOARST
IO port A reset
0
1
GPIOBRST
IO port B reset
1
1
GPIOCRST
IO port C reset
2
1
GPIOHRST
IO port H reset
7
1
AHB2SMENR
AHB2SMENR
AHB2 peripheral clocks enable in Sleep modes register
0x6C
32
read-write
n
0x0
0x0
GPIOASMEN
IO port A clock enable during CPU1 CSleep mode.
0
1
GPIOBSMEN
IO port B clock enable during CPU1 CSleep mode.
1
1
GPIOCSMEN
IO port C clock enable during CPU1 CSleep mode.
2
1
GPIOHSMEN
IO port H clock enable during CPU1 CSleep mode.
7
1
AHB3ENR
AHB3ENR
AHB3 peripheral clock enable register
0x50
32
read-write
n
0x0
0x0
AESEN
AESEN
17
1
FLASHEN
CPU1 Flash interface clock enable
25
1
HSEMEN
HSEMEN
19
1
IPCCEN
IPCCEN
20
1
PKAEN
PKAEN
16
1
RNGEN
RNGEN
18
1
AHB3RSTR
AHB3RSTR
AHB3 peripheral reset register
0x30
32
read-write
n
0x0
0x0
AESRST
AESRST
17
1
FLASHRST
Flash interface reset
25
1
HSEMRST
HSEMRST
19
1
IPCCRST
IPCCRST
20
1
PKARST
PKARST
16
1
RNGRST
RNGRST
18
1
AHB3SMENR
AHB3SMENR
AHB3 peripheral clocks enable in Sleep and Stop modes register
0x70
32
read-write
n
0x0
0x0
AESSMEN
AES accelerator clock enable during CPU1 CSleep mode.
17
1
FLASHSMEN
Flash interface clock enable during CPU1 CSleep mode.
25
1
PKASMEN
PKA accelerator clock enable during CPU1 CSleep mode.
16
1
RNGSMEN
True RNG clocks enable during CPU1 Csleep and CStop modes
18
1
SRAM1SMEN
SRAM1 interface clock enable during CPU1 CSleep mode.
23
1
SRAM2SMEN
SRAM2 memory interface clock enable during CPU1 CSleep mode
24
1
APB1ENR1
APB1ENR1
APB1 peripheral clock enable register 1
0x58
32
read-write
n
0x0
0x0
DAC1EN
CPU1 DAC1 clock enable
29
1
read-write
I2C1EN
CPU1 I2C1 clocks enable
21
1
read-write
I2C2EN
CPU1 I2C2 clocks enable
22
1
read-write
I2C3EN
CPU1 I2C3 clocks enable
23
1
read-write
LPTIM1EN
CPU1 Low power timer 1 clocks enable
31
1
read-write
RTCAPBEN
CPU1 RTC APB clock enable
10
1
read-write
SPI2S2EN
CPU1 SPI2S2 clock enable
14
1
read-write
TIM2EN
CPU1 TIM2 timer clock enable
0
1
read-write
USART2EN
CPU1 USART2 clock enable
17
1
read-write
WWDGEN
CPU1 Window watchdog clock enable
11
1
read-write
APB1ENR2
APB1ENR2
APB1 peripheral clock enable register 2
0x5C
32
read-write
n
0x0
0x0
LPTIM2EN
CPU1 Low power timer 2 clocks enable
5
1
LPTIM3EN
CPU1 Low power timer 3 clocks enable
6
1
LPUART1EN
CPU1 Low power UART 1 clocks enable
0
1
APB1RSTR1
APB1RSTR1
APB1 peripheral reset register 1
0x38
32
read-write
n
0x0
0x0
DACRST
DAC1 reset
29
1
I2C1RST
I2C1 reset
21
1
I2C2RST
I2C2 reset
22
1
I2C3RST
I2C3 reset
23
1
LPTIM1RST
Low Power Timer 1 reset
31
1
SPI2S2RST
SPI2S2 reset
14
1
TIM2RST
TIM2 timer reset
0
1
USART2RST
USART2 reset
17
1
APB1RSTR2
APB1RSTR2
APB1 peripheral reset register 2
0x3C
32
read-write
n
0x0
0x0
LPTIM2RST
Low-power timer 2 reset
5
1
LPTIM3RST
Low-power timer 3 reset
6
1
LPUART1RST
Low-power UART 1 reset
0
1
APB1SMENR1
APB1SMENR1
APB1 peripheral clocks enable in Sleep mode register 1
0x78
32
read-write
n
0x0
0x0
DACSMEN
DAC1 clock enable during CPU1 CSleep mode.
29
1
I2C1SMEN
I2C1 clock enable during CPU1 Csleep and CStop modes
21
1
I2C2SMEN
I2C2 clock enable during CPU1 Csleep and CStop modes
22
1
I2C3SMEN
I2C3 clock enable during CPU1 Csleep and CStop modes
23
1
LPTIM1SMEN
Low power timer 1 clock enable during CPU1 Csleep and CStop mode
31
1
RTCAPBSMEN
RTC bus clock enable during CPU1 CSleep mode.
10
1
SPI2S2SMEN
SPI2S2 clock enable during CPU1 CSleep mode.
14
1
TIM2SMEN
TIM2 timer clock enable during CPU1 CSleep mode.
0
1
USART2SMEN
USART2 clock enable during CPU1 CSleep mode.
17
1
WWDGSMEN
Window watchdog clocks enable during CPU1 CSleep mode.
11
1
APB1SMENR2
APB1SMENR2
APB1 peripheral clocks enable in Sleep mode register 2
0x7C
32
read-write
n
0x0
0x0
LPTIM2SMEN
Low power timer 2 clock enable during CPU1 Csleep and CStop modes
5
1
LPTIM3SMEN
Low power timer 3 clock enable during CPU1 Csleep and CStop modes
6
1
LPUART1SMEN
Low power UART 1 clock enable during CPU1 Csleep and CStop modes.
0
1
APB2ENR
APB2ENR
APB2 peripheral clock enable register
0x60
32
read-write
n
0x0
0x0
ADCEN
CPU1 ADC clocks enable
9
1
SPI1EN
CPU1 SPI1 clock enable
12
1
TIM16EN
CPU1 TIM16 timer clock enable
17
1
TIM17EN
CPU1 TIM17 timer clock enable
18
1
TIM1EN
CPU1 TIM1 timer clock enable
11
1
USART1EN
CPU1 USART1clocks enable
14
1
APB2RSTR
APB2RSTR
APB2 peripheral reset register
0x40
32
read-write
n
0x0
0x0
ADCRST
ADC reset
9
1
SPI1RST
SPI1 reset
12
1
TIM16RST
TIM16 timer reset
17
1
TIM17RST
TIM17 timer reset
18
1
TIM1RST
TIM1 timer reset
11
1
USART1RST
USART1 reset
14
1
APB2SMENR
APB2SMENR
APB2 peripheral clocks enable in Sleep mode register
0x80
32
read-write
n
0x0
0x0
ADCSMEN
ADC clocks enable during CPU1 Csleep and CStop modes
9
1
SPI1SMEN
SPI1 clock enable during CPU1 CSleep mode.
12
1
TIM16SMEN
TIM16 timer clock enable during CPU1 CSleep mode.
17
1
TIM17SMEN
TIM17 timer clock enable during CPU1 CSleep mode.
18
1
TIM1SMEN
TIM1 timer clock enable during CPU1 CSleep mode.
11
1
USART1SMEN
USART1 clock enable during CPU1 Csleep and CStop modes.
14
1
APB3ENR
APB3ENR
APB3 peripheral clock enable register
0x64
32
read-write
n
0x0
0x0
SUBGHZSPIEN
sub-GHz radio SPI clock enable
0
1
APB3RSTR
APB3RSTR
APB3 peripheral reset register
0x44
32
read-write
n
0x0
0x0
SUBGHZSPIRST
Sub-GHz radio SPI reset
0
1
APB3SMENR
APB3SMENR
APB3 peripheral clock enable in Sleep mode register
0x84
32
read-write
n
0x0
0x0
SUBGHZSPISMEN
Sub-GHz radio SPI clock enable during Sleep and Stop modes
0
1
BDCR
BDCR
Backup domain control register
0x90
32
read-write
n
0x0
0x0
BDRST
Backup domain software reset
16
1
read-write
LSCOEN
Low speed clock output enable
24
1
read-write
LSCOSEL
Low speed clock output selection
25
1
read-write
LSEBYP
LSE oscillator bypass
2
1
read-write
LSECSSD
CSS on LSE failure Detection
6
1
read-only
LSECSSON
CSS on LSE enable
5
1
read-write
LSEDRV
LSE oscillator drive capability
3
2
read-write
LSEON
LSE oscillator enable
0
1
read-write
LSERDY
LSE oscillator ready
1
1
read-only
LSESYSEN
LSE system clock enable
7
1
read-write
LSESYSRDY
LSE system clock ready
11
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL
RTC clock source selection
8
2
read-write
C2AHB1ENR
C2AHB1ENR
CPU2 AHB1 peripheral clock enable register
0x148
32
read-write
n
0x0
0x0
CRCEN
CPU2 CRC clock enable
12
1
DMA1EN
CPU2 DMA1 clock enable
0
1
DMA2EN
CPU2 DMA2 clock enable
1
1
DMAMUX1EN
CPU2 DMAMUX1 clock enable
2
1
C2AHB1SMENR
C2AHB1SMENR
CPU2 AHB1 peripheral clocks enable in Sleep modes register [dual core device only]
0x168
32
read-write
n
0x0
0x0
CRCSMEN
CRC clock enable during CPU2 CSleep mode.
12
1
DMA1SMEN
DMA1 clock enable during CPU2 CSleep mode.
0
1
DMA2SMEN
DMA2 clock enable during CPU2 CSleep mode.
1
1
DMAMUX1SMEN
DMAMUX1 clock enable during CPU2 CSleep mode.
2
1
C2AHB2ENR
C2AHB2ENR
CPU2 AHB2 peripheral clock enable register
0x14C
32
read-write
n
0x0
0x0
GPIOAEN
CPU2 IO port A clock enable
0
1
GPIOBEN
CPU2 IO port B clock enable
1
1
GPIOCEN
CPU2 IO port C clock enable
2
1
GPIOHEN
CPU2 IO port H clock enable
7
1
C2AHB2SMENR
C2AHB2SMENR
CPU2 AHB2 peripheral clocks enable in Sleep modes register [dual core device only]
0x16C
32
read-write
n
0x0
0x0
GPIOASMEN
IO port A clock enable during CPU2 CSleep mode.
0
1
GPIOBSMEN
IO port B clock enable during CPU2 CSleep mode.
1
1
GPIOCSMEN
IO port C clock enable during CPU2 CSleep mode.
2
1
GPIOHSMEN
IO port H clock enable during CPU2 CSleep mode.
7
1
C2AHB3ENR
C2AHB3ENR
CPU2 AHB3 peripheral clock enable register [dual core device only]
0x150
32
read-write
n
0x0
0x0
AESEN
CPU2 AES accelerator clock enable
17
1
FLASHEN
CPU2 Flash interface clock enable
25
1
HSEMEN
CPU2 HSEM clock enable
19
1
IPCCEN
CPU2 IPCC interface clock enable
20
1
PKAEN
CPU2 PKA accelerator clock enable
16
1
RNGEN
CPU2 True RNG clocks enable
18
1
C2AHB3SMENR
C2AHB3SMENR
CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]
0x170
32
read-write
n
0x0
0x0
AESSMEN
AES accelerator clock enable during CPU2 CSleep mode.
17
1
FLASHSMEN
Flash interface clock enable during CPU2 CSleep mode.
25
1
PKASMEN
PKA accelerator clock enable during CPU2 CSleep mode.
16
1
RNGSMEN
True RNG clock enable during CPU2 CSleep and CStop mode.
18
1
SRAM1SMEN
SRAM1 interface clock enable during CPU2 CSleep mode.
23
1
SRAM2SMEN
SRAM2 memory interface clock enable during CPU2 CSleep mode.
24
1
C2APB1ENR1
C2APB1ENR1
CPU2 APB1 peripheral clock enable register 1 [dual core device only]
0x158
32
read-write
n
0x0
0x0
DAC1EN
CPU2 DAC1 clock enable
29
1
I2C1EN
CPU2 I2C1 clocks enable
21
1
I2C2EN
CPU2 I2C2 clocks enable
22
1
I2C3EN
CPU2 I2C3 clocks enable
23
1
LPTIM1EN
CPU2 Low power timer 1 clocks enable
31
1
RTCAPBEN
CPU2 RTC APB clock enable
10
1
SPI2S2EN
CPU2 SPI2S2 clock enable
14
1
TIM2EN
CPU2 TIM2 timer clock enable
0
1
USART2EN
CPU2 USART2 clock enable
17
1
C2APB1ENR2
C2APB1ENR2
CPU2 APB1 peripheral clock enable register 2 [dual core device only]
0x15C
32
read-write
n
0x0
0x0
LPTIM2EN
CPU2 Low power timer 2 clocks enable
5
1
LPTIM3EN
CPU2 Low power timer 3 clocks enable
6
1
LPUART1EN
CPU2 Low power UART 1 clocks enable
0
1
C2APB1SMENR1
C2APB1SMENR1
CPU2 APB1 peripheral clocks enable in Sleep mode register 1 [dual core device only]
0x178
32
read-write
n
0x0
0x0
DAC1SMEN
DAC1 clock enable during CPU2 CSleep mode.
29
1
I2C1SMEN
I2C1 clock enable during CPU2 CSleep and CStop modes
21
1
I2C2SMEN
I2C2 clock enable during CPU2 CSleep and CStop modes
22
1
I2C3SMEN
I2C3 clock enable during CPU2 CSleep and CStop modes
23
1
LPTIM1SMEN
Low power timer 1 clock enable during CPU2 CSleep and CStop mode
31
1
RTCAPBSMEN
RTC bus clock enable during CPU2 CSleep mode.
10
1
SPI2S2SMEN
SPI2S2 clock enable during CPU2 CSleep mode.
14
1
TIM2SMEN
TIM2 timer clock enable during CPU2 CSleep mode.
0
1
USART2SMEN
USART2 clock enable during CPU2 CSleep mode.
17
1
C2APB1SMENR2
C2APB1SMENR2
CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]
0x17C
32
read-write
n
0x0
0x0
LPTIM2SMEN
Low power timer 2 clocks enable during CPU2 CSleep and CStop modes.
5
1
LPTIM3SMEN
Low power timer 3 clocks enable during CPU2 CSleep and CStop modes.
6
1
LPUART1SMEN
Low power UART 1 clock enable during CPU2 CSleep and CStop mode
0
1
C2APB2ENR
C2APB2ENR
CPU2 APB2 peripheral clock enable register [dual core device only]
0x160
32
read-write
n
0x0
0x0
ADCEN
ADC clocks enable
9
1
SPI1EN
CPU2 SPI1 clock enable
12
1
TIM16EN
CPU2 TIM16 timer clock enable
17
1
TIM17EN
CPU2 TIM17 timer clock enable
18
1
TIM1EN
CPU2 TIM1 timer clock enable
11
1
USART1EN
CPU2 USART1clocks enable
14
1
C2APB2SMENR
C2APB2SMENR
CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]
0x180
32
read-write
n
0x0
0x0
ADCSMEN
ADC clocks enable during CPU2 Csleep and CStop modes
9
1
SPI1SMEN
SPI1 clock enable during CPU2 CSleep mode
12
1
TIM16SMEN
TIM16 timer clock enable during CPU2 CSleep mode
17
1
TIM17SMEN
TIM17 timer clock enable during CPU2 CSleep mode
18
1
TIM1SMEN
TIM1 timer clock enable during CPU2 CSleep mode
11
1
USART1SMEN
USART1clock enable during CPU2 CSleep and CStop mode
14
1
C2APB3ENR
C2APB3ENR
CPU2 APB3 peripheral clock enable register [dual core device only]
0x164
32
read-write
n
0x0
0x0
SUBGHZSPIEN
CPU2 sub-GHz radio SPI clock enable
0
1
C2APB3SMENR
C2APB3SMENR
CPU2 APB3 peripheral clock enable in Sleep mode register [dual core device only]
0x184
32
read-write
n
0x0
0x0
SUBGHZSPISMEN
sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes
0
1
CCIPR
CCIPR
Peripherals independent clock configuration register
0x88
32
read-write
n
0x0
0x0
ADCSEL
ADC clock source selection
28
2
I2C1SEL
I2C1 clock source selection
12
2
I2C2SEL
I2C2 clock source selection
14
2
I2C3SEL
I2C3 clock source selection
16
2
LPTIM1SEL
Low power timer 1 clock source selection
18
2
LPTIM2SEL
Low power timer 2 clock source selection
20
2
LPTIM3SEL
Low power timer 3 clock source selection
22
2
LPUART1SEL
LPUART1 clock source selection
10
2
RNGSEL
RNG clock source selection
30
2
SPI2S2SEL
SPI2S2 I2S clock source selection
8
2
USART1SEL
USART1 clock source selection
0
2
USART2SEL
USART2 clock source selection
2
2
CFGR
CFGR
Clock configuration register
0x8
32
read-write
n
0x0
0x0
HPRE
HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
4
4
read-write
HPREF
HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)
16
1
read-only
MCOPRE
Microcontroller clock output prescaler
28
3
read-write
MCOSEL
Microcontroller clock output
24
4
read-write
PPRE1
PCLK1 low-speed prescaler (APB1)
8
3
read-write
PPRE1F
PCLK1 prescaler flag (APB1)
17
1
read-only
PPRE2
PCLK2 high-speed prescaler (APB2)
11
3
read-write
PPRE2F
PCLK2 prescaler flag (APB2)
18
1
read-only
STOPWUCK
Wakeup from Stop and CSS backup clock selection
15
1
read-write
SW
System clock switch
0
2
read-write
SWS
System clock switch status
2
2
read-only
CICR
CICR
Clock interrupt clear register
0x20
32
write-only
n
0x0
0x0
CSSC
HSE32 Clock security system interrupt clear
8
1
HSERDYC
HSE32 ready interrupt clear
4
1
HSIRDYC
HSI16 ready interrupt clear
3
1
LSECSSC
LSE Clock security system interrupt clear
9
1
LSERDYC
LSE ready interrupt clear
1
1
LSIRDYC
LSI ready interrupt clear
0
1
MSIRDYC
MSI ready interrupt clear
2
1
PLLRDYC
PLL ready interrupt clear
5
1
CIER
CIER
Clock interrupt enable register
0x18
32
read-write
n
0x0
0x0
HSERDYIE
HSE32 ready interrupt enable
4
1
HSIRDYIE
HSI16 ready interrupt enable
3
1
LSECSSIE
LSE clock security system interrupt enable
9
1
LSERDYIE
LSE ready interrupt enable
1
1
LSIRDYIE
LSI ready interrupt enable
0
1
MSIRDYIE
MSI ready interrupt enable
2
1
PLLRDYIE
PLL ready interrupt enable
5
1
CIFR
CIFR
Clock interrupt flag register
0x1C
32
read-only
n
0x0
0x0
CSSF
HSE32 Clock security system interrupt flag
8
1
HSERDYF
HSE32 ready interrupt flag
4
1
HSIRDYF
HSI16 ready interrupt flag
3
1
LSECSSF
LSE Clock security system interrupt flag
9
1
LSERDYF
LSE ready interrupt flag
1
1
LSIRDYF
LSI ready interrupt flag
0
1
MSIRDYF
MSI ready interrupt flag
2
1
PLLRDYF
PLL ready interrupt flag
5
1
CR
CR
Clock control register
0x0
32
read-write
n
0x0
0x0
CSSON
HSE32 Clock security system enable
19
1
read-write
HSEBYPPWR
Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO.
21
1
read-write
HSEON
HSE32 clock enable
16
1
read-write
HSEPRE
HSE32 sysclk prescaler
20
1
read-write
HSERDY
HSE32 clock ready flag
17
1
read-only
HSIASFS
HSI16 automatic start from Stop
11
1
read-write
HSIKERDY
HSI16 kernel clock ready flag for peripherals requests.
12
1
read-only
HSIKERON
HSI16 always enable for peripheral kernel clocks.
9
1
read-write
HSION
HSI16 clock enable
8
1
read-write
HSIRDY
HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready)
10
1
read-only
MSION
MSI clock enable
0
1
read-write
MSIPLLEN
MSI clock PLL enable
2
1
read-write
MSIRANGE
MSI clock ranges
4
4
read-write
MSIRDY
MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)
1
1
read-only
MSIRGSEL
MSI range control selection
3
1
read-write
PLLON
Main PLL enable
24
1
read-write
PLLRDY
Main PLL clock ready flag
25
1
read-only
CSR
CSR
Control/status register
0x94
32
read-write
n
0x0
0x0
BORRSTF
BOR flag
27
1
read-only
IWDGRSTF
Independent window watchdog reset flag
29
1
read-only
LPWRRSTF
Low-power reset flag
31
1
read-only
LSION
LSI oscillator enable
0
1
read-write
LSIPRE
LSI frequency prescaler
4
1
read-write
LSIRDY
LSI oscillator ready
1
1
read-only
MSISRANGE
MSI clock ranges
8
4
read-write
OBLRSTF
Option byte loader reset flag
25
1
read-only
PINRSTF
Pin reset flag
26
1
read-only
RFILARSTF
Radio illegal access flag
24
1
read-only
RFRST
Radio reset
15
1
read-write
RFRSTF
Radio in reset status flag
14
1
read-only
RMVF
Remove reset flag
23
1
read-write
SFTRSTF
Software reset flag
28
1
read-only
WWDGRSTF
Window watchdog reset flag
30
1
read-only
EXTCFGR
EXTCFGR
Extended clock recovery register
0x108
32
read-write
n
0x0
0x0
C2HPRE
[dual core device only] HCLK2 prescaler (CPU2)
4
4
read-write
C2HPREF
CLK2 prescaler flag (CPU2)
17
1
read-only
SHDHPRE
HCLK3 shared prescaler (AHB3, Flash, and SRAM2)
0
4
read-write
SHDHPREF
HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2)
16
1
read-only
ICSCR
ICSCR
Internal clock sources calibration register
0x4
32
read-write
n
0x0
0x0
HSICAL
HSI16 clock calibration
16
8
read-only
HSITRIM
HSI16 clock trimming
24
7
read-write
MSICAL
MSI clock calibration
0
8
read-only
MSITRIM
MSI clock trimming
8
8
read-write
PLLCFGR
PLLCFGR
PLL configuration register
0xC
32
read-write
n
0x0
0x0
PLLM
Division factor for the main PLL input clock
4
3
PLLN
Main PLL multiplication factor for VCO
8
7
PLLP
Main PLL division factor for PLLPCLK.
17
5
PLLPEN
Main PLL PLLPCLK output enable
16
1
PLLQ
Main PLL division factor for PLLQCLK
25
3
PLLQEN
Main PLL PLLQCLK output enable
24
1
PLLR
Main PLL division factor for PLLRCLK
29
3
PLLREN
Main PLL PLLRCLK output enable
28
1
PLLSRC
Main PLL entry clock source
0
2
RNG
True random number generator
RNG
0x0
0x0
0x400
registers
n
True_RNG
True random number generator interrupt
20
CR
CR
control register
0x0
32
read-write
n
0x0
0x0
CED
Interrupt Enable
5
1
CLKDIV
CLKDIV
16
4
CONDRST
Conditioning soft reset
30
1
CONFIGLOCK
CONFIGLOCK
31
1
IE
Interrupt Enable
3
1
NISTC
NISTC
12
1
RNGEN
True random number generator enable
2
1
RNG_CONFIG1
RNG_CONFIG1
20
6
RNG_CONFIG2
RNG_CONFIG2
13
3
RNG_CONFIG3
RNG_CONFIG3
8
4
DR
DR
data register
0x8
32
read-only
n
0x0
0x0
RNDATA
Random data
0
32
HTCR
HTCR
health test control register
0x10
32
read-write
n
0x0
0x0
HTCFG
health test configuration
0
32
SR
SR
status register
0x4
32
read-write
n
0x0
0x0
CECS
Clock error current status
1
1
read-only
CEIS
Clock error interrupt status
5
1
read-write
DRDY
Data Ready
0
1
read-only
SECS
Seed error current status
2
1
read-only
SEIS
Seed error interrupt status
6
1
read-write
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
TAMP_RTCSTAMP_LSECSS_RTCALARM_RTCSSRU_RTCWKUP
Tamper, TimeStamp, LSECSS,alarm A and B,SSR underflow,RTC wakeup interrupt
2
ALRABINR
ALRABINR
RTC alarm A binary mode register
0x70
32
read-write
n
0x0
0x0
SS
Synchronous counter alarm value in Binary mode
0
32
ALRBBINR
ALRBBINR
RTC alarm B binary mode register
0x74
32
read-write
n
0x0
0x0
SS
Synchronous counter alarm value in Binary mode
0
32
ALRMAR
ALRMAR
ALRMAR
0x40
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm A seconds mask
7
1
MSK2
Alarm A minutes mask
15
1
MSK3
Alarm A hours mask
23
1
MSK4
Alarm A date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format.
4
3
SU
Second units in BCD format.
0
4
WDSEL
Week day selection
30
1
ALRMASSR
ALRMASSR
ALRMASSR
0x44
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
6
SS
Sub seconds value
0
15
SSCLR
Clear synchronous counter on alarm (Binary mode only)
31
1
ALRMBR
ALRMBR
ALRMBR
0x48
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
28
2
DU
Date units or day in BCD format
24
4
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
MSK1
Alarm B seconds mask
7
1
MSK2
Alarm B minutes mask
15
1
MSK3
Alarm B hours mask
23
1
MSK4
Alarm B date mask
31
1
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
WDSEL
Week day selection
30
1
ALRMBSSR
ALRMBSSR
ALRMBSSR
0x4C
32
read-write
n
0x0
0x0
MASKSS
Mask the most-significant bits starting at this bit
24
6
SS
Sub seconds value
0
15
SSCLR
Clear synchronous counter on alarm (Binary mode only)
31
1
CALR
CALR
CALR
0x28
32
read-write
n
0x0
0x0
CALM
Calibration minus
0
9
CALP
Use an 8-second calibration cycle period
15
1
CALW16
CALW16
13
1
CALW8
Use a 16-second calibration cycle period
14
1
LPCAL
Calibration low-power mode
12
1
CR
CR
CR
0x18
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
write-only
ALRAE
Alarm A enable
8
1
read-write
ALRAIE
Alarm A interrupt enable
12
1
read-write
ALRBE
Alarm B enable
9
1
read-write
ALRBIE
Alarm B interrupt enable
13
1
read-write
BKP
Backup
18
1
read-write
BYPSHAD
Bypass the shadow registers
5
1
read-write
COE
Calibration output enable
23
1
read-write
COSEL
Calibration output selection
19
1
read-write
FMT
Hour format
6
1
read-write
ITSE
timestamp on internal event enable
24
1
read-write
OSEL
Output selection
21
2
read-write
OUT2EN
RTC_OUT2 output enable
31
1
read-write
POL
Output polarity
20
1
read-write
REFCKON
RTC_REFIN reference clock detection enable (50 or 60 Hz)
4
1
read-write
SSRUIE
SSR underflow interrupt enable
7
1
read-write
SUB1H
Subtract 1 hour (winter time change)
17
1
write-only
TAMPALRM_PU
TAMPALRM pull-up enable
29
1
read-write
TAMPALRM_TYPE
TAMPALRM output type
30
1
read-write
TAMPOE
Tamper detection output enable on TAMPALRM
26
1
read-write
TAMPTS
Activate timestamp on tamper detection event
25
1
read-write
TSE
timestamp enable
11
1
read-write
TSEDGE
Timestamp event active edge
3
1
read-write
TSIE
Timestamp interrupt enable
15
1
read-write
WUCKSEL
Wakeup clock selection
0
3
read-write
WUTE
Wakeup timer enable
10
1
read-write
WUTIE
Wakeup timer interrupt enable
14
1
read-write
DR
DR
DR
0x4
32
read-write
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
YT
Year tens in BCD format
20
4
YU
Year units in BCD format
16
4
ICSR
ICSR
ICSR
0xC
32
read-write
n
0x0
0x0
BCDU
BCD update
10
3
read-write
BIN
Binary mode
8
2
read-write
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITS
Initialization status flag
4
1
read-only
RECALPF
Recalibration pending Flag
16
1
read-only
RSF
Registers synchronization flag
5
1
read-write
SHPF
Shift operation pending
3
1
read-only
WUTWF
Wakeup timer write flag
2
1
read-only
MISR
MISR
MISR
0x54
32
read-only
n
0x0
0x0
ALRAMF
Alarm A masked flag
0
1
ALRBMF
Alarm B masked flag
1
1
ITSMF
Internal timestamp masked flag
5
1
SSRUMF
SSR underflow masked flag
6
1
TSMF
Timestamp masked flag
3
1
TSOVMF
Timestamp overflow masked flag
4
1
WUTMF
Wakeup timer masked flag
2
1
PRER
PRER
PRER
0x10
32
read-write
n
0x0
0x0
PREDIV_A
Asynchronous prescaler factor
16
7
PREDIV_S
Synchronous prescaler factor
0
15
SCR
SCR
SCR
0x5C
32
write-only
n
0x0
0x0
CALRAF
Clear alarm A flag
0
1
CALRBF
Clear alarm B flag
1
1
CITSF
Clear internal timestamp flag
5
1
CSSRUF
Clear SSR underflow flag
6
1
CTSF
Clear timestamp flag
3
1
CTSOVF
Clear timestamp overflow flag
4
1
CWUTF
Clear wakeup timer flag
2
1
SHIFTR
SHIFTR
SHIFTR
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
SUBFS
Subtract a fraction of a second
0
15
SR
SR
SR
0x50
32
read-only
n
0x0
0x0
ALRAF
Alarm A flag
0
1
ALRBF
Alarm B flag
1
1
ITSF
Internal timestamp flag
5
1
SSRUF
SSR underflow flag
6
1
TSF
Timestamp flag
3
1
TSOVF
Timestamp overflow flag
4
1
WUTF
Wakeup timer flag
2
1
SSR
SSR
SSR
0x8
32
read-only
n
0x0
0x0
SS
Synchronous binary counter
0
32
TR
TR
TR
0x0
32
read-write
n
0x0
0x0
HT
Hour tens in BCD format
20
2
HU
Hour units in BCD format
16
4
MNT
Minute tens in BCD format
12
3
MNU
Minute units in BCD format
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format
4
3
SU
Second units in BCD format
0
4
TSDR
TSDR
TSDR
0x34
32
read-only
n
0x0
0x0
DT
Date tens in BCD format
4
2
DU
Date units in BCD format
0
4
MT
Month tens in BCD format
12
1
MU
Month units in BCD format
8
4
WDU
Week day units
13
3
TSSSR
TSSSR
TSSSR
0x38
32
read-only
n
0x0
0x0
SS
Sub second value
0
32
TSTR
TSTR
TSTR
0x30
32
read-only
n
0x0
0x0
HT
Hour tens in BCD format.
20
2
HU
Hour units in BCD format.
16
4
MNT
Minute tens in BCD format.
12
3
MNU
Minute units in BCD format.
8
4
PM
AM/PM notation
22
1
ST
Second tens in BCD format.
4
3
SU
Second units in BCD format.
0
4
WPR
WPR
write protection register
0x24
32
write-only
n
0x0
0x0
KEY
Write protection key
0
8
WUTR
WUTR
WUTR
0x14
32
read-write
n
0x0
0x0
WUT
Wakeup auto-reload value bits
0
16
WUTOCLR
Wakeup auto-reload output clear value
16
16
SCB
System control block
SCB
0x0
0x0
0x41
registers
n
AFSR
AFSR
Auxiliary fault status register
0x3C
32
read-write
n
0x0
0x0
IMPDEF
Implementation defined
0
32
AIRCR
AIRCR
Application interrupt and reset control register
0xC
32
read-write
n
0x0
0x0
ENDIANESS
ENDIANESS
15
1
PRIGROUP
PRIGROUP
8
3
SYSRESETREQ
SYSRESETREQ
2
1
VECTCLRACTIVE
VECTCLRACTIVE
1
1
VECTKEYSTAT
Register key
16
16
VECTRESET
VECTRESET
0
1
BFAR
BFAR
Bus fault address register
0x38
32
read-write
n
0x0
0x0
BFAR
Bus fault address
0
32
CCR
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0x0
BFHFNMIGN
BFHFNMIGN
8
1
DIV_0_TRP
DIV_0_TRP
4
1
NONBASETHRDENA
Configures how the processor enters Thread mode
0
1
STKALIGN
STKALIGN
9
1
UNALIGN__TRP
UNALIGN_ TRP
3
1
USERSETMPEND
USERSETMPEND
1
1
CFSR_UFSR_BFSR_MMFSR
CFSR_UFSR_BFSR_MMFSR
Configurable fault status register
0x28
32
read-write
n
0x0
0x0
BFARVALID
Bus Fault Address Register (BFAR) valid flag
15
1
DIVBYZERO
Divide by zero usage fault
25
1
IACCVIOL
Instruction access violation flag
1
1
IBUSERR
Instruction bus error
8
1
IMPRECISERR
Imprecise data bus error
10
1
INVPC
Invalid PC load usage fault
18
1
INVSTATE
Invalid state usage fault
17
1
LSPERR
Bus fault on floating-point lazy state preservation
13
1
MLSPERR
MLSPERR
5
1
MMARVALID
Memory Management Fault Address Register (MMAR) valid flag
7
1
MSTKERR
Memory manager fault on stacking for exception entry.
4
1
MUNSTKERR
Memory manager fault on unstacking for a return from exception
3
1
NOCP
No coprocessor usage fault.
19
1
PRECISERR
Precise data bus error
9
1
STKERR
Bus fault on stacking for exception entry
12
1
UNALIGNED
Unaligned access usage fault
24
1
UNDEFINSTR
Undefined instruction usage fault
16
1
UNSTKERR
Bus fault on unstacking for a return from exception
11
1
CPUID
CPUID
CPUID base register
0x0
32
read-only
n
0x0
0x0
Constant
Reads as 0xF
16
4
Implementer
Implementer code
24
8
PartNo
Part number of the processor
4
12
Revision
Revision number
0
4
Variant
Variant number
20
4
HFSR
HFSR
Hard fault status register
0x2C
32
read-write
n
0x0
0x0
DEBUG_VT
Reserved for Debug use
31
1
FORCED
Forced hard fault
30
1
VECTTBL
Vector table hard fault
1
1
ICSR
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag
22
1
NMIPENDSET
NMI set-pending bit.
31
1
PENDSTCLR
SysTick exception clear-pending bit
25
1
PENDSTSET
SysTick exception set-pending bit
26
1
PENDSVCLR
PendSV clear-pending bit
27
1
PENDSVSET
PendSV set-pending bit
28
1
RETTOBASE
Return to base level
11
1
VECTACTIVE
Active vector
0
9
VECTPENDING
Pending vector
12
7
MMFAR
MMFAR
Memory management fault address register
0x34
32
read-write
n
0x0
0x0
MMFAR
Memory management fault address
0
32
SCR
SCR
System control register
0x10
32
read-write
n
0x0
0x0
SEVEONPEND
Send Event on Pending bit
4
1
SLEEPDEEP
SLEEPDEEP
2
1
SLEEPONEXIT
SLEEPONEXIT
1
1
SHCSR
SHCSR
System handler control and state register
0x24
32
read-write
n
0x0
0x0
BUSFAULTACT
Bus fault exception active bit
1
1
BUSFAULTENA
Bus fault enable bit
17
1
BUSFAULTPENDED
Bus fault exception pending bit
14
1
MEMFAULTACT
Memory management fault exception active bit
0
1
MEMFAULTENA
Memory management fault enable bit
16
1
MEMFAULTPENDED
Memory management fault exception pending bit
13
1
MONITORACT
Debug monitor active bit
8
1
PENDSVACT
PendSV exception active bit
10
1
SVCALLACT
SVC call active bit
7
1
SVCALLPENDED
SVC call pending bit
15
1
SYSTICKACT
SysTick exception active bit
11
1
USGFAULTACT
Usage fault exception active bit
3
1
USGFAULTENA
Usage fault enable bit
18
1
USGFAULTPENDED
Usage fault exception pending bit
12
1
SHPR1
SHPR1
System handler priority registers
0x18
32
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4
0
8
PRI_5
Priority of system handler 5
8
8
PRI_6
Priority of system handler 6
16
8
SHPR2
SHPR2
System handler priority registers
0x1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11
24
8
SHPR3
SHPR3
System handler priority registers
0x20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14
16
8
PRI_15
Priority of system handler 15
24
8
VTOR
VTOR
Vector table offset register
0x8
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset field
9
21
SCB_ACTRL
System control block ACTLR
SCB
0x0
0x0
0x5
registers
n
ACTRL
ACTRL
Auxiliary control register
0x0
32
read-write
n
0x0
0x0
DISDEFWBUF
DISDEFWBUF
1
1
DISFOLD
DISFOLD
2
1
DISFPCA
DISFPCA
8
1
DISMCYCINT
DISMCYCINT
0
1
DISOOFP
DISOOFP
9
1
SPI1
Serial peripheral interface/Inter-IC sound
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI 1 global interrupt
25
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
configuration register
0x1C
32
read-write
n
0x0
0x0
ASTRTEN
ASTRTEN
12
1
CHLEN
CHLEN
0
1
CKPOL
CKPOL
3
1
DATLEN
DATLEN
1
2
I2SCFG
I2SCFG
8
2
I2SE
I2SE
10
1
I2SMOD
I2SMOD
11
1
I2SSTD
I2SSTD
4
2
PCMSYNC
PCMSYNC
7
1
I2SPR
I2SPR
prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2SDIV
0
8
MCKOE
MCKOE
9
1
ODD
ODD
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
CHSIDE
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
UDR
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface/Inter-IC sound
SPI
0x0
0x0
0x400
registers
n
SPI2S2
SPI2S2 global interrupt
26
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
configuration register
0x1C
32
read-write
n
0x0
0x0
ASTRTEN
ASTRTEN
12
1
CHLEN
CHLEN
0
1
CKPOL
CKPOL
3
1
DATLEN
DATLEN
1
2
I2SCFG
I2SCFG
8
2
I2SE
I2SE
10
1
I2SMOD
I2SMOD
11
1
I2SSTD
I2SSTD
4
2
PCMSYNC
PCMSYNC
7
1
I2SPR
I2SPR
prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2SDIV
0
8
MCKOE
MCKOE
9
1
ODD
ODD
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
CHSIDE
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
UDR
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
SPI3
Serial peripheral interface/Inter-IC sound
SPI
0x0
0x0
0x400
registers
n
SUBGHZSPI
Sub-GHz radio SPI global interrupt
30
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BIDIMODE
Bidirectional data mode enable
15
1
BIDIOE
Output enable in bidirectional mode
14
1
BR
Baud rate control
3
3
CPHA
Clock phase
0
1
CPOL
Clock polarity
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNEXT
CRC transfer next
12
1
DFF
Data frame format
11
1
LSBFIRST
Frame format
7
1
MSTR
Master selection
2
1
RXONLY
Receive only
10
1
SPE
SPI enable
6
1
SSI
Internal slave select
8
1
SSM
Software slave management
9
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
DS
Data size
8
4
ERRIE
Error interrupt enable
5
1
FRF
Frame format
4
1
FRXTH
FIFO reception threshold
12
1
LDMA_RX
Last DMA transfer for reception
13
1
LDMA_TX
Last DMA transfer for transmission
14
1
NSSP
NSS pulse management
3
1
RXDMAEN
Rx buffer DMA enable
0
1
RXNEIE
RX buffer not empty interrupt enable
6
1
SSOE
SS output enable
2
1
TXDMAEN
Tx buffer DMA enable
1
1
TXEIE
Tx buffer empty interrupt enable
7
1
CRCPR
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
DR
DR
data register
0xC
32
read-write
n
0x0
0x0
DR
Data register
0
16
I2SCFGR
I2SCFGR
configuration register
0x1C
32
read-write
n
0x0
0x0
ASTRTEN
ASTRTEN
12
1
CHLEN
CHLEN
0
1
CKPOL
CKPOL
3
1
DATLEN
DATLEN
1
2
I2SCFG
I2SCFG
8
2
I2SE
I2SE
10
1
I2SMOD
I2SMOD
11
1
I2SSTD
I2SSTD
4
2
PCMSYNC
PCMSYNC
7
1
I2SPR
I2SPR
prescaler register
0x20
32
read-write
n
0x0
0x0
I2SDIV
I2SDIV
0
8
MCKOE
MCKOE
9
1
ODD
ODD
8
1
RXCRCR
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RxCRC
Rx CRC register
0
16
SR
SR
status register
0x8
32
read-write
n
0x0
0x0
BSY
Busy flag
7
1
read-only
CHSIDE
CHSIDE
2
1
read-only
CRCERR
CRC error flag
4
1
read-write
FRLVL
FIFO reception level
9
2
read-only
FTLVL
FIFO transmission level
11
2
read-only
MODF
Mode fault
5
1
read-only
OVR
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TIFRFE
TI frame format error
8
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDR
UDR
3
1
read-only
TXCRCR
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TxCRC
Tx CRC register
0
16
STK
SysTick timer
STK
0x0
0x0
0x11
registers
n
CALIB
CALIB
SysTick calibration value register
0xC
32
read-write
n
0x0
0x0
NOREF
NOREF flag. Reads as zero
31
1
SKEW
SKEW flag: Indicates whether the TENMS value is exact
30
1
TENMS
Calibration value
0
24
CTRL
CTRL
SysTick control and status register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source selection
2
1
COUNTFLAG
COUNTFLAG
16
1
ENABLE
Counter enable
0
1
TICKINT
SysTick exception request enable
1
1
LOAD
LOAD
SysTick reload value register
0x4
32
read-write
n
0x0
0x0
RELOAD
RELOAD value
0
24
VAL
VAL
SysTick current value register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current counter value
0
24
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x30
registers
n
C2IMR1
C2IMR1
SYSCFG CPU2 interrupt mask register 1
0x108
32
read-write
n
0x0
0x0
ADCIM
ADCIM
12
1
AESIM
AESIM
10
1
COMPIM
COMPIM
11
1
DACIM
DACIM
13
1
EXTI0IM
EXTI0IM
16
1
EXTI10IM
EXTI10IM
26
1
EXTI11IM
EXTI11IM
27
1
EXTI12IM
EXTI12IM
28
1
EXTI13IM
EXTI13IM
29
1
EXTI14IM
EXTI14IM
30
1
EXTI15IM
EXTI15IM
31
1
EXTI1IM
EXTI1IM
17
1
EXTI2IM
EXTI2IM
18
1
EXTI3IM
EXTI3IM
19
1
EXTI4IM
EXTI4IM
20
1
EXTI5IM
EXTI5IM
21
1
EXTI6IM
EXTI6IM
22
1
EXTI7IM
EXTI7IM
23
1
EXTI8IM
EXTI8IM
24
1
EXTI9IM
EXTI9IM
25
1
FLASHIM
FLASHIM
6
1
PKAIM
PKAIM
8
1
RCCIM
RCCIM
5
1
RTCALARMIM
RTCALARMIM
1
1
RTCSSRUIM
RTCSSRUIM
2
1
RTCSTAMPTAMPLSECSSIM
RTCSTAMPTAMPLSECSSIM
0
1
RTCWKUPIM
RTCWKUPIM
3
1
C2IMR2
C2IMR2
SYSCFG CPU2 interrupt mask register 2
0x10C
32
read-write
n
0x0
0x0
DMA1CH1IM
DMA1CH1IM
0
1
DMA1CH2IM
DMA1CH2IM
1
1
DMA1CH3IM
DMA1CH3IM
2
1
DMA1CH4IM
DMA1CH4IM
3
1
DMA1CH5IM
DMA1CH5IM
4
1
DMA1CH6IM
DMA1CH6IM
5
1
DMA1CH7IM
DMA1CH7IM
6
1
DMA2CH1IM
DMA2CH1IM
8
1
DMA2CH2IM
DMA2CH2IM
9
1
DMA2CH3IM
DMA2CH3IM
10
1
DMA2CH4IM
DMA2CH4IM
11
1
DMA2CH5IM
DMA2CH5IM
12
1
DMA2CH6IM
DMA2CH6IM
13
1
DMA2CH7IM
DMA2CH7IM
14
1
DMAMUX1IM
DMAMUX1IM
15
1
PVDIM
PVDIM
20
1
PVM3IM
PVM3IM
18
1
CFGR1
CFGR1
configuration register 1
0x4
32
read-write
n
0x0
0x0
BOOSTEN
I/O analog switch voltage booster enable
8
1
I2C1_FMP
I2C1 Fast-mode Plus driving capability activation
20
1
I2C2_FMP
I2C2 Fast-mode Plus driving capability activation
21
1
I2C3_FMP
I2C3 Fast-mode Plus driving capability activation
22
1
I2C_PB6_FMP
Fast-mode Plus (Fm+) driving capability activation on PB6
16
1
I2C_PB7_FMP
Fast-mode Plus (Fm+) driving capability activation on PB7
17
1
I2C_PB8_FMP
Fast-mode Plus (Fm+) driving capability activation on PB8
18
1
I2C_PB9_FMP
Fast-mode Plus (Fm+) driving capability activation on PB9
19
1
CFGR2
CFGR2
CFGR2
0x1C
32
read-write
n
0x0
0x0
CLL
CPU1 LOCKUP (Hardfault) output enable bit
0
1
read-write
ECCL
ECC Lock
3
1
read-write
PVDL
PVD lock enable bit
2
1
read-write
SPF
SRAM2 parity error flag
8
1
read-write
SPL
SRAM2 parity lock bit
1
1
read-write
EXTICR1
EXTICR1
external interrupt configuration register 1
0x8
32
read-write
n
0x0
0x0
EXTI0
EXTI 0 configuration bits
0
3
EXTI1
EXTI 1 configuration bits
4
3
EXTI2
EXTI 2 configuration bits
8
3
EXTI3
EXTI 3 configuration bits
12
3
EXTICR2
EXTICR2
external interrupt configuration register 2
0xC
32
read-write
n
0x0
0x0
EXTI4
EXTI 4 configuration bits
0
3
EXTI5
EXTI 5 configuration bits
4
3
EXTI6
EXTI 6 configuration bits
8
3
EXTI7
EXTI 7 configuration bits
12
3
EXTICR3
EXTICR3
external interrupt configuration register 3
0x10
32
read-write
n
0x0
0x0
EXTI10
EXTI 10 configuration bits
8
3
EXTI11
EXTI 11 configuration bits
12
3
EXTI8
EXTI 8 configuration bits
0
3
EXTI9
EXTI 9 configuration bits
4
3
EXTICR4
EXTICR4
external interrupt configuration register 4
0x14
32
read-write
n
0x0
0x0
EXTI12
EXTI12 configuration bits
0
3
EXTI13
EXTI13 configuration bits
4
3
EXTI14
EXTI14 configuration bits
8
3
EXTI15
EXTI15 configuration bits
12
3
IMR1
IMR1
SYSCFG CPU1 interrupt mask register 1
0x100
32
read-write
n
0x0
0x0
EXTI10IM
EXTI10IM
26
1
EXTI11IM
EXTI11IM
27
1
EXTI12IM
EXTI12IM
28
1
EXTI13IM
EXTI13IM
29
1
EXTI14IM
EXTI14IM
30
1
EXTI15IM
EXTI15IM
31
1
EXTI5IM
EXTI5IM
21
1
EXTI6IM
EXTI6IM
22
1
EXTI7IM
EXTI7IM
23
1
EXTI8IM
EXTI8IM
24
1
EXTI9IM
EXTI9IM
25
1
RTCSSRUIM
RTCSSRUIM
2
1
RTCSTAMPTAMPLSECSSIM
RTCSTAMPTAMPLSECSSIM
0
1
IMR2
IMR2
SYSCFG CPU1 interrupt mask register 2
0x104
32
read-write
n
0x0
0x0
PVDIM
PVDIM
20
1
PVM3IM
PVM3IM
18
1
MEMRMP
MEMRMP
memory remap register
0x0
32
read-write
n
0x0
0x0
MEM_MODE
Memory mapping selection
0
3
RFDCR
RFDCR
radio debug control register
0x208
32
read-write
n
0x0
0x0
RFTBSEL
radio debug test bus selection
0
1
SCSR
SCSR
SCSR
0x18
32
read-write
n
0x0
0x0
PKASRAMBSY
PKA SRAM busy by erase operation
8
1
read-only
SRAM2ER
SRAM2 erase
0
1
read-write
SRAMBSY
SRAM1, SRAM2 and PKA SRAM busy by erase operation
1
1
read-only
SKR
SKR
SKR
0x24
32
write-only
n
0x0
0x0
KEY
SRAM2 write protection key for software erase
0
8
SWPR
SWPR
SWPR
0x20
32
read-write
n
0x0
0x0
P0WP
SRAM2 1Kbyte page 0 write protection
0
1
P10WP
SRAM2 1Kbyte page 10 write protection
10
1
P11WP
SRAM2 1Kbyte page 11 write protection
11
1
P12WP
SRAM2 1Kbyte page 12 write protection
12
1
P13WP
SRAM2 1Kbyte page 13 write protection
13
1
P14WP
SRAM2 1Kbyte page 14 write protection
14
1
P15WP
SRAM2 1Kbyte page 15 write protection
15
1
P16WP
SRAM2 1Kbyte page 16 write protection
16
1
P17WP
SRAM2 1Kbyte page 17 write protection
17
1
P18WP
SRAM2 1Kbyte page 18 write protection
18
1
P19WP
SRAM2 1Kbyte page 19 write protection
19
1
P1WP
SRAM2 1Kbyte page 1 write protection
1
1
P20WP
SRAM2 1Kbyte page 20 write protection
20
1
P21WP
SRAM2 1Kbyte page 21 write protection
21
1
P22WP
SRAM2 1Kbyte page 22 write protection
22
1
P23WP
SRAM2 1Kbyte page 23 write protection
23
1
P24WP
SRAM2 1Kbyte page 24 write protection
24
1
P25WP
SRAM2 1Kbyte page 25 write protection
25
1
P26WP
SRAM2 1Kbyte page 26 write protection
26
1
P27WP
SRAM2 1Kbyte page 27 write protection
27
1
P28WP
SRAM2 1Kbyte page 28 write protection
28
1
P29WP
SRAM2 1Kbyte page 29 write protection
29
1
P2WP
SRAM2 1Kbyte page 2 write protection
2
1
P30WP
SRAM2 1Kbyte page 30 write protection
30
1
P31WP
SRAM2 1Kbyte page 31 write protection
31
1
P3WP
SRAM2 1Kbyte page 3 write protection
3
1
P4WP
SRAM2 1Kbyte page 4 write protection
4
1
P5WP
SRAM2 1Kbyte page 5 write protection
5
1
P6WP
SRAM2 1Kbyte page 6 write protection
6
1
P7WP
SRAM2 1Kbyte page 7 write protection
7
1
P8WP
SRAM2 1Kbyte page 8 write protection
8
1
P9WP
SRAM2 1Kbyte page 9 write protection
9
1
SYSCFG_continue
System configuration controller
SYSCFG
0x0
0x0
0x100
registers
n
C2IMR1
C2IMR1
C2IMR1
0x8
32
read-write
n
0x0
0x0
ADCIM
Peripheral ADC interrupt mask to CPU2
12
1
AES1IM
AES1IM
10
1
COMPIM
Peripheral COMP interrupt mask to CPU2
11
1
DAC1IM
Peripheral DAC1 interrupt mask to CPU2
13
1
EXTI0IM
Peripheral EXTI0 interrupt mask to CPU2
16
1
EXTI10IM
Peripheral EXTI10 interrupt mask to CPU2
26
1
EXTI11IM
Peripheral EXTI11 interrupt mask to CPU2
27
1
EXTI12IM
Peripheral EXTI12 interrupt mask to CPU2
28
1
EXTI13IM
Peripheral EXTI13 interrupt mask to CPU2
29
1
EXTI14IM
Peripheral EXTI14 interrupt mask to CPU2
30
1
EXTI15IM
Peripheral EXTI15 interrupt mask to CPU2
31
1
EXTI1IM
Peripheral EXTI1 interrupt mask to CPU2
17
1
EXTI2IM
Peripheral EXTI2 interrupt mask to CPU2
18
1
EXTI3IM
Peripheral EXTI3 interrupt mask to CPU2
19
1
EXTI4IM
Peripheral EXTI4 interrupt mask to CPU2
20
1
EXTI5IM
Peripheral EXTI5 interrupt mask to CPU2
21
1
EXTI6IM
Peripheral EXTI6 interrupt mask to CPU2
22
1
EXTI7IM
Peripheral EXTI7 interrupt mask to CPU2
23
1
EXTI8IM
Peripheral EXTI8 interrupt mask to CPU2
24
1
EXTI9IM
Peripheral EXTI9 interrupt mask to CPU2
25
1
FLASHIM
Peripheral FLASH interrupt mask to CPU2
6
1
PKAIM
PKAIM
8
1
RCCIM
Peripheral RCC interrupt mask to CPU2
5
1
RTCALARMIM
Peripheral RTCALARM interrupt mask to CPU2
1
1
RTCSSRUIM
RTCSSRUIM
2
1
RTCSTAMPTAMPLSECSSIM
Peripheral RTCSTAMPTAMPLSECSS interrupt mask to CPU2
0
1
RTCWKUPIM
Peripheral RTCWKUP interrupt mask to CPU2
3
1
C2IMR2
C2IMR2
C2IMR2
0xC
32
read-write
n
0x0
0x0
DMA1CH1IM
Peripheral DMA1CH1 interrupt mask to CPU2
0
1
DMA1CH2IM
Peripheral DMA1CH2 interrupt mask to CPU2
1
1
DMA1CH3IM
Peripheral DMA1CH3 interrupt mask to CPU2
2
1
DMA1CH4IM
Peripheral DMA1CH4 interrupt mask to CPU2
3
1
DMA1CH5IM
Peripheral DMA1CH5 interrupt mask to CPU2
4
1
DMA1CH6IM
Peripheral DMA1CH6 interrupt mask to CPU2
5
1
DMA1CH7IM
Peripheral DMA1CH7 interrupt mask to CPU2
6
1
DMA2CH1IM
Peripheral DMA2CH1 interrupt mask to CPU2
8
1
DMA2CH2IM
Peripheral DMA2CH2 interrupt mask to CPU2
9
1
DMA2CH3IM
Peripheral DMA2CH3 interrupt mask to CPU2
10
1
DMA2CH4IM
Peripheral DMA2CH4 interrupt mask to CPU2
11
1
DMA2CH5IM
Peripheral DMA2CH5 interrupt mask to CPU2
12
1
DMA2CH6IM
Peripheral DMA2CH6 interrupt mask to CPU2
13
1
DMA2CH7IM
Peripheral DMA2CH7 interrupt mask to CPU2
14
1
DMAMUX1IM
Peripheral DMAMUX1 interrupt mask to CPU2
15
1
PVDIM
Peripheral PVD interrupt mask to CPU2
20
1
PVM3IM
Peripheral PVM3 interrupt mask to CPU2
18
1
IMR1
IMR1
IMR1
0x0
32
read-write
n
0x0
0x0
EXTI10IM
Peripheral EXTI10 interrupt mask to CPU1
26
1
EXTI11IM
Peripheral EXTI11 interrupt mask to CPU1
27
1
EXTI12IM
Peripheral EXTI12 interrupt mask to CPU1
28
1
EXTI13IM
Peripheral EXTI13 interrupt mask to CPU1
29
1
EXTI14IM
Peripheral EXTI14 interrupt mask to CPU1
30
1
EXTI15IM
Peripheral EXTI15 interrupt mask to CPU1
31
1
EXTI5IM
Peripheral EXTI5 interrupt mask to CPU1
21
1
EXTI6IM
Peripheral EXTI6 interrupt mask to CPU1
22
1
EXTI7IM
Peripheral EXTI7 interrupt mask to CPU1
23
1
EXTI8IM
Peripheral EXTI8 interrupt mask to CPU1
24
1
EXTI9IM
Peripheral EXTI9 interrupt mask to CPU1
25
1
RTCSSRUIM
RTCSSRUIM
2
1
RTCSTAMPTAMPLSECSSIM
RTCSTAMPTAMPLSECSSIM
0
1
IMR2
IMR2
IMR2
0x4
32
read-write
n
0x0
0x0
PVDIM
Peripheral xxx interrupt mask to CPU1
20
1
PVM3IM
Peripheral xxx interrupt mask to CPU1
18
1
TAMP
Tamper and backup registers
TAMP
0x0
0x0
0x400
registers
n
BKP0R
BKP0R
TAMP backup register
0x100
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP10R
BKP10R
TAMP backup register
0x140
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP11R
BKP11R
TAMP backup register
0x144
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP12R
BKP12R
TAMP backup register
0x148
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP13R
BKP13R
TAMP backup register
0x14C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP14R
BKP14R
TAMP backup register
0x150
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP15R
BKP15R
TAMP backup register
0x154
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP16R
BKP16R
TAMP backup register
0x158
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP17R
BKP17R
TAMP backup register
0x15C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP18R
BKP18R
TAMP backup register
0x160
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP19R
BKP19R
TAMP backup register
0x164
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP1R
BKP1R
TAMP backup register
0x104
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP2R
BKP2R
TAMP backup register
0x108
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP3R
BKP3R
TAMP backup register
0x10C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP4R
BKP4R
TAMP backup register
0x110
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP5R
BKP5R
TAMP backup register
0x114
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP6R
BKP6R
TAMP backup register
0x118
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP7R
BKP7R
TAMP backup register
0x11C
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP8R
BKP8R
TAMP backup register
0x120
32
read-write
n
0x0
0x0
BKP
BKP
0
32
BKP9R
BKP9R
TAMP backup register
0x124
32
read-write
n
0x0
0x0
BKP
BKP
0
32
COUNTR
COUNTR
monotonic counter register
0x40
32
read-only
n
0x0
0x0
COUNT
COUNT
0
32
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ITAMP3E
ITAMP3E
18
1
ITAMP5E
ITAMP5E
20
1
ITAMP6E
ITAMP6E
21
1
ITAMP8E
ITAMP8E
23
1
TAMP1E
TAMP1E
0
1
TAMP2E
TAMP2E
1
1
TAMP3E
TAMP2E
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
BKERASE
Backup registerserase
23
1
TAMP1MSK
TAMP1MSK
16
1
TAMP1NOER
TAMP1NOER
0
1
TAMP1TRG
TAMP1TRG
24
1
TAMP2MSK
TAMP2MSK
17
1
TAMP2NOER
TAMP2NOER
1
1
TAMP2TRG
TAMP2TRG
25
1
TAMP3MSK
TAMP3MSK
18
1
TAMP3NOER
TAMP3NOER
2
1
TAMP3TRG
TAMP3TRG
26
1
CR3
CR3
TAMP control register 3
0x8
32
read-write
n
0x0
0x0
ITAMP3NOER
ITAMP3NOER
2
1
ITAMP5NOER
ITAMP5NOER
4
1
ITAMP6NOER
ITAMP6NOER
5
1
ITAMP8NOER
ITAMP8NOER
7
1
FLTCR
FLTCR
TAMP filter control register
0xC
32
read-write
n
0x0
0x0
TAMPFLT
TAMPFLT
3
2
TAMPFREQ
TAMPFREQ
0
3
TAMPPRCH
TAMPPRCH
5
2
TAMPPUDIS
TAMPPUDIS
7
1
IER
IER
TAMP interrupt enable register
0x2C
32
read-write
n
0x0
0x0
ITAMP3IE
ITAMP3IE
18
1
ITAMP5IE
ITAMP5IE
20
1
ITAMP6IE
ITAMP6IE
21
1
ITAMP8IE
ITAMP8IE
23
1
TAMP1IE
TAMP1IE
0
1
TAMP2IE
TAMP2IE
1
1
TAMP3IE
TAMP3IE
2
1
MISR
MISR
TAMP masked interrupt status register
0x34
32
read-only
n
0x0
0x0
ITAMP3MF
ITAMP3MF
18
1
ITAMP5MF
ITAMP5MF
20
1
ITAMP6MF
ITAMP6MF
21
1
ITAMP8MF
ITAMP8MF
23
1
TAMP1MF
TAMP1MF:
0
1
TAMP2MF
TAMP2MF
1
1
TAMP3MF
TAMP3MF
2
1
SCR
SCR
TAMP status clear register
0x3C
32
write-only
n
0x0
0x0
CITAMP3F
CITAMP3F
18
1
CITAMP5F
CITAMP5F
20
1
CITAMP6F
CITAMP6F
21
1
CITAMP8F
CITAMP8F
23
1
CTAMP1F
CTAMP1F
0
1
CTAMP2F
CTAMP2F
1
1
CTAMP3F
CTAMP3F
2
1
SR
SR
TAMP status register
0x30
32
read-only
n
0x0
0x0
ITAMP3F
ITAMP3F
18
1
ITAMP5F
ITAMP5F
20
1
ITAMP6F
ITAMP6F
21
1
ITAMP8F
ITAMP8F
23
1
TAMP1F
TAMP1F
0
1
TAMP2F
TAMP2F
1
1
TAMP3F
TAMP3F
2
1
TIM1
Advanced-control timers
AdavanceTIM
0x0
0x0
0x400
registers
n
TIM1_BRK_TIM1_UP_TIM1_TRG_COM_TIM1_CC
Timer 1 break, update, trigger and communication,capture compare interrupt
14
AF1
AF1
alternate function option register 1
0x60
32
read-write
n
0x0
0x0
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarity
11
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
ResETRSEL
ETR source selection
14
4
AF2
AF2
Alternate function register 2
0x64
32
read-write
n
0x0
0x0
BK2CMP1E
BRK2 COMP1 enable
1
1
BK2CMP1P
BRK2 COMP1 input polarity
10
1
BK2CMP2E
BRK2 COMP2 enable
2
1
BK2CMP2P
BRK2 COMP2 input polarity
11
1
BK2INE
BRK2 BKIN input enable
0
1
BK2INP
BRK2 BKIN2 input polarity
9
1
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BK2BID
Break2 bidirectional
29
1
BK2DSRM
Break2 Disarm
27
1
BK2E
Break 2 enable
24
1
BK2F
Break 2 filter
20
4
BK2P
Break 2 polarity
25
1
BKBID
BKBID
28
1
BKDSRM
BKDSRM
26
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DT
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
CC1E
0
1
CC1NE
CC1NE
2
1
CC1NP
CC1NP
3
1
CC1P
CC1P
1
1
CC2E
CC2E
4
1
CC2NE
CC2NE
6
1
CC2NP
CC2NP
7
1
CC2P
CC2P
5
1
CC3E
CC3E
8
1
CC3NE
CC3NE
10
1
CC3NP
CC3NP
11
1
CC3P
CC3P
9
1
CC4E
CC4E
12
1
CC4P
CC4P
13
1
CC5E
CC5E
16
1
CC5P
CC5P
17
1
CC6E
CC6E
20
1
CC6P
CC6P
21
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1M_3
Output Compare 1 mode - bit 3
16
1
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output Compare 2 mode - bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output Compare 3 mode - bit 3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output Compare 4 mode - bit 3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCMR3OutputComparemode
CCMR3OutputComparemode
capture/compare mode register 3
0x54
32
read-write
n
0x0
0x0
OC5CE
OC5CE
7
1
OC5FE
OC5FE
2
1
OC5M
OC5M
4
3
OC5M_3
OC5M
16
1
OC5PE
OC5PE
3
1
OC6CE
OC6CE
15
1
OC6FE
OC6FE
10
1
OC6M
OC6M
12
3
OC6M_3
OC6M
24
1
OC6PE
OC6PE
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2
Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3
Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4
Capture/Compare value
0
16
CCR5
CCR5
capture/compare register 5
0x58
32
read-write
n
0x0
0x0
CCR5
Capture/Compare 5 value
0
16
GC5C1
Group Channel 5 and Channel 1
29
1
GC5C2
Group Channel 5 and Channel 2
30
1
GC5C3
Group Channel 5 and Channel 3
31
1
CCR6
CCR6
capture/compare register 6
0x5C
32
read-write
n
0x0
0x0
CCR6
Capture/Compare 6 value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
CNT
0
16
read-write
UIFCPY
UIF copy
31
1
read-only
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
CCPC
Capture/compare preloaded control
0
1
CCUS
Capture/compare control update selection
2
1
MMS
Master mode selection
4
3
MMS2
Master mode selection 2
20
4
OIS1
Output Idle state 1 (OC1 output)
8
1
OIS1N
Output Idle state 1 (OC1N output)
9
1
OIS2
Output Idle state 2 (OC2 output)
10
1
OIS2N
Output Idle state 2 (OC2N output)
11
1
OIS3
Output Idle state 3 (OC3 output)
12
1
OIS3N
Output Idle state 3 (OC3N output)
13
1
OIS4
Output Idle state 4 (OC4 output)
14
1
OIS5
Output Idle state 5 (OC5 output)
16
1
OIS6
Output Idle state 6 (OC6 output)
18
1
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
TDE
Trigger DMA request enable
14
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
B2G
Break 2 generation
8
1
BG
Break generation
7
1
CC1G
Capture/Compare 1 generation
1
1
CC2G
Capture/Compare 2 generation
2
1
CC3G
Capture/Compare 3 generation
3
1
CC4G
Capture/Compare 4 generation
4
1
COM
Capture/Compare control update generation
5
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
OR1
option register 1
0x50
32
read-write
n
0x0
0x0
TI1_RMP
Input Capture 1 remap
4
1
TIM1_ETR_ADC1_RMP
TIM1_ETR_ADC1 remapping capability
0
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS_3
Slave mode selection
16
1
TS
Trigger selection
4
3
TS3_4
Trigger selection
20
2
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
B2IF
Break 2 interrupt flag
8
1
BIF
Break interrupt flag
7
1
CC1IF
Capture/Compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/Compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
CC5IF
Compare 5 interrupt flag
16
1
CC6IF
Compare 6 interrupt flag
17
1
COMIF
COM interrupt flag
5
1
SBIF
System Break interrupt flag
13
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TISEL
TISEL
timer input selection register
0x68
32
read-write
n
0x0
0x0
TI1SEL
selects TI1[0] to TI1[15] input
0
4
TI2SEL
selects TI2[0] to TI2[15] input
8
4
TI3SEL
selects TI3[0] to TI3[15] input
16
4
TI4SEL
selects TI4[0] to TI4[15] input
24
4
TIM16
General-purpose timers
GPTIM
0x0
0x0
0x400
registers
n
TIM16
Timer 16 global interrupt
16
AF1
TIM16_AF1
TIM16 alternate function register 1
0x60
32
read-write
n
0x0
0x0
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarity
11
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
ARR
ARR
TIM16/TIM17 auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
TIM16/TIM17 break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKBID
Break Bidirectional
28
1
BKDSRM
Break Disarm
26
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DT
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
TIM16/TIM17 capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 complementary output polarity
3
1
CC1P
Capture/Compare 1 output polarity
1
1
CCMR1_Input
CCMR1_Input
TIM16/TIM17 capture/compare mode register 1
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
CCMR1_Output
CCMR1_Output
TIM16/TIM17 capture/compare mode register 1
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1M_3
OC1M
16
1
OC1PE
OC1PE
3
1
CCR1
CCR1
TIM16/TIM17 capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
TIM16/TIM17 counter
0x24
32
read-write
n
0x0
0x0
CNT
CNT
0
16
read-write
UIFCPYorRes
UIF Copy
31
1
read-only
CR1
CR1
TIM16/TIM17 control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
TIM16/TIM17 control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
CCDS
3
1
CCPC
CCPC
0
1
CCUS
CCUS
2
1
OIS1
OIS1
8
1
OIS1N
OIS1N
9
1
DCR
DCR
TIM16/TIM17 DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
TIM16/TIM17 DMA/interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
TIM16/TIM17 DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
TIM16/TIM17 event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/Compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
UG
Update generation
0
1
OR1
TIM16_OR1
TIM16 option register 1
0x50
32
read-write
n
0x0
0x0
TI1_RMP
Timer 17 input 1 connection
0
2
PSC
PSC
TIM16/TIM17 prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
TIM16/TIM17 repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
TIM16/TIM17 status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/Compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
UIF
Update interrupt flag
0
1
TISEL
TIM16_TISEL
TIM16 input selection register
0x68
32
read-write
n
0x0
0x0
TISEL
TISEL
0
4
TIM17
General-purpose timers
GPTIM
0x0
0x0
0x400
registers
n
TIM17
Timer 17 global interrupt
17
AF1
TIM17_AF1
TIM17 alternate function register 1
0x60
32
read-write
n
0x0
0x0
BKCMP1E
BRK COMP1 enable
1
1
BKCMP1P
BRK COMP1 input polarity
10
1
BKCMP2E
BRK COMP2 enable
2
1
BKCMP2P
BRK COMP2 input polarity
11
1
BKINE
BRK BKIN input enable
0
1
BKINP
BRK BKIN input polarity
9
1
ARR
ARR
TIM16/TIM17 auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR
Auto-reload value
0
16
BDTR
BDTR
TIM16/TIM17 break and dead-time register
0x44
32
read-write
n
0x0
0x0
AOE
Automatic output enable
14
1
BKBID
Break Bidirectional
28
1
BKDSRM
Break Disarm
26
1
BKE
Break enable
12
1
BKF
Break filter
16
4
BKP
Break polarity
13
1
DT
Dead-time generator setup
0
8
LOCK
Lock configuration
8
2
MOE
Main output enable
15
1
OSSI
Off-state selection for Idle mode
10
1
OSSR
Off-state selection for Run mode
11
1
CCER
CCER
TIM16/TIM17 capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NE
Capture/Compare 1 complementary output enable
2
1
CC1NP
Capture/Compare 1 complementary output polarity
3
1
CC1P
Capture/Compare 1 output polarity
1
1
CCMR1_Input
CCMR1_Input
TIM16/TIM17 capture/compare mode register 1
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
IC1F
IC1F
4
4
IC1PSC
IC1PSC
2
2
CCMR1_Output
CCMR1_Output
TIM16/TIM17 capture/compare mode register 1
0x18
32
read-write
n
0x0
0x0
CC1S
CC1S
0
2
OC1FE
OC1FE
2
1
OC1M
OC1M
4
3
OC1M_3
OC1M
16
1
OC1PE
OC1PE
3
1
CCR1
CCR1
TIM16/TIM17 capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1
Capture/Compare 1 value
0
16
CNT
CNT
TIM16/TIM17 counter
0x24
32
read-write
n
0x0
0x0
CNT
CNT
0
16
read-write
UIFCPYorRes
UIF Copy
31
1
read-only
CR1
CR1
TIM16/TIM17 control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
OPM
One pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
TIM16/TIM17 control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
CCDS
3
1
CCPC
CCPC
0
1
CCUS
CCUS
2
1
OIS1
OIS1
8
1
OIS1N
OIS1N
9
1
DCR
DCR
TIM16/TIM17 DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
TIM16/TIM17 DMA/interrupt enable register
0xC
32
read-write
n
0x0
0x0
BIE
Break interrupt enable
7
1
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
COMDE
COM DMA request enable
13
1
COMIE
COM interrupt enable
5
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
TIM16/TIM17 DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
TIM16/TIM17 event generation register
0x14
32
write-only
n
0x0
0x0
BG
Break generation
7
1
CC1G
Capture/Compare 1 generation
1
1
COMG
Capture/Compare control update generation
5
1
UG
Update generation
0
1
OR1
TIM17_OR1
TIM17 option register 1
0x50
32
read-write
n
0x0
0x0
TI1_RMP
Timer 17 input 1 connection
0
2
PSC
PSC
TIM16/TIM17 prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
RCR
RCR
TIM16/TIM17 repetition counter register
0x30
32
read-write
n
0x0
0x0
REP
Repetition counter value
0
8
SR
SR
TIM16/TIM17 status register
0x10
32
read-write
n
0x0
0x0
BIF
Break interrupt flag
7
1
CC1IF
Capture/Compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
COMIF
COM interrupt flag
5
1
UIF
Update interrupt flag
0
1
TISEL
TIM17_TISEL
TIM17 input selection register
0x68
32
read-write
n
0x0
0x0
TISEL
TISEL
0
4
TIM2
General-purpose-timers
GPTIM
0x0
0x0
0x400
registers
n
TIM2
Timer 2 global interrupt
15
AF1
TIM2_AF1
TIM2 alternate function option register 1
0x60
32
read-write
n
0x0
0x0
ETRSEL
External trigger source selection
14
4
ARR
ARR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
ARR_H
High Auto-reload value (TIM2 only)
16
16
ARR_L
Low Auto-reload value
0
16
CCER
CCER
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CC1E
Capture/Compare 1 output enable
0
1
CC1NP
Capture/Compare 1 output Polarity
3
1
CC1P
Capture/Compare 1 output Polarity
1
1
CC2E
Capture/Compare 2 output enable
4
1
CC2NP
Capture/Compare 2 output Polarity
7
1
CC2P
Capture/Compare 2 output Polarity
5
1
CC3E
Capture/Compare 3 output enable
8
1
CC3NP
Capture/Compare 3 output Polarity
11
1
CC3P
Capture/Compare 3 output Polarity
9
1
CC4E
Capture/Compare 4 output enable
12
1
CC4NP
Capture/Compare 4 output Polarity
15
1
CC4P
Capture/Compare 3 output Polarity
13
1
CCMR1_Input
CCMR1_Input
capture/compare mode register 1 (input mode)
CCMR1_Output
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/compare 2 selection
8
2
IC1F
Input capture 1 filter
4
4
IC1PSC
Input capture 1 prescaler
2
2
IC2F
Input capture 2 filter
12
4
IC2PSC
Input capture 2 prescaler
10
2
CCMR1_Output
CCMR1_Output
capture/compare mode register 1 (output mode)
0x18
32
read-write
n
0x0
0x0
CC1S
Capture/Compare 1 selection
0
2
CC2S
Capture/Compare 2 selection
8
2
OC1CE
Output compare 1 clear enable
7
1
OC1FE
Output compare 1 fast enable
2
1
OC1M
Output compare 1 mode
4
3
OC1M_3
Output Compare 1 mode - bit 3
16
1
OC1PE
Output compare 1 preload enable
3
1
OC2CE
Output compare 2 clear enable
15
1
OC2FE
Output compare 2 fast enable
10
1
OC2M
Output compare 2 mode
12
3
OC2M_3
Output Compare 2 mode - bit 3
24
1
OC2PE
Output compare 2 preload enable
11
1
CCMR2_Input
CCMR2_Input
capture/compare mode register 2 (input mode)
CCMR2_Output
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
IC3F
Input capture 3 filter
4
4
IC3PSC
Input capture 3 prescaler
2
2
IC4F
Input capture 4 filter
12
4
IC4PSC
Input capture 4 prescaler
10
2
CCMR2_Output
CCMR2_Output
capture/compare mode register 2 (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3S
Capture/Compare 3 selection
0
2
CC4S
Capture/Compare 4 selection
8
2
OC3CE
Output compare 3 clear enable
7
1
OC3FE
Output compare 3 fast enable
2
1
OC3M
Output compare 3 mode
4
3
OC3M_3
Output Compare 3 mode - bit 3
16
1
OC3PE
Output compare 3 preload enable
3
1
OC4CE
Output compare 4 clear enable
15
1
OC4FE
Output compare 4 fast enable
10
1
OC4M
Output compare 4 mode
12
3
OC4M_3
Output Compare 4 mode - bit 3
24
1
OC4PE
Output compare 4 preload enable
11
1
CCR1
CCR1
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CCR1_H
High Capture/Compare 1 value (TIM2 only)
16
16
CCR1_L
Low Capture/Compare 1 value
0
16
CCR2
CCR2
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CCR2_H
High Capture/Compare 2 value (TIM2 only)
16
16
CCR2_L
Low Capture/Compare 2 value
0
16
CCR3
CCR3
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CCR3_H
High Capture/Compare value (TIM2 only)
16
16
CCR3_L
Low Capture/Compare value
0
16
CCR4
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CCR4_H
High Capture/Compare value (TIM2 only)
16
16
CCR4_L
Low Capture/Compare value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT_H
High counter value (TIM2 only)
16
16
CNT_L
Low counter value
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
ARPE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKD
Clock division
8
2
CMS
Center-aligned mode selection
5
2
DIR
Direction
4
1
OPM
One-pulse mode
3
1
UDIS
Update disable
1
1
UIFREMAP
UIF status bit remapping
11
1
URS
Update request source
2
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
CCDS
Capture/compare DMA selection
3
1
MMS
Master mode selection
4
3
TI1S
TI1 selection
7
1
DCR
DCR
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIER
DIER
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CC1DE
Capture/Compare 1 DMA request enable
9
1
CC1IE
Capture/Compare 1 interrupt enable
1
1
CC2DE
Capture/Compare 2 DMA request enable
10
1
CC2IE
Capture/Compare 2 interrupt enable
2
1
CC3DE
Capture/Compare 3 DMA request enable
11
1
CC3IE
Capture/Compare 3 interrupt enable
3
1
CC4DE
Capture/Compare 4 DMA request enable
12
1
CC4IE
Capture/Compare 4 interrupt enable
4
1
TIE
Trigger interrupt enable
6
1
UDE
Update DMA request enable
8
1
UIE
Update interrupt enable
0
1
DMAR
DMAR
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
EGR
EGR
event generation register
0x14
32
write-only
n
0x0
0x0
CC1G
Capture/compare 1 generation
1
1
CC2G
Capture/compare 2 generation
2
1
CC3G
Capture/compare 3 generation
3
1
CC4G
Capture/compare 4 generation
4
1
TG
Trigger generation
6
1
UG
Update generation
0
1
OR1
TIM2_OR1
TIM2 option register
0x50
32
read-write
n
0x0
0x0
ETR_RMP
External trigger remap
1
1
TI4_RMP
Input capture 4 remap
2
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCR
SMCR
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECE
External clock enable
14
1
ETF
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPS
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCCS
OCREF clear selection
3
1
SMS
Slave mode selection
0
3
SMS_3
Slave mode selection - bit 3
16
1
TS
Trigger selection
4
3
SR
SR
status register
0x10
32
read-write
n
0x0
0x0
CC1IF
Capture/compare 1 interrupt flag
1
1
CC1OF
Capture/Compare 1 overcapture flag
9
1
CC2IF
Capture/Compare 2 interrupt flag
2
1
CC2OF
Capture/compare 2 overcapture flag
10
1
CC3IF
Capture/Compare 3 interrupt flag
3
1
CC3OF
Capture/Compare 3 overcapture flag
11
1
CC4IF
Capture/Compare 4 interrupt flag
4
1
CC4OF
Capture/Compare 4 overcapture flag
12
1
TIF
Trigger interrupt flag
6
1
UIF
Update interrupt flag
0
1
TISEL
TIM2_TISEL
TIM2 timer input selection register
0x68
32
read-write
n
0x0
0x0
TI1SEL
TI1SEL
0
4
TI2SEL
TI2SEL
8
4
TZIC
TrustZone Interrupt Control
TZSC
0x0
0x0
0x400
registers
n
TZIC_ILA
Security Interrupt controller illegal access interrupt
0
ICR1
ICR1
TZIC interrupt status clear register 1
0x20
32
read-write
n
0x0
0x0
AESCF
AESCF
2
1
DMA1CF
DMA1CF
7
1
DMA2CF
DMA2CF
8
1
DMAMUX1CF
DMAMUX1CF
9
1
FLASHCF
FLASHCF
10
1
FLASHIFCF
FLASHIFCF
6
1
PKACF
PKACF
13
1
PWRCF
PWRCF
5
1
RNGCF
RNGCF
3
1
SRAM1CF
SRAM1CF
11
1
SRAM2CF
SRAM2CF
12
1
SUBGHZSPICF
SUBGHZSPICF
4
1
TZICCF
TZICCF
0
1
TZSCCF
TZSCCF
1
1
IER1
IER1
TZIC interrupt enable register 1
0x0
32
read-write
n
0x0
0x0
AESIE
AESIE
2
1
DMA1IE
DMA1IE
7
1
DMA2IE
DMA2IE
8
1
DMAMUX1IE
DMAMUX1IE
9
1
FLASHIE
FLASHIE
10
1
FLASHIFIE
FLASHIFIE
6
1
PKAIE
PKAIE
13
1
PWRIE
PWRIE
5
1
RNGIE
RNGIE
3
1
SRAM1IE
SRAM1IE
11
1
SRAM2IE
SRAM2IE
12
1
SUBGHZSPIIE
SUBGHZSPIIE
4
1
TZICIE
TZICIE
0
1
TZSCIE
TZSCIE
1
1
MISR1
MISR1
TZIC status register 1
0x10
32
read-only
n
0x0
0x0
AESMF
AESMF
2
1
DMA1MF
DMA1MF
7
1
DMA2MF
DMA2MF
8
1
DMAMUX1MF
DMAMUX1MF
9
1
FLASHIFMF
FLASHIFMF
6
1
FLASHMF
FLASHMF
10
1
PKAMF
PKAMF
13
1
PWRMF
PWRMF
5
1
RNGMF
RNGMF
3
1
SRAM1MF
SRAM1MF
11
1
SRAM2MF
SRAM2MF
12
1
SUBGHZSPIMF
SUBGHZSPIMF
4
1
TZICMF
TZICMF
0
1
TZSCMF
TZSCMF
1
1
TZSC
Global TrustZone Controller
TZSC
0x0
0x0
0x400
registers
n
CR
TZSC_CR
TZSC control register
0x0
32
read-write
n
0x0
0x0
LCK
LCK
0
1
MPCWM1_UPWMR
TZSC_MPCWM1_UPWMR
Unprivileged Water Mark 1 register
0x130
32
read-write
n
0x0
0x0
LGTH
LGTH
16
12
MPCWM1_UPWWMR
TZSC_MPCWM1_UPWWMR
Unprivileged Writable Water Mark 1 register
0x134
32
read-write
n
0x0
0x0
LGTH
Define the length of Flash Unprivileged Writable area, in 2
16
12
MPCWM2_UPWMR
TZSC_MPCWM2_UPWMR
Unprivileged Water Mark 2 register
0x138
32
read-write
n
0x0
0x0
LGTH
LGTH
16
12
MPCWM3_UPWMR
TZSC_MPCWM3_UPWMR
Unprivileged Water Mark 3 register
0x140
32
read-write
n
0x0
0x0
LGTH
LGTH
16
12
PRIVCFGR1
TZSC_PRIVCFGR1
TZSC privilege configuration register 1
0x20
32
read-write
n
0x0
0x0
AESPRIV
AESPRIV
2
1
PKAPRIV
PKAPRIV
13
1
RNGPRIV
RNGPRIV
3
1
SUBGHZSPIPRIV
SUBGHZSPIPRIV
4
1
SECCFGR1
TZSC_SECCFGR1
TZSC security configuration register
0x10
32
read-write
n
0x0
0x0
AESSEC
AESSEC
2
1
PKASEC
PKASEC
13
1
RNGSEC
RNGSEC
3
1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 global interrupt
27
BRR
BRR
baud rate register
0xC
32
read-write
n
0x0
0x0
BRR
BRR
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable deassertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
Receive data register not empty/RXFIFO not empty interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
Transmit data register empty/TXFIFO not full interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in low-power mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD3_0
Address of the USART node
24
4
ADD7_4
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DATAINV
Binary data inversion
18
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
stop bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
OVRDIS: Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT2_0
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from low-power mode interrupt enable
22
1
WUS
Wakeup from low-power mode interrupt flag selection
20
2
GTPR
GTPR
guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NECF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCBGTCF
Transmission complete before Guard time clear flag
7
1
TCCF
Transmission complete clear flag
6
1
TXFECF
TXFIFO empty clear flag
5
1
UDRCF
SPI slave underrun clear flag
13
1
WUCF
Wakeup from low-power mode clear flag
20
1
ISR
ISR
interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NE
NE
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
UDR
UDR
13
1
WUF
WUF
20
1
PRESC
PRESC
prescaler register
0x2C
32
read-write
n
0x0
0x0
PRESCALER
Clock prescaler
0
4
RDR
RDR
receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
request register
0x18
32
read-write
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
USART2 global interrupt
28
BRR
BRR
baud rate register
0xC
32
read-write
n
0x0
0x0
BRR
BRR
0
16
CR1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
CMIE
Character match interrupt enable
14
1
DEAT0
DEAT0
21
1
DEAT1
DEAT1
22
1
DEAT2
DEAT2
23
1
DEAT3
DEAT3
24
1
DEAT4
Driver Enable assertion time
25
1
DEDT0
DEDT0
16
1
DEDT1
DEDT1
17
1
DEDT2
DEDT2
18
1
DEDT3
DEDT3
19
1
DEDT4
Driver Enable deassertion time
20
1
EOBIE
End of Block interrupt enable
27
1
FIFOEN
FIFO mode enable
29
1
IDLEIE
IDLE interrupt enable
4
1
M
Word length
12
1
M1
Word length
28
1
MME
Mute mode enable
13
1
OVER8
Oversampling mode
15
1
PCE
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PS
Parity selection
9
1
RE
Receiver enable
2
1
RTOIE
Receiver timeout interrupt enable
26
1
RXFFIE
RXFIFO Full interrupt enable
31
1
RXNEIE
Receive data register not empty/RXFIFO not empty interrupt enable
5
1
TCIE
Transmission complete interrupt enable
6
1
TE
Transmitter enable
3
1
TXEIE
Transmit data register empty/TXFIFO not full interrupt enable
7
1
TXFEIE
TXFIFO empty interrupt enable
30
1
UE
USART enable
0
1
UESM
USART enable in low-power mode
1
1
WAKE
Receiver wakeup method
11
1
CR2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ABREN
Auto baud rate enable
20
1
ABRMOD0
ABRMOD0
21
1
ABRMOD1
Auto baud rate mode
22
1
ADD3_0
Address of the USART node
24
4
ADD7_4
Address of the USART node
28
4
ADDM7
7-bit Address Detection/4-bit Address Detection
4
1
CLKEN
Clock enable
11
1
CPHA
Clock phase
9
1
CPOL
Clock polarity
10
1
DATAINV
Binary data inversion
18
1
DIS_NSS
DIS_NSS
3
1
LBCL
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
LIN break detection length
5
1
LINEN
LIN mode enable
14
1
MSBFIRST
Most significant bit first
19
1
RTOEN
Receiver timeout enable
23
1
RXINV
RX pin active level inversion
16
1
SLVEN
Synchronous Slave mode enable
0
1
STOP
stop bits
12
2
SWAP
Swap TX/RX pins
15
1
TXINV
TX pin active level inversion
17
1
CR3
CR3
control register 3
0x8
32
read-write
n
0x0
0x0
CTSE
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DEP
Driver enable polarity selection
15
1
DMAR
DMA enable receiver
6
1
DMAT
DMA enable transmitter
7
1
EIE
Error interrupt enable
0
1
HDSEL
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NACK
Smartcard NACK enable
4
1
ONEBIT
One sample bit method enable
11
1
OVRDIS
OVRDIS: Overrun Disable
12
1
RTSE
RTS enable
8
1
RXFTCFG
Receive FIFO threshold configuration
25
3
RXFTIE
RXFIFO threshold interrupt enable
28
1
SCARCNT2_0
Smartcard auto-retry count
17
3
SCEN
Smartcard mode enable
5
1
TCBGTIE
Transmission Complete before guard time, interrupt enable
24
1
TXFTCFG
TXFIFO threshold configuration
29
3
TXFTIE
TXFIFO threshold interrupt enable
23
1
WUFIE
Wakeup from low-power mode interrupt enable
22
1
WUS
Wakeup from low-power mode interrupt flag selection
20
2
GTPR
GTPR
guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GT
Guard time value
8
8
PSC
Prescaler value
0
8
ICR
ICR
interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
CMCF
Character match clear flag
17
1
CTSCF
CTS clear flag
9
1
EOBCF
End of block clear flag
12
1
FECF
Framing error clear flag
1
1
IDLECF
Idle line detected clear flag
4
1
LBDCF
LIN break detection clear flag
8
1
NECF
Noise detected clear flag
2
1
ORECF
Overrun error clear flag
3
1
PECF
Parity error clear flag
0
1
RTOCF
Receiver timeout clear flag
11
1
TCBGTCF
Transmission complete before Guard time clear flag
7
1
TCCF
Transmission complete clear flag
6
1
TXFECF
TXFIFO empty clear flag
5
1
UDRCF
SPI slave underrun clear flag
13
1
WUCF
Wakeup from low-power mode clear flag
20
1
ISR
ISR
interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABRE
ABRE
14
1
ABRF
ABRF
15
1
BUSY
BUSY
16
1
CMF
CMF
17
1
CTS
CTS
10
1
CTSIF
CTSIF
9
1
EOBF
EOBF
12
1
FE
FE
1
1
IDLE
IDLE
4
1
LBDF
LBDF
8
1
NE
NE
2
1
ORE
ORE
3
1
PE
PE
0
1
REACK
REACK
22
1
RTOF
RTOF
11
1
RWU
RWU
19
1
RXFF
RXFF
24
1
RXFT
RXFT
26
1
RXNE
RXNE
5
1
SBKF
SBKF
18
1
TC
TC
6
1
TCBGT
TCBGT
25
1
TEACK
TEACK
21
1
TXE
TXE
7
1
TXFE
TXFE
23
1
TXFT
TXFT
27
1
UDR
UDR
13
1
WUF
WUF
20
1
PRESC
PRESC
prescaler register
0x2C
32
read-write
n
0x0
0x0
PRESCALER
Clock prescaler
0
4
RDR
RDR
receive data register
0x24
32
read-only
n
0x0
0x0
RDR
Receive data value
0
9
RQR
RQR
request register
0x18
32
read-write
n
0x0
0x0
ABRRQ
Auto baud rate request
0
1
MMRQ
Mute mode request
2
1
RXFRQ
Receive data flush request
3
1
SBKRQ
Send break request
1
1
TXFRQ
Transmit data flush request
4
1
RTOR
RTOR
receiver timeout register
0x14
32
read-write
n
0x0
0x0
BLEN
Block Length
24
8
RTO
Receiver timeout value
0
24
TDR
TDR
transmit data register
0x28
32
read-write
n
0x0
0x0
TDR
Transmit data value
0
9
VREFBUF
Voltage reference buffer
VREFBUF
0x0
0x0
0xD0
registers
n
CCR
CCR
calibration control register
0x4
32
read-write
n
0x0
0x0
TRIM
Trimming code
0
6
CSR
CSR
control and status register
0x0
32
read-write
n
0x0
0x0
ENVR
Voltage reference buffer mode enable
0
1
read-write
HIZ
High impedance mode
1
1
read-write
VRR
Voltage reference buffer ready
3
1
read-only
VRS
Voltage reference scale
2
1
read-write
WWDG
System window watchdog
WWDG
0x0
0x0
0x400
registers
n
CFR
CFR
Configuration register
0x4
32
read-write
n
0x0
0x0
EWI
Early wakeup interrupt
9
1
write-only
W
7-bit window value
0
7
read-write
WDGTB
Timer base
11
3
read-write
CR
CR
Control register
0x0
32
read-write
n
0x0
0x0
T
7-bit counter (MSB to LSB)
0
7
WDGA
Activation bit
7
1
SR
SR
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1