SiFive
FE310
2024.04.25
FE310
false
8
32
AONCLK
Always-On Clock Configuration
AONCLOCK
0x0
lfrosccfg
AON Clock Configuration Register
0x70
read-write
n
0x0
0x0
div
0
enable
30
ready
31
trim
16
21
BACKUP
Backup Registers
BACKUP
0x0
backup[0]
Backup Register
0x100
read-write
n
0x0
0x0
backup[10]
Backup Register
0x6DC
read-write
n
0x0
0x0
backup[11]
Backup Register
0x788
read-write
n
0x0
0x0
backup[12]
Backup Register
0x838
read-write
n
0x0
0x0
backup[13]
Backup Register
0x8EC
read-write
n
0x0
0x0
backup[14]
Backup Register
0x9A4
read-write
n
0x0
0x0
backup[15]
Backup Register
0xA60
read-write
n
0x0
0x0
backup[1]
Backup Register
0x184
read-write
n
0x0
0x0
backup[2]
Backup Register
0x20C
read-write
n
0x0
0x0
backup[3]
Backup Register
0x298
read-write
n
0x0
0x0
backup[4]
Backup Register
0x328
read-write
n
0x0
0x0
backup[5]
Backup Register
0x3BC
read-write
n
0x0
0x0
backup[6]
Backup Register
0x454
read-write
n
0x0
0x0
backup[7]
Backup Register
0x4F0
read-write
n
0x0
0x0
backup[8]
Backup Register
0x590
read-write
n
0x0
0x0
backup[9]
Backup Register
0x634
read-write
n
0x0
0x0
CLINT
Coreplex Local Interrupts
CLINT
0x0
msip
Hart 0 software interrupt register
0x0
read-write
n
0x0
0x0
mtime
Timer register
0xBFF8
read-write
n
0x0
0x0
mtimecmp
Hart 0 time comparator register
0x4000
read-write
n
0x0
0x0
mtimecmph
Hart 0 time comparator register
0x4004
read-write
n
0x0
0x0
mtimeh
Timer register
0xBFFC
read-write
n
0x0
0x0
GPIO0
General Purpose Input Output
GPIO
0x0
GPIO0
8
GPIO1
9
GPIO2
10
GPIO3
11
GPIO4
12
GPIO5
13
GPIO6
14
GPIO7
15
GPIO8
16
GPIO9
17
GPIO10
18
GPIO11
19
GPIO12
20
GPIO13
21
GPIO14
22
GPIO15
23
GPIO16
24
GPIO17
25
GPIO18
26
GPIO19
27
GPIO20
28
GPIO21
29
GPIO22
30
GPIO23
31
GPIO24
32
GPIO25
33
GPIO26
34
GPIO27
35
GPIO28
36
GPIO29
37
GPIO30
38
GPIO31
39
drive
Drive Strength Register
0x14
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
fall_ie
Fall Interrupt Enable Register
0x20
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
fall_ip
Fall Interrupt Pending Register
0x24
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
high_ie
High Interrupt Enable Register
0x28
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
high_ip
High Interrupt Pending Register
0x2C
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
input_en
Pin Input Enable Register
0x4
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
iof_en
HW I/O Function Enable Register
0x38
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
iof_sel
HW I/O Function Select Register
0x3C
read-write
n
0x0
0x0
pin0
0
IOF0
None
0
PWM0_0
None
1
pin1
1
IOF0
None
0
PWM0_1
None
1
pin10
10
QSPI1_SS3
None
0
PWM2_0
None
1
pin11
11
IOF0
None
0
PWM2_1
None
1
pin12
12
IOF0
None
0
PWM2_2
None
1
pin13
13
IOF0
None
0
PWM2_3
None
1
pin14
14
IOF0
None
0
IOF1
None
1
pin15
15
IOF0
None
0
IOF1
None
1
pin16
16
UART0_RX
None
0
IOF1
None
1
pin17
17
UART0_TX
None
0
IOF1
None
1
pin18
18
IOF0
None
0
IOF1
None
1
pin19
19
IOF0
None
0
PWM1_1
None
1
pin2
2
QSPI1_SS0
None
0
PWM0_2
None
1
pin20
20
IOF0
None
0
PWM1_0
None
1
pin21
21
IOF0
None
0
PWM1_2
None
1
pin22
22
IOF0
None
0
PWM1_3
None
1
pin23
23
IOF0
None
0
IOF1
None
1
pin24
24
UART1_RX
None
0
IOF1
None
1
pin25
25
UART1_TX
None
0
IOF1
None
1
pin26
26
QSPI2_SS
None
0
IOF1
None
1
pin27
27
QSPI2_SD0
None
0
IOF1
None
1
pin28
28
QSPI2_SD1
None
0
IOF1
None
1
pin29
29
QSPI2_SCK
None
0
IOF1
None
1
pin3
3
QSPI1_SD0
None
0
PWM0_3
None
1
pin30
30
QSPI2_SD2
None
0
IOF1
None
1
pin31
31
QSPI2_SD3
None
0
IOF1
None
1
pin4
4
QSPI1_SD1
None
0
IOF1
None
1
pin5
5
QSPI1_SCK
None
0
IOF1
None
1
pin6
6
QSPI1_SD2
None
0
IOF1
None
1
pin7
7
QSPI1_SD3
None
0
IOF1
None
1
pin8
8
QSPI1_SS1
None
0
IOF1
None
1
pin9
9
QSPI1_SS2
None
0
IOF1
None
1
low_ie
Low Interrupt Enable Register
0x30
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
low_ip
Low Interrupt Pending Register
0x34
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
output_en
Pin Output Enable Register
0x8
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
out_xor
Output XOR (invert) Register
0x40
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
port
Output Port Value Register
0xC
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
pullup
Internal Pull-Up Enable Register
0x10
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
rise_ie
Rise Interrupt Enable Register
0x18
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
rise_ip
Rise Interrupt Pending Register
0x1C
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
value
Pin value.
0x0
read-write
n
0x0
0x0
pin0
0
pin1
1
pin10
10
pin11
11
pin12
12
pin13
13
pin14
14
pin15
15
pin16
16
pin17
17
pin18
18
pin19
19
pin2
2
pin20
20
pin21
21
pin22
22
pin23
23
pin24
24
pin25
25
pin26
26
pin27
27
pin28
28
pin29
29
pin3
3
pin30
30
pin31
31
pin4
4
pin5
5
pin6
6
pin7
7
pin8
8
pin9
9
I2C0
Inter-Integrated Circuit Master Interface (FE310-G002 only)
I2C
0x0
I2C0
52
cr
Command register
0x10
write-only
n
0x0
0x0
ack
When a receiver, sent ACK (0) or NACK (1)
3
4
ack
None
0
nack
None
1
iack
Interrupt acknowledge. When set, clears a pending interrupt
0
1
rd
Read from slave
5
6
sta
Generate (repeated) start condition
7
8
sto
Generate stop condition
6
7
wr
Write to slave
4
5
cr_sr
Command register / Status register
0x10
read-write
n
0x0
0x0
ctr
Control register
0x8
read-write
n
0x0
0x0
en
I2C core enable bit
7
8
ien
I2C core interrupt enable bit
6
7
prer_hi
Clock Prescale register hi-byte
0x4
read-write
n
0x0
0x0
value
0
8
prer_lo
Clock Prescale register lo-byte
0x0
read-write
n
0x0
0x0
value
0
8
sr
Status register
cr
0x10
read-only
n
0x0
0x0
al
Arbitration lost
5
6
busy
I2C bus busy
6
7
if
Interrupt Flag. This bit is set when an interrupt is pending, which will cause a processor interrupt request if the IEN bit is set.
0
1
rx_ack
Received acknowledge from slave. This flag represents acknowledge from the addressed slave. '1' = No acknowledge received '0' = Acknowledge received
7
8
tip
Transfer in progress
1
2
txr_rxr
Transmit register / Receive register
0xC
read-write
n
0x0
0x0
data
0
8
OTP
One Time Programmable Memory
OTP
0x0
addr
OTP device address
0x28
read-write
n
0x0
0x0
clock
OTP device clock signal
0x4
read-write
n
0x0
0x0
data_in
OTP device data input
0x2C
read-write
n
0x0
0x0
data_out
OTP device data output
0x30
read-write
n
0x0
0x0
lock
Programmed-I/O lock register
0x0
read-write
n
0x0
0x0
mode
OTP device mode register
0x14
read-write
n
0x0
0x0
mpp
OTP write-voltage charge pump control
0x1C
read-write
n
0x0
0x0
mrr
OTP read-voltage regulator control
0x18
read-write
n
0x0
0x0
output_en
OTP device output-enable signal
0x8
read-write
n
0x0
0x0
rsctrl
OTP read sequencer control
0x34
read-write
n
0x0
0x0
select
OTP device chip-select signal
0xC
read-write
n
0x0
0x0
vppen
OTP write-voltage enable
0x24
read-write
n
0x0
0x0
vrren
OTP read-voltage enable
0x20
read-write
n
0x0
0x0
write_en
OTP device write-enable signal
0x10
read-write
n
0x0
0x0
PLIC
Platform Level Interrupt Control
PLIC
0x0
claim
Claim/Complete Register
0x200004
read-write
n
0x0
0x0
enable[0]
Interrupt Enable Register
0x4000
read-write
n
0x0
0x0
enable[1]
Interrupt Enable Register
0x6004
read-write
n
0x0
0x0
pending[0]
Interrupt Pending Register
0x2000
read-write
n
0x0
0x0
pending[1]
Interrupt Pending Register
0x3004
read-write
n
0x0
0x0
priority[0]
Interrupt Priority Register
0x0
read-write
n
0x0
0x0
priority[10]
Interrupt Priority Register
0xDC
read-write
n
0x0
0x0
priority[11]
Interrupt Priority Register
0x108
read-write
n
0x0
0x0
priority[12]
Interrupt Priority Register
0x138
read-write
n
0x0
0x0
priority[13]
Interrupt Priority Register
0x16C
read-write
n
0x0
0x0
priority[14]
Interrupt Priority Register
0x1A4
read-write
n
0x0
0x0
priority[15]
Interrupt Priority Register
0x1E0
read-write
n
0x0
0x0
priority[16]
Interrupt Priority Register
0x220
read-write
n
0x0
0x0
priority[17]
Interrupt Priority Register
0x264
read-write
n
0x0
0x0
priority[18]
Interrupt Priority Register
0x2AC
read-write
n
0x0
0x0
priority[19]
Interrupt Priority Register
0x2F8
read-write
n
0x0
0x0
priority[1]
Interrupt Priority Register
0x4
read-write
n
0x0
0x0
priority[20]
Interrupt Priority Register
0x348
read-write
n
0x0
0x0
priority[21]
Interrupt Priority Register
0x39C
read-write
n
0x0
0x0
priority[22]
Interrupt Priority Register
0x3F4
read-write
n
0x0
0x0
priority[23]
Interrupt Priority Register
0x450
read-write
n
0x0
0x0
priority[24]
Interrupt Priority Register
0x4B0
read-write
n
0x0
0x0
priority[25]
Interrupt Priority Register
0x514
read-write
n
0x0
0x0
priority[26]
Interrupt Priority Register
0x57C
read-write
n
0x0
0x0
priority[27]
Interrupt Priority Register
0x5E8
read-write
n
0x0
0x0
priority[28]
Interrupt Priority Register
0x658
read-write
n
0x0
0x0
priority[29]
Interrupt Priority Register
0x6CC
read-write
n
0x0
0x0
priority[2]
Interrupt Priority Register
0xC
read-write
n
0x0
0x0
priority[30]
Interrupt Priority Register
0x744
read-write
n
0x0
0x0
priority[31]
Interrupt Priority Register
0x7C0
read-write
n
0x0
0x0
priority[32]
Interrupt Priority Register
0x840
read-write
n
0x0
0x0
priority[33]
Interrupt Priority Register
0x8C4
read-write
n
0x0
0x0
priority[34]
Interrupt Priority Register
0x94C
read-write
n
0x0
0x0
priority[35]
Interrupt Priority Register
0x9D8
read-write
n
0x0
0x0
priority[36]
Interrupt Priority Register
0xA68
read-write
n
0x0
0x0
priority[37]
Interrupt Priority Register
0xAFC
read-write
n
0x0
0x0
priority[38]
Interrupt Priority Register
0xB94
read-write
n
0x0
0x0
priority[39]
Interrupt Priority Register
0xC30
read-write
n
0x0
0x0
priority[3]
Interrupt Priority Register
0x18
read-write
n
0x0
0x0
priority[40]
Interrupt Priority Register
0xCD0
read-write
n
0x0
0x0
priority[41]
Interrupt Priority Register
0xD74
read-write
n
0x0
0x0
priority[42]
Interrupt Priority Register
0xE1C
read-write
n
0x0
0x0
priority[43]
Interrupt Priority Register
0xEC8
read-write
n
0x0
0x0
priority[44]
Interrupt Priority Register
0xF78
read-write
n
0x0
0x0
priority[45]
Interrupt Priority Register
0x102C
read-write
n
0x0
0x0
priority[46]
Interrupt Priority Register
0x10E4
read-write
n
0x0
0x0
priority[47]
Interrupt Priority Register
0x11A0
read-write
n
0x0
0x0
priority[48]
Interrupt Priority Register
0x1260
read-write
n
0x0
0x0
priority[49]
Interrupt Priority Register
0x1324
read-write
n
0x0
0x0
priority[4]
Interrupt Priority Register
0x28
read-write
n
0x0
0x0
priority[50]
Interrupt Priority Register
0x13EC
read-write
n
0x0
0x0
priority[51]
Interrupt Priority Register
0x14B8
read-write
n
0x0
0x0
priority[5]
Interrupt Priority Register
0x3C
read-write
n
0x0
0x0
priority[6]
Interrupt Priority Register
0x54
read-write
n
0x0
0x0
priority[7]
Interrupt Priority Register
0x70
read-write
n
0x0
0x0
priority[8]
Interrupt Priority Register
0x90
read-write
n
0x0
0x0
priority[9]
Interrupt Priority Register
0xB4
read-write
n
0x0
0x0
threshold
Priority Threshold Register
0x200000
read-write
n
0x0
0x0
priority
0
Priority
Never
Never interrupt
0
P1
Priority 1
1
P2
Priority 2
2
P3
Priority 3
3
P4
Priority 4
4
P5
Priority 5
5
P6
Priority 6
6
P7
Priority 7
7
PMU
PMU
PMU
0x0
pmucause
PMU Cause Register
0x144
read-write
n
0x0
0x0
resetcause
8
PowerOn
Power-on reset
0
External
External reset
1
Watchdog
Watchdog reset
2
wakeupcause
0
Reset
Reset wakeup
0
RTC
RTC wakeup
1
Digital
Digital input wakeup
2
pmuie
PMU Interrupt Enable Register
0x140
read-write
n
0x0
0x0
awakeup
3
dwakeup
2
rtc
1
pmukey
PMU Key Register
0x14C
read-write
n
0x0
0x0
pmusleep
PMU Sleep Register
0x148
write-only
n
0x0
0x0
sleep
0
pmusleeppm[0]
PMU Sleep Program Memory
0x240
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[1]
PMU Sleep Program Memory
0x364
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[2]
PMU Sleep Program Memory
0x48C
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[3]
PMU Sleep Program Memory
0x5B8
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[4]
PMU Sleep Program Memory
0x6E8
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[5]
PMU Sleep Program Memory
0x81C
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[6]
PMU Sleep Program Memory
0x954
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmusleeppm[7]
PMU Sleep Program Memory
0xA90
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[0]
PMU Wake Program Memory
0x200
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[1]
PMU Wake Program Memory
0x304
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[2]
PMU Wake Program Memory
0x40C
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[3]
PMU Wake Program Memory
0x518
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[4]
PMU Wake Program Memory
0x628
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[5]
PMU Wake Program Memory
0x73C
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[6]
PMU Wake Program Memory
0x854
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
pmuwakepm[7]
PMU Wake Program Memory
0x970
read-write
n
0x0
0x0
corerst
7
delay
0
hfclkrst
8
isolate
9
pmu_out_0_en
4
pmu_out_1_en
5
PRCI
Power Reset Clock Interrupts
PRCI
0x0
coreclkcfg
Clock Configuration Register
0x10
read-write
n
0x0
0x0
hfrosccfg
Clock Configuration Register
0x0
read-write
n
0x0
0x0
div
0
enable
30
ready
31
trim
16
hfxosccfg
Clock Configuration Register
0x4
read-write
n
0x0
0x0
enable
30
ready
31
pllcfg
PLL Configuration Register
0x8
read-write
n
0x0
0x0
bypass
18
lock
31
pllf
4
pllq
10
PLLQ
Q2
None
1
Q4
None
2
Q8
None
3
pllr
0
PLLR
R1
None
0
R2
None
1
R3
None
2
R4
None
3
refsel
17
sel
16
plloutdiv
PLL Divider Register
0xC
read-write
n
0x0
0x0
div
0
divby1
8
PWM0
8-bit timer with 4 cmp
PWM
0x0
PWM0CMP0
40
PWM0CMP1
41
PWM0CMP2
42
PWM0CMP3
43
cfg
PWM Configuration Register
0x0
read-write
n
0x0
0x0
cmp0center
16
cmp0gang
24
cmp0ip
28
cmp1center
17
cmp1gang
25
cmp1ip
29
cmp2center
18
cmp2gang
26
cmp2ip
30
cmp3center
19
cmp3gang
27
cmp3ip
31
deglitch
10
enalways
12
enoneshot
13
scale
0
sticky
8
zerocmp
9
cmp0
Compare Register
0x20
read-write
n
0x0
0x0
value
0
cmp1
Compare Register
0x24
read-write
n
0x0
0x0
value
0
cmp2
Compare Register
0x28
read-write
n
0x0
0x0
value
0
cmp3
Compare Register
0x2C
read-write
n
0x0
0x0
value
0
count
Counter Register
0x8
read-write
n
0x0
0x0
pwms
Scaled Halfword Counter Register
0x10
read-write
n
0x0
0x0
PWM1
8-bit timer with 4 cmp
PWM
0x0
PWM1CMP0
44
PWM1CMP1
45
PWM1CMP2
46
PWM1CMP3
47
cfg
PWM Configuration Register
0x0
read-write
n
0x0
0x0
cmp0center
16
cmp0gang
24
cmp0ip
28
cmp1center
17
cmp1gang
25
cmp1ip
29
cmp2center
18
cmp2gang
26
cmp2ip
30
cmp3center
19
cmp3gang
27
cmp3ip
31
deglitch
10
enalways
12
enoneshot
13
scale
0
sticky
8
zerocmp
9
cmp0
Compare Register
0x20
read-write
n
0x0
0x0
value
0
cmp1
Compare Register
0x24
read-write
n
0x0
0x0
value
0
cmp2
Compare Register
0x28
read-write
n
0x0
0x0
value
0
cmp3
Compare Register
0x2C
read-write
n
0x0
0x0
value
0
count
Counter Register
0x8
read-write
n
0x0
0x0
pwms
Scaled Halfword Counter Register
0x10
read-write
n
0x0
0x0
PWM2
8-bit timer with 4 cmp
PWM
0x0
PWM2CMP0
48
PWM2CMP1
49
PWM2CMP2
50
PWM2CMP3
51
cfg
PWM Configuration Register
0x0
read-write
n
0x0
0x0
cmp0center
16
cmp0gang
24
cmp0ip
28
cmp1center
17
cmp1gang
25
cmp1ip
29
cmp2center
18
cmp2gang
26
cmp2ip
30
cmp3center
19
cmp3gang
27
cmp3ip
31
deglitch
10
enalways
12
enoneshot
13
scale
0
sticky
8
zerocmp
9
cmp0
Compare Register
0x20
read-write
n
0x0
0x0
value
0
cmp1
Compare Register
0x24
read-write
n
0x0
0x0
value
0
cmp2
Compare Register
0x28
read-write
n
0x0
0x0
value
0
cmp3
Compare Register
0x2C
read-write
n
0x0
0x0
value
0
count
Counter Register
0x8
read-write
n
0x0
0x0
pwms
Scaled Halfword Counter Register
0x10
read-write
n
0x0
0x0
QSPI0
Quad Serial Peripheral Interface
QSPI
0x0
QSPI0
5
csdef
Chip Select Default Register
0x14
read-write
n
0x0
0x0
csid
Chip Select ID Register
0x10
read-write
n
0x0
0x0
csmode
Chip Select Mode Register
0x18
read-write
n
0x0
0x0
delay0
Delay Control 0 Register
0x28
read-write
n
0x0
0x0
cssck
0
sckcs
16
delay1
Delay Control 1 Register
0x2C
read-write
n
0x0
0x0
intercs
0
interxfr
16
div
Serial Clock Divisor Register
0x0
read-write
n
0x0
0x0
value
0
fctrl
SPI Flash Interface Control Register
0x60
read-write
n
0x0
0x0
enable
0
ffmt
SPI Flash Instruction Format Register
0x64
read-write
n
0x0
0x0
addr_len
Number of address bytes (0 to 4)
1
addr_proto
Protocol for transmitting address and padding
10
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
cmd_code
Value of command byte
16
cmd_en
Enable sending of command
0
cmd_proto
Protocol for transmitting command
8
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
data_proto
Protocol for receiving data bytes
12
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
pad_cnt
Number of dummy cycles
0
pad_code
First 8 bits to transmit during dummy cycles
24
fmt
Frame Format Register
0x40
read-write
n
0x0
0x0
direction
3
Rx
For dual and quad protocols, the DQ pins are tri-stated. For
the single protocol, the DQ0 pin is driven with the transmit
data as normal.
0
Tx
The receive FIFO is not populated.
1
endian
2
Big
Transmit MSB first.
0
Little
Transmit LSB first.
1
length
16
protocol
0
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
ie
SPI Interrupt Enable Register
0x70
read-write
n
0x0
0x0
rxwm
1
txwm
0
ip
SPI Interrupt Pending Register
0x74
read-write
n
0x0
0x0
rxwm
1
txwm
0
mode
Serial Clock Mode Register
0x4
read-write
n
0x0
0x0
phase
0
polarity
1
rxdata
Receive Data Register
0x4C
read-write
n
0x0
0x0
data
0
empty
31
rxmark
Receive Watermark Register
0x54
read-write
n
0x0
0x0
value
0
txdata
Transmit Data Register
0x48
read-write
n
0x0
0x0
data
0
full
31
txmark
Transmit Watermark Register
0x50
read-write
n
0x0
0x0
value
0
QSPI1
Quad Serial Peripheral Interface
QSPI
0x0
QSPI1
6
csdef
Chip Select Default Register
0x14
read-write
n
0x0
0x0
csid
Chip Select ID Register
0x10
read-write
n
0x0
0x0
csmode
Chip Select Mode Register
0x18
read-write
n
0x0
0x0
delay0
Delay Control 0 Register
0x28
read-write
n
0x0
0x0
cssck
0
sckcs
16
delay1
Delay Control 1 Register
0x2C
read-write
n
0x0
0x0
intercs
0
interxfr
16
div
Serial Clock Divisor Register
0x0
read-write
n
0x0
0x0
value
0
fctrl
SPI Flash Interface Control Register
0x60
read-write
n
0x0
0x0
enable
0
ffmt
SPI Flash Instruction Format Register
0x64
read-write
n
0x0
0x0
addr_len
Number of address bytes (0 to 4)
1
addr_proto
Protocol for transmitting address and padding
10
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
cmd_code
Value of command byte
16
cmd_en
Enable sending of command
0
cmd_proto
Protocol for transmitting command
8
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
data_proto
Protocol for receiving data bytes
12
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
pad_cnt
Number of dummy cycles
0
pad_code
First 8 bits to transmit during dummy cycles
24
fmt
Frame Format Register
0x40
read-write
n
0x0
0x0
direction
3
Rx
For dual and quad protocols, the DQ pins are tri-stated. For
the single protocol, the DQ0 pin is driven with the transmit
data as normal.
0
Tx
The receive FIFO is not populated.
1
endian
2
Big
Transmit MSB first.
0
Little
Transmit LSB first.
1
length
16
protocol
0
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
ie
SPI Interrupt Enable Register
0x70
read-write
n
0x0
0x0
rxwm
1
txwm
0
ip
SPI Interrupt Pending Register
0x74
read-write
n
0x0
0x0
rxwm
1
txwm
0
mode
Serial Clock Mode Register
0x4
read-write
n
0x0
0x0
phase
0
polarity
1
rxdata
Receive Data Register
0x4C
read-write
n
0x0
0x0
data
0
empty
31
rxmark
Receive Watermark Register
0x54
read-write
n
0x0
0x0
value
0
txdata
Transmit Data Register
0x48
read-write
n
0x0
0x0
data
0
full
31
txmark
Transmit Watermark Register
0x50
read-write
n
0x0
0x0
value
0
QSPI2
Quad Serial Peripheral Interface
QSPI
0x0
QSPI2
7
csdef
Chip Select Default Register
0x14
read-write
n
0x0
0x0
csid
Chip Select ID Register
0x10
read-write
n
0x0
0x0
csmode
Chip Select Mode Register
0x18
read-write
n
0x0
0x0
delay0
Delay Control 0 Register
0x28
read-write
n
0x0
0x0
cssck
0
sckcs
16
delay1
Delay Control 1 Register
0x2C
read-write
n
0x0
0x0
intercs
0
interxfr
16
div
Serial Clock Divisor Register
0x0
read-write
n
0x0
0x0
value
0
fctrl
SPI Flash Interface Control Register
0x60
read-write
n
0x0
0x0
enable
0
ffmt
SPI Flash Instruction Format Register
0x64
read-write
n
0x0
0x0
addr_len
Number of address bytes (0 to 4)
1
addr_proto
Protocol for transmitting address and padding
10
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
cmd_code
Value of command byte
16
cmd_en
Enable sending of command
0
cmd_proto
Protocol for transmitting command
8
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
data_proto
Protocol for receiving data bytes
12
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
pad_cnt
Number of dummy cycles
0
pad_code
First 8 bits to transmit during dummy cycles
24
fmt
Frame Format Register
0x40
read-write
n
0x0
0x0
direction
3
Rx
For dual and quad protocols, the DQ pins are tri-stated. For
the single protocol, the DQ0 pin is driven with the transmit
data as normal.
0
Tx
The receive FIFO is not populated.
1
endian
2
Big
Transmit MSB first.
0
Little
Transmit LSB first.
1
length
16
protocol
0
Single
DQ0 (MOSI), DQ1 (MISO)
0
Dual
DQ0, DQ1
1
Quad
DQ0, DQ1, DQ2, DQ3
2
ie
SPI Interrupt Enable Register
0x70
read-write
n
0x0
0x0
rxwm
1
txwm
0
ip
SPI Interrupt Pending Register
0x74
read-write
n
0x0
0x0
rxwm
1
txwm
0
mode
Serial Clock Mode Register
0x4
read-write
n
0x0
0x0
phase
0
polarity
1
rxdata
Receive Data Register
0x4C
read-write
n
0x0
0x0
data
0
empty
31
rxmark
Receive Watermark Register
0x54
read-write
n
0x0
0x0
value
0
txdata
Transmit Data Register
0x48
read-write
n
0x0
0x0
data
0
full
31
txmark
Transmit Watermark Register
0x50
read-write
n
0x0
0x0
value
0
RTC
Watchdog
RTC
0x0
RTC
2
rtccfg
RTC Configuration Register
0x40
read-write
n
0x0
0x0
cmpip
28
enalways
12
scale
0
rtccmp
RTC Compare Register
0x60
read-write
n
0x0
0x0
rtchi
RTC Counter High Register
0x4C
read-write
n
0x0
0x0
value
0
rtclo
RTC Counter Low Register
0x48
read-write
n
0x0
0x0
rtcs
RTC Scaled Counter Register
0x50
read-write
n
0x0
0x0
UART0
Universal Asynchronous Receiver Transmitter
UART
0x0
UART0
3
div
Baud Rate Divisor Register
0x18
read-write
n
0x0
0x0
value
0
ie
Interrupt Enable Register
0x10
read-write
n
0x0
0x0
rxwm
1
txwm
0
ip
Interrupt Pending Register
0x14
read-write
n
0x0
0x0
rxwm
1
txwm
0
rxctrl
Receive Control Register
0xC
read-write
n
0x0
0x0
counter
16
enable
0
rxdata
Receive Data Register
0x4
read-write
n
0x0
0x0
data
0
empty
31
txctrl
Transmit Control Register
0x8
read-write
n
0x0
0x0
counter
16
enable
0
nstop
1
txdata
Transmit Data Register
0x0
read-write
n
0x0
0x0
data
0
full
31
UART1
Universal Asynchronous Receiver Transmitter
UART
0x0
UART1
4
div
Baud Rate Divisor Register
0x18
read-write
n
0x0
0x0
value
0
ie
Interrupt Enable Register
0x10
read-write
n
0x0
0x0
rxwm
1
txwm
0
ip
Interrupt Pending Register
0x14
read-write
n
0x0
0x0
rxwm
1
txwm
0
rxctrl
Receive Control Register
0xC
read-write
n
0x0
0x0
counter
16
enable
0
rxdata
Receive Data Register
0x4
read-write
n
0x0
0x0
data
0
empty
31
txctrl
Transmit Control Register
0x8
read-write
n
0x0
0x0
counter
16
enable
0
nstop
1
txdata
Transmit Data Register
0x0
read-write
n
0x0
0x0
data
0
full
31
WDOG
Watchdog
Watchdog
0x0
WATCHDOG
1
wdogcfg
Watchdog Configuration Register
0x0
read-write
n
0x0
0x0
cmpip
28
enalways
12
encoreawake
13
rsten
8
scale
0
zerocmp
9
wdogcmp
Watchdog Compare Register
0x20
read-write
n
0x0
0x0
value
0
wdogcount
Watchdog Counter Register
0x8
read-write
n
0x0
0x0
wdogfeed
Watchdog Feed Register
0x18
read-write
n
0x0
0x0
wdogkey
Watchdog Key Register
0x1C
write-only
n
0x0
0x0
wdogs
Watchdog Scaled Counter Register
0x10
read-write
n
0x0
0x0