SiliconLabs
RS1xxxx
2024.04.28
RS1xxxx Cortex-M4 MCU
CM4
r0p1
little
true
true
6
false
8
32
AUX_ADC_DAC_COMP
The ADC-DAC Controller works on a ADC with a resolution of 12bits at 10Maga sample per second when ADC reference Voltage is greater than 2.8v or 5Maga sample per second when ADC reference Voltage is less than 2.8v.
ADC_DAC_COMP
0x0
0x0
0x214
registers
n
COMP2
7
COMP1
8
ADC
11
ADC_CH_BIT_MAP_CONFIG_0
This is configuration register0 to explain the bit map for ADC channels
0x0
32
read-write
n
0x0
0x0
CHANNEL_BITMAP
This field explain the bit map for ADC channels
0
32
read-write
ADC_CH_BIT_MAP_CONFIG_1
This is configuration register1 to explain the bit map for ADC channels
0x4
32
read-write
n
0x0
0x0
CHANNEL_BITMAP
This field explain the bit map for ADC channels
0
32
read-write
ADC_CH_BIT_MAP_CONFIG_2
This is configuration register2 to explain the bit map for ADC channels
0x8
32
read-write
n
0x0
0x0
CHANNEL_BITMAP
This field explain the bit map for ADC channels
0
32
read-write
ADC_CH_BIT_MAP_CONFIG_3
This is configuration register3 to explain the bit map for ADC channels
0xC
32
read-write
n
0x0
0x0
CHANNEL_BITMAP
This field explain the bit map for ADC channels
0
32
read-write
ADC_CH_FREQ0
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x178
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ1
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x17C
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ10
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1A0
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ11
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1A4
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ12
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1A8
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ13
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1AC
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ14
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1B0
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ15
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x1B4
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ2
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x180
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ3
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x184
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ4
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x188
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ5
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x18C
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ6
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x190
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ7
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x194
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ8
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x198
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_FREQ9
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 )
0x19C
32
read-write
n
0x0
CH_FREQ_VALUE
This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16)
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET0
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x138
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET1
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x13C
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET10
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x160
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET11
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x164
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET12
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x168
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET13
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x16C
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET14
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x170
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET15
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x174
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET2
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x140
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET3
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x144
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET4
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x148
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET5
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x14C
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET6
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x150
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET7
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x154
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET8
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x158
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_CH_OFFSET9
This Register specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0x15C
32
read-write
n
0x0
CH_OFFSET
This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled.
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
ADC_DET_THR_CTRL_0
ADC detection threshold control 0
0x18
32
read-write
n
0x0
ADC_INPUT_DETECTION_THRESHOLD_0
The value against which the ADC output has to be compared is to be programmed in this register
0
8
read-write
ADC_INPUT_DETECTION_THRESHOLD_1
Carries upper two bits of ADC detection threshold
12
14
read-write
COMP_EQ_EN
When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is equal to the programmed Aux ADC detection threshold
10
11
read-write
Disable
Disable compare equal bit
0
Enable
Enable compare equal bit
1
COMP_GRTR_THAN_EN
When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is greater than the programmed Aux ADC detection threshold..
9
10
read-write
Disable
Disable grater than mode
0
Enable
Enable grater than mode
1
COMP_LESS_THAN_EN
When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls below the programmed Aux ADC detection threshold.
8
9
read-write
Disable
Disable less than mode
0
Enable
Enable less than mode
1
RANGE_COMPARISON_ENABLE
When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls within the range specified in AUX ADC Detection threshold0 and AUX ADC Detection threshold1
11
12
read-write
Disable
Disable range comparison
0
Enable
Enable range comparison
1
RESERVED1
Reserved1
14
32
read-write
ADC_DET_THR_CTRL_1
ADC detection threshold control 1
0x1C
32
read-write
n
0x0
ADC_DETECTION_THRESHOLD_2_UPPER_BITS
Upper 2 bits of ADC detection threshold 2
11
13
read-write
ADC_INPUT_DETECTION_THRESHOLD_2
The value against which the ADC output has to be compared is to be programmed in this register.
0
8
read-write
COMP_EQ_EN
When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is equal to the programmed Aux ADC detection threshold.
10
11
read-write
Disable
Disable compare equal bit
0
Enable
Enable compare equal bit
1
COMP_GRTR_THAN_EN
When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is greater than the programmed Aux ADC detection threshold.
9
10
read-write
Disable
Disable grater than mode
0
Enable
Enable grater than mode
1
COMP_LESS_THAN_EN
When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output falls below the programmed Aux ADC detection threshold.
8
9
read-write
Disable
Disable less than mode
0
Enable
Enable less than mode
1
RESERVED1
Reserved1
13
32
read-write
ADC_INT_MEM_1
This register explain start address of first/second buffer corresponding to the channel location ADC INT MEM 2
0x1D4
32
read-write
n
0x0
PROG_WR_DATA
These 32-bits specifies the start address of first/second buffer corresponding to the channel location ADC INT MEM
0
32
read-write
ADC_INT_MEM_2
This register explain ADC INT MEM2.
0x1D8
32
read-write
n
0x0
PROG_WR_ADDR
These bits correspond to the address of the internal memory basing on the channel number, whose information we want to program
10
15
read-write
PROG_WR_DATA
These 10-bits specify the buffer length of first/second buffer corresponding to the channel location ADC INT MEM2
0
10
read-write
PROG_WR_DATA1
Valid bit for first/second buffers corresponding to ADC INT MEM2
15
16
read-write
RESERVED3
Reserved3
16
32
read-write
ADC_SEQ_CTRL
This register explain configuration parameter for AUXADC
0x1CC
32
read-write
n
0x0
ADC_SEQ_CTRL_DMA_MODE
To enable/disable per channel ping-pong operation (One-hot coding).
16
32
read-write
ADC_SEQ_CTRL_PING_PONG
To enable/disable per channel DAM mode (One-hot coding)
0
16
read-write
AUXADC_CLK_DIV_FAC
ADC clock division register
0xC
32
read-write
n
0x0
ADC_CLK_DIV_FAC
These bits control the Total-Duration of the ADC clock
0
10
read-write
ADC_CLK_ON_DUR
These bits control the On-Duration of the ADC clock
16
25
read-write
RESERVED1
Reserved1
10
16
read-write
RESERVED2
Reserved2
25
32
read-write
AUXADC_CONFIG_1
This register explain configuration parameter for AUXADC
0x1C4
32
read-write
n
0x0
AUXADC_DIFF_MODE
AUX ADC Differential Mode select
26
27
read-write
AUXADC_INN_SEL
Mux select for negetive input of adc
22
26
read-write
AUXADC_INP_SEL
Mux select for positive input of adc
17
22
read-write
RESERVED1
Reserved1
0
17
read-write
RESERVED2
Reserved2
27
32
read-write
AUXADC_CONFIG_2
This register is AUX-ADC config2
0x208
32
read-write
n
0x0
AUXADC_CONFIG_ENABLE
Aux ADC Configuration Enable
11
12
read-write
Disable
Disable ADC Configuration
0
Enable
ADC Configuration Enable
1
RESERVED1
Reserved1
0
11
read-write
RESERVED2
Reserved2
12
32
read-write
AUXADC_CTRL_1
Control register1 for ADC
0x4
32
read-write
n
0x0
ADC_CH_SEL_LS
Aux ADC channel number from which the data has to be sampled This is valid only when adc multiple channel active is zero. When channel number is greater than three, upper bits should also be programmed ADC CHANNEL SELECT MS to bits in this register
12
14
read-write
CHANNEL_0
channel 0
0
CHANNEL_1
channel 1
1
CHANNEL_2
channel 2
2
CHANNEL_3
channel 3
3
ADC_CH_SEL_MSB
It is recommended to write these bits to 0
7
9
read-write
ADC_ENABLE
This bits activates the ADC path in Aux ADC-DAC controller.
0
1
read-write
Disable
Disable ADC
0
Enable
Enable ADC
1
ADC_FIFO_FLUSH
This bit is used to flush the ADC FIFO
2
3
read-write
Disable
Do not flush
0
Enable
Flush ADC FIFO
1
ADC_FIFO_THRESHOLD
These bits control the ADC FIFO threshold. When used by DMA, this will act as almost empty threshold. For TA, it acts as almost full threshold.
3
6
read-write
ADC_MULTIPLE_CHAN_ACTIVE
This bit is used to control the auxadc sel signal going to the Aux ADC.
6
7
read-write
Disable
Data will be sampled from the programmed ADC channel
0
Enable
Data will be sampled from four ADC channels in sequential order and written to the receive FIFO in the same order.
1
ADC_NUM_PHASE
ADC number of phase
27
28
read-write
ADC_STATIC_MODE
This bit is used to select non-FIFO mode in ADC.
1
2
read-write
Disable
FIFO mode enabled here data directly to FIFO.
0
Enable
Static mode enable here data directly to register not in FIFO
1
BYPASS_NOISE_AVG
ADC in Bypass noise avg mode.
9
10
read-write
EN_ADC_CLK
Enable AUX ADC Divider output clock
10
11
read-write
RESERVED1
Reserved1
11
12
read-write
RESERVED2
Reserved2
14
27
read-write
RESERVED3
Reserved3
28
32
read-write
AUXADC_DATA
AUXADC Data Read through Register.
0x14
32
read-write
n
0x0
AUXADC_CH_ID
Channel ID of AUX DATA sample, Valid only in FIFO mode
12
16
read-only
AUXADC_DATA
AUXADC Data Read through Register
0
12
read-only
RESERVED1
Reserved1
16
32
read-write
AUXDAC_CLK_DIV_FAC
DAC clock division register
0x8
32
read-write
n
0x0
DAC_CLK_DIV_FAC
These bits control the DAC clock division factor
0
10
read-write
RESERVED1
Reserved1
10
32
read-write
AUXDAC_CONIG_1
This register is AUX-DAC config1
0x20C
32
read-write
n
0x0
AUXDAC_DATA_S
Satatic AUX Dac Data
4
14
read-write
AUXDAC_DYN_EN
Satatic AUX Dac Data
14
15
read-write
AUXDAC_EN_S
Enable signal DAC
0
1
read-write
AUXDAC_OUT_MUX_EN
Aux OUT mux Enable
1
2
read-write
Disable
DAC output is not connected to PAD
0
Enable
DAC output is connected to PAD
1
AUXDAC_OUT_MUX_SEL
AUXDAC OUT MUX SELECT Enable
2
3
read-write
Disable
DAC output is not connected to PAD
0
Enable
DAC output is connected to PAD
1
RESERVED1
Reserved1
3
4
read-write
RESERVED2
RESERVED2
15
32
read-write
AUXDAC_CTRL_1
Control register1 for DAC
0x0
32
read-write
n
0x0
DAC_ENABLE_F
This bit is used to enable AUX DAC controller ,valid only when DAC enable is happpen
6
7
read-write
Disable
Disable DAC Controller
0
Enable
Enable DAC Controller
1
DAC_FIFO_FLUSH
This bit is used to flush the DAC FIFO.
2
3
read-write
Disable
Do not flush
0
Enable
Flush dac FIFO
1
DAC_FIFO_THRESHOLD
These bits control the DAC FIFO threshold. When used by DMA, this will act as almost full threshold. For TA, it acts as almost empty threshold
3
6
read-write
DAC_STATIC_MODE
This bit is used to select non-FIFO mode in DAC.
1
2
read-write
Disable
FIFO mode enabled. Data written to the DAC_DATA_REG is written to the FIFO in this mode. In either of these modes, data will be driven to the DAC only when dac_enable is set.
0
Enable
Static mode is enabled. Data written to the DAC_DATA_REG will not be written to the FIFO. It will be played on DAC directly. Only single sample can be held at a time
1
DAC_TO_CTRL_ADC
When set, AUX-DAC control is handed over to Aux ADC-DAC controller. By default, AUX-DAC is under the control of baseband.
9
10
read-write
ENDAC_FIFO_CONFIG
This bit activates the DAC path in Aux ADC-DAC controller. Data samples will be played on DAC only when this bit is set.
0
1
read-write
Disable
Disable fifo configuration of DAC
0
Enable
Enable fifo configuration of DAC
1
RESERVED1
It is recommended to write these bits to 0
7
9
read-write
RESERVED2
Reserved2
10
32
read-write
AUXDAC_DATA_REG
Writing to this register will fill DAC FIFO for streaming Data to DAC
0x10
32
read-write
n
0x0
AUXDAC_DATA
Writing to this register will fill DAC FIFO for streaming Data to DAC
0
10
write-only
RESERVED1
Reserved1
10
32
read-write
AUX_LDO
This register is AUX-LDO configuration
0x210
32
read-write
n
0x0
BYPASS_LDO
bypass the LDO
5
6
read-write
DYN_EN
Dynamic Enable
7
8
read-write
ENABLE_LDO
Turn LDO
6
7
read-write
LDO_CTRL
Enable ldo control field
0
4
read-write
LDO_DEFAULT_MODE
ldo default mode enable
4
5
read-write
RESERVED1
It is recommended to write these bits to 0.
8
32
read-write
BOD
Programs resistor bank, reference buffer and scaler
0x200
32
read-write
n
0x0
BOD_RES_EN
configuration of register bank 1 for enable and 0 for disable
8
9
read-write
Disable
Disable register bank bit
0
Enable
Enable register bank bit
1
BOD_THRSH
Programmability for resistor bank
9
14
read-write
REFBUF_EN
Reference buffer configuration 1 for enable 0 for disable
3
4
read-write
Disable
Disable reference buffer enable bit
0
Enable
Enable reference buffer enable bit
1
REFBUF_VOLT_SEL
selection of voltage of reference buffer
4
8
read-write
RESERVED1
Reserved1
0
3
read-write
RESERVED2
Reserved2
14
32
read-write
COMPARATOR1
Programs comparators1 and comparators2
0x204
32
read-write
n
0x0
CMP1_EN
To enable comparator1
0
1
read-write
Disable
Disable comparator1
0
Enable
Enable comparator1
1
CMP1_EN_FILTER
To enable filter for comparator 1
1
2
read-write
Disable
Disable filter for comparator1
0
Enable
Enable filter to comparator1
1
CMP1_HYST
Programmability to control hysteresis of comparator1
2
4
read-write
CMP1_MUX_SEL_N
Select for negative input of comparator_1
8
12
read-write
comp1_n0
external pin as negative input for comparator1
0
comp1_n1
external pin as negative input for comparator1
1
DAC
DAC as negative input for comparator1
2
reference_buffer_out
reference_buffer_out as negative input for comparator1
3
reference_scaler_out
reference_scaler_out as negative input for comparator1
4
register_bank_out
register_bank_out as negative input for comparator1
5
opamp1
opamp1 as negative input for comparator1
6
opamp2
opamp2 as negative input for comparator1
7
opamp3
opamp3 as negative input for comparator1
8
CMP1_MUX_SEL_P
Select for positive input of comparator_1
4
8
read-write
comp1_p0
external pin as positive input for comparator1
0
comp1_p1
external pin as positive input for comparator1
1
DAC
DAC as positive input for comparator1
2
reference_buffer_out
reference_buffer_out as positive input for comparator1
3
reference_scaler_out
reference_scaler_out as positive input for comparator1
4
register_bank_out
register_bank_out as positive input for comparator1
5
opamp1
opamp1 as positive input for comparator1
6
opamp2
opamp2 as positive input for comparator1
7
opamp3
opamp3 as positive input for comparator1
8
CMP2_EN
To enable comparator 2
12
13
read-write
Disable
Disable comparator2
0
Enable
Enable comparator2
1
CMP2_EN_FILTER
To enable filter for comparator 2
13
14
read-write
Disable
Disable filter for comparator2
0
Enable
Enable filter to comparator2
1
CMP2_HYST
Programmability to control hysteresis of comparator2
14
16
read-write
CMP2_MUX_SEL_N
Select for negative input of comparator_2
20
24
read-write
comp2_n0
external pin as negative input for comparator2
0
comp2_n1
external pin as negative input for comparator2
1
DAC
DAC as negative input for comparator2
2
reference_buffer_out
reference_buffer_out as negative input for comparator2
3
reference_scaler_out
reference_scaler_out as negative input for comparator2
4
register_bank_out
register_bank_out as negative input for comparator2
5
opamp1
opamp1 as negative input for comparator2
6
opamp2
opamp2 as negative input for comparator2
7
opamp3
opamp3 as negative input for comparator2
8
CMP2_MUX_SEL_P
Select for positive input of comparator_2
16
20
read-write
comp2_p0
external pin as positive input for comparator2
0
comp2_p1
external pin as positive input for comparator2
1
DAC
DAC as positive input for comparator2
2
reference_buffer_out
reference_buffer_out as positive input for comparator2
3
reference_scaler_out
reference_scaler_out as positive input for comparator2
4
register_bank_out
register_bank_out as positive input for comparator2
5
opamp1
opamp1 as positive input for comparator2
6
opamp2
opamp2 as positive input for comparator2
7
opamp3
opamp3 as positive input for comparator2
8
RESERVED1
Reserved1
24
32
read-write
FIFO_STATUS_REG
Interrupt masked status register
0x30
32
read-only
n
0x0
ADC_FIFO_AEMPTY
Set when the FIFO occupancy less than ADC FIFO threshold
3
4
read-only
ADC_FIFO_AFULL
Set when ADC FIFO occupancy greater than ADC FIFO threshold.
7
8
read-only
ADC_FIFO_EMPTY
Set when FIFO is empty. This bit gets cleared when the ADC FIFO is not empty.
2
3
read-only
ADC_FIFO_FULL
Set when ADC FIFO is full. This bit gets cleared when data is read from the FIFO.
6
7
read-only
DAC_FIFO_AEMPTY
Set when the FIFO occupancy less than DAC FIFO threshold
5
6
read-only
DAC_FIFO_AFULL
Set when DAC FIFO occupancy greater than FIFO threshold
1
2
read-only
DAC_FIFO_EMPTY
Set when FIFO is empty. This bit gets cleared when the DAC FIFO is not empty.
4
5
read-only
DAC_FIFO_FULL
Set when DAC FIFO is full. In word mode, FIFO will be shown as full unless there is space for 16-bits.
0
1
read-only
RESERVED1
Reserved1
8
32
read-only
INTERNAL_DMA_CH_ENABLE
This register is internal channel enable
0x1DC
32
read-write
n
0x0
INTERNAL_DMA_ENABLE
When Set, Internal DMA will be used for reading ADC samples from ADC FIFO and writing them to ULP SRAM Memories.
31
32
read-write
PER_CHANNEL_ENABLE
Enable bit for Each channel,like channel0 for bit0 to channel15 for bit15 etc
0
16
read-write
RESERVED3
Reserved3
16
31
read-write
INTR_CLEAR_REG
ADC detection threshold control 1
0x20
32
read-write
n
0x0
CLR_INTR
This bit is used to clear threshold detection interrupt
0
1
read-write
NO_EFFECT
Disable compare equal bit
0
CLEAR_INTERRUPT
Clear the interrupt
1
INTR_CLEAR_REG
If enabled, corresponding first_mem_switch_intr bits will be cleared.
8
24
read-write
RESERVED1
Reserved1
1
8
read-write
RESERVED2
Reserved2
24
32
read-write
INTR_MASKED_STATUS_REG
Interrupt masked status register
0x2C
32
read-only
n
0x0
ADC_FIFO_AFULL_MASKED
Masked Interrupt. Set when ADC FIFO occupancy greater than ADC FIFO threshold
4
5
read-only
ADC_FIFO_FULL_MASKED
Masked Interrupt. Set when ADC FIFO is full.
3
4
read-only
ADC_FIFO_OVERFLOW_MASKED
Masked Interrupt. Set when a write attempt is made to ADC FIFO when the FIFO is already full.
5
6
read-only
ADC_THRESHOLD_DETECTION_INTR_MASKED
Masked Interrupt. This bit is set when ADC threshold matches with the programmed conditions
0
1
read-only
DAC_FIFO_AEMPTY_MASKED
Masked Interrupt. Set when the FIFO occupancy less than equal to DAC FIFO threshold.
2
3
read-only
DAC_FIFO_EMPTY_MASKED
Masked Interrupt.Set when DAC FIFO is empty
1
2
read-only
DAC_FIFO_UNDERRUN_MASKED
Masked Interrupt. Set when a read is done on DAC FIFO when the FIFO is empty.
6
7
read-only
FIRST_MEM_SWITCH_INTR_MASKED
Masked Interrupt status indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation
7
23
read-only
RESERVED1
Reserved1
23
32
read-only
INTR_MASK_REG
Mask interrupt register
0x24
32
read-write
n
0x0
ADC_FIFO_AFULL_INTR_MASK
When Cleared, adc FIFO afull interrupt will be unmasked
4
5
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
ADC_FIFO_FULL_INTR_MASK
When Cleared, adc FIFO full interrupt will be unmasked
3
4
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
ADC_FIFO_OVERFLOW_INTR_MASK
When Cleared, dac FIFO underrun interrupt will be unmasked
5
6
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
DAC_FIFO_AEMPTY_INTR_MASK
When Cleared, adc FIFO full interrupt will be unmasked
2
3
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
DAC_FIFO_EMPTY_INTR_MASK
When Cleared, dac_FIFO_empty interrupt will be unmasked
1
2
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
DAC_FIFO_UNDERRUN_INTR_MASK
When Cleared, dac FIFO underrun interrupt will be unmasked
6
7
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
FIRST_MEM_SWITCH_INTR_MASK
When Cleared, first_mem_switch_intr will be unmasked
7
23
read-write
RESERVED1
Reserved1
23
32
read-write
THRESHOLD_DETECTION_INTR_EN
When Cleared, threshold detection interrupt will be unmasked
0
1
read-write
UNMASK_EFFECT
When bit is clear unmask the interrupt
0
MASK_INTERRUPT
When bit is set mask the interrupt
1
INTR_STATUS_REG
Status interrupt register
0x28
32
read-only
n
0x0
ADC_FIFO_AFULL
Set when ADC FIFO occupancy less than or equal to ADC FIFO threshold
4
5
read-only
ADC_FIFO_FULL
Set when ADC FIFO is full,This bit gets cleared when data is read from the FIFO
3
4
read-only
ADC_FIFO_OVERFLOW
Set when a write attempt is made to ADC FIFO when the FIFO is already full
5
6
read-only
ADC_THRESHOLD_DETECTION_INTR
This bit is set when ADC threshold matches with the programmed conditions This will be be cleared as soon as this interrupt is acknowledged by processor
0
1
read-only
DAC_FIFO_AEMPTY
Set when the FIFO occupancy grater than or equal to DAC FIFO threshold.
2
3
read-only
DAC_FIFO_EMPTY
Set when DAC FIFO is empty. This bit gets cleared when the DAC FIFO at least a single sample is available in DAC FIFO
1
2
read-only
DAC_FIFO_UNDERRUN
Set when a read is done on DAC FIFO when the FIFO is empty
6
7
read-only
FIRST_MEM_SWITCH_INTR
Interrupt indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation
7
23
read-only
RESERVED1
Reserved1
23
32
read-only
TS_PTAT_ENABLE
This register is enable PTAT for temperature sensor
0x1E0
32
read-write
n
0x0
RESERVED1
Reserved1
1
32
read-write
TS_PTAT_EN
BJT based Temperature sensor
0
1
read-write
Disable
Disable PTAT bit
0
Enable
Enable PTAT bit
1
VAD_BBP_ID
This register explain VDD BBP ID
0x1D0
32
read-write
n
0x0
AUX_ADC_BPP_EN
Enable Indication for BBP
5
6
read-write
BPP_EN
Enables Aux-ADC samples to BBP
4
5
read-write
BPP_ID
Channel id for bbp samples.
0
4
read-write
DISCONNET_MODE
Per channel discontinuous mode enable signal. When discontinuous mode is enabled, data is sampled only once from that channel and the enable bit is reset to 0.
16
32
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
RESERVED2
13
16
read-write
VAD_EN
Enable VAD
12
13
read-write
VAD_ID
Enable VAD identification
8
12
read-write
CAN
The DCAN is a standalone CAN (Controller Area Network) controller widely used in automotive and industrial applications.
CAN
0x0
0x0
0x1F
registers
n
CAN1
66
ACR
ACCEPTANCE CODE REGISTER
0x10
32
read-write
n
0x0
0x0
ACR0
The acceptance code registers contains bit patterns of messages to be received
0
8
read-write
ACR1
The acceptance code registers contains bit patterns of messages to be received
8
16
read-write
ACR2
The acceptance code registers contains bit patterns of messages to be received
16
24
read-write
ACR3
The acceptance code registers contains bit patterns of messages to be received
24
32
read-write
ALC
ARBITRATION LOST CODE CAPTURE REGISTER
0x1B
8
read-only
n
0x0
0x0
ALC
Arbitration Lost Capture
0
5
read-only
RESERVED1
Reserved1
5
8
read-only
AMR
ACCEPTANCE MASK REGISTER
0x14
32
read-write
n
0x0
0x0
AMR0
Acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
0
8
read-write
AMR1
acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
8
16
read-write
AMR2
acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
16
24
read-write
AMR3
acceptance mask registers defines which bit positions will be compared and which ones are do not care. Setting certain AMR bit define corresponding bit in ACR as do not care.
24
32
read-write
BTIM0
BUS TIMING REGISTER 0
0x6
8
read-write
n
0x0
0x0
BRP
Baud Rate Pre scaler
0
6
read-write
SJW
Synchronization Jump Width
6
8
read-write
BTIM1
BUS TIMING REGISTER 1.define the length of bit period, location of the sample point and number of samples to be taken at each sample point
0x7
8
read-write
n
0x0
0x0
SAM
Number of bus level samples
7
8
read-write
Disable
bus level is sampled once
0
Enable
bus level is sampled three times
1
TSEG1
Number of clock cycles per Time Segment 1
0
4
read-write
TSEG2
Number of clock cycles per Time Segment 1
4
7
read-write
CMR
Command Register
0x1
8
write-only
n
0x0
0x0
AT
Abort Transmission
1
2
write-only
RESERVED1
Reserved1
0
1
write-only
RESERVED2
Reserved2
4
8
write-only
TR
Transmit Request
2
3
write-only
Disable
NONE
0
Enable
initiates frame transmission by Bit Stream Processor
01
ECC
ERROR CODE CAPTURE REGISTER
0x18
8
read-only
n
0x0
0x0
ACKER
Acknowledgement error occurred
4
5
read-only
BER
Bit Error occurred
0
1
read-only
CRCER
CRC error occurred
2
3
read-only
EDIR
direction of transfer while error occurred
5
6
read-only
Disable
Transmission
0
Enable
Reception
1
FRMER
Frame error occurred
3
4
read-only
RXWRN
set when RXERR counter is greater than or equal to 96
7
8
read-only
STFER
stuff error occurred
1
2
read-only
TXWRN
set when TXERR counter is greater than or equal to 96
6
7
read-only
IMR
Interrupt Mask register.Setting appropriate bit in IMR register enables interrupt assigned to it, clearing disables this interrupt
0x4
8
read-write
n
0x0
0x0
ALIM
mask for ALI interrupt
6
7
read-write
BEIM
mask for BEI interrupt
1
2
read-write
DOIM
mask for DOI interrupt
0
1
read-write
EPIM
mask for EPI interrupt
4
5
read-write
EWIM
mask for EWI interrupt
5
6
read-write
RESERVED1
Reserved1
7
8
read-write
RIM
mask for RI interrupt
3
4
read-write
TIM
mask for TI interrupt
2
3
read-write
ISR_IACK
Interrupt Status/Acknowledge Register
0x3
8
read-write
n
0x0
0x0
ALI
Arbitration Lost Interrupt
6
7
read-write
Disable
Write 1 to ALI clears this interrupt
0
Enable
ALI (Arbitration Lost Interrupt) is activated when DCAN core lost arbitration during transmission of its own message and became a receiver.
1
BEI
Bus Error Interrupt
1
2
read-write
Disable
BEI interrupt write 1 to this bit.
0
Enable
DCAN encounters bus error while transmitting or receiving message
1
DOI
Data Overrun Interrupt
0
1
read-write
Disable
DOI interrupt write this bit with 1.
0
Enable
receive FIFO overrun occurred
1
EPI
Error Passive Interrupt
4
5
read-write
Disable
Write 1 to EPI clears the Error Passive Interrupt
0
Enable
CAN bus controller reached or exit error passive level (i.e. on state change active-to-passive or passive-to-active).
1
EWI
Error Warning Interrupt
5
6
read-write
Disable
Write 1 to EWI to clear interrupt
0
Enable
CAN bus controller reached or exit error passive level (i.e. on state change active-to-passive or passive-to-active).
1
RESERVED1
Reserved1
7
8
read-write
RI
Receive Interrupt
3
4
read-write
Disable
CPU must write RI bit with 1 (message read acknowledge), to decrement RX message counter (RMC)
0
Enable
there is at least one message in the receive FIFO.
1
TI
Transmission Interrupt
2
3
read-write
Disable
TI bit must be cleared by CPU by writing 1 to it to reset write pointer to TX RAM before next frame data will be written.
0
Enable
bit is set high after successful transmission
1
MR
Mode Register
0x0
8
read-write
n
0x0
0x0
AFM
hardware acceptance filter scheme
0
1
read-write
Dual
dual filter is used
0
Single
single filter is used
1
LOM
Listen Only Mode
1
2
read-write
Disable
Normal mode is set by writing 0 to LOM and 0to RM while in reset mode
00
Enable
Listen only mode is set by writing 1 to LOM bit and 0 to RM bit while in reset mode
01
RESERVED1
Reserved1
3
8
read-write
RM
Reset Mode
2
3
read-write
Disable
Normal mode or Listen only mode depending on LOM value
00
Enable
DCAN works in reset mode
01
RMC
Receive Message Counter
0x5
8
read-only
n
0x0
0x0
RESERVED1
Reserved1
5
8
read-only
RMC
number of stored message frames
0
5
read-only
RXBUF
RECEIVE BUFFER REGISTER
0xC
32
read-only
n
0x0
0x0
RXBUF0
Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
0
8
read-only
RXBUF1
Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
8
16
read-only
RXBUF2
Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
16
24
read-only
RXBUF3
Receive Buffer Register is used to read CAN frames received by the DCAN core from CAN network
24
32
read-only
RXERR
RECEIVE ERROR COUNTER REGISTER
0x19
8
read-only
n
0x0
0x0
RXERR
The RXERR register reflects current value of the receive error counter
0
8
read-only
SR
Status register
0x2
8
read-only
n
0x0
BS
Bus Off Status
0
1
read-only
Disable
frame reception and transmission is possible
0
Enable
node is in bus off state and cannot transmit and receive frames
01
DSO
Data Overrun Status
6
7
read-only
Disable
no overrun occurred since last clear data overrun command.
0
Enable
RX FIFO encounters overrun
1
ES
Error Status
1
2
read-only
Disable
NONE
0
Enable
At least one of CAN error counters reached error warning limit (96).
01
RBS
Data Overrun Status
7
8
read-only
Disable
no messages are in FIFO
0
Enable
at least one message is in FIFO
01
RESERVED1
Reserved1
4
5
read-only
RS
Receive Status
3
4
read-only
Disable
NONE
0
Enable
DCAN core is receiving a message.
01
TBS
Transmit Buffer Status
5
6
read-only
Disable
transmit buffer is locked for CPU (ie. message is being transmitted or transmission pending).
0
Enable
transmit buffer is released for CPU (ie. CPU may write new message into TX buffer).
01
TS
Transmit Status
2
3
read-only
Disable
NONE
0
Enable
DCAN core is transmitting a message
01
TXBUF
TRANSMIT BUFFER REGISTER
0x8
32
write-only
n
0x0
0x0
TXBUF0
Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
0
8
write-only
TXBUF1
Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
8
16
write-only
TXBUF2
Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
16
24
write-only
TXBUF3
Transmit Buffer Register is used to write CAN frame destined to send over CAN network.
24
32
write-only
TXERR
RECEIVE ERROR COUNTER REGISTER
0x1A
8
read-only
n
0x0
0x0
TXERR
The TXERR register reflects current value of the transmit error counter
0
8
read-only
CCI
CCI module helps external memories and peripherals to communicate with internal AHB bus with less number of pins
CCI
0x0
0x0
0x20C
registers
n
CCI
71
CONTROL
CCI control register
0x0
32
read-write
n
0x0
ADDR_WIDTH_CONFIG
address width configuration of AHB slave during address phase
6
8
read-write
CCI_CTRL_ENABLE
configurable time out value for slave response.
31
32
read-write
DISABLE_TIME_OUT_FOR_DATA_ACCESS
configurable time out value for slave response.
29
30
read-write
EBT_S
Support for Early Burst Termination
5
6
read-write
ENABLED_SLAVES
Indicates Slaves enable.
2
5
read-write
MODE
This bit represents mode of the interface
9
12
read-write
NUM_SLAVES
Indicates the number of slaves
0
2
read-write
RESERVED1
reserved1
12
13
read-write
RESERVED2
reserved2
26
29
read-write
SELECT_TIME_OUT_INTR_OR_MSG_INTR
configurable time out value for slave response.
30
31
read-write
SLAVE_PRIORITY
This bits will represents priority of the slaves
13
16
read-write
TIME_OUT_PRG
configurable time out value for slave response.
16
26
read-write
TRANSLATE_ENABLE
translation enable
8
9
read-write
FIFO_THRESHOLD_REG
CCI fifo threshold
0x200
32
read-write
n
0x0
0x0
FIFO_AEMPTY_THRESHOLD
ALMOST empty threshold
5
10
read-write
FIFO_AFULL_THRESHOLD
ALMOST full threshold
0
5
read-write
RESERVED1
RESERVED1
10
32
read-write
LSB_A_S1
Lower Address of slave 0 supported
0x4
32
read-write
n
0x0
0x0
LOWER_ADDRESS
Lower Address of slave 0 supported. Make sure that slave0 is enabled.
0
32
read-write
LSB_A_S2
LOWER Address of slave 0 supported
0x8
32
read-write
n
0x0
0x0
LOWER_ADDRESS
Lower Address of slave 1 supported. Make sure that slave1 is enabled.
0
32
read-write
MODE_INTR_STATUS
Interrupt Status
0x28
32
read-write
n
0x0
0x0
INTR_CLEAR
By setting this bits will clear the interrupt status
3
5
read-write
INTR_STATUS
These bits will represents the status of the interrupt in read mode
11
13
read-only
RESERVED1
Reserved1
0
3
read-write
RESERVED2
Reserved2
5
11
read-write
RESERVED3
RESER
13
32
read-write
MSB_A_S1
upper Address of slave 0 supported
0x10
32
read-write
n
0x0
0x0
HIGHER_ADDRESS
Higher Address of slave 0 supported. Make sure that slave0 is enabled.
0
32
read-write
MSB_A_S2
UPPER Address of slave 0 supported
0x14
32
read-write
n
0x0
0x0
HIGHER_ADDRESS
Higher Address of slave 1 supported. Make sure that slave1 is enabled.
0
32
read-write
PREFETCH_CTRL
CCI prefetch control register
0x208
32
read-write
n
0x0
0x0
CCI_2X_CLK_ENABLE_FOR_DDR_MODE
It is an enable for CCI 2x clock in DDR mode
1
2
read-write
CCI_PREFETCH_EN
cci pre-fetch enables on AHB read operation.
0
1
read-write
RESERVED1
Reserved1
2
32
read-write
TRANS_ADDRESS
cci trans address
0x204
32
read-write
n
0x0
0x0
TRANSLATION_ADDRESS
Address offset for translation address
1
32
read-write
TRANSLATION_ADDRESS_VALID
Translation is enabled or not
0
1
read-write
Enable
Translation is enabled
0
Disable
Translation is not enabled
1
CRC
CRC is used in all wireless communication as a first data integrity check
CRC
0x0
0x0
0x3C
registers
n
DIN_CTRL_RESET_REG
Input data control set register
0x2C
32
read-write
n
0x0
0x0
DIN_WIDTH_FROM_CNT
Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits).
6
7
read-write
Disable
write 0 No effect read 0 Din width does not consider cnt value.This overrides the din_width_from_reg
0
Enable
write 1 Din width will be taken from both apb and cnt value. read 1 Din width is from ULI and cnt value.
1
DIN_WIDTH_FROM_REG
Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data.
5
6
read-write
Disable
write 0 No effect read 0 Din valid width is not taken from reg
0
Enable
write 1 Din valid width will be taken from reg. read 1 Din valid width is taken from reg.
1
DIN_WIDTH_REG
Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits.
0
5
read-write
FIFO_AEMPTY_THRESHOLD
FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value.
24
28
read-write
FIFO_AFULL_THRESHOULD
FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value
28
32
read-write
RESERVED1
Reserved for future use.
8
9
read-write
RESERVED2
Reserved for future use.
9
24
read-write
USE_SWAPPED_DIN
Use bit swapped input data. If this is set input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine.
7
8
read-write
Disable
write 0 No effect read 0 Direct write data is filled in to FIFO.
0
Enable
write 1 Bit swapped data will be filled in to FIFO read 1 Bit swapped data is filled in to FIFO
1
DIN_CTRL_SET
Input data control set register
0x28
32
read-write
n
0x0
0x0
DIN_WIDTH_FROM_CNT
Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits).
6
7
read-write
Disable
write 0 No effect read 0 Din width does not consider cnt value.This overrides the din_width_from_reg
0
Enable
write 1 Din width will be taken from both apb and cnt value. read 1 Din width is from ULI and cnt value.
1
DIN_WIDTH_FROM_REG
Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data.
5
6
read-write
Disable
write 0 No effect read 0 Din valid width is not taken from reg
0
Enable
write 1 Din valid width will be taken from reg. read 1 Din valid width is taken from reg.
1
DIN_WIDTH_REG
Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits.
0
5
read-write
FIFO_AEMPTY_THRESHOLD
FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value.
24
28
read-write
FIFO_AFULL_THRESHOULD
FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value
28
32
read-write
RESERVED1
Reserved for future use.
9
24
read-write
RESET_FIFO_PTRS
Reset fifo pointer. This clears the FIFO.When this is set, FIFO will be cleared.
8
9
read-write
Disable
write 0 No effect
0
Enable
write 1 FIFO will be cleared in the next cycle.
1
USE_SWAPPED_DIN
Use bit swapped input data. If this is set, input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine.
7
8
read-write
Disable
write 0 No effect read 0 Direct write data is filled in to FIFO.
0
Enable
write 1 Bit swapped data will be filled in to FIFO read 1 Bit swapped data is filled in to FIFO
1
DIN_FIFO
Data input FIFO register
0x24
32
write-only
n
0x0
0x0
DIN_FIFO
FIFO input port is mapped to this register. Data on which the final CRC has to be computed has to be loaded to this FIFO
0
32
write-only
DIN_NUM_BYTES
Data input FIFO register
0x30
32
read-write
n
0x0
0x0
DIN_NUM_BYTES
in out data number of bytes
0
32
read-write
DIN_STS
Input data status register
0x34
32
read-only
n
0x0
FIFO_AEMPTY
FIFO almost empty indication status.
1
2
read-only
FIFO_AFULL
FIFO almost full indication status
2
3
read-only
FIFO_EMPTY
FIFO empty indication status
0
1
read-only
FIFO_FULL
FIFO full indication status
3
4
read-only
FIFO_OCC
FIFO occupancy
4
10
read-only
RESERVED1
Reserved for future use.
10
32
read-only
GEN_CTRL_RESET
General control reset register
0x4
32
read-write
n
0x0
RESERVED1
Reserved for future use.
0
32
read-write
GEN_CTRL_SET_REG
General control set register
0x0
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use.
1
32
read-write
SOFT_RST
Soft reset. This clears the FIFO and settles all the state machines to their IDLE
0
1
read-write
Disable
No effect
0
Enable
Soft reset will be triggered.
1
GEN_STS
General status register
0x8
32
read-only
n
0x0
CALC_DONE
When the computation of final CRC with the data out of fifo, this will get set to 1 otherwise 0
0
1
read-only
DIN_NUM_BYTES_DONE
When number of bytes requested for computation of final CRC is read from fifo by internal FSM, this will get set to 1 otherwise 0.
1
2
read-only
RESERVED1
Reserved for future use.
2
32
read-only
LFSR_INIT_CTRL_RESET
LFSR state initialization control reset register
0x20
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use.
0
1
read-write
RESERVED2
Reserved for future use.
1
2
read-write
RESERVED3
Reserved for future use.
3
32
read-write
USE_SWAPPED_INIT_VAL
Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state
2
3
read-write
Disable
write 0 No effect read 0 use_swapped_init_val is disabled.
0
Enable
write 1 use_swapped_init_val will be enabled read 1 use_swapped_init_val is enabled
1
LFSR_INIT_CTRL_SET
LFSR state initialization control set register
0x1C
32
read-write
n
0x0
0x0
CLEAR_LFSR
Clear LFSR state. When this is set, LFSR state is cleared to 0
0
1
read-write
Disable
No effect
0
Enable
LFSR state will be cleared in next cycle
1
INIT_LFSR
Initialize LFSR state. When this is set LFSR state will be initialized with LFSR_INIT_VAL/bit swapped LFSR_INIT_VAL in the next cycle
1
2
read-write
Disable
No effect
0
Enable
Initialization will be done in next cycle
1
RESERVED1
Reserved for future use.
3
32
read-write
USE_SWAPPED_INIT_VAL
Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state
2
3
read-write
Disable
write 0 No effect read 0 use_swapped_init_val is disabled.
0
Enable
write 1 use_swapped_init_val will be enabled read 1 use_swapped_init_val is enabled
1
LFSR_INIT_VAL
LFSR initial value
0x18
32
read-write
n
0x0
0x0
LFSR_INIT
This holds LFSR initialization value. When ever LFSR needs to be initialized, this has to be updated with the init value and trigger init_lfsr in LFSR_INIT_CTRL_SET register. For example, in WiFi case, 0xffffffff is used as init value of LFSR.
0
32
read-write
LFSR_STATE
LFSR state register
0x38
32
read-write
n
0x0
LFSR_STATE
If LFSR dynamic loading is required this can be used for writing the LFSR state directly.
0
32
read-write
POLYNOMIAL
This register holds the polynomial with which the final CRC is computed.
0xC
32
read-write
n
0x0
0x0
POLYNOMIAL
Polynomial register. This register holds the polynomial with which the final CRC is computed.When write Polynomial will be updated.When read read polynomial.
0
32
read-write
POLYNOMIAL_CTRL_RESET
Polynomial control set register
0x14
32
read-write
n
0x0
0x0
POLYNOMIAL_WIDTH_SET
Polynomial width reset. If a new width has to be configured, clear the existing length first by writing 0x1f. When read, actual polynomial width is read.
0
5
read-write
RESERVED1
Reserved for future use.
5
32
read-write
POLYNOMIAL_CTRL_SET
Polynomial control set register
0x10
32
read-write
n
0x0
0x0
POLYNOMIAL_WIDTH_SET
Polynomial width set. Number of bits/width of the polynomial has to be written here for the computation of final CRC. If a new width has to be configured, clear the existing length first by writing 0x1f in polynomial_ctrl_reset register. When read, actual polynomial width is read.
0
5
read-write
RESERVED1
Reserved for future use.
5
32
read-write
CT0
Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock
CT
0x0
0x0
0xB0
registers
n
CT
34
CT_CAPTURE_COUNTER_AND_EVENT
Capture counter AND event register
0x90
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
CAPTURE_COUNTER_0_AND_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_COUNTER_EVENT_SEL
Capture counter event select register
0x8C
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter
0
6
read-write
CAPTURE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_CAPTURE_COUNTER_OR_EVENT
Capture counter OR event register
0x94
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event
0
4
read-write
CAPTURE_COUNTER_0_OR_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_REG
Capture Register
0x20
32
read-only
n
0x0
COUNTER_0_CAPTURE
This is a latched value of counter lower part when the selected capture_event occurs
0
16
read-only
COUNTER_1_CAPTURE
This is a latched value of counter upper part when the selected capture_event occurs
16
32
read-only
CT_CONTINUE_COUNTER_AND_EVENT
Continue counter AND event register
0x60
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event.
0
4
read-write
CONTINUE_COUNTER_0_AND_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CONTINUE_COUNTER_EVENT_SEL
Continue counter event select register
0x5C
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter
0
6
read-write
CONTINUE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid.
16
22
read-write
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
CT_CONTINUE_COUNTER_OR_EVENT
Continue counter OR event register
0x64
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event
0
4
read-write
CONTINUE_COUNTER_0_OR_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_COUNTER_REG
Counter Register
0x24
32
read-write
n
0x0
COUNTER0
This holds the value of counter-0
0
16
read-only
COUNTER1
This holds the value of counter-1
16
32
read-only
CT_GEN_CTRL_RESET_REG
General control reset register
0x4
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
1
2
read-only
RESERVED2
Reserved2
3
4
read-only
RESERVED3
Reserved3
6
7
read-only
RESERVED4
Reserved4
8
17
read-only
RESERVED5
Reserved5
17
18
read-only
RESERVED6
Reserved6
19
20
read-only
RESERVED7
Reserved7
22
23
read-only
RESERVED8
Reserved8
24
32
read-only
CT_GEN_CTRL_SET_REG
General control set register
0x0
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
6
7
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_0 will be active. If Read:Read should always return 0
1
COUNTER_0_TRIG_FRM_REG
This enables the counter to run/active
3
4
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active If Read:Read should always return 0
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
22
23
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active. If Read:Read should always return 0
1
COUNTER_1_TRIG_FRM
This enables the counter to run/active
19
20
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be active If Read:Always should return 0
1
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
8
17
read-write
RESERVED2
Reserved2
24
32
read-write
SOFT_RESET_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
1
2
read-write
Disable
If Write: No effect If Read: Always should return 0
0
Enable
If Write: Counter_1 will be reset If Read: Always should return 0
1
SOFT_RESET_COUNTER_1_FRM_REG
This resets the counter on the write
17
18
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be reset If Read:Always should return 0
1
CT_HALT_COUNTER_AND_EVENT
Halt counter AND event register
0x78
32
read-write
n
0x0
0x0
HALT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
HALT_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
HALT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_HALT_COUNTER_EVENT_SEL
Halt counter event select register
0x74
32
read-write
n
0x0
0x0
HALT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
0
6
read-write
HALT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
7
16
read-only
RESERVED2
Reserved2
23
32
read-only
RESUME_FROM_HALT_COUNTER_0
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
6
7
write-only
RESUME_FROM_HALT_COUNTER_1
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
22
23
write-only
CT_HALT_COUNTER_OR_EVENT
Halt counter OR event register
0x7C
32
read-write
n
0x0
0x0
HALT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event
0
4
read-write
HALT_COUNTER_0_OR_VLD
none
8
12
read-write
HALT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_AND_EVENT
Increment counter AND event register
0x84
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
INCREMENT_COUNTER_0_AND_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_EVENT_SEL
Increment counter event select register
0x80
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter
0
6
read-write
INCREMENT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INCREMENT_COUNTER_OR_EVENT
Increment counter OR event register
0x88
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event
0
4
read-write
INCREMENT_COUNTER_0_OR_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED4
Reserved4
20
24
read-only
RESERVED5
Reserved5
28
32
read-only
CT_INTER_UNMASK
Interrupts unmask
0x10
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt unmask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt unmask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt unmask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt unmask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt unmask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt unmask signal
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt unmask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt unmask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_INTR_ACK
Interrupt clear/ack register
0x14
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt ack signal.
3
4
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_0_IS_ZERO_L
Interrupt ack signal.
2
3
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_PEAK_L
Interrupt ack signal.
19
20
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_ZERO_L
Interrupt ack signal.
18
19
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_0_FULL_L
Interrupt ack signal.
1
2
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_1_FULL_L
Interrupt ack signal.
17
18
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_0_L
Interrupt ack signal.
0
1
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_1_L
Interrupt ack signal.
16
17
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-write
CT_INTR_AND_EVENT
Interrupt AND Event Register
0xA8
32
read-write
n
0x0
0x0
INTR_0_AND_EVENT
None
0
4
read-write
INTR_0_AND_VLD
None
8
12
read-write
INTR_1_AND_EVENT
None
16
20
read-write
INTR_1_AND_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_EVENT_SEL
Interrupt Event Select Register
0xA4
32
read-write
n
0x0
0x0
INTR_EVENT_SEL_0
For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
INTR_EVENT_SEL_1
For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INTR_MASK
Interrupts mask
0xC
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt mask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt mask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt mask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt mask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt mask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt mask signal.
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt mask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt mask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-write
RESERVED2
Reserved2
20
32
read-write
CT_INTR_OR_EVENT_REG
Interrupt OR Event Register
0xAC
32
read-write
n
0x0
0x0
INTR_0_OR_EVENT
None
0
4
read-write
INTR_0_OR_VLD
None
8
12
read-write
INTR_1_OR_EVENT
None
16
20
read-write
INTR_1_OR_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_STS
Interrupt status
0x8
32
read-only
n
0x0
COUNTER_0_IS_PEAK_L
Counter 0 hit peak (MATCH) in active mode.
3
4
read-only
COUNTER_0_IS_ZERO_L
Counter 0 hit zero in active mode.
2
3
read-only
COUNTER_1_IS_PEAK_L
Counter 1 hit peak (MATCH) in active mode.
19
20
read-only
COUNTER_1_IS_ZERO_L
Counter 1 hit zero in active mode.
18
19
read-only
FIFO_0_FULL_L
Indicates the FIFO full signal of channel-0
1
2
read-only
FIFO_1_FULL_L
Indicates the FIFO full signal of channel-1
17
18
read-only
INTR_0_L
Indicates the FIFO full signal of channel-0
0
1
read-only
INTR_1_L
Indicates the FIFO full signal of channel-1
16
17
read-only
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_MATCH_BUF_REG
Match Buffer register
0x1C
32
read-write
n
0x0
0x0
COUNTER_0_MATCH_BUF
This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0.
0
16
read-write
COUNTER_1_MATCH_BUF
This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0.
16
32
read-write
CT_MATCH_REG
Match value register
0x18
32
read-write
n
0x0
0x0
COUNTER_0_MATCH
This will be used as lower match
0
16
read-write
COUNTER_1_MATCH
This will be used as upper match
16
32
read-write
CT_OCU_COMPARE2_NXT_REG
PWM compare next register
0x40
32
read-write
n
0x0
0x0
OCU_COMPARE2_NXT_COUNTER0
OCU output should be high for counter 1
0
16
read-write
OCU_COMPARE2_NXT_COUNTER1
PWM output should be high for counter 0
16
32
read-write
CT_OCU_COMPARE2_REG
OCU Compare2 Register
0x30
32
read-write
n
0x0
0x0
OCU_COMPARE2_0_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE2_1_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_COMPARE_NXT_REG
PWM compare next register
0x38
32
read-write
n
0x0
0x0
OCU_COMPARE_NXT_COUNTER0
PWM output should be high for counter 0
16
32
read-write
OCU_COMPARE_NXT_COUNTER1
OCU output should be high for counter 1
0
16
read-write
CT_OCU_COMPARE_REG
OCU Compare Register
0x2C
32
read-write
n
0x0
0x0
OCU_COMPARE_0_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE_1_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_CTRL_REG
OCU control register
0x28
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
6
9
read-write
MAKE_OUTPUT_0_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
9
12
read-write
MAKE_OUTPUT_1_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
22
25
read-write
MAKE_OUTPUT_1_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
25
28
read-write
OCU_0_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 0
4
5
read-write
OCU_0_MODE_8_16
Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode
5
6
read-write
OCU_1_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 1
20
21
read-write
OCU_1_MODE_8_16_MODE
Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode
21
22
read-write
OUTPUT_1_IS_OCU
Indicates whether the output is in OCU mode or not for channel 1
16
17
read-write
OUTPUT_IS_OCU_0
Indicates whether the output is in OCU mode or not for channel-0
0
1
read-write
RESERVED1
Reserved1
12
16
read-write
RESERVED2
Reserved2
28
32
read-write
SYNC_WITH_0
Indicates whether the other channel is in sync with this channel
1
4
read-write
SYNC_WITH_1
Indicates whether the other channel is in sync with this channel
17
20
read-write
CT_OCU_SYNC_REG
OCU Synchronization Register
0x34
32
read-write
n
0x0
0x0
OCU_SYNC_CHANNEL0_REG
Starting point of channel 0 for synchronization purpose
0
16
read-write
OCU_SYNC_CHANNEL1_REG
Starting point of channel 1 for synchronization purpose
16
32
read-write
CT_OUTPUT_AND_EVENT_REG
Output AND event Register
0x9C
32
read-write
n
0x0
0x0
OUTPUT_0_AND_EVENT
AND expression for AND event in output Counter_0 event.
0
4
read-write
OUTPUT_0_AND_VLD
AND expression for AND event in output Counter_0 event.
8
12
read-write
OUTPUT_1_AND_EVENT
AND expression for AND event in output Counter_1 event.
16
20
read-write
OUTPUT_1_AND_VLD
AND expression for AND event in output Counter_1 event.
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_OUTPUT_EVENT_SEL
Output event select register
0x98
32
read-write
n
0x0
0x0
OUTPUT_EVENT_SEL_0
For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
OUTPUT_EVENT_SEL_1
For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_OUTPUT_OR_EVENT
Output OR event Register
0xA0
32
read-write
n
0x0
0x0
OUTPUT_0_OR_EVENT
OR expression for OR event in output Counter_0 event
0
4
read-write
OUTPUT_0_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
8
12
read-write
OUTPUT_1_OR_EVENT
OR expression for OR event in output Counter_0 event
16
20
read-write
OUTPUT_1_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_START_COUNTER_AND_EVENT
Start counter AND event register
0x54
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event
0
4
read-write
START_COUNTER_0_AND_VLD
none
8
12
read-write
START_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid
16
20
read-write
START_COUNTER_1_AND_VLD
none
24
28
read-write
CT_START_COUNTER_EVENT_SEL
Start counter event select register
0x50
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
START_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter
0
6
read-write
START_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description
16
22
read-write
CT_START_COUNTER_OR_EVENT
Start counter OR event register
0x58
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event
0
4
read-write
START_COUNTER_0_OR_VLD
none
8
12
read-write
START_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid.
16
20
read-write
START_COUNTER_1_OR_VLD
none
24
28
read-write
CT_STOP_COUNTER_AND_EVENT
Stop counter AND event register
0x6C
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
STOP_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
STOP_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_AND_VLD
none
24
28
read-write
CT_STOP_COUNTER_EVENT_SEL
Stop counter event select register
0x68
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
STOP_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter
0
6
read-write
STOP_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
CT_STOP_COUNTER_OR_EVENT
Stop counter OR event register
0x70
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event
0
4
read-write
STOP_COUNTER_0_OR_VLD
none
8
12
read-write
STOP_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_OR_VLD
none
24
28
read-write
CT_WFG_CTRL_REG
WFG control register
0x3C
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_TGL_0_SEL
Check the counter ocus possibilities for description for channel 0.
0
3
read-write
MAKE_OUTPUT_0_TGL_1_SEL
Check the counter ocus possibilities for description for channel 0.
3
6
read-write
MAKE_OUTPUT_1_TGL_0_SEL
Check the counter ocus possibilities for description for channel 1.
16
19
read-write
MAKE_OUTPUT_1_TGL_1_SEL
Check the counter ocus possibilities for description for channel 1.
19
22
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
22
24
read-write
WFG_TGL_CNT_0_PEAK
WFG mode output toggle count clock for channel 0.
8
16
read-write
WFG_TGL_CNT_1_PEAK
WFG mode output toggle count clock for channel 1
24
32
read-write
CT1
Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock
CT
0x0
0x0
0xB0
registers
n
CT
34
CT_CAPTURE_COUNTER_AND_EVENT
Capture counter AND event register
0x90
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
CAPTURE_COUNTER_0_AND_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_COUNTER_EVENT_SEL
Capture counter event select register
0x8C
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter
0
6
read-write
CAPTURE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_CAPTURE_COUNTER_OR_EVENT
Capture counter OR event register
0x94
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event
0
4
read-write
CAPTURE_COUNTER_0_OR_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_REG
Capture Register
0x20
32
read-only
n
0x0
COUNTER_0_CAPTURE
This is a latched value of counter lower part when the selected capture_event occurs
0
16
read-only
COUNTER_1_CAPTURE
This is a latched value of counter upper part when the selected capture_event occurs
16
32
read-only
CT_CONTINUE_COUNTER_AND_EVENT
Continue counter AND event register
0x60
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event.
0
4
read-write
CONTINUE_COUNTER_0_AND_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CONTINUE_COUNTER_EVENT_SEL
Continue counter event select register
0x5C
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter
0
6
read-write
CONTINUE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid.
16
22
read-write
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
CT_CONTINUE_COUNTER_OR_EVENT
Continue counter OR event register
0x64
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event
0
4
read-write
CONTINUE_COUNTER_0_OR_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_COUNTER_REG
Counter Register
0x24
32
read-write
n
0x0
COUNTER0
This holds the value of counter-0
0
16
read-only
COUNTER1
This holds the value of counter-1
16
32
read-only
CT_GEN_CTRL_RESET_REG
General control reset register
0x4
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
1
2
read-only
RESERVED2
Reserved2
3
4
read-only
RESERVED3
Reserved3
6
7
read-only
RESERVED4
Reserved4
8
17
read-only
RESERVED5
Reserved5
17
18
read-only
RESERVED6
Reserved6
19
20
read-only
RESERVED7
Reserved7
22
23
read-only
RESERVED8
Reserved8
24
32
read-only
CT_GEN_CTRL_SET_REG
General control set register
0x0
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
6
7
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_0 will be active. If Read:Read should always return 0
1
COUNTER_0_TRIG_FRM_REG
This enables the counter to run/active
3
4
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active If Read:Read should always return 0
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
22
23
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active. If Read:Read should always return 0
1
COUNTER_1_TRIG_FRM
This enables the counter to run/active
19
20
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be active If Read:Always should return 0
1
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
8
17
read-write
RESERVED2
Reserved2
24
32
read-write
SOFT_RESET_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
1
2
read-write
Disable
If Write: No effect If Read: Always should return 0
0
Enable
If Write: Counter_1 will be reset If Read: Always should return 0
1
SOFT_RESET_COUNTER_1_FRM_REG
This resets the counter on the write
17
18
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be reset If Read:Always should return 0
1
CT_HALT_COUNTER_AND_EVENT
Halt counter AND event register
0x78
32
read-write
n
0x0
0x0
HALT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
HALT_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
HALT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_HALT_COUNTER_EVENT_SEL
Halt counter event select register
0x74
32
read-write
n
0x0
0x0
HALT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
0
6
read-write
HALT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
7
16
read-only
RESERVED2
Reserved2
23
32
read-only
RESUME_FROM_HALT_COUNTER_0
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
6
7
write-only
RESUME_FROM_HALT_COUNTER_1
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
22
23
write-only
CT_HALT_COUNTER_OR_EVENT
Halt counter OR event register
0x7C
32
read-write
n
0x0
0x0
HALT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event
0
4
read-write
HALT_COUNTER_0_OR_VLD
none
8
12
read-write
HALT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_AND_EVENT
Increment counter AND event register
0x84
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
INCREMENT_COUNTER_0_AND_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_EVENT_SEL
Increment counter event select register
0x80
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter
0
6
read-write
INCREMENT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INCREMENT_COUNTER_OR_EVENT
Increment counter OR event register
0x88
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event
0
4
read-write
INCREMENT_COUNTER_0_OR_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED4
Reserved4
20
24
read-only
RESERVED5
Reserved5
28
32
read-only
CT_INTER_UNMASK
Interrupts unmask
0x10
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt unmask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt unmask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt unmask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt unmask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt unmask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt unmask signal
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt unmask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt unmask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_INTR_ACK
Interrupt clear/ack register
0x14
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt ack signal.
3
4
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_0_IS_ZERO_L
Interrupt ack signal.
2
3
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_PEAK_L
Interrupt ack signal.
19
20
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_ZERO_L
Interrupt ack signal.
18
19
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_0_FULL_L
Interrupt ack signal.
1
2
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_1_FULL_L
Interrupt ack signal.
17
18
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_0_L
Interrupt ack signal.
0
1
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_1_L
Interrupt ack signal.
16
17
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-write
CT_INTR_AND_EVENT
Interrupt AND Event Register
0xA8
32
read-write
n
0x0
0x0
INTR_0_AND_EVENT
None
0
4
read-write
INTR_0_AND_VLD
None
8
12
read-write
INTR_1_AND_EVENT
None
16
20
read-write
INTR_1_AND_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_EVENT_SEL
Interrupt Event Select Register
0xA4
32
read-write
n
0x0
0x0
INTR_EVENT_SEL_0
For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
INTR_EVENT_SEL_1
For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INTR_MASK
Interrupts mask
0xC
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt mask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt mask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt mask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt mask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt mask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt mask signal.
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt mask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt mask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-write
RESERVED2
Reserved2
20
32
read-write
CT_INTR_OR_EVENT_REG
Interrupt OR Event Register
0xAC
32
read-write
n
0x0
0x0
INTR_0_OR_EVENT
None
0
4
read-write
INTR_0_OR_VLD
None
8
12
read-write
INTR_1_OR_EVENT
None
16
20
read-write
INTR_1_OR_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_STS
Interrupt status
0x8
32
read-only
n
0x0
COUNTER_0_IS_PEAK_L
Counter 0 hit peak (MATCH) in active mode.
3
4
read-only
COUNTER_0_IS_ZERO_L
Counter 0 hit zero in active mode.
2
3
read-only
COUNTER_1_IS_PEAK_L
Counter 1 hit peak (MATCH) in active mode.
19
20
read-only
COUNTER_1_IS_ZERO_L
Counter 1 hit zero in active mode.
18
19
read-only
FIFO_0_FULL_L
Indicates the FIFO full signal of channel-0
1
2
read-only
FIFO_1_FULL_L
Indicates the FIFO full signal of channel-1
17
18
read-only
INTR_0_L
Indicates the FIFO full signal of channel-0
0
1
read-only
INTR_1_L
Indicates the FIFO full signal of channel-1
16
17
read-only
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_MATCH_BUF_REG
Match Buffer register
0x1C
32
read-write
n
0x0
0x0
COUNTER_0_MATCH_BUF
This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0.
0
16
read-write
COUNTER_1_MATCH_BUF
This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0.
16
32
read-write
CT_MATCH_REG
Match value register
0x18
32
read-write
n
0x0
0x0
COUNTER_0_MATCH
This will be used as lower match
0
16
read-write
COUNTER_1_MATCH
This will be used as upper match
16
32
read-write
CT_OCU_COMPARE2_NXT_REG
PWM compare next register
0x40
32
read-write
n
0x0
0x0
OCU_COMPARE2_NXT_COUNTER0
OCU output should be high for counter 1
0
16
read-write
OCU_COMPARE2_NXT_COUNTER1
PWM output should be high for counter 0
16
32
read-write
CT_OCU_COMPARE2_REG
OCU Compare2 Register
0x30
32
read-write
n
0x0
0x0
OCU_COMPARE2_0_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE2_1_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_COMPARE_NXT_REG
PWM compare next register
0x38
32
read-write
n
0x0
0x0
OCU_COMPARE_NXT_COUNTER0
PWM output should be high for counter 0
16
32
read-write
OCU_COMPARE_NXT_COUNTER1
OCU output should be high for counter 1
0
16
read-write
CT_OCU_COMPARE_REG
OCU Compare Register
0x2C
32
read-write
n
0x0
0x0
OCU_COMPARE_0_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE_1_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_CTRL_REG
OCU control register
0x28
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
6
9
read-write
MAKE_OUTPUT_0_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
9
12
read-write
MAKE_OUTPUT_1_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
22
25
read-write
MAKE_OUTPUT_1_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
25
28
read-write
OCU_0_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 0
4
5
read-write
OCU_0_MODE_8_16
Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode
5
6
read-write
OCU_1_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 1
20
21
read-write
OCU_1_MODE_8_16_MODE
Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode
21
22
read-write
OUTPUT_1_IS_OCU
Indicates whether the output is in OCU mode or not for channel 1
16
17
read-write
OUTPUT_IS_OCU_0
Indicates whether the output is in OCU mode or not for channel-0
0
1
read-write
RESERVED1
Reserved1
12
16
read-write
RESERVED2
Reserved2
28
32
read-write
SYNC_WITH_0
Indicates whether the other channel is in sync with this channel
1
4
read-write
SYNC_WITH_1
Indicates whether the other channel is in sync with this channel
17
20
read-write
CT_OCU_SYNC_REG
OCU Synchronization Register
0x34
32
read-write
n
0x0
0x0
OCU_SYNC_CHANNEL0_REG
Starting point of channel 0 for synchronization purpose
0
16
read-write
OCU_SYNC_CHANNEL1_REG
Starting point of channel 1 for synchronization purpose
16
32
read-write
CT_OUTPUT_AND_EVENT_REG
Output AND event Register
0x9C
32
read-write
n
0x0
0x0
OUTPUT_0_AND_EVENT
AND expression for AND event in output Counter_0 event.
0
4
read-write
OUTPUT_0_AND_VLD
AND expression for AND event in output Counter_0 event.
8
12
read-write
OUTPUT_1_AND_EVENT
AND expression for AND event in output Counter_1 event.
16
20
read-write
OUTPUT_1_AND_VLD
AND expression for AND event in output Counter_1 event.
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_OUTPUT_EVENT_SEL
Output event select register
0x98
32
read-write
n
0x0
0x0
OUTPUT_EVENT_SEL_0
For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
OUTPUT_EVENT_SEL_1
For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_OUTPUT_OR_EVENT
Output OR event Register
0xA0
32
read-write
n
0x0
0x0
OUTPUT_0_OR_EVENT
OR expression for OR event in output Counter_0 event
0
4
read-write
OUTPUT_0_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
8
12
read-write
OUTPUT_1_OR_EVENT
OR expression for OR event in output Counter_0 event
16
20
read-write
OUTPUT_1_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_START_COUNTER_AND_EVENT
Start counter AND event register
0x54
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event
0
4
read-write
START_COUNTER_0_AND_VLD
none
8
12
read-write
START_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid
16
20
read-write
START_COUNTER_1_AND_VLD
none
24
28
read-write
CT_START_COUNTER_EVENT_SEL
Start counter event select register
0x50
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
START_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter
0
6
read-write
START_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description
16
22
read-write
CT_START_COUNTER_OR_EVENT
Start counter OR event register
0x58
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event
0
4
read-write
START_COUNTER_0_OR_VLD
none
8
12
read-write
START_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid.
16
20
read-write
START_COUNTER_1_OR_VLD
none
24
28
read-write
CT_STOP_COUNTER_AND_EVENT
Stop counter AND event register
0x6C
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
STOP_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
STOP_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_AND_VLD
none
24
28
read-write
CT_STOP_COUNTER_EVENT_SEL
Stop counter event select register
0x68
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
STOP_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter
0
6
read-write
STOP_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
CT_STOP_COUNTER_OR_EVENT
Stop counter OR event register
0x70
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event
0
4
read-write
STOP_COUNTER_0_OR_VLD
none
8
12
read-write
STOP_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_OR_VLD
none
24
28
read-write
CT_WFG_CTRL_REG
WFG control register
0x3C
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_TGL_0_SEL
Check the counter ocus possibilities for description for channel 0.
0
3
read-write
MAKE_OUTPUT_0_TGL_1_SEL
Check the counter ocus possibilities for description for channel 0.
3
6
read-write
MAKE_OUTPUT_1_TGL_0_SEL
Check the counter ocus possibilities for description for channel 1.
16
19
read-write
MAKE_OUTPUT_1_TGL_1_SEL
Check the counter ocus possibilities for description for channel 1.
19
22
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
22
24
read-write
WFG_TGL_CNT_0_PEAK
WFG mode output toggle count clock for channel 0.
8
16
read-write
WFG_TGL_CNT_1_PEAK
WFG mode output toggle count clock for channel 1
24
32
read-write
CT2
Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock
CT
0x0
0x0
0xB0
registers
n
CT
34
CT_CAPTURE_COUNTER_AND_EVENT
Capture counter AND event register
0x90
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
CAPTURE_COUNTER_0_AND_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_COUNTER_EVENT_SEL
Capture counter event select register
0x8C
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter
0
6
read-write
CAPTURE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_CAPTURE_COUNTER_OR_EVENT
Capture counter OR event register
0x94
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event
0
4
read-write
CAPTURE_COUNTER_0_OR_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_REG
Capture Register
0x20
32
read-only
n
0x0
COUNTER_0_CAPTURE
This is a latched value of counter lower part when the selected capture_event occurs
0
16
read-only
COUNTER_1_CAPTURE
This is a latched value of counter upper part when the selected capture_event occurs
16
32
read-only
CT_CONTINUE_COUNTER_AND_EVENT
Continue counter AND event register
0x60
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event.
0
4
read-write
CONTINUE_COUNTER_0_AND_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CONTINUE_COUNTER_EVENT_SEL
Continue counter event select register
0x5C
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter
0
6
read-write
CONTINUE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid.
16
22
read-write
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
CT_CONTINUE_COUNTER_OR_EVENT
Continue counter OR event register
0x64
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event
0
4
read-write
CONTINUE_COUNTER_0_OR_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_COUNTER_REG
Counter Register
0x24
32
read-write
n
0x0
COUNTER0
This holds the value of counter-0
0
16
read-only
COUNTER1
This holds the value of counter-1
16
32
read-only
CT_GEN_CTRL_RESET_REG
General control reset register
0x4
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
1
2
read-only
RESERVED2
Reserved2
3
4
read-only
RESERVED3
Reserved3
6
7
read-only
RESERVED4
Reserved4
8
17
read-only
RESERVED5
Reserved5
17
18
read-only
RESERVED6
Reserved6
19
20
read-only
RESERVED7
Reserved7
22
23
read-only
RESERVED8
Reserved8
24
32
read-only
CT_GEN_CTRL_SET_REG
General control set register
0x0
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
6
7
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_0 will be active. If Read:Read should always return 0
1
COUNTER_0_TRIG_FRM_REG
This enables the counter to run/active
3
4
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active If Read:Read should always return 0
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
22
23
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active. If Read:Read should always return 0
1
COUNTER_1_TRIG_FRM
This enables the counter to run/active
19
20
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be active If Read:Always should return 0
1
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
8
17
read-write
RESERVED2
Reserved2
24
32
read-write
SOFT_RESET_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
1
2
read-write
Disable
If Write: No effect If Read: Always should return 0
0
Enable
If Write: Counter_1 will be reset If Read: Always should return 0
1
SOFT_RESET_COUNTER_1_FRM_REG
This resets the counter on the write
17
18
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be reset If Read:Always should return 0
1
CT_HALT_COUNTER_AND_EVENT
Halt counter AND event register
0x78
32
read-write
n
0x0
0x0
HALT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
HALT_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
HALT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_HALT_COUNTER_EVENT_SEL
Halt counter event select register
0x74
32
read-write
n
0x0
0x0
HALT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
0
6
read-write
HALT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
7
16
read-only
RESERVED2
Reserved2
23
32
read-only
RESUME_FROM_HALT_COUNTER_0
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
6
7
write-only
RESUME_FROM_HALT_COUNTER_1
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
22
23
write-only
CT_HALT_COUNTER_OR_EVENT
Halt counter OR event register
0x7C
32
read-write
n
0x0
0x0
HALT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event
0
4
read-write
HALT_COUNTER_0_OR_VLD
none
8
12
read-write
HALT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_AND_EVENT
Increment counter AND event register
0x84
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
INCREMENT_COUNTER_0_AND_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_EVENT_SEL
Increment counter event select register
0x80
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter
0
6
read-write
INCREMENT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INCREMENT_COUNTER_OR_EVENT
Increment counter OR event register
0x88
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event
0
4
read-write
INCREMENT_COUNTER_0_OR_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED4
Reserved4
20
24
read-only
RESERVED5
Reserved5
28
32
read-only
CT_INTER_UNMASK
Interrupts unmask
0x10
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt unmask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt unmask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt unmask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt unmask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt unmask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt unmask signal
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt unmask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt unmask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_INTR_ACK
Interrupt clear/ack register
0x14
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt ack signal.
3
4
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_0_IS_ZERO_L
Interrupt ack signal.
2
3
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_PEAK_L
Interrupt ack signal.
19
20
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_ZERO_L
Interrupt ack signal.
18
19
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_0_FULL_L
Interrupt ack signal.
1
2
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_1_FULL_L
Interrupt ack signal.
17
18
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_0_L
Interrupt ack signal.
0
1
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_1_L
Interrupt ack signal.
16
17
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-write
CT_INTR_AND_EVENT
Interrupt AND Event Register
0xA8
32
read-write
n
0x0
0x0
INTR_0_AND_EVENT
None
0
4
read-write
INTR_0_AND_VLD
None
8
12
read-write
INTR_1_AND_EVENT
None
16
20
read-write
INTR_1_AND_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_EVENT_SEL
Interrupt Event Select Register
0xA4
32
read-write
n
0x0
0x0
INTR_EVENT_SEL_0
For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
INTR_EVENT_SEL_1
For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INTR_MASK
Interrupts mask
0xC
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt mask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt mask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt mask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt mask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt mask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt mask signal.
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt mask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt mask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-write
RESERVED2
Reserved2
20
32
read-write
CT_INTR_OR_EVENT_REG
Interrupt OR Event Register
0xAC
32
read-write
n
0x0
0x0
INTR_0_OR_EVENT
None
0
4
read-write
INTR_0_OR_VLD
None
8
12
read-write
INTR_1_OR_EVENT
None
16
20
read-write
INTR_1_OR_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_STS
Interrupt status
0x8
32
read-only
n
0x0
COUNTER_0_IS_PEAK_L
Counter 0 hit peak (MATCH) in active mode.
3
4
read-only
COUNTER_0_IS_ZERO_L
Counter 0 hit zero in active mode.
2
3
read-only
COUNTER_1_IS_PEAK_L
Counter 1 hit peak (MATCH) in active mode.
19
20
read-only
COUNTER_1_IS_ZERO_L
Counter 1 hit zero in active mode.
18
19
read-only
FIFO_0_FULL_L
Indicates the FIFO full signal of channel-0
1
2
read-only
FIFO_1_FULL_L
Indicates the FIFO full signal of channel-1
17
18
read-only
INTR_0_L
Indicates the FIFO full signal of channel-0
0
1
read-only
INTR_1_L
Indicates the FIFO full signal of channel-1
16
17
read-only
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_MATCH_BUF_REG
Match Buffer register
0x1C
32
read-write
n
0x0
0x0
COUNTER_0_MATCH_BUF
This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0.
0
16
read-write
COUNTER_1_MATCH_BUF
This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0.
16
32
read-write
CT_MATCH_REG
Match value register
0x18
32
read-write
n
0x0
0x0
COUNTER_0_MATCH
This will be used as lower match
0
16
read-write
COUNTER_1_MATCH
This will be used as upper match
16
32
read-write
CT_OCU_COMPARE2_NXT_REG
PWM compare next register
0x40
32
read-write
n
0x0
0x0
OCU_COMPARE2_NXT_COUNTER0
OCU output should be high for counter 1
0
16
read-write
OCU_COMPARE2_NXT_COUNTER1
PWM output should be high for counter 0
16
32
read-write
CT_OCU_COMPARE2_REG
OCU Compare2 Register
0x30
32
read-write
n
0x0
0x0
OCU_COMPARE2_0_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE2_1_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_COMPARE_NXT_REG
PWM compare next register
0x38
32
read-write
n
0x0
0x0
OCU_COMPARE_NXT_COUNTER0
PWM output should be high for counter 0
16
32
read-write
OCU_COMPARE_NXT_COUNTER1
OCU output should be high for counter 1
0
16
read-write
CT_OCU_COMPARE_REG
OCU Compare Register
0x2C
32
read-write
n
0x0
0x0
OCU_COMPARE_0_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE_1_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_CTRL_REG
OCU control register
0x28
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
6
9
read-write
MAKE_OUTPUT_0_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
9
12
read-write
MAKE_OUTPUT_1_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
22
25
read-write
MAKE_OUTPUT_1_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
25
28
read-write
OCU_0_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 0
4
5
read-write
OCU_0_MODE_8_16
Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode
5
6
read-write
OCU_1_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 1
20
21
read-write
OCU_1_MODE_8_16_MODE
Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode
21
22
read-write
OUTPUT_1_IS_OCU
Indicates whether the output is in OCU mode or not for channel 1
16
17
read-write
OUTPUT_IS_OCU_0
Indicates whether the output is in OCU mode or not for channel-0
0
1
read-write
RESERVED1
Reserved1
12
16
read-write
RESERVED2
Reserved2
28
32
read-write
SYNC_WITH_0
Indicates whether the other channel is in sync with this channel
1
4
read-write
SYNC_WITH_1
Indicates whether the other channel is in sync with this channel
17
20
read-write
CT_OCU_SYNC_REG
OCU Synchronization Register
0x34
32
read-write
n
0x0
0x0
OCU_SYNC_CHANNEL0_REG
Starting point of channel 0 for synchronization purpose
0
16
read-write
OCU_SYNC_CHANNEL1_REG
Starting point of channel 1 for synchronization purpose
16
32
read-write
CT_OUTPUT_AND_EVENT_REG
Output AND event Register
0x9C
32
read-write
n
0x0
0x0
OUTPUT_0_AND_EVENT
AND expression for AND event in output Counter_0 event.
0
4
read-write
OUTPUT_0_AND_VLD
AND expression for AND event in output Counter_0 event.
8
12
read-write
OUTPUT_1_AND_EVENT
AND expression for AND event in output Counter_1 event.
16
20
read-write
OUTPUT_1_AND_VLD
AND expression for AND event in output Counter_1 event.
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_OUTPUT_EVENT_SEL
Output event select register
0x98
32
read-write
n
0x0
0x0
OUTPUT_EVENT_SEL_0
For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
OUTPUT_EVENT_SEL_1
For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_OUTPUT_OR_EVENT
Output OR event Register
0xA0
32
read-write
n
0x0
0x0
OUTPUT_0_OR_EVENT
OR expression for OR event in output Counter_0 event
0
4
read-write
OUTPUT_0_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
8
12
read-write
OUTPUT_1_OR_EVENT
OR expression for OR event in output Counter_0 event
16
20
read-write
OUTPUT_1_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_START_COUNTER_AND_EVENT
Start counter AND event register
0x54
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event
0
4
read-write
START_COUNTER_0_AND_VLD
none
8
12
read-write
START_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid
16
20
read-write
START_COUNTER_1_AND_VLD
none
24
28
read-write
CT_START_COUNTER_EVENT_SEL
Start counter event select register
0x50
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
START_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter
0
6
read-write
START_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description
16
22
read-write
CT_START_COUNTER_OR_EVENT
Start counter OR event register
0x58
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event
0
4
read-write
START_COUNTER_0_OR_VLD
none
8
12
read-write
START_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid.
16
20
read-write
START_COUNTER_1_OR_VLD
none
24
28
read-write
CT_STOP_COUNTER_AND_EVENT
Stop counter AND event register
0x6C
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
STOP_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
STOP_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_AND_VLD
none
24
28
read-write
CT_STOP_COUNTER_EVENT_SEL
Stop counter event select register
0x68
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
STOP_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter
0
6
read-write
STOP_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
CT_STOP_COUNTER_OR_EVENT
Stop counter OR event register
0x70
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event
0
4
read-write
STOP_COUNTER_0_OR_VLD
none
8
12
read-write
STOP_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_OR_VLD
none
24
28
read-write
CT_WFG_CTRL_REG
WFG control register
0x3C
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_TGL_0_SEL
Check the counter ocus possibilities for description for channel 0.
0
3
read-write
MAKE_OUTPUT_0_TGL_1_SEL
Check the counter ocus possibilities for description for channel 0.
3
6
read-write
MAKE_OUTPUT_1_TGL_0_SEL
Check the counter ocus possibilities for description for channel 1.
16
19
read-write
MAKE_OUTPUT_1_TGL_1_SEL
Check the counter ocus possibilities for description for channel 1.
19
22
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
22
24
read-write
WFG_TGL_CNT_0_PEAK
WFG mode output toggle count clock for channel 0.
8
16
read-write
WFG_TGL_CNT_1_PEAK
WFG mode output toggle count clock for channel 1
24
32
read-write
CT3
Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock
CT
0x0
0x0
0xB0
registers
n
CT
34
CT_CAPTURE_COUNTER_AND_EVENT
Capture counter AND event register
0x90
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
CAPTURE_COUNTER_0_AND_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_COUNTER_EVENT_SEL
Capture counter event select register
0x8C
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter
0
6
read-write
CAPTURE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_CAPTURE_COUNTER_OR_EVENT
Capture counter OR event register
0x94
32
read-write
n
0x0
0x0
CAPTURE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event
0
4
read-write
CAPTURE_COUNTER_0_OR_VLD
none
8
12
read-write
CAPTURE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid
16
20
read-write
CAPTURE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CAPTURE_REG
Capture Register
0x20
32
read-only
n
0x0
COUNTER_0_CAPTURE
This is a latched value of counter lower part when the selected capture_event occurs
0
16
read-only
COUNTER_1_CAPTURE
This is a latched value of counter upper part when the selected capture_event occurs
16
32
read-only
CT_CONTINUE_COUNTER_AND_EVENT
Continue counter AND event register
0x60
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event.
0
4
read-write
CONTINUE_COUNTER_0_AND_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_CONTINUE_COUNTER_EVENT_SEL
Continue counter event select register
0x5C
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter
0
6
read-write
CONTINUE_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid.
16
22
read-write
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
CT_CONTINUE_COUNTER_OR_EVENT
Continue counter OR event register
0x64
32
read-write
n
0x0
0x0
CONTINUE_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event
0
4
read-write
CONTINUE_COUNTER_0_OR_VLD
none
8
12
read-write
CONTINUE_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid
16
20
read-write
CONTINUE_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_COUNTER_REG
Counter Register
0x24
32
read-write
n
0x0
COUNTER0
This holds the value of counter-0
0
16
read-only
COUNTER1
This holds the value of counter-1
16
32
read-only
CT_GEN_CTRL_RESET_REG
General control reset register
0x4
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
1
2
read-only
RESERVED2
Reserved2
3
4
read-only
RESERVED3
Reserved3
6
7
read-only
RESERVED4
Reserved4
8
17
read-only
RESERVED5
Reserved5
17
18
read-only
RESERVED6
Reserved6
19
20
read-only
RESERVED7
Reserved7
22
23
read-only
RESERVED8
Reserved8
24
32
read-only
CT_GEN_CTRL_SET_REG
General control set register
0x0
32
read-write
n
0x0
0x0
BUF_REG_0_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
7
8
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
BUF_REG_1_EN
Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG.
23
24
read-write
Disable
If Write: No effect If Read:Buffer is not enabled and not in path.
0
Enable
If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path
1
COUNTER_0_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
6
7
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_0 will be active. If Read:Read should always return 0
1
COUNTER_0_TRIG_FRM_REG
This enables the counter to run/active
3
4
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active If Read:Read should always return 0
1
COUNTER_0_UP_DOWN
This enables the counter to run in up/down/up-down/down-up directions
4
6
read-write
00
If Write:No effect If Read:Counter_0 is in down-up counting mode
0
01
If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_0 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode
3
COUNTER_1_SYNC_TRIG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found.
22
23
read-write
Disable
If Write: No effect If Read:Read should always return 0
0
Enable
If Write:Counter_1 will be active. If Read:Read should always return 0
1
COUNTER_1_TRIG_FRM
This enables the counter to run/active
19
20
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be active If Read:Always should return 0
1
COUNTER_1_UP_DOWN
This enables the counter to run in upward direction
20
22
read-write
00
If Write:No effect If Read:Counter_1 is in down-up counting mode
0
01
If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode
1
10
If Write:Counter down direction enable If Read:Counter_1 is in down counting mode
2
11
If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode
3
COUNTER_IN_32_BIT_MODE
Counter_1 and Counter_0 will be merged and used as a single 32 bit counter
0
1
read-write
Disable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
0
Enable
If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode
1
PERIODIC_EN_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
2
3
read-write
Disable
If Write: No effect If Read: Counter_1 is not in periodic mode
0
Enable
If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode
1
PERIODIC_EN_COUNTER_1_FRM_REG
This resets the counter on the write
18
19
read-write
Disable
If Write:No effect If Read:Counter_1 is not in periodic mode
0
Enable
If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode
1
RESERVED1
Reserved1
8
17
read-write
RESERVED2
Reserved2
24
32
read-write
SOFT_RESET_COUNTER_0_FRM_REG
This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter
1
2
read-write
Disable
If Write: No effect If Read: Always should return 0
0
Enable
If Write: Counter_1 will be reset If Read: Always should return 0
1
SOFT_RESET_COUNTER_1_FRM_REG
This resets the counter on the write
17
18
read-write
Disable
If Write:No effect If Read:Always should return 0
0
Enable
If Write:Counter_1 will be reset If Read:Always should return 0
1
CT_HALT_COUNTER_AND_EVENT
Halt counter AND event register
0x78
32
read-write
n
0x0
0x0
HALT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
HALT_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
HALT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_HALT_COUNTER_EVENT_SEL
Halt counter event select register
0x74
32
read-write
n
0x0
0x0
HALT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
0
6
read-write
HALT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
7
16
read-only
RESERVED2
Reserved2
23
32
read-only
RESUME_FROM_HALT_COUNTER_0
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
6
7
write-only
RESUME_FROM_HALT_COUNTER_1
For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter
22
23
write-only
CT_HALT_COUNTER_OR_EVENT
Halt counter OR event register
0x7C
32
read-write
n
0x0
0x0
HALT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event
0
4
read-write
HALT_COUNTER_0_OR_VLD
none
8
12
read-write
HALT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid
16
20
read-write
HALT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_AND_EVENT
Increment counter AND event register
0x84
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
INCREMENT_COUNTER_0_AND_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_AND_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INCREMENT_COUNTER_EVENT_SEL
Increment counter event select register
0x80
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter
0
6
read-write
INCREMENT_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INCREMENT_COUNTER_OR_EVENT
Increment counter OR event register
0x88
32
read-write
n
0x0
0x0
INCREMENT_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event
0
4
read-write
INCREMENT_COUNTER_0_OR_VLD
none
8
12
read-write
INCREMENT_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid
16
20
read-write
INCREMENT_COUNTER_1_OR_VLD
none
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED4
Reserved4
20
24
read-only
RESERVED5
Reserved5
28
32
read-only
CT_INTER_UNMASK
Interrupts unmask
0x10
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt unmask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt unmask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt unmask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt unmask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt unmask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt unmask signal
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt unmask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt unmask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_INTR_ACK
Interrupt clear/ack register
0x14
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt ack signal.
3
4
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_0_IS_ZERO_L
Interrupt ack signal.
2
3
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_PEAK_L
Interrupt ack signal.
19
20
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
COUNTER_1_IS_ZERO_L
Interrupt ack signal.
18
19
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_0_FULL_L
Interrupt ack signal.
1
2
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
FIFO_1_FULL_L
Interrupt ack signal.
17
18
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_0_L
Interrupt ack signal.
0
1
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
INTR_1_L
Interrupt ack signal.
16
17
read-write
Disable
If Write: No effect. If Read: should be returned as this is self clear bit
0
Enable
If Write: Interrupt will be de asserted.
1
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-write
CT_INTR_AND_EVENT
Interrupt AND Event Register
0xA8
32
read-write
n
0x0
0x0
INTR_0_AND_EVENT
None
0
4
read-write
INTR_0_AND_VLD
None
8
12
read-write
INTR_1_AND_EVENT
None
16
20
read-write
INTR_1_AND_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_EVENT_SEL
Interrupt Event Select Register
0xA4
32
read-write
n
0x0
0x0
INTR_EVENT_SEL_0
For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
INTR_EVENT_SEL_1
For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_INTR_MASK
Interrupts mask
0xC
32
read-write
n
0x0
0x0
COUNTER_0_IS_PEAK_L
Interrupt mask signal.
3
4
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_0_IS_ZERO_L
Interrupt mask signal.
2
3
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_PEAK_L
Interrupt mask signal.
19
20
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
COUNTER_1_IS_ZERO_L
Interrupt mask signal.
18
19
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_0_FULL_L
Interrupt mask signal.
1
2
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
FIFO_1_FULL_L
Interrupt mask signal.
17
18
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_0_L
Interrupt mask signal.
0
1
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
INTR_1_L
Interrupt mask signal.
16
17
read-write
Disable
If Write: No effect If Read:Interrupt is masked.
0
Enable
If Write: Interrupt will be masked. If Read: Interrupt is unmasked.
1
RESERVED1
Reserved1
4
16
read-write
RESERVED2
Reserved2
20
32
read-write
CT_INTR_OR_EVENT_REG
Interrupt OR Event Register
0xAC
32
read-write
n
0x0
0x0
INTR_0_OR_EVENT
None
0
4
read-write
INTR_0_OR_VLD
None
8
12
read-write
INTR_1_OR_EVENT
None
16
20
read-write
INTR_1_OR_VLD
None
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_INTR_STS
Interrupt status
0x8
32
read-only
n
0x0
COUNTER_0_IS_PEAK_L
Counter 0 hit peak (MATCH) in active mode.
3
4
read-only
COUNTER_0_IS_ZERO_L
Counter 0 hit zero in active mode.
2
3
read-only
COUNTER_1_IS_PEAK_L
Counter 1 hit peak (MATCH) in active mode.
19
20
read-only
COUNTER_1_IS_ZERO_L
Counter 1 hit zero in active mode.
18
19
read-only
FIFO_0_FULL_L
Indicates the FIFO full signal of channel-0
1
2
read-only
FIFO_1_FULL_L
Indicates the FIFO full signal of channel-1
17
18
read-only
INTR_0_L
Indicates the FIFO full signal of channel-0
0
1
read-only
INTR_1_L
Indicates the FIFO full signal of channel-1
16
17
read-only
RESERVED1
Reserved1
4
16
read-only
RESERVED2
Reserved2
20
32
read-only
CT_MATCH_BUF_REG
Match Buffer register
0x1C
32
read-write
n
0x0
0x0
COUNTER_0_MATCH_BUF
This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0.
0
16
read-write
COUNTER_1_MATCH_BUF
This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0.
16
32
read-write
CT_MATCH_REG
Match value register
0x18
32
read-write
n
0x0
0x0
COUNTER_0_MATCH
This will be used as lower match
0
16
read-write
COUNTER_1_MATCH
This will be used as upper match
16
32
read-write
CT_OCU_COMPARE2_NXT_REG
PWM compare next register
0x40
32
read-write
n
0x0
0x0
OCU_COMPARE2_NXT_COUNTER0
OCU output should be high for counter 1
0
16
read-write
OCU_COMPARE2_NXT_COUNTER1
PWM output should be high for counter 0
16
32
read-write
CT_OCU_COMPARE2_REG
OCU Compare2 Register
0x30
32
read-write
n
0x0
0x0
OCU_COMPARE2_0_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE2_1_REG
Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_COMPARE_NXT_REG
PWM compare next register
0x38
32
read-write
n
0x0
0x0
OCU_COMPARE_NXT_COUNTER0
PWM output should be high for counter 0
16
32
read-write
OCU_COMPARE_NXT_COUNTER1
OCU output should be high for counter 1
0
16
read-write
CT_OCU_COMPARE_REG
OCU Compare Register
0x2C
32
read-write
n
0x0
0x0
OCU_COMPARE_0_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0)
0
16
read-write
OCU_COMPARE_1_REG
Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1)
16
32
read-write
CT_OCU_CTRL_REG
OCU control register
0x28
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
6
9
read-write
MAKE_OUTPUT_0_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
9
12
read-write
MAKE_OUTPUT_1_HIGH_SEL
Check counter ocus for possibilities. When this is hit output will be made high.
22
25
read-write
MAKE_OUTPUT_1_LOW_SEL
Check counter ocus for possibilities. When this is hit output will be made low.
25
28
read-write
OCU_0_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 0
4
5
read-write
OCU_0_MODE_8_16
Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode
5
6
read-write
OCU_1_DMA_MODE
Indicates whether the OCU DMA mode is active or not for channel 1
20
21
read-write
OCU_1_MODE_8_16_MODE
Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode
21
22
read-write
OUTPUT_1_IS_OCU
Indicates whether the output is in OCU mode or not for channel 1
16
17
read-write
OUTPUT_IS_OCU_0
Indicates whether the output is in OCU mode or not for channel-0
0
1
read-write
RESERVED1
Reserved1
12
16
read-write
RESERVED2
Reserved2
28
32
read-write
SYNC_WITH_0
Indicates whether the other channel is in sync with this channel
1
4
read-write
SYNC_WITH_1
Indicates whether the other channel is in sync with this channel
17
20
read-write
CT_OCU_SYNC_REG
OCU Synchronization Register
0x34
32
read-write
n
0x0
0x0
OCU_SYNC_CHANNEL0_REG
Starting point of channel 0 for synchronization purpose
0
16
read-write
OCU_SYNC_CHANNEL1_REG
Starting point of channel 1 for synchronization purpose
16
32
read-write
CT_OUTPUT_AND_EVENT_REG
Output AND event Register
0x9C
32
read-write
n
0x0
0x0
OUTPUT_0_AND_EVENT
AND expression for AND event in output Counter_0 event.
0
4
read-write
OUTPUT_0_AND_VLD
AND expression for AND event in output Counter_0 event.
8
12
read-write
OUTPUT_1_AND_EVENT
AND expression for AND event in output Counter_1 event.
16
20
read-write
OUTPUT_1_AND_VLD
AND expression for AND event in output Counter_1 event.
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_OUTPUT_EVENT_SEL
Output event select register
0x98
32
read-write
n
0x0
0x0
OUTPUT_EVENT_SEL_0
For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event
0
6
read-write
OUTPUT_EVENT_SEL_1
For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid
16
22
read-write
RESERVED1
Reserved1
6
16
read-only
RESERVED2
Reserved2
22
32
read-only
CT_OUTPUT_OR_EVENT
Output OR event Register
0xA0
32
read-write
n
0x0
0x0
OUTPUT_0_OR_EVENT
OR expression for OR event in output Counter_0 event
0
4
read-write
OUTPUT_0_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
8
12
read-write
OUTPUT_1_OR_EVENT
OR expression for OR event in output Counter_0 event
16
20
read-write
OUTPUT_1_OR_VLD
Indicates which bits in 3:0 are valid for considering OR event
24
28
read-write
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
CT_START_COUNTER_AND_EVENT
Start counter AND event register
0x54
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-only
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event
0
4
read-write
START_COUNTER_0_AND_VLD
none
8
12
read-write
START_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid
16
20
read-write
START_COUNTER_1_AND_VLD
none
24
28
read-write
CT_START_COUNTER_EVENT_SEL
Start counter event select register
0x50
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
START_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter
0
6
read-write
START_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description
16
22
read-write
CT_START_COUNTER_OR_EVENT
Start counter OR event register
0x58
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
START_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event
0
4
read-write
START_COUNTER_0_OR_VLD
none
8
12
read-write
START_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid.
16
20
read-write
START_COUNTER_1_OR_VLD
none
24
28
read-write
CT_STOP_COUNTER_AND_EVENT
Stop counter AND event register
0x6C
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_AND_EVENT
For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event
0
4
read-write
STOP_COUNTER_0_AND_VLD
Indicates which bits in 3:0 are valid for considering AND event
8
12
read-write
STOP_COUNTER_1_AND_EVENT
For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_AND_VLD
none
24
28
read-write
CT_STOP_COUNTER_EVENT_SEL
Stop counter event select register
0x68
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
6
16
read-write
RESERVED2
Reserved2
22
32
read-only
STOP_COUNTER_0_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter
0
6
read-write
STOP_COUNTER_1_EVENT_SEL
For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid
16
22
read-write
CT_STOP_COUNTER_OR_EVENT
Stop counter OR event register
0x70
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
4
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
20
24
read-only
RESERVED4
Reserved4
28
32
read-only
STOP_COUNTER_0_OR_EVENT
For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event
0
4
read-write
STOP_COUNTER_0_OR_VLD
none
8
12
read-write
STOP_COUNTER_1_OR_EVENT
For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid
16
20
read-write
STOP_COUNTER_1_OR_VLD
none
24
28
read-write
CT_WFG_CTRL_REG
WFG control register
0x3C
32
read-write
n
0x0
0x0
MAKE_OUTPUT_0_TGL_0_SEL
Check the counter ocus possibilities for description for channel 0.
0
3
read-write
MAKE_OUTPUT_0_TGL_1_SEL
Check the counter ocus possibilities for description for channel 0.
3
6
read-write
MAKE_OUTPUT_1_TGL_0_SEL
Check the counter ocus possibilities for description for channel 1.
16
19
read-write
MAKE_OUTPUT_1_TGL_1_SEL
Check the counter ocus possibilities for description for channel 1.
19
22
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
22
24
read-write
WFG_TGL_CNT_0_PEAK
WFG mode output toggle count clock for channel 0.
8
16
read-write
WFG_TGL_CNT_1_PEAK
WFG mode output toggle count clock for channel 1
24
32
read-write
CTS
The capacitive touch sensor (CTS) controller is used to detect the position of the touch from the user on the capacitive touch screen
CAPACITIVE_TOUCH_SENSOR
0x0
0x0
0x124
registers
n
CTS
6
CONFIG_REG_0_0
Configuration Register 0_0
0x0
32
read-write
n
0x0
CLK_SEL1
Mux select for clock_mux_1
0
2
read-write
CLK_SEL2
Mux select for clock_mux_2
14
15
read-write
CTS_STATIC_CLK_EN
Enable static for capacitive touch sensor
15
16
read-write
disable
Clocks are gated
0
enable
Clocks are not gated
1
FIFO_AEMPTY_THRLD
Threshold for fifo aempty
22
28
read-write
FIFO_AFULL_THRLD
Threshold for fifo afull
16
22
read-write
FIFO_EMPTY
FIFO empty status bit
28
29
read-only
PRE_SCALAR_1
Division factor for clock divider
2
10
read-write
PRE_SCALAR_2
Division factor for clock divider
10
14
read-write
RESERVED1
Reserved1
29
32
read-only
CONFIG_REG_1_1
Configuration Register 1_1
0x100
32
read-write
n
0x0
BIT_SEL
Selects different set of 12 bits to be stored in FIFO
16
18
read-write
BUFFER_DELAY
Delay of buffer. Delay programmed will be equal to delay in nano seconds. Max delay value is 32.Default delay should be programmed before using Capacitive touch sensor module.
3
8
read-write
BYPASS
Bypass signal
15
16
write-only
Disable
Use Random number generator output bit as input to Non-Overlapping stream generator.
0
Enable
Bypass the Random number generator output to the Non-overlapping stream generator and to give clock as input to the Non-Overlapping stream generator.
1
CNT_ONEHOT_MODE
Continuous or One hot mode
11
12
read-write
One_hot
disable the cap sensor module
0
Continuous
enable the cap sensor module
1
ENABLE1
Enable signal
9
10
read-write
disable
disable the cap sensor module
0
enable
enable the cap sensor module
1
EXT_TRIG_EN
Select bit for NPSS clock or Enable
19
20
write-only
Enable
Enable
0
Clock
NPSS clock
1
POLYNOMIAL_LEN
Length of polynomial
0
2
read-write
RESERVED1
Reserved1
18
19
read-write
RESERVED2
Reserved2
20
32
read-write
RESET_WR_FIFO
Resets the signal fifo_wr_int
14
15
read-write
Reset
Reset
0
Out_of_reset
Out of reset
1
SAMPLE_MODE
Select bits for FIFO write and FIFO average
12
14
read-write
SEED_LOAD
Seed of polynomial
2
3
read-write
disable
loading of seed is not allowed
0
enable
to load the seed
1
SOFT_RESET_2
Reset the FIFO write and FIFO read occupancy pointers
10
11
read-write
WAKE_UP_ACK
Ack for wake up interrupt. This is a level signal. To acknowledge wake up , set this bit to one and reset it .
8
9
read-write
CONFIG_REG_1_2
Configuration Register 1_2
0x104
32
read-write
n
0x0
PWM_OFF_PERIOD
PWM OFF period
16
32
read-write
PWM_ON_PERIOD
PWM ON period
0
16
read-write
CONFIG_REG_1_3
Configuration Register 1_3
0x108
32
read-write
n
0x0
PRS_SEED
Pseudo random generator (PRS) seed value
0
32
read-write
CONFIG_REG_1_4
Configuration Register 1_4
0x10C
32
read-write
n
0x0
PRS_POLY
Polynomial programming register for PRS generator
0
32
read-write
CONFIG_REG_1_5
Configuration Register 1_5
0x110
32
read-write
n
0x0
INTER_SENSOR_DELAY
Inter-sensor scan delay value
0
16
read-write
N_SAMPLE_COUNT
Number of repetitions of sensor scan
16
32
read-write
CONFIG_REG_1_6
Configuration Register 1_6
0x114
32
read-write
n
0x0
SENSOR_CFG
Register of scan controller containing the programmed bit map
0
32
read-write
CONFIG_REG_1_7
Configuration Register 1_7
0x118
32
read-write
n
0x0
MASK_FIFO_AFULL_INTR
Wake up interrupt and fifo_afull_intr are ORed and given as a single interrupt to the processor.
7
8
read-write
Unmaked
fifo_afull_intr is unmasked
0
Masked
fifo_afull_intr is masked
1
REF_VOLT_CONFIG
This is given as an input voltage to analog model as comparator reference voltage.
12
15
read-write
RESERVED1
Reserved1
4
6
read-write
RESERVED2
Reserved2
8
12
read-write
VALID_SENSORS
Value of number of sensors valid in the bit map
0
4
read-write
VREF_SEL
Enable for Vref programmed
6
7
read-write
WAKEUP_MODE
Select bit for high/low mode.
15
16
read-write
Less_Than
Wakeup if count is lesser than threshold
0
Greater_Than
Wakeup if count is greater than threshold
1
WAKE_UP_THRESHOLD
Wakeup threshold.
16
32
read-write
CONFIG_REG_1_8
Configuration Register 1_8
0x11C
32
read-only
n
0x0
PRS_STATE
Current state of PRS
0
32
read-only
CONFIG_REG_1_9
Configuration Register 1_9
0x120
32
read-write
n
0x0
RESERVED1
Reserved1
10
32
read-write
TRIG_DIV
Allows one pulse for every 'trig_div' no. of pulses of 1 ms clock
0
10
read-write
FIFO_ADDRESS
FIFO Address Register
0x4
32
read-write
n
0x0
FIFO
Used for FIFO reads and write operations
0
32
read-write
CT_MUX_REG
Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock
CT
0x0
0x0
0x20
registers
n
CT_MUX_SEL_0_REG
MUX_SEL_0_REG Register
0x0
32
read-write
n
0x0
0x0
MUX_SEL_0
Select value to select first output value fifo_0_full[0] out of all the fifo_0_full_muxed signals of counter 0
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
CT_MUX_SEL_1_REG
MUX_SEL_1_REG Register
0x4
32
read-write
n
0x0
0x0
MUX_SEL_1
Select value to select first output value fifo_0_full[1] out of all the fifo_0_full_muxed signals of counter 0
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
CT_MUX_SEL_2_REG
MUX_SEL_2_REG Register
0x8
32
read-write
n
0x0
0x0
MUX_SEL_2
Select value to select first output value fifo_1_full[0] out of all the fifo_1_full_muxed signals of counter 1
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
CT_MUX_SEL_3_REG
MUX_SEL_3_REG Register
0xC
32
read-write
n
0x0
0x0
MUX_SEL_3
Select value to select first output value fifo_1_full[1] out of all the fifo_1_full_muxed signals of counter 1
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
CT_OUTPUT_EVENT1_ADC_SEL
OUTPUT_EVENT_ADC_SEL Register
0x18
32
read-write
n
0x0
0x0
OUTPUT_EVENT_ADC_SEL
Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
CT_OUTPUT_EVENT2_ADC_SEL
OUTPUT_EVENT_ADC_SEL Register
0x1C
32
read-write
n
0x0
0x0
OUTPUT_EVENT_ADC_SEL
Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module
0
4
read-write
RESERVED1
Reserved1
4
32
read-write
EFUSE
The EFUSE controller is used to provide an interface to one time program memory (EFUSE macro) to perform write and read operations
EFUSE
0x0
0x0
0x38
registers
n
CTRL_REG
Control Register
0xC
32
read-write
n
0x0
0x0
EFUSE_DIRECT_PATH_ENABLE
This bit specifies whether the EFUSE direct path is enabled or not for direct accessing of the EFUSE pins
1
2
read-write
disable
EFUSE direct accessing disabled
0
enable
EFUSE direct accessing enabled
1
EFUSE_ENABLE
This bit specifies whether the EFUSE module is enabled or not
0
1
read-write
disable
EFUSE module disabled
0
enable
EFUSE module enabled
1
ENABLE_EFUSE_WRITE
Controls the switch on VDDIQ for eFuse read/write.
2
3
read-write
disable
VDDIQ is gated
0
enable
VDDIQ is supplied
1
RESERVED1
reserved1
3
16
read-only
RESERVED2
reserved2
16
32
read-only
DA_ADDR_REG
Direct Access Registers
0x0
32
read-write
n
0x0
0x0
ADDR_BITS
These bits specifies the address to write or read from EFUSE macro model
0
16
read-write
RESERVED1
reserved1
16
32
read-write
DA_CLR_STROBE_REG
none
0x34
32
read-write
n
0x0
0x0
EFUSE_STROBE_CLR_CNT
Strobe signal Clear count in direct access mode. value depends on APB clock frequency of eFuse controller
0
9
read-write
EFUSE_STROBE_ENABLE
none
9
10
read-write
RESERVED1
reserved1
10
16
read-only
RESERVED2
reserved2
16
32
read-only
DA_CTRL_CLEAR_REG
Direct Access Clear Registers
0x8
32
read-write
n
0x0
0x0
CSB
Clear Chip Enable
1
2
read-write
disable
no effect
0
enable
Clear EFUSE Chip enable (CSB) pin when direct accessing is enabled
1
LOAD
Clear Load enable
3
4
read-write
disable
no effect
0
enable
Clear EFUSE load enable (LOAD) pin when direct accessing is enabled
1
PGENB
Clear Program enable
0
1
read-write
disable
no effect
0
enable
Clear EFUSE program enable (PGENB) pin when direct accessing is enabled
1
RESERVED1
reserved1
2
3
read-only
RESERVED2
reserved2
4
16
read-only
RESERVED3
reserved3
16
32
read-only
DA_CTRL_SET_REG
Direct Access Set Registers
0x4
32
read-write
n
0x0
0x0
CSB
Set Chip Enable
1
2
read-write
disable
no effect
0
enable
Sets EFUSE Chip enable (CSB) pin when direct accessing is enabled
1
LOAD
Set Load enable
3
4
read-write
disable
no effect
0
enable
Sets EFUSE load enable (LOAD) pin when direct accessing is enabled
1
PGENB
Set Program enable
0
1
read-write
disable
no effect
0
enable
Sets EFUSE program enable (PGENB) pin when direct accessing is enabled
1
RESERVED1
reserved1
4
16
read-write
RESERVED2
reserved2
16
32
read-write
STROBE
Set strobe enable
2
3
read-write
disable
no effect
0
enable
Sets EFUSE STROBE enable (STROBE) pin when direct accessing is enabled
1
MEM_MAP_LENGTH_REG
none
0x24
32
read-write
n
0x0
0x0
EFUSE_MEM_MAP_LEN
0: 8 bit read 1: 16 bit read
0
1
read-write
RESERVED1
reserved1
1
16
read-only
RESERVED2
reserved2
16
32
read-only
RD_TMNG_PARAM_REG
none
0x1C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
12
16
read-only
RESERVED2
reserved2
16
32
read-only
THRA
for 32x8 macro: A4 A0 to STROBE hold time into Read mode 5122x8 macro: A8 A0 to STROBE hold time into Read mode
8
12
read-write
TSQ
Q7-Q0 access time from STROBE rising edge
4
8
read-write
TSUR_CS
CSB to STROBE setup time into read mode
0
4
read-write
READ_ADDR_REG
Read address Register
0x10
32
read-write
n
0x0
0x0
DO_READ
Enables read FSM after EFUSE is enabled
15
16
write-only
READ_ADDR_BITS
These bits specifies the address from which read operation has to be performed
0
13
read-write
RESERVED1
reserved1
13
15
read-only
RESERVED2
reserved2
16
32
read-only
READ_BLOCK_ENABLE_REG
The Transmit Poll Demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA
0x30
32
read-write
n
0x0
0x0
efuse_read_block_enable
Enable for blocking the read access from a programmable memory location
0
1
read-write
RESERVED1
reserved1
1
16
read-only
RESERVED2
reserved2
16
32
read-only
READ_BLOCK_END_LOCATION
Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given
0x2C
32
read-write
n
0x0
0x0
EFUSE_READ_BLOCK_END_LOCATION
End address till which the read has to be blocked. Once the end address is written , it cannot be changed till power on reset is given.
0
16
read-write
RESERVED1
reserved1
16
32
read-only
READ_BLOCK_STARTING_LOCATION
Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given
0x28
32
read-write
n
0x0
0x0
EFUSE_READ_BLOCK_STARTING_LOCATION
Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given.
0
16
read-write
RESERVED1
reserved1
16
32
read-only
READ_DATA_REG
Read address Register
0x14
32
read-write
n
0x0
0x0
READ_DATA_BITS
These bits specifies the data bits that are read from a given address specified in the EFUSE_READ_ADDRESS_REGISTER bits 8:0
0
8
read-write
READ_FSM_DONE
Indicates read fsm is done. After this read data is available in EFUSE_READ_DATA_REGISTER bits 7:0
15
16
read-only
RESERVED1
reserved1
8
15
read-only
RESERVED2
reserved2
16
32
read-only
STATUS_REG
Read address Register
0x18
32
read-only
n
0x0
0x0
EFUSE_DOUT_SYNC
This bit specifies the 8-bit data read out from the EFUSE macro. This is synchronized with pclk
2
10
read-only
EFUSE_ENABLED
This bit specifies whether the EFUSE is enabled or not
0
1
read-only
RESERVED1
reserved1
1
2
read-only
RESERVED2
reserved2
10
16
read-only
RESERVED3
reserved3
16
32
read-only
EGPIO
ENHANCED GENERAL PERPOSE INPUT/OUTPUT
EGPIO
0x0
0x0
0x1260
registers
n
EGPIO_GROUP_0
50
EGPIO_GROUP_1
51
EGPIO_PIN_0
52
EGPIO_PIN_1
53
EGPIO_PIN_2
54
EGPIO_PIN_3
55
EGPIO_PIN_4
56
EGPIO_PIN_5
57
EGPIO_PIN_6
58
EGPIO_PIN_7
59
BIT_LOAD_REG
Bit Load
0x4
32
read-write
n
0x0
0x0
BIT_LOAD
Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit
0
1
read-write
RESERVED1
Reserved1
1
32
read-write
GPIO_CONFIG_REG
GPIO Configuration Register
0x0
32
read-write
n
0x0
0x0
DIRECTION
Direction of the GPIO pin
0
1
read-write
Disable
Output
0
Enable
Input
1
GROUP_INTERRUPT1_ENABLE
When set, the corresponding GPIO is pin is selected for group intr 1 generation
8
9
read-write
Disable
disable the gpio group interrupt1
0
Enable
enable the gpio group interrupt
1
GROUP_INTERRUPT1_POLARITY
Decides the active value of the pin to be considered for group interrupt 1 generation
9
10
read-write
Disable
group interrupt gets generated when gpio input pin status is zero
0
Enable
grp interrupt gets generated when gpio input pin status is 1
1
GROUP_INTERRUPT2_ENABLE
When set, the corresponding GPIO is pin is selected for group intr 2 generation
10
11
read-write
Disable
disable the gpio group interrupt2
0
Enable
enable the gpio group interrupt2
1
GROUP_INTERRUPT2_POLARITY
Decides the active value of the pin to be considered for group interrupt 2 generation
11
12
read-write
Disable
group interrupt gets generated when gpio input pin status is zero
0
Enable
grp interrupt gets generated when gpio input pin status is 1
1
MODE
GPIO Pin Mode Used for GPIO Pin Muxing
2
6
read-write
Mode0
000: Mode 0
0
Mode1
001:Mode 1
1
Mode2
010:Mode 2
2
Mode3
011:Mode 3
3
Mode4
100:Mode 4
4
Mode5
101: Mode 5
5
Mode6
110:Mode 6
6
Mode7
111:Mode 7
7
PORTMASK
Port mask value
1
2
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
16
32
read-write
GPIO_GRP_INTR_CTRL_REG
GPIO Interrupt 0 Control Register
0x0
32
read-write
n
0x0
0x0
AND_OR
AND/OR
0
1
read-write
Disable
AND
0
Enable
OR
1
ENABLE_INTERRUPT
Enable Interrupt
3
4
read-write
Disable
Disable
0
Enable
Enable
1
ENABLE_WAKEUP
For wakeup generation, actual pin status has to be seen(before double ranking point)
2
3
read-write
LEVEL_EDGE
Level/Edge
1
2
read-write
Disable
Level
0
Enable
Edge
1
MASK
Mask
4
5
read-write
Disable
Mask
0
Enable
unmask
1
RESERVED1
Reserved1
5
32
read-write
GPIO_GRP_INTR_STS
GPIO Interrupt 0 Status Register
0x4
32
read-write
n
0x0
0x0
INTERRUPT_STATUS
Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared.
0
1
read-write
MASK_CLEAR
Gives zero on read
4
5
read-write
MASK_SET
Gives zero on read
3
4
read-write
RESERVED1
Reserved1
2
3
read-write
RESERVED2
Reserved2
5
32
read-write
WAKEUP
Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared
1
2
read-only
GPIO_INTR_CTRL
GPIO Interrupt Control Register
0x0
32
read-write
n
0x0
0x0
FALL_EDGE_ENABLE
enables interrupt generation when Falling edge is detected on pin
3
4
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
LEVEL_HIGH_ENABLE
enables interrupt generation when pin level is 1
0
1
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
LEVEL_LOW_ENABLE
enables interrupt generation when pin level is 0
1
2
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
MASK
Masks the interrupt. Interrupt will still be seen in status register when enabled
4
5
read-write
Disable
Interrupt masked
0
Enable
Interrupt unmasked
1
PIN_NUMBER
GPIO Pin to be chosen for interrupt generation
8
12
read-write
PORT_NUMBER
GPIO Port to be chosen for interrupt generation
12
14
read-write
RESERVED1
Reserved1
5
8
read-write
RESERVED2
Reserved2
14
32
read-write
RISE_EDGE_ENABLE
enables interrupt generation when rising edge is detected on pin
2
3
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
GPIO_INTR_STATUS
GPIO Interrupt Status Register
0x4
32
read-write
n
0x0
0x0
FALL_EDGE_STATUS
Gets set when Fall edge is enabled and occurs.
2
3
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared.
1
INTERRUPT_STATUS
Gets set when interrupt is enabled and occurs.
0
1
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared. Also clears rise edge and fall edge status bits
1
MASK_CLEAR
Mask Clear
4
5
write-only
Disable
On read, this bit should result it in 0
0
Enable
When 1 is written mask bit gets cleared
1
MASK_SET
Mask set
3
4
write-only
Disable
On read, this bit should result it in 0
0
Enable
When 1 is written mask bit will get set
1
RESERVED1
Reserved1
5
32
read-write
RISE_EDGE_STATUS
Gets set when rise edge is enabled and occurs.
1
2
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared.
1
PORT_CLEAR_REG
Port Clear Register
0x8
32
write-only
n
0x0
0x0
PORT_CLEAR
Clears the pin when corresponding bit is high. Writing zero has no effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_LOAD_REG
Port Load
0x0
32
read-write
n
0x0
0x0
PORT_LOAD
Loads the value on to pin on write. And reads the value of load register on read
0
16
read-write
RES
RES
16
32
read-only
PORT_MASKED_LOAD_REG
Port Masked Load Register
0xC
32
write-only
n
0x0
0x0
PORT_MASKED_LOAD
Only loads into pins which are not masked. On read, pass only status unmasked pins
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_READ_REG
Port Read Register
0x14
32
read-only
n
0x0
0x0
PORT_READ
Reads the value on GPIO pins irrespective of the pin mode.
0
16
read-only
RESERVED1
Reserved1
16
32
read-only
PORT_SET_REG
Port Set Register
0x4
32
write-only
n
0x0
0x0
PORT_SET
Sets the pin when corresponding bit is high. Writing zero has no effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_TOGGLE_REG
Port Toggle Register
0x10
32
write-only
n
0x0
0x0
PORT_TOGGLE
Toggles the pin when corresponding bit is high. Writing zero has not effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
WORD_LOAD_REG
Word Load
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
16
32
read-write
WORD_LOAD
Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits.
0
16
read-write
EGPIO1
ENHANCED GENERAL PERPOSE INPUT/OUTPUT
EGPIO
0x0
0x0
0x1260
registers
n
ULP_EGPIO_PIN
18
ULP_EGPIO_GROUP
19
BIT_LOAD_REG
Bit Load
0x4
32
read-write
n
0x0
0x0
BIT_LOAD
Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit
0
1
read-write
RESERVED1
Reserved1
1
32
read-write
GPIO_CONFIG_REG
GPIO Configuration Register
0x0
32
read-write
n
0x0
0x0
DIRECTION
Direction of the GPIO pin
0
1
read-write
Disable
Output
0
Enable
Input
1
GROUP_INTERRUPT1_ENABLE
When set, the corresponding GPIO is pin is selected for group intr 1 generation
8
9
read-write
Disable
disable the gpio group interrupt1
0
Enable
enable the gpio group interrupt
1
GROUP_INTERRUPT1_POLARITY
Decides the active value of the pin to be considered for group interrupt 1 generation
9
10
read-write
Disable
group interrupt gets generated when gpio input pin status is zero
0
Enable
grp interrupt gets generated when gpio input pin status is 1
1
GROUP_INTERRUPT2_ENABLE
When set, the corresponding GPIO is pin is selected for group intr 2 generation
10
11
read-write
Disable
disable the gpio group interrupt2
0
Enable
enable the gpio group interrupt2
1
GROUP_INTERRUPT2_POLARITY
Decides the active value of the pin to be considered for group interrupt 2 generation
11
12
read-write
Disable
group interrupt gets generated when gpio input pin status is zero
0
Enable
grp interrupt gets generated when gpio input pin status is 1
1
MODE
GPIO Pin Mode Used for GPIO Pin Muxing
2
6
read-write
Mode0
000: Mode 0
0
Mode1
001:Mode 1
1
Mode2
010:Mode 2
2
Mode3
011:Mode 3
3
Mode4
100:Mode 4
4
Mode5
101: Mode 5
5
Mode6
110:Mode 6
6
Mode7
111:Mode 7
7
PORTMASK
Port mask value
1
2
read-write
RESERVED1
Reserved1
6
8
read-write
RESERVED2
Reserved2
12
16
read-write
RESERVED3
Reserved3
16
32
read-write
GPIO_GRP_INTR_CTRL_REG
GPIO Interrupt 0 Control Register
0x0
32
read-write
n
0x0
0x0
AND_OR
AND/OR
0
1
read-write
Disable
AND
0
Enable
OR
1
ENABLE_INTERRUPT
Enable Interrupt
3
4
read-write
Disable
Disable
0
Enable
Enable
1
ENABLE_WAKEUP
For wakeup generation, actual pin status has to be seen(before double ranking point)
2
3
read-write
LEVEL_EDGE
Level/Edge
1
2
read-write
Disable
Level
0
Enable
Edge
1
MASK
Mask
4
5
read-write
Disable
Mask
0
Enable
unmask
1
RESERVED1
Reserved1
5
32
read-write
GPIO_GRP_INTR_STS
GPIO Interrupt 0 Status Register
0x4
32
read-write
n
0x0
0x0
INTERRUPT_STATUS
Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared.
0
1
read-write
MASK_CLEAR
Gives zero on read
4
5
read-write
MASK_SET
Gives zero on read
3
4
read-write
RESERVED1
Reserved1
2
3
read-write
RESERVED2
Reserved2
5
32
read-write
WAKEUP
Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared
1
2
read-only
GPIO_INTR_CTRL
GPIO Interrupt Control Register
0x0
32
read-write
n
0x0
0x0
FALL_EDGE_ENABLE
enables interrupt generation when Falling edge is detected on pin
3
4
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
LEVEL_HIGH_ENABLE
enables interrupt generation when pin level is 1
0
1
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
LEVEL_LOW_ENABLE
enables interrupt generation when pin level is 0
1
2
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
MASK
Masks the interrupt. Interrupt will still be seen in status register when enabled
4
5
read-write
Disable
Interrupt masked
0
Enable
Interrupt unmasked
1
PIN_NUMBER
GPIO Pin to be chosen for interrupt generation
8
12
read-write
PORT_NUMBER
GPIO Port to be chosen for interrupt generation
12
14
read-write
RESERVED1
Reserved1
5
8
read-write
RESERVED2
Reserved2
14
32
read-write
RISE_EDGE_ENABLE
enables interrupt generation when rising edge is detected on pin
2
3
read-write
Disable
disabled
0
Enable
Interrupt enabled
1
GPIO_INTR_STATUS
GPIO Interrupt Status Register
0x4
32
read-write
n
0x0
0x0
FALL_EDGE_STATUS
Gets set when Fall edge is enabled and occurs.
2
3
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared.
1
INTERRUPT_STATUS
Gets set when interrupt is enabled and occurs.
0
1
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared. Also clears rise edge and fall edge status bits
1
MASK_CLEAR
Mask Clear
4
5
write-only
Disable
On read, this bit should result it in 0
0
Enable
When 1 is written mask bit gets cleared
1
MASK_SET
Mask set
3
4
write-only
Disable
On read, this bit should result it in 0
0
Enable
When 1 is written mask bit will get set
1
RESERVED1
Reserved1
5
32
read-write
RISE_EDGE_STATUS
Gets set when rise edge is enabled and occurs.
1
2
read-write
Disable
Writing 0 has not effect
0
Enable
When 1 is written it gets cleared.
1
PORT_CLEAR_REG
Port Clear Register
0x8
32
write-only
n
0x0
0x0
PORT_CLEAR
Clears the pin when corresponding bit is high. Writing zero has no effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_LOAD_REG
Port Load
0x0
32
read-write
n
0x0
0x0
PORT_LOAD
Loads the value on to pin on write. And reads the value of load register on read
0
16
read-write
RES
RES
16
32
read-only
PORT_MASKED_LOAD_REG
Port Masked Load Register
0xC
32
write-only
n
0x0
0x0
PORT_MASKED_LOAD
Only loads into pins which are not masked. On read, pass only status unmasked pins
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_READ_REG
Port Read Register
0x14
32
read-only
n
0x0
0x0
PORT_READ
Reads the value on GPIO pins irrespective of the pin mode.
0
16
read-only
RESERVED1
Reserved1
16
32
read-only
PORT_SET_REG
Port Set Register
0x4
32
write-only
n
0x0
0x0
PORT_SET
Sets the pin when corresponding bit is high. Writing zero has no effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
PORT_TOGGLE_REG
Port Toggle Register
0x10
32
write-only
n
0x0
0x0
PORT_TOGGLE
Toggles the pin when corresponding bit is high. Writing zero has not effect.
0
16
write-only
RESERVED1
Reserved1
16
32
write-only
WORD_LOAD_REG
Word Load
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
16
32
read-write
WORD_LOAD
Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits.
0
16
read-write
ETH
The Ethernet Controller enables a host to transmit and receive data over Ethernet
ETHERNET_REG
0x0
0x0
0x1058
registers
n
DMA_BUS_MODE_REG
Ethernet register
0x1000
32
read-write
n
0x0
DMA_CURRENT_HOST_RX_BUFF_ADDR_REG
Ethernet register
0x1054
32
read-write
n
0x0
DMA_CURRENT_HOST_RX_DESC_REG
Ethernet register
0x104C
32
read-write
n
0x0
DMA_CURRENT_HOST_TX_BUFF_ADDR_REG
Ethernet register
0x1050
32
read-write
n
0x0
DMA_CURRENT_HOST_TX_DESC_REG
Ethernet register
0x1048
32
read-write
n
0x0
DMA_INTR_EN_REG
Ethernet register
0x101C
32
read-write
n
0x0
DMA_MISSED_FRAME_BOC_REG
Ethernet register
0x1020
32
read-write
n
0x0
DMA_OPER_MODE_REG
Ethernet register
0x1018
32
read-write
n
0x0
DMA_RX_DESC_LIST_ADDR_REG
Ethernet register
0x100C
32
read-write
n
0x0
DMA_RX_POLL_DEMAND_REG
Ethernet register
0x1008
32
read-write
n
0x0
DMA_STATUS_REG
Ethernet register
0x1014
32
read-write
n
0x0
DMA_TX_DESC_LIST_ADDR_REG
Ethernet register
0x1010
32
read-write
n
0x0
DMA_TX_POLL_DEMAND_REG
Ethernet register
0x1004
32
read-write
n
0x0
MAC_ADDR0_HIGH_REG
ETHERNET REG
0x40
32
read-write
n
0x0
MAC_ADDR0_LOW_REG
ETHERNET REG
0x44
32
read-write
n
0x0
MAC_ADDR1_HIGH_REG
ETHERNET REG
0x48
32
read-write
n
0x0
MAC_ADDR1_LOW_REG
ETHERNET REG
0x4C
32
read-write
n
0x0
MAC_ADDR2_HIGH_REG
ETHERNET REG
0x50
32
read-write
n
0x0
MAC_ADDR2_LOW_REG
ETHERNET REG
0x54
32
read-write
n
0x0
MAC_ADDR3_HIGH_REG
ETHERNET REG
0x58
32
read-write
n
0x0
MAC_ADDR3_LOW_REG
ETHERNET REG
0x5C
32
read-write
n
0x0
MAC_ADDR4_HIGH_REG
ETHERNET REG
0x60
32
read-write
n
0x0
MAC_ADDR4_LOW_REG
ETHERNET REG
0x64
32
read-write
n
0x0
MAC_CONFIG_REG
ETHERNET REG
0x0
32
read-write
n
0x0
MAC_FLOW_CTRL_REG
ETHERNET REG
0x18
32
read-write
n
0x0
MAC_FRAME_FILTER_REG
ETHERNET REG
0x4
32
read-write
n
0x0
MAC_GMII_ADDR_REG
ETHERNET REG
0x10
32
read-write
n
0x0
MAC_GMII_DATA_REG
ETHERNET REG
0x14
32
read-write
n
0x0
MAC_HASH_TABLE_HIGH_REG
ETHERNET REG
0x8
32
read-write
n
0x0
MAC_HASH_TABLE_LOW_REG
ETHERNET REG
0xC
32
read-write
n
0x0
MAC_INTR_MASK_REG
ETHERNET REG
0x3C
32
read-write
n
0x0
MAC_PMT_CTRL_STATUS_REG
ETHERNET REG
0x2C
32
read-write
n
0x0
MAC_REM_WAKEUP_FRAME_FILTER_REG
ETHERNET REG
0x28
32
read-write
n
0x0
MAC_STATUS_REG
ETHERNET REG
0x38
32
read-write
n
0x0
MAC_VER_REG
ETHERNET REG
0x20
32
read-write
n
0x0
MAC_VLAN_TAG_REG
ETHERNET REG
0x1C
32
read-write
n
0x0
MMC_CTRL_REG
ETHERNET REG
0x100
32
read-write
n
0x0
MMC_INTR_MASK_RX_REG
ETHERNET REG
0x10C
32
read-write
n
0x0
MMC_INTR_MASK_TX_REG
ETHERNET REG
0x110
32
read-write
n
0x0
MMC_INTR_RX_REG
ETHERNET REG
0x104
32
read-write
n
0x0
MMC_INTR_TX_REG
ETHERNET REG
0x108
32
read-write
n
0x0
MMC_RX_CRC_ERROR_REG
ETHERNET REG
0x194
32
read-write
n
0x0
MMC_RX_FIFO_OVER_FLOW_REG
ETHERNET REG
0x1D4
32
read-write
n
0x0
MMC_TX_DEFFERED_REG
ETHERNET REG
0x154
32
read-write
n
0x0
MMC_TX_FRAME_COUNT_GB_REG
ETHERNET REG
0x180
32
read-write
n
0x0
MMC_TX_FRAME_COUNT_G_REG
ETHERNET REG
0x168
32
read-write
n
0x0
MMC_TX_SINGLE_COL_REG
ETHERNET REG
0x14C
32
read-write
n
0x0
MMC_TX_UNDERFLOW_ERROR_REG
ETHERNET REG
0x148
32
read-write
n
0x0
FIM
FIM support fixed point Multiplications implemented through programmable shifting.
FIM
0x0
0x0
0x24
registers
n
FIM
17
CONFIG_REG1
Configuration Register for FIM Operations.
0x1C
32
read-write
n
INP1_LEN
Indicates the length of 1st input for FIM Operations other than filtering (FIR, IIR) and Interpolation
6
16
read-write
INP2_LEN
Indicates the length of 2nd input for FIM Operations other than filtering (FIR, IIR) and Interpolation.
16
26
read-write
MAT_LEN
Indicates the number of columns in 1st input for Matrix Multiplication. This is same as number of rows in 2nd input for Matrix Multiplication.
0
6
read-write
RESERVED1
reserved1
26
32
read-only
CONFIG_REG2
Configuration Register for FIM Operations
0x20
32
read-write
n
COL_M2
Indicates the number of columns in 2nd input for Matrix Multiplication
10
16
read-write
CPLX_FLAG
Complex Flag,not valid in matrix mode
8
10
read-write
Real_Real
input1 and input2 both are real
0x0
Real_Complex
input1 is real and input2 is complex
0x1
Complex_Real
input1 is complex and input2 is real
0x2
Complex_Complex
input1 and input2 both are complex
0x3
INTRP_FAC
Indicates the Interpolation Factor
22
28
read-write
RES
reserved5
1
8
read-only
RESERVED1
reserved1
28
32
read-only
ROW_M1
Indicates the number of rows in 1st input for Matrix Multiplication
16
22
read-write
START_OPER
Start trigger for the FIM operations,this is reset upon write register
0
1
write-only
Disable
Disable start operation
0
Enable
Enable start operation
1
INP1_ADDR
This register used for COP input address for 0 register.
0x4
32
read-write
n
INP1_ADDR
Indicates the Start Address of 1st Input Data for FIM Operations
0
13
read-write
RESERVED1
reserved1
13
32
read-only
INP2_ADDR
This register used for COP input address for 1 register
0x8
32
read-write
n
INP2_ADDR
Indicates the Start Address of 2nd Input Data for FIM Operations
0
13
read-write
RESERVED1
reserved1
13
32
read-only
MODE_INTERRUPT
Configuration for FIM Operation Mode and Interrupt Control
0x0
32
read-write
n
INTR_CLEAR
Writing 1 to this bit clears the interrupt
10
11
write-only
Disable
Disable to clear interrupt
0
Enable
Enable to clear interrupt
1
LATCH_MODE
Enable latch mode
0
1
read-write
Disable
Disable latch mode enable of FIM
0
Enable
Enable latch mode enable of FIM
1
OPER_MODE
Indicates the Mode of Operation to be performed.
1
9
read-write
RESERVED1
reserved1
9
10
read-only
RESERVED2
reserved2
11
32
read-only
OUT_ADDR
Memory Offset Address for Output from FIM Operations
0xC
32
read-write
n
OUT_ADDR
Indicates the Start Address of Output Data for FIM Operations
0
13
read-write
RESERVED1
reserved1
13
32
read-only
POLE_DATA2
Feedback coefficient for IIR filter operation
0x14
32
read-write
n
POLE_DATA2
Indicates the feedback coefficient for IIR Operations
0
32
read-write
SAT_SHIFT
Configuration for precision of Output Data for FIM Operations
0x18
32
read-write
n
RESERVED1
reserved1
5
10
read-only
RESERVED2
reserved2
18
32
read-only
SAT_VAL
Indicates the number of MSB's to be saturated for Output Data
0
5
read-write
SHIFT_VAL
Indicates the number of bits to be right-shifted for Output Data
10
16
read-write
SCALAR_POLE_DATA1
Indicates the Input Scalar Data for Scalar Operations indicates the feedback coefficient for IIR Operations
0x10
32
read-write
n
SCALAR_POLE_DATA1
Pole 0/Scalar Value
0
32
read-write
GPDMA_C
GPDMAC (dma controller) is an AMBA complaint peripheral unit supports 8-channels
GPDMA
0x0
0x0
0x71C
registers
n
CHANNEL_CTRL_REG_CHNL
Channel Control Register for channel 0 to 7
0xC
32
read-write
n
0x0
0x0
DEST_ADDR_CONTIGUOUS
Indicates Address is contiguous from previous
26
27
read-write
0
0
0
1
1:Indicates Address is contiguous from previous
1
DEST_DATA_WIDTH
Data transfer to destination.
18
20
read-write
00
08 bits of data on the bus
0
01
16 bits of data on the bus
1
10
32 bits of data on the bus
2
11
reserved1
3
DEST_FIFO_MODE
If set to 1 destination address will not be incremented(means fifo mode for destination)
30
31
read-write
DMA_BLK_SIZE
This is data to be transmitted. Loaded at the beginning of the DMA transfer and decremented at every dma transaction.
0
12
read-write
DMA_FLOW_CTRL
DMA flow control
14
16
read-write
00
RPDMAC :can be set for any type of transfers
0
01
source peripheral : typically set for peripheral to memory
1
10
peripheral to memory destination peripheral : typically set for memory to peripheral
2
11
src_and_dest peripheral : Typically set for peripheral to peripheral
3
LINK_INTERRUPT
This bit is set in link list descriptor.Hard ware will send an interrupt when the DMA transfer is done for the corresponding link list address
28
29
read-write
LINK_LIST_MSTR_SEL
This mode is set, when we do link listed operation
24
25
read-write
0
0:M0 will be used to fetch desc
0
1
1:M1 will be used to fetch desc
1
LINK_LIST_ON
This mode is set, when we do link listed operation
23
24
read-write
MSTR_IF_FETCH_SEL
This selects the MASTER IF from which data to be fetched
16
17
read-write
0
0:MSTR-0 for fetch (from src)
0
1
1:MSTR-0 for fetch (from src)
1
MSTR_IF_SEND_SEL
This selects the MASTER IF from which data to be sent
17
18
read-write
0
0:MSTR-0 for send (to destination)
0
1
1:MSTR-1 for send (to destination)
1
RESERVED1
Reserved1
31
32
read-only
RETRY_ON_ERROR
When this bit is set, if we recieve HRESPERR, We will retry the DMA for that channel.
27
28
read-write
SRC_ADDR_CONTIGUOUS
Indicates Address is contiguous from previous
25
26
read-write
0
0
0
1
1:Indicates Address is contiguous from previous
1
SRC_ALIGN
Reserved.Value set to 0 We do not do any singles. We just do burst, save first 3 bytes in to residue buffer in one cycle, In the next cycle send 4 bytes to fifo, save 3 bytes in to residue. This continues on.
22
23
read-write
SRC_DATA_WIDTH
Data transfer from source.
20
22
read-write
00
08 bits of data on the bus
0
01
16 bits of data on the bus
1
10
32 bits of data on the bus
2
11
reserved2
3
SRC_FIFO_MODE
If set to 1 source address will not be incremented(means fifo mode for source)
29
30
read-write
TRNS_TYPE
DMA transfer type
12
14
read-write
00
Memory to Memory
0
01
memory to peripheral
1
10
peripheral to memory
2
11
peripheral to peripheral
3
DEST_ADDR_REG_CHNL
Source Address Register for channel 0 to 7
0x8
32
read-write
n
0x0
0x0
DEST_ADDR
This is the destination address to whih the data is sent
0
32
read-write
FIFO_CONFIG_REGS
FIFO Configuration Register for channel 1
0x14
32
read-write
n
0x0
0x0
FIFO_SIZE
Channel size
6
12
read-write
FIFO_STRT_ADDR
Starting row address of channel
0
6
read-write
RESERVED1
Reserved1
12
32
read-only
LINK_LIST_PTR_REGS
Link List Register for channel 0 to 7
0x0
32
read-write
n
0x0
0x0
LINK_LIST_PTR_REG_CHNL
This is the address of the memory location from which we get our next descriptor
0
32
read-write
MISC_CHANNEL_CTRL_REG_CHNL
Misc Channel Control Register for channel 0
0x10
32
read-write
n
0x0
0x0
AHB_BURST_SIZE
Burst size
0
3
read-write
DEST_CHNL_ID
This is the destination channel Id to which the data is sent. Must be set up prior to DMA_CHANNEL_ENABLE
15
21
read-write
DEST_DATA_BURST
Burst writes in beats to destination.(000000-64 beats .....111111-63 beats)
3
9
read-write
oneToSet
DMA_PROT
Protection level to go with the data. It will be concatenated with 1 b1 as there will be no opcode fetching and directly assign to hprot in AHB interface
27
30
read-write
MEM_FILL_ENABLE
Enable for memory filling with either 1s or 0s.
30
31
read-write
Disable
Disabled
0
Enable
Enabled the memory filling
1
MEM_ONE_FILL
Select for memory filling with either 1s or 0s.
31
32
read-write
Disable
Memory fill with 0s.
0
Enable
Memory fill with 1s.
1
SRC_CHNL_ID
This is the source channel Id, from which the data is fetched. must be set up prior to DMA_CHANNEL_ENABLE
21
27
read-write
SRC_DATA_BURST
Burst writes in beats from source(000000-64 beats .....111111-63 beats)
9
15
read-write
oneToSet
PRIORITY_CHNL_REGS
Priority Register for channel 0 to 7
0x18
32
read-write
n
0x0
0x0
PRIORITY_CH
Set a value between 2 b00 to 2 b11. The channel having highest number is the highest priority channel.
0
2
read-write
00
priority level 0
0
01
priority level 1
1
10
priority level 2
2
11
priority level 3
3
RESERVED1
Reserved1
2
32
read-only
SRC_ADDR_REG_CHNL
Source Address Register for channel 0 to 7
0x4
32
read-write
n
0x0
0x0
SRC_ADDR
This is the address of the memory location from which we get our next descriptor
0
32
read-write
GPDMA_G
GPDMA is an AMBA complaint peripheral unit supports 8-channels
GPDMA
0x0
0x1084
0x18
registers
n
GPDMA
31
DMA_CHNL_ENABLE_REG
This register used for enable DMA channel
0xC
32
read-write
n
0x0
0x0
CH_ENB
CWhen a bit is set to one, it indicates, corresponding channel is enabled for dma operation
0
8
read-write
RESERVED1
Reserved1
8
32
read-only
DMA_CHNL_LOCK_REG
This register used for enable DMA channel squash
0x14
32
read-write
n
0x0
0x0
CHNL_LOCK
When set entire DMA block transfer is done, before other DMA request is serviced
0
8
read-write
RESERVED1
Reserved1
8
32
read-only
DMA_CHNL_SQUASH_REG
This register used for enable DMA channel squash
0x10
32
read-write
n
0x0
0x0
CH_DIS
CPU Will be masked to write zeros, CPU is allowed write 1 only
0
8
read-write
RESERVED1
Reserved1
8
32
read-only
INTERRUPT_MASK_REG
Interrupt Mask Register
0x4
32
read-write
n
0x0
0x0
LINK_LIST_FETCH_MASK
Linked list fetch done interrupt bit mask control. By default, descriptor fetch done interrupt is masked.
8
16
read-write
RESERVED1
reserved1
0
8
read-write
RESERVED2
reserved2
24
32
read-write
TFR_DONE_MASK
Transfer done interrupt bit mask control.
16
24
read-write
INTERRUPT_REG
Interrupt Register
0x0
32
read-write
n
0x0
0x0
GPDMAC_INT_STAT
Interrupt Status
0
8
read-write
RESERVED1
reserved1
8
32
read-only
INTERRUPT_STAT_REG
Interrupt status register
0x8
32
read-write
n
0x0
0x0
GPDMAC_ERR0
transfer size or burst size or h size mismatch error
3
4
read-write
GPDMAC_ERR1
transfer size or burst size or h size mismatch error
7
8
read-write
GPDMAC_ERR2
transfer size or burst size or h size mismatch error
11
12
read-write
GPDMAC_ERR3
transfer size or burst size or h size mismatch error
15
16
read-write
GPDMAC_ERR4
transfer size or burst size or h size mismatch error
19
20
read-write
GPDMAC_ERR5
transfer size or burst size or h size mismatch error
23
24
read-write
GPDMAC_ERR6
transfer size or burst size or h size mismatch error
27
28
read-write
GPDMAC_ERR7
transfer size or burst size or h size mismatch error
31
32
read-write
HRESP_ERR0
DMA error bit
0
1
read-write
HRESP_ERR1
HRESP error bit
4
5
read-write
HRESP_ERR2
HRESP error bit
8
9
read-write
HRESP_ERR3
HRESP error bit
12
13
read-write
HRESP_ERR4
HRESP error bit
16
17
read-write
HRESP_ERR5
HRESP error bit
20
21
read-write
HRESP_ERR6
HRESP error bit
24
25
read-only
HRESP_ERR7
HRESP error bit
28
29
read-write
LINK_LIST_FETCH_DONE0
This bit indicates the status of linked list descriptor fetch done for channel 0
1
2
read-write
LINK_LIST_FETCH_DONE1
This bit indicates the status of linked list descriptor fetch done for channel 1
5
6
read-write
LINK_LIST_FETCH_DONE2
This bit indicates the status of linked list descriptor fetch done for channel 2.
9
10
read-write
LINK_LIST_FETCH_DONE3
This bit indicates the status of linked list descriptor fetch done for channel 3.
13
14
read-write
LINK_LIST_FETCH_DONE4
This bit indicates the status of linked list descriptor fetch done for channel 4.
17
18
read-write
LINK_LIST_FETCH_DONE5
This bit indicates the status of linked list descriptor fetch done for channel 5.
21
22
read-write
LINK_LIST_FETCH_DONE6
This bit indicates the status of linked list descriptor fetch done for channel 6.
25
26
read-write
LINK_LIST_FETCH_DONE7
This bit indicates the status of linked list descriptor fetch done for channel 7.
29
30
read-write
TFR_DONE0
This bit indicates the status of DMA transfer done interrupt for channel 0
2
3
read-write
TFR_DONE1
This bit indicates the status of DMA transfer done interrupt for channel 1.
6
7
read-write
TFR_DONE2
This bit indicates the status of DMA transfer done interrupt for channel 2.
10
11
read-write
TFR_DONE3
This bit indicates the status of DMA transfer done interrupt for channel 3.
14
15
read-write
TFR_DONE4
This bit indicates the status of DMA transfer done interrupt for channel 4.
18
19
read-write
TFR_DONE5
This bit indicates the status of DMA transfer done interrupt for channel 5.
22
23
read-write
TFR_DONE6
This bit indicates the status of DMA transfer done interrupt for channel 6.
26
27
read-write
TFR_DONE7
This bit indicates the status of DMA transfer done interrupt for channel 7.
30
31
read-write
GPIO_25_30_CONFIG_REG
Host gpio use as general gpio mode
EGPIO0
0x0
0x0
0x10
registers
n
GPIO_25_30_CONFIG_REG
This register disable host gpio mode and configure as general GPIO mode
0xC
32
read-write
n
0x0
GPIO_25_30_EN
Writing 1 to this enables the functionality for GPIO_n (n=25:30)
10
11
read-write
RESERVED1
Reserved1
0
10
read-only
RESERVED2
Reserved2
11
32
read-only
GPIO_TIMESTAMP
The Block is used for capturing the Timestamp of GPIO signal going high from SLEEP to Active state
SLEEP_FSM
0x0
0x0
0x8
registers
n
MCU_GPIO_TIMESTAMP_CONFIG
Configuration register foe GPIO timestamp
0x0
32
read-write
n
0x0
ENABLE_GPIO_TIMESTAMPING
Enable GPIO time stamping Feature.
0
1
read-write
disable
Disable GPIO time stamping Feature.
0
enable
Enable GPIO time stamping Feature.
1
RESERVED1
It is recommended to write these bits to 0.
6
31
read-write
TIMESTAMPING_DONE
This signal indicated Timestamp of GPIO is ready for reading.
31
32
read-only
TIMESTAMPING_ON_GPIO0
Enable GPIO time stamping on GPIO0
1
2
read-write
disable
Disable GPIO time stamping on GPIO0
0
enable
Enable GPIO time stamping on GPIO0
1
TIMESTAMPING_ON_GPIO1
Enable GPIO time stamping on GPIO1
2
3
read-write
disable
Disable GPIO time stamping on GPIO1
0
enable
Enable GPIO time stamping on GPIO1
1
TIMESTAMPING_ON_GPIO2
Enable GPIO time stamping on GPIO2
3
4
read-write
disable
Disable GPIO time stamping on GPIO2
0
enable
Enable GPIO time stamping on GPIO2
1
TIMESTAMPING_ON_GPIO3
Enable GPIO time stamping on GPIO3
4
5
read-write
disable
Disable GPIO time stamping on GPIO3
0
enable
Enable GPIO time stamping on GPIO3
1
TIMESTAMPING_ON_GPIO4
Enable GPIO time stamping on GPIO4
5
6
read-write
disable
Disable GPIO time stamping on GPIO4
0
enable
Enable GPIO time stamping on GPIO4
1
MCU_GPIO_TIMESTAMP_READ
GPIO timestamp read register
0x4
32
read-only
n
0x0
GPIO_EVENT_COUNT_FULL
Counter value indicating the duration from GPIO going high to first Sleep clock
0
11
read-only
GPIO_EVENT_COUNT_PARTIAL
Counter value indicating number for 32MHz clock present in 1 Sleep clock
16
27
read-only
RESERVED1
It is recommended to write these bits to 0.
11
16
read-only
RESERVED2
It is recommended to write these bits to 0.
27
32
read-only
GSPI0
GSPI, or Generic SPI, is a module which has been derived from QSPI. GSPI can act only as a master
GSPI
0x0
0x0
0xC0
registers
n
GSPI0
46
GSPI_BUS_MODE
GSPI Bus Mode Register
0x4
32
read-write
n
0x0
0x0
GSPI_CLK_MODE_CSN0
NONE
1
2
read-write
Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select0 (csn0)
0
Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select0 (csn0)
1
GSPI_CLK_MODE_CSN1
NONE
2
3
read-write
Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select1 (csn1)
0
Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select1 (csn1)
1
GSPI_CLK_MODE_CSN2
NONE
3
4
read-write
Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select2 (csn2)
0
Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select2 (csn2)
1
GSPI_CLK_MODE_CSN3
NONE
4
5
read-write
Disable
Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select3 (csn3)
0
Enable
Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select3 (csn3)
1
GSPI_DATA_SAMPLE_EDGE
Samples MISO data on clock edges. This should be ZERO for mode3 clock
0
1
read-write
Disable
Pos edge of loop back spi_pad_clk
0
Enable
Neg edge of loop back spi_pad_clk
1
GSPI_GPIO_MODE_ENABLES
These bits are used to map GSPI on GPIO pins
5
11
read-write
RESERVED1
reserved for future use
12
32
read-write
SPI_HIGH_PERFORMANCE_EN
High performance features are enabled when this bit is set to one
11
12
read-write
GSPI_CLK_CONFIG
GSPI Clock Configuration Register
0x0
32
read-write
n
0x0
0x0
GSPI_CLK_EN
GSPI clock enable
1
2
read-write
Disable
Dynamic clock gating is enabled in side GSPI controller
0
Enable
Full time clock is enabled for GSPI controller.
1
GSPI_CLK_SYNC
If the clock frequency to FLASH (spi_clk) and SOC clk is same.
0
1
read-write
Disable
Divided SOC clock is connected SCLK. Division value is programmable
0
Enable
SCLK clock and SOC clock are same
1
Enable
SCLK clock and SOC clock are same
1
Enable
SCLK clock and SOC clock are same
1
Enable
SCLK clock and SOC clock are same
1
RESERVED1
reserved for future use
2
32
read-write
GSPI_CLK_DIV
GSPI Clock Division Factor Register
0x38
32
read-write
n
0x0
0x0
GSPI_CLK_DIV_FACTOR
Provides GSPI clock division factor to the clock divider, which takes SOC clock as input clock and generates required clock according to division factor
0
8
read-write
RESERVED1
reserved1
8
32
read-only
GSPI_CONFIG1
GSPI Configuration 1 Register
0x10
32
read-write
n
0x0
0x0
GSPI_MANUAL_CSN
SPI CS in manual mode
0
1
read-write
GSPI_MANUAL_CSN_SELECT
Indicates which CSn is valid. Can be programmable in manual mode
13
15
read-write
GSPI_MANUAL_RD
Read enable for manual mode when CS is low
2
3
read-write
GSPI_MANUAL_RD_CNT
Indicates total number of bytes to be read
3
13
read-write
GSPI_MANUAL_WR
Write enable for manual mode when CS is low.
1
2
read-write
RESERVED1
reserved for future use
16
32
read-write
SPI_FULL_DUPLEX_EN
Full duplex mode enable
15
16
read-write
Disable
Full duplex mode disabled.
0
Enable
Full duplex mode enabled
1
GSPI_CONFIG2
GSPI Manual Configuration 2 Register
0x14
32
read-write
n
0x0
0x0
GSPI_MANUAL_SIZE_FRM_REG
Manual reads and manual writes
8
9
read-write
Disable
1 Byte 8 bit mode
0
Enable
2 Bytes 16 bit mode
1
GSPI_RD_DATA_SWAP_MNL_CSN0
Swap the read data inside the GSPI controller it-self.
4
5
read-write
Disable
Manual read data swap is disabled for csn0
0
Enable
Manual read data swap is enabled for csn0
1
GSPI_RD_DATA_SWAP_MNL_CSN1
Swap the read data inside the GSPI controller it-self.
5
6
read-write
Disable
Manual read data swap is disabled for csn1
0
Enable
Manual read data swap is enabled for csn1
1
GSPI_RD_DATA_SWAP_MNL_CSN2
Swap the read data inside the GSPI controller it-self.
6
7
read-write
Disable
Manual read data swap is disabled for csn2
0
Enable
Manual read data swap is enabled for csn2
1
GSPI_RD_DATA_SWAP_MNL_CSN3
Swap the read data inside the GSPI controller it-self.
7
8
read-write
Disable
Manual read data swap is disabled for csn3
0
Enable
Manual read data swap is enabled for csn3
1
GSPI_WR_DATA_SWAP_MNL_CSN0
Swap the write data inside the GSPI controller it-self.
0
1
read-write
Disable
Manual write data swap is disabled for csn0.
0
Enable
Manual write data swap is enabled for csn0.
1
GSPI_WR_DATA_SWAP_MNL_CSN1
Swap the write data inside the GSPI controller it-self.
1
2
read-write
Disable
Manual write data swap is disabled for csn1
0
Enable
Manual write data swap is enabled for csn1
1
GSPI_WR_DATA_SWAP_MNL_CSN2
Swap the write data inside the GSPI controller it-self.
2
3
read-write
Disable
Manual write data swap is disabled for csn2
0
Enable
Manual write data swap is enabled for csn2
1
GSPI_WR_DATA_SWAP_MNL_CSN3
Swap the write data inside the GSPI controller it-self.
3
4
read-write
Disable
Manual write data swap is disabled for csn3
0
Enable
Manual write data swap is enabled for csn3
1
MANUAL_GSPI_MODE
Internally the priority is given to manual mode
11
12
read-write
Disable
SPI mode
0
Enable
Host SPI mode
1
RESERVED1
reserved for future use
9
10
read-write
RESERVED2
reserved for future use
12
32
read-write
TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG
NONE
10
11
read-write
Disable
No action
0
Enable
Take write size from Manual config register1[20:19]
1
GSPI_CONFIG3
GSPI Configuration 3 Register
0x3C
32
read-write
n
0x0
RESERVED1
reserved1
15
32
read-write
SPI_MANUAL_RD_LNTH_TO_BC
Bits are used to indicate the total number of bytes to read from flash during read operation
0
15
read-write
GSPI_FIFO_THRLD
GSPI FIFO Threshold Register
0x1C
32
read-write
n
0x0
0x0
FIFO_AEMPTY_THRLD
FIFO almost empty threshold
0
4
read-write
FIFO_AFULL_THRLD
FIFO almost full threshold
4
8
read-write
RESERVED1
reserved for future use
10
32
read-write
RFIFO_RESET
read FIFO reset
9
10
read-write
WFIFO_RESET
Write FIFO reset
8
9
read-write
GSPI_INTR_ACK
GSPI Interrupt Acknowledge Register
0x30
32
write-only
n
0x0
0x0
FIFO_AEMPTY_RFIFO_ACK
NONE
1
2
write-only
Disable
Do not touch
0
Enable
Read fifo almost empty intr ack
1
FIFO_AFULL_WFIFO_ACK
NONE
4
5
write-only
Disable
Do not touch
0
Enable
Write fifo almost full intr ack
1
FIFO_EMPTY_RFIFO_ACK
NONE
6
7
write-only
Disable
Do not touch
0
Enable
Read fifo is empty intr ack
1
FIFO_FULL_WFIFO_ACK
NONE
5
6
write-only
Disable
Do not touch
0
Enable
write fifo full intr ack
1
GSPI_INTR_ACK
GSPI Interrupt status bit
0
1
write-only
Disable
Do not touch
0
Enable
GSPI intr ack.
1
RESERVED1
reserved for future use
2
4
write-only
RESERVED2
reserved1
7
32
write-only
GSPI_INTR_MASK
GSPI Interrupt Mask Register
0x24
32
read-write
n
0x0
0x0
FIFO_AEMPTY_RFIFO_MASK
NONE
1
2
read-write
Disable
Do not touch
0
Enable
Read fifo almost empty intr mask.
1
FIFO_AEMPTY_WFIFO_MASK
NONE
3
4
read-write
Disable
Do not touch
0
Enable
write fifo almost empty intr mask
1
FIFO_AFULL_RFIFO_MASK
NONE
2
3
read-write
Disable
Do not touch
0
Enable
read fifo almost full intr mask
1
FIFO_AFULL_WFIFO_MASK
NONE
4
5
read-write
Disable
Do not touch
0
Enable
Write fifo almost full intr mask.
1
FIFO_EMPTY_RFIFO_MASK
NONE
6
7
read-write
Disable
Do not touch
0
Enable
Read fifo is empty intr mask
1
FIFO_FULL_WFIFO_MASK
NONE
5
6
read-write
Disable
Do not touch
0
Enable
write fifo full intr mask.
1
GSPI_INTR_MASK
GSPI Interrupt mask bit
0
1
read-write
Disable
Do not touch
0
Enable
mask the GSPI intr
1
RESERVED1
reserved for future use
7
32
read-write
GSPI_INTR_STS
GSPI Interrupt Status Register
0x2C
32
read-only
n
0x0
0x0
FIFO_AEMPTY_RFIFO_LVL
NONE
1
2
read-only
Disable
Read fifo does not reach almost empty threshold.
0
Enable
Read fifo reached almost empty threshold
1
FIFO_AFULL_WFIFO_LVL
NONE
4
5
read-only
Disable
Write fifo not reached almost full threshold
0
Enable
Write fifo almost full threshold
1
FIFO_EMPTY_RFIFO_LVL
NONE
6
7
read-only
Disable
Read fifo is not empty
0
Enable
Read fifo is empty
1
FIFO_FULL_WFIFO_LVL
NONE
5
6
read-only
Disable
write fifo not full
0
Enable
write fifo full
1
GSPI_INTR_LVL
GSPI Interrupt status bit
0
1
read-only
Disable
no interrupt
0
Enable
GSPI raised a interrupt
1
RESERVED1
reserved for future use
2
4
read-only
RESERVED2
reserved for future use
7
32
read-only
GSPI_INTR_UNMASK
GSPI Interrupt Unmask Register
0x28
32
read-write
n
0x0
0x0
FIFO_AEMPTY_RFIFO_UNMASK
NONE
1
2
read-write
Disable
Do not touch
0
Enable
Read fifo almost empty intr unmask.
1
FIFO_AEMPTY_WFIFO_UNMASK
NONE
3
4
read-write
Disable
Do not touch
0
Enable
write fifo almost empty intr unmask
1
FIFO_AFULL_RFIFO_UNMASK
NONE
2
3
read-write
Disable
Do not touch
0
Enable
read fifo almost full intr unmask.
1
FIFO_AFULL_WFIFO_UNMASK
NONE
4
5
read-write
Disable
Do not touch
0
Enable
Write fifo almost full intr unmask.
1
FIFO_EMPTY_RFIFO_UNMASK
NONE
6
7
read-write
Disable
Do not touch
0
Enable
Read fifo is empty intr unmask
1
FIFO_FULL_WFIFO_UNMASK
NONE
5
6
read-write
Disable
Do not touch
0
Enable
write fifo full intr unmask.
1
GSPI_INTR_UNMASK
GSPI Interrupt unmask bit
0
1
read-write
Disable
Do not touch
0
Enable
unmask the GSPI intr
1
RESERVED1
reserved for future use
7
32
read-write
GSPI_READ_FIFO0
GSPI READ FIFO
0x80
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO1
GSPI READ FIFO
0x84
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO10
GSPI READ FIFO
0xA8
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO11
GSPI READ FIFO
0xAC
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO12
GSPI READ FIFO
0xB0
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO13
GSPI READ FIFO
0xB4
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO14
GSPI READ FIFO
0xB8
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO15
GSPI READ FIFO
0xBC
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO2
GSPI READ FIFO
0x88
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO3
GSPI READ FIFO
0x8C
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO4
GSPI READ FIFO
0x90
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO5
GSPI READ FIFO
0x94
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO6
GSPI READ FIFO
0x98
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO7
GSPI READ FIFO
0x9C
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO8
GSPI READ FIFO
0xA0
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_READ_FIFO9
GSPI READ FIFO
0xA4
32
read-only
n
0x0
0x0
READ_FIFO
FIFO data is read from this address space
0
32
read-only
GSPI_STATUS
GSPI Status Register
0x20
32
read-only
n
0x0
0x0
FIFO_AEMPTY_RFIFO_S
Aempty status indication for Rfifo in manual mode
8
9
read-only
FIFO_AFULL_WFIFO_S
Almost full status indication for Wfifo in manual mode
2
3
read-only
FIFO_EMPTY_RFIFO_S
Empty status indication for Rfifo in manual mode
7
8
read-only
FIFO_EMPTY_WFIFO
Empty status indication for Wfifo in manual mode
3
4
read-only
FIFO_FULL_RFIFO
Full status indication for Rfifo in manual mode
5
6
read-only
FIFO_FULL_WFIFO_S
Full status indication for Wfifo in manual mode
1
2
read-only
GSPI_BUSY
State of Manual mode
0
1
read-only
Disable
GSPI controller is IDLE in Manual mode.
0
Enable
A read, write or dummy cycle operation is in process in manual mode
1
GSPI_MANUAL_CSN
Provide the status of chip select signal
10
11
read-only
Disable
Active
0
Enable
Inactive
1
GSPI_MANUAL_RD_CNT
This is a result of 10 bits ORing counter
9
10
read-only
Disable
No read transactions are in pending
0
Enable
Read transactions are in pending ( to be done)
1
RESERVED1
reserved for future use
4
5
read-only
RESERVED2
reserved for future use
6
7
read-only
RESERVED3
reserved for future use
11
32
read-only
GSPI_STS_MC
GSPI State Machine Monitor Register
0x34
32
read-only
n
0x0
0x0
BUS_CTRL_PSTATE
Provides SPI bus controller present state
0
3
read-only
RESERVED1
reserved1
16
32
read-only
SPI_RD_CNT
number of pending bytes to be read by device
3
16
read-only
GSPI_WRITE_DATA2
GSPI Write Data 2 Register
0x18
32
read-write
n
0x0
0x0
GSPI_MANUAL_WRITE_DATA2
Number of bits to be written in write mode
0
4
read-write
RESERVED1
reserved for future use
4
7
read-write
RESERVED2
reserved for future use
8
32
read-write
USE_PREV_LENGTH
Use previous length
7
8
read-write
Disable
No action
0
Enable
Uses previously programmed length in [3:0] of this register for next writes
1
GSPI_WRITE_FIFO0
GSPI fifo
0x80
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO1
GSPI fifo
0x84
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO10
GSPI fifo
0xA8
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO11
GSPI fifo
0xAC
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO12
GSPI fifo
0xB0
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO13
GSPI fifo
0xB4
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO14
GSPI fifo
0xB8
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO15
GSPI fifo
0xBC
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO2
GSPI fifo
0x88
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO3
GSPI fifo
0x8C
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO4
GSPI fifo
0x90
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO5
GSPI fifo
0x94
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO6
GSPI fifo
0x98
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO7
GSPI fifo
0x9C
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO8
GSPI fifo
0xA0
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
GSPI_WRITE_FIFO9
GSPI fifo
0xA4
32
write-only
n
0x0
0x0
WRITE_FIFO
FIFO data is write to this address space
0
32
write-only
HWRNG
Random numbers generated are 16-bit random numbers and are generated using either the True random number generator or the Pseudo random number generator.
HWRNG
0x0
0x0
0x8
registers
n
HRNG_CTRL
Random Number Generator Control Register
0x0
32
read-write
n
0x0
0x0
HWRNG_PRBS_ST
This bit is used to start the pseudo random number generation
1
2
read-write
Disable
Disables pseudo random number generation
0
Enable
Enables pseudo random number generation
1
HWRNG_RNG_ST
This bit is used to start the true number generation.
0
1
read-write
Disable
Disables true random number generation
0
Enable
Enables true random number generation
1
RESERVED1
RESERVED1
3
32
read-only
SOFT_RESET
This bit is used to start the pseudo random number generation
2
3
read-write
Disable
Not resetted
0
Enable
Reset the scrambled data
1
HRNG_RAND_NUM
Hardware Random Number Register
0x4
32
read-only
n
0x0
0x0
HWRNG_RAND_NUM
Generated random number can be read from this register.
0
32
read-only
I2C0
Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system
I2C
0x0
0x0
0x100
registers
n
I2C0
42
IC_ACK_GENERAL_CALL
I2C ACK General Call Register
0x98
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
1
32
read-only
IC_CLR_ACTIVITY
Clear ACTIVITY Interrupt Register
0x5C
32
read-only
n
0x0
0x0
CLR_ACTIVITY
Reading this register clears the ACTIVITY interrupt if the I2C is not active any more
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_GEN_CALL
Clear GEN_CALL Interrupt Register
0x68
32
read-only
n
0x0
0x0
CLR_GEN_CALL
Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_INTR
Clear Combined and Individual Interrupt Register
0x40
32
read-only
n
0x0
0x0
CLR_INTR
Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RD_REQ
Clear RD_REQ Interrupt Register
0x50
32
read-only
n
0x0
0x0
CLR_RD_REQ
Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RESTART_DET
Clear RESTART_DET Interrupt Register
0xA8
32
read-only
n
0x0
0x0
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_DONE
Clear RX_DONE Interrupt Register
0x58
32
read-only
n
0x0
0x0
CLR_RX_DONE
Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_OVER
Clear RX_OVER Interrupt Register
0x48
32
read-only
n
0x0
0x0
CLR_RX_OVER
Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_UNDER
Clear RX_UNDER Interrupt Register
0x44
32
read-only
n
0x0
0x0
CLR_RX_UNDER
Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SCL_STUCK_DET
Clear SCL Stuck at Low Detect Interrupt Register
0xB4
32
read-only
n
0x0
CLR_SCL_STUCK
Read this register to clear the SCL_STUCK_DET interrupt
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SMBUS_INTR
Clear SMBUS Interrupt Register
0xD4
32
read-write
n
0x0
0x0
RESERVED1
RESERVED1
0
32
read-write
IC_CLR_START_DET
Clear START_DET Interrupt Register
0x64
32
read-only
n
0x0
0x0
CLR_START_DET
Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_STOP_DET
Clear STOP_DET Interrupt Register
0x60
32
read-only
n
0x0
0x0
CLR_STOP_DET
Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_ABRT
Clear TX_ABRT Interrupt Register
0x54
32
read-only
n
0x0
0x0
CLR_TX_ABRT
Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_OVER
Clear TX_OVER Interrupt Register
0x4C
32
read-only
n
0x0
0x0
CLR_TX_OVER
Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_COMP_PARAM_1
I2C HS Spike Suppression Limit Register
0xF4
32
read-only
n
0x0
0x0
ADD_ENCODED_PARAMS
Add Encoded Parameters
7
8
read-only
False
False
0x0
True
True
0x1
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
HAS_DMA
DMA Handshake Interface signal
6
7
read-only
False
False
0x0
True
True
0x1
HC_COUNT_VALUES
Hard Code the count values
4
5
read-only
False
False
0x0
True
True
0x1
INTR_IO
Single Interrupt Output port
5
6
read-only
Individual
Individual
0x0
Combined
Combined
0x1
MAX_SPEED_MODE
Maximum Speed Mode
2
4
read-only
NONE
none
0x0
Standard
Standard
0x1
Fast
Fast
0x2
High
High
0x3
RESERVED1
reserved1
24
32
read-only
RX_BUFFER_DEPTH
Depth of receive buffer the buffer is 8 bits wide 2 to 256
8
16
read-only
TX_BUFFER_DEPTH
Depth of Transmit buffer the buffer is 8 bits wide 2 to 256
16
24
read-only
IC_COMP_TYPE
I2C Component Type Register
0xFC
32
read-only
n
0x0
IC_COMP_TYPE
Design ware Component Type number = 0x44_57_01_40
0
32
read-only
IC_COMP_VERSION
I2C Component Version Register
0xF8
32
read-only
n
0x0
IC_COMP_VERSION
Signifies the component version
0
32
read-only
IC_CON
This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.
0x0
32
read-write
n
0x0
0x0
BUS_CLEAR_FEATURE_CTRL
In Master mode.
11
12
read-write
Disable
Bus Clear Feature is disabled
0
Enable
Bus Clear Feature is enabled
1
IC_10BITADDR_MASTER_RD_ONLY
the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only
4
5
read-only
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_10BITADDR_SLAVE
When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.
3
4
read-write
Disable
7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared
0
Enable
10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
1
IC_RESTART_EN
Determines whether RESTART conditions may be sent when acting as a master
5
6
read-write
Disable
Disabled
0
Enable
Enabled
1
IC_SLAVE_DISABLE
This bit controls whether I2C has its slave disabled
6
7
read-write
Disable
slave is enabled
0
Enable
slave is disabled
1
MASTER_MODE
This bit controls whether the I2C master is enabled.
0
1
read-write
Disable
master disabled
0
Enable
master enabled
1
RESERVED1
reserved1
9
10
read-only
RESERVED2
reserved2
12
32
read-write
SPEED
These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software.
1
3
read-write
Standard Mode
standard mode (0 to 100 kbit/s)
1
Fast Mode
fast mode (less than or equal 400 kbit/s)
2
High Speed Mode
high speed mode (less than or equal 3.4 Mbit/s)
3
STOP_DET_IFADDRESSED
The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR
7
8
read-write
Disable
Issues the STOP DETECTION irrespective of whether it is addressed or not.
0
Enable
issues the STOP DETECTION interrupt only when it is addressed.
1
STOP_DET_IF_MASTER_ACTIVE
In Master mode.
10
11
read-write
Disable
Issues the STOP_DET irrespective of whether the master is active.
0
Enable
Issues the STOP_DET interrupt only when the master is active
1
TX_EMPTY_CTRL
This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register.
8
9
read-write
IC_DATA_CMD
I2C Rx/Tx Data Buffer and Command Register
0x10
32
read-write
n
0x0
0x0
CMD
This bit controls whether a read or a write is performed
8
9
write-only
Disable
write
0
Enable
Read
1
DAT
This register contains the data to be transmitted or received on the I2C bus
0
8
read-write
FIRST_DATA_BYTE
Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode
11
12
read-only
RESERVED1
reserved1
12
32
read-only
RESTART
This bit controls whether a RESTART is issued before the byte is sent or received
10
11
write-only
Disable
If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command
0
Enable
If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
1
STOP
This bit controls whether a STOP is issued after the byte is sent or received
9
10
write-only
Disable
STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty
0
Enable
STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty
1
IC_DEVICE_ID
I2C Device ID
0xB8
32
read-only
n
0x0
DEVICE_ID
Contains the Device-ID of the component assigned through the configuration parameter
0
24
read-only
RESERVED1
reserved1
24
32
read-only
IC_DMA_CR
DMA Control Register
0x88
32
read-write
n
0x0
0x0
RDMAE
Receive DMA Enable
0
1
read-write
Disable
Receive DMA disabled
0
Enable
Receive DMA enabled
1
RESERVED1
reserved1
2
32
read-only
TDMAE
Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
Disable
Transmit DMA disabled
0
Enable
Transmit DMA enabled
1
IC_DMA_RDLR
I2C Receive Data Level Register
0x90
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_DMA_TDLR
DMA Transmit Data Level Register
0x8C
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_ENABLE
Clear GEN_CALL Interrupt Register
0x6C
32
read-write
n
0x0
0x0
ABORT
When set, the controller initiates the transfer abort
1
2
read-write
Disable
ABORT not initiated or ABORT done
0
Enable
ABORT operation in progress
1
EN
Controls whether the DW_apb_i2c is enabled
0
1
read-write
Disable
Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)
0
Enable
Enables DW_apb_i2c
1
RESERVED1
reserved1
4
16
read-only
RESERVED2
reserved2
16
32
read-only
SDA_STUCK_RECOVERY_ENABLE
If SDA is stuck at low indicated through the TX_ABORT interrupt IC_TX_ABRT_SOURCE17, then this bit is used as a control knob to initiate the SDA Recovery Mechanism
3
4
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
TX_CMD_BLOCK
none
2
3
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
IC_ENABLE_STATUS
I2C Enable Status Register
0x9C
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
3
32
read-write
SLV_DISABLED_WHILE_BUSY
This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0
1
2
read-only
Disable
DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
0
Enable
DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer
1
SLV_RX_DATA_LOST
Slave Received Data Lost
2
3
read-only
Disable
DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK
0
Enable
DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer
1
IC_FS_SCL_HCNT
Fast Speed I2C Clock SCL High Count Register
0x1C
32
read-write
n
0x0
0x0
IC_FS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SCL_LCNT
Fast Speed I2C Clock SCL Low Count Register
0x20
32
read-write
n
0x0
0x0
IC_FS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SPKLEN
I2C SS and FS Spike Suppression Limit Register
IC_UFM_SPKLEN
0xA0
32
read-write
n
0x0
0x0
IC_FS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_HS_MADDR
I2C High Speed Master Mode Code Address Register
0xC
32
read-write
n
0x0
0x0
IC_HS_MAR
This bit field holds the value of the I2C HS mode master code
0
3
read-write
RESERVED1
reserved1
3
32
read-only
IC_HS_SCL_HCNT
High Speed I2C Clock SCL High Count Register
0x24
32
read-write
n
0x0
0x0
IC_HS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SCL_LCNT
High Speed I2C Clock SCL Low Count Register
0x28
32
read-write
n
0x0
0x0
IC_HS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SPKLEN
I2C HS Spike Suppression Limit Register
0xA4
32
read-write
n
0x0
0x0
IC_HS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_INTR_MASK
I2C Interrupt Mask Register
0x30
32
read-write
n
0x0
0x0
M_ACTIVITY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
8
9
read-write
M_GEN_CALL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
11
12
read-write
M_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-write
M_RD_REQ
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
5
6
read-write
M_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-write
M_RX_DONE
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
7
8
read-write
M_RX_FULL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
2
3
read-write
M_RX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
1
2
read-write
M_RX_UNDER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
0
1
read-write
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
M_START_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
10
11
read-write
M_STOP_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
9
10
read-write
M_TX_ABRT
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
6
7
read-write
M_TX_EMPTY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
4
5
read-write
M_TX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register
3
4
read-write
RESERVED1
reserved1
15
32
read-only
IC_INTR_STAT
I2C Interrupt Status Register
0x2C
32
read-only
n
0x0
0x0
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
RESERVED1
reserved1
15
32
read-only
R_ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
R_GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
R_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
R_RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
R_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
R_RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
R_RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
R_RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
R_RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
R_START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
R_STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
R_TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
R_TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
R_TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_OPTIONAL_SAR
Optional Slave Address Register
0xD8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_RAW_INTR_STAT
I2C Raw Interrupt Status Register
0x34
32
read-only
n
0x0
0x0
ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
RESERVED1
reserved1
15
32
read-only
RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_RXFLR
I2C Receive FIFO Level Register
0x78
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
RXFLR
Receive FIFO Level. Contains the number of valid data entries in the receive FIFO
0
4
read-only
IC_RX_TL
I2C Receive FIFO Threshold Register
0x38
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
RX_TL
Receive FIFO Threshold Level
0
8
read-write
IC_SAR
I2C Slave Address Register
0x8
32
read-write
n
0x0
0x0
IC_SAR
The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
0
10
read-write
RESERVED1
reserved1
10
32
read-only
IC_SCL_STUCK_AT_LOW_TIMEOUT
I2C SCL Stuck at Low Timeout
0xAC
32
read-write
n
0x0
IC_SCL_STUCK_LOW_TIMEOUT
Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period
0
32
read-write
IC_SDA_HOLD
I2C SDA Hold Time Length Register
0x7C
32
read-write
n
0x0
0x0
IC_SDA_RX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver.
16
24
read-write
IC_SDA_TX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter.
0
16
read-write
RESERVED1
reserved1
24
32
read-only
IC_SDA_SETUP
I2C SDA Setup Register
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SDA_SETUP
This register controls the amount of time delay (in terms of number of ic_clk clock periods)
0
8
read-write
IC_SDA_STUCK_AT_LOW_TIMEOUT
I2C SDA Stuck at Low Timeout
0xB0
32
read-write
n
0x0
IC_SDA_STUCK_LOW_TIMEOUT
Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period.
0
32
read-write
IC_SLV_DATA_NACK_ONLY
Generate Slave Data NACK Register
0x84
32
read-write
n
0x0
0x0
NACK
Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
IC_SMBUS_CLOCK_LOW_MEXT
SMBUS Master extend clock Timeout Register
0xC0
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_MEXT_TIMEOUT
The values in this register are in units of ic_clk period..
0
32
read-write
IC_SMBUS_CLOCK_LOW_SEXT
SMBUS Slave Clock Extend Timeout Register
0xBC
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_SEXT_TIMEOUT
The values in this register are in units of ic_clk period.
0
32
read-write
IC_SMBUS_INTR_MASK
Interrupt Mask Register
0xCC
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_INTR_RAW_STATUS
SMBUS Raw Interrupt Status Register
0xD0
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_SMBUS_INTR_STAT
SMBUS Interrupt Status Register
0xC8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_THIGH_MAX_IDLE_COUNT
SMBus Thigh MAX Bus-Idle count Register
0xC4
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
16
32
read-write
SMBUS_THIGH_MAX_BUS_IDLE_CNT
The values in this register are in units of ic_clk period.
0
16
read-write
IC_SMBUS_UDID_LSB
SMBUS ARP UDID LSB Register
0xDC
32
read-write
n
0x0
0x0
IC_SMBUS_ARP_UDID_LSB
This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol.
0
32
read-write
IC_SS_SCL_HCNT
Standard Speed I2C Clock SCL High Count Register
0x14
32
read-write
n
0x0
0x0
IC_SS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_SS_SCL_LCNT
Standard Speed I2C Clock SCL Low Count Register
0x18
32
read-write
n
0x0
0x0
IC_SS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_STATUS
I2C Status Register
0x70
32
read-only
n
0x0
0x0
ACTIVITY
I2C Activity Status
0
1
read-only
MST_ACTIVITY
Master FSM Activity Status
5
6
read-only
Disable
Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active
0
Enable
Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active
1
MST_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received.
8
9
read-only
MST_HOLD_TX_FIFO_EMPTY
The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set.
7
8
read-only
RESERVED1
reserved1
12
32
read-only
RFF
Receive FIFO Completely Full
4
5
read-only
Disable
Receive FIFO is not full
0
Enable
Receive FIFO is full
1
RFNE
Receive FIFO Not Empty
3
4
read-only
Disable
Receive FIFO is not empty
0
Enable
Receive FIFO is not empty
1
SDA_STUCK_NOT_RECOVERED
This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism.
11
12
read-only
SLV_ACTIVITY
Slave FSM Activity Status
6
7
read-only
Disable
Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active
0
Enable
Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
1
SLV_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
10
11
read-only
SLV_HOLD_TX_FIFO_EMPTY
This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
9
10
read-only
TFE
Transmit FIFO Completely Empty
2
3
read-only
Disable
Transmit FIFO is not empty
0
Enable
Transmit FIFO is empty
1
TFNF
Transmit FIFO Not Full
1
2
read-only
Disable
Transmit FIFO is full
0
Enable
Transmit FIFO is not full
1
IC_TAR
I2C Target Address Register
0x4
32
read-write
n
0x0
0x0
DEVICE_ID
If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master
13
14
read-write
Disable
Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command.
0
Enable
: Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO.
1
GC_OR_START
If bit 11 (SPECIAL) is set to 1 and bit 13 (Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the I2C
10
11
read-write
Disable
The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared
0
Enable
START BYTE
1
IC_10BITADDR_MASTER
This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master
12
13
read-write
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_TAR
This is the target address for any master transaction
0
10
read-write
RESERVED1
reserved1
14
32
read-only
SPECIAL
This bit indicates whether software performs a General Call or START BYTE command
11
12
read-write
Disable
ignore bit 10 GC_OR_START and use IC_TAR normally
0
Enable
perform special I2C command as specified in GC_OR_START bit
1
IC_TXFLR
I2C Transmit FIFO Level Register
0x74
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
TXFLR
Contains the number of valid data entries in the transmit FIFO.
0
4
read-only
IC_TX_ABRT_SOURCE
I2C Transmit Abort Source Register
0x80
32
read-only
n
0x0
0x0
ABRT_10ADDR1_NOACK
1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave
1
2
read-only
ABRT_10ADDR2_NOACK
1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave
2
3
read-only
ABRT_10B_RD_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode
10
11
read-only
ABRT_7B_ADDR_NOACK
1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave
0
1
read-only
ABRT_DEVICE_NOACK
Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave
18
19
read-only
ABRT_DEVICE_SLVADDR_NOACK
Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave
19
20
read-only
ABRT_DEVICE_WRITE
Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands.
20
21
read-only
ABRT_GCALL_NOACK
1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call
4
5
read-only
ABRT_GCALL_READ
1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)
5
6
read-only
ABRT_HS_ACKDET
1: Master is in High Speed mode and the High Speed Master code was acknowledged
6
7
read-only
ABRT_HS_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
8
9
read-only
ABRT_MASTER_DIS
1: User tries to initiate a Master operation with the Master mode disabled
11
12
read-only
ABRT_SBYTE_ACKDET
1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)
7
8
read-only
ABRT_SBYTE_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte
9
10
read-only
ABRT_SDA_STUCK_AT_LOW
Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks
17
18
read-only
ABRT_SLVFLUSH_TXFIFO
1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO
13
14
read-only
ABRT_SLVRD_INTX
1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register
15
16
read-only
ABRT_SLV_ARBLOST
1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time
14
15
read-only
ABRT_TXDATA_NOACK
1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)
3
4
read-only
ABRT_USER_ABRT
This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]).
16
17
read-only
ARB_LOST
1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration
12
13
read-only
RESERVED1
reserved1
21
23
read-only
TX_FLUSH_CNT
This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt
23
32
read-only
IC_TX_TL
I2C Transmit FIFO Threshold Register
0x3C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
TX_TL
Transmit FIFO Threshold Level
0
8
read-write
I2C1
Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system
I2C
0x0
0x0
0x100
registers
n
I2C1
61
IC_ACK_GENERAL_CALL
I2C ACK General Call Register
0x98
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
1
32
read-only
IC_CLR_ACTIVITY
Clear ACTIVITY Interrupt Register
0x5C
32
read-only
n
0x0
0x0
CLR_ACTIVITY
Reading this register clears the ACTIVITY interrupt if the I2C is not active any more
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_GEN_CALL
Clear GEN_CALL Interrupt Register
0x68
32
read-only
n
0x0
0x0
CLR_GEN_CALL
Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_INTR
Clear Combined and Individual Interrupt Register
0x40
32
read-only
n
0x0
0x0
CLR_INTR
Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RD_REQ
Clear RD_REQ Interrupt Register
0x50
32
read-only
n
0x0
0x0
CLR_RD_REQ
Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RESTART_DET
Clear RESTART_DET Interrupt Register
0xA8
32
read-only
n
0x0
0x0
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_DONE
Clear RX_DONE Interrupt Register
0x58
32
read-only
n
0x0
0x0
CLR_RX_DONE
Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_OVER
Clear RX_OVER Interrupt Register
0x48
32
read-only
n
0x0
0x0
CLR_RX_OVER
Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_UNDER
Clear RX_UNDER Interrupt Register
0x44
32
read-only
n
0x0
0x0
CLR_RX_UNDER
Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SCL_STUCK_DET
Clear SCL Stuck at Low Detect Interrupt Register
0xB4
32
read-only
n
0x0
CLR_SCL_STUCK
Read this register to clear the SCL_STUCK_DET interrupt
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SMBUS_INTR
Clear SMBUS Interrupt Register
0xD4
32
read-write
n
0x0
0x0
RESERVED1
RESERVED1
0
32
read-write
IC_CLR_START_DET
Clear START_DET Interrupt Register
0x64
32
read-only
n
0x0
0x0
CLR_START_DET
Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_STOP_DET
Clear STOP_DET Interrupt Register
0x60
32
read-only
n
0x0
0x0
CLR_STOP_DET
Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_ABRT
Clear TX_ABRT Interrupt Register
0x54
32
read-only
n
0x0
0x0
CLR_TX_ABRT
Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_OVER
Clear TX_OVER Interrupt Register
0x4C
32
read-only
n
0x0
0x0
CLR_TX_OVER
Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_COMP_PARAM_1
I2C HS Spike Suppression Limit Register
0xF4
32
read-only
n
0x0
0x0
ADD_ENCODED_PARAMS
Add Encoded Parameters
7
8
read-only
False
False
0x0
True
True
0x1
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
HAS_DMA
DMA Handshake Interface signal
6
7
read-only
False
False
0x0
True
True
0x1
HC_COUNT_VALUES
Hard Code the count values
4
5
read-only
False
False
0x0
True
True
0x1
INTR_IO
Single Interrupt Output port
5
6
read-only
Individual
Individual
0x0
Combined
Combined
0x1
MAX_SPEED_MODE
Maximum Speed Mode
2
4
read-only
NONE
none
0x0
Standard
Standard
0x1
Fast
Fast
0x2
High
High
0x3
RESERVED1
reserved1
24
32
read-only
RX_BUFFER_DEPTH
Depth of receive buffer the buffer is 8 bits wide 2 to 256
8
16
read-only
TX_BUFFER_DEPTH
Depth of Transmit buffer the buffer is 8 bits wide 2 to 256
16
24
read-only
IC_COMP_TYPE
I2C Component Type Register
0xFC
32
read-only
n
0x0
IC_COMP_TYPE
Design ware Component Type number = 0x44_57_01_40
0
32
read-only
IC_COMP_VERSION
I2C Component Version Register
0xF8
32
read-only
n
0x0
IC_COMP_VERSION
Signifies the component version
0
32
read-only
IC_CON
This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.
0x0
32
read-write
n
0x0
0x0
BUS_CLEAR_FEATURE_CTRL
In Master mode.
11
12
read-write
Disable
Bus Clear Feature is disabled
0
Enable
Bus Clear Feature is enabled
1
IC_10BITADDR_MASTER_RD_ONLY
the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only
4
5
read-only
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_10BITADDR_SLAVE
When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.
3
4
read-write
Disable
7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared
0
Enable
10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
1
IC_RESTART_EN
Determines whether RESTART conditions may be sent when acting as a master
5
6
read-write
Disable
Disabled
0
Enable
Enabled
1
IC_SLAVE_DISABLE
This bit controls whether I2C has its slave disabled
6
7
read-write
Disable
slave is enabled
0
Enable
slave is disabled
1
MASTER_MODE
This bit controls whether the I2C master is enabled.
0
1
read-write
Disable
master disabled
0
Enable
master enabled
1
RESERVED1
reserved1
9
10
read-only
RESERVED2
reserved2
12
32
read-write
SPEED
These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software.
1
3
read-write
Standard Mode
standard mode (0 to 100 kbit/s)
1
Fast Mode
fast mode (less than or equal 400 kbit/s)
2
High Speed Mode
high speed mode (less than or equal 3.4 Mbit/s)
3
STOP_DET_IFADDRESSED
The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR
7
8
read-write
Disable
Issues the STOP DETECTION irrespective of whether it is addressed or not.
0
Enable
issues the STOP DETECTION interrupt only when it is addressed.
1
STOP_DET_IF_MASTER_ACTIVE
In Master mode.
10
11
read-write
Disable
Issues the STOP_DET irrespective of whether the master is active.
0
Enable
Issues the STOP_DET interrupt only when the master is active
1
TX_EMPTY_CTRL
This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register.
8
9
read-write
IC_DATA_CMD
I2C Rx/Tx Data Buffer and Command Register
0x10
32
read-write
n
0x0
0x0
CMD
This bit controls whether a read or a write is performed
8
9
write-only
Disable
write
0
Enable
Read
1
DAT
This register contains the data to be transmitted or received on the I2C bus
0
8
read-write
FIRST_DATA_BYTE
Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode
11
12
read-only
RESERVED1
reserved1
12
32
read-only
RESTART
This bit controls whether a RESTART is issued before the byte is sent or received
10
11
write-only
Disable
If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command
0
Enable
If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
1
STOP
This bit controls whether a STOP is issued after the byte is sent or received
9
10
write-only
Disable
STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty
0
Enable
STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty
1
IC_DEVICE_ID
I2C Device ID
0xB8
32
read-only
n
0x0
DEVICE_ID
Contains the Device-ID of the component assigned through the configuration parameter
0
24
read-only
RESERVED1
reserved1
24
32
read-only
IC_DMA_CR
DMA Control Register
0x88
32
read-write
n
0x0
0x0
RDMAE
Receive DMA Enable
0
1
read-write
Disable
Receive DMA disabled
0
Enable
Receive DMA enabled
1
RESERVED1
reserved1
2
32
read-only
TDMAE
Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
Disable
Transmit DMA disabled
0
Enable
Transmit DMA enabled
1
IC_DMA_RDLR
I2C Receive Data Level Register
0x90
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_DMA_TDLR
DMA Transmit Data Level Register
0x8C
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_ENABLE
Clear GEN_CALL Interrupt Register
0x6C
32
read-write
n
0x0
0x0
ABORT
When set, the controller initiates the transfer abort
1
2
read-write
Disable
ABORT not initiated or ABORT done
0
Enable
ABORT operation in progress
1
EN
Controls whether the DW_apb_i2c is enabled
0
1
read-write
Disable
Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)
0
Enable
Enables DW_apb_i2c
1
RESERVED1
reserved1
4
16
read-only
RESERVED2
reserved2
16
32
read-only
SDA_STUCK_RECOVERY_ENABLE
If SDA is stuck at low indicated through the TX_ABORT interrupt IC_TX_ABRT_SOURCE17, then this bit is used as a control knob to initiate the SDA Recovery Mechanism
3
4
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
TX_CMD_BLOCK
none
2
3
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
IC_ENABLE_STATUS
I2C Enable Status Register
0x9C
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
3
32
read-write
SLV_DISABLED_WHILE_BUSY
This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0
1
2
read-only
Disable
DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
0
Enable
DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer
1
SLV_RX_DATA_LOST
Slave Received Data Lost
2
3
read-only
Disable
DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK
0
Enable
DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer
1
IC_FS_SCL_HCNT
Fast Speed I2C Clock SCL High Count Register
0x1C
32
read-write
n
0x0
0x0
IC_FS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SCL_LCNT
Fast Speed I2C Clock SCL Low Count Register
0x20
32
read-write
n
0x0
0x0
IC_FS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SPKLEN
I2C SS and FS Spike Suppression Limit Register
IC_UFM_SPKLEN
0xA0
32
read-write
n
0x0
0x0
IC_FS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_HS_MADDR
I2C High Speed Master Mode Code Address Register
0xC
32
read-write
n
0x0
0x0
IC_HS_MAR
This bit field holds the value of the I2C HS mode master code
0
3
read-write
RESERVED1
reserved1
3
32
read-only
IC_HS_SCL_HCNT
High Speed I2C Clock SCL High Count Register
0x24
32
read-write
n
0x0
0x0
IC_HS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SCL_LCNT
High Speed I2C Clock SCL Low Count Register
0x28
32
read-write
n
0x0
0x0
IC_HS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SPKLEN
I2C HS Spike Suppression Limit Register
0xA4
32
read-write
n
0x0
0x0
IC_HS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_INTR_MASK
I2C Interrupt Mask Register
0x30
32
read-write
n
0x0
0x0
M_ACTIVITY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
8
9
read-write
M_GEN_CALL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
11
12
read-write
M_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-write
M_RD_REQ
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
5
6
read-write
M_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-write
M_RX_DONE
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
7
8
read-write
M_RX_FULL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
2
3
read-write
M_RX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
1
2
read-write
M_RX_UNDER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
0
1
read-write
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
M_START_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
10
11
read-write
M_STOP_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
9
10
read-write
M_TX_ABRT
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
6
7
read-write
M_TX_EMPTY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
4
5
read-write
M_TX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register
3
4
read-write
RESERVED1
reserved1
15
32
read-only
IC_INTR_STAT
I2C Interrupt Status Register
0x2C
32
read-only
n
0x0
0x0
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
RESERVED1
reserved1
15
32
read-only
R_ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
R_GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
R_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
R_RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
R_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
R_RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
R_RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
R_RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
R_RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
R_START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
R_STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
R_TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
R_TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
R_TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_OPTIONAL_SAR
Optional Slave Address Register
0xD8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_RAW_INTR_STAT
I2C Raw Interrupt Status Register
0x34
32
read-only
n
0x0
0x0
ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
RESERVED1
reserved1
15
32
read-only
RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_RXFLR
I2C Receive FIFO Level Register
0x78
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
RXFLR
Receive FIFO Level. Contains the number of valid data entries in the receive FIFO
0
4
read-only
IC_RX_TL
I2C Receive FIFO Threshold Register
0x38
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
RX_TL
Receive FIFO Threshold Level
0
8
read-write
IC_SAR
I2C Slave Address Register
0x8
32
read-write
n
0x0
0x0
IC_SAR
The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
0
10
read-write
RESERVED1
reserved1
10
32
read-only
IC_SCL_STUCK_AT_LOW_TIMEOUT
I2C SCL Stuck at Low Timeout
0xAC
32
read-write
n
0x0
IC_SCL_STUCK_LOW_TIMEOUT
Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period
0
32
read-write
IC_SDA_HOLD
I2C SDA Hold Time Length Register
0x7C
32
read-write
n
0x0
0x0
IC_SDA_RX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver.
16
24
read-write
IC_SDA_TX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter.
0
16
read-write
RESERVED1
reserved1
24
32
read-only
IC_SDA_SETUP
I2C SDA Setup Register
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SDA_SETUP
This register controls the amount of time delay (in terms of number of ic_clk clock periods)
0
8
read-write
IC_SDA_STUCK_AT_LOW_TIMEOUT
I2C SDA Stuck at Low Timeout
0xB0
32
read-write
n
0x0
IC_SDA_STUCK_LOW_TIMEOUT
Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period.
0
32
read-write
IC_SLV_DATA_NACK_ONLY
Generate Slave Data NACK Register
0x84
32
read-write
n
0x0
0x0
NACK
Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
IC_SMBUS_CLOCK_LOW_MEXT
SMBUS Master extend clock Timeout Register
0xC0
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_MEXT_TIMEOUT
The values in this register are in units of ic_clk period..
0
32
read-write
IC_SMBUS_CLOCK_LOW_SEXT
SMBUS Slave Clock Extend Timeout Register
0xBC
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_SEXT_TIMEOUT
The values in this register are in units of ic_clk period.
0
32
read-write
IC_SMBUS_INTR_MASK
Interrupt Mask Register
0xCC
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_INTR_RAW_STATUS
SMBUS Raw Interrupt Status Register
0xD0
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_SMBUS_INTR_STAT
SMBUS Interrupt Status Register
0xC8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_THIGH_MAX_IDLE_COUNT
SMBus Thigh MAX Bus-Idle count Register
0xC4
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
16
32
read-write
SMBUS_THIGH_MAX_BUS_IDLE_CNT
The values in this register are in units of ic_clk period.
0
16
read-write
IC_SMBUS_UDID_LSB
SMBUS ARP UDID LSB Register
0xDC
32
read-write
n
0x0
0x0
IC_SMBUS_ARP_UDID_LSB
This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol.
0
32
read-write
IC_SS_SCL_HCNT
Standard Speed I2C Clock SCL High Count Register
0x14
32
read-write
n
0x0
0x0
IC_SS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_SS_SCL_LCNT
Standard Speed I2C Clock SCL Low Count Register
0x18
32
read-write
n
0x0
0x0
IC_SS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_STATUS
I2C Status Register
0x70
32
read-only
n
0x0
0x0
ACTIVITY
I2C Activity Status
0
1
read-only
MST_ACTIVITY
Master FSM Activity Status
5
6
read-only
Disable
Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active
0
Enable
Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active
1
MST_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received.
8
9
read-only
MST_HOLD_TX_FIFO_EMPTY
The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set.
7
8
read-only
RESERVED1
reserved1
12
32
read-only
RFF
Receive FIFO Completely Full
4
5
read-only
Disable
Receive FIFO is not full
0
Enable
Receive FIFO is full
1
RFNE
Receive FIFO Not Empty
3
4
read-only
Disable
Receive FIFO is not empty
0
Enable
Receive FIFO is not empty
1
SDA_STUCK_NOT_RECOVERED
This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism.
11
12
read-only
SLV_ACTIVITY
Slave FSM Activity Status
6
7
read-only
Disable
Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active
0
Enable
Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
1
SLV_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
10
11
read-only
SLV_HOLD_TX_FIFO_EMPTY
This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
9
10
read-only
TFE
Transmit FIFO Completely Empty
2
3
read-only
Disable
Transmit FIFO is not empty
0
Enable
Transmit FIFO is empty
1
TFNF
Transmit FIFO Not Full
1
2
read-only
Disable
Transmit FIFO is full
0
Enable
Transmit FIFO is not full
1
IC_TAR
I2C Target Address Register
0x4
32
read-write
n
0x0
0x0
DEVICE_ID
If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master
13
14
read-write
Disable
Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command.
0
Enable
: Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO.
1
GC_OR_START
If bit 11 (SPECIAL) is set to 1 and bit 13 (Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the I2C
10
11
read-write
Disable
The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared
0
Enable
START BYTE
1
IC_10BITADDR_MASTER
This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master
12
13
read-write
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_TAR
This is the target address for any master transaction
0
10
read-write
RESERVED1
reserved1
14
32
read-only
SPECIAL
This bit indicates whether software performs a General Call or START BYTE command
11
12
read-write
Disable
ignore bit 10 GC_OR_START and use IC_TAR normally
0
Enable
perform special I2C command as specified in GC_OR_START bit
1
IC_TXFLR
I2C Transmit FIFO Level Register
0x74
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
TXFLR
Contains the number of valid data entries in the transmit FIFO.
0
4
read-only
IC_TX_ABRT_SOURCE
I2C Transmit Abort Source Register
0x80
32
read-only
n
0x0
0x0
ABRT_10ADDR1_NOACK
1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave
1
2
read-only
ABRT_10ADDR2_NOACK
1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave
2
3
read-only
ABRT_10B_RD_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode
10
11
read-only
ABRT_7B_ADDR_NOACK
1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave
0
1
read-only
ABRT_DEVICE_NOACK
Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave
18
19
read-only
ABRT_DEVICE_SLVADDR_NOACK
Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave
19
20
read-only
ABRT_DEVICE_WRITE
Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands.
20
21
read-only
ABRT_GCALL_NOACK
1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call
4
5
read-only
ABRT_GCALL_READ
1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)
5
6
read-only
ABRT_HS_ACKDET
1: Master is in High Speed mode and the High Speed Master code was acknowledged
6
7
read-only
ABRT_HS_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
8
9
read-only
ABRT_MASTER_DIS
1: User tries to initiate a Master operation with the Master mode disabled
11
12
read-only
ABRT_SBYTE_ACKDET
1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)
7
8
read-only
ABRT_SBYTE_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte
9
10
read-only
ABRT_SDA_STUCK_AT_LOW
Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks
17
18
read-only
ABRT_SLVFLUSH_TXFIFO
1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO
13
14
read-only
ABRT_SLVRD_INTX
1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register
15
16
read-only
ABRT_SLV_ARBLOST
1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time
14
15
read-only
ABRT_TXDATA_NOACK
1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)
3
4
read-only
ABRT_USER_ABRT
This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]).
16
17
read-only
ARB_LOST
1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration
12
13
read-only
RESERVED1
reserved1
21
23
read-only
TX_FLUSH_CNT
This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt
23
32
read-only
IC_TX_TL
I2C Transmit FIFO Threshold Register
0x3C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
TX_TL
Transmit FIFO Threshold Level
0
8
read-write
I2S0
I2S(Inter-IC Sound) is transferring two-channel digital audio data from one IC device to another
I2S
0x0
0x0
0x200
registers
n
I2S0
43
I2S_CCR
Clock Configuration Register
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
5
32
read-write
SCLKG
These bits are used to program the gating of sclk
0
3
read-write
WSS
These bits are used to program the number of sclk cycles
3
5
read-write
I2S_CER
Clock Enable Register
0xC
32
read-write
n
0x0
0x0
CLKEN
Clock generation enable/disable
0
1
read-write
Disable
none
0
Enable
none
1
RESERVED1
Reserved for future use
1
32
read-write
I2S_COMP_PARAM_1
Component Parameter 1 Register
0x1F4
32
read-only
n
0x0
0x0
APB_DATA_WIDTH
Width of APB data bus
0
2
read-only
0x0
8 Bits
0
0x1
16 Bits
1
0x2
32 Bits
2
0x3
Reserved1
3
I2S_FIFO_DEPTH_GLOBAL
Determines FIFO depth for all channels
2
4
read-only
0x0
2 Words deep
0
0x1
4 Words deep
1
0x2
8 Words deep
2
0x3
16 words deep
3
I2S_FIFO_MODE_EN
Determines whether component act as Master or Slave
4
5
read-only
Slave
Mode
0
Master
Mode
1
I2S_RECEIVER_BLOCK
Shows the presence of the receiver block
6
7
read-only
Absent
Block not present
0
Present
Block is present
1
I2S_RX_CHANNELS
Returns the number of receiver channels
7
9
read-only
00
1 Channel
0
01
2 Channels
1
10
3 Channels
2
11
4 Channels
3
I2S_TRANSMITTER_BLOCK
Shows the presence of the transmitter block
5
6
read-only
Absent
Block not present
0
Present
Block is present
1
I2S_TX_CHANNELS
Returns the number of transmitter channels
9
11
read-only
00
1 Channel
0
01
2 Channels
1
10
3 Channels
2
11
4 Channels
3
I2S_TX_WORDSIZE_0
Returns the value of word size of transmitter channel 0
16
19
read-only
I2S_TX_WORDSIZE_1
Returns the value of word size of transmitter channel 1
19
22
read-only
RESERVED1
Reserved1
11
16
read-only
RESERVED2
Reserved2
22
32
read-only
I2S_COMP_PARAM_2
Component Parameter 2 Register
0x1F0
32
read-only
n
0x0
0x0
I2S_RX_WORDSIZE_0
On Read returns the value of word size of receiver channel 0
0
3
read-only
I2S_RX_WORDSIZE_1
On Read returns the value of word size of receiver channel 1
3
6
read-only
RESERVED1
Reserved1
6
32
read-only
I2S_COMP_TYPE_REG
Component Type
0x1FC
32
read-only
n
0x0
0x0
I2S_COMP_TYPE
Return the component type
0
32
read-only
I2S_COMP_VERSION_REG
Component Version ID
0x1F8
32
read-only
n
0x0
0x0
I2S_COMP_VERSION
Return the component version(1.02)
0
32
read-only
I2S_IER
I2S Enable Register
0x0
32
read-write
n
0x0
0x0
IEN
Inter Block Enable
0
1
read-write
Disable
Disable DWP_apb_i2s
0
Enable
Enable DWP_apb_i2s
1
RESERVED1
Reserved for future use
1
32
read-write
I2S_IMR
Interrupt Mask Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
2
4
read-write
RESERVED2
Reserved for future use
6
32
read-write
RXDAM
RX Data Available Mask Interrupt
0
1
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
RXFOM
RX FIFO Overrun Mask Interrupt
1
2
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
TXFEM
TX FIFO Empty Interrupt
4
5
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
TXFOM
TX FIFO Overrun Interrupt
5
6
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
I2S_IRER
I2S Receiver Block Enable Register
0x4
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
RXEN
Receive Block Enable, Bit Overrides any Individual Receive Channel Enables
0
1
read-write
Disable
Disable Receiver
0
Enable
Enable Receiver
1
I2S_ISR
Interrupt Status Register
0x18
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
2
4
read-only
RESERVED2
Reserved for future use
6
32
read-only
RXDA
Receive Data Available
0
1
read-only
Not_reached
trigger level not reached
0
Reached
trigger level reached
1
RXFO
Receive Data FIFO
1
2
read-only
Valid
RX FIFO Write valid
0
Overrun
RX FIFO Write overrun
1
TXFE
Transmit FIFO Empty
4
5
read-only
Not_reached
trigger level not reached
0
Reached
trigger level reached
1
TXFO
Transmit FIFO
5
6
read-only
Valid
TX FIFO Write valid
0
Overrun
TX FIFO Write overrun
1
I2S_ITER
Transmitter Block Enable
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
TXEN
Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables
0
1
read-write
Disable
Transmit channel is disabled
0
Enable
Transmit channel is enabled
1
I2S_LRBR
Left Receive Buffer Register
0x0
32
read-only
n
0x0
0x0
LRBR
Data received serially from the received channel input
0
24
read-only
RESERVED1
Reserved for future use
24
32
read-only
I2S_LTHR
Left Receive Buffer Register
LRBR
0x0
32
write-only
n
0x0
0x0
LTHR
The Left Stereo Data to be transmitted serially from the Transmitted channel output
0
24
write-only
RESERVED1
Reserved for future use
24
32
write-only
I2S_RCR
Receive Configuration Register
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
3
32
read-write
WLEN
This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word
0
3
read-write
000
Ignore Word Length
0
001
12 Bit Resolution
1
010
16 Bit Resolution
2
011
20 Bit Resolution
3
100
24 Bit Resolution
4
101
32 Bit Resolution
5
I2S_RER
Receive Enable Register
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
RXCHEN
This Bit enables/disables a receive channel independently of all other channels
0
1
read-write
Disable
Receive Channel is Disable
0
Enable
Receive Channel is Disable
1
I2S_RFCR
Receive FIFO Configuration Register0
0x28
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
RXCHDT
This bits program the trigger level in the RX FIFO at which the data available interrupt is generated
0
4
read-write
I2S_RFF
Receive FIFO Flush
0x30
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RXCHFR
Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit
0
1
write-only
I2S_ROR
Receive Overrun Register
0x20
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXCHO
Read this bit to clear the RX FIFO data overrun interrupt
0
1
read-only
Valid
RX FIFO Write Valid
0
Overrun
RX FIFO Write Overrun
1
I2S_RRBR
Right Receive Buffer Register
0x4
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
24
32
read-only
RRBR
The Right Stereo Data received serially from the received channel input through this register
0
24
read-only
I2S_RRXDMA
Reset Receiver Block DMA Register
0x1C4
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RRXDMA
Writing a 1 to this self-clearing register resets the RXDMA register
0
1
write-only
I2S_RTHR
Right Transmit Holding Register
RRBR
0x4
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
24
32
write-only
RTHR
The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register
0
24
write-only
I2S_RTXDMA
Reset Transmitter Block DMA Register
0x1CC
32
write-only
n
0x0
0x0
RESERVED1
Reserved1
1
32
write-only
RTXDMA
Writing a 1 to this self-clearing register resets the TXDMA register
0
1
write-only
I2S_RXDMA
Receiver Block DMA Register
0x1C0
32
read-only
n
0x0
0x0
RXDMA
Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs
0
32
read-only
I2S_RXFFR
Receiver Block FIFO Reset Register
0x14
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RXFFR
Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
0
1
write-only
I2S_TCR
Transmit Configuration Register
0x14
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
3
32
read-write
WLEN
This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first.
0
3
read-write
000
Ignore Word Length
0
001
12 Bit Resolution
1
010
16 Bit Resolution
2
011
20 Bit Resolution
3
100
24 Bit Resolution
4
101
32 Bit Resolution
5
I2S_TER
Transmit Enable Register
0xC
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
TXCHEN
This Bit enables/disables a transmit channel independently of all other channels
0
1
read-write
Disable
Transmit Channel is Disable
0
Enable
Transmit Channel is Enable
1
I2S_TFF
Transmit FIFO Flush
0x34
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
TXCHFR
Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit
0
1
write-only
I2S_TOR
Transmit Overrun Register
0x24
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
TXCHO
Read this bit to clear the TX FIFO data overrun interrupt
0
1
read-only
Valid
TX FIFO Write Valid
0
Overrun
TX FIFO Write Overrun
1
I2S_TXDMA
Transmitter Block DMA Register
0x1C8
32
write-only
n
0x0
0x0
TXDMA
Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs
0
32
write-only
I2S_TXFCR
Transmit FIFO Configuration Register
0x2C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-only
TXCHET
This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated
0
4
read-write
I2S_TXFFR
Transmitter Block FIFO Reset Register
0x18
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
TXFFR
Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
0
1
write-only
RSVD0
none
0x38
32
read-only
n
0x0
0x0
RSVD1
none
0x3C
32
read-only
n
0x0
0x0
I2S1
I2S(Inter-IC Sound) is transferring two-channel digital audio data from one IC device to another
I2S
0x0
0x0
0x200
registers
n
I2S1
12
I2S_CCR
Clock Configuration Register
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
5
32
read-write
SCLKG
These bits are used to program the gating of sclk
0
3
read-write
WSS
These bits are used to program the number of sclk cycles
3
5
read-write
I2S_CER
Clock Enable Register
0xC
32
read-write
n
0x0
0x0
CLKEN
Clock generation enable/disable
0
1
read-write
Disable
none
0
Enable
none
1
RESERVED1
Reserved for future use
1
32
read-write
I2S_COMP_PARAM_1
Component Parameter 1 Register
0x1F4
32
read-only
n
0x0
0x0
APB_DATA_WIDTH
Width of APB data bus
0
2
read-only
0x0
8 Bits
0
0x1
16 Bits
1
0x2
32 Bits
2
0x3
Reserved1
3
I2S_FIFO_DEPTH_GLOBAL
Determines FIFO depth for all channels
2
4
read-only
0x0
2 Words deep
0
0x1
4 Words deep
1
0x2
8 Words deep
2
0x3
16 words deep
3
I2S_FIFO_MODE_EN
Determines whether component act as Master or Slave
4
5
read-only
Slave
Mode
0
Master
Mode
1
I2S_RECEIVER_BLOCK
Shows the presence of the receiver block
6
7
read-only
Absent
Block not present
0
Present
Block is present
1
I2S_RX_CHANNELS
Returns the number of receiver channels
7
9
read-only
00
1 Channel
0
01
2 Channels
1
10
3 Channels
2
11
4 Channels
3
I2S_TRANSMITTER_BLOCK
Shows the presence of the transmitter block
5
6
read-only
Absent
Block not present
0
Present
Block is present
1
I2S_TX_CHANNELS
Returns the number of transmitter channels
9
11
read-only
00
1 Channel
0
01
2 Channels
1
10
3 Channels
2
11
4 Channels
3
I2S_TX_WORDSIZE_0
Returns the value of word size of transmitter channel 0
16
19
read-only
I2S_TX_WORDSIZE_1
Returns the value of word size of transmitter channel 1
19
22
read-only
RESERVED1
Reserved1
11
16
read-only
RESERVED2
Reserved2
22
32
read-only
I2S_COMP_PARAM_2
Component Parameter 2 Register
0x1F0
32
read-only
n
0x0
0x0
I2S_RX_WORDSIZE_0
On Read returns the value of word size of receiver channel 0
0
3
read-only
I2S_RX_WORDSIZE_1
On Read returns the value of word size of receiver channel 1
3
6
read-only
RESERVED1
Reserved1
6
32
read-only
I2S_COMP_TYPE_REG
Component Type
0x1FC
32
read-only
n
0x0
0x0
I2S_COMP_TYPE
Return the component type
0
32
read-only
I2S_COMP_VERSION_REG
Component Version ID
0x1F8
32
read-only
n
0x0
0x0
I2S_COMP_VERSION
Return the component version(1.02)
0
32
read-only
I2S_IER
I2S Enable Register
0x0
32
read-write
n
0x0
0x0
IEN
Inter Block Enable
0
1
read-write
Disable
Disable DWP_apb_i2s
0
Enable
Enable DWP_apb_i2s
1
RESERVED1
Reserved for future use
1
32
read-write
I2S_IMR
Interrupt Mask Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
2
4
read-write
RESERVED2
Reserved for future use
6
32
read-write
RXDAM
RX Data Available Mask Interrupt
0
1
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
RXFOM
RX FIFO Overrun Mask Interrupt
1
2
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
TXFEM
TX FIFO Empty Interrupt
4
5
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
TXFOM
TX FIFO Overrun Interrupt
5
6
read-write
Unmask
Unmask Interrupt
0
Mask
Mask Interrupt
1
I2S_IRER
I2S Receiver Block Enable Register
0x4
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
RXEN
Receive Block Enable, Bit Overrides any Individual Receive Channel Enables
0
1
read-write
Disable
Disable Receiver
0
Enable
Enable Receiver
1
I2S_ISR
Interrupt Status Register
0x18
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
2
4
read-only
RESERVED2
Reserved for future use
6
32
read-only
RXDA
Receive Data Available
0
1
read-only
Not_reached
trigger level not reached
0
Reached
trigger level reached
1
RXFO
Receive Data FIFO
1
2
read-only
Valid
RX FIFO Write valid
0
Overrun
RX FIFO Write overrun
1
TXFE
Transmit FIFO Empty
4
5
read-only
Not_reached
trigger level not reached
0
Reached
trigger level reached
1
TXFO
Transmit FIFO
5
6
read-only
Valid
TX FIFO Write valid
0
Overrun
TX FIFO Write overrun
1
I2S_ITER
Transmitter Block Enable
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
TXEN
Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables
0
1
read-write
Disable
Transmit channel is disabled
0
Enable
Transmit channel is enabled
1
I2S_LRBR
Left Receive Buffer Register
0x0
32
read-only
n
0x0
0x0
LRBR
Data received serially from the received channel input
0
24
read-only
RESERVED1
Reserved for future use
24
32
read-only
I2S_LTHR
Left Receive Buffer Register
LRBR
0x0
32
write-only
n
0x0
0x0
LTHR
The Left Stereo Data to be transmitted serially from the Transmitted channel output
0
24
write-only
RESERVED1
Reserved for future use
24
32
write-only
I2S_RCR
Receive Configuration Register
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
3
32
read-write
WLEN
This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word
0
3
read-write
000
Ignore Word Length
0
001
12 Bit Resolution
1
010
16 Bit Resolution
2
011
20 Bit Resolution
3
100
24 Bit Resolution
4
101
32 Bit Resolution
5
I2S_RER
Receive Enable Register
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
RXCHEN
This Bit enables/disables a receive channel independently of all other channels
0
1
read-write
Disable
Receive Channel is Disable
0
Enable
Receive Channel is Disable
1
I2S_RFCR
Receive FIFO Configuration Register0
0x28
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
RXCHDT
This bits program the trigger level in the RX FIFO at which the data available interrupt is generated
0
4
read-write
I2S_RFF
Receive FIFO Flush
0x30
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RXCHFR
Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit
0
1
write-only
I2S_ROR
Receive Overrun Register
0x20
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXCHO
Read this bit to clear the RX FIFO data overrun interrupt
0
1
read-only
Valid
RX FIFO Write Valid
0
Overrun
RX FIFO Write Overrun
1
I2S_RRBR
Right Receive Buffer Register
0x4
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
24
32
read-only
RRBR
The Right Stereo Data received serially from the received channel input through this register
0
24
read-only
I2S_RRXDMA
Reset Receiver Block DMA Register
0x1C4
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RRXDMA
Writing a 1 to this self-clearing register resets the RXDMA register
0
1
write-only
I2S_RTHR
Right Transmit Holding Register
RRBR
0x4
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
24
32
write-only
RTHR
The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register
0
24
write-only
I2S_RTXDMA
Reset Transmitter Block DMA Register
0x1CC
32
write-only
n
0x0
0x0
RESERVED1
Reserved1
1
32
write-only
RTXDMA
Writing a 1 to this self-clearing register resets the TXDMA register
0
1
write-only
I2S_RXDMA
Receiver Block DMA Register
0x1C0
32
read-only
n
0x0
0x0
RXDMA
Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs
0
32
read-only
I2S_RXFFR
Receiver Block FIFO Reset Register
0x14
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
RXFFR
Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
0
1
write-only
I2S_TCR
Transmit Configuration Register
0x14
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
3
32
read-write
WLEN
This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first.
0
3
read-write
000
Ignore Word Length
0
001
12 Bit Resolution
1
010
16 Bit Resolution
2
011
20 Bit Resolution
3
100
24 Bit Resolution
4
101
32 Bit Resolution
5
I2S_TER
Transmit Enable Register
0xC
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
TXCHEN
This Bit enables/disables a transmit channel independently of all other channels
0
1
read-write
Disable
Transmit Channel is Disable
0
Enable
Transmit Channel is Enable
1
I2S_TFF
Transmit FIFO Flush
0x34
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
TXCHFR
Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit
0
1
write-only
I2S_TOR
Transmit Overrun Register
0x24
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
TXCHO
Read this bit to clear the TX FIFO data overrun interrupt
0
1
read-only
Valid
TX FIFO Write Valid
0
Overrun
TX FIFO Write Overrun
1
I2S_TXDMA
Transmitter Block DMA Register
0x1C8
32
write-only
n
0x0
0x0
TXDMA
Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs
0
32
write-only
I2S_TXFCR
Transmit FIFO Configuration Register
0x2C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-only
TXCHET
This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated
0
4
read-write
I2S_TXFFR
Transmitter Block FIFO Reset Register
0x18
32
write-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
write-only
TXFFR
Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit
0
1
write-only
RSVD0
none
0x38
32
read-only
n
0x0
0x0
RSVD1
none
0x3C
32
read-only
n
0x0
0x0
IR
IR Decoder are used for the decoding the external ir sensor input.
IR
0x0
0x0
0x1C
registers
n
IR
15
CONFIG
This register used to configure the ir structure for application purpose.
0x10
32
read-write
n
EN_CLK_IR_CORE
Enable 32KHz clock to IR Core bit ,if bit 1 then clock gating disable and bit is 0 then clock gating Enable
2
3
read-write
EN_CONT_IR_DET
This bit is Enable continues IR detection,When enabled there will be no power cycling on External IR Sensor.
8
9
read-write
EN_IR_DET
Enable IR detection logic bit if bit 1 then detection enable if 0 then not enable.
0
1
read-write
IR_DET_RSTART
Enable IR detection re-start logic bit if bit 1 then re-start.
1
2
read-write
RES
reserved5
3
8
read-only
RES1
reserved6
9
16
read-only
RES2
reserved7
17
32
read-only
SREST_IR_CORE
This bit is used soft reset IR core block
16
17
read-write
DET_THRESHOLD
This register used Minimum Number of edges to detected during on-time failing which IR detection is re-stated.
0xC
32
read-write
n
IR_DET_THRESHOLD
Minimum Number of edges to detected during on-time failing which IR detection is re-stated.
0
7
read-write
RES
reserved5
7
32
read-only
FRAME_DONE_THRESHOLD
This register used count with respect to 32KHz clock after not more toggle are expected to a given pattern.
0x8
32
read-write
n
IR_FRAME_DONE_THRESHOLD
count with respect to 32KHz clock after not more toggle are expected to a given pattern
0
15
read-write
RES
reserved5
15
32
read-only
MEM_ADDR_ACCESS
This register used to access memory address for application purpose.
0x14
32
read-write
n
IR_MEM_ADDR
This field is used to IR read address.
0
7
read-write
IR_MEM_RD_EN
This field used to IR memory read enable.
9
10
read-write
RES
reserved5
7
9
read-only
RES1
reserved6
10
32
read-only
MEM_READ
This register used to IR Read data from memory.
0x18
32
read-only
n
IR_DATA_MEM_DEPTH
This field used to indicated valid number of IR Address in the memory to be read.
24
31
read-only
IR_MEM_DATA_OUT
This field is used to IR Read data from memory.
0
16
read-only
RES
reserved5
16
24
read-only
RES1
reserved6
31
32
read-only
OFF_TIME_DURATION
This register used for IR sleep duration timer value.
0x0
32
read-write
n
IR_OFF_TIME_DURATION
This field define ir off time
0
17
read-write
RES
reserved5
17
32
read-only
ON_TIME_DURATION
This register used for IR Detection duration timer value.
0x4
32
read-write
n
IR_ON_TIME_DURATION
This field define ir on time for ir detection on
0
12
read-write
RES
reserved5
12
32
read-only
MCPWM
The Motor Control PWM (MCPWM) controller is used to generate a periodic pulse waveform, which is useful in motor control and power control applications
MCPWM
0x0
0x0
0x14C
registers
n
MCPWM
48
PWM_DEADTIME_A
PWM deadtime for A and channel varies from 0 to 3
0x0
32
read-write
n
0x0
0x0
DEADTIME_A_CH
Dead time A value to load into dead time counter A of channel0 to channel3
0
6
read-write
RESERVED1
reserved1
6
32
read-write
PWM_DEADTIME_B
PWM deadtime for B and channel varies from 0 to 3
0x4
32
read-write
n
0x0
0x0
DEADTIME_B_CH
Dead time B value to load into deadtime counter B of channel0 to channel3
0
6
read-write
RESERVED1
reserved1
6
32
read-write
PWM_DEADTIME_CTRL_RESET_REG
Dead time Control Reset Register
0x7C
32
read-write
n
0x0
0x0
DEADTIME_DISABLE_FRM_REG
Dead time counter soft reset for each channel.
8
12
read-write
DEADTIME_SELECT_ACTIVE
Dead time select bits for PWM going active
0
4
read-write
Disable
means use counter A
0
Enable
means use counter B
1
DEADTIME_SELECT_INACTIVE
Dead time select bits for PWM going inactive
4
8
read-write
Disable
means use counter A
0
Enable
means use counter B
1
RESERVED1
reserved1
12
32
read-only
PWM_DEADTIME_CTRL_SET_REG
Dead time Control Set Register
0x78
32
read-write
n
0x0
0x0
DEADTIME_DISABLE_FRM_REG
Dead time counter soft reset for each channel.
8
12
read-write
DEADTIME_SELECT_ACTIVE
Dead time select bits for PWM going active
0
4
read-write
Disable
means use counter A
0
Enable
means use counter B
1
DEADTIME_SELECT_INACTIVE
Dead time select bits for PWM going inactive
4
8
read-write
Disable
means use counter A
0
Enable
means use counter B
1
RESERVED1
reserved1
12
32
read-only
PWM_DEADTIME_PRESCALE_SELECT_A
Dead time Prescale Select Register for A
0x80
32
read-write
n
0x0
0x0
DEADTIME_PRESCALE_SELECT_A
Dead time prescale selection bits for unit A.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
PWM_DEADTIME_PRESCALE_SELECT_B
Dead time Prescale Select Register for B
0x84
32
read-write
n
0x0
0x0
DEADTIME_PRESCALE_SELECT_B
Dead time prescale selection bits for unit B
0
8
read-write
RESERVED1
reserved1
8
32
read-only
PWM_DUTYCYCLE_CTRL_RESET_REG
Duty cycle Control Reset Register
0x54
32
read-write
n
0x0
0x0
DUTYCYCLE_UPDATE_DISABLE
Duty cycle register updation disable. There is a separate bit for each channel.
4
8
read-write
IMDT_DUTYCYCLE_UPDATE_EN
Enable to update the duty cycle immediately
0
4
read-write
RESERVED1
reserved1
8
32
read-only
PWM_DUTYCYCLE_CTRL_SET_REG
Duty cycle Control Set Register
0x50
32
read-write
n
0x0
0x0
DUTYCYCLE_UPDATE_DISABLE
Duty cycle register updation disable. There is a separate bit for each channel
4
8
read-write
IMDT_DUTYCYCLE_UPDATE_EN
Enable to update the duty cycle immediately
0
4
read-write
RESERVED1
reserved1
8
32
read-only
PWM_DUTYCYCLE_REG_WR_VALUE0
Duty cycle Value Register for Channel0 to channel3
0x58
32
read-write
n
0x0
0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH
Duty cycle value for channel0 to channel3
0
16
read-write
RESERVED1
reserved1
16
32
read-only
PWM_DUTYCYCLE_REG_WR_VALUE1
Duty cycle Value Register for Channel0 to channel3
0x5C
32
read-write
n
0x0
0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH
Duty cycle value for channel0 to channel3
0
16
read-write
RESERVED1
reserved1
16
32
read-only
PWM_DUTYCYCLE_REG_WR_VALUE2
Duty cycle Value Register for Channel0 to channel3
0x60
32
read-write
n
0x0
0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH
Duty cycle value for channel0 to channel3
0
16
read-write
RESERVED1
reserved1
16
32
read-only
PWM_DUTYCYCLE_REG_WR_VALUE3
Duty cycle Value Register for Channel0 to channel3
0x64
32
read-write
n
0x0
0x0
PWM_DUTYCYCLE_REG_WR_VALUE_CH
Duty cycle value for channel0 to channel3
0
16
read-write
RESERVED1
reserved1
16
32
read-only
PWM_FLT_A_OVERRIDE_VALUE_REG
Fault input A PWM override value
0xE8
32
read-write
n
0x0
0x0
PWM_FLT_A_OVERRIDE_VALUE_H0
4 bit for H0
4
5
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_H1
5 bit for H1
5
6
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_H2
6 bit for H2
6
7
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_H3
7 bit for H3
7
8
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_L0
0 bit for L0
0
1
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_L1
1 bit for L1
1
2
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_L2
2 bit for L2
2
3
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_A_OVERRIDE_VALUE_L3
3 bit for L3
3
4
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
RESERVED1
reserved1
8
32
read-write
PWM_FLT_B_OVERRIDE_VALUE_REG
Fault input B PWM override value
0xEC
32
read-write
n
0x0
0x0
PWM_FLT_B_OVERRIDE_VALUE_H0
4 bit for H0
4
5
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_H1
5 bit for H1
5
6
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_H2
6 bit for H2
6
7
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_H3
7 bit for H3
7
8
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_L0
0 bit for L0
0
1
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_L1
1 bit for L1
1
2
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_L2
2 bit for L2
2
3
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
PWM_FLT_B_OVERRIDE_VALUE_L3
3 bit for L3
3
4
read-write
Inactive
0 means PWM output pin is driven inactive on an external fault input A event
0
Active
1 means PWM output pin is driven active on an external fault input A event.
1
RESERVED1
reserved1
8
32
read-write
PWM_FLT_OVERRIDE_CTRL_RESET_REG
fault override control reset register
0xE4
32
read-write
n
0x0
0x0
COMPLEMENTARY_MODE
PWM I/O pair mode
12
16
read-write
Disable
PWM I/O pin pair is in the independent output mode
0
Enable
PWM I/O pin pair is in the complementary output mode
1
FLT_A_ENABLE
Fault A enable. Separate enable bit is present for channel
4
8
read-write
FLT_A_MODE
Fault B mode
0
1
read-write
Disable
latched mode
0
Enable
cycle by cycle by mode
1
FLT_B_ENABLE
Fault B enable. Separate enable bit is present for channel
8
12
read-write
FLT_B_MODE
Fault B mode
1
2
read-write
Disable
latched mode
0
Enable
cycle by cycle by mode
1
OP_POLARITY_H
Ouput polarity for high (H3, H2, H1, H0) side signals
2
3
read-write
Disable
means active low mode
0
Enable
means active high mode
1
OP_POLARITY_L
Ouput polarity for low (L3, L2, L1, L0) side signals.
3
4
read-write
Disable
means active low mode
0
Enable
means active high mode
1
RESERVED1
reserved1
16
32
read-write
PWM_FLT_OVERRIDE_CTRL_SET_REG
fault override control set register
0xE0
32
read-write
n
0x0
0x0
COMPLEMENTARY_MODE
PWM I/O pair mode
12
16
read-write
Disable
PWM I/O pin pair is in the independent output mode
0
Enable
PWM I/O pin pair is in the complementary output mode
1
FLT_A_ENABLE
Fault A enable. Separate enable bit is present for channel
4
8
read-write
FLT_A_MODE
Fault A mode
0
1
read-write
Disable
latched mode
0
Enable
cycle by cycle by mode
1
FLT_B_ENABLE
Fault B enable. Separate enable bit is present for channel
8
12
read-write
FLT_B_MODE
Fault B mode
1
2
read-write
Disable
latched mode
0
Enable
cycle by cycle by mode
1
OP_POLARITY_H
Ouput polarity for high (H3, H2, H1, H0) side signals
2
3
read-write
Disable
means active low mode
0
Enable
means active high mode
1
OP_POLARITY_L
Ouput polarity for low (L3, L2, L1, L0) side signals.
3
4
read-write
Disable
means active low mode
0
Enable
means active high mode
1
RESERVED1
reserved1
16
32
read-write
PWM_INTR_ACK
PWM Interrupt Acknowledgement Register
0xC
32
read-write
n
0x0
0x0
FLT_A_INTR_ACK
pwm fault A interrupt will be cleared.
2
3
write-only
Disable
No effect
0
Enable
pwm faultA interrupt will be cleared
1
FLT_B_INTR_ACK
pwm fault B interrupt will be cleared.
3
4
write-only
Disable
No effect
0
Enable
pwm faultB interrupt will be cleared.
1
PWM_TIME_PRD_MATCH_INTR_CH0_ACK
pwm time period match interrupt for 0th channel will be cleared
1
2
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 0th channel will be cleared
1
PWM_TIME_PRD_MATCH_INTR_CH1_ACK
pwm time period match interrupt for 1st channel will be cleared.
5
6
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 1st channel will be cleared.
1
PWM_TIME_PRD_MATCH_INTR_CH2_ACK
pwm time period match interrupt for 2nd channel will be cleared.
7
8
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 2nd channel will be cleared.
1
PWM_TIME_PRD_MATCH_INTR_CH3_ACK
pwm time period match interrupt for 3rd channel will be cleared.
9
10
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 3rd channel will be cleared
1
RESERVED1
reserved1
10
32
read-write
RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK
pwm time period match interrupt for 0th channel will be cleared.
0
1
write-only
Disable
No effect.
0
Enable
PWM time period match interrupt for 0th channel will be cleared.
1
RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK
pwm time period match interrupt for 1st channel will be cleared
4
5
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 1st channel will be cleared
1
RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK
pwm time period match interrupt for 2nd channel will be cleared.
6
7
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 2nd channel will be cleared
1
RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK
pwm time period match interrupt for 3rd channel will be cleared.
8
9
write-only
Disable
No effect
0
Enable
pwm time period match interrupt for 3rd channel will be cleared
1
PWM_INTR_MASK
PWM Interrupt mask Register
0x8
32
read-write
n
0x0
0x0
PWM_INTR_UNMASK
Interrupt Mask
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_INTR_STS
PWM Interrupt Status Register
0x0
32
read-only
n
0x0
FLT_A_INTR
When the fault A pin is driven low, this interrupt is raised.
2
3
read-only
FLT_B_INTR
When the fault B pin is driven low, this interrupt is raised.
3
4
read-only
PWM_TIME_PRD_MATCH_INTR_CH0
This time base interrupt for 0th channel, which considers postscaler value
1
2
read-only
PWM_TIME_PRD_MATCH_INTR_CH1
This time base interrupt for 1st channel, which considers postscaler value.
5
6
read-only
PWM_TIME_PRD_MATCH_INTR_CH2
This time base interrupt for 2nd channel, which considers postscaler value
7
8
read-only
PWM_TIME_PRD_MATCH_INTR_CH3
This time base interrupt for 3rd channel, which considers postscaler value.
9
10
read-only
RESERVED1
reserved1
10
32
read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0
This time base interrupt for 0th channel without considering postscaler
0
1
read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1
This time base interrupt for 1st channel without considering postscaler value
4
5
read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2
This time base interrupt for 2nd channel without considering postscaler value.
6
7
read-only
RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3
This time base interrupt for 3rd channel without considering postscaler value.
8
9
read-only
PWM_INTR_UNMASK
PWM Interrupt Unmask Register
0x4
32
read-write
n
0x0
0x0
PWM_INTR_UNMASK
Interrupt Unmask
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_OP_OVERRIDE_CTRL_RESET_REG
output override control reset register
0xCC
32
read-write
n
0x0
0x0
OP_OVERRIDE_SYNC
Output override is synced with pwm time period depending on operating mode
0
1
read-write
RESERVED1
reserved1
1
32
read-write
PWM_OP_OVERRIDE_CTRL_SET_REG
output override control set register
0xC8
32
read-write
n
0x0
0x0
OP_OVERRIDE_SYNC
Output override is synced with pwm time period depending on operating mode
0
1
read-write
RESERVED1
reserved1
1
32
read-only
PWM_OP_OVERRIDE_ENABLE_RESET_REG
output override enable reset register
0xD4
32
read-write
n
0x0
0x0
PWM_OP_OVERRIDE_ENABLE_REG
Pwm output over ride enable
0
8
read-write
RESERVED1
reserved1
8
32
read-write
PWM_OP_OVERRIDE_ENABLE_SET_REG
output override enable set register
0xD0
32
read-write
n
0x0
0x0
PWM_OP_OVERRIDE_ENABLE_REG
Pwm output over ride enable
0
8
read-write
RESERVED1
reserved1
8
32
read-write
PWM_OP_OVERRIDE_VALUE_RESET_REG
output override enable reset register
0xDC
32
read-write
n
0x0
0x0
OP_OVERRIDE_VALUE
Pwm output over ride value.
0
8
read-write
RESERVED1
reserved1
8
32
read-write
PWM_OP_OVERRIDE_VALUE_SET_REG
output override value set register
0xD8
32
read-write
n
0x0
0x0
OP_OVERRIDE_VALUE
Pwm output over ride value.
0
8
read-write
RESERVED1
reserved1
8
32
read-write
PWM_SVT_COMPARE_VALUE_REG
Special event compare value register
0xFC
32
read-write
n
0x0
0x0
PWM_SVT_COMPARE_VALUE
Special event compare value. This is used to compare with pwm time period counter to generate special event trigger
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_SVT_CTRL_RESET_REG
Special event control reset register
0xF4
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-write
SVT_DIRECTION_FRM
Special event trigger for time base direction
1
2
read-write
COUNT_UP
A special event trigger will occur when PWM time base is counting up
0
COUNT_DOWN
A special event trigger will occur when PWM time base is counting down
1
SVT_ENABLE_FRM
Special event trigger enable. This is used to enable generation special event trigger
0
1
read-write
PWM_SVT_CTRL_SET_REG
NONE
0xF0
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-write
SVT_DIRECTION_FRM
Special event trigger for time base direction
1
2
read-write
COUNT_UP
A special event trigger will occur when PWM time base is counting up
0
COUNT_DOWN
A special event trigger will occur when PWM time base is counting down
1
SVT_ENABLE_FRM
Special event trigger enable. This is used to enable generation special event trigger
0
1
read-write
PWM_SVT_PARAM_REG
Special event parameter register
0xF8
32
read-write
n
0x0
0x0
RESERVED1
reserved1
4
32
read-write
SVT_POSTSCALER_SELECT
PWM special event trigger output postscale select bits
0
4
read-write
PWM_TIME_PRD_CNTR_VALUE_CH0
Base Time period counter current value register for channel0
0x3C
32
read-only
n
0x0
0x0
PWM_TIME_PRD_CNTR_VALUE_CH0
Time period counter current value for channel0
0
16
read-only
RESERVED1
reserved1
16
32
read-only
PWM_TIME_PRD_CNTR_VALUE_CH1
Time period counter current value for channel1
0x114
32
read-write
n
0x0
0x0
PWM_TIME_PRD_CNTR_VALUE_CH1
Time period counter current value for channel1
0
1
read-write
RESERVED1
reserved1
1
32
read-only
PWM_TIME_PRD_CNTR_VALUE_CH2
Time period counter current value register for channel2
0x12C
32
read-only
n
0x0
0x0
PWM_TIME_PRD_CNTR_VALUE_CH2
Time period counter current value for channel2
0
1
read-only
RESERVED1
reserved1
1
12
read-only
RESERVED2
reserved2
12
32
read-only
PWM_TIME_PRD_CNTR_VALUE_CH3
Time period counter current value register for channel3
0x144
32
read-only
n
0x0
0x0
PWM_TIME_PRD_CNTR_VALUE_CH3
Time period counter current value for channe3
0
16
read-only
RESERVED1
reserved1
16
32
read-only
PWM_TIME_PRD_CNTR_WR_REG_CH0
Base time counter initial value register for channel 0
0x2C
32
read-write
n
0x0
0x0
PWM_TIME_PRD_CNTR_WR_REG_CH0
To update the base time counter initial value for channel 0
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_CNTR_WR_REG_CH1
Base time counter initial value register for channel1
0x104
32
read-write
n
0x0
0x0
PWM_TIME_PRD_CNTR_WR_REG_CH1
To update the base time counter initial value for channel 1
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_CNTR_WR_REG_CH2
Base time counter initial value register for channal2
0x11C
32
read-write
n
0x0
0x0
PWM_TIME_PRD_CNTR_WR_REG_CH2
To update the base time counter initial value for channel 2
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_CNTR_WR_REG_CH3
Base time counter initial value register for channel3
0x134
32
read-write
n
0x0
0x0
PWM_TIME_PRD_REG_WR_VALUE_CH3
Value to update the base timer period register of channel 3
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_COMMON_REG
Time period common register
0x148
32
read-write
n
0x0
0x0
PWM_TIME_PRD_COMMON_TIMER_VALUE
Base timers select to generate special event trigger
1
3
read-write
PWM_TIME_PRD_USE_0TH_TIMER_ONLY
Instead of use four base timers for four channels, use only one base timer for all channels.
0
1
read-write
ONE_TIMER_ONE_CHANNEL
one base timer for each channel
0
ONE_TIMER_ALL_CHANNEL
only one base timer for all channels
1
RESERVED1
reserved1
4
32
read-write
USE_EXT_TIMER_TRIG_FRM_REG
Enable to use external trigger for base time counter increment or decrement.
3
4
read-write
PWM_TIME_PRD_CTRL_REG_CH0
Base time counter initial value register for channel 0
0x34
32
read-write
n
0x0
0x0
PWM_SFT_RST
MC PWM soft reset
2
3
read-write
PWM_TIME_BASE_EN_FRM_REG_CH0
Base timer enable for channnel0
1
2
read-write
Disable
timer is disabled
0
Enable
timer is enabled
1
PWM_TIME_PRD_CNTR_RST_FRM_REG
Time period counter soft reset
0
1
read-write
RESERVED1
reserved1
3
32
read-only
PWM_TIME_PRD_CTRL_REG_CH1
Base time period control register for channel1
0x10C
32
read-write
n
0x0
0x0
PWM_SFT_RST
MC PWM soft reset
2
3
read-write
PWM_TIME_BASE_EN_FRM_REG_CH1
Base timer enable for channnel1
1
2
read-write
Disable
timer is disabled
0
Enable
timer is enabled
1
PWM_TIME_PRD_CNTR_RST_FRM_REG
Time period counter soft reset
0
1
read-write
RESERVED1
reserved1
3
32
read-write
PWM_TIME_PRD_CTRL_REG_CH2
Base time period control register for channel2
0x124
32
read-write
n
0x0
0x0
PWM_SFT_RST
MC PWM soft reset
2
3
read-write
PWM_TIME_BASE_EN_FRM_REG_CH2
Base timer enable for channnel2
1
2
read-write
Disable
timer is disabled
0
Enable
timer is enabled
1
PWM_TIME_PRD_CNTR_RST_FRM_REG
Time period counter soft reset
0
1
read-write
RESERVED1
reserved1
3
32
read-write
PWM_TIME_PRD_CTRL_REG_CH3
Base time period control register for channel3
0x13C
32
read-write
n
0x0
0x0
PWM_SFT_RST
MC PWM soft reset
2
3
read-write
PWM_TIME_BASE_EN_FRM_REG_CH3
Base timer enable for channnel3
1
2
read-write
Disable
timer is disabled
0
Enable
timer is enabled
1
PWM_TIME_PRD_CNTR_RST_FRM_REG
Time period counter soft reset
0
1
read-write
RESERVED1
reserved1
3
32
read-write
PWM_TIME_PRD_PARAM_REG_CH0
Base time period config parameter's register for channel0
0x30
32
read-write
n
0x0
0x0
PWM_TIME_PRD_POST_SCALAR_VALUE_CH0
Time base output post scale bits for channel0
8
12
read-write
1:1_POST_SCALE
0000 1 to 1 post scale
0
1:2_POST_SCALE
0001 1 to 2
1
1:11_POST_SCALE
1010 1 to 11
10
1:12_POST_SCALE
1011 1:12
11
1:13_POST_SCALE
1100 1:13
12
1:14_POST_SCALE
1101 1 to 14
13
1:15_POST_SCALE
1110 1 to 15
14
1:16_POST_SCALE
1111 1 to 16
15
1:3_POST_SCALE
0010 1 to 3
2
1:4_POST_SCALE
0011 1 to 4
3
1:5_POST_SCALE
0100 1 to 5
4
1:6_POST_SCALE
0101 1 to 6
5
1:7_POST_SCALE
0110 1 to 7
6
1:8_POST_SCALE
0111 1 to 8
7
1:9_POST_SCALE
1000 1 to 9
8
1:10_POST_SCALE
1001 1 to 10
9
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0
Base timer input clock pre scale select value for channel0.
4
7
read-write
1X_CLOCK_PERIOD
1x input clock period
0
2X_CLOCK_PERIOD
2x input clock period
1
4X_CLOCK_PERIOD
4x input clock period
2
16X_CLOCK_PERIOD
16x input clock period
3
32X_CLOCK_PERIOD
32x input clock period
4
NONE1
none1
5
64X_CLOCK_PERIOD
64x input clock period
6
NONE2
none2
7
RESERVED1
reserved1
3
4
read-write
RESERVED2
reserved2
7
8
read-write
RESERVED3
reserved3
12
32
read-write
TMR_OPEARATING_MODE_CH0
Base timer operating mode for channel0
0
3
read-write
FREE_RUNNING_MODE
free running mode
0
SINGLE_EVENT_MODE
single event mode
1
DOWN_COUNT_MODE
down count mode
2
NONE1
none1
3
UP_DOWN_MODE
up/down mode
4
UP_DOWN_DOUBLER_MODE
up/down mode with interrupts for double PWM updates
5
NONE2
none2
6
NONE3
none3
7
PWM_TIME_PRD_PARAM_REG_CH1
NONE
0x108
32
read-write
n
0x0
0x0
PWM_TIME_PRD_POST_SCALAR_VALUE_CH1
Time base output post scale bits for channel1
8
12
read-write
1:1_post_scale
0000 1:1 post scale
0
1:2_post_scale
0001 1:2
1
1:11_post_scale
1010 1:11
10
1:12_post_scale
1011 1:12
11
1:13_post_scale
1100 1:13
12
1:14_post_scale
1101 1:14
13
1:15_post_scale
1110 1:15
14
1:16_post_scale
1111 1:16
15
1:3_post_scale
0010 1:3
2
1:4_post_scale
0011 1:4
3
1:5_post_scale
0100 1:5
4
1:6_post_scale
0101 1:6
5
1:7_post_scale
0110 1:7
6
1:8_post_scale
0111 1:8
7
1:9_post_scale
1000 1:9
8
1:10_post_scale
1001 1:10
9
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1
Base timer input clock prescale select value for channel1.
4
7
read-write
1x_clock_period
1x input clock period
0
2x_clock_period
2x input clock period
1
4x_clock_period
4x input clock period
2
16x_clock_period
16x input clock period
3
32x_clock_period
32x input clock period
4
NONE1
none2
5
64x_clock_period
64x input clock period
6
NONE2
none1
7
RESERVED1
reserved1
3
4
read-write
RESERVED2
reserved2
7
8
read-write
RESERVED3
reserved3
12
32
read-write
TMR_OPEARATING_MODE_CH1
Base timer operating mode for channel1
0
3
read-write
FREE_RUNNING_MODE
free running mode
0
SINGLE_EVENT_MODE
single event mode
1
DOWN_COUNT_MODE
down count mode
2
NONE1
none1
3
UP_DOWN_MODE
up/down mode
4
UP_DOWN_DOUBLER_MODE
up/dowm mode with interrupts for double PWM updates
5
NONE2
none2
6
NONE3
none3
7
PWM_TIME_PRD_PARAM_REG_CH2
Base time period config parameter's register for channel2
0x120
32
read-write
n
0x0
0x0
PWM_TIME_PRD_POST_SCALAR_VALUE_CH2
Time base output post scale bits for channel2
8
12
read-write
1:1_POST_SCALE
0000 1:1 post scale
0
1:2_POST_SCALE
0001 1:2
1
1:11_POST_SCALE
1010 1:11
10
1:12_POST_SCALE
1011 1:12
11
1:13_POST_SCALE
1100 1:13
12
1:14_POST_SCALE
1101 1:14
13
1:15_POST_SCALE
1110 1:15
14
1:16_POST_SCALE
1111 1:16
15
1:3_POST_SCALE
0010 1:3
2
1:4_POST_SCALE
0011 1:4
3
1:5_POST_SCALE
0100 1:5
4
1:6_POST_SCALE
0101 1:6
5
1:7_POST_SCALE
0110 1:7
6
1:8_POST_SCALE
0111 1:8
7
1:9_POST_SCALE
1000 1:9
8
1:10_POST_SCALE
1001 1:10
9
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2
Base timer input clock pre scale select value for channel2.
4
7
read-write
1X_CLOCK_PERIOD
1x input clock period
0
2X_CLOCK_PERIOD
2x input clock period
1
4X_CLOCK_PERIOD
4x input clock period
2
16X_CLOCK_PERIOD
16x input clock period
3
32X_CLOCK_PERIOD
32x input clock period
4
NONE1
none1
5
64X_CLOCK_PERIOD
64x input clock period
6
NONE2
none2
7
RESERVED1
reserved1
3
4
read-write
RESERVED2
reserved2
7
8
read-write
RESERVED3
reserved3
12
32
read-write
TMR_OPEARATING_MODE_CH2
Base timer operating mode for channel2
0
3
read-write
FREE_RUNNING_MODE
free running mode
0
SINGLE_EVENT_MODE
single event mode
1
DOWN_COUNT_MODE
down count mode
2
NONE1
none1
3
UP_DOWN_MODE
up/down mode
4
UP_DOWN_DOUBLER_MODE
up/down mode with interrupts for double PWM updates
5
NONE2
none2
6
NONE3
none3
7
PWM_TIME_PRD_PARAM_REG_CH3
Base time period config parameter's register for channel3
0x138
32
read-write
n
0x0
0x0
PWM_TIME_PRD_POST_SCALAR_VALUE_CH3
Time base output post scale bits for channel3
8
12
read-write
1:1_POST_SCALE
0000 1:1 post scale
0
1:2_POST_SCALE
0001 1:2
1
1:11_POST_SCALE
1010 1:11
10
1:12_POST_SCALE
1011 1:12
11
1:13_POST_SCALE
1100 1:13
12
1:14_POST_SCALE
1101 1:14
13
1:15_POST_SCALE
1110 1:15
14
1:16_POST_SCALE
1111 1:16
15
1:3_POST_SCALE
0010 1:3
2
1:4_POST_SCALE
0011 1:4
3
1:5_POST_SCALE
0100 1:5
4
1:6_POST_SCALE
0101 1:6
5
1:7_POST_SCALE
0110 1:7
6
1:8_POST_SCALE
0111 1:8
7
1:9_POST_SCALE
1000 1:9
8
1:10_POST_SCALE
1001 1:10
9
PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3
Base timer input clock pre scale select value for channel2.
4
7
read-write
1X_CLOCK_PERIOD
1x input clock period
0
2X_CLOCK_PERIOD
2x input clock period
1
4X_CLOCK_PERIOD
4x input clock period
2
16X_CLOCK_PERIOD
16x input clock period
3
32X_CLOCK_PERIOD
32x input clock period
4
NONE1
none
5
64X_CLOCK_PERIOD
64x input clock period
6
NONE2
none2
7
RESERVED1
reserved1
3
4
read-write
RESERVED2
reserved2
7
8
read-write
RESERVED3
reserved3
12
32
read-write
TMR_OPEARATING_MODE_CH3
Base timer operating mode for channel3
0
3
read-write
FREE_RUNNING_MODE
free running mode
0
SINGLE_EVENT_MODE
single event mode
1
DOWN_COUNT_MODE
down count mode
2
NONE1
none
3
UP_DOWN_MODE
up/down mode
4
DOUBLE_PWM_UPDATES
up/down mode with interrupts for double PWM updates
5
NONE2
none2
6
NONE3
none3
7
PWM_TIME_PRD_STS_REG_CH0
Base time period status register for channel0
0x38
32
read-only
n
0x0
0x0
PWM_TIME_PRD_DIR_STS_CH0
Time period counter direction status for channel0
0
1
read-only
Downward
Time period counter direction is downward
0
Upward
Time period counter direction is upward
1
RESERVED1
reserved1
1
32
read-only
PWM_TIME_PRD_STS_REG_CH1
Base time period status register for channel1
0x110
32
read-only
n
0x0
0x0
PWM_TIME_PRD_DIR_STS_CH1
Time period counter direction status for channel1.
0
1
read-only
Downward
downward
0
Upward
upward
1
RESERVED1
reserved1
1
32
read-only
PWM_TIME_PRD_STS_REG_CH2
Base time period status register for channel2
0x128
32
read-only
n
0x0
0x0
PWM_TIME_PRD_DIR_STS_CH2
Time period counter direction status for channel2.
0
1
read-only
Downward
downward
0
Upward
upward
1
RESERVED1
reserved1
1
32
read-only
PWM_TIME_PRD_STS_REG_CH3
Base time period status register for channel3
0x140
32
read-only
n
0x0
0x0
PWM_TIME_PRD_DIR_STS_CH3
Time period counter direction status for channel3.
0
1
read-only
downward
downward
0
upward
upward
1
RESERVED1
reserved1
1
16
read-only
RESERVED2
reserved2
16
32
read-only
PWM_TIME_PRD_WR_REG_CH0
Base timer period register of channel 0
0x28
32
read-write
n
0x0
0x0
PWM_TIME_PRD_REG_WR_VALUE_CH0
Value to update the base timer period register of channel 0
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_WR_REG_CH1
Base timer period register of channel1
0x100
32
read-write
n
0x0
0x0
PWM_TIME_PRD_REG_WR_VALUE_CH1
Value to update the base timer period register of channel 1
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_WR_REG_CH2
Base timer period register of channel2
0x118
32
read-write
n
0x0
0x0
PWM_TIME_PRD_REG_WR_VALUE_CH2
Value to update the base timer period register of channel 2
0
16
read-write
RESERVED1
reserved1
16
32
read-write
PWM_TIME_PRD_WR_REG_CH3
Base timer period register of channel3
0x130
32
read-write
n
0x0
0x0
PWM_TIME_PRD_REG_WR_VALUE_CH3
To update the base time counter initial value for channel 3
0
16
read-write
RESERVED1
reserved1
16
32
read-write
MCUHP_CLOCK
MCU HP (High Performance) domain contains the Cortex-M4F Processor, FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and MCU/SZP shareable Interfaces
MCUHP_CLOCK
0x0
0x0
0x5C
registers
n
MCUHP_CLOCK
69
MCUHP_CLKEN_CLEAR_REG1
Clock Enable Clear Register 1
0x4
32
read-write
n
0x0
MCUHP_CCI_AHB_CLK_EN
Writing 1 to this disables clock to CCI AHB Interface.Writing 0 to this has no effect.
25
26
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this disables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CRC_CLK_EN
Writing 1 to this disables clock to CRC Accelerator.Writing 0 to this has no effect.
18
19
read-write
MCUHP_CT_CLK_EN
Writing 1 to this disables clock to Configurable Timers.Writing 0 to this has no effect.
9
10
read-write
MCUHP_DMA_CLK_EN
Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
13
14
read-write
MCUHP_DMA_CLK_EN
Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
13
14
read-write
MCUHP_DMA_CLK_EN
Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
13
14
read-write
MCUHP_DMA_CLK_EN
Writing 1 to this disables clock to DMA.Writing 0 to this has no effect
13
14
read-write
MCUHP_ETH_AHB_CLK_EN
Writing 1 to this disables clock to Ethernet Controller AHB Interface.Writing 0 to this has no effect.
21
22
read-write
MCUHP_RNG_CLK_EN
Writing 1 to this disables clock to Random-Number-Generator.Writing 0 to this has no effect.
22
23
read-write
MCUHP_SDMEM_CLK_EN
Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
29
30
read-write
MCUHP_SDMEM_CLK_EN
Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
29
30
read-write
MCUHP_SDMEM_CLK_EN
Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
29
30
read-write
MCUHP_SDMEM_CLK_EN
Writing 1 to this disables clock to SD-MEM Controller.Writing 0 to this has no effect
29
30
read-write
MCUHP_UART1_APB_CLK_EN
Writing 1 to this disables clock to UART1 APB Interface.Writing 0 to this has no effect.
0
1
read-write
MCUHP_UART1_CLK_EN
Writing 1 to this disables clock to UART1 Controller.Writing 0 to this has no effect.
1
2
read-write
MCUHP_UART2_APB_CLK_EN
Writing 1 to this disables clock to UART2 APB Interface.Writing 0 to this has no effect.
2
3
read-write
MCUHP_UART2_CLK_EN
Writing 1 to this disables clock to UART2 Controller.Writing 0 to this has no effect.
3
4
read-write
MCUHP_ULP_CLK_EN
Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
31
32
read-write
MCUHP_ULP_CLK_EN
Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
31
32
read-write
MCUHP_ULP_CLK_EN
Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
31
32
read-write
MCUHP_ULP_CLK_EN
Writing 1 to this disables clock to MCU-ULPDomain.Writing 0 to this has no effect.
31
32
read-write
RESERVED1
It is recommended to write these bits to 0.
4
9
read-write
RESERVED2
It is recommended to write these bits to 0.
10
13
read-write
RESERVED3
It is recommended to write these bits to 0.
14
18
read-write
RESERVED4
It is recommended to write these bits to 0.
19
21
read-write
RESERVED5
It is recommended to write these bits to 0.
23
25
read-write
RESERVED6
It is recommended to write these bits to 0.
27
29
read-write
RESERVED6
It is recommended to write these bits to 0.
27
29
read-write
RESERVED6
It is recommended to write these bits to 0.
27
29
read-write
RESERVED6
It is recommended to write these bits to 0.
27
29
read-write
RESERVED7
It is recommended to write these bits to 0.
30
31
read-write
RESERVED7
It is recommended to write these bits to 0.
30
31
read-write
RESERVED7
It is recommended to write these bits to 0.
30
31
read-write
RESERVED7
It is recommended to write these bits to 0.
30
31
read-write
MCUHP_CLKEN_CLEAR_REG2
Clock Enable Clear Register 2
0xC
32
read-write
n
0x0
MCUHP_CAN_CLK_EN
Writing 1 to this disables clock to CAN Controller.Writing 0 to this has no effect.
3
4
read-write
MCUHP_ETH_CLK_EN
Writing 1 to this disables clock to Ethernet Controller.Writing 0 to this has no effect.
28
29
read-write
MCUHP_GSPI_APB_CLK_EN
Writing 1 to this disables clock to Generic-SPI Master APB Interface.Writing 0 to this has no effect.
0
1
read-write
MCUHP_I2C2_APB_CLK_EN
Writing 1 to this disables clock to I2C-2 APB Interface.Writing 0 to this has no effect.
8
9
read-write
MCUHP_I2C_APB_CLK_EN
Writing 1 to this disables clock to I2C-1 APB Interface.Writing 0 to this has no effect.
7
8
read-write
MCUHP_I2S_APB_CLK_EN
Writing 1 to this disables clock to I2S APB Interface.Writing 0 to this has no effect.
15
16
read-write
MCUHP_I2S_CLK_EN
Writing 1 to this disables clock to I2S Controller in Master Mode.Writing 0 to this has no effect.
13
14
read-write
MCUHP_I2S_INTF_CLK_EN
Writing 1 to this disables clock to I2S Interface.Writing 0 to this has no effect.
14
15
read-write
MCUHP_MCPWM_CLK_EN
Writing 1 to this disables clock to Motor-Control PWM.Writing 0 to this has no effect.
18
19
read-write
MCUHP_QE_CLK_EN
Writing 1 to this disables clock to Quadrature Encoder.Writing 0 to this has no effect.
17
18
read-write
MCUHP_QSPI_AHB_CLK_EN
Writing 1 to this disables clock to AHB Interface for SPI Flash Controller.Writing 0 to this has no effect.
12
13
read-write
MCUHP_QSPI_CLK_DIV_EN
Writing 1 to this disables clock to Clock dividers for SPI Flash Controller.Writing 0 to this has no effect.
11
12
read-write
MCUHP_SSI_APB_CLK_EN
Writing 1 to this disables clock to SPI/SSI Master APB Interface.Writing 0 to this has no effect.
23
24
read-write
MCUHP_SSI_CLK_EN
Writing 1 to this disables clock to SPI/SSI Master Controller.Writing 0 to this has no effect.
24
25
read-write
MCUHP_SSI_SLV_APB_CLK_EN
Writing 1 to this disables clock to SSI Slave APB Interface.Writing 0 to this has no effect.
9
10
read-write
MCUHP_SSI_SLV_CLK_EN
Writing 1 to this disables clock to SSI Slave Controller.Writing 0 to this has no effect.
10
11
read-write
MCUHP_UDMA_CLK_EN
Writing 1 to this disables clock to Micro-DMA.Writing 0 to this has no effect.
6
7
read-write
RESERVED1
It is recommended to write these bits to 0.
1
3
read-write
RESERVED2
It is recommended to write these bits to 0.
4
6
read-write
RESERVED3
It is recommended to write these bits to 0.
16
17
read-write
RESERVED4
It is recommended to write these bits to 0.
19
23
read-write
RESERVED5
It is recommended to write these bits to 0.
25
28
read-write
RESERVED6
It is recommended to write these bits to 0.
29
32
read-write
MCUHP_CLKEN_CLEAR_REG3
Clock Enable Clear Register 3
0x14
32
read-write
n
0x0
MCUHP_EFUSE_CLK_EN
Writing 1 to this disables clock to eFUSE Controller.Writing 0 to this has no effect.
5
6
read-write
MCUHP_EGPIO_CLK_EN
Writing 1 to this disables clock to Enhanced-GPIO Controller.Writing 0 to this has no effect.
16
17
read-write
MCUHP_I2C2_CLK_EN
Writing 1 to this disables clock to I2C-2 Controller.Writing 0 to this has no effect.
18
19
read-write
MCUHP_I2C_CLK_EN
Writing 1 to this disables clock to I2C-1 Controller.Writing 0 to this has no effect.
17
18
read-write
MCUHP_ICACHE_CLK_EN
Writing 1 to this disables clock to Generic-SPI Master.Writing 0 to this has no effect.
27
28
read-write
MCUHP_PERI_CLK_EN
Writing 1 to this disables clock source to Peripherals.Writing 0 to this has no effect.
26
27
read-write
MCUHP_QSPI_CLK_EN
Writing 1 to this disables clock to SPI Flash Controller.Writing 0 to this has no effect.
13
14
read-write
MCUHP_QSPI_CLK_SYNC_EN
Writing 1 to this disables SPI Flash Controller clock in synchronous with Processor Clock. Writing 0 to this has no effect.
14
15
read-write
MCUHP_SIO_CLK_EN
Writing 1 to this disables clock to SIO Controller.Writing 0 to this has no effect.
20
21
read-write
RESERVED1
It is recommended to write these bits to 0.
0
5
read-write
RESERVED2
It is recommended to write these bits to 0.
6
13
read-write
RESERVED3
It is recommended to write these bits to 0.
15
16
read-write
RESERVED4
It is recommended to write these bits to 0.
19
20
read-write
RESERVED5
It is recommended to write these bits to 0.
21
26
read-write
RESERVED6
It is recommended to write these bits to 0.
28
32
read-write
MCUHP_CLKEN_SET_REG1
Clock Enable Set Register 1
0x0
32
read-write
n
0x0
MCUHP_CCI_AHB_CLK_EN
Writing 1 to this enables clock to CCI AHB Interface.Writing 0 to this has no effect.
25
26
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CCI_CLK_EN
Writing 1 to this enables clock to CCI Controller.Writing 0 to this has no effect.
26
27
read-write
MCUHP_CRC_CLK_EN
Writing 1 to this enables clock to CRC Accelerator.Writing 0 to this has no effect.
18
19
read-write
MCUHP_CT_CLK_EN
Writing 1 to this enables clock to Configurable Timers.Writing 0 to this has no effect.
9
10
read-write
MCUHP_DMA_CLK_EN
Writing 1 to this disables clock to DMA.Writing 0 to this has no effect.
13
14
read-write
MCUHP_ETH_AHB_CLK_EN
Writing 1 to this enables clock to Ethernet Controller AHB Interface.Writing 0 to this has no effect.
21
22
read-write
MCUHP_RNG_CLK_EN
Writing 1 to this enables clock to Random-Number-Generator
22
23
read-write
MCUHP_SDMEM_CLK_EN
Writing 1 to this enables clock to SD-MEM Controller.Writing 0 to this has no effect.
29
30
read-write
MCUHP_UART1_APB_CLK_EN
Writing 1 to this enables clock to UART1 APB Interface.Writing 0 to this has no effect.
0
1
read-write
MCUHP_UART1_CLK_EN
Writing 1 to this enables clock to UART1 Controller.Writing 0 to this has no effect.
1
2
read-write
MCUHP_UART2_APB_CLK_EN
Writing 1 to this enables clock to UART2 APB Interface.Writing 0 to this has no effect.
2
3
read-write
MCUHP_UART2_CLK_EN
Writing 1 to this enables clock to UART2 Controller.Writing 0 to this has no effect.
3
4
read-write
MCUHP_ULP_CLK_EN
Writing 1 to this enables clock to MCU-ULPDomain.Writing 0 to this has no effect.
31
32
read-write
RESERVED1
It is recommended to write these bits to 0.
4
9
read-write
RESERVED2
It is recommended to write these bits to 0.
10
13
read-write
RESERVED3
It is recommended to write these bits to 0.
14
18
read-write
RESERVED4
It is recommended to write these bits to 0.
19
21
read-write
RESERVED5
It is recommended to write these bits to 0.
23
25
read-write
RESERVED6
It is recommended to write these bits to 0.
27
29
read-write
RESERVED7
It is recommended to write these bits to 0.
30
31
read-write
MCUHP_CLKEN_SET_REG2
Clock Enable Set Register 2
0x8
32
read-write
n
0x0
MCUHP_CAN_CLK_EN
Writing 1 to this enables clock to CAN Controller.Writing 0 to this has no effect.
3
4
read-write
MCUHP_ETH_CLK_EN
Writing 1 to this enables clock to Ethernet Controller.Writing 0 to this has no effect.
28
29
read-write
MCUHP_GSPI_APB_CLK_EN
Writing 1 to this enables clock to Generic-SPI Master APB Interface.Writing 0 to this has no effect.
0
1
read-write
MCUHP_I2C2_APB_CLK_EN
Writing 1 to this enables clock to I2C-2 APB Interface.Writing 0 to this has no effect.
8
9
read-write
MCUHP_I2C_APB_CLK_EN
Writing 1 to this enables clock to I2C-1 APB Interface.Writing 0 to this has no effect.
7
8
read-write
MCUHP_I2S_APB_CLK_EN
Writing 1 to this enables clock to I2S APB Interface.Writing 0 to this has no effect.
15
16
read-write
MCUHP_I2S_CLK_EN
Writing 1 to this enables clock to I2S Controller in Master Mode.Writing 0 to this has no effect.
13
14
read-write
MCUHP_I2S_INTF_CLK_EN
Writing 1 to this enables clock to I2S Interface.Writing 0 to this has no effect.
14
15
read-write
MCUHP_MCPWM_CLK_EN
Writing 1 to this enables clock to Motor-Control PWM.Writing 0 to this has no effect.
18
19
read-write
MCUHP_QE_CLK_EN
Writing 1 to this enables clock to Quadrature Encoder.Writing 0 to this has no effect.
17
18
read-write
MCUHP_QSPI_AHB_CLK_EN
Writing 1 to this enables clock to AHB Interface for SPI Flash Controller.Writing 0 to this has no effect..
12
13
read-write
MCUHP_QSPI_CLK_DIV_EN
Writing 1 to this enables clock to Clock dividers for SPI Flash Controller.Writing 0 to this has no effect.
11
12
read-write
MCUHP_SSI_APB_CLK_EN
Writing 1 to this enables clock to SPI/SSI Master APN Interface.Writing 0 to this has no effect.
23
24
read-write
MCUHP_SSI_CLK_EN
Writing 1 to this enables clock to SPI/SSI Master Controller.Writing 0 to this has no effect.
24
25
read-write
MCUHP_SSI_SLV_APB_CLK_EN
Writing 1 to this enables clock to SSI Slave APB Interface.Writing 0 to this has no effect.
9
10
read-write
MCUHP_SSI_SLV_CLK_EN
Writing 1 to this enables clock to SSI Slave Controller.Writing 0 to this has no effect.
10
11
read-write
MCUHP_UDMA_CLK_EN
Writing 1 to this enables clock to Micro-DMA.Writing 0 to this has no effect.
6
7
read-write
RESERVED1
It is recommended to write these bits to 0
1
3
read-write
RESERVED2
It is recommended to write these bits to 0.
4
6
read-write
RESERVED3
It is recommended to write these bits to 0.
16
17
read-write
RESERVED4
It is recommended to write these bits to 0.
19
23
read-write
RESERVED5
It is recommended to write these bits to 0.
25
28
read-write
RESERVED6
It is recommended to write these bits to 0.
29
32
read-write
MCUHP_CLKEN_SET_REG3
Clock Enable Set Register 3
0x10
32
read-write
n
0x0
MCUHP_EFUSE_CLK_EN
Writing 1 to this enables clock to eFUSE Controller.Writing 0 to this has no effect.
5
6
read-write
MCUHP_EGPIO_CLK_EN
Writing 1 to this enables clock to Enhanced-GPIO Controller.Writing 0 to this has no effect.
16
17
read-write
MCUHP_I2C2_CLK_EN
Writing 1 to this enables clock to I2C-2 Controller.Writing 0 to this has no effect.
18
19
read-write
MCUHP_I2C_CLK_EN
Writing 1 to this enables clock to I2C-1 Controller.Writing 0 to this has no effect.
17
18
read-write
MCUHP_ICACHE_CLK_EN
Writing 1 to this enables clock to Generic-SPI Master.Writing 0 to this has no effect.
27
28
read-write
MCUHP_PERI_CLK_EN
Writing 1 to this enables clock source to Peripherals.Writing 0 to this has no effect.
26
27
read-write
MCUHP_QSPI_CLK_EN
Writing 1 to this enables clock to SPI Flash Controller.Writing 0 to this has no effect.
13
14
read-write
MCUHP_QSPI_CLK_SYNC_EN
Writing 1 to this enables SPI Flash Controller clock in synchronous with Processor Clock.Writing 0 to this has no effect.
14
15
read-write
MCUHP_SIO_CLK_EN
Writing 1 to this enables clock to SIO Controller.Writing 0 to this has no effect.
20
21
read-write
RESERVED1
It is recommended to write these bits to 0.
0
5
read-write
RESERVED2
It is recommended to write these bits to 0.
6
13
read-write
RESERVED3
It is recommended to write these bits to 0.
15
16
read-write
RESERVED4
It is recommended to write these bits to 0.
19
20
read-write
RESERVED5
It is recommended to write these bits to 0.
21
26
read-write
RESERVED6
It is recommended to write these bits to 0.
28
32
read-write
MCUHP_CLK_CONFIG_REG1
Clock Configuration Register 1
0x18
32
read-write
n
0x0
MCUHP_ETH_CLK_DIV_FAC
Specifies the clock division factor for Ethernet RMII Controller.
19
23
read-write
MCUHP_ETH_CLK_DIV_SEL
Selects the Divider type for Ethernet Controller.
23
24
read-write
0
EVEN Clock Divider output is selected
0
1
Clock Divider output is selected
1
MCUHP_ETH_CLK_SEL
Specifies the clock source for Ethernet RMII Controller.
18
19
read-write
0
Interface-PLL Clock
0
1
SoC-PLL Clock
1
MCUHP_GSPI_CLK_SEL
Specifies the clock source for GSPI Controller.
24
27
read-write
000
RESERVED1
0
001
MCU-HP Reference Clock
1
010
SoC-PLL Clock
2
011
RESERVED2
3
100
Interface-PLL Clock
4
101
Output Clock is gated
5
110
Output Clock is gated
6
111
Output Clock is gated
7
MCUHP_QSPI_CLK_DIV_FAC
Specifies the clock division factor for SPI Flash Controller.
3
9
read-write
MCUHP_QSPI_CLK_SEL
Specifies the clock source for SPI Flash controller when independent clock source.
0
3
read-write
000
MCU-HP Reference Clock
0
001
Interface-PLL Clock
1
010
RESERVED1
2
011
SoC-PLL Clock
3
100
Output Clock is gated
4
101
Output Clock is gated
5
110
Output Clock is gated
6
111
Output Clock is gated
7
MCUHP_SSI_CLK_DIV_FAC
Specifies the clock division factor for for SPI/SSI Master.
11
15
read-write
MCUHP_SSI_CLK_SEL
Specifies the clock source for SPI/SSI Master.
15
18
read-write
000
MCU-HP Reference Clock
0
001
SoC-PLL Clock
1
010
RESERVED1
2
011
Interface-PLL Clock
3
100
RESERVED2
4
101
RESERVED3
5
110
Output Clock is gated
6
111
Output Clock is gated
7
RESERVED1
It is recommended to write these bits to 0.
9
11
read-write
RESERVED2
It is recommended to write these bits to 0.
27
32
read-write
MCUHP_CLK_CONFIG_REG2
Clock Configuration Register 2
0x1C
32
read-write
n
0x0
MCUHP_CCI_CLK_DIV_FAC
Specifies the clock division factor for CCI Controller.
24
28
read-write
MCUHP_QSPI_CLK_ODD_SEL
Selects the Divider type for SPI Flash Controller when independent clock source w.r.t Processor is selected.
28
29
read-write
0
EVEN Clock Divider output is selected
0
1
ODD Clock Divider output is selected
1
MCUHP_UART1_CLK_DIV_FAC
Specifies the clock division factor for UART1 Controller.
3
7
read-write
MCUHP_UART1_CLK_SEL
Specifies the clock source to be used for UART1 Controller.
0
3
read-write
000
MCU-HP Reference Clock
0
001
SoC-PLL Clock
1
010
RESERVED1
2
011
RESERVED2
3
100
Interface-PLL Clock
4
101
Output Clock is gated
5
110
Output Clock is gated
6
111
Output Clock is gated
7
MCUHP_UART1_FRAC_CLK_SEL
Selects the Divider type for UART1 Controller. 0 - Clock Swallow output is selected 1 - Fractional Clock Divider output is selected
29
30
read-write
0
Clock Swallow output is selected
0
1
Fractional Clock Divider output is selected
1
MCUHP_UART2_CLK_DIV_FAC
Specifies the clock division factor for UART2 Controller.
10
14
read-write
MCUHP_UART2_CLK_SEL
Specifies the clock source to be used for UART2 Controller.
7
10
read-write
000
MCU-HP Reference Clock
0
001
SoC-PLL Clock
1
010
RESERVED1
2
011
Interface-PLL Clock
3
100
RESERVED2
4
101
Output Clock is gated
5
110
Output Clock is gated
6
111
Output Clock is gated
7
MCUHP_UART2_FRAC_CLK_SEL
Selects the Divider type for UART2 Controller. 0 - Clock Swallow output is selected 1 - Fractional Clock Divider output is selected
30
31
read-write
0
Clock Swallow output is selected
0
1
Fractional Clock Divider output is selected
1
RESERVED1
It is recommended to write these bits to 0.
14
24
read-write
RESERVED2
It is recommended to write these bits to 0.
31
32
read-write
MCUHP_CLK_CONFIG_REG3
Clock Configuration Register 3
0x20
32
read-write
n
0x0
MCUHP_CAN_CLK_DIV_FAC
Specifies the clock division factor for CAN Controller.
0
8
read-write
MCUHP_EXT_CLK_DIV_FAC
Specifies the clock division factor for External Clock.
12
18
read-write
MCUHP_EXT_CLK_EN
Writing 1 to this enables the External clock on GPIO PAD.Writing 0 to this disables the External clock on GPIO PAD.
18
19
read-write
MCUHP_EXT_CLK_SEL
Specifies the clock source to be used for External Clock.
8
12
read-write
0000
Output Clock is Gated
0
0001
High Freq RC Clock source
1
1010
Interface-PLL Clock
10
1011
RESERVED3
11
1100
RESERVED4
12
1101
SoC-PLL Clock
13
1110
I2S-PLL Clock
14
1111
RESERVED5
15
0010
XTAL Clock source.
2
0011
RESERVED1
3
0100
High Freq RO Clock source
4
0101
Doubler Clock
5
0110
RESERVED2
6
0111
Low Freq RC Clock source
7
1000
Low Freq XTAL Clock source
8
1001
Low Freq RO Clock source
9
RESERVED1
It is recommended to write these bits to 0.
19
32
read-write
MCUHP_CLK_CONFIG_REG5
Clock Configuration Register 5
0x28
32
read-write
n
0x0
MCUHP_CT_CLK_DIV_FAC
Specifies the clock division factor for Configurable Timers.
20
26
read-write
MCUHP_CT_CLK_SEL
Specifies the clock source to be used for Configurable Timers.
17
20
read-write
000
MCU-HP Reference Clock
0
001
Interface-PLL Clock
1
010
SoC-PLL Clock
2
011
RESERVED1
3
100
Output Clock is gated
4
101
Output Clock is gated
5
110
Output Clock is gated
6
111
Output Clock is gated
7
MCUHP_I2S_CLK_DIV_FAC
Specifies the clock division factor for I2S Controller in Master Mode.
11
17
read-write
MCUHP_I2S_CLK_SEL
Specifies the clock source to be used for I2S Controller in Master Mode.
10
11
read-write
0
I2S-PLL Clock
0
1
RESERVED1
1
MCUHP_PROC_CLK_DIV_FAC
Specifies the clock division factor for Processor Clock.
4
10
read-write
MCUHP_PROC_CLK_SEL
Specifies the clock source to be used for Processor.
0
4
read-write
0000
MCU-HP Reference Clock
0
0001
RESERVED1
1
0010
SoC-PLL Clock
2
0011
RESERVED2
3
0100
Interface-PLL Clock
4
0101
Low-Power Clock
5
0110
RESERVED3
6
0111
RESERVED4
7
MCUHP_ULP_CLK_SEL
Specifies the divider type to be selected to MCU ULP Domain source.
28
29
read-write
0
Clock Divider output is selected
0
1
Odd Clock Divider output is selected
1
RESERVED1
It is recommended to write these bits to 0.
26
28
read-write
RESERVED2
It is recommended to retain the contents by using read/modify write to this register.
29
32
read-write
MCUHP_CLK_STATUS_REG
Clock Status Register for Dynamic Clock Muxes
0x58
32
read-write
n
0x0
MCUHP_CCI_CLK_SWITCHED
Status of Dynamic Clock Mux in CCI Clock Generation
23
24
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_CT_CLK_SWITCHED
Status of Dynamic Clock Mux in Configurable Timer Clock Generation
15
16
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_ETH_CLK_SWITCHED
Status of Dynamic Clock Mux in Ethernet RMII Clock Generation
18
19
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_EXT_CLK_SWITCHED
Status of Dynamic Clock Mux in External Clock Generation
22
23
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_GSPI_CLK_SWITCHED
Status of Dynamic Clock Mux in Generic SPI Master Clock Generation
12
13
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_I2S_CLK_SWITCHED
Status of Dynamic Clock Mux in I2S Clock Generation
17
18
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_LP_CLK_SWITCHED
Status of Dynamic Clock Mux in Low-Power Clock Generation
21
22
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_PROC_CLK_SWITCHED
Status of Dynamic Clock Mux in Processor Clock Generation
8
9
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_QSPI_CLK_SWITCHED
Status of Dynamic Clock Mux in SPI Flash Controller Clock Generation
9
10
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_REF_CLK_SWITCHED
Status of Dynamic Clock Mux in Reference Clock Generation
31
32
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_SDMEM_CLK_SWITCHED
Status of Dynamic Clock Mux in SD-MEM(eMMC) Clock Generation
14
15
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_SSI_CLK_SWITCHED
Status of Dynamic Clock Mux in SPI/SSI Master Clock Generation
13
14
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_UART1_CLK_SWITCHED
Status of Dynamic Clock Mux in UART1 Clock Generation
10
11
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUHP_UART2_CLK_SWITCHED
Status of Dynamic Clock Mux in UART2 Clock Generation
11
12
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
RESERVED1
It is recommended to write these bits to 0.
0
8
read-write
RESERVED2
It is recommended to write these bits to 0.
16
17
read-write
RESERVED3
It is recommended to write these bits to 0.
19
21
read-write
RESERVED4
It is recommended to write these bits to 0.
24
31
read-only
MCUHP_SDMEM_CLK_CONFIG
SDMEM Clock Configuration Register
0x40
32
read-write
n
0x0
MCUHP_SDMEM_CLK_DIV_FAC
Specifies the clock division factor for SDMEM Controller.
0
6
read-write
MCUHP_SDMEM_CLK_DIV_SEL
Specifies the divider type to be selected to SDMEM Controller
9
10
read-write
0
EVEN Clock Divider output is selected
0
1
Clock Divider output is selected
1
MCUHP_SDMEM_CLK_SEL
Specifies the clock source to be used for SD-MEM(eMMC).
6
9
read-write
000
SoC-PLL Clock
0
010
Interface-PLL Clock
2
011
RESERVED1
3
100
Output clock is disabled
4
101
Output clock is disabled
5
110
Output clock is disabled
6
111
Output clock is disabled
7
RESERVED1
It is recommended to write these bits to 0.
10
32
read-write
MCU_GPIO_TIMESTAMP_READ
Clock Configuration Register 4
0x24
32
read-write
n
0x0
MCUHP_CCI_CLK_SEL
Specifies the clock source to be used for Low-Power Clock.
31
32
read-write
0
RESERVED1
0
1
Interface-PLL Clock
1
MCUHP_LP_CLK_SEL
Specifies the clock source to be used for Low-Power Clock.
21
23
read-write
000
Low Freq RC Clock source
0
001
Low Freq XTAL Clock source
1
010
Output Clock is gated
2
011
Low Freq RO Clock source
3
MCUHP_ULP_DIV_FAC
Specifies the clock division factor for MCU ULP Domain source.
25
31
read-write
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
0
21
read-write
RESERVED2
It is recommended to retain the contents by using read/modify write to this register.
23
25
read-write
MCUHP_MISC_CLOCK
MCU HP (High Performance) domain contains the Cortex-M4F Processor, FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and MCU/SZP shareable Interfaces
MCUHP_MISC_CLOCK
0x0
0x0
0x48
registers
n
MCUHP_MISC_CONFIG_1
Miscellaneous Clock Configuration Register1
0x14
32
read-write
n
0x0
MCUHP_CCI_CLK_SYNC_EN
Specifies the clock dependency w.r.t processor clock used for MCUHP CCI
16
17
read-write
0
Independent clock source
0
1
Undivided version of Processor Clock
1
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
0
16
read-write
RESERVED2
It is recommended to retain the contents by using read/modify write to this register.
17
32
read-write
MCUHP_MISC_CONFIG_3
Miscellaneous Clock Configuration Register1
0x44
32
read-write
n
0x0
MCUHP_I2S_MASTER_SLAVE_MODE
Writing 1 to this configures I2S controller to Master Mode.Writing 0 to this configures I2S controller to Slave Mode.
23
24
read-write
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
0
23
read-write
RESERVED2
It is recommended to retain the contents by using read/modify write to this register.
24
32
read-write
MCUULP_CLOCK
The MCU ULP (Ultra Low Power) domain contains the MCU ULP AHB Inter-Connect-Matrix, MCU ULP Peripherals and the direct AHB Interface with the Processor. This section describes the different clock sources possible for each peripheral and the AHB/APB Interfaces.
MCUULP_CLOCK
0x0
0x0
0xA8
registers
n
MCUULP_ADCDAC_CLK_CONFIG
MCU-ULP Aux-ADC/DAC Configuration Register
0x34
32
read-write
n
0x0
MCUULP_ADCDAC_CLK_SEL
Specifies the clock source to be used for Aux-ADC/DAC Controller
1
5
read-write
0000
MCU-ULP Reference Clock.
0
0001
ro_32khz_clk.
1
1010
RESERVED2
10
1011
RESERVED3
11
1100
RESERVED4
12
1101
RESERVED5
13
1110
RESERVED6
14
1111
Output clock is gated
15
0010
rc_32khz_clk.
2
0011
xtal_32khz_clk.
3
0100
rc_32mhz_clk.
4
0101
ro_hf_clk.
5
0110
MCU-HP ULP Clock.
6
0111
doubler_clk
7
1000
i2s_pll_clk
8
1001
RESERVED1
9
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
5
13
read-write
RESERVED3
It is recommended to write these bits to 0.
13
32
read-write
MCUULP_CLK_EN_REG1
MCU-ULP Clock Enable Register 1
0x0
32
read-write
n
0x0
MCUULP_EGPIO_CLK_EN
ULP EGPIO clock enable
14
15
read-write
Disable
Writing 0 to this disables clock to Enhanced-GPIO.
0
Enable
Writing 1 to this enables clock to Enhanced-GPIO.
1
MCUULP_FIM_CLK_EN
ULP FIM clock enable
16
17
read-write
Disable
Writing 0 to this disables clock to FIM Engine.
0
Enable
Writing 1 to this enables clock to FIM Engine.
1
MCUULP_I2C_APB_CLK_EN
ULP I2C APB clock enable
5
6
read-write
Disable
Writing 0 to this disables clock to I2C APB Interface.
0
Enable
Writing 1 to this enables clock to I2C APB Interface.
1
MCUULP_I2S_CLK_EN
ULP I2S clock enable
6
7
read-write
Disable
Writing 0 to this disables clock to I2S Controller.
0
Enable
Writing 1 to this enables clock to I2S Controller.
1
MCUULP_IR_CLK_EN
ULP IR receiver clock enable
4
5
read-write
Disable
Writing 0 to this disables clock to IR Receiver.
0
Enable
Writing 1 to this enables clock to IR Receiver.
1
MCUULP_SSI_APB_CLK_EN
ULP SSI APB clock enable
7
8
read-write
Disable
Writing 0 to this disables clock to SPI/SSI Master APB Interface.
0
Enable
Writing 1 to this enables clock to SPI/SSI Master APB Interface.
1
MCUULP_SSI_CLK_EN
ULP SSI clock enable
8
9
read-write
Disable
Writing 0 to this disables clock to SPI/SSI Master.
0
Enable
Writing 1 to this enables clock to SPI/SSI Master.
1
MCUULP_TOUCH_APB_CLK_EN
ULP VAD clock enable
31
32
read-write
Disable
Writing 0 to this disables clock to Touch Sensor APB Interface.
0
Enable
Writing 1 to this enables clock to Touch Sensor APB Interface.
1
MCUULP_UART_APB_CLK_EN
ULP UART APB clock enable
9
10
read-write
Disable
Writing 0 to this disables clock to UART APB Interface.
0
Enable
Writing 1 to this enables clock to UART APB Interface.
1
MCUULP_UART_CLK_EN
ULP UART clock enable
10
11
read-write
Disable
Writing 0 to this disables clock to UART Controller.
0
Enable
Writing 1 to this enables clock to UART Controller.
1
MCUULP_VAD_CLK_EN
ULP VAD clock enable
17
18
read-write
Disable
Writing 0 to this disables clock to VAD Controller.
0
Enable
Writing 1 to this enables clock to VAD Controller.
1
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
0
4
read-write
RESERVED2
It is recommended to write these bits to 0.
11
14
read-write
RESERVED3
It is recommended to write these bits to 0.
15
16
read-write
RESERVED4
It is recommended to retain the contents by using read/modify write to this register.
18
31
read-write
MCUULP_CLK_EN_REG2
MCU-ULP Clock Enable Register 2
0xA0
32
read-write
n
0x0
MCUULP_ADCDAC_CLK_EN
ULP ADC and DAC clock enable
12
13
read-write
0
Writing 0 to this disables clock to Aux-ADC/DAC Controller.
0
1
Writing 1 to this enables clock to Aux-ADC/DAC Controller.
1
MCUULP_UDMA_CLK_EN
ULP UDMA clock enable
17
18
read-write
0
Writing 0 to this disables clock to Aux-ADC/DAC Controller.
0
1
Writing 1 to this enables clock to Aux-ADC/DAC Controller.
1
RESERVED1
It is recommended to write these bits to 0.
0
12
read-write
RESERVED2
It is recommended to write these bits to 0.
13
17
read-write
RESERVED3
It is recommended to write these bits to 0.
18
32
read-write
MCUULP_CLK_STATUS_REG
MCU-ULP Clock Status Register
0x28
32
read-only
n
0x0
MCUHP_UART_CLK_SWITCHED
Status of Dynamic Clock Mux in UART Clock Generation.
0
1
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_ADCDAC_CLK_SWITCHED
Status of Dynamic Clock Mux in Aux-ADC/DAC Clock Generation
7
8
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_I2S_CLK_SWITCHED
Status of Dynamic Clock Mux in I2S Controller Clock Generation.
1
2
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_PROC_CLK_SWITCHED
Status of Dynamic Clock Mux in AHB Interface Clock Generation.
3
4
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_SSI_CLK_SWITCHED
Status of Dynamic Clock Mux in SPI/SSI Master Clock Generation.
5
6
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_TIMER_CLK_SWITCHED
Status of Dynamic Clock Mux in Timer Clock Generation.
8
9
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_TOUCH_CLK_SWITCHED
Status of Dynamic Clock Mux in Touch Sensor Clock Generation.
9
10
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_VAD_CLK_SWITCHED
Status of Dynamic Clock Mux in VAD Clock Generation.
6
7
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_VAD_FCLK_SWITCHED
Status of Dynamic Clock Mux in VAD Fast Clock Generation.
10
11
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
MCUULP_VAD_SCLK_SWITCHED
Status of Dynamic Clock Mux in VAD Slow Clock Generation
11
12
read-only
0
Clock switching is in progress
0
1
Clock got switched and output clock can be used
1
RESERVED1
It is recommended to write these bits to 0.
2
3
read-only
RESERVED2
It is recommended to write these bits to 0.
4
5
read-only
RESERVED3
It is recommended to write these bits to 0.
12
32
read-only
MCUULP_I2C_SSI_CLK_CONFIG
MCU-ULP SSI Master and I2C Clock Configuration Register
0x18
32
read-write
n
0x0
MCUULP_I2C_CLK_EN
ULP I2C clock enables
0
1
read-write
Disable
Writing 0 to this disables clock to I2C Controller.
0
Enable
Writing 1 to this enables clock to I2C Controller.
1
MCUULP_SSI_CLK_DIV_EN
ULP SSI clock division enables
16
17
read-write
Disable
Writing 0 to this disables clock to SPI/SSI Master Clock Dividers.
0
Enable
Writing 1 to this enables clock to SPI/SSI Master Clock Dividers.
1
MCUULP_SSI_CLK_DIV_FAC
Specifies the clock division factor for SPI/SSI Master Clock.
17
24
read-write
MCUULP_SSI_CLK_SEL
ULP SSI clock select
28
32
read-write
0000
MCU-ULP Reference Clock
0
0001
ro_32khz_clk
1
1010
RESERVED4
10
1011
RESERVED5
11
1100
RESERVED6
12
1101
RESERVED7
13
1110
RESERVED8
14
1111
Output clock is gated
15
0010
rc_32khz_clk
2
0011
xtal_32khz_clk
3
0100
rc_32mhz_clk
4
0101
ro_hf_clk
5
0110
MCU-HP ULP Clock
6
0111
RESERVED1
7
1000
RESERVED2
8
1001
RESERVED3
9
RESERVED1
It is recommended to write these bits to 0.
1
16
read-write
RESERVED2
It is recommended to write these bits to 0.
24
28
read-write
MCUULP_I2S_CLK_CONFIG
MCU-ULP I2S Clock Configuration Register
0x1C
32
read-write
n
0x0
MCUULP_I2S_APB_CLK_EN
I2S APB clock enable
18
19
read-write
Disable
Writing 0 to this disables clock to I2S APB Interface.
0
Enable
Writing 1 to this enables clock to I2S APB Interface.
1
MCUULP_I2S_CLK_DIV_EN
ULP I2S clock division enable
0
1
read-write
Disable
Writing 0 to this disables clock to I2S Clock Dividers.
0
Enable
Writing 1 to this enables clock to I2S Clock Dividers.
1
MCUULP_I2S_CLK_DIV_FAC
Specifies the clock division factor for I2S Master Clock.
5
13
read-write
MCUULP_I2S_CLK_SEL
Specifies the clock source to be used for I2S Master
1
5
read-write
0000
MCU-ULP Reference Clock
0
0001
ro_32khz_clk
1
1010
RESERVED2
10
1011
RESERVED3
11
1100
RESERVED4
12
1101
RESERVED5
13
1110
RESERVED6
14
1111
Output clock is gated
15
0010
rc_32khz_clk
2
0011
xtal_32khz_clk
3
0100
rc_32mhz_clk
4
0101
ro_hf_clk
5
0110
MCU-HP ULP Clock
6
0111
doubler_clk
7
1000
i2s_pll_clk
8
1001
RESERVED1
9
MCUULP_I2S_MASTER_SLAVE_MODE
Enable I2S master or slave mode
13
14
read-write
Slave
Writing 0 to this configures I2S to Slave Mode.
0
Master
Writing 1 to this configures I2S to Master Mode.
1
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
14
18
read-write
RESERVED2
It is recommended to write these bits to 0.
19
32
read-write
MCUULP_PROC_CLK_CONFIG
MCU-ULP AHB Clock Configuration Register
0x14
32
read-write
n
0x0
MCUULP_PROC_CLK_DIV_DAC
Specifies the clock division factor for AHB Interface Clock.
5
13
read-write
MCUULP_PROC_CLK_SEL
ULP Processor clock select
1
5
read-write
0000
MCU-ULP Reference Clock
0
0001
ro_32khz_clk
1
1010
Output clock is gated
10
1011
Output clock is gated
11
1100
Output clock is gated
12
1101
Output clock is gated
13
1110
Output clock is gated
14
1111
Output clock is gated
15
0010
rc_32khz_clk
2
0011
xtal_32khz_clk
3
0100
rc_32mhz_clk
4
0101
ro_hf_clk
5
0110
MCU-HP ULP Clock
6
0111
doubler_clk
7
1000
Output clock is gated
8
1001
Output clock is gated
9
RESERVED1
It is recommended to retain the contents by using read/modify write to this register.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
13
32
read-write
MCUULP_TIMER_CLK_CONFIG
MCU-ULP Timer Clock Configuration Register
0x30
32
read-write
n
0x0
MCUULP_TIMER_CLK_SEL
Specifies the clock source to be used for Timer.
1
5
read-write
0000
MCU-ULP Reference Clock.
0
0001
ro_32khz_clk.
1
1010
RESERVED4
10
1011
RESERVED5
11
1100
RESERVED6
12
1101
RESERVED7
13
1110
RESERVED8
14
1111
Output clock is gated
15
0010
rc_32khz_clk.
2
0011
xtal_32khz_clk.
3
0100
rc_32mhz_clk.
4
0101
ro_hf_clk.
5
0110
MCU-HP ULP Clock.
6
0111
RESERVED1
7
1000
RESERVED2
8
1001
RESERVED3
9
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
5
14
read-write
RESERVED3
It is recommended to write these bits to 0.
14
32
read-write
MCUULP_TOUCH_CLK_CONFIG
MCU-ULP Touch Sensor Clock Configuration Register
0x2C
32
read-write
n
0x0
MCUULP_TOUCH_CLK_SEL
Specifies the clock source to be used for Touch Sensor.
1
5
read-write
0000
MCU-ULP Reference Clock.
0
0001
ro_32khz_clk.
1
1010
RESERVED4
10
1011
RESERVED5
11
1100
RESERVED6
12
1101
RESERVED7
13
1110
RESERVED8
14
1111
Output clock is gated
15
0010
rc_32khz_clk.
2
0011
xtal_32khz_clk.
3
0100
rc_32mhz_clk.
4
0101
ro_hf_clk.
5
0110
MCU-HP ULP Clock.
6
0111
RESERVED1
7
1000
RESERVED2
8
1001
RESERVED3
9
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
5
13
read-write
RESERVED3
It is recommended to write these bits to 0.
13
32
read-write
MCUULP_UART_CLK_CONFIG
MCU-ULP UART Clock Configuration Register
0x20
32
read-write
n
0x0
MCUULP_UART_CLK_DIV_FAC
Specifies the clock division factor for UART.
5
13
read-write
MCUULP_UART_CLK_SEL
Specifies the clock source to be used for UART.
1
5
read-write
0000
MCU-ULP Reference Clock.
0
0001
ro_32khz_clk.
1
1010
RESERVED3
10
1011
RESERVED4
11
1100
RESERVED5
12
1101
RESERVED6
13
1110
RESERVED7
14
1111
Output clock is gated
15
0010
rc_32khz_clk.
2
0011
xtal_32khz_clk.
3
0100
rc_32mhz_clk.
4
0101
ro_hf_clk.
5
0110
MCU-HP ULP Clock.
6
0111
doubler_clk
7
1000
RESERVED1
8
1001
RESERVED2
9
MCUULP_UART_FRAC_CLK_SEL
Selects the Divider type for UART Controller.
0
1
read-write
0
Clock Swallow output is selected.
0
1
Fractional Clock Divider output is selected.
1
RESERVED1
It is recommended to write these bits to 0.
13
32
read-write
MCUULP_UULP_CLK_CONFIG
UULP APB Clock Configuration Register
0xA4
32
read-write
n
0x0
MCUULP_APB_CLK_DIV_FAC
Specifies the clock division factor for UULP APB Interface.
0
8
read-write
RESERVED1
It is recommended to write these bits to 1.
8
9
read-write
RESERVED2
It is recommended to write these bits to 0.
9
32
read-write
MCUULP_VAD_CLK_CONFIG
MCU-ULP VAD Configuration Register
0x38
32
read-write
n
0x0
MCUULP_VAD_CLK_SEL
Specifies the clock source to be used for VAD Controller
4
5
read-write
0
VAD Slow Clock
0
1
VAD Fast Clock
1
MCUULP_VAD_FCLK_DIV_FAC
Specifies the clock division factor for VAD Fast clock.
9
17
read-write
MCUULP_VAD_FCLK_SEL
Specifies the clock source to be used for VAD Fast Clock
5
9
read-write
0000
MCU ULP AHB Interface clock.
0
0001
MCU-ULP Reference clock.
1
1010
RESERVED6
10
1011
RESERVED7
11
1100
RESERVED8
12
1101
RESERVED9
13
1110
RESERVED10
14
1111
Output clock is gated
15
0010
rc_32mhz_clk.
2
0011
ro_hf_clk.
3
0100
MCU-HP ULP clock.
4
0101
RESERVED1
5
0110
RESERVED2
6
0111
RESERVED3
7
1000
RESERVED4
8
1001
RESERVED5
9
MCUULP_VAD_SCLK_SEL
Specifies the clock source to be used for VAD Slow Clock
1
4
read-write
000
ro_32khz_clk.
0
001
rc_32khz_clk.
1
010
xtal_32khz_clk.
2
011
RESERVED1.
3
100
RESERVED2.
4
101
RESERVED3.
5
110
RESERVED4.
6
111
Output clock is gated
7
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
17
32
read-write
MCU_ULP_VBAT_CLOCK
The MCU ULP VBAT domain contains the MCU ULP VBAT Peripherals. This section describes the different clock sources possible for each peripheral.
ULTRA_LOW_POWER_DOMAINS
0x0
0x0
0x24
registers
n
MCUULP_VBAT_LFCLK_REG
Low Frequency Clock Select Register
0x20
32
read-write
n
0x0
MCUULP_VBAT_LF_CLK_SEL
Select the MCU VBAT clock.
0
3
read-write
ro_32k_clk
Enable ro 32khz clock
1
rc_32k_clk
Enable rc 32khz clock
2
xtal_32k_clk
Enable rc 32khz clock
4
MCUULP_VBAT_LF_CLK_SWITCHED
Status of NPSS Low Frequency Clock Dynamic Clock Mux
3
4
read-write
Disable
Clock switching is in progress
0
Enable
Clock got switched and output clock can be used
1
RESERVED1
It is recommended to write these bits to 0.
4
32
read-only
MCU_WDT
A dedicated window watch dog timer for MCU applications
WDT
0x0
0x0
0x1C
registers
n
NPSS_TO_MCU_WDT_INTR
20
MCU_WWD_ARM_STUCK_EN
watchdog arm stuck enable register
0xC
32
read-write
n
0x0
PROCESSOR_STUCK_RESET_EN
Enable to reset M4 core on seeing LOCKUP signal
16
17
write-only
PROCESSOR_STUCK_RESET_EN_
Read signal for processor stuck reset enable
24
25
read-only
RESERVED1
reser
0
16
read-only
RESERVED2
reser
17
24
read-write
RESERVED3
reser
25
32
read-write
MCU_WWD_INTERRUPT_TIMER
WATCHDOG interrupt timer register
0x0
32
read-write
n
0x0
RESERVED1
reser
5
32
read-only
WWD_INTERRUPT_TIMER
Watchdog Timer programming values
0
5
read-write
MCU_WWD_KEY_ENABLE
watchdog key enable register
0x18
32
read-write
n
0x0
WWD_KEY_ENABLE
enable access to program Watch dog registers
0
32
write-only
MCU_WWD_MODE_AND_RSTART
WATCHDOG mode and restart register
0x10
32
read-write
n
0x0
RESERVED1
reser
1
16
read-only
RESERVED2
reser
24
32
read-only
WWD_MODE_EN_STATUS
Watchdog timer mode
16
24
read-write
WWD_MODE_RSTART
restart pulse to restart watchdog timer
0
1
read-write
MCU_WWD_SYSTEM_RESET_TIMER
MCU watchdog system reset register
0x4
32
read-write
n
0x0
RESERVED1
reser
5
32
read-only
WWD_SYSTEM_RESET_TIMER
Watch dog soc reset delay timer programming values
0
5
read-write
MCU_WWD_WINDOW_TIMER
watchdog window timer register
0x8
32
read-write
n
0x0
RESERVED1
reser
4
32
read-only
WINDOW_TIMER
watchdog window timer
0
4
read-write
OPAMP
The opamps top consists of 3 general purpose Operational Amplifiers (OPAMP) offering rail-to-rail inputs and outputs
OPAMP
0x0
0x0
0xC
registers
n
1
Programs opamp1
0x0
32
read-write
n
0x0
MEMS_RES_BANK_EN
enables mems res bank
21
22
read-write
Disable
Disable the memory register bank
0
Enable
Enable the memory register bank
1
OPAMP1_DYN_EN
dynamic enable for opamp1
31
32
read-write
Disable
Disable the opamp1 dynamic mode
0
Enable
Enable the opamp1 dynamic mode
1
OPAMP1_ENABLE
To enable opamp 1
0
1
read-write
Disable
Disable opamp1
0
Enable
Enable opamp1
1
OPAMP1_EN_RES_BANK
enables the resistor bank 1 for enable 0 for disable
7
8
read-write
Disable
Disable opamp1 resister bank
0
Enable
Enable opamp1 resister bank
1
OPAMP1_INN_SEL
selecting -ve input of opamp
13
16
read-write
Input0_Negative
External pin0 as negative input for OPAMP1
0
Input1_Negative
External pin1 as negative input for OPAMP1
1
DAC
DAC as negative input for OPAMP1
2
res_tap
register tap as negative input for OPAMP1
3
opamp1_out
opamp1_out as negative input for OPAMP1
4
OPAMP1_INP_SEL
selecting +ve input of opamp
16
20
read-write
Input0_positive
External pin0 as positive input for OPAMP1
0
Input1_positive
External pin1 as positive input for OPAMP1
1
Input2_positive
External pin2 as positive input for OPAMP1
2
Input3_positive
External pin3 as positive input for OPAMP1
3
Input4_positive
External pin4 as positive input for OPAMP1
4
Input5_positive
External pin5 as positive input for OPAMP1
5
DAC
DAC as positive input for OPAMP1
6
res_tap
register tap as positive input for OPAMP1
7
opamp1_out
opamp1_out as positive input for OPAMP1
8
OPAMP1_LP_MODE
Enable or disable low power mode
1
2
read-write
Disable
Disable opamp1 low power mode
0
Enable
Enable opamp1 low power mode
1
OPAMP1_OUT_MUX_EN
out mux enable
12
13
read-write
Disable
Disable opamp1 out mux
0
Enable
Enable opamp1 out mux
1
OPAMP1_OUT_MUX_SEL
to connect opamp1 output to pad
20
21
read-write
Dis_select
Dis select opamp1 out mux
0
Select
Select opamp1 out mux
1
OPAMP1_R1_SEL
Programmability to select resister bank R1
2
4
read-write
Zero_ohm
R1 as short
0
Twenty_ohm
R1 as Twenty_ohm
1
Sixty_ohm
R1 as Sixty_ohm
2
Oneforty_ohm
R1 as Oneforty_ohm
3
OPAMP1_R2_SEL
Programmability to select resister bank R2
4
7
read-write
Twenty_ohm
R2 as Twenty_ohm
0
Thirty_ohm
R1 as Thirty_ohm
1
forty_ohm
R1 as forty_ohm
2
Sixty_ohm
R1 as Sixty_ohm
3
Onetwenty_ohm
R1 as Onetwenty_ohm
4
twofifty_ohm
R1 as twofifty_ohm
5
fivehundred_ohm
R1 as fivehundred_ohm
6
Onethousand_ohm
R1 as Onethousand_ohm
7
OPAMP1_RES_MUX_SEL
selecting input for registor bank
8
11
read-write
OPAMP1_RES_TO_OUT_VDD
connect resistor bank to out or vdd i.e 0-out and 1-vdd
11
12
read-write
res_out
connect resister bank to out
0
res_vdd
connect resbank to vdd
1
RESERVED1
res
26
27
read-write
VREF_MUX_EN
vref mux enable
22
26
read-write
VREF_MUX_SEL
vref mux enable
27
31
read-write
2
Programs opamp2
0x4
32
read-write
n
0x0
OPAMP2_DYN_EN
dynamic enable for opamp2
19
20
read-write
Disable
Disable the opamp2 dynamic mode
0
Enable
Enable the opamp2 dynamic mode
1
OPAMP2_ENABLE
enables the opamp2
0
1
read-write
Disable
Disable opamp2
0
Enable
Enable opamp2
1
OPAMP2_EN_RES_BANK
enables the resistor bank 1 for enable 0 for disable
7
8
read-write
Disable
Disable opamp2 resister bank
0
Enable
Enable opamp2 resister bank
1
OPAMP2_INN_SEL
selecting -ve input of opamp
14
16
read-write
Input0_-ve
External pin0 as negative input for OPAMP2
0
DAC
DAC as negative input for OPAMP2
1
res_tap
register tap as negative input for OPAMP2
2
opamp1_out
opamp1_out as negative input for OPAMP2
3
OPAMP2_INP_SEL
selecting +ve input of opamp2
16
19
read-write
Input0_+ve
External pin0 as positive input for OPAMP2
0
Input1_+ve
External pin1 as positive input for OPAMP2
1
Input2_+ve
External pin2 as positive input for OPAMP2
2
DAC
DAC as positive input for OPAMP2
3
res_tap
register tap as positive input for OPAMP2
4
gnd
ground as positive input for OPAMP2
5
OPAMP1_out
OPAMP1_out as positive input for OPAMP2
6
OPAMP2_LP_MODE
select the power mode 0-normal mode and 1-low power mode
1
2
read-write
Disable
Disable opamp2 low power mode
0
Enable
Enable opamp2 low power mode
1
OPAMP2_OUT_MUX_EN
out mux enable
13
14
read-write
Disable
Disable opamp2 out mux
0
Enable
Enable opamp2 out mux
1
OPAMP2_R1_SEL
Programmability to select resister bank R1
2
4
read-write
Zero_ohm
R1 as short
0
Twenty_ohm
R1 as Twenty_ohm
1
Sixty_ohm
R1 as Sixty_ohm
2
Oneforty_ohm
R1 as Oneforty_ohm
3
OPAMP2_R2_SEL
Programmability to select resister bank R2
4
7
read-write
Twenty_ohm
R2 as Twenty_ohm
0
Thirty_ohm
R1 as Thirty_ohm
1
forty_ohm
R1 as forty_ohm
2
Sixty_ohm
R1 as Sixty_ohm
3
Onetwenty_ohm
R1 as Onetwenty_ohm
4
twofifty_ohm
R1 as twofifty_ohm
5
fivehundred_ohm
R1 as fivehundred_ohm
6
Onethousand_ohm
R1 as Onethousand_ohm
7
OPAMP2_RES_MUX_SEL
selecting input for registor bank
8
11
read-write
OPAMP2_RES_TO_OUT_VDD
connect resistor bank to out or vdd or gnd or DAC i.e 0-out and 1-vdd 2-DAC 3-gnd
11
13
read-write
resbank_out
connect resbank to out
0
resbank_vdd
connect resbank to vdd
1
resbank_DAC
connect resbank to DAC
2
resbank_GND
connect resbank to gnd
3
RESERVED1
res
20
32
read-write
3
Programs opamp3
0x8
32
read-write
n
0x0
OPAMP3_DYN_EN
dynamic enable for opamp2
18
19
read-write
Disable
Disable the opamp3 dynamic mode
0
Enable
Enable the opamp3 dynamic mode
1
OPAMP3_ENABLE
enables the opamp3 1 for enable 0 for disable
0
1
read-write
Disable
Disable opamp3
0
Enable
Enable opamp3
1
OPAMP3_EN_RES_BANK
enables the resistor bank 1 for enable 0 for disable
7
8
read-write
Disable
Disable opamp3 resister bank
0
Enable
Enable opamp3 resister bank
1
OPAMP3_INN_SEL
selecting -ve input of opamp
13
15
read-write
Input0_-ve
External pin0 as negative input for OPAMP3
0
DAC
DAC as negative input for OPAMP3
1
res_tap
register tap as negative input for OPAMP3
2
opamp2_out
opamp2_out as negative input for OPAMP3
3
OPAMP3_INP_SEL
selecting +ve input of opamp
15
18
read-write
Input0_+ve
External pin0 as positive input for OPAMP3
0
Input1_+ve
External pin1 as positive input for OPAMP3
1
DAC
DAC as positive input for OPAMP3
2
res_tap
register tap as positive input for OPAMP3
3
gnd
ground as positive input for OPAMP3
4
OPAMP2_out
OPAMP2_out as positive input for OPAMP3
5
OPAMP2_restap
OPAMP2_restap as positive input for OPAMP3
6
OPAMP3_LP_MODE
select the power mode 0-normal mode and 1-low power mode
1
2
read-write
Disable
Disable opamp3 low power mode
0
Enable
Enable opamp3 low power mode
1
OPAMP3_OUT_MUX_EN
out mux enable
12
13
read-write
Disable
Disable opamp3 out mux
0
Enable
Enable opamp3 out mux
1
OPAMP3_R1_SEL
Programmability to select resister bank R1
2
4
read-write
Zero_ohm
R1 as short
0
Twenty_ohm
R1 as Twenty_ohm
1
Sixty_ohm
R1 as Sixty_ohm
2
Oneforty_ohm
R1 as Oneforty_ohm
3
OPAMP3_R2_SEL
Programmability to select resister bank R2
4
7
read-write
Twenty_ohm
R2 as Twenty_ohm
0
Thirty_ohm
R1 as Thirty_ohm
1
forty_ohm
R1 as forty_ohm
2
Sixty_ohm
R1 as Sixty_ohm
3
Onetwenty_ohm
R1 as Onetwenty_ohm
4
twofifty_ohm
R1 as twofifty_ohm
5
fivehundred_ohm
R1 as fivehundred_ohm
6
Onethousand_ohm
R1 as Onethousand_ohm
7
OPAMP3_RES_MUX_SEL
selecting input for registor bank
8
11
read-write
OPAMP3_RES_TO_OUT_VDD
connect resistor bank to out or vdd i.e 0-out and 1-vdd
11
12
read-write
res_out
connect resister bank to out
0
res_vdd
connect resbank to vdd
1
RESERVED1
res
19
32
read-write
POWER_DOMAINS
All the Applications, High Speed Interfaces and Peripherals are segregated into multiple power domains to achieve lower current consumption when they are inactive. At reset, all the domains are powered ON.
POWER_DOMAINS
0x0
0x8
0x88
registers
n
DLL_POWER_CONTROL
Controls power for DDR-FLASH-DLL domains
0x84
32
read-write
n
0x0
PWRCTRL_DLL_RX
It is enable power to the Rx section of DLL
2
3
read-write
Disable
Writing 0 to this disables power to the Rx Section of DLL
0
Enable
Writing 1 to this enables power to the Rx Section of DLL
1
PWRCTRL_DLL_TX
It is enable power to the Tx section of DLL
6
7
read-write
Disable
Writing 0 to this disables power to the Tx Section of DLL
0
Enable
Writing 1 to this enables power to the Tx Section of DLL
1
RESERVED1
It is recommended to write these bits to 0.
0
2
read-write
RESERVED2
It is not recommended to overwrite the content in this bit.
3
6
read-write
RESERVED3
It is recommended to write these bits to 0.
7
32
read-write
PLL_POWER_CONTROL
Controls power for HIGH-FREQ-PLL domains.
0x80
32
read-write
n
0x0
PWRCTRL_PLL_REG
It is enable power to the PLL Programming Registers.
6
7
read-write
Disable
Writing 0 to this disables power to the PLL Programming Registers.
0
Enable
Writing 1 to this enables power to the PLL Programming Registers.
1
RESERVED1
It is recommended to write these bits to 0.
0
6
read-write
RESERVED2
It is recommended to write these bits to 0.
8
32
read-write
SOCPLL_VDD13_ISO_EN
This is used for isolation of signals from DC-DC 1.35 to the VBATT supply in SoC-PLL to avoid leakage.
7
8
read-write
Disable
Writing 1 to this enables isolation.
0
Enable
Writing 0 to this disables isolation.
1
POWER_CONTROL_CLEAR
Disables power for APPLICATIONS, HIGH SPEED INTERFACES, HP-PERIPHERALS domains
0xC
32
read-write
n
0x0
PWRCTRL_CCI
Disable Power to CCI
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the CCI.
1
PWRCTRL_DEBUG
Disable Power to DEBUG.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the DEBUG.
1
PWRCTRL_DMA
Disable Power to DMA.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the DMA.
1
PWRCTRL_EFUSE
Disable Power to EFUSE
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the EFUSE.
1
PWRCTRL_ETHERNET
Disable Power to SDIO-SPI Slave.
12
13
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the ETHERNET.
1
PWRCTRL_FPU
Disable Power to FPU.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the FPU.
1
PWRCTRL_ICACHE
Disable Power to ICACHE.
15
16
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the ICACHE.
1
PWRCTRL_PERI_DOMAIN1
Disable Power to PERI-DOMAIN1.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the PERI-DOMAIN1.
1
PWRCTRL_PERI_DOMAIN2
Disable Power to PERI-DOMAIN2.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the PERI-DOMAIN2.
1
PWRCTRL_PERI_DOMAIN3
Disable Power to PERI-DOMAIN3.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the PERI-DOMAIN3.
1
PWRCTRL_QSPI
Disable Power to QSPI.
13
14
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the QSPI.
1
PWRCTRL_ROM
Disable Power to ROM.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the ROM.
1
PWRCTRL_SDIO_SPI
Disable Power to SDIO-SPI Slave.
11
12
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the SDIO-SPI Slave.
1
PWRCTRL_SDMEM
Disable Power to SDMEM
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the SDMEM.
1
PWRCTRL_USB
Disable Power to USB.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the USB.
1
RESERVED1
It is recommended to write these bits to 0.
0
2
read-write
RESERVED2
It is recommended to write these bits to 0.
3
4
read-write
RESERVED3
It is recommended to write these bits to 0.
14
15
read-write
RESERVED4
It is recommended to write these bits to 0.
18
19
read-write
RESERVED5
It is recommended to write these bits to 0.
19
22
read-write
RESERVED6
It is recommended to write these bits to 0.
23
32
read-write
POWER_CONTROL_SET
Enables power for APPLICATIONS, HIGH SPEED INTERFACES, HP-PERIPHERALS domains
0x8
32
read-write
n
0x0
PWRCTRL_CCI
Enable Power to CCI
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the CCI.
1
PWRCTRL_DEBUG
Enable Power to DEBUG.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the DEBUG.
1
PWRCTRL_DMA
Enable Power to DMA.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the DMA.
1
PWRCTRL_EFUSE
Enable Power to EFUSE
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the EFUSE.
1
PWRCTRL_ETHERNET
Enable Power to SDIO-SPI Slave.
12
13
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the ETHERNET.
1
PWRCTRL_FPU
Enable Power to FPU.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the FPU.
1
PWRCTRL_ICACHE
Enable Power to ICACHE.
15
16
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the ICACHE.
1
PWRCTRL_PERI_DOMAIN1
Enable Power to PERI-DOMAIN1.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the PERI-DOMAIN1.
1
PWRCTRL_PERI_DOMAIN2
Enable Power to PERI-DOMAIN2.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the PERI-DOMAIN2.
1
PWRCTRL_PERI_DOMAIN3
Enable Power to PERI-DOMAIN3.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the PERI-DOMAIN3.
1
PWRCTRL_QSPI
Enable Power to QSPI.
13
14
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the QSPI.
1
PWRCTRL_ROM
Enable Power to ROM.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the ROM.
1
PWRCTRL_SDIO_SPI
Enable Power to SDIO-SPI Slave.
11
12
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the SDIO-SPI Slave.
1
PWRCTRL_SDMEM
Enable Power to SDMEM
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the SDMEM.
1
PWRCTRL_USB
Enable Power to USB.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the USB.
1
RESERVED1
It is recommended to write these bits to 0.
0
2
read-write
RESERVED2
It is recommended to write these bits to 0.
3
4
read-write
RESERVED3
It is recommended to write these bits to 0.
14
15
read-write
RESERVED4
It is recommended to write these bits to 0.
18
19
read-write
RESERVED5
It is recommended to write these bits to 0.
19
22
read-write
RESERVED6
It is recommended to write these bits to 0.
23
32
read-write
SRAM_POWER_CONTROL_REG1_CLEAR
Disables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
0x14
32
read-write
n
0x0
PWRCTRL1_HPSRAM1_1
It is disables power control1 to all banks in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-1.
1
PWRCTRL1_HPSRAM1_2
It is disables power control1 to all banks in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-2.
1
PWRCTRL1_HPSRAM1_3
It is disables power control1 to all banks in HP-SRAM1-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-3.
1
PWRCTRL1_HPSRAM2_1
It is disables power control1 to all banks in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-1.
1
PWRCTRL1_HPSRAM2_2
It is disables power to all banks in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-2.
1
PWRCTRL1_HPSRAM2_3
It is disables power control1 to all banks in HP-SRAM2-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-3.
1
PWRCTRL1_HPSRAM2_4
It is disables power control1 to all banks in HP-SRAM2-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-4.
1
PWRCTRL1_LPSRAM_1
It is disables power control1 to all banks in LP-SRAM-1.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-1.
1
PWRCTRL1_LPSRAM_2
It is disables power control1 to all banks in LP-SRAM-2.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-2.
1
PWRCTRL1_LPSRAM_3
It is disables power control1 to all banks in LP-SRAM-3.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-3.
1
PWRCTRL1_LPSRAM_4
It is disables power control1 to all banks in LP-SRAM-4.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-4.
1
PWRCTRL1_LPSRAM_5
It is disables power control1 to all banks in LP-SRAM-5.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-5.
1
PWRCTRL1_LPSRAM_6
It is disables power control1 to all banks in LP-SRAM-6.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-6.
1
PWRCTRL1_LPSRAM_7
It is disables power control1 to all banks in LP-SRAM-7.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
10
16
read-write
RESERVED2
It is recommended to write these bits to 0.
20
32
read-write
SRAM_POWER_CONTROL_REG1_SET
Enables power for HP-SRAM1, HP-SRAM2 and LP-SRAM domains.
0x10
32
read-write
n
0x0
PWRCTRL1_HPSRAM1_1
It is enables power control1 to all banks in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-1.
1
PWRCTRL1_HPSRAM1_2
It is enables power control1 to all banks in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-2.
1
PWRCTRL1_HPSRAM1_3
It is enables power control1 to all banks in HP-SRAM1-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-3.
1
PWRCTRL1_HPSRAM2_1
It is enables power control1 to all banks in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-1.
1
PWRCTRL1_HPSRAM2_2
It is enables power control1 to all banks in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-2.
1
PWRCTRL1_HPSRAM2_3
It is enables power control1 to all banks in HP-SRAM2-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-3.
1
PWRCTRL1_HPSRAM2_4
It is enables power control1 to all banks in HP-SRAM2-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-4.
1
PWRCTRL1_LPSRAM_1
It is enables power control1 to all banks in LP-SRAM-1.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-1.
1
PWRCTRL1_LPSRAM_2
It is enables power control1 to all banks in LP-SRAM-2.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-2.
1
PWRCTRL1_LPSRAM_3
It is enables power control1 to all banks in LP-SRAM-3.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-3.
1
PWRCTRL1_LPSRAM_4
It is enables power control1 to all banks in LP-SRAM-4.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-4.
1
PWRCTRL1_LPSRAM_5
It is enables power control1 to all banks in LP-SRAM-5.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-5.
1
PWRCTRL1_LPSRAM_6
It is enables power control1 to all banks in LP-SRAM-6.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-6.
1
PWRCTRL1_LPSRAM_7
It is enables power control1 to all banks in LP-SRAM-7.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
10
16
read-write
RESERVED2
It is recommended to write these bits to 0.
20
32
read-write
SRAM_POWER_CONTROL_REG2_CLEAR
Disables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
0x1C
32
read-write
n
0x0
PWRCTRL2_HPSRAM1_1
It is disable power control2 to all banks in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-1.
1
PWRCTRL2_HPSRAM1_2
It is disable power control2 to all banks in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-2.
1
PWRCTRL2_HPSRAM1_3
It is disable power control2 to all banks in HP-SRAM1-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM1-3.
1
PWRCTRL2_HPSRAM2_1
It is disable power control2 to all banks in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-1.
1
PWRCTRL2_HPSRAM2_2
It is disable power control2 to all banks in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-2.
1
PWRCTRL2_HPSRAM2_3
It is disable power control2 to all banks in HP-SRAM2-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-3.
1
PWRCTRL2_HPSRAM2_4
It is disable power control2 to all banks in HP-SRAM2-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in HP-SRAM2-4.
1
PWRCTRL2_LPSRAM_1
It is disable power control2 to all banks in LP-SRAM-1.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-1.
1
PWRCTRL2_LPSRAM_2
It is disable power control2 to all banks in LP-SRAM-2.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-2.
1
PWRCTRL2_LPSRAM_3
It is disable power to all banks in LP-SRAM-3.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-3.
1
PWRCTRL2_LPSRAM_4
It is disable power control2 to all banks in LP-SRAM-4.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-4.
1
PWRCTRL2_LPSRAM_5
It is disable power control2 to all banks in LP-SRAM-5.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-5.
1
PWRCTRL2_LPSRAM_6
It is disable power control2 to all banks in LP-SRAM-6.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-6.
1
PWRCTRL2_LPSRAM_7
It is disable power control2 to all banks in LP-SRAM-7.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
10
16
read-write
RESERVED2
It is recommended to write these bits to 0.
20
32
read-write
SRAM_POWER_CONTROL_REG2_SET
Enables power for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
0x18
32
read-write
n
0x0
PWRCTRL2_HPSRAM1_1
It is enable power control2 to all banks in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-1.
1
PWRCTRL2_HPSRAM1_2
It is enable power control2 to all banks in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-2.
1
PWRCTRL2_HPSRAM1_3
It is enable power control2 to all banks in HP-SRAM1-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM1-3.
1
PWRCTRL2_HPSRAM2_1
It is enable power control2 to all banks in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-1.
1
PWRCTRL2_HPSRAM2_2
It is enable power control2 to all banks in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-2.
1
PWRCTRL2_HPSRAM2_3
It is enable power control2 to all banks in HP-SRAM2-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-3.
1
PWRCTRL2_HPSRAM2_4
It is enable power control2 to all banks in HP-SRAM2-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in HP-SRAM2-4.
1
PWRCTRL2_LPSRAM_1
It is enable power control2 to all banks in LP-SRAM-1.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-1.
1
PWRCTRL2_LPSRAM_2
It is enable power control2 to all banks in LP-SRAM-2.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-2.
1
PWRCTRL2_LPSRAM_3
It is enable power to all banks in LP-SRAM-3.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-3.
1
PWRCTRL2_LPSRAM_4
It is enable power control2 to all banks in LP-SRAM-4.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-4.
1
PWRCTRL2_LPSRAM_5
It is enables power control2 to all banks in LP-SRAM-5.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-5.
1
PWRCTRL2_LPSRAM_6
It is enables power control2 to all banks in LP-SRAM-6.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-6.
1
PWRCTRL2_LPSRAM_7
It is enable power control2 to all banks in LP-SRAM-7.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
10
16
read-write
RESERVED2
It is recommended to write these bits to 0.
20
32
read-write
SRAM_POWER_CONTROL_REG3_CLEAR
Disables isolation on HP-SRAM, HP-SRAM2 and LP-SRAM input signals.
0x24
32
read-write
n
0x0
INP_ISO_HP_SRAM1
It is disables isolation on inputs for HP-SRAM1 Banks.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables isolation on inputs for HP-SRAM1 Banks.
1
INP_ISO_HP_SRAM2
It is disables isolation on inputs for HP-SRAM2 Banks.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables isolation on inputs for HP-SRAM2 Banks.
1
INP_ISO_LP_SRAM
It is disable isolation on inputs for LP-SRAM Banks.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables isolation on inputs for LP-SRAM Banks.
1
RESERVED1
It is recommended to write these bits to 0.
1
3
read-write
RESERVED2
It is recommended to write these bits to 0.
4
16
read-write
RESERVED3
It is recommended to write these bits to 0.
17
32
read-write
SRAM_POWER_CONTROL_REG3_SET
Enables isolation on HP-SRAM, HP-SRAM2 and LP-SRAM input signals.
0x20
32
read-write
n
0x0
INP_ISO_HP_SRAM1
It is enables isolation on inputs for HP-SRAM1 Banks.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables isolation on inputs for HP-SRAM1 Banks.
1
INP_ISO_HP_SRAM2
It is enables isolation on inputs for HP-SRAM2 Banks.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables isolation on inputs for HP-SRAM2 Banks.
1
INP_ISO_LP_SRAM
It is enable isolation on inputs for LP-SRAM Banks.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables isolation on inputs for LP-SRAM Banks.
1
RESERVED1
It is recommended to write these bits to 0.
1
3
read-write
RESERVED2
It is recommended to write these bits to 0.
4
16
read-write
RESERVED3
It is recommended to write these bits to 0.
17
32
read-write
SRAM_POWER_CONTROL_REG4_CLEAR
Disables Deep-Sleep for HP-SRAM, HP-SRAM2 and LP-SRAM domains
0x2C
32
read-write
n
0x0
DS_HPSRAM1_1_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-1.
1
DS_HPSRAM1_2_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-2.
1
DS_HPSRAM1_2_B2
It is disable deep sleep mode to 2nd Bank in HP-SRAM1-2.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM1-2.
1
DS_HPSRAM1_3_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM1-3.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM1-3.
1
DS_HPSRAM2_1_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-1.
1
DS_HPSRAM2_2_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disable deep sleep mode to 1st Bank in HP-SRAM2-2.
1
DS_HPSRAM2_2_B2
It is disable deep sleep mode to 2nd Bank in HP-SRAM2-2.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-2.
1
DS_HPSRAM2_3_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM2-3.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B2
It is disable deep sleep mode to 2nd Bank in HP-SRAM2-3.
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B3
It is disable deep sleep mode to 3rd Bank in HP-SRAM2-3.
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B4
It is disable deep sleep mode to 4th Bank in HP-SRAM2-3.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 4th Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B5
It is disable deep sleep mode to 5th Bank in HP-SRAM2-3.
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 5th Bank in HP-SRAM2-3.
1
DS_HPSRAM2_4_B1
It is disable deep sleep mode to 1st Bank in HP-SRAM2-4.
24
25
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B2
It is disable deep sleep mode to 2nd Bank in HP-SRAM2-4.
25
26
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B3
It is disable deep sleep mode to 3rd Bank in HP-SRAM2-4.
26
27
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B4
It is disable deep sleep mode to 4th Bank in HP-SRAM2-4.
27
28
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 4th Bank in HP-SRAM2-4.
1
DS_LPSRAM_1_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-1.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-1.
1
DS_LPSRAM_2_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-2.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-2.
1
DS_LPSRAM_3_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-3.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-3.
1
DS_LPSRAM_4_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-4.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-4.
1
DS_LPSRAM_5_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-5.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-5.
1
DS_LPSRAM_5_B2
It is disable deep sleep mode to 2nd Bank in LP-SRAM-5.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in LP-SRAM-5.
1
DS_LPSRAM_6_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-6.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B2
It is disable deep sleep mode to 2nd Bank in LP-SRAM-6.
11
12
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 2nd Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B3
It is disable deep sleep mode to 3rd Bank in LP-SRAM-6.
12
13
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 3rd Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B4
It is disable deep sleep mode to 4th Bank in LP-SRAM-6.
13
14
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 4th Bank in LP-SRAM-6.
1
DS_LPSRAM_7_B1
It is disable deep sleep mode to 1st Bank in LP-SRAM-7.
14
15
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
15
16
read-write
RESERVED2
It is recommended to write these bits to 0.
28
32
read-write
SRAM_POWER_CONTROL_REG4_SET
Enables Deep-Sleep for HP-SRAM, HP-SRAM2 and LP-SRAM domains.
0x28
32
read-write
n
0x0
DS_HPSRAM1_1_B1
It is enable deep sleep mode to 1st Bank in HP-SRAM1-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-1.
1
DS_HPSRAM1_2_B1
It is enable deep sleep mode to 1st Bank in HP-SRAM1-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-2.
1
DS_HPSRAM1_2_B2
It is enable deep sleep mode to 2nd Bank in HP-SRAM1-2.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM1-2.
1
DS_HPSRAM1_3_B1
It is enable deep sleep mode to 1st Bank in HP-SRAM1-3.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM1-3.
1
DS_HPSRAM2_1_B1
It is enables deep sleep mode to 1st Bank in HP-SRAM2-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-1.
1
DS_HPSRAM2_2_B1
It is enables deep sleep mode to 1st Bank in HP-SRAM2-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-2.
1
DS_HPSRAM2_2_B2
It is enables deep sleep mode to 2nd Bank in HP-SRAM2-2.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-2.
1
DS_HPSRAM2_3_B1
It is enables deep sleep mode to 1st Bank in HP-SRAM2-3.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B2
It is enables deep sleep mode to 2nd Bank in HP-SRAM2-3.
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B3
It is enables deep sleep mode to 3rd Bank in HP-SRAM2-3.
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B4
It is enables deep sleep mode to 4th Bank in HP-SRAM2-3.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 4th Bank in HP-SRAM2-3.
1
DS_HPSRAM2_3_B5
It is enables deep sleep mode to 5th Bank in HP-SRAM2-3.
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 5th Bank in HP-SRAM2-3.
1
DS_HPSRAM2_4_B1
It is enables deep sleep mode to 1st Bank in HP-SRAM2-4.
24
25
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B2
It is enables deep sleep mode to 2nd Bank in HP-SRAM2-4.
25
26
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B3
It is enables deep sleep mode to 3rd Bank in HP-SRAM2-4.
26
27
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in HP-SRAM2-4.
1
DS_HPSRAM2_4_B4
It is enables deep sleep mode to 4th Bank in HP-SRAM2-4.
27
28
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 4th Bank in HP-SRAM2-4.
1
DS_LPSRAM_1_B1
It is enable deep sleep mode to 1st Bank in LP-SRAM-1.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-1.
1
DS_LPSRAM_2_B1
It is enable deep sleep mode to 1st Bank in LP-SRAM-2.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-2.
1
DS_LPSRAM_3_B1
It is enable deep sleep mode to 1st Bank in LP-SRAM-3.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-3.
1
DS_LPSRAM_4_B1
It is enables deep sleep mode to 1st Bank in LP-SRAM-4.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-4.
1
DS_LPSRAM_5_B1
It is enables deep sleep mode to 1st Bank in LP-SRAM-5.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-5.
1
DS_LPSRAM_5_B2
It is enables deep sleep mode to 2nd Bank in LP-SRAM-5.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in LP-SRAM-5.
1
DS_LPSRAM_6_B1
It is enables deep sleep mode to 1st Bank in LP-SRAM-6.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B2
It is enables deep sleep mode to 2nd Bank in LP-SRAM-6.
11
12
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 2nd Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B3
It is enables deep sleep mode to 3rd Bank in LP-SRAM-6.
12
13
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 3rd Bank in LP-SRAM-6.
1
DS_LPSRAM_6_B4
It is enables deep sleep mode to 4th Bank in LP-SRAM-6.
13
14
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 4th Bank in LP-SRAM-6.
1
DS_LPSRAM_7_B1
It is enables deep sleep mode to 1st Bank in LP-SRAM-7.
14
15
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in LP-SRAM-7.
1
RESERVED1
It is recommended to write these bits to 0.
15
16
read-write
RESERVED2
It is recommended to write these bits to 0.
28
32
read-write
ULP_ISOLATION_CTRL
Isolation Configuration for Ultra Low-Power Mode of the processor (PS2 State)
0x3C
32
read-write
n
0x0
RESERVED1
It is recommended to write these bits to 0.
6
32
read-write
ULP_ISOLATION_CTRL
Writing 0xAAAA to this provides immediate trigger to SHIP mode.
0
6
write-only
Disable
Writing 'h00 to this disables Isolation between Low-Voltage and HIGH VOLTAGE Domains.
00
Enable
Writing 'h3F to this enables Isolation between Low-Voltage and HIGH VOLTAGE Domains
0x3F
ULP_PERIPHERAL_POWER_CONTROL_CLEAR
Enables power for ULP-PERIPHERALS domains
0x48
32
read-write
n
0x0
PWRCTRL_ADC_DAC
It is disable power to ADC/DAC
25
26
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the ADC/DAC.
1
PWRCTRL_DMA
It is disable power to IR
27
28
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the DMA.
1
PWRCTRL_FIM
It is disable power to FIM
28
29
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the FIM.
1
PWRCTRL_I2C
It is disable power to I2C
24
25
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the I2C.
1
PWRCTRL_I2S
It is disable power to SPI/SSI
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the I2S.
1
PWRCTRL_IR
It is disable power to IR
26
27
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the IR.
1
PWRCTRL_SSI
It is disable power to SPI/SSI
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the SPI/SSI.
1
PWRCTRL_TIMER
It is disable power to TIMER
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the TIMER.
1
PWRCTRL_TOUCH
It is disable power to TOUCH
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the TOUCH.
1
PWRCTRL_UART
It is disable power to UART
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the UART.
1
PWRCTRL_VAD
It is disable power to TOUCH
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the VAD.
1
RESERVED1
It is recommended to write these bits to 0.
0
18
read-write
RESERVED2
It is recommended to write these bits to 0.
29
32
read-write
ULP_PERIPHERAL_POWER_CONTROL_SET
Enables power for ULP-PERIPHERALS domains
0x44
32
read-write
n
0x0
PWRCTRL_ADC_DAC
It is enable power to ADC/DAC
25
26
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the ADC/DAC.
1
PWRCTRL_DMA
It is enable power to IR
27
28
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the DMA.
1
PWRCTRL_FIM
It is enable power to FIM
28
29
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the FIM.
1
PWRCTRL_I2C
It is enable power to I2C
24
25
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the I2C.
1
PWRCTRL_I2S
It is enable power to SPI/SSI
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the I2S.
1
PWRCTRL_IR
It is enable power to IR
26
27
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the IR.
1
PWRCTRL_SSI
It is enable power to SPI/SSI
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the SPI/SSI.
1
PWRCTRL_TIMER
It is enable power to TIMER
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the TIMER.
1
PWRCTRL_TOUCH
It is enable power to TOUCH
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the TOUCH.
1
PWRCTRL_UART
It is enable power to UART
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the UART.
1
PWRCTRL_VAD
It is enable power to TOUCH
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the VAD.
1
RESERVED1
It is recommended to write these bits to 0.
0
18
read-write
RESERVED2
It is recommended to write these bits to 0.
29
32
read-write
ULP_SRAM_POWER_CONTROL_REG1_CLEAR
Disables power for ULP-SRAM domains.
0x50
32
read-write
n
0x0
PWRCTRL1_ULPSRAM_1
It is disable power to all Banks in ULP-SRAM-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-1.
1
PWRCTRL1_ULPSRAM_2
It is disable power to all Banks in ULP-SRAM-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
1
PWRCTRL1_ULPSRAM_3
It is disable power to all Banks in ULP-SRAM-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-3.
1
PWRCTRL1_ULPSRAM_4
It is disable power to all Banks in ULP-SRAM-4.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-4.
1
PWRCTRL1_ULPSRAM_5
It is disable power to all Banks in ULP-SRAM-5.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-5.
1
PWRCTRL1_ULPSRAM_6
It is disable power to all Banks in ULP-SRAM-6.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-6.
1
PWRCTRL1_ULPSRAM_7
It is disable power to all Banks in ULP-SRAM-7.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-7.
1
PWRCTRL1_ULPSRAM_8
It is disable power to all Banks in ULP-SRAM-8.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disable power to all Banks in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
8
32
read-write
ULP_SRAM_POWER_CONTROL_REG1_SET
Enables power for ULP-PERIPHERALS domains
0x4C
32
read-write
n
0x0
PWRCTRL1_ULPSRAM_1
It is enable power to all Banks in ULP-SRAM-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-1.
1
PWRCTRL1_ULPSRAM_2
It is enable power to all Banks in ULP-SRAM-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
1
PWRCTRL1_ULPSRAM_3
It is enable power to all Banks in ULP-SRAM-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-3.
1
PWRCTRL1_ULPSRAM_4
It is enable power to all Banks in ULP-SRAM-4.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-4.
1
PWRCTRL1_ULPSRAM_5
It is enable power to all Banks in ULP-SRAM-5.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-5.
1
PWRCTRL1_ULPSRAM_6
It is enable power to all Banks in ULP-SRAM-6.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-6.
1
PWRCTRL1_ULPSRAM_7
It is enable power to all Banks in ULP-SRAM-7.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-7.
1
PWRCTRL1_ULPSRAM_8
It is enable power to all Banks in ULP-SRAM-8.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
8
32
read-write
ULP_SRAM_POWER_CONTROL_REG2_CLEAR
Disables Deep-Sleep for ULP-SRAM domains
0x60
32
read-write
n
0x0
PWRCTRL2_ULPSRAM_1
It is disable power control2 to all Banks in ULP-SRAM-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
1
PWRCTRL2_ULPSRAM_2
It is disable power control2 to all Banks in ULP-SRAM-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-2.
1
PWRCTRL2_ULPSRAM_3
It is disable power control2 to all Banks in ULP-SRAM-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-3.
1
PWRCTRL2_ULPSRAM_4
It is disable power control2 to all Banks in ULP-SRAM-4.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-4.
1
PWRCTRL2_ULPSRAM_5
It is disable power control2 to all Banks in ULP-SRAM-5.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-5.
1
PWRCTRL2_ULPSRAM_6
It is disable power control2 to all Banks in ULP-SRAM-6.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-6.
1
PWRCTRL2_ULPSRAM_7
It is disable power control2 to all Banks in ULP-SRAM-7.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-7.
1
PWRCTRL2_ULPSRAM_8
It is disable power control2 to all Banks in ULP-SRAM-8.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to all Banks in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
8
32
read-write
ULP_SRAM_POWER_CONTROL_REG2_SET
Enables Deep-Sleep for ULP-SRAM domains.
0x5C
32
read-write
n
0x0
PWRCTRL2_ULPSRAM_1
It is enable power control2 to all Banks in ULP-SRAM-1.
0
1
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
1
PWRCTRL2_ULPSRAM_2
It is enable power control2 to all Banks in ULP-SRAM-2.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-2.
1
PWRCTRL2_ULPSRAM_3
It is enable power control2 to all Banks in ULP-SRAM-3.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-3.
1
PWRCTRL2_ULPSRAM_4
It is enable power control2 to all Banks in ULP-SRAM-4.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-4.
1
PWRCTRL2_ULPSRAM_5
It is enable power control2 to all Banks in ULP-SRAM-5.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-5.
1
PWRCTRL2_ULPSRAM_6
It is enable power control2 to all Banks in ULP-SRAM-6.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-6.
1
PWRCTRL2_ULPSRAM_7
It is enable power control2 to all Banks in ULP-SRAM-7.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-7.
1
PWRCTRL2_ULPSRAM_8
It is enable power control2 to all Banks in ULP-SRAM-8.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to all Banks in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
8
32
read-write
ULP_SRAM_POWER_CONTROL_REG4_CLEAR
Disables power for ULP-SRAM domains.
0x58
32
read-write
n
0x0
DS_ULPSRAM_1_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-1.
1
DS_ULPSRAM_2_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-2.
1
DS_ULPSRAM_3_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-3.
1
DS_ULPSRAM_4_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-4.
1
DS_ULPSRAM_5_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-5.
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-5.
1
DS_ULPSRAM_6_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-6.
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-6.
1
DS_ULPSRAM_7_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-7.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-7.
1
DS_ULPSRAM_8_B1
It is disable deep sleep mode to 1st Bank in ULP-SRAM-8
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables deep sleep mode to 1st Bank in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
0
16
read-write
RESERVED2
It is recommended to write these bits to 0.
24
32
read-write
ULP_SRAM_POWER_CONTROL_REG4_SET
Enables power for ULP-SRAM domains.
0x54
32
read-write
n
0x0
DS_ULPSRAM_1_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-1.
16
17
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-1.
1
DS_ULPSRAM_2_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-2.
17
18
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-2.
1
DS_ULPSRAM_3_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-3.
18
19
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-3.
1
DS_ULPSRAM_4_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-4.
19
20
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-4.
1
DS_ULPSRAM_5_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-5.
20
21
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-5.
1
DS_ULPSRAM_6_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-6.
21
22
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-6.
1
DS_ULPSRAM_7_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-7.
22
23
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-7.
1
DS_ULPSRAM_8_B1
It is enable deep sleep mode to 1st Bank in ULP-SRAM-8
23
24
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables deep sleep mode to 1st Bank in ULP-SRAM-8.
1
RESERVED1
It is recommended to write these bits to 0.
0
16
read-write
RESERVED2
It is recommended to write these bits to 0.
24
32
read-write
QEI
The Quadrature Encoder Interface (QEI) module provides the interface to incremental encoders for obtaining mechanical position data
QEI
0x0
0x0
0x50
registers
n
QEI
49
CLK_FREQ_REG
Quadrature Encoder clock frequency register
0x38
32
read-write
n
0x0
0x0
QEI_CLK_FREQ
Indication of clock frequency on which QEI controller is running.
0
9
read-write
RESERVED1
Reserved1
9
32
read-write
CNTLR_INIT_REG
Quadrature Encoder initialization register
0xC
32
read-write
n
0x0
0x0
DF_CLK_DIVIDE_SLT
Digital Filter Clock Divide Select bits
6
10
read-write
0000
0000 = 1:1 Clock divide for Index, position A and B
0
0001
0001 = 1:2 Clock divide for Index, position A and B
1
1010
1010 = 1:1024 Clock divide for Index, position A and B
10
0010
0010 = 1:4 Clock divide for Index, position A and B
2
0011
0011 = 1:8 Clock divide for Index, position A and B
3
0100
0100 = 1:16 Clock divide for Index, position A and B
4
0101
0101 = 1:32 Clock divide for Index, position A and B
5
0110
0110 = 1:64 Clock divide for Index, position A and B
6
0111
0111 = 1:128 Clock divide for Index, position A and B
7
1000
1000 = 1:256 Clock divide for Index, position A and B
8
1001
1001 = 1:512 Clock divide for Index, position A and B
9
INDEX_CNT_INIT
Index counter initial value in unidirectional index enable mode.
12
13
read-write
INDEX_MATCH_VALUE
These bits allow user to specify the state of position A and B during index pulse generation.
4
6
read-write
QEI_ENCODING_MODE
NONE
0
2
read-write
00
1x mode
0
01
2x mode
1
10
4x mode
2
11
NONE
3
RESERVED1
Reserved1
2
4
read-write
RESERVED2
Reserved2
13
32
read-write
UNIDIRECTIONAL_INDEX
Uni directional index enable.
11
12
read-write
Disable
NONE
0
Enable
1 means direction change in position counter resets index counter
1
UNIDIRECTIONAL_VELOCITY
Uni directional velocity enable.
10
11
read-write
Disable
NONE
0
Enable
1 means direction change in position counter resets velocity counter
1
CTRL_RESET_REG
Quadrature Encoder control reset register
0x8
32
read-write
n
0x0
0x0
DIGITAL_FILTER_BYPASS
NONE
9
10
read-write
Disable
digital filter is in-path for all input signals
0
Enable
digital filter is bypassed for all input signals (position A, position B and Index)
1
INDEX_CNT_RST
1= index counter is going to reset.
15
16
read-write
INDEX_CNT_RST_EN
NONE
8
9
read-write
Disable
NONE
0
Enable
index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register.
1
POS_CNT_DIRECTION_CTRL
NONE
4
5
read-write
Disable
position B pin defines the direction of position counter
0
Enable
pos_cnt_dir_frm_reg defines the position counter direction
1
POS_CNT_DIR_FRM_REG
Position Counter Direction indication from user
5
6
read-write
Disable
Position counter direction is negative (-)
0
Enable
Position counter direction is positive (+)
1
POS_CNT_RST
1=position counter is going to reset
14
15
read-write
POS_CNT_RST_WITH_INDEX_EN
Phase A and Phase B Input Swap Select bit
2
3
read-write
Disable
position counter is getting reset after reaching max count, which is mentioned in position_max_cnt
0
Enable
position counter is getting reset for every index pulse
1
QEI_POS_CNT_16_BIT_MODE
Qei position counter 16 bit mode enable
13
14
read-write
Disable
No effect
0
Enable
QEI position status counter will be working as a 16 bit counter
1
QEI_SFT_RST
Quadrature encoder soft reset. It is self reset signal
0
1
read-only
QEI_STOP_IN_IDLE
NONE
12
13
read-write
Disable
QEI position status counter is working as 32 bit counter.
0
Enable
QEI position status counter is working as 16 bit counter
1
QEI_SWAP_PHASE_AB
Phase A and Phase B Input Swap Select bit
1
2
read-write
Disable
Phase A and Phase B inputs are not swapped
0
Enable
Phase A and Phase B inputs are swapped
1
RESERVED1
Reserved1
3
4
read-write
RESERVED2
Reserved2
6
7
read-write
RESERVED3
Reserved3
7
8
read-write
RESERVED4
Reserved4
16
32
read-write
START_VELOCITY_CNTR
Starting the velocity counter. It is self reset bit.
11
12
read-write
TIMER_MODE
NONE
10
11
read-write
Disable
Quadrature encoder mode
0
Enable
timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively
1
CTRL_SET_REG
Quadrature Encoder control set register
0x4
32
read-write
n
0x0
0x0
DIGITAL_FILTER_BYPASS
NONE
9
10
read-write
Disable
digital filter is in-path for all input signals
0
Enable
digital filter is bypassed for all input signals (position A, position B and Index)
1
INDEX_CNT_RST
1= index counter is going to reset.
15
16
read-write
INDEX_CNT_RST_EN
Index count reset enable
8
9
read-write
Disable
NONE
0
Enable
index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register.
1
POS_CNT_DIRECTION_CTRL
NONE
4
5
read-write
Disable
position B pin defines the direction of position counter
0
Enable
pos_cnt_dir_frm_reg defines the position counter direction
1
POS_CNT_DIR_FRM_REG
Position Counter Direction indication from user
5
6
read-write
Disable
Position counter direction is negative (-)
0
Enable
Position counter direction is positive (+)
1
POS_CNT_RST
1=position counter is going to reset
14
15
read-write
POS_CNT_RST_WITH_INDEX_EN
Phase A and Phase B Input Swap Select bit
2
3
read-write
Disable
position counter is getting reset after reaching max count, which is mentioned in position_max_cnt
0
Enable
position counter is getting reset for every index pulse
1
QEI_POS_CNT_16_BIT_MODE
Qei position counter 16 bit mode enable
13
14
read-write
Disable
No effect
0
Enable
QEI position status counter will be working as a 16 bit counter
1
QEI_SFT_RST
Quadrature encoder soft reset. It is self reset signal.
0
1
read-only
QEI_STOP_IN_IDLE
NONE
12
13
read-write
Disable
QEI position status counter is working as 32 bit counter.
0
Enable
QEI position status counter is working as 16 bit counter
1
QEI_SWAP_PHASE_AB
Phase A and Phase B Input Swap Select bit
1
2
read-write
Disable
Phase A and Phase B inputs are not swapped
0
Enable
Phase A and Phase B inputs are swapped
1
RESERVED1
Reserved1
3
4
read-write
RESERVED2
Reserved2
6
7
read-write
RESERVED3
Reserved3
7
8
read-write
RESERVED4
Reserved4
16
32
read-write
START_VELOCITY_CNTR
Starting the velocity counter. It is self reset bit.
11
12
read-write
TIMER_MODE
NONE
10
11
read-write
Disable
Quadrature encoder mode
0
Enable
timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively.
1
DELTA_TIME_REG
Quadrature Delta time register
0x3C
32
read-write
n
0x0
0x0
DELTA_TIME_FOR_VELOCITY
Delta time LSW to compute velocity
0
20
read-write
RESERVED1
Reserved1
20
32
read-write
INDEX_CNT_REG
Quadrature Encoder index counter register
0x10
32
read-write
n
0x0
0x0
QEI_INDEX_CNT
Index counter value.User can initialize/change the index counter using this register
0
16
read-write
RESERVED1
Reserved1
16
32
read-write
INDEX_MAX_CNT_REG
Quadrature Encoder maximum index counter value register
0x14
32
read-write
n
0x0
0x0
QEI_INDEX_MAX_CNT
This is a maximum count value that is allowed to increment in the index counter. If index counter reaches this value, will get reset to zero
0
32
read-write
INTR_ACK_REG
Quadrature Encoder interrupt acknowledge register
0x2C
32
read-write
n
0x0
0x0
POSITION_CNTR_ERR_INTR_LEV
Position_cntr_err_intr_ack
2
3
read-write
Disable
No effect.
0
Enable
Position cntr err intr will be cleared.
1
QEI_INDEX_CNT_MATCH_INTR_LEV
NONE
1
2
read-write
Disable
No effect.
0
Enable
Qei index cnt match intr will be cleared.
1
QEI_POSITION_CNT_MATCH_INTR_LEV
Qei_position_cnt_match_intr_ack
4
5
read-write
Disable
No effect.
0
Enable
Qei position cnt match intr will be cleared.
1
QEI_POSITION_CNT_RESET_INTR_LEV
Qei_position_cnt_reset_intr_ack
0
1
read-write
Disable
No effect.
0
Enable
Qei position cnt reset intr will be cleared.
1
RESERVED1
Reserved1
6
32
read-write
VELOCITY_COMPUTATION_OVER_INTR_LEV
Velocity_computation_over_intr_ack
5
6
read-write
Disable
No effect.
0
Enable
Velocity computation is over intr will be cleared.
1
VELOCITY_LESS_THAN_INTR_LEV
Velocity_less_than_intr_ack
3
4
read-write
Disable
No effect.
0
Enable
Velocity less than intr will be cleared
1
INTR_MASK_REG
Quadrature Encoder interrupt mask register
0x30
32
read-write
n
0x0
0x0
POSITION_CNTR_ERR_INTR_MASK
Position_cntr_err_intr_mask
2
3
read-write
Disable
If read : Position cntr err intr is not given on qei_intr pin. If write: No effect
0
Enable
If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin
1
QEI_INDEX_CNT_MATCH_INTR_MASK
Qei_index_cnt_match_intr_mask
1
2
read-write
Disable
If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect
0
Enable
If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin.
1
QEI_POSITION_CNT_MATCH_INTR_MASK
Qei_position_cnt_match_intr_mask
4
5
read-write
Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
0
Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
1
QEI_POSITION_CNT_RESET_INTR_MASK
Qei_position_cnt_reset_intr_mask
0
1
read-write
Disable
If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect
0
Enable
If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin
1
RESERVED1
Reserved1
6
32
read-write
VELOCITY_COMPUTATION_OVER_INTR_MASK
Velocity_computation_over_intr_mask
5
6
read-write
Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
0
Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
1
VELOCITY_LESS_THAN_INTR_MASK
Velocity_less_than_intr_mask
3
4
read-write
Disable
If read : Velocity less than intr is not given on qei_intr pin. If write: No effect
0
Enable
If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin.
1
INTR_STS_REG
Quadrature Encoder interrupt status register
0x28
32
read-only
n
0x0
0x0
POSITION_CNTR_ERR_INTR_LEV
Whenever number of possible positions are mismatched with actual positions are received between two index pulses this will raised
2
3
read-only
QEI_INDEX_CNT_MATCH_INTR_LEV
This is raised when index counter reaches max value loaded in to index_max_cnt register.
1
2
read-only
QEI_POSITION_CNT_MATCH_INTR_LEV
This is raised when the position counter reaches position match value, which is programmable.
4
5
read-only
QEI_POSITION_CNT_RESET_INTR_LEV
This is raised when the position counter reaches it's extremes
0
1
read-only
QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV
When velocity count is computed for given delta time, than interrupt is raised.
5
6
read-only
RESERVED1
Reserved1
6
32
read-only
VELOCITY_LESS_THAN_INTR_LEV
When velocity count is less than the value given in velocity_value_to_compare register, interrupt is raised
3
4
read-only
INTR_UNMASK_REG
Quadrature Encoder interrupt unmask register
0x34
32
read-write
n
0x0
0x0
POSITION_CNTR_ERR_INTR_UNMASK
Position_cntr_err_intr_unmask
2
3
read-write
Disable
If read : Position cntr err intr is not given on qei_intr pin. If write: No effect
0
Enable
If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin
1
QEI_INDEX_CNT_MATCH_INTR_UNMASK
Qei_index_cnt_match_intr_unmask
1
2
read-write
Disable
If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect
0
Enable
If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin.
1
QEI_POSITION_CNT_MATCH_INTR_UNMASK
Qei_position_cnt_match_intr_unmask
4
5
read-write
Disable
If read :Qei position cnt match intr is given on qei_intr pin If write: No effect
0
Enable
If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin
1
QEI_POSITION_CNT_RESET_INTR_UNMASK
Qei_position_cnt_reset_intr_unmask
0
1
read-write
Disable
If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect
0
Enable
If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin
1
RESERVED1
Reserved1
5
32
read-write
VELOCITY_LESS_THAN_INTR_UNMASK
Velocity_less_than_intr_unmask
3
4
read-write
Disable
If read : Velocity less than intr is not given on qei_intr pin. If write: No effect
0
Enable
If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin.
1
POSITION_CNT_REG
Quadrature Encoder position counter register
0x18
32
read-write
n
0x0
0x0
QEI_POSITION_CNT_WR_VALUE
This is used to program/change the value of position counter status.In 16-bit mode, only the lower 16 bits are used.
0
32
read-write
POSITION_MATCH_REG
Quadrature position match register
0x4C
32
read-write
n
0x0
0x0
POSTION_MATCH_VALUE
Position match value to compare the position counter.
0
32
read-write
POSITION_MAX_CNT_REG
Quadrature Encoder maximum position counter value register
0x20
32
read-write
n
0x0
0x0
QEI_POSITION_MAX_CNT
This is a maximum count value that is allowed to increment in the position counter.
0
32
read-write
STATUS_REG
Quadrature Encoder status register
0x0
32
read-only
n
0x0
0x0
POSITION_CNTR_DIRECTION
Position Counter Direction Status bit
4
5
read-only
Disable
Position counter direction is negative (-)
0
Enable
Position counter direction is positive (+)
1
POSITION_CNTR_ERR
Count Error Status Flag bit
3
4
read-only
QEI_INDEX
This is a direct value from the position signal generator
0
1
read-only
QEI_POSITION_A
This is a direct value from the position signal generator.Value refers to the signal Position_A from the generator.
2
3
read-only
QEI_POSITION_B
This is a direct value from the position signal generator.Value refers to the signal Position_B from the generator.
1
2
read-only
RESERVED1
Reserved1
5
32
read-only
VELOCITY_REG
Quadrature velocity register
0x44
32
read-write
n
0x0
0x0
VELOCITY_VALUE_TO_COMPARE
For read operation :It is the velocity count to compare using TA firmware For write operation :It is the velocity value to compare with velocity count
0
32
read-write
RTC
The MCU RTC acts as RTC with time in seconds, minutes, hours, days, months, years and centuries
MCU_RTC
0x0
0x1C
0x28
registers
n
MCU_RTC
29
MCU_CAL_ALARM_PROG_1
MCU calender alarm prog register 1
0x1C
32
read-write
n
0x0
PROG_ALARM_HOUR
hours value of alarm time
22
27
read-write
PROG_ALARM_MIN
mins value of alarm time
16
22
read-write
PROG_ALARM_MSEC
milli seconds value of alarm time
0
10
read-write
PROG_ALARM_SEC
seconds value of alarm time
10
16
read-write
RESERVED1
reser
27
32
read-only
MCU_CAL_ALARM_PROG_2
MCU calender alarm prog register 2
0x20
32
read-write
n
0x0
ALARM_EN
alarm function enable for calendar
31
32
read-write
PROG_ALARM_CENTURY
century count in alarm time
23
25
read-write
PROG_ALARM_DAY
day count in alarm time 1-31
0
5
read-write
PROG_ALARM_MONTH
month count in alarm time
8
12
read-write
PROG_ALARM_YEAR
year count in alarm time 0 - 99
16
23
read-write
RESERVED1
reser
5
8
read-only
RESERVED2
reser
12
16
read-only
RESERVED3
reser
25
31
read-only
MCU_CAL_KEY_EANBLE
MCU calendar key enable
0x40
32
write-only
n
0x0
RTC_KEY
enable access to program Watch dog registers
0
32
write-only
MCU_CAL_POWERGATE_REG
MCU calender powergate register
0x24
32
read-write
n
0x0
ENABLE_CALENDER_COMBI
Enable calender combitional logic block
1
2
read-write
PG_EN_CALENDER
Start calender block
0
1
read-write
RES
reser
2
32
read-only
MCU_CAL_PROG_TIME_1
MCU calendar prog time 1 register
0x28
32
read-write
n
0x0
PROG_HOUR
hours value to be programmed to real time in calendar when pro_time_trig is 1
22
27
read-write
PROG_MIN
minutes value to be programmed to real time in calendar when pro_time_trig is 1
16
22
read-write
PROG_MSEC
Milli seconds value to be programmed to real time in calendar when pro_time_trig is 1
0
10
read-write
PROG_SEC
seconds value to be programmed to real time in calendar when pro_time_trig is 1
10
16
read-write
RESERVED2
reser
27
32
read-only
MCU_CAL_PROG_TIME_2
MCU calendar prog time 2 register
0x2C
32
read-write
n
0x0
PROG_CENTURY
century value to be programmed to real time in calendar when pro_time_trig is 1
23
25
read-write
PROG_DAY
day count value to be programmed to real time in calendar when pro_time_trig is 1
0
5
read-write
PROG_MONTH
month value to be programmed to real time in calendar when pro_time_trig is 1
8
12
read-write
PROG_TIME_TRIG
load the programmed to the real time in calendar block
31
32
write-only
PROG_WEEK_DAY
program which week day it is
5
8
read-write
PROG_YEAR
year value to be programmed to real time in calendar when pro_time_trig is 1
16
23
read-write
RES
reser
12
16
read-only
RESERVED1
reser
25
31
read-only
MCU_CAL_READ_COUNT_TIMER
MCU calendar read count timer
0x38
32
read-write
n
0x0
READ_COUNT_TIMER
Read timer which increments by time period value to reach to count milliseconds
0
27
read-only
RESERVED1
reser
27
32
read-only
MCU_CAL_READ_TIME_LSB
MCU calendar read time lsb
0x34
32
read-write
n
0x0
DAYS_COUNT
days count
27
32
read-write
HOURS_COUNT
hours count
22
27
read-write
MILLISECONDS_COUNT
milliseconds count
0
10
read-write
MINS_COUNT
mins count
16
22
read-write
SECONDS_COUNT
seconds count
10
16
read-write
MCU_CAL_READ_TIME_MSB
MCU calendar read time msb
0x30
32
read-write
n
0x0
CENTURY_COUNT
century count
14
16
read-write
MONTHS_COUNT
months count
3
7
read-write
RESERVED1
reser
16
32
read-only
WEEK_DAY
week day
0
3
read-write
YEAR_COUNT
years count
7
14
read-write
MCU_CAL_SLEEP_CLK_COUNTERS
MCU calendar sleep clock counter
0x3C
32
read-write
n
0x0
PCLK_COUNT_WRT_SLEEP_CLK
no. of APB clks in 1 sleep clock duration
16
28
read-only
RESERVED1
reser
12
16
read-only
RESERVED2
reser
28
32
read-only
SLEEP_CLK_DURATION
No of sleep clks with respect to APB clock so far from the posedge of sleep clk
0
12
read-only
SHMIC
The SD or SDIO or MMC Host Controller (SMIHC) is compatible with Standard SD Host 3.0 and eMMC5.0 Specification. The SMIHC supports three key interfaces (SD memory, SDIO and eMMC)
SHMIC
0x0
0x0
0x102
registers
n
SMIH_ADMA_ERROR_STATUS_REGISTER
ADMA Error Status Register
0x54
32
read-only
n
0x0
ADMA_ERROR_STATE
This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state.
0
2
read-only
ST_STOP
Stop DMA
0
ST_FDS
Fetch Descriptor
1
ST_TFR
Transfer Data
3
ADMA_LENGHT_MISMATCH_ERROR
While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length.
2
3
read-only
No_Error
No ADMA Length Mismatch Error
0
Error
ADMA Length Mismatch Error
1
RESERVED1
Reserved1
3
32
read-only
SMIH_ADMA_SYSTEM_ADDRESS0_REGISTER
ADMA System Address0 Register
0x58
16
read-write
n
0x0
SMIH_ADMA_SYSTEM_ADDRESS1_REGISTER
ADMA System Address1 Register
0x5A
16
read-write
n
0x0
SMIH_ADMA_SYSTEM_ADDRESS2_REGISTER
ADMA System Address2 Register
0x5C
16
read-write
n
0x0
SMIH_ADMA_SYSTEM_ADDRESS3_REGISTER
ADMA System Address3 Register
0x5E
16
read-write
n
0x0
SMIH_AHB_BURST_SIZE_REGISTER
AHB Burst Size Register
0xEC
16
read-write
n
0x0
AHB_MASTER_BURST_SIZE_REGISTER
AHB Master performs Burst operations as per this register. The default Burst operations performed by SMIHC AHB Master is INCR4, INCR8 and INCR16.
0
7
read-write
RESERVED1
reserved1
7
10
read-write
RESERVED2
reserved1
10
16
read-write
SMIH_ARGUMENT1_REGISTER
Argument 1 Register
0x8
32
read-write
n
0x0
COMMAND_ARGUMENT_1
The SD command argument is specified as bit 39-8 of Command-Format in the Physical Layer Specification.
0
32
read-write
SMIH_AUTO_CMD_ERROR_STATUS_REGISTER
Auto CMD Error Status Register
0x3C
16
read-only
n
0x0
AUTO_CMD12_NOT_EXECUTED
If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12
0
1
read-only
Executed
Mask Command Timeout Error Signal
0
Not_executed
Command Timeout Error Signal Enable
1
AUTO_CMD_CRC_ERROR
This bit is set when detecting a CRC error in the command response
2
3
read-only
No_Error
No Error
0
CRC_Error
CRC Error Generated
1
AUTO_CMD_END_BIT_ERROR
This bit is set when detecting that the end bit of command response is 0.
3
4
read-only
No_Error
No Error
0
Bit_Error
End Bit Error Generated
1
AUTO_CMD_INDEX_ERROR
This bit is set if the Command Index error occurs in response to a command.
4
5
read-only
AUTO_CMD_TIME_ERROR
This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command.
1
2
read-only
No_Error
Not Auto CMD Timeout Error
0
Time_Error
Auto CMD Timeout Error
1
COMMAND_NOT_ISSUED_BY_AUTO_CMD12_ERROR
Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register.
7
8
read-only
No_Error
No Error
0
Error
Command Not Issued By Auto CMD12 Error
1
RESERVED1
reserved1
5
7
read-only
RESERVED2
reserved2
8
16
read-only
SMIH_BLOCK_COUNT_REGISTER
Block Count Register
0x6
16
read-write
n
0x0
BLOCK_COUNT_FOR_CURRENT_TRANSFER
This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers.
0
16
read-write
SMIH_BLOCK_GAP_CONTROL_REGISTER
Power Control Register
0x2A
8
read-write
n
0x0
CONTINUE_REQUEST
This bit is used to restart a transaction which was stopped using Stop At Block Gap request. To cancel stop at block gap Stop At Block Gap to Zero And set this bit to restart the transfer.
1
2
read-write
Not_affect
Not affect
0
Restart
Restart
1
INTERRUPT_AT_BLOCK_GAP
This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
3
4
read-write
Disable
Disable Read Wait Control
0
Enable
Enable Read Wait Control
1
READ_WAIT_CONTROL
The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the DAT[2] line.
2
3
read-write
Disable
Disable Read Wait Control
0
Enable
Enable Read Wait Control
1
Reserved1
Reserved1
4
8
read-write
STOP_AT_BLOCK_GAP_REQUEST
This bit is used to stop executing read and write transaction at the next block gap for non-DMA, SDMA and ADMA transfers. The Host Driver
0
1
read-write
Transfer
Transfer block gap request
0
Stop
Stop At block gap request
1
SMIH_BLOCK_SIZE_REGISTER
Block Size Register
0x4
16
read-write
n
0x0
HOST_SDMA_BUFFER_BOUNDARY
Host Driver to update the SDMA System Address register. At the end of transfer, the SMIHC Controller may issue or may not issue DMA Interrupt.
12
15
read-write
RESERVED1
Reserved1
15
16
read-write
TRANSFER_BLOCK_SIZE
This register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size
0
12
read-write
SMIH_BUFFER_DATA_PORT_REGISTER
SMIH Buffer Data Port Register
0x20
32
read-write
n
0x0
BUFFER_DATA
The SMIHC Controller buffer can be accessed through this 32-bit Data Port register.
0
32
read-write
SMIH_CAPABILITIES_REGISTER
Capabilities Register
0x40
64
read-write
n
0x0
ADMA2_SUPPORT
This bit indicates whether the SMIHC Controller is capable of using ADMA2.
25
26
read-write
ADMA2_Not_Supported
ADMA2_Not_Supported
0
ADMA2_Support
ADMA2_Support
1
BASE_CLOCK_FREQUENCY
This value indicates the base (maximum) clock frequency for the SD Clock. Definition of this field depends on Host Controller Version.
14
22
read-write
CLOCK_MULTIPLIER
CLOCK MULTIPLIER
46
54
read-write
DDR50_SUPPORT
DDR50 SUPPORT
32
33
read-write
DRIVER_TYPEA_SUPPORT
DRIVER_TYPEA SUPPORT
34
35
read-write
DRIVER_TYPEC_SUPPORT
DRIVER_TYPEC SUPPORT
35
36
read-write
DRIVER_TYPED_SUPPORT
DRIVER_TYPED SUPPORT
36
37
read-write
HIGH_SPEED_SUPPORT
This bit indicates whether the SMIHC Controller and the Host System support High Speed mode and they can supply SD Clock frequency from 25MHz to 50MHz.
27
28
read-only
HIGH_SPEED_NOT_SUPPORT
High Speed Not Supported
0
HIGH_SPEED_SUPPORT
High Speed Supported
1
HS200_SUPPORT
HS200 SUPPORT
33
34
read-write
HS400_SUPPORT
HS400 SUPPORT
37
38
read-write
MAXIMUM_BLOCK_LENGTH
This value indicates the maximum block size that the Host Driver can read and write to the buffer in the SMIHC Controller.
22
24
read-write
RESERVED1
Reserved1
6
7
read-write
RESERVED2
This bit is reserved for backward compatibility with prior specifications. If set, the SMIHC Controller is indicating that it supports legacy ADMA1 mode.
26
27
read-write
RESERVED3
RESERVED3
38
42
read-write
RESERVED4
RESERVED4
42
43
read-write
RESERVED5
Reserved5
54
64
read-write
RE_TUNNING_MODES
This field selects re-tuning method and limits the maximum data length.
44
46
read-write
SDMA_SUPPORT
This bit indicates whether the SMIHC Controller is capable of using SDMA to transfer data between system memory and the SMIHC Controller directly.
28
29
read-only
SDMA_Not_Support
SDMA Not Supported
0
SDMA_Support
SDMA Supported
1
SDR104_SUPPORT
SDR104 SUPPORT
31
32
read-write
SDR50_SUPPORT
SDR50 SUPPORT
30
31
read-write
SUSPEND_RESUME_SUPPORT
This bit indicates whether the SMIHC Controller does not supports Suspend or Resume functionality.
29
30
read-write
Not_Support
Not Support Suspend or Resume
0
Support
Suspend or Resume Support
1
TIMEOUT_CLOCK_FREQUENCY
This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock Unit defines the unit of this field's value.
0
6
read-write
TIMEOUT_CLOCK_UNIT
This bit shows the unit of base clock frequency used to detect Data Timeout Error.
7
14
read-write
USE_TUNING_FOR_SDR50
As this bit is set to 1, before using the SDR50 mode, the tuning procedure at the initialization sequence will be executed regardless of Re-Tuning Modes state in the Capabilities register.
43
44
read-write
_8BIT_SUPPORT_FOR_EMDDED_DEVICE
This bit indicates whether the SMIHC Controller is capable of using 8-bit bus width mode. This bit is not effective when slot Type is set to 10b.
24
25
read-write
8_BIT_BUS_Width_Not_Supported
8-bit Bus Width Not Supported
0
8_BIT_BUS_Width_Supported
8-bit Bus Width Supported
1
SMIH_CLOCK_CONTROL_REGISTER
Clock Control Register
0x2C
16
read-write
n
0x0
CLOCK_GENERATOR_SELECT
This bit is used to select the clock generator mode in SDCLK Frequency select
5
6
read-write
INTERNAL_CLOCK_ENABLE
This bit is set to 0 when the Host Driver is not using the SMIHC Controller or the SMIHC Controller awaits a wakeup interrupt.
0
1
read-write
Disable
Disable internal Clock
0
Enable
Enable internal Clock
1
INTERNAL_CLOCK_STABLE
This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1.
1
2
read-write
Disable
Disable Internal Clock Stable
0
Enable
Enable internal Clock Stable
1
Reserved1
Reserved1
3
5
read-write
SDCLK_FREQUENCY_SELECT
This register is used to select the frequency of SDCLK pin.
8
16
read-write
SD_CLOCK_ENABLE
The SMIHC Controller shall stop SDCLK when writing this bit to 0.
2
3
read-write
Disable
Disable SD Clock
0
Enable
Enable SD Clock
1
UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT
PE_SMIH Controller shall support these bits to expand SDCLK Frequency Select to 10-bit
6
8
read-write
SMIH_COMMAND_REGISTER
Command Register
0xE
16
read-write
n
0x0
COMMAND_CRC_CHECK_ENABLE
If this bit is set to 1, the SMIHC Controller shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error.
3
4
read-write
Disable
Disable the command CRC check
0
Enable
Enable the command CRC check
1
COMMAND_INDEX
These bits shall be set to the command number (CMD0-63, ACMD0-63) that is specified in bits 45-40 of the Command-Format in the Physical Layer Specification
8
14
read-write
COMMAND_INDEX_CHECK_ENABLE
If this bit is set to 1, the SMIHC Controller shall check the Index field in the response to see if it has the same value as the command index.
4
5
read-write
Disable
Disable the command index check
0
Enable
Enable the command index check
1
COMMAND_TYPE
There are three types of special commands like Suspend, Resume and Abort. These bits shall be set to 00b for all other commands.
6
8
read-write
Normal
Normal Other commands
0
Suspend
Suspend CMD52 for writing Bus Suspend in CCCR
1
Resume
Resume CMD52 for writing Function Select in CCCR
2
Abort
Abort CMD12,MD52 for writing I/O Abort in CCCR
3
DATA_PRESENT_SELECT
This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line.
5
6
read-write
Absent
Data absent
0
Present
Data present
1
RESERVED1
RESERVED1
2
3
read-write
RESERVED2
RESERVED2
14
16
read-write
RESPONSE_TYPE_SELECT
This register explain the response type select.
0
2
read-write
No_response
No Response
0
Length_136
Response Length 136
1
Length_48
Response Length 48
2
Length_48_check_busy
Response Length 48 check Busy after response
3
SMIH_DS_TUNE_REGISTER
Ds Tune Register
0xE8
32
read-write
n
0x0
AUTO_INCREMENT
Increment locally or not.
6
7
read-write
INCREMENT_TAP_POINT_VALUE
Increment value,When Auto increment bit6 is set to 1, Host controller will increment Tap point based on the value programmed in this field.
7
10
read-write
RESERVED1
reserved1
10
32
read-write
TAP_POINT_VALUE
Tap point value
0
6
read-write
SMIH_ERROR_INTERRUPT_SIGNAL_ENABLE_REGISTER
Error Interrupt Signal Enable Register
0x3A
16
read-write
n
0x0
ADMA_ERROR_SIGNAL_ENABLE
ADMA Error Signal Enable
9
10
read-write
Masked
Mask ADMA Error Signal
0
Enabled
ADMA Error Signal Enable
1
AUTO_CMD_ERROR_SIGNAL_ENABLE
Auto CMD Error Signal Enable
8
9
read-write
Masked
Mask Auto CMD Error Signal
0
Enabled
Auto CMD Error Signal Enable
1
COMMAND_CRC_ERROR_SIGNAL_ENABLE
Command CRC Error Signal Enable
1
2
read-write
Masked
Mask Command CRC Error Signal
0
Enabled
Command CRC Error Signal Enable
1
COMMAND_END_BIT_ERROR_SIGNAL_ENABLE
Command End Bit Signal Enable
2
3
read-write
Masked
Mask Command End Bit Signal
0
Enabled
Command End Bit Signal Enable
1
COMMAND_INDEX_ERROR_SIGNAL_ENABLE
Command Index Signal Enable
3
4
read-write
Masked
Mask Command index Signal
0
Enabled
Command index Signal Enable
1
COMMAND_TIMEOUT_ERROR_SIGNAL_ENABLE
Command Timeout Error Signal Enable
0
1
read-write
Masked
Mask Command Timeout Error Signal
0
Enabled
Command Timeout Error Signal Enable
1
CURRENT_LIMIT_ERROR_SIGNAL_ENABLE
Data CRC Error Signal Enable
7
8
read-write
Masked
Mask Current Limit Error Signal
0
Enabled
Current Limit Error Signal Enable
1
DATA_CRC_ERROR_SIGNAL_ENABLE
Data CRC Error Signal Enable
5
6
read-write
Masked
Mask Data CRC Error Signal
0
Enabled
Data CRC Error Signal Enable
1
DATA_END_BIT_ERROR_SIGNAL_ENABLE
Data CRC Error Signal Enable
6
7
read-write
Masked
Mask Data End Bit Error Signal
0
Enabled
Data End Bit Error Signal Enable
1
DATA_TIMEOUT_ERROR_SIGNAL_ENABLE
Data Timeout Error Signal Enable
4
5
read-write
Masked
Mask Data Timeout Error Signal
0
Enabled
Data Timeout Error Signal Enable
1
RESERVED1
reserved1
11
12
read-write
TUNING_ERROR_SIGNAL_ENABLE
Tuning Error Signal Enable
10
11
read-write
Masked
Mask Tuning Error Signal
0
Enabled
Tuning Error Signal
1
VENDOR_SPECIFIC_ERROR_STATUS_ENABLE
Vendor Specific Error Status Enable
12
16
read-write
SMIH_ERROR_INTERRUPT_STATUS_ENABLE_REGISTER
Error Interrupt Status Enable Register
0x36
16
read-write
n
0x0
ADMA_ERROR_STATUS_ENABLE
Auto CMD Error Status Enable
9
10
read-write
Masked
Mask ADMA Error Status
0
Enabled
ADMA Error Status Enable
1
AUTO_CMD_ERROR_STATUS_ENABLE
Auto CMD Error Status Enable
8
9
read-write
Masked
Mask Auto CMD Error Status
0
Enabled
Auto CMD Error Status Enable
1
COMMAND_CRC_ERROR_STATUS_ENABLE
Command Timeout Error Status Enable
1
2
read-write
Masked
Mask Command CRC Error Status
0
Enabled
Enable Command CRC Error Status Enable
1
COMMAND_END_BIT_ERROR_STATUS_ENABLE
Command Timeout Error Status Enable
2
3
read-write
Masked
Mask Command End Bit Error Status
0
Enabled
Enable Command End Bit Error Status Enable
1
COMMAND_INDEX_ERROR_STATUS_ENABLE
Command Index Error Status Enable
3
4
read-write
Masked
Mask Command Index Error Status
0
Enabled
Command Index Error Status Enable
1
COMMAND_TIMEOUT_ERROR_STATUS_ENABLE
Command Timeout Error Status Enable
0
1
read-write
Masked
Mask command timeout error status enable
0
Enabled
Enable command timeout error status enable
1
CURRENT_LIMIT_ERROR_STATUS_ENABLE
Data End Bit Error Status Enable
7
8
read-write
Masked
Mask Current Limit Error Status
0
Enabled
Current Limit Error Status Enable
1
DATA_CRC_ERROR_STATUS_ENABLE
Data Timeout Error Status Enable
5
6
read-write
Masked
Mask Data CRC Error Status
0
Enabled
Data CRC Error Status Enable
1
DATA_END_BIT_ERROR_STATUS_ENABLE
Data End Bit Error Status Enable
6
7
read-write
Masked
Mask Data End Bit Error Status
0
Enabled
Data End Bit Error Status Enable
1
DATA_TIMEOUT_ERROR_STATUS_ENABLE
Data Timeout Error Status Enable
4
5
read-write
Masked
Mask Data Timeout Error Status
0
Enabled
Command Data Timeout Error Status Enable
1
Reserved1
Reserved1
11
12
read-write
TUNING_ERROR_STATUS_ENABLE
Tuning Error Status Enable
10
11
read-write
Masked
Mask Tuning Error Status
0
Enabled
Tuning Error Status Enable
1
VENDOR_SPECIFIC_ERROR_STATUS_ENABLE
Vendor Specific Error Status Enable
12
16
read-write
SMIH_ERROR_INTERRUPT_STATUS_REGISTER
Error Interrupt Status Register
0x32
16
read-write
n
0x0
ADMA_ERROR
This bit is set when the SMIHC Controller detects errors during ADMA based data transfer.
9
10
read-write
No_Error
No ADMA Error
0
Error
ADMA Error
1
AUTO_CMD_ERROR
Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1
8
9
read-write
No_Error
No Auto CMD Error
0
Error
Auto CMD Error
1
COMMAND_CRC_ERROR
Command CRC Error is generated in two cases.
1
2
read-write
No_Error
No Error
0
CRC_error_generate
CRC error Generated
1
COMMAND_END_BIT_ERROR
This bit is set when detecting that the end bit of a command response is 0.
2
3
read-write
No_error
No command End Bit error
0
Error
End bit error generated
1
COMMAND_INDEX_ERROR
This bit is set if a Command Index error occurs in the command response.
3
4
read-write
NO_error
No Command Index Error
0
Error
Command Index Error
1
COMMAND_TIMEOUT_ERROR
This bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command.
0
1
read-write
No_error
No Error
0
Time_out
Timed out
1
CURRENT_LIMIT_ERROR
By setting the SD Bus Power bit in the Power Control register, the SMIHC Controller is requested to supply power for the SD Bus
7
8
read-write
Error
No current limit error
0
Power_fail
Current limit error
1
DATA_CRC_ERROR
Occurs when detecting CRC error when transferring read data which uses the DAT line
5
6
read-write
Not_Error
Not Data CRC Error
0
Error
Data CRC Error
1
DATA_END_BIT_ERROR
Occurs either when detecting 0 at the end bit position of read data which uses the DAT line or at the end bit position of the CRC Status.
6
7
read-write
No_Error
No data end bit error
0
Error
Data End Bit Error
1
DATA_TIMEOUT_ERROR
This bit is set when detecting one of following timeout conditions ,Busy timeout for R1b,R5b type, busy timeout after write CRC status,write CRC Status timeout,read data timeout.
4
5
read-write
Not_Error
Not data timeout error
0
Error
Data Timeout Error
1
Reserved1
Reserved1
11
16
read-write
TUNING_ERROR
This bit is set when an unrecoverable error is detected in a tuning circuit.
10
11
read-write
No_Error
No Tuning Error
0
Error
Tuning Error
1
SMIH_HOST_CONTROLLER_VERSION_REGISTER
Slot Interrupt Status Register
0xFE
16
read-only
n
0x0
SPECIFICATION_VERSION_NUMBER
This status indicates the Host Controller Spec Version,The upper and lower 4-bits indicate the version.
0
8
read-only
VENDOR_VERSION_NUMBER
This status is reserved for the vendor version number.The Host Driver should not use this status.
8
16
read-only
SMIH_HOST_CONTROL_1_REGISTER
Present State Register
0x28
8
read-write
n
0x0
CARD_DETECT_SIGNAL_SELECTION
This bit selects source for the card detection.
7
8
read-write
Normal_purpose
SDCD is selected for normal use
0
Test_purpose
The Card Detect Test Level is selected for test purpose
1
CARD_DETECT_TEST_LEVEL
This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not.
6
7
read-write
No_card
No Card
0
Card_inserte
Card Inserted
1
DATA_TRANSFER_WIDTH
This bit selects the data width of the SMIHC Controller.The Host Driver shall set it to match the data width of the SD card.
1
2
read-write
1_Bit_Mode
1-bit mode
0
4_Bit_Mode
4-bit mode
1
DMA_SELECT
One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring
3
5
read-write
SDMA_Select
High Speed mode
0
Reserved1
Reserved1
1
ADMA2_Select
ADMA2 select
2
Reserved2
Reserved2
3
EXTENDED_DATA_TRANSFER_WIDTH
This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register.
5
6
read-write
Data_transfer_width
Bus Width is Selected by Data Transfer Width
0
8bit_bus_width
8-bit Bus Width
1
HIGH_SPEED_ENABLE
This bit is optional. Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register.
2
3
read-write
Normal_Speed
Normal Speed mode
0
High_Speed
High Speed mode
1
LED_CONTROL
This bit is used to caution the user not to remove the card while the SD card is being accessed.If the software is going to issue multiple SD commands, this bit can be set during all these transactions.
0
1
read-write
LED_OFF
LED off
0
LED_ON
LED on
1
SMIH_HOST_CONTROL_2_REGISTER
Host Control 2 Register
0x3E
16
read-write
n
0x0
ASYNCHRONOUS_INTERRUPT_ENABLE
This bit can be set to 1 if a card that supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register.
14
15
read-write
Disabled
Disable Asynchronous Interrupt
0
Enabled
Asynchronous Interrupt Enable
1
DRIVER_STRENGTH_SELECT
SMIHC Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective.
4
6
read-write
Driver_type_B
Driver Type B is Selected
0
Driver_type_A
Driver Type A is Selected
1
Driver_type_C
Driver Type C is Selected
2
Driver_type_D
Driver Type D is Selected
3
EXECUTE_TUNNING
This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed.
6
7
read-write
Not_Tuned
Not Tuned or Tuning Completed
0
Execute_Tuning
Execute Tuning
1
PRESET_VALUE_ENABLE
As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver.
15
16
read-write
Disabled
SDCLK and Driver Strength are controlled by Host Driver
0
Enabled
Automatic Selection by Preset Value are Enabled
1
RESERVED1
Reserved1
9
14
read-write
SAMPLING_CLOCK_SELECT
SMIHC Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning.
7
8
read-write
Fixed_Clock
Fixed clock is used to sample data
0
Tuned_Clock
Tuned clock is used to sample data
1
SIGNALING_1_8V_ENABLE
This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V.
3
4
read-write
3.3V_SIGNALING
Enable 3.3V Signaling
0
1.8V_SIGNALING
Enable 1.8V Signaling
1
UHS_MODE_SELECT
This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1.
0
3
read-write
SDR_12
SDR 12 UHS mode select
0
SDR_25
SDR 25 UHS mode select
1
SDR_50
SDR 50 UHS mode select
2
SDR_104
SDR 104 UHS mode select
3
DDR_50
DDR 50 UHS mode select
4
HS400
HS400 UHS mode select
5
Reserved1
Reserved1
6
Reserved2
Reserved2
7
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 04-05 bits of Drive Strength select.
8
9
read-write
SMIH_MAXIMUM_CURRENT_CAPABILITIES_REGISTER
Capabilities Register
0x48
64
read-write
n
0x0
SMIH_NORMAL_INTERRUPT_SIGNAL_ENABLE_REGISTER
Normal Interrupt Signal Enable Register
0x38
16
read-write
n
0x0
BLCOK_GAP_EVENT_SIGNAL_ENABLE
Block Gap Event Signal Enable
2
3
read-write
Masked
Mask Block Gap Event Signal
0
Enabled
Block Gap Event Signal Enable
1
BOOT_ACK_COMPLETE_INTERRUPT_SIGNAL_ENABLE
Boot Ack Complete Interrupt Signal Enable
13
14
read-only
BOOT_DONE_INTERRUPT_SIGNAL_ENABLE
Boot Ack Complete Interrupt Signal Enable
14
15
read-only
BUFFER_READ_READY_SIGNAL_ENABLE
Buffer Read Ready Signal Enable
5
6
read-write
Masked
Mask Buffer Read Ready Signal
0
Enabled
Buffer Read Ready Signal Enable
1
BUFFER_WRITE_READY_SIGNAL_ENABLE
Buffer Write Ready Signal Enable
4
5
read-write
Masked
Mask Buffer Write Ready Signal
0
Enabled
Buffer Write Ready Signal Enable
1
CARD_INSERTION_SIGNAL__ENABLE
Card Insertion Signal Enable
6
7
read-write
Masked
Mask Card Insertion Signal
0
Enabled
Card Insertion Signal Enable
1
CARD_INTERRUPT_SIGNAL_ENABLE
Card Interrupt Signal Enable
8
9
read-write
Masked
Mask Card Interrupt Signal
0
Enabled
Card Interrupt Signal Enable
1
CARD_REMOVAL_SIGNAL__ENABLE
Card Insertion Signal Enable
7
8
read-write
Masked
Mask Card Removal Signal
0
Enabled
Card Removal Signal Enable
1
COMMAND_COMPLETE_SIGNAL_ENABLE
Command Complete Signal Enable
0
1
read-write
Masked
Mask Command Complete Signal Enable
0
Enabled
Command Complete Signal Enable
1
DMA_INTERRUPT_SIGNAL_ENABLE
DMA Interrupt Signal Enable
3
4
read-write
Masked
Mask DMA Interrupt Signal
0
Enabled
DMA Interrupt Signal Enable
1
FIXED_TO_0
The Host Driver shall control error interrupts using the Error Interrupt Signal Enable register.
15
16
read-only
INT_A_SIGNAL_ENABLE
INT_A Signal Enable
9
10
read-write
Masked
Mask INT_A Signal
0
Enabled
INT_A Signal Enable
1
INT_B_SIGNAL_ENABLE
INT_B Signal Enable
10
11
read-write
Masked
Mask INT_B Signal
0
Enabled
INT_B Signal Enable
1
INT_C_SIGNAL_ENABLE
INT_C Signal Enable
11
12
read-write
Masked
Mask INT_C Signal
0
Enabled
INT_C Signal Enable
1
RE_TUNNING_EVENT_SIGNAL_ENABLE
Re-Tuning Event Signal Enable
12
13
read-write
Masked
Mask Re-Tuning Event Signal
0
Enabled
Re-Tuning Event Signal Enable
1
TRANSFER_COMPLETE_SIGNAL_ENABLE
Command Complete Signal Enable
1
2
read-write
Masked
Mask Transfer Complete Signal
0
Enabled
Transfer Complete Signal Enable
1
SMIH_NORMAL_INTERRUPT_STATUS_ENABLE_REGISTER
Normal Interrupt Status Enable Register
0x34
16
read-write
n
0x0
BLOCK_GAP_EVENT_STATUS_ENABLE
Command Complete Status Enable
2
3
read-write
Masked
mask the block gap event status
0
Enabled
enable block gap event status
1
BOOT_ACK_COMPLETE_INTERRUPT_STATUS_ENABLE
If this bit is set to 0, the SMIHC Controller shall clear interrupt request to the System
13
14
read-write
Masked
Mask Boot Ack Complete Interrupt Status Enable
0
Enabled
Boot Ack Complete Interrupt Status Enable
1
BOOT_DONE_INTERRUPT_STATUS_ENABLE
Boot Done Interrupt Status Enable
14
15
read-write
Masked
Masked Boot Done Interrupt Status Enable
0
Enabled
Boot Done Interrupt Status Enable
1
BUFFER_READ_READY_STATUS_ENABLE
Buffer Read Ready Status Enable
5
6
read-write
Masked
Mask Buffer Read Ready Status
0
Enabled
Buffer Read Ready Status Enable
1
BUFFER_WRITE_READY_STATUS_ENABLE
DMA Interrupt Status Enable
4
5
read-write
Masked
Mask Buffer Write Ready Status
0
Enabled
Buffer Write Ready Status Enable
1
CARD_INSERTION_STATUS_ENABLE
Card Insertion Status Enable
6
7
read-write
Masked
Mask Card Insertion Status Enable
0
Enabled
Card Insertion Status Enable
1
CARD_INTERRUPT_STATUS_ENABLE
If this bit is set to 0, the SMIHC Controller shall clear interrupt request to the System
8
9
read-write
Masked
Mask Card Interrupt Status
0
Enabled
Card Interrupt Status Enable
1
CARD_REMOVAL_STATUS_ENABLE
Card Insertion Status Enable
7
8
read-write
Masked
Mask Card Removal Status
0
Enabled
Card Removal Status Enable
1
COMMAND_COMPLETE_STATUS_ENABLE
Command Complete Status Enable
0
1
read-write
Masked
mask command status
0
Enabled
enable command status
1
DMA_INTERRUPT_STATUS_ENABLE
DMA Interrupt Status Enable
3
4
read-write
Masked
mask DMA interrupt status
0
Enabled
DMA Interrupt Status Enable
1
FIXED_TO_0
The Host Driver shall control error interrupts using the Error Interrupt Status Enable register.
15
16
read-only
INT_A_STATUS_ENABLE
The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
9
10
read-write
INT_B_STATUS_ENABLE
The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
10
11
read-write
INT_C_STATUS_ENABLE
The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
11
12
read-write
RETUNING_EVENT_STATUS_ENABLE
Re-Tuning Event Status enable
12
13
read-write
TRANSFER_COMPLETE_STATUS_ENABLE
Command Complete Status Enable
1
2
read-write
Masked
mask the transfer complete status
0
Enabled
enable Transfer Complete Status
1
SMIH_NORMAL_INTERRUPT_STATUS_REGISTER
Normal Interrupt Status Register
0x30
16
read-write
n
0x0
BLOCK_GAP_EVENT
If the Stop At Block Gap Request in the Block Gap Control register is set, this bit is set when both a read or write transaction is stopped at a block gap.
2
3
read-write
No_block_gap_event
No Block Gap Event
0
Transaction_stop
Transaction stopped at block gap
1
BOOT_ACK_COMPLETE_INTERRUPT
This status is set if Re-Tuning Request in the Present State register changes from 0 to 1.
13
14
read-write
NOT_ACK
Boot Mode or Alternate Boot Mode Operation is in Progress
0
ACK
Boot Mode or Alternate Boot Mode Operation is Done
1
BOOT_DONE_INTERRUPT
boot acknowledge interrupt
14
15
read-write
Progress
Boot mode or alternate boot mode operation is in Progress
0
Done
Boot mode or alternate Boot Mode Operation is Done
1
BUFFER_READ_READY
This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer Read Enable in the Present State register
5
6
read-write
Not_Ready
Not ready to read buffer
0
Ready
Ready to read buffer
1
BUFFER_WRITE_READY
This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer Write Enable in the Present State register.
4
5
read-write
Not_Ready
Not ready to write buffer
0
Ready
Ready to write buffer
1
CARD_INSERTION
This status is set if the Card Inserted in the Present State register changes from 0 to 1.
6
7
read-write
Card_Not_inserte
Card state stable or Debouncing
0
Card_inserte
Card inserted
1
CARD_INTERRUPT
interrupt signal from the SD card and the interrupt to the Host System.
8
9
read-only
CARD_REMOVAL
This status is set if the Card Inserted in the Present State register changes from 1 to 0
7
8
read-write
Card_state_stable
Card state stable or Debouncing
0
Card_removal
Card removed
1
COMMAND_COMPLETE
This bit is set when get the end bit of the command response. Auto CMD12 and Auto CMD23 consist of two responses.
0
1
read-write
No_command_complete
No Command complete
0
Command_complete
Complete command
1
DMA_INTERRUPT
This status is set if the SMIHC Controller detects the Host SDMA Buffer boundary during transfer.
3
4
read-write
NO_DMA_interrupt
No DMA Interrupt
0
DMA_interrupt
DMA Interrupt is generated
1
ERROR_INTERRUPT
If any of the bits in the Error Interrupt Status register are set, then this bit is set.
15
16
read-only
INT_A
This status is set if INT_A is enabled and INT_A pin is in low level.
9
10
read-only
INT_B
This status is set if INT_B is enabled and INT_B pin is in low level.
10
11
read-only
INT_C
This status is set if INT_C is enabled and INT_C pin is in low level.
11
12
read-only
RE_TUNING_EVENT
This status is set if Re-Tuning Request in the Present State register changes from 0 to 1.
12
13
read-only
TRANSFER_COMPLETE
This bit is set when a read / write transfer and a command with busy is completed.
1
2
read-write
No_command_complete
Not completed
0
Command_complete
Command execution is completed
1
SMIH_POWER_CONTROL_REGISTER
Power Control Register
0x29
8
read-write
n
0x0
Reserved1
Reserved1
6
8
read-write
SD_BUS_POWER
Before setting this bit, the SD Host Driver shall set SD Bus Voltage Select. If the SMIHC Controller detects the No Card state, this bit shall be cleared.
0
1
read-write
POWER_OFF
Power off
0
POWER_ON
Power on
1
SD_BUS_VOLTAGE_SELECT
By setting these bits, the Host Driver selects the voltage level for the SD card. Before setting this register, the Host Driver shall check the Voltage.
1
4
read-write
POWER_OFF
Power off
0
3.3V
Power on
1
SMIH_OD_PP
This bit is used only in MMC mode.
4
5
read-write
Open_Drain_mode
Open Drain Mode
0
Push_pull_mode
Push Pull Mode
1
SMIH_RST_N
External Hardware reset, used only in MMC mode
5
6
read-write
SMIH_PRESENT_STATE_REGISTER
Present State Register
0x24
32
read-write
n
0x0
BUFFER_READ_ENABLE
This status is used for non-DMA read transfers. The SMIHC Controller may implement multiple buffers to transfer data efficiently. This read only flag indicates that valid data exists in the host side.
11
12
read-only
Disable
Read disable
0
Enable
Read enable
1
BUFFER_WRITE_ENABLE
This status is used for non-DMA write transfers.The SMIHC Controller can implement multiple buffers to transfer data efficiently. This read only flag indicates if space is available for write data.
10
11
read-only
Disable
Write disable
0
Enable
Write enable
1
CARD_DETECT_PIN_LEVEL
This bit reflects the inverse value of the SDCD pin.Debouncing is not performed on this bit. This bit may be valid when Card State Stable is set to 1, but it is not guaranteed because of propagation delay.
18
19
read-only
CARD_INSERTED
This bit indicates whether a card has been inserted. The SMIHC Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
16
17
read-only
Reset
Reset or De bouncing
0
Card_inserted
Inserted
1
CARD_STATE_STABLE
This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is stable.
17
18
read-only
CMD_LINE_SIGNAL_LEVEL
This status is used to check the CMD line level to recover from errors and for debugging.
24
25
read-only
COMMAND_INHIBIT_CMD
If this bit is 0, it indicates the CMD line is not in use and the SMIHC, Controller can issue a SD Command using the CMD line. This bit is set immediately after the Command register (00Fh) is written.
0
1
read-only
Can_issue_command
Can issue command using only CMD line
0
Cannot_issue_command
Cannot issue command
1
COMMAND_INHIBIT_DAT
This status bit is generated if either the DAT Line Active or the Read Transfer Active is set to 1., If this bit is 0, it indicates the SMIHC Controller can issue the next SD Command Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
1
2
read-only
Can_issue_command
Can issue command which uses the DAT line
0
Cannot_issue_command
Cannot issue command which uses the DAT line
1
DAT_LINE_ACTIVE
This bit indicates whether one of the DAT line on SD Bus is in use.
2
3
read-only
DAT_Line_Inactive
DAT Line Inactive
0
DAT_Line_Active
DAT Line Active
1
DAT_LINE_SIGNAL_LEVEL
This status is used to check the DAT line level to recover from errors and for debugging.
20
24
read-only
READ_TRANSFER_ACTIVE
This status is used for detecting completion of a read transfer.
9
10
read-only
Disable
Write disable
0
Enable
Write enable
1
Reserved1
Reserved1
4
8
read-only
Reserved2
Reserved2
12
16
read-write
Reserved3
Reserved3
19
20
read-write
Reserved4
Reserved4
25
32
read-write
RE_TUNING_REQUEST
Re-Tuning Request.
3
4
read-only
WRITE_TRANSFER_ACTIVE
This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the SMIHC Controller..
8
9
read-only
Not_valid_data
No valid data
0
Transfer_data
Transferring Data
1
SMIH_PRESET_VALUE_REGISTER0
Preset Value for Initialization register
0x60
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER1
Preset Value for Initialization register
0x62
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER2
Preset Value for Initialization register
0x64
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER3
Preset Value for Initialization register
0x66
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER4
Preset Value for Initialization register
0x68
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER5
Preset Value for Initialization register
0x6A
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER6
Preset Value for Initialization register
0x6C
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_PRESET_VALUE_REGISTER7
Preset Value for Initialization register
0x6E
16
read-only
n
0x0
CLOCK_GENERATOR_SELECT_VALUE
This bit is effective when Host Controller supports programmable clock generator
10
11
read-only
Compatible_Clock
Host Controller Ver2.00 Compatible Clock Generator
0
Programmable_Clock
Programmable Clock Generator
1
DRIVER_STRENGTH_SELECT_VALUE
Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling.
14
16
read-only
Driver_Type_B
Driver Type B is Selected
0
Driver_Type_A
Driver Type A is Selected
1
Driver_Type_C
Driver Type C is Selected
2
Driver_Type_D
Driver Type D is Selected
3
RESERVED1
reserved1
11
13
read-only
SDCLK_FREQUENCY_SELECT_VALUE
10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
0
10
read-only
UPPER_BIT_OF_DRIVER_STRENGTH_SELECT
This bit reflects the SMIH_DRIVE_STRENGTH2 in association with 14-15 bits of Drive Strength select
13
14
read-only
SMIH_RESPONSE_REGISTER0
Response Register
0x10
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER1
Response Register
0x12
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER2
Response Register
0x14
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER3
Response Register
0x16
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER4
Response Register
0x18
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER5
Response Register
0x1A
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER6
Response Register
0x1C
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RESPONSE_REGISTER7
Response Register
0x1E
16
read-only
n
0x0
COMMAND_RESPONSE
This regISter refers to a bit range within the response data as transmitted on the SD Bus, REP refers to a bit range within the Response register.
0
16
read-only
SMIH_RX_TUNE_REGISTER
Rx Tune Register
0xE4
32
read-write
n
0x0
AUTO_INCREMENT
Increment locally or not.
6
7
read-write
INCREMENT_TAP_POINT_VALUE
Increment value,When Auto increment bit6 is set to 1, Host controller will increment Tap point based on the value programmed in this field.
7
10
read-write
RESERVED1
reserved1
10
32
read-write
TAP_POINT_VALUE
Tap point value
0
6
read-write
SMIH_SDH_REVISION_ID_REGISTER
SDH Revision ID Register
0xF4
32
read-only
n
0x0
MAINTENANCE
Minor BUG Fixes in HW alone
16
24
read-only
MAJOR
Both SW and HW changes required
0
8
read-only
MINOR
HW Changes alone No Software Changes required
8
16
read-only
RESERVED1
reserved1
24
32
read-only
SMIH_SDMA_SYSTEM_ADDRESS_REGISTER
SDMA System Address Register
0x0
32
read-write
n
0x0
SDMA_SYSTEM_ADDRESS_OR_ARGUMENT_2
This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23.
0
32
read-write
SMIH_SLOT_INTERRUPT_STATUS_REGISTER
Slot Interrupt Status Register
0xFC
16
read-write
n
0x0
INTERRUPT_SIGNAL_FOR_A_SLOT
This status bit indicates the logical OR of Interrupt Signal and Wakeup Signal for the slot.
0
1
read-only
RESERVED1
reserved1
1
16
read-write
SMIH_SOFTWARE_RESET_REGISTER
Software Reset Register
0x2F
8
read-write
n
0x0
Reserved1
Reserved1
3
8
read-write
SOFTWARE_RESET_FOR_ALL
This reset affects the entire SMIHC Controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0.
0
1
read-write
Work
work
0
Reset
Software Reset For All
1
SOFTWARE_RESET_FOR_CMD_LINE
Only part of command circuit is reset.
1
2
read-write
Work
Software not reset For CMD Line
0
Reset
Software Reset For CMD Line
1
SOFTWARE_RESET_FOR_DAT_LINE
Only part of data circuit is reset,DMA circuit is also reset.
2
3
read-write
Work
Software not reset For DAT Line
0
Reset
Software Reset For DAT Line
1
SMIH_TIMEOUT_CONTROL_REGISTER
Clock Control Register
0x2E
8
read-write
n
0x0
DATA_TIMEOUT_COUNTER_VALUE
This value determines the interval by which DAT line timeouts are detected.
0
4
read-write
Reserved1
Reserved1
4
8
read-write
SMIH_TX_TUNE_REGISTER
Tx Tune Register
0xE0
32
read-write
n
0x0
AUTO_INCREMENT
Increment locally or not.
6
7
read-write
INCREMENT_TAP_POINT_VALUE
Increment value,When Auto increment bit6 is set to 1, Host controller will increment Tap point based on the value programmed in this field.
7
10
read-write
RESERVED1
reserved1
10
32
read-write
TAP_POINT_VALUE
Tap point value
0
6
read-write
SMIH_WAKE_UP_CONTROL_REGISTER
SMIH wake up control register.
0x2B
8
read-write
n
0x0
Reserved1
Reserved1
3
8
read-write
WAKE_UP_EVENT_ENABLE_ON_CARD_INTERRUPT
This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
0
1
read-write
WAKE_UP_EVENT_ENABLE_ON_SD_CARD_INSERTION
This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS (Wake Up Support) in CIS does not affect this bit.
1
2
read-write
WAKE_UP_EVENT_ENABLE_ON_SD_CARD_REMOVAL
This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register.FN_WUS (Wake Up Support) in CIS does not affect this bit.
2
3
read-write
TRANSFER_MODE_REGISTER
Transfer Mode Register
0xC
16
read-write
n
0x0
ALTERNATE_BOOT_OPERATION
Host Driver should set this bit only for Alternate Boot Operation. For Normal Transaction, this bit should always be zero.
14
15
read-write
Disable
Card will not send Boot Ack
0
Enable
Card will send Boot Ack
1
AUTO_CMD_ENABLE
This field determines use of auto command functions.
2
4
read-write
Auto_command_disable
Auto Command Disabled
0
Auto_command12_enable
Auto CMD12 Enabled
1
Auto_command23_enable
Auto CMD23 Enabled
2
RESERVED1
RESERVED1
3
BLOCK_COUNT_ENABLE
This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled,
1
2
read-write
Disable
Block Count disable
0
Enable
Block Count Enable
1
BOOT_ACK_ENABLE
Enable or disable boot ack
13
14
read-write
Disable
Card will not send Boot Ack
0
Enable
Card will send Boot Ack
1
BOOT_OPERATION
Host Driver should set this bit only for Boot Operation. For Normal Transaction, this bit should always be zero.
15
16
read-write
Disable
Stop Boot Operation.
0
Enable
Start Boot Operation.
1
DATA_TRANSFER_DIRECTION_SELECT
This bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver to transfer data from the SD card to the SMIHC Controller and
4
5
read-write
Write
Write (Host to Card)
0
Read
Read (Card to Host)
1
DMA_ENABLE
This bit enables DMA functionality. DMA can be enabled only if it is supported as indicated in the Capabilities register.
0
1
read-write
Disable
No data transfer or Non DMA data transfer
0
Enable
DMA Data transfer
1
MMC_CMD23
The Host driver has to set this bit for MMC CMD23
10
11
read-write
SD_MODE
CMD23 Format in SD mode
0
MMC_MODE
CMD23 Format in MMC mode
1
MULTI_OR_SINGLE_BLOCK_SELECT
This bit is set when issuing multiple-block transfer commands using DAT line.
5
6
read-write
Single_block
Single Block
0
Multi_block
Multiple Block
1
RESERVED1
RESERVED1
6
10
read-only
SPI_MODE_ENABLE
Enable or disable SPI mode
12
13
read-write
Disable
Disable SPI Mode
0
Enable
Enable SPI Mode
1
STREAM_MODE_ENABLE
The Host driver has to set this bit for MMC CMD11 or CMD20 Stream Read/Write Operations.
11
12
read-write
Disable
Stream Mode is Disabled
0
Enable
Stream Mode is Enabled
1
SIO
SERIAL GENERAL PERPOSE INPUT/OUTPUT
SGPIO
0x0
0x0
0x2CC
registers
n
SIO
37
BUFFER_INTR_STATUS_REG
Buffer Interrupt Status Register
0x22C
32
read-write
n
0x0
0x0
INTR_STATUS
Common pattern interrupt status register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
BUFFER_REG0
Buffer Register
0x68
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG1
Buffer Register
0x6C
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG10
Buffer Register
0x90
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG11
Buffer Register
0x94
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG12
Buffer Register
0x98
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG13
Buffer Register
0x9C
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG14
Buffer Register
0xA0
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG15
Buffer Register
0xA4
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG2
Buffer Register
0x70
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG3
Buffer Register
0x74
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG4
Buffer Register
0x78
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG5
Buffer Register
0x7C
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG6
Buffer Register
0x80
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG7
Buffer Register
0x84
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG8
Buffer Register
0x88
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
BUFFER_REG9
Buffer Register
0x8C
32
read-write
n
0x0
0x0
DATA
Data to load into the shift register
0
32
read-write
CONFIG_REG0
Configuration Register
0x128
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG1
Configuration Register
0x12C
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG10
Configuration Register
0x150
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG11
Configuration Register
0x154
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG12
Configuration Register
0x158
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG13
Configuration Register
0x15C
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG14
Configuration Register
0x160
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG15
Configuration Register
0x164
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG2
Configuration Register
0x130
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG3
Configuration Register
0x134
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG4
Configuration Register
0x138
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG5
Configuration Register
0x13C
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG6
Configuration Register
0x140
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG7
Configuration Register
0x144
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG8
Configuration Register
0x148
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
CONFIG_REG9
Configuration Register
0x14C
32
read-write
n
0x0
0x0
CLK_SEL
clock selection
3
4
read-write
Disable
internal counter clock is used for shift operations and sent out
0
Enable
external clock is used for shift operations and is sent out
1
EDGE_SEL
edge selection
2
3
read-write
Disable
pos edge
0
Enable
neg edge
1
EMPTY_ENABLE
When set, fifo full indication would be asserted when internal buffer is empty
1
2
read-write
FLOW_CONTROL_ENABLED
flow control
5
6
read-write
Disable
flow control disable
0
Enable
flow control enable
1
FULL_ENABLE
When set, fifo full indication would be asserted when internal buffer is full
0
1
read-write
IGNORE_FIRST_SHIFT_CONDITION
data shift condition
4
5
read-write
Disable
at a shift/capture happens at the first clock edge
0
INVERT_CLOCK
invert clock
9
10
read-write
None
direct version of shift clock is provided out
0
none
inverted version of the clock is provided out
1
LOAD_DATA_POS_CNTR_VIA_APB
When set, data position counter can be loaded via APB
16
17
read-write
PARALLEL_MODE
No. of bits to shift/capture at valid clk edge
10
12
read-write
00
1 bit
0
01
2 bits
1
10
4 bits
2
11
8 bits
3
PATTERN_MATCH_ENABLE
pattern match
6
7
read-write
Disable
pattern match disable
0
Enable
pattern match enable
1
PIN_DETECTION_MODE
Pin mode to be considered for gpio interrupt
12
14
read-write
00
rise edge
0
01
fall edge
1
10
level zero
2
11
level one
3
QUALIFIER_MODE
qualifier mode
7
8
read-write
none
Use direct qualifier input
0
None
Use inverted qualifier
1
QUALIFY_CLOCK
qualify clock
8
9
read-write
none
output clock is not qualified
0
None
output clock is qualified with qualifier
1
RESERVED1
Reserved for future use
17
32
read-only
RESET_CLK_OUT
When high resets the sio clock_out port. This is used only when sio is not enabled
15
16
read-write
SET_CLK_OUT
When high sets the sio clock_out port. This is used only when sio is not enabled
14
15
read-write
DATA_POS_COUNT_REG0
Data Position Counter Register
0xE8
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG1
Data Position Counter Register
0xEC
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG10
Data Position Counter Register
0x110
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG11
Data Position Counter Register
0x114
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG12
Data Position Counter Register
0x118
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG13
Data Position Counter Register
0x11C
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG14
Data Position Counter Register
0x120
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG15
Data Position Counter Register
0x124
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG2
Data Position Counter Register
0xF0
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG3
Data Position Counter Register
0xF4
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG4
Data Position Counter Register
0xF8
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG5
Data Position Counter Register
0xFC
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG6
Data Position Counter Register
0x100
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG7
Data Position Counter Register
0x104
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG8
Data Position Counter Register
0x108
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
DATA_POS_COUNT_REG9
Data Position Counter Register
0x10C
32
read-write
n
0x0
0x0
POSITION_COUNTER
The position counter can be loaded via AHB
8
16
read-write
RELOAD_VALUE
No. of shifts to happen before reloading the shift register with data/ pausing the operation
0
8
read-write
RESERVED3
Reserved for future use
16
32
read-only
ENABLE_REG
ENABLE REGISTER
0x0
32
read-write
n
0x0
0x0
RESERVED3
Reserved for future use
16
32
read-only
SIO_OPERATION_ENABLE
Contains the Enables for all SIO
0
16
read-write
FIFO_RD_OFFSET_CNT_REG
Points to start current number forming the FIFO
0x2C8
32
read-write
n
0x0
0x0
SIO_CURRENT_SLICE_NUMBER
Next FIFO operation will happen to buffer in the slice pointed by this register This register has to be set to zero before starting fresh DMA operation
0
32
read-write
FIFO_RD_OFFSET_END_REG
Points to last slice number forming the FIFO
0x2C4
32
read-write
n
0x0
0x0
SIO_END_SLICE_NUMBER
Points to last slice number forming the FIFO
0
32
read-write
FIFO_RD_OFFSET_START_REG
Points to start slice number forming the FIFO
0x2C0
32
read-write
n
0x0
0x0
SIO_START_SLICE_NUMBER
Points to start slice number forming the FIFO
0
32
read-write
FIFO_WR_OFFSET_CNT_REG
Points to current slice number forming the FIFO
0x2BC
32
read-write
n
0x0
0x0
SIO_CURRENT_SLICE_NUMBER
Next FIFO operation will happen to buffer in the slice pointed by this register
0
32
read-write
FIFO_WR_OFFSET_END_REG
SIO last slice no indication Register
0x2B8
32
read-write
n
0x0
0x0
SIO_END_SLICE_NUMBER
points to last slice no forming fifo
0
32
read-write
FIFO_WR_OFFSET_START_REG
Points to start slice number forming the FIFO
0x2B4
32
read-write
n
0x0
0x0
SIO_START_SLICE_NUMBER
Points to start slice number forming the FIFO,On write, FIFO_WR_OFFSET_CNT_REG will also be reset to the value pointed written into this register
0
32
read-write
FIFO_WR_RD_REG
FIFO READ/WRITE Register
0x2B0
32
read-write
n
0x0
0x0
FIFO_DATA_REGISTER
Writes and read into this register will be written into SIO buffer register
0
32
read-write
GPIO_INTR_EN_CLEAR_REG
GPIO Interrupt Enable Clear Register
0x18
32
write-only
n
0x0
0x0
INTR_ENABLE_CLEAR
gpio interrupt enable Clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
GPIO_INTR_EN_SET_REG
GPIO Interrupt Enable Set Register
0x14
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
gpio interrupt enable set register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
read-only
GPIO_INTR_MASK_CLEAR_REG
GPIO Interrupt Enable Clear Register
0x20
32
write-only
n
0x0
0x0
INTR_MASK_CLEAR
gpio interrupt mask clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
GPIO_INTR_MASK_SET_REG
GPIO Interrupt Enable Clear Register
0x1C
32
read-write
n
0x0
0x0
INTR_MASK_SET
Common gpio interrupt mask set register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
GPIO_INTR_STATUS_REG
GPIO Interrupt Status Register
0x24
32
read-write
n
0x0
0x0
INTR_MASK_SET
Common gpio interrupt status register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
read-only
GPIO_IN_REG
GPIO Input Register
0x8
32
read-only
n
0x0
0x0
IN_VALUE
GPIO input pin status
0
32
read-only
GPIO_OEN_REG
GPIO Output enable Register
0x10
32
read-write
n
0x0
0x0
OEN_VALUE
OEN for the GPIO pins
0
32
read-write
GPIO_OUT_REG
GPIO Output Register
0xC
32
read-write
n
0x0
0x0
OUT_VALUE
Value to be loaded on GPIO out pins
0
32
read-write
INPUT_MUX_REG0
Input muxing Register
0x270
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG1
Input muxing Register
0x274
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG10
Input muxing Register
0x298
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG11
Input muxing Register
0x29C
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG12
Input muxing Register
0x2A0
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG13
Input muxing Register
0x2A4
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG14
Input muxing Register
0x2A8
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG15
Input muxing Register
0x2AC
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG2
Input muxing Register
0x278
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG3
Input muxing Register
0x27C
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG4
Input muxing Register
0x280
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG5
Input muxing Register
0x284
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG6
Input muxing Register
0x288
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG7
Input muxing Register
0x28C
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG8
Input muxing Register
0x290
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
INPUT_MUX_REG9
Input muxing Register
0x294
32
read-write
n
0x0
0x0
CLK_SEL
Input clock select for SIO 0
0
3
read-write
DIN_SEL
Data in mux select
7
10
read-write
QUALIFIER_MODE
qualifier mode
5
7
read-write
QUALIFIER_SELECT
qualifier select
3
5
read-write
RESERVED1
Reserved for future use
10
32
read-only
OUT_MUX_REG0
Output muxing Register
0x230
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG1
Output muxing Register
0x234
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG10
Output muxing Register
0x258
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG11
Output muxing Register
0x25C
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG12
Output muxing Register
0x260
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG13
Output muxing Register
0x264
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG14
Output muxing Register
0x268
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG15
Output muxing Register
0x26C
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG2
Output muxing Register
0x238
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG3
Output muxing Register
0x23C
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG4
Output muxing Register
0x240
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG5
Output muxing Register
0x244
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG6
Output muxing Register
0x248
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG7
Output muxing Register
0x24C
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG8
Output muxing Register
0x250
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
OUT_MUX_REG9
Output muxing Register
0x254
32
read-write
n
0x0
0x0
DOUT_OEN_SEL
OEN select for GPIO pin 0
0
3
read-write
DOUT_SEL
Output mux select for GPIO pin 0
3
6
read-write
RESERVED1
Reserved for future use
6
32
read-only
PATTERN_MATCH_INTR_EN_CLEAR_REG
Pattern Match Interrupt Enable Clear Register
0x21C
32
write-only
n
0x0
0x0
INRT_ENABLE_CLEAR
Common pattern or buffer under run interrupt enable clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
PATTERN_MATCH_INTR_EN_SET_REG
Pattern Match Interrupt Enable Set Register
0x218
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
Common pattern or buffer under run interrupt enable set register for all SIOs. Each bit corresponds to one SIO
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
PATTERN_MATCH_INTR_MASK_CLEAR_REG
Pattern Match Interrupt Mask Clear Register
0x224
32
write-only
n
0x0
0x0
INTR_MASK_CLEAR
Common pattern or buffer under run interrupt mask clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
PATTERN_MATCH_INTR_MASK_SET_REG
Pattern Match Interrupt Mask Set Register
0x220
32
read-write
n
0x0
0x0
INTR_MASK_SET
Common pattern or buffer under run interrupt mask set register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
PATTERN_MATCH_INTR_STATUS_REG
Pattern Match Interrupt Status Register
0x228
32
read-write
n
0x0
0x0
INTR_STATUS
Common pattern interrupt status register for all SIOs
0
16
read-write
RESERVED3
Reserved for future use
16
32
read-only
PATTERN_MATCH_MASK_REG_SLICE_0
Pattern Match Mask Register 0
0x168
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_MASK_REG_slice_1
Pattern Match Mask Register Slice 1
0x16C
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_MASK_REG_SLICE_10
Pattern Match Mask Register Slice 10
0x190
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_MASK_REG_SLICE_2
Pattern Match Mask Register Slice 2
0x170
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_MASK_REG_SLICE_8
Pattern Match Mask Register Slice 8
0x188
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_MASK_REG_SLICE_9
Pattern Match Mask Register Slice 9
0x18C
32
read-write
n
0x0
0x0
MATCH_MASK_LOWER16_BITS
Enable for lower 16 bits
0
32
read-write
PATTERN_MATCH_REG_SLICE_0
Pattern Match Mask Register Slice 0
0x1A8
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16-bits of pattern to be detected
0
32
read-write
PATTERN_MATCH_REG_SLICE_1
Pattern Match Mask Register Slice 1
0x1AC
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16-bits of pattern to be detected
0
32
read-write
PATTERN_MATCH_REG_SLICE_10
Pattern Match Mask Register Slice 10
0x1D0
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16 bits of pattern to be detected
0
32
read-write
PATTERN_MATCH_REG_SLICE_2
Pattern Match Mask Register Slice 2
0x1B0
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16-bits of pattern to be detected
0
32
read-write
PATTERN_MATCH_REG_SLICE_8
Pattern Match Mask Register Slice 8
0x1C8
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16 bits of pattern to be detected
0
32
read-write
PATTERN_MATCH_REG_SLICE_9
Pattern Match Mask Register Slice 9
0x1CC
32
read-write
n
0x0
0x0
PATTERN_MATCH_LOWER16_BITS
Lower 16 bits of pattern to be detected
0
32
read-write
PAUSE_REG
PAUSE REGISTER
0x4
32
read-write
n
0x0
0x0
RESERVED3
Reserved for future use
16
32
read-only
SIO_POSITION_COUNTER_DISABLE
Contains sio position counter disable for all SIOs
0
16
read-write
SHIFT_COUNTER0
Shift counter register
0x28
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER1
Shift counter register
0x2C
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER10
Shift counter register
0x50
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER11
Shift counter register
0x54
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER12
Shift counter register
0x58
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER13
Shift counter register
0x5C
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER14
Shift counter register
0x60
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER15
Shift counter register
0x64
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER2
Shift counter register
0x30
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER3
Shift counter register
0x34
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER4
Shift counter register
0x38
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER5
Shift counter register
0x3C
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER6
Shift counter register
0x40
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER7
Shift counter register
0x44
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER8
Shift counter register
0x48
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNTER9
Shift counter register
0x4C
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
14
32
read-only
SHIFT_COUNTER
shift counter current value
0
14
read-only
SHIFT_COUNT_PRELOAD_REG0
Shift counter Reload Register
0xA8
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG1
Shift counter Reload Register
0xAC
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG10
Shift counter Reload Register
0xD0
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG11
Shift counter Reload Register
0xD4
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG12
Shift counter Reload Register
0xD8
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG13
Shift counter Reload Register
0xDC
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG14
Shift counter Reload Register
0xE0
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG15
Shift counter Reload Register
0xE4
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG2
Shift counter Reload Register
0xB0
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG3
Shift counter Reload Register
0xB4
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG4
Shift counter Reload Register
0xB8
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG5
Shift counter Reload Register
0xBC
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG6
Shift counter Reload Register
0xC0
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG7
Shift counter Reload Register
0xC4
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG8
Shift counter Reload Register
0xC8
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_COUNT_PRELOAD_REG9
Shift counter Reload Register
0xCC
32
read-write
n
0x0
0x0
RELOAD_VALUE
division factor required to generate shift clock
0
14
read-write
RESERVED1
Reserved for future use
14
15
read-only
RESERVED2
Reserved for future use
16
32
read-only
REVERSE_LOAD
When set, the data on APB is loaded to buffer is reverse order
15
16
read-write
SHIFT_INTR_EN_CLEAR_REG
Shift Interrupt Enable Clear Register
0x1F4
32
write-only
n
0x0
0x0
INRT_ENABLE_CLEAR
Common shift interrupt enable Clear register for all SIOs
0
16
write-only
RESERVED3
Reserved for future use
16
32
write-only
SHIFT_INTR_EN_SET_REG
Shift Interrupt Enable Set Register
0x1F0
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
Common shift interrupt enable set register for all SIOs
0
16
read-write
RESERVED3
Reserved for future use
16
32
read-only
SHIFT_INTR_MASK_CLEAR_REG
Shift Interrupt Mask Clear Register
0x1FC
32
write-only
n
0x0
0x0
INTR_MASK_CLEAR
Common shift interrupt mask clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
SHIFT_INTR_MASK_SET_REG
Shift Interrupt Mask Set Register
0x1F8
32
read-write
n
0x0
0x0
INTR_MASK_SET
Common shift interrupt enable Set register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
SHIFT_INTR_STATUS_REG
Shift Interrupt Status Register
0x200
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
Common shift interrupt mask clear register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
SWAP_INTR_EN_CLEAR_REG
Swap Interrupt Enable Clear Register
0x208
32
write-only
n
0x0
0x0
INTR_ENABLE_CLEAR
Swap interrupt enable Clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
SWAP_INTR_EN_SET_REG
Swap Interrupt Enable Set Register
0x204
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
Swap interrupt enable set register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
SWAP_INTR_MASK_CLEAR_REG
Swap Interrupt Mask Clear Register
0x210
32
write-only
n
0x0
0x0
INTR_MASK_CLEAR
Common swap interrupt mask Clear register for all SIOs
0
16
write-only
RESERVED1
Reserved for future use
16
32
write-only
SWAP_INTR_MASK_SET_REG
Swap Interrupt Mask Set Register
0x20C
32
read-write
n
0x0
0x0
INTR_MASK_SET
Common swap interrupt mask set register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
SWAP_INTR_STATUS_REG
Swap Interrupt Statusr Register
0x214
32
read-write
n
0x0
0x0
INTR_ENABLE_SET
Common swap interrupt status register for all SIOs
0
16
read-write
RESERVED1
Reserved for future use
16
32
read-only
SLEEP_FSM
This is explain the Sleep FSM registers.
SLEEP_FSM
0x0
0x0
0x28
registers
n
FSM_CTRL_POWER_DOMAINS
Power Domains Controlled by Sleep FSM.
0x24
32
read-write
n
0x0
EN_WDT_SLEEP
Its enable or disable WDT during Sleep/Shutdown states.
0
1
read-write
disable
Writing 0 to this enables WDT during Sleep/Shutdown states.
0
enable
Writing 1 to this enables WDT during Sleep/Shutdown states.
1
PWRCTRL_DS_TIMER
Its enable or disable Power to DEEP SLEEP Timer.
18
19
read-write
disable
Writing 0 to this disables Power to DEEP SLEEP Timer.
0
enable
Writing 1 to this enables Power to DEEP SLEEP Timer.
1
PWRCTRL_LP_FSM
Its enable or disable Power to Low-Power FSM.
16
17
read-write
disable
Writing 0 to this disables Power to Low-Power FSM.
0
enable
Writing 1 to this enables Power to Low-Power FSM.
1
PWRCTRL_RETEN
Its enable or disable Power to Retention Flops during SHIP state.These Flops are used for storing Chip Configuration.
19
20
read-write
disable
Writing 0 to this disables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration.
0
enable
Writing 1 to this enables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration.
1
PWRCTRL_TIMESTAMP
Its enable or disable Power to TIMESTAMP.
17
18
read-write
disable
Writing 0 to this disables Power to TIMESTAMP.
0
enable
Writing 1 to this enables Power to TIMESTAMP.
1
RESERVED1
It is recommended to write these bits to 0.
3
16
read-write
RESERVED2
It is recommended to write these bits to 0.
20
32
read-write
RESET_BFF_EN
Its enable or disable reset of Power Domain Control Battery FF's on wakeup.
2
3
read-write
disable
Writing 0 to this disables reset of Power Domain Control Battery FF's on wakeup.
0
enable
Writing 1 to this enables reset of Power Domain Control Battery FF's on wakeup
1
WAKEFI_RX_EN
Its enable or disable detection of On-Air Pattern using Wake-Fi Rx.
1
2
read-write
disable
Writing 0 to this disables detection of On-Air Pattern using Wake-Fi Rx.
0
enable
Writing 1 to this enables detection of On-Air Pattern using Wake-Fi Rx.
1
FSM_POWER_CTRL_DELAY
Power Control and Delay Configuration for Ultra Low-Power Mode of the processor (PS2 State)
0x14
32
read-write
n
0x0
DCDC_EN
Its used to configures DC-DC 1.35 ON or OFF state during PS2.
17
18
read-write
OFF
Writing 0 to this configures DC-DC 1.35 in OFF state during PS2.
0
ON
Writing 1 to this configures DC-DC 1.35 to ON state during PS2.
1
DCDC_LDoSoC_OFF_TIME
Configures the time for switching OFF the LDO SoC 1.1 and the DC-DC 1.35 during transition from PS2 to PS4 state.
0
5
read-write
DCDC_ON_TIME
Configures the time for switching ON the DC-DC 1.35 during transition from PS2 to PS4 state.
12
16
read-write
50
Configure switching 50us ON time of DC-DC.
0
100
Configure switching 100us ON time of DC-DC.
1
1000
Configure switching 1000us ON time of DC-DC.
10
1100
Configure switching 1100us ON time of DC-DC.
11
1200
Configure switching 1200us ON time of DC-DC.
12
1300
Configure switching 1300us ON time of DC-DC.
13
1400
Configure switching 1400us ON time of DC-DC.
14
1500
Configure switching 1400us ON time of DC-DC.
15
200
Configure switching 200us ON time of DC-DC.
2
300
Configure switching 300us ON time of DC-DC.
3
400
Configure switching 400us ON time of DC-DC.
4
500
Configure switching 500us ON time of DC-DC.
5
600
Configure switching 600us ON time of DC-DC.
6
700
Configure switching 700us ON time of DC-DC.
7
800
Configure switching 800us ON time of DC-DC.
8
900
Configure switching 900us ON time of DC-DC.
9
LDoSoC_EN
Its used to configures LDO Soc 1.1 ON or OFF state during PS2.
16
17
read-write
OFF
Writing 0 to this configures LDO SoC 1.1 in OFF state during PS2.
0
ON
Writing 1 to this configures LDO SoC 1.1 to ON state during PS2.
1
LDoSoC_ON_TIME
Configures the time for switching ON the LDO SoC 1.1 during transition from PS2 to PS4 state.
8
12
read-write
50
Configure switching 50us ON time of LDO Soc.
0
100
Configure switching 100us ON time of LDO Soc.
1
1000
Configure switching 1000us ON time of LDO Soc.
10
1100
Configure switching 1100us ON time of LDO Soc.
11
1200
Configure switching 1200us ON time of LDO Soc.
12
1300
Configure switching 1300us ON time of LDO Soc.
13
1400
Configure switching 1400us ON time of LDO Soc.
14
1500
Configure switching 1400us ON time of LDO Soc.
15
200
Configure switching 200us ON time of LDO Soc.
2
300
Configure switching 300us ON time of LDO Soc.
3
400
Configure switching 400us ON time of LDO Soc.
4
500
Configure switching 500us ON time of LDO Soc.
5
600
Configure switching 600us ON time of LDO Soc.
6
700
Configure switching 700us ON time of LDO Soc.
7
800
Configure switching 800us ON time of LDO Soc.
8
900
Configure switching 900us ON time of LDO Soc.
9
RESERVED1
It is recommended to write these bits to 0.
5
8
read-write
RESERVED2
It is recommended to write these bits to 0.
18
19
read-write
RESERVED3
It is recommended to write these bits to 0.
28
32
read-write
VOLTAGE_SEL_LP_SRAM
Configures the Voltage source to be used for LOW-VOLTAGE-LPRAM Domain in PS2 state.
24
26
read-write
0
RESERVED1
0
1
DC-DC 0.95
1
3
LDO SoC 1.1
3
VOLTAGE_SEL_LP_SRAM_16KB
Configures the Voltage source to be used for LOW-VOLTAGE-LPRAM-16KB Domain in PS2 state.
22
24
read-write
0
LDO 0.7V
0
1
DC-DC 0.95
1
3
LDO SoC 1.1
3
VOLTAGE_SEL_PROC
Configures the Voltage source to be used for PROC-DOMAIN Domain in PS2 state.
20
22
read-write
0
LDO 0.7V
0
1
DC-DC 0.95
1
3
LDO SoC 1.1
3
VOLTAGE_SEL_ULP_PERIPH
Configures the Voltage source to be used for LOW-VOLTAGE-ULPPERIPH Domain in PS2 .
19
20
read-write
0
DC-DC 0.95.
0
1
LDO SoC 1.1
1
VOLTAGE_SEL_ULP_SRAM
Configures the Voltage source to be used for LOW-VOLTAGE-ULPRAM Domain in PS2 state.
26
28
read-write
0
RESERVED4
0
1
DC-DC 0.95
1
3
LDO SoC 1.1
3
FSM_SLEEP_CTRLS_AND_WAKEUP_MODE
Sleep Control Signals and Wakeup source selection
0x0
32
read-write
n
0x0
Alarm_Wakeup
It is enable or disable ALARM Interrupt as a Wakeup source.
26
27
read-write
disable
Writing 0 to this disables ALARM Interrupt as a Wakeup source.
0
enable
Writing 1 to this enables ALARM Interrupt as a Wakeup source.
1
CMPR_BOD_BUTTON_Wakeup
It is enable or disable 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
21
22
read-write
disable
Writing 0 to this disables 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
0
enable
Writing 1 to this enables 4x-Comparator/BOD/BUTTON Interrupt as a Wakeup source
1
DCDC_ON
It is maintain DC-DC 1.35 on state
10
11
read-write
disable
Writing 0 to this maintains LDO FL 1.8 in OFF state during Sleep.
0
enable
Writing 1 to this maintains LDO FL 1.8 in ON state during Sleep.
1
HP_SRAM1_RETENTION_EN
SRAM retention Control for 64KB of HP-SRAM1
3
4
read-write
disable
Writing 1 to this enables Retention during sleep
0
enable
Writing 1 to this enables Retention during sleep
1
HP_SRAM2_RETENTION_EN
SRAM retention Control for 192KB of HP-SRAM2
5
6
read-write
disable
Writing 1 to this enables Retention during sleep
0
enable
Writing 1 to this enables Retention during sleep
1
LDOFL_ON
It is maintain LDO FL 1.8 on state
9
10
read-write
disable
Writing 0 to this maintains LDO FL 1.8 in OFF state during Sleep.
0
enable
Writing 1 to this maintains LDO FL 1.8 in ON state during Sleep.
1
LDoSoC_ON
It is maintain LDO SOC 1.1 on state
8
9
read-write
disable
Writing 0 to this maintains LDO SoC 1.1 in OFF state during Sleep.
0
enable
Writing 1 to this maintains LDO SoC 1.1 in ON state during Sleep.
1
LP_SRAM_16KB_RETENTION_EN
SRAM retention Control for 16KB of LP-SRAM (LP-SRAM-1, LP-SRAM-2, LP-SRAM-3, LP-SRAM-4)
7
8
read-write
disable
Writing 1 to this enables Retention during sleep
0
enable
Writing 1 to this enables Retention during sleep
1
LP_SRAM_RETENTION_EN
SRAM retention Control for 112KB of LP-SRAM (LP-SRAM-5, LP-SRAM-6, LP-SRAM-7)
4
5
read-write
disable
Writing 1 to this enables Retention during sleep
0
enable
Writing 1 to this enables Retention during sleep
1
MilliSecond_Wakeup
It is enable or disable Milli-Second Interrupt as a Wakeup source
28
29
read-write
disable
Writing 0 to this disables Milli-Second Interrupt as a Wakeup source.
0
enable
Writing 1 to this enables Milli-Second Interrupt as a Wakeup source.
1
NWP_Wakeup
It is enable or disable NWP Interrupt as a Wakeup source
18
19
read-write
disable
Writing 0 to this disables RTC Interrupt as a Wakeup source
0
enable
Writing 1 to this enables RTC Interrupt as a Wakeup source
1
RESERVED1
It is recommended to write these bits to 0.
0
3
read-write
RESERVED2
It is recommended to write these bits to 0.
12
16
read-write
RESERVED3
It is recommended to write these bits to 0.
17
18
read-write
RESERVED4
It is recommended to write these bits to 0.
19
20
read-write
RESERVED6
It is recommended to write these bits to 0.
23
24
read-write
RESERVED7
It is recommended to write these bits to 0.
31
32
read-write
RTC_Wakeup
It is enable or disable RTC Interrupt as a Wakeup source
16
17
read-write
disable
Writing 0 to this disables RTC Interrupt as a Wakeup source
0
enable
Writing 1 to this enables RTC Interrupt as a Wakeup source
1
SDC_Wakeup
It is enable or disable Sensor Data Collector Interrupt as a Wakeup source.
25
26
read-write
disable
Writing 0 to this disables Sensor Data Collector Interrupt as a Wakeup source
0
enable
Writing 1 to this enables Sensor Data Collector Interrupt as a Wakeup source
1
Second_Wakeup
It is enable or disable Second Interrupt as a Wakeup source
27
28
read-write
disable
Writing 0 to this disables Second Interrupt as a Wakeup source.
0
enable
Writing 1 to this enables Second Interrupt as a Wakeup source
1
SKIP_XTAL_WAIT_TIME
It is used to skips the settling time for High Frequency XTAL during wakeup.
11
12
read-write
disable
Writing 0 to this includes the settling time for High Frequency XTAL during wakeup.
0
enable
Writing 1 to this skips the settling time for High Frequency XTAL during wakeup.
1
ULP_Peripheral_Sleep
It is enable or disable ULP Peripheral Interrupt as a Sleep source.
30
31
read-write
disable
Writing 0 to this disables ULP Peripheral Interrupt as a Sleep source.
0
enable
Writing 1 to this enables ULP Peripheral Interrupt as a Sleep source.
1
ULP_Peripheral_Wakeup
It is enable or disable ULP Peripheral Interrupt as a Wakeup source
24
25
read-write
disable
Writing 0 to this disables ULP Peripheral Interrupt as a Wakeup source
0
enable
Writing 1 to this enables ULP Peripheral Interrupt as a Wakeup source
1
ULP_SRAM_RETENTION_EN
SRAM retention Control for 16KB of ULP-SRAM
6
7
read-write
disable
Writing 1 to this enables Retention during sleep
0
enable
Writing 1 to this enables Retention during sleep
1
UULP_Vbat_GPIO_Wakeup
It is enable or disable UULP Vbat GPIO Interrupt as a Wakeup source
20
21
read-write
disable
Writing 0 to this disables UULP Vbat GPIO Interrupt as a Wakeup source
0
enable
Writing 1 to this enables UULP Vbat GPIO Interrupt as a Wakeup source
1
WDT_Wakeup
It is enable or disable WDT Interrupt as a Wakeup source.
29
30
read-write
disable
Writing 0 to this disables WDT Interrupt as a Wakeup source.
0
enable
Writing 1 to this enables WDT Interrupt as a Wakeup source.
1
WuRx_Wakeup
It is enable or disable wake-Fi Rx Interrupt as a Wakeup source
22
23
read-write
disable
Writing 0 to this disables Wake-Fi Rx Interrupt as a Wakeup source.
0
enable
Writing 1 to this enables Wake-Fi Rx Interrupt as a Wakeup source.
1
MCUULP_VBAT_HFCLK_REG
High Frequency Clock Select Register
0x18
32
read-write
n
0x0
MCUULP_VBAT_HF_CLK_SEL
Select the MCU VBAT clock.
2
5
read-write
clock_gated
clock gated
0
ro_20m_clk
Enable rc 20Mhz clock
1
rc_32m_clk
Enable rc 20Mhz clock
2
MCUULP_VBAT_HF_CLK_SWITCHED
Status of NPSS High Frequency Clock Dynamic Clock Mux
15
16
read-only
Disable
Clock switching is in progress
0
Enable
Clock got switched and output clock can be used
1
RESERVED1
Reserved1
0
2
read-only
RESERVED2
Reserved2
5
15
read-only
RESERVED3
It is recommended to write these bits to 0.
16
32
read-only
ULP_CLKOSC_CTRL_REG
ULP Clock Oscillators Control Register
0x20
32
read-write
n
0x0
DOUBLER_CLK_EN
Enable or disable DOUBLER Clock
21
22
read-write
Disable
Writing 0 to this disables the Doubler Clock
0
Enable
Writing 1 to this enables the Doubler Clock
1
RC_32KHZ_CLK_EN
Enable or disable RC 32 KHZ clock
16
17
read-write
Disable
Writing 0 to this disables the RC 32KHz Clock
0
Enable
Writing 1 to this enables the RC 32KHz Clock
1
RC_32MHZ_CLK_EN
Enable or disable RC 32MHz Clock
19
20
read-write
Disable
Writing 0 to this disables the XTAL 32KHz Clock
0
Enable
Writing 1 to this enables the XTAL 32KHz Clock
1
RESERVED1
Reserved1
0
16
read-write
RESERVED2
RESERVED2
23
32
read-write
RO_32KHZ_CLK_EN
Enable or disable RO 32 KHZ clock
17
18
read-write
Disable
Writing 0 to this disables the RO 32KHz Clock
0
Enable
Writing 1 to this enables the RO 32KHz Clock
1
RO_HF_CLK_EN
Enable or disable RO High-Frequency Clock
20
21
read-write
Disable
Writing 0 to this disables the RO High-Frequency Clock
0
Enable
Writing 1 to this enables the RO High-Frequency Clock
1
XTAL_32KHZ_CLK_EN
Enable or disable XTAL 32KHz Clock
18
19
read-write
Disable
Writing 0 to this disables the XTAL 32KHz Clock
0
Enable
Writing 1 to this enables the XTAL 32KHz Clock
1
XTAL_40MHZ_CLK_EN
Enable or disable XTAL 40MHZ Clock
22
23
read-write
Disable
Writing 0 to this disables the XTAL-40MHz Clock
0
Enable
Writing 1 to this enables the XTAL-40MHz Clock
1
ULP_MODE_CONFIG
Configuration for Ultra Low-Power Mode of the processor (PS2 State)
0x4
32
read-write
n
0x0
BGPMU_SAMPLING_EN
Controls the mode of Band-Gap for DC-DC 1.35 during PS2 state.
16
17
read-write
disable
Writing 0 to this disables sampling mode of Band-Gap. This is described in Power Management Section.
0
enable
Writing 1 to this enables sampling mode of Band-Gap. This is described in Power Management Section.
1
RESERVED1
It is recommended to write these bits to 0.
3
16
read-write
RESERVED2
It is recommended to write these bits to 0.
17
32
read-write
ULP_MODE_FUNC_SWITCH
Enable functional switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions
1
2
read-write
disable
Writing 0 to this disables functional switching for PS2-PS4/PS3 state transition
0
enable
Writing 1 to this enables functional switching for PS4/PS3-PS2 state transition.
1
ULP_MODE_MEM_CONFIG
Its enable or disable maximum of 32KB of LP-SRAM for operation in PS2 state
2
3
read-write
disable
Writing 0 to this enables a maximum of 128KB of LP-SRAM for operation in PS2 state.
0
enable
Writing 1 to this enables a maximum of 32KB of LP-SRAM for operation in PS2 state.
1
ULP_MODE_VOLT_SWITCH
Enables voltage switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions.
0
1
read-write
disable
Writing 0 to this disables voltage switching for PS2-PS4/PS3 state transition
0
enable
Writing 1 to this enables voltage switching for PS4/PS3-PS2 state transition.
1
SSIMaster
Synchronous Serial Interface(SSI)
SSI
0x0
0x0
0xF8
registers
n
SSIMaster
47
BAUDR
Baud Rate Select Register
0x14
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
16
32
read-write
SCKDV
SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register
0
16
read-write
CTRLR0
Control Register 0
0x0
32
read-write
n
0x0
0x0
CFS
Control Frame Size Selects the length of the control word for the Micro wire frame format
12
16
read-write
None
Range -> 1 bit
0
none
Range -> 16 bit
15
DFS
Select the data frame length (4-bit to 16-bit serial data transfers)
0
4
read-write
DFS_32
Selects the data frame length
16
21
read-write
none
Range -> 16 bit
15
None
Range -> 3 bit
3
FRF
Frame Format, Selects which serial protocol transfers the data
4
6
read-write
00
Motorola SPI
0
01
Texas Instruments SSP
1
10
National Semiconductors Micro wire
2
11
none
3
RESERVED1
Reserved for future use
23
32
read-write
SCPH
Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI
6
7
read-write
disable
Serial clock toggles in middle of first data bit
0
enable
Serial clock toggles at start of first data bit
1
SCPOL
Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI
7
8
read-write
disable
Inactive state of serial clock is low
0
enable
Inactive state of serial clock is high
1
SLV_OE
DW_apb_ssi is configured as a serial-slave device
10
11
read-write
None
Slave txd is enabled
0
none
Slave txd is disabled
1
SPI_FRF
Selects data frame format for transmitting or receiving data
21
23
read-write
00
Standard SPI Format
0
01
Dual SPI Format
1
10
Quad SPI Format
2
11
Reser
3
SRL
Shift Register Loop Used for testing purposes only
11
12
read-write
None
Normal Mode Operation
0
none
Test Mode Operation
1
TMOD
Selects the mode of transfer for serial communication
8
10
read-write
00
Transmit and Receive
0
01
Transmit Only
1
10
Receive Only
2
CTRLR1
Control Register 1
0x4
32
read-write
n
0x0
0x0
NDF
Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master
0
16
read-write
RESERVED1
Reserved for future use.
16
32
read-write
DMACR
DMA Control Register
0x4C
32
read-write
n
0x0
0x0
RDMAE
This bit enables/disables the receive FIFO DMA channel
0
1
read-write
disabled
Receive DMA disabled
0
enabled
Receive DMA enabled
1
RESERVED1
Reserved for future use
2
32
read-only
TDMAE
This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
disabled
Transmit DMA disabled
0
enabled
Transmit DMA enabled
1
DMARDLR
DMA Receive Data Level Register
0x54
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-write
DMATDLR
DMA Transmit Data Level
0x50
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-only
DR
Data Register
0x60
32
read-write
n
0x0
0x0
DR
When writing to this register must right-justify the data
0
32
read-write
ICR
Interrupt Clear Register
0x48
32
read-only
n
0x0
ICR
This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
IDR
Identification Register
0x58
32
read-only
n
0x0
0x0
IDCODE
This register contains the peripherals identification code
0
32
read-only
IMR
Interrupt Mask Register
0x2C
32
read-write
n
0x0
0x0
MSTIM
Multi-Master Contention Interrupt Mask
5
6
read-write
disable
ssi_mst_intr interrupt is masked
0
enable
ssi_mst_intr interrupt is not masked
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIM
Receive FIFO Full Interrupt Mask
4
5
read-write
disable
ssi_rxf_intr interrupt is masked
0
enable
ssi_rxf_intr interrupt is not masked
1
RXOIM
Receive FIFO Overflow Interrupt Mask
3
4
read-write
disable
ssi_rxo_intr interrupt is masked
0
enable
ssi_rxo_intr interrupt is not masked
1
RXUIM
Receive FIFO Underflow Interrupt Mask
2
3
read-write
disable
ssi_rxu_intr interrupt is masked
0
enable
ssi_rxu_intr interrupt is not masked
1
TXEIM
Transmit FIFO Empty Interrupt Mask
0
1
read-write
disable
ssi_txe_intr interrupt is masked
0
enable
ssi_txe_intr interrupt is not masked
1
TXOIM
Transmit FIFO Overflow Interrupt Mask
1
2
read-write
disable
ssi_txo_intr interrupt is masked
0
enable
ssi_txo_intr interrupt is not masked
1
ISR
Interrupt Status Register
0x30
32
read-only
n
0x0
MSTIS
Multi-Master Contention Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt not active after masking
0
enable
ssi_mst_intr interrupt is active after masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIS
Receive FIFO Full Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active after masking
0
enable
ssi_rxf_intr interrupt is full after masking
1
RXOIS
Receive FIFO Overflow Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active after masking
0
enable
ssi_rxo_intr interrupt is active after masking
1
RXUIS
Receive FIFO Underflow Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active after masking
0
enable
ssi_rxu_intr interrupt is active after masking
1
TXEIS
Transmit FIFO Empty Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active after masking
0
enable
ssi_txe_intr interrupt is active after masking
1
TXOIS
Transmit FIFO Overflow Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active after masking
0
enable
ssi_txo_intr interrupt is active after masking
1
MSTICR
Multi-Master Interrupt Clear Register
0x44
32
read-only
n
0x0
MSTICR
This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
MWCR
Micro wire Control Register
0xC
32
read-write
n
0x0
0x0
MDD
The direction of the data word when the Micro wire serial protocol is used
1
2
read-write
disable
the data word is received by the SSI MacroCell from the external serial device
0
enable
the data word is transmitted from the SSI MacroCell to the external serial device
1
MHS
Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol
2
3
read-write
disable
handshaking interface is disabled
0
enable
handshaking interface is enabled
1
MWMOD
The Micro wire transfer is sequential or non-sequential
0
1
read-write
disable
non-sequential transfer
0
enable
sequential transfer
1
RESERVED1
Reserved for future use
3
32
read-write
RISR
Raw Interrupt Status Register
0x34
32
read-only
n
0x0
MSTIR
Multi-Master Contention Raw Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt is not active prior to masking
0
enable
ssi_mst_intr interrupt is active prior masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIR
Receive FIFO Full Raw Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active prior to masking
0
enable
ssi_rxf_intr interrupt is active prior to masking
1
RXOIR
Receive FIFO Overflow Raw Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active prior to masking
0
enable
ssi_rxo_intr interrupt is active prior masking
1
RXUIR
Receive FIFO Underflow Raw Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active prior to masking
0
enable
ssi_rxu_intr interrupt is active prior to masking
1
TXEIR
Transmit FIFO Empty Raw Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active prior to masking
0
enable
ssi_txe_intr interrupt is active prior masking
1
TXOIR
Transmit FIFO Overflow Raw Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active prior to masking
0
enable
1 = ssi_txo_intr interrupt is active prior masking
1
RXFLR
Receive FIFO Level Register
0x24
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
RXTFL
Contains the number of valid data entries in the receive FIFO
0
5
read-only
RXFTLR
Receive FIFO Threshold Level
0x1C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
RFT
Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt
0
4
read-write
RXOICR
Receive FIFO Overflow Interrupt Clear Register
0x3C
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXOICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt
0
1
read-only
RXUICR
Receive FIFO Underflow Interrupt Clear Register
0x40
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXUICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt
0
1
read-only
RX_SAMPLE_DLY
Rx Sample Delay Register
0xF0
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
8
32
read-write
RSD
Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal.
0
8
read-write
SER
SLAVE ENABLE REGISTER
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
SER
Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master.
0
4
read-write
disable
Not selected
0
enable
selected
1
SPI_CTRLR0
SPI control Register
0xF4
32
read-write
n
0x0
0x0
ADDR_L
This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO
2
6
read-write
INST_L
DUAL/QUAD length in bits
8
10
read-write
RESERVED1
Reserved for future use
6
8
read-only
RESERVED2
Reserved for future use
10
11
read-only
RESERVED3
Reserved for future use
15
32
read-only
TRANS_TYPE
Address and instruction transfer format
0
2
read-write
WAIT_CYCLES
This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles
11
15
read-write
SR
Status Register
0x28
32
read-only
n
0x0
BUSY
indicates that a serial transfer is in progress
0
1
read-only
disable
SSI is idle or disabled
0
enable
SSI is actively transferring data
1
DCOL
This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer
6
7
read-only
disable
No error
0
enable
Transmit data collision error
1
RESERVED1
Reserved for future use
7
32
read-only
RFF
When the receive FIFO is completely full this bit is set
4
5
read-only
disable
Receive FIFO is not full
0
enable
Receive FIFO is full
1
RFNE
Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty
3
4
read-only
disable
Receive FIFO is empty
0
enable
Receive FIFO is not empty
1
TFE
When the transmit FIFO is completely empty this bit is set
2
3
read-only
disable
Transmit FIFO is not empty
0
enable
Transmit FIFO is empty
1
TFNF
Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full
1
2
read-only
disable
Transmit FIFO is full
0
enable
Transmit FIFO is not full
1
TXE
This bit is cleared when read
5
6
read-only
disable
No error
0
enable
Transmission error
1
SSIENR
SSI Enable Register
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
SSI_EN
Enables and disables all ssi operations
0
1
read-write
SSI_COMP_VERSION
coreKit version ID register
0x5C
32
read-only
n
0x0
0x0
SSI_COMP_VERSION
Contains the hex representation of the Synopsys component version
0
32
read-only
TXFLR
Transmit FIFO Level Register
0x20
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
TXTFL
Contains the number of valid data entries in the transmit FIFO
0
5
read-only
TXFTLR
Transmit FIFO Threshold Level Register
0x18
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
TFT
Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt
0
4
read-write
TXOICR
Transmit FIFO Overflow Interrupt Clear Register
0x38
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
TXOICR
Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt
0
1
read-only
SSISlave
Synchronous Serial Interface(SSI)
SSI
0x0
0x0
0xF8
registers
n
SSISlave
44
BAUDR
Baud Rate Select Register
0x14
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
16
32
read-write
SCKDV
SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register
0
16
read-write
CTRLR0
Control Register 0
0x0
32
read-write
n
0x0
0x0
CFS
Control Frame Size Selects the length of the control word for the Micro wire frame format
12
16
read-write
None
Range -> 1 bit
0
none
Range -> 16 bit
15
DFS
Select the data frame length (4-bit to 16-bit serial data transfers)
0
4
read-write
DFS_32
Selects the data frame length
16
21
read-write
none
Range -> 16 bit
15
None
Range -> 3 bit
3
FRF
Frame Format, Selects which serial protocol transfers the data
4
6
read-write
00
Motorola SPI
0
01
Texas Instruments SSP
1
10
National Semiconductors Micro wire
2
11
none
3
RESERVED1
Reserved for future use
23
32
read-write
SCPH
Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI
6
7
read-write
disable
Serial clock toggles in middle of first data bit
0
enable
Serial clock toggles at start of first data bit
1
SCPOL
Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI
7
8
read-write
disable
Inactive state of serial clock is low
0
enable
Inactive state of serial clock is high
1
SLV_OE
DW_apb_ssi is configured as a serial-slave device
10
11
read-write
None
Slave txd is enabled
0
none
Slave txd is disabled
1
SPI_FRF
Selects data frame format for transmitting or receiving data
21
23
read-write
00
Standard SPI Format
0
01
Dual SPI Format
1
10
Quad SPI Format
2
11
Reser
3
SRL
Shift Register Loop Used for testing purposes only
11
12
read-write
None
Normal Mode Operation
0
none
Test Mode Operation
1
TMOD
Selects the mode of transfer for serial communication
8
10
read-write
00
Transmit and Receive
0
01
Transmit Only
1
10
Receive Only
2
CTRLR1
Control Register 1
0x4
32
read-write
n
0x0
0x0
NDF
Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master
0
16
read-write
RESERVED1
Reserved for future use.
16
32
read-write
DMACR
DMA Control Register
0x4C
32
read-write
n
0x0
0x0
RDMAE
This bit enables/disables the receive FIFO DMA channel
0
1
read-write
disabled
Receive DMA disabled
0
enabled
Receive DMA enabled
1
RESERVED1
Reserved for future use
2
32
read-only
TDMAE
This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
disabled
Transmit DMA disabled
0
enabled
Transmit DMA enabled
1
DMARDLR
DMA Receive Data Level Register
0x54
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-write
DMATDLR
DMA Transmit Data Level
0x50
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-only
DR
Data Register
0x60
32
read-write
n
0x0
0x0
DR
When writing to this register must right-justify the data
0
32
read-write
ICR
Interrupt Clear Register
0x48
32
read-only
n
0x0
ICR
This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
IDR
Identification Register
0x58
32
read-only
n
0x0
0x0
IDCODE
This register contains the peripherals identification code
0
32
read-only
IMR
Interrupt Mask Register
0x2C
32
read-write
n
0x0
0x0
MSTIM
Multi-Master Contention Interrupt Mask
5
6
read-write
disable
ssi_mst_intr interrupt is masked
0
enable
ssi_mst_intr interrupt is not masked
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIM
Receive FIFO Full Interrupt Mask
4
5
read-write
disable
ssi_rxf_intr interrupt is masked
0
enable
ssi_rxf_intr interrupt is not masked
1
RXOIM
Receive FIFO Overflow Interrupt Mask
3
4
read-write
disable
ssi_rxo_intr interrupt is masked
0
enable
ssi_rxo_intr interrupt is not masked
1
RXUIM
Receive FIFO Underflow Interrupt Mask
2
3
read-write
disable
ssi_rxu_intr interrupt is masked
0
enable
ssi_rxu_intr interrupt is not masked
1
TXEIM
Transmit FIFO Empty Interrupt Mask
0
1
read-write
disable
ssi_txe_intr interrupt is masked
0
enable
ssi_txe_intr interrupt is not masked
1
TXOIM
Transmit FIFO Overflow Interrupt Mask
1
2
read-write
disable
ssi_txo_intr interrupt is masked
0
enable
ssi_txo_intr interrupt is not masked
1
ISR
Interrupt Status Register
0x30
32
read-only
n
0x0
MSTIS
Multi-Master Contention Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt not active after masking
0
enable
ssi_mst_intr interrupt is active after masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIS
Receive FIFO Full Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active after masking
0
enable
ssi_rxf_intr interrupt is full after masking
1
RXOIS
Receive FIFO Overflow Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active after masking
0
enable
ssi_rxo_intr interrupt is active after masking
1
RXUIS
Receive FIFO Underflow Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active after masking
0
enable
ssi_rxu_intr interrupt is active after masking
1
TXEIS
Transmit FIFO Empty Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active after masking
0
enable
ssi_txe_intr interrupt is active after masking
1
TXOIS
Transmit FIFO Overflow Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active after masking
0
enable
ssi_txo_intr interrupt is active after masking
1
MSTICR
Multi-Master Interrupt Clear Register
0x44
32
read-only
n
0x0
MSTICR
This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
MWCR
Micro wire Control Register
0xC
32
read-write
n
0x0
0x0
MDD
The direction of the data word when the Micro wire serial protocol is used
1
2
read-write
disable
the data word is received by the SSI MacroCell from the external serial device
0
enable
the data word is transmitted from the SSI MacroCell to the external serial device
1
MHS
Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol
2
3
read-write
disable
handshaking interface is disabled
0
enable
handshaking interface is enabled
1
MWMOD
The Micro wire transfer is sequential or non-sequential
0
1
read-write
disable
non-sequential transfer
0
enable
sequential transfer
1
RESERVED1
Reserved for future use
3
32
read-write
RISR
Raw Interrupt Status Register
0x34
32
read-only
n
0x0
MSTIR
Multi-Master Contention Raw Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt is not active prior to masking
0
enable
ssi_mst_intr interrupt is active prior masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIR
Receive FIFO Full Raw Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active prior to masking
0
enable
ssi_rxf_intr interrupt is active prior to masking
1
RXOIR
Receive FIFO Overflow Raw Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active prior to masking
0
enable
ssi_rxo_intr interrupt is active prior masking
1
RXUIR
Receive FIFO Underflow Raw Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active prior to masking
0
enable
ssi_rxu_intr interrupt is active prior to masking
1
TXEIR
Transmit FIFO Empty Raw Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active prior to masking
0
enable
ssi_txe_intr interrupt is active prior masking
1
TXOIR
Transmit FIFO Overflow Raw Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active prior to masking
0
enable
1 = ssi_txo_intr interrupt is active prior masking
1
RXFLR
Receive FIFO Level Register
0x24
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
RXTFL
Contains the number of valid data entries in the receive FIFO
0
5
read-only
RXFTLR
Receive FIFO Threshold Level
0x1C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
RFT
Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt
0
4
read-write
RXOICR
Receive FIFO Overflow Interrupt Clear Register
0x3C
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXOICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt
0
1
read-only
RXUICR
Receive FIFO Underflow Interrupt Clear Register
0x40
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXUICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt
0
1
read-only
RX_SAMPLE_DLY
Rx Sample Delay Register
0xF0
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
8
32
read-write
RSD
Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal.
0
8
read-write
SER
SLAVE ENABLE REGISTER
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
SER
Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master.
0
4
read-write
disable
Not selected
0
enable
selected
1
SPI_CTRLR0
SPI control Register
0xF4
32
read-write
n
0x0
0x0
ADDR_L
This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO
2
6
read-write
INST_L
DUAL/QUAD length in bits
8
10
read-write
RESERVED1
Reserved for future use
6
8
read-only
RESERVED2
Reserved for future use
10
11
read-only
RESERVED3
Reserved for future use
15
32
read-only
TRANS_TYPE
Address and instruction transfer format
0
2
read-write
WAIT_CYCLES
This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles
11
15
read-write
SR
Status Register
0x28
32
read-only
n
0x0
BUSY
indicates that a serial transfer is in progress
0
1
read-only
disable
SSI is idle or disabled
0
enable
SSI is actively transferring data
1
DCOL
This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer
6
7
read-only
disable
No error
0
enable
Transmit data collision error
1
RESERVED1
Reserved for future use
7
32
read-only
RFF
When the receive FIFO is completely full this bit is set
4
5
read-only
disable
Receive FIFO is not full
0
enable
Receive FIFO is full
1
RFNE
Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty
3
4
read-only
disable
Receive FIFO is empty
0
enable
Receive FIFO is not empty
1
TFE
When the transmit FIFO is completely empty this bit is set
2
3
read-only
disable
Transmit FIFO is not empty
0
enable
Transmit FIFO is empty
1
TFNF
Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full
1
2
read-only
disable
Transmit FIFO is full
0
enable
Transmit FIFO is not full
1
TXE
This bit is cleared when read
5
6
read-only
disable
No error
0
enable
Transmission error
1
SSIENR
SSI Enable Register
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
SSI_EN
Enables and disables all ssi operations
0
1
read-write
SSI_COMP_VERSION
coreKit version ID register
0x5C
32
read-only
n
0x0
0x0
SSI_COMP_VERSION
Contains the hex representation of the Synopsys component version
0
32
read-only
TXFLR
Transmit FIFO Level Register
0x20
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
TXTFL
Contains the number of valid data entries in the transmit FIFO
0
5
read-only
TXFTLR
Transmit FIFO Threshold Level Register
0x18
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
TFT
Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt
0
4
read-write
TXOICR
Transmit FIFO Overflow Interrupt Clear Register
0x38
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
TXOICR
Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt
0
1
read-only
TEMPERATURE_SENSOR
The temperature sensor is used to read the temperature by using APB registers, which is access through direct to ULPSS system.
TEMPSENSOR
0x0
0x0
0x14
registers
n
TEMPERATURE_READ
read the temperature
0x10
32
read-write
n
0x0
RES10
reserved10
11
32
read-write
TEMPERATURE_RD
Temperature value for read in signed format
0
11
read-only
TS_COUNTS_READ
temperature sensor count read
0xC
32
read-only
n
0x0
COUNT_F1
count of clk_f1 cycles
16
26
read-only
COUNT_F2
count of clk_f2 cycles
0
10
read-only
RESERVED1
Reserved1
10
16
read-only
RESERVED2
Reserved2
26
32
read-only
TS_ENABLE_AND_TEMPERATURE_DONE
Temperature sensor enable and measurement calculation done indication register
0x0
32
read-write
n
0x0
CONT_COUNT_FREEZE
Count of reference clock on which ptat clock counts
2
12
read-write
REF_CLK_SEL
if this bit is zero then reference RO clock from analog,else this bit is one then MCU FSM clock
1
2
read-write
RO_CLOCK
use KHz RO clock from analog as reference clock
0
MCU_FSM
use MCU FSM clock as reference clock
1
RESERVED1
reserved1
13
32
read-write
TEMP_MEASUREMENT_DONE
temperature measurement done indication.
12
13
read-only
TEMP_SENS_EN
Temperature sensing enable,self clearing register
0
1
write-only
Disable
Disable the temperature sensor
0
Enable
Enable the temperature sensor
1
TS_FE_COUNTS_NOMINAL_SETTINGS
determine calibrated temperature
0x8
32
read-write
n
0x0
F2_NOMINAL
ptat clock count during calibration,This will vary with chip to chip.
0
10
read-write
NOMINAL_TEMPERATURE
calibrated temperature
16
23
read-write
RESERVED1
Reserved1
10
16
read-write
RESERVED2
Reserved2
23
32
read-write
TS_SLOPE_SET
temperature sensor slope set(slope will be change with respect to temperature change)
0x4
32
read-write
n
0x0
BJT_BASED_TEMP
Temperature is updated through which is calculated using bjt based if bit is high(1) through spi and bit is low(0) then through calculation RO based
28
29
read-write
Through_RO
Temperature is updated through which is calculated using bjt based ,through calculation RO based
0
Through_SPI
Temperature is updated through which is calculated using bjt based , through spi
1
RESERVED1
Reserved1
10
16
read-write
RESERVED2
Reserved2
29
32
read-write
SLOPE
This is one time measurement for one package after chip arrives from fab,this is signed bit.
0
10
read-write
TEMPERATURE_SPI
temperature known
16
27
read-write
TEMP_UPDATED
temperature updated signal for the reg to capture this temperature.
27
28
write-only
TIMEPERIOD_CALIBRATION
In this the time periods of 32KHz RC clock, 32KHz RO clock and 32KHz XTAL clock can be calibrated
TIMEPERIOD_CALIBRATION
0x0
0x0
0x1C
registers
n
MCU_CAL_RC_TIMEPERIOD_READ
rc timeperiod read register
0x14
32
read-only
n
0x0
RESERVED1
reser
25
32
read-only
TIMEPERIOD_RC
Calibrated RC timeperiod
0
25
read-only
MCU_CAL_REF_CLK_SETTLE_REG
reference clock settle register
0x10
32
read-write
n
0x0
RESERVED1
reser
7
16
read-only
RESERVED2
reser
18
32
read-only
VALID_RC_TIMEPERIOD
Valid signal for reading RC timeperiod calibrated
16
17
read-only
VALID_RO_TIMEPERIOD
Valid signal for reading RO timeperiod
17
18
read-only
XTAL_SETTLE
no of 32khz clocks for xtal 40mhz clk to settle
0
7
read-write
MCU_CAL_REF_CLK_TIEMPERIOD_REG
reference clock timeperiod register
0x18
32
read-write
n
0x0
RESERVED1
reser
24
32
read-only
TIMEPERIOD_REF_CLK
timeperiod of reference clk with each bit corresponding to granularity of 2^27 = 1us
0
24
read-write
MCU_CAL_RO_TIMEPERIOD_READ
RO timeperiod read register
0x0
32
read-only
n
0x0
RESERVED1
reser
25
32
read-only
TIMEPERIOD_RO
Calibrated RO timeperiod
0
25
read-only
MCU_CAL_START_REG
mcu cal start register
0xC
32
read-write
n
0x0
ALPHA_RC
alpha = 1/2^alpha_rc , averaging factor of RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev
3
6
read-write
ALPHA_RO
alpha = 1/2^alpha_ro , averaging factor of RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev
0
3
read-write
LOW_POWER_TRIGGER_SEL
power trigger select
26
27
read-write
NO_OF_RC_CLKS
2^no_of_rc_clocks = no of rc clocks used in calibration
10
13
read-write
NO_OF_RO_CLKS
2^no_of_ro_clks no of clocks of ro clock counts for no of rc clocks in that time to measure timeperiod
6
10
read-write
PERIODIC_RC_CALIB_EN
periodically calibrate RC timeperiod based rc trigger time sel
22
23
read-write
PERIODIC_RO_CALIB_EN
periodically calibrate RO timeperiod based ro trigger time sel
21
22
read-write
RC_SETTLE_TIME
no of clocks of RO for the RC clk to settle when enabled
13
16
read-write
RC_TRIGGER_TIME_SEL
rc trigger time select
18
21
read-write
RC_XTAL_MUX_SEL
xtal mux select
25
26
read-write
RESERVED1
reser
30
32
read-write
RO_TRIGGER_TIME_SEL
ro trigger time select
16
18
read-write
START_CALIB_RC
to initiate RC calibration
24
25
write-only
START_CALIB_RO
to initiate RO calibration
23
24
write-only
VBATT_TRIGGER_TIME_SEL
trigger to ipmu block for checking vbatt status periodicaly
27
30
read-write
MCU_CAL_TEMP_PROG_REG
temprature program register
0x8
32
read-write
n
0x0
BYPASS_CALIB_PG
To bypass power gating and keep all the blocks always on
0
1
read-write
MAX_TEMP_CHANGE
maximum temperature change after which rc calibration must be trigger
16
21
read-write
PERIODIC_TEMP_CALIB_EN
Enable periodic checking of temperature
23
24
read-write
RESERVED1
reser
1
16
read-only
RESERVED2
reser
25
32
read-only
RTC_TIMER_PERIOD_MUX_SEL
rtc timer period mux select
24
25
read-write
TEMP_TRIGGER_TIME_SEL
temperature trigger time select
21
23
read-write
MCU_CAL_TIMER_CLOCK_PERIOD
MCU calender timer clock period register
0x4
32
read-write
n
0x0
RESERVED1
reser
25
31
read-only
RTC_TIMER_CLK_PERIOD
RTC timer clock period programmed by SOC
0
25
read-write
SPI_RTC_TIMER_CLK_PERIOD_APPLIED
Indicated SOC programmed rtc_timer clock period is applied at KHz clock domain
31
32
read-only
TIMERS
TIMER can be used to generate various timing events for the software
TIMERS
0x0
0x0
0xA0
registers
n
TIMER0
2
TIMER1
3
TIMER2
4
TIMER3
5
MCUULP_TMR_ACTIVE_STATUS
Timer Active Status Register
0x9C
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
TIMER_ACTIVE
Timer active status for each timer. LSB bit specifies the status for 0th timer and so on.
0
4
read-only
Timer_Inative
No Interrupt present
0
Timer_Active
Interrupt present
1
MCUULP_TMR_CNTRL
Timer Control Register
0x4
32
read-write
n
0x0
0x0
COUNTER_UP
For reading/tracking counter in up counting this bit has to be set
7
8
read-write
RESERVED1
reserved1
8
32
read-write
TMR_INTR_CLR
This Bit are Used to clear the timer
1
2
write-only
Clear_Interrupt
Clear interrupt
1
TMR_INTR_ENABLE
This Bit are Used to enable the time out interrupt
2
3
read-write
Disable
Interrupt disable
0
Enable
Interrupt enable
1
TMR_MODE
This Bit are Used to select the mode working of timer
5
6
read-write
Disable
One shot timer
0
Enable
Periodic timer
1
TMR_START
This Bit are Used to start the timer timer gets reset upon setting this bit
0
1
write-only
None
Timer start
1
TMR_STOP
This Bit are Used to stop the timer
6
7
write-only
None
Stops the timer
1
TMR_TYPE
This Bit are Used to select the type of timer
3
5
read-write
COUNT_DOWN_TIMER
Count down timer
0
ONE_MICRO_SECOND
1 Micro second mode
1
256_MICRO_SECOND
256 Micro second mode
2
MCUULP_TMR_INTR_STAT
Timer Status Register
0x80
32
read-write
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
TMR0_INTR_STATUS
This bit indicates status of the interrupt generated by timer 0
0
1
read-write
Interrupt_Absent
No Interrupt present
0
Interrupt_Present
Interrupt present
1
TMR1_INTR_STATUS
This bit indicates status of the interrupt generated by timer 1
1
2
read-write
Interrupt_Absent
No Interrupt present
0
Interrupt_Present
Interrupt present
1
TMR2_INTR_STATUS
This bit indicates status of the interrupt generated by timer 2
2
3
read-write
Interrupt_Absent
No Interrupt present
0
Interrupt_Present
Interrupt present
1
TMR3_INTR_STATUS
This bit indicates status of the interrupt generated by timer 3
3
4
read-write
Interrupt_Absent
No Interrupt present
0
Interrupt_Present
Interrupt present
1
MCUULP_TMR_MATCH
Timer Match Register
0x0
32
read-write
n
0x0
0x0
TMR_MATCH
This bits are used to program the lower significant 16-bits of timer time out value in millisecond or number of system clocks
0
32
read-write
MCUULP_TMR_MS_PERIOD_FRAC
Timer 256 microsecond period Fractional Part Register
0x90
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
TMR_MS_PERIOD_FRAC
This bits are used to program the fractional part of number of clock cycles per 256 microseconds of the system clock used
0
8
read-write
MCUULP_TMR_MS_PERIOD_INT
Timer 256 microsecond period Integral Part Register
0x8C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
16
32
read-only
TMR_MS_PERIOD_INT
This bits are used to program the integer part of number of clock cycles per 256 microseconds of the system clock used
0
16
read-write
MCUULP_TMR_US_PERIOD_FRAC
Timer microsecond period Fractional Part Register
0x88
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
TMR_US_PERIOD_FRAC
This bits are used to program the fractional part of number of clock cycles per microseconds of the system clock used
0
8
read-write
MCUULP_TMR_US_PERIOD_INT
Timer micro second period Integral Part Register
0x84
32
read-write
n
0x0
0x0
RESERVED1
reserved1
16
32
read-only
TMR_US_PERIOD_INT
This bits are used to program the integer part of number of clock cycles per microseconds of the system clock used
0
16
read-write
UART0
Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets
UART_USRT
0x0
0x0
0x100
registers
n
USART1
38
CPR
Component Parameter Register
0xF4
32
read-only
n
ADDITIONAL_FEAT
none
8
9
read-only
AFCE_MODE
none
4
5
read-only
APB_DATA_WIDTH
APB data width register.
0
2
read-only
DMA_EXTRA
none
13
14
read-only
FIFO_ACCESS
none
9
10
read-only
FIFO_MODE
none
16
24
read-only
FIFO_STAT
none
10
11
read-only
RESERVED1
reserved1
2
4
read-only
RESERVED2
reserved2
14
16
read-only
RESERVED3
reserved3
24
32
read-only
SHADOW
none
11
12
read-only
SIR_LP_MODE
none
7
8
read-only
SIR_MODE
none
6
7
read-only
THRE_MODE
none
5
6
read-only
UART_ADD_ENCODED_PARAMS
none
12
13
read-only
CTR
Component Type Register
0xFC
32
read-only
n
0x0
UART_COMP_VER
This register contains the peripherals identification code.
0
32
read-only
DE_EN
Driver Output Enable Register.
0xB0
32
read-write
n
0x0
DE_EN
DE Enable control.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
DLF
Divisor Latch Fraction Register.
0xC0
32
read-write
n
0x0
DLF
Fractional part of divisor.
0
4
read-write
RESERVED1
reserved1
4
32
read-only
DLH
Divisor Latch High
IER
0x4
32
read-write
n
0x0
0x0
DLH
Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DLL
Divisor Latch Low
0x0
32
read-write
n
0x0
0x0
DLL
Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DMASA
DMA Software Acknowledge
0xA8
32
read-write
n
0x0
0x0
DMA_SOFTWARE_ACK
This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition
0
1
write-only
RESERVED1
reserved1
1
32
read-only
DTE
Driver Output Enable Timing Register.
0xB8
32
read-write
n
0x0
DE_ASSERT_TIME
Driver enable assertion time.
0
8
read-write
DE_DE_ASSERT_TIME
Driver enable de-assertion time.
16
24
read-write
RES
reserved.
8
16
RESERVED1
reserved1
24
32
read-only
FAR
none
0x70
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SYNC_MODE
none
0
1
read-write
FIFO_ACCESS_DISABLE
FIFO access mode disabled
0
FIFO_ACCESS_ENABLE
FIFO access mode enabled
1
FCR
FIFO Control Register
0x8
32
write-only
n
0x0
0x0
DMAM
DMA signalling mode
3
4
write-only
Mode0
DMA Signalling mode0
0
Mode1
DMA Signalling mode1
1
FIFOE
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs
0
1
write-only
RESERVED1
reserved1
8
32
write-only
RFIFOR
RCVR FIFO Reset
1
2
write-only
RT
This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated
6
8
write-only
FIFO_1_CHARACTER
1 character in the FIFO
0
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
1
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
2
FIFO_LESS_THAN_2_CHARACTER
FIFO 2 less than full
3
TET
TX Empty Trigger
4
6
write-only
FIFO_EMPTY
FIFO Empty
0
FIFO_2_CHARACTER
2 characters in the FIFO
1
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
2
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
3
XFIFOR
XMIT FIFO Reset
2
3
write-only
HDEN
none
0x40
32
read-write
n
0x0
0x0
FULL_DUPLEX_MODE
none
0
1
read-write
DISABLE
Full duplex mode disable
0
ENABLE
Full duplex mode enable
1
RESERVED1
reserved1
2
32
read-only
TX_MODE_RX_MODE
This signal is valid when full_duplex_mode is disabled
1
2
read-write
tx_mode
tx_mode
0
rx_mode
rx_mode
1
HTX
Halt Transmit
0xA4
32
read-write
n
0x0
0x0
HALT_TX
This register is use to halt transmissions for testing
0
1
read-write
Disabled
Halt TX disabled
0
Enabled
Halt TX enabled
1
RESERVED1
reserved1
1
32
read-only
IER
Interrupt Enable Register
0x4
32
read-write
n
0x0
0x0
EDSSI
Enable Modem Status Interrupt
3
4
read-write
Disable
Modem Status Interrupt is disabled
0
Enable
Modem Status Interrupt is enabled
1
ELSI
Enable Receiver Line Status Interrupt
2
3
read-write
Disable
Receiver Line Status Interrupt is disabled
0
Enable
Receiver Line Status Interrupt is enabled
1
ERBFI
Enable Received Data Available Interrupt
0
1
read-write
Disable
Received Data Available Interrupt is disabled
0
Enable
Received Data Available Interrupt is enabled
1
ETBEI
Enable Transmit Holding Register Empty Interrupt
1
2
read-write
Disable
Transmit Holding Register Empty Interrupt is disabled
0
Enable
Transmit Holding Register Empty Interrupt is enabled
1
PTIME
Programmable THRE Interrupt Mode Enable
7
8
read-write
Disable
generation of THRE Interrupt is disabled
0
Enable
generation of THRE Interrupt is enabled
1
RESERVED1
reserved1
4
7
read-only
RESERVED2
reserved2
8
32
read-only
IIR
Interrupt Identity Register
0x8
32
read-only
n
0x0
FIFOSE
This is used to indicate whether the FIFOs are enabled or disabled.
6
8
read-only
Disable
FIFO is disabled
0
Enable
FIFO is enabled
1
IID
Interrupt ID
0
4
read-only
0000
modem status pending pending interrupt
0
0001
This field indicates no interrupt pending status
1
1100
Character Timeout pending interrupt
12
0010
Transmit Holding Register Empty pending interrupt
2
0100
Received Data Available pending interrupt
4
0110
Receive line status pending interrupt
6
0111
Busy detect pending interrupt
7
RESERVED1
reserved1
4
6
read-only
RESERVED2
reserved2
8
32
read-only
LCR
Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
This is used to cause a break condition to be transmitted to the receiving device
6
7
read-write
SERIAL_OUTPUT_SPACING_STATE
If set to 1, the serial output is forced to the spacing (logic 0) state
0
DLAB
This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART
7
8
read-write
INIT_BAUD_RATE_SET
This bit must be cleared after initial baud rate set up
0
DLS
Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives
0
2
read-write
5_BITS_PER_CHARACTER
5 bits per character
0
6_BITS_PER_CHARACTER
6 bits per character
1
7_BITS_PER_CHARACTER
7 bits per character
2
8_BITS_PER_CHARACTER
8 bits per character
3
EPS
This is used to select between even and odd parity
4
5
read-write
Set to 0
An odd number of logic 1s is transmitted or checked
0
Set to 1
An even number of logic 1s is transmitted or checked
1
PEN
This bit is used to enable and disable parity generation and detection in transmitted and received serial character
3
4
read-write
Disable
Parity disabled
0
Enable
Parity Enabled
1
RESERVED1
reserved1
8
32
read-only
STICK_PARITY
This bit is used to force parity value
5
6
read-write
LOGIC0
When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0
0
LOGIC1
If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1
1
STOP
This is used to select the number of stop bits per character that the peripheral transmits and receives
2
3
read-write
1_STOP_BIT_PER_CHARACTER
1 stop bit per character
0
1.5_OR_2_STOPS_BIT_PER_CHARACTER
1.5 or 2 stop bits per character
1
LCR_EXT
Line Extended Control Register
0xCC
32
read-write
n
0x0
ADDR_MATCH
Address Match Mode.
1
2
read-write
DLS_E
Extension for DLS.
0
1
read-write
RESERVED1
reserved1
4
32
read-only
SEND_ADDR
Send address control bit.
2
3
read-write
TRANSMIT_MODE
Transmit mode control bit.
3
4
read-write
LPDLH
Low Power Divisor Latch High Register
0x24
32
read-write
n
0x0
0x0
LOW_POWER_DLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LPDLL
Low Power Divisor Latch Low Register
0x20
32
read-write
n
0x0
0x0
LOW_POWER_DLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LSR
Line Status Register
0x14
32
read-only
n
0x0
ADDRRCVD
Address Received bit
8
9
read-only
BI
his is used to indicate the detection of a break sequence on the serial input data
4
5
read-only
DR
This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO
0
1
read-only
Disabled
No data Ready
0
Enabled
Data Ready
1
FE
This is used to indicate the occurrence of a framing error in the receiver
3
4
read-only
Disabled
no framing error
0
Enabled
framing error
1
OE
This is used to indicate the occurrence of an overrun error
1
2
read-only
Disabled
no overrun error
0
Enabled
overrun error
1
PE
This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set
2
3
read-only
Disabled
no parity error
0
Enabled
parity error
1
RESERVED1
reserved1
9
32
read-only
RFE
This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO
7
8
read-only
Disabled
no error in RX FIFO
0
Enabled
error in RX FIFO
1
TEMT
Transmitter Empty bit
6
7
read-only
THRE
Transmit Holding Register Empty bit
5
6
read-only
MCR
Modem Control Register
0x10
32
read-write
n
0x0
0x0
AFCE
This is used to directly control the user-designated Output2 (out2_n) output
5
6
read-write
Disabled
Auto Flow Control Mode disabled
0
Enabled
Auto Flow Control Mode enabled
1
DTR
This is used to directly control the Data Terminal Ready (dtr_n) output
0
1
read-write
DTR_LOGIC1
dtr_n de-asserted (logic 1)
0
DTR_LOGIC0
dtr_n asserted (logic 0)
1
LB
This is used to put the UART into a diagnostic mode for test purposes
4
5
read-write
OUT1
This is used to directly control the user-designated Output1 (out1_n) output
2
3
read-write
OUT1_LOGIC1
out1_n de-asserted (logic 1)
0
OUT1_LOGIC0
out1_n asserted (logic 0)
1
OUT2
This is used to directly control the user-designated Output2 (out2_n) output
3
4
read-write
OUT2_LOGIC1
out2_n de-asserted (logic 1)
0
OUT2_LOGIC0
out2_n asserted (logic 0)
1
RESERVED1
reserved1
7
32
read-only
RTS
This is used to directly control the Request to Send (rts_n) output
1
2
read-write
SIRE
This is used to enable/disable the IrDA SIR Mode features
6
7
read-write
Disabled
IrDA SIR Mode disabled
0
Enabled
IrDA SIR Mode enabled
1
MSR
Modem Status Register
0x18
32
read-only
n
0x0
0x0
CTS
This is used to indicate the current state of the modem control line cts_n
4
5
read-only
Disabled
cts_n input is de-asserted (logic 1)
0
Enabled
cts_n input is asserted (logic 0)
1
DCD
This is used to indicate the current state of the modem control line dcd_n
7
8
read-only
Disabled
dcd_n input is de-asserted (logic 1)
0
Enabled
dcd_n input is asserted (logic 0)
1
DCTS
This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read
0
1
read-only
Disabled
no change on cts_n since last read of MSR
0
Enabled
change on cts_n since last read of MSR
1
DDCD
This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read
3
4
read-only
Disabled
no change on dcd_n since last read of MSR
0
Enabled
change on dcd_n since last read of MSR
1
DDSR
This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read
1
2
read-only
Disabled
no change on dsr_n since last read of MSR
0
Enabled
change on dsr_n since last read of MSR
1
DSR
This is used to indicate the current state of the modem control line dsr_n
5
6
read-only
Disabled
dsr_n input is de-asserted (logic 1)
0
Enabled
dsr_n input is asserted (logic 0)
1
RESERVED1
reserved1
8
32
read-only
RI
This is used to indicate the current state of the modem control line ri_n
6
7
read-only
Disabled
ri_n input is de-asserted (logic 1)
0
Enabled
ri_n input is asserted (logic 0)
1
TERI
This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read
2
3
read-only
Disabled
no change on ri_n since last read of MSR
0
Enabled
change on ri_n since last read of MSR
1
RAR
Receive Address Register.
0xC4
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
RBR
Receive Buffer Register
DLL
0x0
32
read-only
n
0x0
0x0
RBR
Receive Buffer Field
0
8
read-only
RESERVED1
reserved1
8
32
read-only
RE_EN
Receiver Output Enable Register.
0xB4
32
read-write
n
0x0
RESERVED1
reserved1
1
32
read-only
RE_EN
RE Enable control.
0
1
read-write
RFL
Receive FIFO Level
0x84
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
RFW
none
0x78
32
read-write
n
0x0
RESERVED1
reserved1
10
32
read-only
RFFE
Receive FIFO Framing Error
9
10
read-write
RFPE
Receive FIFO Parity Error
8
9
read-write
RFWD
Receive FIFO Write Data
0
8
read-write
SBCR
Shadow Break Control Register
0x90
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SBCR
Shadow Break Control Bit
0
1
read-write
SCR
Scratch pad Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose
0
8
read-write
SDMAM
Shadow DMA Mode
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SDMAM
Shadow DMA Mode
0
1
read-write
MODE0
mode 0
0
MODE1
mode 1
1
SFE
Shadow FIFO Enable
0x98
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SFE
Shadow FIFO Enable
0
1
read-write
SMCR
none
0x58
32
read-write
n
0x0
0x0
CONTI_CLK_MODE
none
4
5
read-write
NON_CONTINUOUS_CLK_MODE
Non-continuous clock mode
0
CONTINUOUS_CLK_MODE
Continuous clock mode
1
MST_MODE
none
1
2
read-write
NON_MST_MODE
Non-MST mode
0
MST_MODE
MST mode
1
RESERVED1
reserved1
6
32
read-only
START_STOP_EN
none
5
6
read-write
DISABLE_START_STOP
Disable start stop
0
ENABLE_START_STOP
Enable start stop
1
SYNC_MODE
none
0
1
read-write
NON_SYNC_MODE
Non-Sync mode
0
SYNC_MODE
Sync mode
1
SRR
Software Reset Register
0x88
32
write-only
n
0x0
RESERVED1
reserved1
3
32
write-only
RFR
RCVR FIFO Reset
1
2
write-only
UR
UART Reset
0
1
write-only
XFR
XMIT FIFO Reset
2
3
write-only
SRT
Shadow RCVR Trigger
0x9C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
SRT
Shadow RCVR Trigger
0
2
read-write
SRTS
Shadow Request to Send
0x8C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SRTS
Shadow Request to Send.
0
1
read-write
STET
Shadow TX Empty Trigger
0xA0
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
STET
Shadow TX Empty Trigger
0
2
read-write
TAR
Transmit Address Register.
0xC8
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
TAT
TurnAround Timing Register
0xBC
32
read-write
n
0x0
DE_RE
Driver Enable to Receiver Enable TurnAround time.
0
16
read-write
RE_DE
Receiver Enable to Driver Enable TurnAround time.
16
32
read-write
TCR
Transceiver Control Register.
0xAC
32
read-write
n
0x0
DE_POL
Driver Enable Polarity.
2
3
read-write
RESERVED1
reserved1
5
32
read-only
RE_POL
Receiver Enable Polarity.
1
2
read-write
RS485_EN
RS485 Transfer Enable.
0
1
read-write
XFER_MODE
Transfer Mode.
3
5
read-write
TFL
Transmit FIFO Level
0x80
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
TFR
none
0x74
32
read-only
n
0x0
RESERVED1
reserved1
8
32
read-only
TX_FIFO_RD
Transmit FIFO Read
0
8
read-only
THR
Transmit Holding Register
DLL
0x0
32
write-only
n
0x0
0x0
RESERVED1
reserved1
8
32
write-only
THR
Data to be transmitted on serial output port
0
8
write-only
UCV
UART Component Version
0xF8
32
read-only
n
0x0
UART_COMP_VER
ASCII value for each number in the version, followed by *
0
32
read-only
USR
UART Status Register
0x7C
32
read-only
n
0x0
BUSY
Indicates that a serial transfer is in progress
0
1
read-only
Disabled
UART is idle or inactive
0
Enabled
UART is busy (actively transferring data)
1
RESERVED1
reserved1
5
32
read-only
RFE
To Indicate that the receive FIFO is completely full
4
5
read-only
Disabled
Receive FIFO not full
0
Enabled
Receive FIFO Full
1
RFNE
To Indicate that the receive FIFO contains one or more entries
3
4
read-only
Disabled
Receive FIFO is empty
0
Enabled
Receive FIFO is not empty
1
TFE
To Indicate that the transmit FIFO is completely empty
2
3
read-only
Disabled
Transmit FIFO is not empty
0
Enabled
Transmit FIFO is empty
1
TFNF
To Indicate that the transmit FIFO is not full
1
2
read-only
Disabled
Transmit FIFO is full
0
Enabled
Transmit FIFO is not full
1
UART1
Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets
UART_USRT
0x0
0x0
0x100
registers
n
USART2
39
CPR
Component Parameter Register
0xF4
32
read-only
n
ADDITIONAL_FEAT
none
8
9
read-only
AFCE_MODE
none
4
5
read-only
APB_DATA_WIDTH
APB data width register.
0
2
read-only
DMA_EXTRA
none
13
14
read-only
FIFO_ACCESS
none
9
10
read-only
FIFO_MODE
none
16
24
read-only
FIFO_STAT
none
10
11
read-only
RESERVED1
reserved1
2
4
read-only
RESERVED2
reserved2
14
16
read-only
RESERVED3
reserved3
24
32
read-only
SHADOW
none
11
12
read-only
SIR_LP_MODE
none
7
8
read-only
SIR_MODE
none
6
7
read-only
THRE_MODE
none
5
6
read-only
UART_ADD_ENCODED_PARAMS
none
12
13
read-only
CTR
Component Type Register
0xFC
32
read-only
n
0x0
UART_COMP_VER
This register contains the peripherals identification code.
0
32
read-only
DE_EN
Driver Output Enable Register.
0xB0
32
read-write
n
0x0
DE_EN
DE Enable control.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
DLF
Divisor Latch Fraction Register.
0xC0
32
read-write
n
0x0
DLF
Fractional part of divisor.
0
4
read-write
RESERVED1
reserved1
4
32
read-only
DLH
Divisor Latch High
IER
0x4
32
read-write
n
0x0
0x0
DLH
Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DLL
Divisor Latch Low
0x0
32
read-write
n
0x0
0x0
DLL
Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DMASA
DMA Software Acknowledge
0xA8
32
read-write
n
0x0
0x0
DMA_SOFTWARE_ACK
This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition
0
1
write-only
RESERVED1
reserved1
1
32
read-only
DTE
Driver Output Enable Timing Register.
0xB8
32
read-write
n
0x0
DE_ASSERT_TIME
Driver enable assertion time.
0
8
read-write
DE_DE_ASSERT_TIME
Driver enable de-assertion time.
16
24
read-write
RES
reserved.
8
16
RESERVED1
reserved1
24
32
read-only
FAR
none
0x70
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SYNC_MODE
none
0
1
read-write
FIFO_ACCESS_DISABLE
FIFO access mode disabled
0
FIFO_ACCESS_ENABLE
FIFO access mode enabled
1
FCR
FIFO Control Register
0x8
32
write-only
n
0x0
0x0
DMAM
DMA signalling mode
3
4
write-only
Mode0
DMA Signalling mode0
0
Mode1
DMA Signalling mode1
1
FIFOE
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs
0
1
write-only
RESERVED1
reserved1
8
32
write-only
RFIFOR
RCVR FIFO Reset
1
2
write-only
RT
This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated
6
8
write-only
FIFO_1_CHARACTER
1 character in the FIFO
0
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
1
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
2
FIFO_LESS_THAN_2_CHARACTER
FIFO 2 less than full
3
TET
TX Empty Trigger
4
6
write-only
FIFO_EMPTY
FIFO Empty
0
FIFO_2_CHARACTER
2 characters in the FIFO
1
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
2
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
3
XFIFOR
XMIT FIFO Reset
2
3
write-only
HDEN
none
0x40
32
read-write
n
0x0
0x0
FULL_DUPLEX_MODE
none
0
1
read-write
DISABLE
Full duplex mode disable
0
ENABLE
Full duplex mode enable
1
RESERVED1
reserved1
2
32
read-only
TX_MODE_RX_MODE
This signal is valid when full_duplex_mode is disabled
1
2
read-write
tx_mode
tx_mode
0
rx_mode
rx_mode
1
HTX
Halt Transmit
0xA4
32
read-write
n
0x0
0x0
HALT_TX
This register is use to halt transmissions for testing
0
1
read-write
Disabled
Halt TX disabled
0
Enabled
Halt TX enabled
1
RESERVED1
reserved1
1
32
read-only
IER
Interrupt Enable Register
0x4
32
read-write
n
0x0
0x0
EDSSI
Enable Modem Status Interrupt
3
4
read-write
Disable
Modem Status Interrupt is disabled
0
Enable
Modem Status Interrupt is enabled
1
ELSI
Enable Receiver Line Status Interrupt
2
3
read-write
Disable
Receiver Line Status Interrupt is disabled
0
Enable
Receiver Line Status Interrupt is enabled
1
ERBFI
Enable Received Data Available Interrupt
0
1
read-write
Disable
Received Data Available Interrupt is disabled
0
Enable
Received Data Available Interrupt is enabled
1
ETBEI
Enable Transmit Holding Register Empty Interrupt
1
2
read-write
Disable
Transmit Holding Register Empty Interrupt is disabled
0
Enable
Transmit Holding Register Empty Interrupt is enabled
1
PTIME
Programmable THRE Interrupt Mode Enable
7
8
read-write
Disable
generation of THRE Interrupt is disabled
0
Enable
generation of THRE Interrupt is enabled
1
RESERVED1
reserved1
4
7
read-only
RESERVED2
reserved2
8
32
read-only
IIR
Interrupt Identity Register
0x8
32
read-only
n
0x0
FIFOSE
This is used to indicate whether the FIFOs are enabled or disabled.
6
8
read-only
Disable
FIFO is disabled
0
Enable
FIFO is enabled
1
IID
Interrupt ID
0
4
read-only
0000
modem status pending pending interrupt
0
0001
This field indicates no interrupt pending status
1
1100
Character Timeout pending interrupt
12
0010
Transmit Holding Register Empty pending interrupt
2
0100
Received Data Available pending interrupt
4
0110
Receive line status pending interrupt
6
0111
Busy detect pending interrupt
7
RESERVED1
reserved1
4
6
read-only
RESERVED2
reserved2
8
32
read-only
LCR
Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
This is used to cause a break condition to be transmitted to the receiving device
6
7
read-write
SERIAL_OUTPUT_SPACING_STATE
If set to 1, the serial output is forced to the spacing (logic 0) state
0
DLAB
This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART
7
8
read-write
INIT_BAUD_RATE_SET
This bit must be cleared after initial baud rate set up
0
DLS
Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives
0
2
read-write
5_BITS_PER_CHARACTER
5 bits per character
0
6_BITS_PER_CHARACTER
6 bits per character
1
7_BITS_PER_CHARACTER
7 bits per character
2
8_BITS_PER_CHARACTER
8 bits per character
3
EPS
This is used to select between even and odd parity
4
5
read-write
Set to 0
An odd number of logic 1s is transmitted or checked
0
Set to 1
An even number of logic 1s is transmitted or checked
1
PEN
This bit is used to enable and disable parity generation and detection in transmitted and received serial character
3
4
read-write
Disable
Parity disabled
0
Enable
Parity Enabled
1
RESERVED1
reserved1
8
32
read-only
STICK_PARITY
This bit is used to force parity value
5
6
read-write
LOGIC0
When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0
0
LOGIC1
If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1
1
STOP
This is used to select the number of stop bits per character that the peripheral transmits and receives
2
3
read-write
1_STOP_BIT_PER_CHARACTER
1 stop bit per character
0
1.5_OR_2_STOPS_BIT_PER_CHARACTER
1.5 or 2 stop bits per character
1
LCR_EXT
Line Extended Control Register
0xCC
32
read-write
n
0x0
ADDR_MATCH
Address Match Mode.
1
2
read-write
DLS_E
Extension for DLS.
0
1
read-write
RESERVED1
reserved1
4
32
read-only
SEND_ADDR
Send address control bit.
2
3
read-write
TRANSMIT_MODE
Transmit mode control bit.
3
4
read-write
LPDLH
Low Power Divisor Latch High Register
0x24
32
read-write
n
0x0
0x0
LOW_POWER_DLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LPDLL
Low Power Divisor Latch Low Register
0x20
32
read-write
n
0x0
0x0
LOW_POWER_DLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LSR
Line Status Register
0x14
32
read-only
n
0x0
ADDRRCVD
Address Received bit
8
9
read-only
BI
his is used to indicate the detection of a break sequence on the serial input data
4
5
read-only
DR
This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO
0
1
read-only
Disabled
No data Ready
0
Enabled
Data Ready
1
FE
This is used to indicate the occurrence of a framing error in the receiver
3
4
read-only
Disabled
no framing error
0
Enabled
framing error
1
OE
This is used to indicate the occurrence of an overrun error
1
2
read-only
Disabled
no overrun error
0
Enabled
overrun error
1
PE
This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set
2
3
read-only
Disabled
no parity error
0
Enabled
parity error
1
RESERVED1
reserved1
9
32
read-only
RFE
This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO
7
8
read-only
Disabled
no error in RX FIFO
0
Enabled
error in RX FIFO
1
TEMT
Transmitter Empty bit
6
7
read-only
THRE
Transmit Holding Register Empty bit
5
6
read-only
MCR
Modem Control Register
0x10
32
read-write
n
0x0
0x0
AFCE
This is used to directly control the user-designated Output2 (out2_n) output
5
6
read-write
Disabled
Auto Flow Control Mode disabled
0
Enabled
Auto Flow Control Mode enabled
1
DTR
This is used to directly control the Data Terminal Ready (dtr_n) output
0
1
read-write
DTR_LOGIC1
dtr_n de-asserted (logic 1)
0
DTR_LOGIC0
dtr_n asserted (logic 0)
1
LB
This is used to put the UART into a diagnostic mode for test purposes
4
5
read-write
OUT1
This is used to directly control the user-designated Output1 (out1_n) output
2
3
read-write
OUT1_LOGIC1
out1_n de-asserted (logic 1)
0
OUT1_LOGIC0
out1_n asserted (logic 0)
1
OUT2
This is used to directly control the user-designated Output2 (out2_n) output
3
4
read-write
OUT2_LOGIC1
out2_n de-asserted (logic 1)
0
OUT2_LOGIC0
out2_n asserted (logic 0)
1
RESERVED1
reserved1
7
32
read-only
RTS
This is used to directly control the Request to Send (rts_n) output
1
2
read-write
SIRE
This is used to enable/disable the IrDA SIR Mode features
6
7
read-write
Disabled
IrDA SIR Mode disabled
0
Enabled
IrDA SIR Mode enabled
1
MSR
Modem Status Register
0x18
32
read-only
n
0x0
0x0
CTS
This is used to indicate the current state of the modem control line cts_n
4
5
read-only
Disabled
cts_n input is de-asserted (logic 1)
0
Enabled
cts_n input is asserted (logic 0)
1
DCD
This is used to indicate the current state of the modem control line dcd_n
7
8
read-only
Disabled
dcd_n input is de-asserted (logic 1)
0
Enabled
dcd_n input is asserted (logic 0)
1
DCTS
This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read
0
1
read-only
Disabled
no change on cts_n since last read of MSR
0
Enabled
change on cts_n since last read of MSR
1
DDCD
This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read
3
4
read-only
Disabled
no change on dcd_n since last read of MSR
0
Enabled
change on dcd_n since last read of MSR
1
DDSR
This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read
1
2
read-only
Disabled
no change on dsr_n since last read of MSR
0
Enabled
change on dsr_n since last read of MSR
1
DSR
This is used to indicate the current state of the modem control line dsr_n
5
6
read-only
Disabled
dsr_n input is de-asserted (logic 1)
0
Enabled
dsr_n input is asserted (logic 0)
1
RESERVED1
reserved1
8
32
read-only
RI
This is used to indicate the current state of the modem control line ri_n
6
7
read-only
Disabled
ri_n input is de-asserted (logic 1)
0
Enabled
ri_n input is asserted (logic 0)
1
TERI
This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read
2
3
read-only
Disabled
no change on ri_n since last read of MSR
0
Enabled
change on ri_n since last read of MSR
1
RAR
Receive Address Register.
0xC4
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
RBR
Receive Buffer Register
DLL
0x0
32
read-only
n
0x0
0x0
RBR
Receive Buffer Field
0
8
read-only
RESERVED1
reserved1
8
32
read-only
RE_EN
Receiver Output Enable Register.
0xB4
32
read-write
n
0x0
RESERVED1
reserved1
1
32
read-only
RE_EN
RE Enable control.
0
1
read-write
RFL
Receive FIFO Level
0x84
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
RFW
none
0x78
32
read-write
n
0x0
RESERVED1
reserved1
10
32
read-only
RFFE
Receive FIFO Framing Error
9
10
read-write
RFPE
Receive FIFO Parity Error
8
9
read-write
RFWD
Receive FIFO Write Data
0
8
read-write
SBCR
Shadow Break Control Register
0x90
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SBCR
Shadow Break Control Bit
0
1
read-write
SCR
Scratch pad Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose
0
8
read-write
SDMAM
Shadow DMA Mode
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SDMAM
Shadow DMA Mode
0
1
read-write
MODE0
mode 0
0
MODE1
mode 1
1
SFE
Shadow FIFO Enable
0x98
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SFE
Shadow FIFO Enable
0
1
read-write
SMCR
none
0x58
32
read-write
n
0x0
0x0
CONTI_CLK_MODE
none
4
5
read-write
NON_CONTINUOUS_CLK_MODE
Non-continuous clock mode
0
CONTINUOUS_CLK_MODE
Continuous clock mode
1
MST_MODE
none
1
2
read-write
NON_MST_MODE
Non-MST mode
0
MST_MODE
MST mode
1
RESERVED1
reserved1
6
32
read-only
START_STOP_EN
none
5
6
read-write
DISABLE_START_STOP
Disable start stop
0
ENABLE_START_STOP
Enable start stop
1
SYNC_MODE
none
0
1
read-write
NON_SYNC_MODE
Non-Sync mode
0
SYNC_MODE
Sync mode
1
SRR
Software Reset Register
0x88
32
write-only
n
0x0
RESERVED1
reserved1
3
32
write-only
RFR
RCVR FIFO Reset
1
2
write-only
UR
UART Reset
0
1
write-only
XFR
XMIT FIFO Reset
2
3
write-only
SRT
Shadow RCVR Trigger
0x9C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
SRT
Shadow RCVR Trigger
0
2
read-write
SRTS
Shadow Request to Send
0x8C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SRTS
Shadow Request to Send.
0
1
read-write
STET
Shadow TX Empty Trigger
0xA0
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
STET
Shadow TX Empty Trigger
0
2
read-write
TAR
Transmit Address Register.
0xC8
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
TAT
TurnAround Timing Register
0xBC
32
read-write
n
0x0
DE_RE
Driver Enable to Receiver Enable TurnAround time.
0
16
read-write
RE_DE
Receiver Enable to Driver Enable TurnAround time.
16
32
read-write
TCR
Transceiver Control Register.
0xAC
32
read-write
n
0x0
DE_POL
Driver Enable Polarity.
2
3
read-write
RESERVED1
reserved1
5
32
read-only
RE_POL
Receiver Enable Polarity.
1
2
read-write
RS485_EN
RS485 Transfer Enable.
0
1
read-write
XFER_MODE
Transfer Mode.
3
5
read-write
TFL
Transmit FIFO Level
0x80
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
TFR
none
0x74
32
read-only
n
0x0
RESERVED1
reserved1
8
32
read-only
TX_FIFO_RD
Transmit FIFO Read
0
8
read-only
THR
Transmit Holding Register
DLL
0x0
32
write-only
n
0x0
0x0
RESERVED1
reserved1
8
32
write-only
THR
Data to be transmitted on serial output port
0
8
write-only
UCV
UART Component Version
0xF8
32
read-only
n
0x0
UART_COMP_VER
ASCII value for each number in the version, followed by *
0
32
read-only
USR
UART Status Register
0x7C
32
read-only
n
0x0
BUSY
Indicates that a serial transfer is in progress
0
1
read-only
Disabled
UART is idle or inactive
0
Enabled
UART is busy (actively transferring data)
1
RESERVED1
reserved1
5
32
read-only
RFE
To Indicate that the receive FIFO is completely full
4
5
read-only
Disabled
Receive FIFO not full
0
Enabled
Receive FIFO Full
1
RFNE
To Indicate that the receive FIFO contains one or more entries
3
4
read-only
Disabled
Receive FIFO is empty
0
Enabled
Receive FIFO is not empty
1
TFE
To Indicate that the transmit FIFO is completely empty
2
3
read-only
Disabled
Transmit FIFO is not empty
0
Enabled
Transmit FIFO is empty
1
TFNF
To Indicate that the transmit FIFO is not full
1
2
read-only
Disabled
Transmit FIFO is full
0
Enabled
Transmit FIFO is not full
1
UART2
Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets
UART_USRT
0x0
0x0
0x100
registers
n
USART1
38
CPR
Component Parameter Register
0xF4
32
read-only
n
ADDITIONAL_FEAT
none
8
9
read-only
AFCE_MODE
none
4
5
read-only
APB_DATA_WIDTH
APB data width register.
0
2
read-only
DMA_EXTRA
none
13
14
read-only
FIFO_ACCESS
none
9
10
read-only
FIFO_MODE
none
16
24
read-only
FIFO_STAT
none
10
11
read-only
RESERVED1
reserved1
2
4
read-only
RESERVED2
reserved2
14
16
read-only
RESERVED3
reserved3
24
32
read-only
SHADOW
none
11
12
read-only
SIR_LP_MODE
none
7
8
read-only
SIR_MODE
none
6
7
read-only
THRE_MODE
none
5
6
read-only
UART_ADD_ENCODED_PARAMS
none
12
13
read-only
CTR
Component Type Register
0xFC
32
read-only
n
0x0
UART_COMP_VER
This register contains the peripherals identification code.
0
32
read-only
DE_EN
Driver Output Enable Register.
0xB0
32
read-write
n
0x0
DE_EN
DE Enable control.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
DLF
Divisor Latch Fraction Register.
0xC0
32
read-write
n
0x0
DLF
Fractional part of divisor.
0
4
read-write
RESERVED1
reserved1
4
32
read-only
DLH
Divisor Latch High
IER
0x4
32
read-write
n
0x0
0x0
DLH
Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DLL
Divisor Latch Low
0x0
32
read-write
n
0x0
0x0
DLL
Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DMASA
DMA Software Acknowledge
0xA8
32
read-write
n
0x0
0x0
DMA_SOFTWARE_ACK
This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition
0
1
write-only
RESERVED1
reserved1
1
32
read-only
DTE
Driver Output Enable Timing Register.
0xB8
32
read-write
n
0x0
DE_ASSERT_TIME
Driver enable assertion time.
0
8
read-write
DE_DE_ASSERT_TIME
Driver enable de-assertion time.
16
24
read-write
RES
reserved.
8
16
RESERVED1
reserved1
24
32
read-only
FAR
none
0x70
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SYNC_MODE
none
0
1
read-write
FIFO_ACCESS_DISABLE
FIFO access mode disabled
0
FIFO_ACCESS_ENABLE
FIFO access mode enabled
1
FCR
FIFO Control Register
0x8
32
write-only
n
0x0
0x0
DMAM
DMA signalling mode
3
4
write-only
Mode0
DMA Signalling mode0
0
Mode1
DMA Signalling mode1
1
FIFOE
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs
0
1
write-only
RESERVED1
reserved1
8
32
write-only
RFIFOR
RCVR FIFO Reset
1
2
write-only
RT
This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated
6
8
write-only
FIFO_1_CHARACTER
1 character in the FIFO
0
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
1
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
2
FIFO_LESS_THAN_2_CHARACTER
FIFO 2 less than full
3
TET
TX Empty Trigger
4
6
write-only
FIFO_EMPTY
FIFO Empty
0
FIFO_2_CHARACTER
2 characters in the FIFO
1
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
2
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
3
XFIFOR
XMIT FIFO Reset
2
3
write-only
HDEN
none
0x40
32
read-write
n
0x0
0x0
FULL_DUPLEX_MODE
none
0
1
read-write
DISABLE
Full duplex mode disable
0
ENABLE
Full duplex mode enable
1
RESERVED1
reserved1
2
32
read-only
TX_MODE_RX_MODE
This signal is valid when full_duplex_mode is disabled
1
2
read-write
tx_mode
tx_mode
0
rx_mode
rx_mode
1
HTX
Halt Transmit
0xA4
32
read-write
n
0x0
0x0
HALT_TX
This register is use to halt transmissions for testing
0
1
read-write
Disabled
Halt TX disabled
0
Enabled
Halt TX enabled
1
RESERVED1
reserved1
1
32
read-only
IER
Interrupt Enable Register
0x4
32
read-write
n
0x0
0x0
EDSSI
Enable Modem Status Interrupt
3
4
read-write
Disable
Modem Status Interrupt is disabled
0
Enable
Modem Status Interrupt is enabled
1
ELSI
Enable Receiver Line Status Interrupt
2
3
read-write
Disable
Receiver Line Status Interrupt is disabled
0
Enable
Receiver Line Status Interrupt is enabled
1
ERBFI
Enable Received Data Available Interrupt
0
1
read-write
Disable
Received Data Available Interrupt is disabled
0
Enable
Received Data Available Interrupt is enabled
1
ETBEI
Enable Transmit Holding Register Empty Interrupt
1
2
read-write
Disable
Transmit Holding Register Empty Interrupt is disabled
0
Enable
Transmit Holding Register Empty Interrupt is enabled
1
PTIME
Programmable THRE Interrupt Mode Enable
7
8
read-write
Disable
generation of THRE Interrupt is disabled
0
Enable
generation of THRE Interrupt is enabled
1
RESERVED1
reserved1
4
7
read-only
RESERVED2
reserved2
8
32
read-only
IIR
Interrupt Identity Register
0x8
32
read-only
n
0x0
FIFOSE
This is used to indicate whether the FIFOs are enabled or disabled.
6
8
read-only
Disable
FIFO is disabled
0
Enable
FIFO is enabled
1
IID
Interrupt ID
0
4
read-only
0000
modem status pending pending interrupt
0
0001
This field indicates no interrupt pending status
1
1100
Character Timeout pending interrupt
12
0010
Transmit Holding Register Empty pending interrupt
2
0100
Received Data Available pending interrupt
4
0110
Receive line status pending interrupt
6
0111
Busy detect pending interrupt
7
RESERVED1
reserved1
4
6
read-only
RESERVED2
reserved2
8
32
read-only
LCR
Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
This is used to cause a break condition to be transmitted to the receiving device
6
7
read-write
SERIAL_OUTPUT_SPACING_STATE
If set to 1, the serial output is forced to the spacing (logic 0) state
0
DLAB
This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART
7
8
read-write
INIT_BAUD_RATE_SET
This bit must be cleared after initial baud rate set up
0
DLS
Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives
0
2
read-write
5_BITS_PER_CHARACTER
5 bits per character
0
6_BITS_PER_CHARACTER
6 bits per character
1
7_BITS_PER_CHARACTER
7 bits per character
2
8_BITS_PER_CHARACTER
8 bits per character
3
EPS
This is used to select between even and odd parity
4
5
read-write
Set to 0
An odd number of logic 1s is transmitted or checked
0
Set to 1
An even number of logic 1s is transmitted or checked
1
PEN
This bit is used to enable and disable parity generation and detection in transmitted and received serial character
3
4
read-write
Disable
Parity disabled
0
Enable
Parity Enabled
1
RESERVED1
reserved1
8
32
read-only
STICK_PARITY
This bit is used to force parity value
5
6
read-write
LOGIC0
When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0
0
LOGIC1
If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1
1
STOP
This is used to select the number of stop bits per character that the peripheral transmits and receives
2
3
read-write
1_STOP_BIT_PER_CHARACTER
1 stop bit per character
0
1.5_OR_2_STOPS_BIT_PER_CHARACTER
1.5 or 2 stop bits per character
1
LCR_EXT
Line Extended Control Register
0xCC
32
read-write
n
0x0
ADDR_MATCH
Address Match Mode.
1
2
read-write
DLS_E
Extension for DLS.
0
1
read-write
RESERVED1
reserved1
4
32
read-only
SEND_ADDR
Send address control bit.
2
3
read-write
TRANSMIT_MODE
Transmit mode control bit.
3
4
read-write
LPDLH
Low Power Divisor Latch High Register
0x24
32
read-write
n
0x0
0x0
LOW_POWER_DLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LPDLL
Low Power Divisor Latch Low Register
0x20
32
read-write
n
0x0
0x0
LOW_POWER_DLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LSR
Line Status Register
0x14
32
read-only
n
0x0
ADDRRCVD
Address Received bit
8
9
read-only
BI
his is used to indicate the detection of a break sequence on the serial input data
4
5
read-only
DR
This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO
0
1
read-only
Disabled
No data Ready
0
Enabled
Data Ready
1
FE
This is used to indicate the occurrence of a framing error in the receiver
3
4
read-only
Disabled
no framing error
0
Enabled
framing error
1
OE
This is used to indicate the occurrence of an overrun error
1
2
read-only
Disabled
no overrun error
0
Enabled
overrun error
1
PE
This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set
2
3
read-only
Disabled
no parity error
0
Enabled
parity error
1
RESERVED1
reserved1
9
32
read-only
RFE
This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO
7
8
read-only
Disabled
no error in RX FIFO
0
Enabled
error in RX FIFO
1
TEMT
Transmitter Empty bit
6
7
read-only
THRE
Transmit Holding Register Empty bit
5
6
read-only
MCR
Modem Control Register
0x10
32
read-write
n
0x0
0x0
AFCE
This is used to directly control the user-designated Output2 (out2_n) output
5
6
read-write
Disabled
Auto Flow Control Mode disabled
0
Enabled
Auto Flow Control Mode enabled
1
DTR
This is used to directly control the Data Terminal Ready (dtr_n) output
0
1
read-write
DTR_LOGIC1
dtr_n de-asserted (logic 1)
0
DTR_LOGIC0
dtr_n asserted (logic 0)
1
LB
This is used to put the UART into a diagnostic mode for test purposes
4
5
read-write
OUT1
This is used to directly control the user-designated Output1 (out1_n) output
2
3
read-write
OUT1_LOGIC1
out1_n de-asserted (logic 1)
0
OUT1_LOGIC0
out1_n asserted (logic 0)
1
OUT2
This is used to directly control the user-designated Output2 (out2_n) output
3
4
read-write
OUT2_LOGIC1
out2_n de-asserted (logic 1)
0
OUT2_LOGIC0
out2_n asserted (logic 0)
1
RESERVED1
reserved1
7
32
read-only
RTS
This is used to directly control the Request to Send (rts_n) output
1
2
read-write
SIRE
This is used to enable/disable the IrDA SIR Mode features
6
7
read-write
Disabled
IrDA SIR Mode disabled
0
Enabled
IrDA SIR Mode enabled
1
MSR
Modem Status Register
0x18
32
read-only
n
0x0
0x0
CTS
This is used to indicate the current state of the modem control line cts_n
4
5
read-only
Disabled
cts_n input is de-asserted (logic 1)
0
Enabled
cts_n input is asserted (logic 0)
1
DCD
This is used to indicate the current state of the modem control line dcd_n
7
8
read-only
Disabled
dcd_n input is de-asserted (logic 1)
0
Enabled
dcd_n input is asserted (logic 0)
1
DCTS
This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read
0
1
read-only
Disabled
no change on cts_n since last read of MSR
0
Enabled
change on cts_n since last read of MSR
1
DDCD
This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read
3
4
read-only
Disabled
no change on dcd_n since last read of MSR
0
Enabled
change on dcd_n since last read of MSR
1
DDSR
This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read
1
2
read-only
Disabled
no change on dsr_n since last read of MSR
0
Enabled
change on dsr_n since last read of MSR
1
DSR
This is used to indicate the current state of the modem control line dsr_n
5
6
read-only
Disabled
dsr_n input is de-asserted (logic 1)
0
Enabled
dsr_n input is asserted (logic 0)
1
RESERVED1
reserved1
8
32
read-only
RI
This is used to indicate the current state of the modem control line ri_n
6
7
read-only
Disabled
ri_n input is de-asserted (logic 1)
0
Enabled
ri_n input is asserted (logic 0)
1
TERI
This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read
2
3
read-only
Disabled
no change on ri_n since last read of MSR
0
Enabled
change on ri_n since last read of MSR
1
RAR
Receive Address Register.
0xC4
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
RBR
Receive Buffer Register
DLL
0x0
32
read-only
n
0x0
0x0
RBR
Receive Buffer Field
0
8
read-only
RESERVED1
reserved1
8
32
read-only
RE_EN
Receiver Output Enable Register.
0xB4
32
read-write
n
0x0
RESERVED1
reserved1
1
32
read-only
RE_EN
RE Enable control.
0
1
read-write
RFL
Receive FIFO Level
0x84
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
RFW
none
0x78
32
read-write
n
0x0
RESERVED1
reserved1
10
32
read-only
RFFE
Receive FIFO Framing Error
9
10
read-write
RFPE
Receive FIFO Parity Error
8
9
read-write
RFWD
Receive FIFO Write Data
0
8
read-write
SBCR
Shadow Break Control Register
0x90
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SBCR
Shadow Break Control Bit
0
1
read-write
SCR
Scratch pad Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose
0
8
read-write
SDMAM
Shadow DMA Mode
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SDMAM
Shadow DMA Mode
0
1
read-write
MODE0
mode 0
0
MODE1
mode 1
1
SFE
Shadow FIFO Enable
0x98
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SFE
Shadow FIFO Enable
0
1
read-write
SMCR
none
0x58
32
read-write
n
0x0
0x0
CONTI_CLK_MODE
none
4
5
read-write
NON_CONTINUOUS_CLK_MODE
Non-continuous clock mode
0
CONTINUOUS_CLK_MODE
Continuous clock mode
1
MST_MODE
none
1
2
read-write
NON_MST_MODE
Non-MST mode
0
MST_MODE
MST mode
1
RESERVED1
reserved1
6
32
read-only
START_STOP_EN
none
5
6
read-write
DISABLE_START_STOP
Disable start stop
0
ENABLE_START_STOP
Enable start stop
1
SYNC_MODE
none
0
1
read-write
NON_SYNC_MODE
Non-Sync mode
0
SYNC_MODE
Sync mode
1
SRR
Software Reset Register
0x88
32
write-only
n
0x0
RESERVED1
reserved1
3
32
write-only
RFR
RCVR FIFO Reset
1
2
write-only
UR
UART Reset
0
1
write-only
XFR
XMIT FIFO Reset
2
3
write-only
SRT
Shadow RCVR Trigger
0x9C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
SRT
Shadow RCVR Trigger
0
2
read-write
SRTS
Shadow Request to Send
0x8C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SRTS
Shadow Request to Send.
0
1
read-write
STET
Shadow TX Empty Trigger
0xA0
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
STET
Shadow TX Empty Trigger
0
2
read-write
TAR
Transmit Address Register.
0xC8
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
TAT
TurnAround Timing Register
0xBC
32
read-write
n
0x0
DE_RE
Driver Enable to Receiver Enable TurnAround time.
0
16
read-write
RE_DE
Receiver Enable to Driver Enable TurnAround time.
16
32
read-write
TCR
Transceiver Control Register.
0xAC
32
read-write
n
0x0
DE_POL
Driver Enable Polarity.
2
3
read-write
RESERVED1
reserved1
5
32
read-only
RE_POL
Receiver Enable Polarity.
1
2
read-write
RS485_EN
RS485 Transfer Enable.
0
1
read-write
XFER_MODE
Transfer Mode.
3
5
read-write
TFL
Transmit FIFO Level
0x80
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
TFR
none
0x74
32
read-only
n
0x0
RESERVED1
reserved1
8
32
read-only
TX_FIFO_RD
Transmit FIFO Read
0
8
read-only
THR
Transmit Holding Register
DLL
0x0
32
write-only
n
0x0
0x0
RESERVED1
reserved1
8
32
write-only
THR
Data to be transmitted on serial output port
0
8
write-only
UCV
UART Component Version
0xF8
32
read-only
n
0x0
UART_COMP_VER
ASCII value for each number in the version, followed by *
0
32
read-only
USR
UART Status Register
0x7C
32
read-only
n
0x0
BUSY
Indicates that a serial transfer is in progress
0
1
read-only
Disabled
UART is idle or inactive
0
Enabled
UART is busy (actively transferring data)
1
RESERVED1
reserved1
5
32
read-only
RFE
To Indicate that the receive FIFO is completely full
4
5
read-only
Disabled
Receive FIFO not full
0
Enabled
Receive FIFO Full
1
RFNE
To Indicate that the receive FIFO contains one or more entries
3
4
read-only
Disabled
Receive FIFO is empty
0
Enabled
Receive FIFO is not empty
1
TFE
To Indicate that the transmit FIFO is completely empty
2
3
read-only
Disabled
Transmit FIFO is not empty
0
Enabled
Transmit FIFO is empty
1
TFNF
To Indicate that the transmit FIFO is not full
1
2
read-only
Disabled
Transmit FIFO is full
0
Enabled
Transmit FIFO is not full
1
UDMA0
DMA Performs data transfers along with Addresses and control information
UDMA
0x0
0x0
0x830
registers
n
UDMA0
33
ALT_CTRL_BASE_PTR
Channel Alternate Control Data Base Pointer
0xC
32
read-only
n
0x0
ALT_CTRL_BASE_PTR
Base address of the alternative data structure
0
32
read-only
CHANNEL_STATUS_REG
Channel status Register
0x804
32
read-only
n
0x0
0x0
BUSY_OR_IDEAL_STATUS_CHANNEL_0
Reading 1 indicates that the channel 0 is busy
0
1
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_1
Reading 1 indicates that the channel 1 is busy
1
2
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_10
Reading 1 indicates that the channel 10 is busy
10
11
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_11
Reading 1 indicates that the channel 11 is busy
11
12
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_12
Reading 1 indicates that the channel 12 is busy
12
13
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_13
Reading 1 indicates that the channel 13 is busy
13
14
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_14
Reading 1 indicates that the channel 14 is busy
14
15
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_15
Reading 1 indicates that the channel 15 is busy
15
16
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_16
Reading 1 indicates that the channel 16 is busy
16
17
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_17
Reading 1 indicates that the channel 17 is busy
17
18
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_18
Reading 1 indicates that the channel 18 is busy
18
19
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_19
Reading 1 indicates that the channel 19 is busy
19
20
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_2
Reading 1 indicates that the channel 2 is busy
2
3
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_20
Reading 1 indicates that the channel 20 is busy
20
21
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_21
Reading 1 indicates that the channel 21 is busy
21
22
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_22
Reading 1 indicates that the channel 22 is busy
22
23
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_23
Reading 1 indicates that the channel 23 is busy
23
24
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_24
Reading 1 indicates that the channel 24 is busy
24
25
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_25
Reading 1 indicates that the channel 25 is busy
25
26
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_26
Reading 1 indicates that the channel 26 is busy
26
27
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_27
Reading 1 indicates that the channel 27 is busy
27
28
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_28
Reading 1 indicates that the channel 28 is busy
28
29
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_29
Reading 1 indicates that the channel 29 is busy
29
30
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_3
Reading 1 indicates that the channel 3 is busy
3
4
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_30
Reading 1 indicates that the channel 30 is busy
30
31
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_31
Reading 1 indicates that the channel 31 is busy
31
32
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_4
Reading 1 indicates that the channel 4 is busy
4
5
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_5
Reading 1 indicates that the channel 5 is busy
5
6
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_6
Reading 1 indicates that the channel 6 is busy
6
7
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_7
Reading 1 indicates that the channel 7 is busy
7
8
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_8
Reading 1 indicates that the channel 8 is busy
8
9
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_9
Reading 1 indicates that the channel 9 is busy
9
10
read-only
CHNL_ENABLE_CLR
UDMA Channel enable clear register
0x2C
32
write-only
n
CHNL_ENABLE_CLR
Set the appropriate bit to disable the corresponding DMA channel
0
32
write-only
CHNL_ENABLE_SET
UDMA Channel enable register
0x28
32
read-write
n
0x0
0x0
CHNL_ENABLE_SET
This Bits are Used to Load the 16bits of Source address
0
32
read-write
CHNL_PRIORITY_CLR
UDMA Channel Priority Clear
0x3C
32
write-only
n
CHNL_PRIORITY_CLR
Set the appropriate bit to select the default priority level for the specified DMA channel
0
32
write-only
CHNL_PRIORITY_SET
UDMA Channel Priority Set
0x38
32
read-write
n
0x0
0x0
CHNL_PRIORITY_SET
Set the appropriate bit to select the primary data structure for the corresponding DMA channel
0
32
read-write
CHNL_PRI_ALT_CLR
UDMA Channel primary alternate clear
0x34
32
write-only
n
CHNL_PRI_ALT_CLR
Set the appropriate bit to select the primary data structure for the corresponding DMA channel
0
32
write-only
CHNL_PRI_ALT_SET
UDMA Channel primary or alternate set
0x30
32
read-write
n
0x0
0x0
CHNL_PRI_ALT_SET
Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel
0
32
read-write
CHNL_REQ_MASK_CLR
UDMA Channel request mask clear
0x24
32
write-only
n
CHNL_REQ_MASK_CLR
Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[]
0
32
write-only
CHNL_REQ_MASK_SET
UDMA Channel request mask set Register
0x20
32
read-write
n
0x0
0x0
CHNL_REQ_MASK_SET
Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests
0
32
read-write
CHNL_SW_REQUEST
Channel Software Request
0x14
32
write-only
n
CHNL_SW_REQUEST
Set the appropriate bit to generate a software DMA request on the corresponding DMA channel
0
32
write-only
CHNL_USEBURST_CLR
UDMA Channel use burst clear
0x1C
32
write-only
n
CHNL_USEBURST_CLR
Set the appropriate bit to enable dma_sreq[] to generate requests
0
32
write-only
CHNL_USEBURST_SET
UDMA Channel use burst set
0x18
32
read-write
n
0x0
0x0
CHNL_USEBURST_SET
The use burst status, or disables dma_sreq[C] from generating DMA requests.
0
32
read-write
CTRL_BASE_PTR
Channel Control Data Base Pointer
0x8
32
read-write
n
0x0
0x0
CTRL_BASE_PTR
Pointer to the base address of the primary data structure
10
32
read-write
RESERVED1
Reserved1
0
10
write-only
DMA_CFG
DMA Configuration
0x4
32
write-only
n
CHNL_PROT_CTRL
Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls HPROT[2] to indicate if cacheable access is occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring
5
8
write-only
MASTER_ENABLE
Enable for the controller
0
1
write-only
Disable
controller is disable
0
Enable
controller is enable
1
RESERVED1
Reserved1
1
5
write-only
RESERVED2
Reserved2
8
32
write-only
DMA_STATUS
UDMA Status Register
0x0
32
read-only
n
0x0
CHNLS_MINUS1
Number of available DMA channels minus one
16
21
read-only
MASTER_ENABLE
Enable status of controller
0
1
read-only
Disable
controller is disable
0
Enable
controller is enable
1
RESERVED1
Reserved1
1
4
read-only
RESERVED2
Reserved2
8
16
read-only
RESERVED3
Reserved3
21
28
read-only
STATE
Current state of the control state machine
4
8
read-only
TEST_STATUS
To reduce the gate count you can configure the controller
28
32
read-only
0x0
Controller does not includes integration test logic
0
0x1
Controller does not includes integration test logic
1
DMA_WAITONREQUEST_STATUS
Channel Wait on request status register
0x10
32
read-only
n
0x0
DMA_WAITONREQ_STATUS
Per Channel wait on request status
0
32
read-only
ERR_CLR
UDMA Bus Error Clear Register
0x4C
32
read-write
n
0x0
0x0
ERR_CLR
Returns the status of dma_err
0
1
read-write
disabled
Read as:0 = dma_err is LOW Write as:0 = No effect, status of dma_err is unchanged
0
enabled
Read as:1 = dma_err is HIGH Write as:1 = Sets dma_err LOW
1
RESERVED1
Reserved1
1
32
read-write
UDMA_CONFIG_CTRL_REG
DMA Controller Transfer Length Register
0x828
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use.
1
32
read-write
SINGLE_REQUEST_ENABLE
Enabled signal for single request
0
1
read-write
disabled
Single request will be disabled
0
enabled
Single request will be enabled
1
UDMA_DONE_STATUS_REG
UDMA Done status Register
0x800
32
read-write
n
0x0
0x0
DONE_STATUS_CHANNEL_0
UDMA done Status of the channel 0
0
1
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 0th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_1
UDMA done Status of the channel 1
1
2
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 1st Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_10
UDMA done Status of the channel 10
10
11
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 10th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_11
UDMA done Status of the channel 3
11
12
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 11th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_12
UDMA done Status of the channel 12
12
13
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 12th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_13
UDMA done Status of the channel 13
13
14
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 13th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_14
UDMA done Status of the channel 14
14
15
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 14th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_15
UDMA done Status of the channel 15
15
16
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 15th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_16
UDMA done Status of the channel 16
16
17
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 16th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_17
UDMA done Status of the channel 17
17
18
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 17th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_18
UDMA done Status of the channel 18
18
19
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 18th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_19
UDMA done Status of the channel 19
19
20
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 19th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_2
UDMA done Status of the channel 2
2
3
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 2nd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_20
UDMA done Status of the channel 3
20
21
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 20th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_21
UDMA done Status of the channel 21
21
22
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 21th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_22
UDMA done Status of the channel 22
22
23
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 22th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_23
UDMA done Status of the channel 23
23
24
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 23rd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_24
UDMA done Status of the channel 24
24
25
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 24th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_25
UDMA done Status of the channel 25
25
26
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 25th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_26
UDMA done Status of the channel 26
26
27
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 26th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_27
UDMA done Status of the channel 27
27
28
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 27th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_28
UDMA done Status of the channel 28
28
29
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 28th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_29
UDMA done Status of the channel 29
29
30
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 29th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_3
UDMA done Status of the channel 3
3
4
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 3rd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_30
UDMA done Status of the channel 30
30
31
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 30th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_31
UDMA done Status of the channel 31
31
32
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 31st Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_4
UDMA done Status of the channel 4
4
5
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 4th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_5
UDMA done Status of the channel 5
5
6
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 5th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_6
UDMA done Status of the channel 6
6
7
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 6th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_7
UDMA done Status of the channel 7
7
8
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 7th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_8
UDMA done Status of the channel 8
8
9
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 8th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_9
UDMA done Status of the channel 9
9
10
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 9th Write as:1 will clear the bit
1
UDMA_INTR_MASK_REG
Mask the uDMA interrupt register
0x82C
32
read-write
n
RESERVED1
RESERVED1
12
32
read-only
UDMA_INTR_MASK
Mask the uDMA interrupt register
0
12
read-write
UDMA_SKIP_DESC_FETCH_REG
UDMA skip descriptor fetch Register
0x50
32
read-write
n
0x0
0x0
SKIP_DESC_FETCH
improving the performance of transfer and saves bus cycles. This features has to be enabled always.
0
32
read-write
UDMA1
DMA Performs data transfers along with Addresses and control information
UDMA
0x0
0x0
0x830
registers
n
UDMA1
10
ALT_CTRL_BASE_PTR
Channel Alternate Control Data Base Pointer
0xC
32
read-only
n
0x0
ALT_CTRL_BASE_PTR
Base address of the alternative data structure
0
32
read-only
CHANNEL_STATUS_REG
Channel status Register
0x804
32
read-only
n
0x0
0x0
BUSY_OR_IDEAL_STATUS_CHANNEL_0
Reading 1 indicates that the channel 0 is busy
0
1
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_1
Reading 1 indicates that the channel 1 is busy
1
2
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_10
Reading 1 indicates that the channel 10 is busy
10
11
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_11
Reading 1 indicates that the channel 11 is busy
11
12
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_12
Reading 1 indicates that the channel 12 is busy
12
13
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_13
Reading 1 indicates that the channel 13 is busy
13
14
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_14
Reading 1 indicates that the channel 14 is busy
14
15
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_15
Reading 1 indicates that the channel 15 is busy
15
16
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_16
Reading 1 indicates that the channel 16 is busy
16
17
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_17
Reading 1 indicates that the channel 17 is busy
17
18
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_18
Reading 1 indicates that the channel 18 is busy
18
19
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_19
Reading 1 indicates that the channel 19 is busy
19
20
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_2
Reading 1 indicates that the channel 2 is busy
2
3
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_20
Reading 1 indicates that the channel 20 is busy
20
21
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_21
Reading 1 indicates that the channel 21 is busy
21
22
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_22
Reading 1 indicates that the channel 22 is busy
22
23
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_23
Reading 1 indicates that the channel 23 is busy
23
24
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_24
Reading 1 indicates that the channel 24 is busy
24
25
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_25
Reading 1 indicates that the channel 25 is busy
25
26
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_26
Reading 1 indicates that the channel 26 is busy
26
27
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_27
Reading 1 indicates that the channel 27 is busy
27
28
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_28
Reading 1 indicates that the channel 28 is busy
28
29
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_29
Reading 1 indicates that the channel 29 is busy
29
30
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_3
Reading 1 indicates that the channel 3 is busy
3
4
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_30
Reading 1 indicates that the channel 30 is busy
30
31
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_31
Reading 1 indicates that the channel 31 is busy
31
32
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_4
Reading 1 indicates that the channel 4 is busy
4
5
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_5
Reading 1 indicates that the channel 5 is busy
5
6
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_6
Reading 1 indicates that the channel 6 is busy
6
7
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_7
Reading 1 indicates that the channel 7 is busy
7
8
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_8
Reading 1 indicates that the channel 8 is busy
8
9
read-only
BUSY_OR_IDEAL_STATUS_CHANNEL_9
Reading 1 indicates that the channel 9 is busy
9
10
read-only
CHNL_ENABLE_CLR
UDMA Channel enable clear register
0x2C
32
write-only
n
CHNL_ENABLE_CLR
Set the appropriate bit to disable the corresponding DMA channel
0
32
write-only
CHNL_ENABLE_SET
UDMA Channel enable register
0x28
32
read-write
n
0x0
0x0
CHNL_ENABLE_SET
This Bits are Used to Load the 16bits of Source address
0
32
read-write
CHNL_PRIORITY_CLR
UDMA Channel Priority Clear
0x3C
32
write-only
n
CHNL_PRIORITY_CLR
Set the appropriate bit to select the default priority level for the specified DMA channel
0
32
write-only
CHNL_PRIORITY_SET
UDMA Channel Priority Set
0x38
32
read-write
n
0x0
0x0
CHNL_PRIORITY_SET
Set the appropriate bit to select the primary data structure for the corresponding DMA channel
0
32
read-write
CHNL_PRI_ALT_CLR
UDMA Channel primary alternate clear
0x34
32
write-only
n
CHNL_PRI_ALT_CLR
Set the appropriate bit to select the primary data structure for the corresponding DMA channel
0
32
write-only
CHNL_PRI_ALT_SET
UDMA Channel primary or alternate set
0x30
32
read-write
n
0x0
0x0
CHNL_PRI_ALT_SET
Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel
0
32
read-write
CHNL_REQ_MASK_CLR
UDMA Channel request mask clear
0x24
32
write-only
n
CHNL_REQ_MASK_CLR
Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[]
0
32
write-only
CHNL_REQ_MASK_SET
UDMA Channel request mask set Register
0x20
32
read-write
n
0x0
0x0
CHNL_REQ_MASK_SET
Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests
0
32
read-write
CHNL_SW_REQUEST
Channel Software Request
0x14
32
write-only
n
CHNL_SW_REQUEST
Set the appropriate bit to generate a software DMA request on the corresponding DMA channel
0
32
write-only
CHNL_USEBURST_CLR
UDMA Channel use burst clear
0x1C
32
write-only
n
CHNL_USEBURST_CLR
Set the appropriate bit to enable dma_sreq[] to generate requests
0
32
write-only
CHNL_USEBURST_SET
UDMA Channel use burst set
0x18
32
read-write
n
0x0
0x0
CHNL_USEBURST_SET
The use burst status, or disables dma_sreq[C] from generating DMA requests.
0
32
read-write
CTRL_BASE_PTR
Channel Control Data Base Pointer
0x8
32
read-write
n
0x0
0x0
CTRL_BASE_PTR
Pointer to the base address of the primary data structure
10
32
read-write
RESERVED1
Reserved1
0
10
write-only
DMA_CFG
DMA Configuration
0x4
32
write-only
n
CHNL_PROT_CTRL
Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls HPROT[2] to indicate if cacheable access is occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring
5
8
write-only
MASTER_ENABLE
Enable for the controller
0
1
write-only
Disable
controller is disable
0
Enable
controller is enable
1
RESERVED1
Reserved1
1
5
write-only
RESERVED2
Reserved2
8
32
write-only
DMA_STATUS
UDMA Status Register
0x0
32
read-only
n
0x0
CHNLS_MINUS1
Number of available DMA channels minus one
16
21
read-only
MASTER_ENABLE
Enable status of controller
0
1
read-only
Disable
controller is disable
0
Enable
controller is enable
1
RESERVED1
Reserved1
1
4
read-only
RESERVED2
Reserved2
8
16
read-only
RESERVED3
Reserved3
21
28
read-only
STATE
Current state of the control state machine
4
8
read-only
TEST_STATUS
To reduce the gate count you can configure the controller
28
32
read-only
0x0
Controller does not includes integration test logic
0
0x1
Controller does not includes integration test logic
1
DMA_WAITONREQUEST_STATUS
Channel Wait on request status register
0x10
32
read-only
n
0x0
DMA_WAITONREQ_STATUS
Per Channel wait on request status
0
32
read-only
ERR_CLR
UDMA Bus Error Clear Register
0x4C
32
read-write
n
0x0
0x0
ERR_CLR
Returns the status of dma_err
0
1
read-write
disabled
Read as:0 = dma_err is LOW Write as:0 = No effect, status of dma_err is unchanged
0
enabled
Read as:1 = dma_err is HIGH Write as:1 = Sets dma_err LOW
1
RESERVED1
Reserved1
1
32
read-write
UDMA_CONFIG_CTRL_REG
DMA Controller Transfer Length Register
0x828
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use.
1
32
read-write
SINGLE_REQUEST_ENABLE
Enabled signal for single request
0
1
read-write
disabled
Single request will be disabled
0
enabled
Single request will be enabled
1
UDMA_DONE_STATUS_REG
UDMA Done status Register
0x800
32
read-write
n
0x0
0x0
DONE_STATUS_CHANNEL_0
UDMA done Status of the channel 0
0
1
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 0th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_1
UDMA done Status of the channel 1
1
2
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 1st Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_10
UDMA done Status of the channel 10
10
11
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 10th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_11
UDMA done Status of the channel 3
11
12
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 11th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_12
UDMA done Status of the channel 12
12
13
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 12th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_13
UDMA done Status of the channel 13
13
14
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 13th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_14
UDMA done Status of the channel 14
14
15
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 14th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_15
UDMA done Status of the channel 15
15
16
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 15th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_16
UDMA done Status of the channel 16
16
17
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 16th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_17
UDMA done Status of the channel 17
17
18
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 17th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_18
UDMA done Status of the channel 18
18
19
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 18th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_19
UDMA done Status of the channel 19
19
20
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 19th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_2
UDMA done Status of the channel 2
2
3
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 2nd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_20
UDMA done Status of the channel 3
20
21
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 20th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_21
UDMA done Status of the channel 21
21
22
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 21th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_22
UDMA done Status of the channel 22
22
23
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 22th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_23
UDMA done Status of the channel 23
23
24
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 23rd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_24
UDMA done Status of the channel 24
24
25
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 24th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_25
UDMA done Status of the channel 25
25
26
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 25th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_26
UDMA done Status of the channel 26
26
27
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 26th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_27
UDMA done Status of the channel 27
27
28
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 27th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_28
UDMA done Status of the channel 28
28
29
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 28th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_29
UDMA done Status of the channel 29
29
30
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 29th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_3
UDMA done Status of the channel 3
3
4
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 3rd Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_30
UDMA done Status of the channel 30
30
31
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 30th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_31
UDMA done Status of the channel 31
31
32
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 31st Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_4
UDMA done Status of the channel 4
4
5
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 4th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_5
UDMA done Status of the channel 5
5
6
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 5th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_6
UDMA done Status of the channel 6
6
7
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 6th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_7
UDMA done Status of the channel 7
7
8
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 7th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_8
UDMA done Status of the channel 8
8
9
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 8th Write as:1 will clear the bit
1
DONE_STATUS_CHANNEL_9
UDMA done Status of the channel 9
9
10
read-write
disabled
Write as:0 will have no effect
0
enabled
Read as:1 indicates the transfer is completed for channel 9th Write as:1 will clear the bit
1
UDMA_INTR_MASK_REG
Mask the uDMA interrupt register
0x82C
32
read-write
n
RESERVED1
RESERVED1
12
32
read-only
UDMA_INTR_MASK
Mask the uDMA interrupt register
0
12
read-write
UDMA_SKIP_DESC_FETCH_REG
UDMA skip descriptor fetch Register
0x50
32
read-write
n
0x0
0x0
SKIP_DESC_FETCH
improving the performance of transfer and saves bus cycles. This features has to be enabled always.
0
32
read-write
ULP_I2C
Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system
I2C
0x0
0x0
0x100
registers
n
I2C2
13
IC_ACK_GENERAL_CALL
I2C ACK General Call Register
0x98
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
1
32
read-only
IC_CLR_ACTIVITY
Clear ACTIVITY Interrupt Register
0x5C
32
read-only
n
0x0
0x0
CLR_ACTIVITY
Reading this register clears the ACTIVITY interrupt if the I2C is not active any more
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_GEN_CALL
Clear GEN_CALL Interrupt Register
0x68
32
read-only
n
0x0
0x0
CLR_GEN_CALL
Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_INTR
Clear Combined and Individual Interrupt Register
0x40
32
read-only
n
0x0
0x0
CLR_INTR
Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RD_REQ
Clear RD_REQ Interrupt Register
0x50
32
read-only
n
0x0
0x0
CLR_RD_REQ
Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RESTART_DET
Clear RESTART_DET Interrupt Register
0xA8
32
read-only
n
0x0
0x0
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_DONE
Clear RX_DONE Interrupt Register
0x58
32
read-only
n
0x0
0x0
CLR_RX_DONE
Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_OVER
Clear RX_OVER Interrupt Register
0x48
32
read-only
n
0x0
0x0
CLR_RX_OVER
Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_RX_UNDER
Clear RX_UNDER Interrupt Register
0x44
32
read-only
n
0x0
0x0
CLR_RX_UNDER
Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SCL_STUCK_DET
Clear SCL Stuck at Low Detect Interrupt Register
0xB4
32
read-only
n
0x0
CLR_SCL_STUCK
Read this register to clear the SCL_STUCK_DET interrupt
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_SMBUS_INTR
Clear SMBUS Interrupt Register
0xD4
32
read-write
n
0x0
0x0
RESERVED1
RESERVED1
0
32
read-write
IC_CLR_START_DET
Clear START_DET Interrupt Register
0x64
32
read-only
n
0x0
0x0
CLR_START_DET
Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_STOP_DET
Clear STOP_DET Interrupt Register
0x60
32
read-only
n
0x0
0x0
CLR_STOP_DET
Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_ABRT
Clear TX_ABRT Interrupt Register
0x54
32
read-only
n
0x0
0x0
CLR_TX_ABRT
Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_CLR_TX_OVER
Clear TX_OVER Interrupt Register
0x4C
32
read-only
n
0x0
0x0
CLR_TX_OVER
Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
0
1
read-only
RESERVED1
reserved1
1
32
read-only
IC_COMP_PARAM_1
I2C HS Spike Suppression Limit Register
0xF4
32
read-only
n
0x0
0x0
ADD_ENCODED_PARAMS
Add Encoded Parameters
7
8
read-only
False
False
0x0
True
True
0x1
CLR_RESTART_DET
Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe
0
1
read-only
HAS_DMA
DMA Handshake Interface signal
6
7
read-only
False
False
0x0
True
True
0x1
HC_COUNT_VALUES
Hard Code the count values
4
5
read-only
False
False
0x0
True
True
0x1
INTR_IO
Single Interrupt Output port
5
6
read-only
Individual
Individual
0x0
Combined
Combined
0x1
MAX_SPEED_MODE
Maximum Speed Mode
2
4
read-only
NONE
none
0x0
Standard
Standard
0x1
Fast
Fast
0x2
High
High
0x3
RESERVED1
reserved1
24
32
read-only
RX_BUFFER_DEPTH
Depth of receive buffer the buffer is 8 bits wide 2 to 256
8
16
read-only
TX_BUFFER_DEPTH
Depth of Transmit buffer the buffer is 8 bits wide 2 to 256
16
24
read-only
IC_COMP_TYPE
I2C Component Type Register
0xFC
32
read-only
n
0x0
IC_COMP_TYPE
Design ware Component Type number = 0x44_57_01_40
0
32
read-only
IC_COMP_VERSION
I2C Component Version Register
0xF8
32
read-only
n
0x0
IC_COMP_VERSION
Signifies the component version
0
32
read-only
IC_CON
This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect.
0x0
32
read-write
n
0x0
0x0
BUS_CLEAR_FEATURE_CTRL
In Master mode.
11
12
read-write
Disable
Bus Clear Feature is disabled
0
Enable
Bus Clear Feature is enabled
1
IC_10BITADDR_MASTER_RD_ONLY
the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only
4
5
read-only
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_10BITADDR_SLAVE
When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.
3
4
read-write
Disable
7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared
0
Enable
10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
1
IC_RESTART_EN
Determines whether RESTART conditions may be sent when acting as a master
5
6
read-write
Disable
Disabled
0
Enable
Enabled
1
IC_SLAVE_DISABLE
This bit controls whether I2C has its slave disabled
6
7
read-write
Disable
slave is enabled
0
Enable
slave is disabled
1
MASTER_MODE
This bit controls whether the I2C master is enabled.
0
1
read-write
Disable
master disabled
0
Enable
master enabled
1
RESERVED1
reserved1
9
10
read-only
RESERVED2
reserved2
12
32
read-write
SPEED
These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software.
1
3
read-write
Standard Mode
standard mode (0 to 100 kbit/s)
1
Fast Mode
fast mode (less than or equal 400 kbit/s)
2
High Speed Mode
high speed mode (less than or equal 3.4 Mbit/s)
3
STOP_DET_IFADDRESSED
The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR
7
8
read-write
Disable
Issues the STOP DETECTION irrespective of whether it is addressed or not.
0
Enable
issues the STOP DETECTION interrupt only when it is addressed.
1
STOP_DET_IF_MASTER_ACTIVE
In Master mode.
10
11
read-write
Disable
Issues the STOP_DET irrespective of whether the master is active.
0
Enable
Issues the STOP_DET interrupt only when the master is active
1
TX_EMPTY_CTRL
This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register.
8
9
read-write
IC_DATA_CMD
I2C Rx/Tx Data Buffer and Command Register
0x10
32
read-write
n
0x0
0x0
CMD
This bit controls whether a read or a write is performed
8
9
write-only
Disable
write
0
Enable
Read
1
DAT
This register contains the data to be transmitted or received on the I2C bus
0
8
read-write
FIRST_DATA_BYTE
Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode
11
12
read-only
RESERVED1
reserved1
12
32
read-only
RESTART
This bit controls whether a RESTART is issued before the byte is sent or received
10
11
write-only
Disable
If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command
0
Enable
If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
1
STOP
This bit controls whether a STOP is issued after the byte is sent or received
9
10
write-only
Disable
STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty
0
Enable
STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty
1
IC_DEVICE_ID
I2C Device ID
0xB8
32
read-only
n
0x0
DEVICE_ID
Contains the Device-ID of the component assigned through the configuration parameter
0
24
read-only
RESERVED1
reserved1
24
32
read-only
IC_DMA_CR
DMA Control Register
0x88
32
read-write
n
0x0
0x0
RDMAE
Receive DMA Enable
0
1
read-write
Disable
Receive DMA disabled
0
Enable
Receive DMA enabled
1
RESERVED1
reserved1
2
32
read-only
TDMAE
Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
Disable
Transmit DMA disabled
0
Enable
Transmit DMA enabled
1
IC_DMA_RDLR
I2C Receive Data Level Register
0x90
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_DMA_TDLR
DMA Transmit Data Level Register
0x8C
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
reserved1
4
32
read-only
IC_ENABLE
Clear GEN_CALL Interrupt Register
0x6C
32
read-write
n
0x0
0x0
ABORT
When set, the controller initiates the transfer abort
1
2
read-write
Disable
ABORT not initiated or ABORT done
0
Enable
ABORT operation in progress
1
EN
Controls whether the DW_apb_i2c is enabled
0
1
read-write
Disable
Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)
0
Enable
Enables DW_apb_i2c
1
RESERVED1
reserved1
4
16
read-only
RESERVED2
reserved2
16
32
read-only
SDA_STUCK_RECOVERY_ENABLE
If SDA is stuck at low indicated through the TX_ABORT interrupt IC_TX_ABRT_SOURCE17, then this bit is used as a control knob to initiate the SDA Recovery Mechanism
3
4
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
TX_CMD_BLOCK
none
2
3
read-write
Disable
The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO
0
Enable
Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit
1
IC_ENABLE_STATUS
I2C Enable Status Register
0x9C
32
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call
0
1
read-write
Disable
DW_apb_i2c does not generate General Call interrupts
0
Enable
DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call.
1
RESERVED1
reserved1
3
32
read-write
SLV_DISABLED_WHILE_BUSY
This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0
1
2
read-only
Disable
DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
0
Enable
DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer
1
SLV_RX_DATA_LOST
Slave Received Data Lost
2
3
read-only
Disable
DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK
0
Enable
DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer
1
IC_FS_SCL_HCNT
Fast Speed I2C Clock SCL High Count Register
0x1C
32
read-write
n
0x0
0x0
IC_FS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SCL_LCNT
Fast Speed I2C Clock SCL Low Count Register
0x20
32
read-write
n
0x0
0x0
IC_FS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_FS_SPKLEN
I2C SS and FS Spike Suppression Limit Register
IC_UFM_SPKLEN
0xA0
32
read-write
n
0x0
0x0
IC_FS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_HS_MADDR
I2C High Speed Master Mode Code Address Register
0xC
32
read-write
n
0x0
0x0
IC_HS_MAR
This bit field holds the value of the I2C HS mode master code
0
3
read-write
RESERVED1
reserved1
3
32
read-only
IC_HS_SCL_HCNT
High Speed I2C Clock SCL High Count Register
0x24
32
read-write
n
0x0
0x0
IC_HS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SCL_LCNT
High Speed I2C Clock SCL Low Count Register
0x28
32
read-write
n
0x0
0x0
IC_HS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_HS_SPKLEN
I2C HS Spike Suppression Limit Register
0xA4
32
read-write
n
0x0
0x0
IC_HS_SPKLEN
This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic
0
8
read-write
RESERVED1
reserved1
8
32
read-only
IC_INTR_MASK
I2C Interrupt Mask Register
0x30
32
read-write
n
0x0
0x0
M_ACTIVITY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
8
9
read-write
M_GEN_CALL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
11
12
read-write
M_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-write
M_RD_REQ
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
5
6
read-write
M_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-write
M_RX_DONE
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
7
8
read-write
M_RX_FULL
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
2
3
read-write
M_RX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
1
2
read-write
M_RX_UNDER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
0
1
read-write
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
M_START_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
10
11
read-write
M_STOP_DET
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
9
10
read-write
M_TX_ABRT
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
6
7
read-write
M_TX_EMPTY
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register.
4
5
read-write
M_TX_OVER
This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register
3
4
read-write
RESERVED1
reserved1
15
32
read-only
IC_INTR_STAT
I2C Interrupt Status Register
0x2C
32
read-only
n
0x0
0x0
M_SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
RESERVED1
reserved1
15
32
read-only
R_ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
R_GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
R_MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
R_RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
R_RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
R_RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
R_RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
R_RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
R_RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
R_START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
R_STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
R_TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
R_TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
R_TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_OPTIONAL_SAR
Optional Slave Address Register
0xD8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_RAW_INTR_STAT
I2C Raw Interrupt Status Register
0x34
32
read-only
n
0x0
0x0
ACTIVITY
This bit captures DW_apb_i2c activity and stays set until it is cleared
8
9
read-only
GEN_CALL
Set only when a General Call address is received and it is acknowledged
11
12
read-only
MST_ON_HOLD
Indicates whether a master is holding the bus and the Tx FIFO is empty.
13
14
read-only
RD_REQ
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c.
5
6
read-only
RESERVED1
reserved1
15
32
read-only
RESTART_DET
Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave
12
13
read-only
RX_DONE
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte
7
8
read-only
RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
2
3
read-only
RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device
1
2
read-only
RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register
0
1
read-only
SCL_STUCK_AT_LOW
Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods
14
15
read-only
START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
10
11
read-only
STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
9
10
read-only
TX_ABRT
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO
6
7
read-only
TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
4
5
read-only
TX_OVER
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
3
4
read-only
IC_RXFLR
I2C Receive FIFO Level Register
0x78
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
RXFLR
Receive FIFO Level. Contains the number of valid data entries in the receive FIFO
0
4
read-only
IC_RX_TL
I2C Receive FIFO Threshold Register
0x38
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
RX_TL
Receive FIFO Threshold Level
0
8
read-write
IC_SAR
I2C Slave Address Register
0x8
32
read-write
n
0x0
0x0
IC_SAR
The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
0
10
read-write
RESERVED1
reserved1
10
32
read-only
IC_SCL_STUCK_AT_LOW_TIMEOUT
I2C SCL Stuck at Low Timeout
0xAC
32
read-write
n
0x0
IC_SCL_STUCK_LOW_TIMEOUT
Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period
0
32
read-write
IC_SDA_HOLD
I2C SDA Hold Time Length Register
0x7C
32
read-write
n
0x0
0x0
IC_SDA_RX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver.
16
24
read-write
IC_SDA_TX_HOLD
Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter.
0
16
read-write
RESERVED1
reserved1
24
32
read-only
IC_SDA_SETUP
I2C SDA Setup Register
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SDA_SETUP
This register controls the amount of time delay (in terms of number of ic_clk clock periods)
0
8
read-write
IC_SDA_STUCK_AT_LOW_TIMEOUT
I2C SDA Stuck at Low Timeout
0xB0
32
read-write
n
0x0
IC_SDA_STUCK_LOW_TIMEOUT
Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period.
0
32
read-write
IC_SLV_DATA_NACK_ONLY
Generate Slave Data NACK Register
0x84
32
read-write
n
0x0
0x0
NACK
Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
IC_SMBUS_CLOCK_LOW_MEXT
SMBUS Master extend clock Timeout Register
0xC0
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_MEXT_TIMEOUT
The values in this register are in units of ic_clk period..
0
32
read-write
IC_SMBUS_CLOCK_LOW_SEXT
SMBUS Slave Clock Extend Timeout Register
0xBC
32
read-write
n
0x0
0x0
SMBUS_CLK_LOW_SEXT_TIMEOUT
The values in this register are in units of ic_clk period.
0
32
read-write
IC_SMBUS_INTR_MASK
Interrupt Mask Register
0xCC
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_INTR_RAW_STATUS
SMBUS Raw Interrupt Status Register
0xD0
32
read-write
n
0x0
0x0
RESERVED1
Reserved1.
0
32
read-write
IC_SMBUS_INTR_STAT
SMBUS Interrupt Status Register
0xC8
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
0
32
read-write
IC_SMBUS_THIGH_MAX_IDLE_COUNT
SMBus Thigh MAX Bus-Idle count Register
0xC4
32
read-write
n
0x0
0x0
RESERVED1
Reserved1
16
32
read-write
SMBUS_THIGH_MAX_BUS_IDLE_CNT
The values in this register are in units of ic_clk period.
0
16
read-write
IC_SMBUS_UDID_LSB
SMBUS ARP UDID LSB Register
0xDC
32
read-write
n
0x0
0x0
IC_SMBUS_ARP_UDID_LSB
This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol.
0
32
read-write
IC_SS_SCL_HCNT
Standard Speed I2C Clock SCL High Count Register
0x14
32
read-write
n
0x0
0x0
IC_SS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_SS_SCL_LCNT
Standard Speed I2C Clock SCL Low Count Register
0x18
32
read-write
n
0x0
0x0
IC_SS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing
0
16
read-write
RESERVED1
reserved1
16
32
read-only
IC_STATUS
I2C Status Register
0x70
32
read-only
n
0x0
0x0
ACTIVITY
I2C Activity Status
0
1
read-only
MST_ACTIVITY
Master FSM Activity Status
5
6
read-only
Disable
Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active
0
Enable
Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active
1
MST_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received.
8
9
read-only
MST_HOLD_TX_FIFO_EMPTY
The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set.
7
8
read-only
RESERVED1
reserved1
12
32
read-only
RFF
Receive FIFO Completely Full
4
5
read-only
Disable
Receive FIFO is not full
0
Enable
Receive FIFO is full
1
RFNE
Receive FIFO Not Empty
3
4
read-only
Disable
Receive FIFO is not empty
0
Enable
Receive FIFO is not empty
1
SDA_STUCK_NOT_RECOVERED
This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism.
11
12
read-only
SLV_ACTIVITY
Slave FSM Activity Status
6
7
read-only
Disable
Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active
0
Enable
Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
1
SLV_HOLD_RX_FIFO_FULL
This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received.
10
11
read-only
SLV_HOLD_TX_FIFO_EMPTY
This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty.
9
10
read-only
TFE
Transmit FIFO Completely Empty
2
3
read-only
Disable
Transmit FIFO is not empty
0
Enable
Transmit FIFO is empty
1
TFNF
Transmit FIFO Not Full
1
2
read-only
Disable
Transmit FIFO is full
0
Enable
Transmit FIFO is not full
1
IC_TAR
I2C Target Address Register
0x4
32
read-write
n
0x0
0x0
DEVICE_ID
If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master
13
14
read-write
Disable
Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command.
0
Enable
: Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO.
1
GC_OR_START
If bit 11 (SPECIAL) is set to 1 and bit 13 (Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the I2C
10
11
read-write
Disable
The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared
0
Enable
START BYTE
1
IC_10BITADDR_MASTER
This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master
12
13
read-write
Disable
7-bit addressing
0
Enable
10-bit addressing
1
IC_TAR
This is the target address for any master transaction
0
10
read-write
RESERVED1
reserved1
14
32
read-only
SPECIAL
This bit indicates whether software performs a General Call or START BYTE command
11
12
read-write
Disable
ignore bit 10 GC_OR_START and use IC_TAR normally
0
Enable
perform special I2C command as specified in GC_OR_START bit
1
IC_TXFLR
I2C Transmit FIFO Level Register
0x74
32
read-only
n
0x0
0x0
RESERVED1
reserved1
4
32
read-only
TXFLR
Contains the number of valid data entries in the transmit FIFO.
0
4
read-only
IC_TX_ABRT_SOURCE
I2C Transmit Abort Source Register
0x80
32
read-only
n
0x0
0x0
ABRT_10ADDR1_NOACK
1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave
1
2
read-only
ABRT_10ADDR2_NOACK
1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave
2
3
read-only
ABRT_10B_RD_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode
10
11
read-only
ABRT_7B_ADDR_NOACK
1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave
0
1
read-only
ABRT_DEVICE_NOACK
Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave
18
19
read-only
ABRT_DEVICE_SLVADDR_NOACK
Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave
19
20
read-only
ABRT_DEVICE_WRITE
Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands.
20
21
read-only
ABRT_GCALL_NOACK
1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call
4
5
read-only
ABRT_GCALL_READ
1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1)
5
6
read-only
ABRT_HS_ACKDET
1: Master is in High Speed mode and the High Speed Master code was acknowledged
6
7
read-only
ABRT_HS_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
8
9
read-only
ABRT_MASTER_DIS
1: User tries to initiate a Master operation with the Master mode disabled
11
12
read-only
ABRT_SBYTE_ACKDET
1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior)
7
8
read-only
ABRT_SBYTE_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte
9
10
read-only
ABRT_SDA_STUCK_AT_LOW
Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks
17
18
read-only
ABRT_SLVFLUSH_TXFIFO
1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO
13
14
read-only
ABRT_SLVRD_INTX
1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register
15
16
read-only
ABRT_SLV_ARBLOST
1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time
14
15
read-only
ABRT_TXDATA_NOACK
1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s)
3
4
read-only
ABRT_USER_ABRT
This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]).
16
17
read-only
ARB_LOST
1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration
12
13
read-only
RESERVED1
reserved1
21
23
read-only
TX_FLUSH_CNT
This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt
23
32
read-only
IC_TX_TL
I2C Transmit FIFO Threshold Register
0x3C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
TX_TL
Transmit FIFO Threshold Level
0
8
read-write
ULP_SSI
Synchronous Serial Interface(SSI)
SSI
0x0
0x0
0xF8
registers
n
ULP_SSI
16
BAUDR
Baud Rate Select Register
0x14
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
16
32
read-write
SCKDV
SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register
0
16
read-write
CTRLR0
Control Register 0
0x0
32
read-write
n
0x0
0x0
CFS
Control Frame Size Selects the length of the control word for the Micro wire frame format
12
16
read-write
None
Range -> 1 bit
0
none
Range -> 16 bit
15
DFS
Select the data frame length (4-bit to 16-bit serial data transfers)
0
4
read-write
DFS_32
Selects the data frame length
16
21
read-write
none
Range -> 16 bit
15
None
Range -> 3 bit
3
FRF
Frame Format, Selects which serial protocol transfers the data
4
6
read-write
00
Motorola SPI
0
01
Texas Instruments SSP
1
10
National Semiconductors Micro wire
2
11
none
3
RESERVED1
Reserved for future use
23
32
read-write
SCPH
Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI
6
7
read-write
disable
Serial clock toggles in middle of first data bit
0
enable
Serial clock toggles at start of first data bit
1
SCPOL
Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI
7
8
read-write
disable
Inactive state of serial clock is low
0
enable
Inactive state of serial clock is high
1
SLV_OE
DW_apb_ssi is configured as a serial-slave device
10
11
read-write
None
Slave txd is enabled
0
none
Slave txd is disabled
1
SPI_FRF
Selects data frame format for transmitting or receiving data
21
23
read-write
00
Standard SPI Format
0
01
Dual SPI Format
1
10
Quad SPI Format
2
11
Reser
3
SRL
Shift Register Loop Used for testing purposes only
11
12
read-write
None
Normal Mode Operation
0
none
Test Mode Operation
1
TMOD
Selects the mode of transfer for serial communication
8
10
read-write
00
Transmit and Receive
0
01
Transmit Only
1
10
Receive Only
2
CTRLR1
Control Register 1
0x4
32
read-write
n
0x0
0x0
NDF
Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master
0
16
read-write
RESERVED1
Reserved for future use.
16
32
read-write
DMACR
DMA Control Register
0x4C
32
read-write
n
0x0
0x0
RDMAE
This bit enables/disables the receive FIFO DMA channel
0
1
read-write
disabled
Receive DMA disabled
0
enabled
Receive DMA enabled
1
RESERVED1
Reserved for future use
2
32
read-only
TDMAE
This bit enables/disables the transmit FIFO DMA channel
1
2
read-write
disabled
Transmit DMA disabled
0
enabled
Transmit DMA enabled
1
DMARDLR
DMA Receive Data Level Register
0x54
32
read-write
n
0x0
0x0
DMARDL
This bit field controls the level at which a DMA request is made by the receive logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-write
DMATDLR
DMA Transmit Data Level
0x50
32
read-write
n
0x0
0x0
DMATDL
This bit field controls the level at which a DMA request is made by the transmit logic
0
4
read-write
RESERVED1
Reserved for future use
4
32
read-only
DR
Data Register
0x60
32
read-write
n
0x0
0x0
DR
When writing to this register must right-justify the data
0
32
read-write
ICR
Interrupt Clear Register
0x48
32
read-only
n
0x0
ICR
This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
IDR
Identification Register
0x58
32
read-only
n
0x0
0x0
IDCODE
This register contains the peripherals identification code
0
32
read-only
IMR
Interrupt Mask Register
0x2C
32
read-write
n
0x0
0x0
MSTIM
Multi-Master Contention Interrupt Mask
5
6
read-write
disable
ssi_mst_intr interrupt is masked
0
enable
ssi_mst_intr interrupt is not masked
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIM
Receive FIFO Full Interrupt Mask
4
5
read-write
disable
ssi_rxf_intr interrupt is masked
0
enable
ssi_rxf_intr interrupt is not masked
1
RXOIM
Receive FIFO Overflow Interrupt Mask
3
4
read-write
disable
ssi_rxo_intr interrupt is masked
0
enable
ssi_rxo_intr interrupt is not masked
1
RXUIM
Receive FIFO Underflow Interrupt Mask
2
3
read-write
disable
ssi_rxu_intr interrupt is masked
0
enable
ssi_rxu_intr interrupt is not masked
1
TXEIM
Transmit FIFO Empty Interrupt Mask
0
1
read-write
disable
ssi_txe_intr interrupt is masked
0
enable
ssi_txe_intr interrupt is not masked
1
TXOIM
Transmit FIFO Overflow Interrupt Mask
1
2
read-write
disable
ssi_txo_intr interrupt is masked
0
enable
ssi_txo_intr interrupt is not masked
1
ISR
Interrupt Status Register
0x30
32
read-only
n
0x0
MSTIS
Multi-Master Contention Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt not active after masking
0
enable
ssi_mst_intr interrupt is active after masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIS
Receive FIFO Full Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active after masking
0
enable
ssi_rxf_intr interrupt is full after masking
1
RXOIS
Receive FIFO Overflow Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active after masking
0
enable
ssi_rxo_intr interrupt is active after masking
1
RXUIS
Receive FIFO Underflow Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active after masking
0
enable
ssi_rxu_intr interrupt is active after masking
1
TXEIS
Transmit FIFO Empty Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active after masking
0
enable
ssi_txe_intr interrupt is active after masking
1
TXOIS
Transmit FIFO Overflow Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active after masking
0
enable
ssi_txo_intr interrupt is active after masking
1
MSTICR
Multi-Master Interrupt Clear Register
0x44
32
read-only
n
0x0
MSTICR
This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt
0
1
read-only
RESERVED1
Reserved for future use
1
32
read-only
MWCR
Micro wire Control Register
0xC
32
read-write
n
0x0
0x0
MDD
The direction of the data word when the Micro wire serial protocol is used
1
2
read-write
disable
the data word is received by the SSI MacroCell from the external serial device
0
enable
the data word is transmitted from the SSI MacroCell to the external serial device
1
MHS
Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol
2
3
read-write
disable
handshaking interface is disabled
0
enable
handshaking interface is enabled
1
MWMOD
The Micro wire transfer is sequential or non-sequential
0
1
read-write
disable
non-sequential transfer
0
enable
sequential transfer
1
RESERVED1
Reserved for future use
3
32
read-write
RISR
Raw Interrupt Status Register
0x34
32
read-only
n
0x0
MSTIR
Multi-Master Contention Raw Interrupt Status
5
6
read-only
disable
ssi_mst_intr interrupt is not active prior to masking
0
enable
ssi_mst_intr interrupt is active prior masking
1
RESERVED1
Reserved for future use
6
32
read-only
RXFIR
Receive FIFO Full Raw Interrupt Status
4
5
read-only
disable
ssi_rxf_intr interrupt is not active prior to masking
0
enable
ssi_rxf_intr interrupt is active prior to masking
1
RXOIR
Receive FIFO Overflow Raw Interrupt Status
3
4
read-only
disable
ssi_rxo_intr interrupt is not active prior to masking
0
enable
ssi_rxo_intr interrupt is active prior masking
1
RXUIR
Receive FIFO Underflow Raw Interrupt Status
2
3
read-only
disable
ssi_rxu_intr interrupt is not active prior to masking
0
enable
ssi_rxu_intr interrupt is active prior to masking
1
TXEIR
Transmit FIFO Empty Raw Interrupt Status
0
1
read-only
disable
ssi_txe_intr interrupt is not active prior to masking
0
enable
ssi_txe_intr interrupt is active prior masking
1
TXOIR
Transmit FIFO Overflow Raw Interrupt Status
1
2
read-only
disable
ssi_txo_intr interrupt is not active prior to masking
0
enable
1 = ssi_txo_intr interrupt is active prior masking
1
RXFLR
Receive FIFO Level Register
0x24
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
RXTFL
Contains the number of valid data entries in the receive FIFO
0
5
read-only
RXFTLR
Receive FIFO Threshold Level
0x1C
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
RFT
Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt
0
4
read-write
RXOICR
Receive FIFO Overflow Interrupt Clear Register
0x3C
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXOICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt
0
1
read-only
RXUICR
Receive FIFO Underflow Interrupt Clear Register
0x40
32
read-only
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-only
RXUICR
This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt
0
1
read-only
RX_SAMPLE_DLY
Rx Sample Delay Register
0xF0
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
8
32
read-write
RSD
Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal.
0
8
read-write
SER
SLAVE ENABLE REGISTER
0x10
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
SER
Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master.
0
4
read-write
disable
Not selected
0
enable
selected
1
SPI_CTRLR0
SPI control Register
0xF4
32
read-write
n
0x0
0x0
ADDR_L
This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO
2
6
read-write
INST_L
DUAL/QUAD length in bits
8
10
read-write
RESERVED1
Reserved for future use
6
8
read-only
RESERVED2
Reserved for future use
10
11
read-only
RESERVED3
Reserved for future use
15
32
read-only
TRANS_TYPE
Address and instruction transfer format
0
2
read-write
WAIT_CYCLES
This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles
11
15
read-write
SR
Status Register
0x28
32
read-only
n
0x0
BUSY
indicates that a serial transfer is in progress
0
1
read-only
disable
SSI is idle or disabled
0
enable
SSI is actively transferring data
1
DCOL
This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer
6
7
read-only
disable
No error
0
enable
Transmit data collision error
1
RESERVED1
Reserved for future use
7
32
read-only
RFF
When the receive FIFO is completely full this bit is set
4
5
read-only
disable
Receive FIFO is not full
0
enable
Receive FIFO is full
1
RFNE
Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty
3
4
read-only
disable
Receive FIFO is empty
0
enable
Receive FIFO is not empty
1
TFE
When the transmit FIFO is completely empty this bit is set
2
3
read-only
disable
Transmit FIFO is not empty
0
enable
Transmit FIFO is empty
1
TFNF
Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full
1
2
read-only
disable
Transmit FIFO is full
0
enable
Transmit FIFO is not full
1
TXE
This bit is cleared when read
5
6
read-only
disable
No error
0
enable
Transmission error
1
SSIENR
SSI Enable Register
0x8
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
1
32
read-write
SSI_EN
Enables and disables all ssi operations
0
1
read-write
SSI_COMP_VERSION
coreKit version ID register
0x5C
32
read-only
n
0x0
0x0
SSI_COMP_VERSION
Contains the hex representation of the Synopsys component version
0
32
read-only
TXFLR
Transmit FIFO Level Register
0x20
32
read-only
n
0x0
RESERVED1
Reserved for future use
5
32
read-only
TXTFL
Contains the number of valid data entries in the transmit FIFO
0
5
read-only
TXFTLR
Transmit FIFO Threshold Level Register
0x18
32
read-write
n
0x0
0x0
RESERVED1
Reserved for future use
4
32
read-write
TFT
Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt
0
4
read-write
TXOICR
Transmit FIFO Overflow Interrupt Clear Register
0x38
32
read-only
n
0x0
RESERVED1
Reserved for future use
1
32
read-only
TXOICR
Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt
0
1
read-only
ULTRA_LOW_POWER_DOMAINS
This is explain the Ultra low power domains peripherals registers.
ULTRA_LOW_POWER_DOMAINS
0x0
0x0
0x14
registers
n
SHIP_MODE_CTRL
SHIP Mode Entry/Exit Configuration Register.
0x10
32
read-write
n
0x0
ENTER_SHELF_MODE
Writing 0xAAAA to this provides immediate trigger to SHIP mode.
0
16
write-only
RESERVED1
It is recommended to write these bits to 0.
22
32
read-write
RESET_TIME_FROM_SHIP_MODE
Configures the Reset time in number of clocks @32KHz RC Clock during exit from SHIP mode.
19
22
read-write
SHIP_MODE_ENTRY_CFG
Configures the Trigger for entering SHIP mode.Writing 1 to this enable entry to SHIP mode on Falling edge on the UULP Vbat GPIO configuration as mentioned in SHUTDOWN_WAKEUP_CFG.
18
19
read-write
SHUTDOWN_WAKEUP_CFG
Enables the Wakeup trigger from SHIP mode based on rising edge of the below combinations.
16
18
read-write
00
UULP Vbat GPIO 2.
00
01
UULP Vbat GPIO 3.
1
10
UULP Vbat GPIO2 AND UULP Vbat GPIO3
2
11
UULP Vbat GPIO 2 OR UULP Vbat GPIO3.
3
UULP_PERIPHERAL_POWER_CONTROL_SET
Enables power for UULP-PERIPHERALS domains
0x0
32
read-write
n
0x0
PWRCTRL_BBFFS
It is enable power control to BBFFS.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the BBFFS.
1
PWRCTRL_CLOCK_CALIB
Writing 1 to this enables power to the CLOCK-CALIB.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the CLOCK-CALIB.
1
PWRCTRL_FSM
It is enable power control to FSM.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the FSM.
1
PWRCTRL_PS
It is enable power control to PS.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the PS.
1
PWRCTRL_RTC
It is enable power control to RTC.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the RTC.
1
PWRCTRL_STORAGE_DOMAIN1
Writing 1 to this enables power to the STORAGE-DOMAIN1.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the STORAGE-DOMAIN1.
1
PWRCTRL_STORAGE_DOMAIN2
Writing 1 to this enables power to the STORAGE-DOMAIN2.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the STORAGE-DOMAIN2.
1
PWRCTRL_STORAGE_DOMAIN3
Writing 1 to this enables power to the STORAGE-DOMAIN3.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the STORAGE-DOMAIN3.
1
PWRCTRL_TS
Writing 1 to this enables power to the TS.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the PS.
1
PWRCTRL_WDT
It is enable power control to WDT.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the WDT.
1
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
11
32
read-write
UULP_PERIPHRAL_POWER_CONTROL_CLEAR
Disables power for UULP-PERIPHERALS domains
0x4
32
read-write
n
0x0
PWRCTRL_BBFFS
It is disable power control to BBFFS.
1
2
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the BBFFS.
1
PWRCTRL_CLOCK_CALIB
It is disable power control to the CLOCK-CALIB.
10
11
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the CLOCK-CALIB.
1
PWRCTRL_FSM
It is disable power control to FSM.
2
3
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the FSM.
1
PWRCTRL_PS
It is disable power control to PS.
5
6
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the PS.
1
PWRCTRL_RTC
It is disable power control to RTC.
3
4
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the RTC.
1
PWRCTRL_STORAGE_DOMAIN1
It is disable power control to STORAGE-DOMAIN1.
7
8
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the STORAGE-DOMAIN1.
1
PWRCTRL_STORAGE_DOMAIN2
It is disable power control to the STORAGE-DOMAIN2.
8
9
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the STORAGE-DOMAIN2.
1
PWRCTRL_STORAGE_DOMAIN3
It is disable power control to the STORAGE-DOMAIN3.
9
10
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this enables power to the STORAGE-DOMAIN3.
1
PWRCTRL_TS
It is disable power control to TS.
6
7
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the PS.
1
PWRCTRL_WDT
It is disable power control to WDT.
4
5
read-write
Disable
Writing 0 to this has no effect.
0
Enable
Writing 1 to this disables power to the WDT.
1
RESERVED1
It is recommended to write these bits to 0.
0
1
read-write
RESERVED2
It is recommended to write these bits to 0.
11
32
read-write
USBHS
The Universal Serial Bus (USB) is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals
USB
0x0
0x0
0x200
registers
n
USB
73
ASYNCLISTADDR
Next Asynchronous List Address Register
0x158
32
read-write
n
0x0
0x0
BURSTSIZE
Programmable Burst Size Register
0x160
32
read-write
n
0x0
0x0
CAPLENGTH
Capability Length Register
0x100
32
read-only
n
0x0
0x0
CONFIGFLAG
Configured Flag Register
0x180
32
read-write
n
0x0
0x0
CTRLDSSEGMENT
Control Data Structure Segment Register
0x150
32
read-write
n
0x0
0x0
DCCPARAMS
Device Ctrl. Capability Parameters Register
0x124
32
read-only
n
0x0
DCIVERSION
Dev. Interface Version Number Register
0x120
32
read-only
n
0x0
DEVICEADDR
USB Device Address Register
PERIODICLISTBASE
0x154
32
read-write
n
0x0
0x0
ENDPOINTLISTADDR
Address at Endpoint list in memory Register
ASYNCLISTADDR
0x158
32
read-write
n
0x0
0x0
ENDPTCOMPLETE
Endpoint Complete Register
0x1BC
32
read-write
n
0x0
0x0
ENDPTCTRL0
Endpoint Control Address 0 Register
0x1C0
32
read-write
n
0x0
0x0
ENDPTCTRL1
Endpoint Control Address 1 Register
0x1C4
32
read-write
n
0x0
0x0
ENDPTCTRL10
Endpoint Control Address 10 Register
0x1E8
32
read-write
n
0x0
0x0
ENDPTCTRL11
Endpoint Control Address 11 Register
0x1EC
32
read-write
n
0x0
0x0
ENDPTCTRL12
Endpoint Control Address 12 Register
0x1F0
32
read-write
n
0x0
0x0
ENDPTCTRL13
Endpoint Control Address 13 Register
0x1F4
32
read-write
n
0x0
0x0
ENDPTCTRL14
Endpoint Control Address 14 Register
0x1F8
32
read-write
n
0x0
0x0
ENDPTCTRL15
Endpoint Control Address 15 Register
0x1FC
32
read-write
n
0x0
0x0
ENDPTCTRL2
Endpoint Control Address 2 Register
0x1C8
32
read-write
n
0x0
0x0
ENDPTCTRL3
Endpoint Control Address 3 Register
0x1CC
32
read-write
n
0x0
0x0
ENDPTCTRL4
Endpoint Control Address 4 Register
0x1D0
32
read-write
n
0x0
0x0
ENDPTCTRL5
Endpoint Control Address 5 Register
0x1D4
32
read-write
n
0x0
0x0
ENDPTCTRL6
Endpoint Control Address 6 Register
0x1D8
32
read-write
n
0x0
0x0
ENDPTCTRL7
Endpoint Control Address 7 Register
0x1DC
32
read-write
n
0x0
0x0
ENDPTCTRL8
Endpoint Control Address 8 Register
0x1E0
32
read-write
n
0x0
0x0
ENDPTCTRL9
Endpoint Control Address 9 Register
0x1E4
32
read-write
n
0x0
0x0
ENDPTFLUSH
Endpoint De_Initialize Register
0x1B4
32
read-write
n
0x0
0x0
ENDPTNAK
Endpoint NAK Registerr
0x178
32
read-write
n
0x0
0x0
ENDPTNAKEN
Endpoint NAK Enable Register
0x17C
32
read-write
n
0x0
0x0
ENDPTPRIME
Endpoint Initialization Register
0x1B0
32
read-write
n
0x0
0x0
ENDPTSETUPSTAT
Endpoint Setup Status Register
0x1AC
32
read-write
n
0x0
0x0
ENDPTSTAT
Endpoint Status Register
0x1B8
32
read-write
n
0x0
0x0
FRINDEX_D
USB Frame Index (device mode)Register
FRINDEX_H
0x14C
32
read-write
n
0x0
0x0
FRINDEX_H
USB Frame Index(host mode) Register
0x14C
32
read-write
n
0x0
0x0
GPTIMER0CTRL
General Purpose Timer 0 Control Register
0x84
32
read-write
n
0x0
0x0
GPTIMER0LD
General Purpose Timer 0 Load Register
0x80
32
read-write
n
0x0
0x0
GPTIMER1CTRL
General Purpose Timer 1 Control Register
0x8C
32
read-write
n
0x0
0x0
GPTIMER1LD
general purpose timer 1 load register
0x88
32
read-write
n
0x0
0x0
HCCPARAMS
Host Ctrl. Capability Parameters Register
0x108
32
read-only
n
0x0
HCSPARAMS
Host Ctrl. Structural Parameters Register
0x104
32
read-only
n
0x0
HWDEVICE
Device Hardware Parameters Register
0xC
32
read-only
n
0x0
0x0
HWGENERAL
General Hardware Parameters Register
0x4
32
read-only
n
0x0
0x0
HWHOST
Host Hardware Parameters Register
0x8
32
read-only
n
0x0
0x0
HWRXBUF
RX Buffer Hardware Parameters Register
0x14
32
read-only
n
0x0
0x0
HWTXBUF
TX Buffer Hardware Parameters Register
0x10
32
read-only
n
0x0
0x0
IC_USB
IC_USB enable and voltage negotiation Register
0x16C
32
read-write
n
0x0
0x0
IDENTIFICATION_REGISTER
IDENTIFICATION_REGISTER
0x0
32
read-only
n
0x0
0x0
OTGSC
OTG status and control register
0x1A4
32
read-write
n
0x0
0x0
PERIODICLISTBASE
Frame List Base Address Register
0x154
32
read-write
n
0x0
0x0
PORTSC1_D
Multi Port Status/Control (device mode)Register
PORTSC1_H
0x184
32
read-write
n
0x0
0x0
PORTSC1_H
Multi Port Status/Control(host mode) Register
0x184
32
read-write
n
0x0
0x0
SBUSCFG
Control for the System Bus interface Register
0x90
32
read-write
n
0x0
0x0
TTCTRL
TT Status and Control Register
0x15C
32
read-write
n
0x0
0x0
TXFILLTUNING
Host Transmit Pre_Buffer Packet Tuning Register
0x164
32
read-write
n
0x0
0x0
ULPIVIEWPORT
ULPI Viewport Registerr
0x170
32
read-write
n
0x0
0x0
USBCMD_D
USB Command(device mode) Register
USBCMD_H
0x140
32
read-write
n
0x0
0x0
USBCMD_H
USB Command(host mode) Register
0x140
32
read-write
n
0x0
0x0
USBINTR_D
USB Interrupt Enable(device mode) Register
USBINTR_H
0x148
32
read-write
n
0x0
0x0
USBINTR_H
USB Interrupt Enable(host mode))Register
0x148
32
read-write
n
0x0
0x0
USBMODE_D
USB Device Mode(device) Register
USBMODE_H
0x1A8
32
read-write
n
0x0
0x0
USBMODE_H
USB Device Mode (host)Register
0x1A8
32
read-write
n
0x0
0x0
USBSTS_D
USB Status(device mode) Register
USBSTS_H
0x144
32
read-write
n
0x0
0x0
USBSTS_H
USB Status (host mode)Register
0x144
32
read-write
n
0x0
0x0
USRT0
Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets
UART_USRT
0x0
0x0
0x100
registers
n
USART1
38
CPR
Component Parameter Register
0xF4
32
read-only
n
ADDITIONAL_FEAT
none
8
9
read-only
AFCE_MODE
none
4
5
read-only
APB_DATA_WIDTH
APB data width register.
0
2
read-only
DMA_EXTRA
none
13
14
read-only
FIFO_ACCESS
none
9
10
read-only
FIFO_MODE
none
16
24
read-only
FIFO_STAT
none
10
11
read-only
RESERVED1
reserved1
2
4
read-only
RESERVED2
reserved2
14
16
read-only
RESERVED3
reserved3
24
32
read-only
SHADOW
none
11
12
read-only
SIR_LP_MODE
none
7
8
read-only
SIR_MODE
none
6
7
read-only
THRE_MODE
none
5
6
read-only
UART_ADD_ENCODED_PARAMS
none
12
13
read-only
CTR
Component Type Register
0xFC
32
read-only
n
0x0
UART_COMP_VER
This register contains the peripherals identification code.
0
32
read-only
DE_EN
Driver Output Enable Register.
0xB0
32
read-write
n
0x0
DE_EN
DE Enable control.
0
1
read-write
RESERVED1
reserved1
1
32
read-only
DLF
Divisor Latch Fraction Register.
0xC0
32
read-write
n
0x0
DLF
Fractional part of divisor.
0
4
read-write
RESERVED1
reserved1
4
32
read-only
DLH
Divisor Latch High
IER
0x4
32
read-write
n
0x0
0x0
DLH
Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DLL
Divisor Latch Low
0x0
32
read-write
n
0x0
0x0
DLL
Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
DMASA
DMA Software Acknowledge
0xA8
32
read-write
n
0x0
0x0
DMA_SOFTWARE_ACK
This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition
0
1
write-only
RESERVED1
reserved1
1
32
read-only
DTE
Driver Output Enable Timing Register.
0xB8
32
read-write
n
0x0
DE_ASSERT_TIME
Driver enable assertion time.
0
8
read-write
DE_DE_ASSERT_TIME
Driver enable de-assertion time.
16
24
read-write
RES
reserved.
8
16
RESERVED1
reserved1
24
32
read-only
FAR
none
0x70
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SYNC_MODE
none
0
1
read-write
FIFO_ACCESS_DISABLE
FIFO access mode disabled
0
FIFO_ACCESS_ENABLE
FIFO access mode enabled
1
FCR
FIFO Control Register
0x8
32
write-only
n
0x0
0x0
DMAM
DMA signalling mode
3
4
write-only
Mode0
DMA Signalling mode0
0
Mode1
DMA Signalling mode1
1
FIFOE
This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs
0
1
write-only
RESERVED1
reserved1
8
32
write-only
RFIFOR
RCVR FIFO Reset
1
2
write-only
RT
This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated
6
8
write-only
FIFO_1_CHARACTER
1 character in the FIFO
0
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
1
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
2
FIFO_LESS_THAN_2_CHARACTER
FIFO 2 less than full
3
TET
TX Empty Trigger
4
6
write-only
FIFO_EMPTY
FIFO Empty
0
FIFO_2_CHARACTER
2 characters in the FIFO
1
FIFO_1_BY_4_CHARACTER
FIFO 1/4 full
2
FIFO_1_BY_2_CHARACTER
FIFO 1/2 full
3
XFIFOR
XMIT FIFO Reset
2
3
write-only
HDEN
none
0x40
32
read-write
n
0x0
0x0
FULL_DUPLEX_MODE
none
0
1
read-write
DISABLE
Full duplex mode disable
0
ENABLE
Full duplex mode enable
1
RESERVED1
reserved1
2
32
read-only
TX_MODE_RX_MODE
This signal is valid when full_duplex_mode is disabled
1
2
read-write
tx_mode
tx_mode
0
rx_mode
rx_mode
1
HTX
Halt Transmit
0xA4
32
read-write
n
0x0
0x0
HALT_TX
This register is use to halt transmissions for testing
0
1
read-write
Disabled
Halt TX disabled
0
Enabled
Halt TX enabled
1
RESERVED1
reserved1
1
32
read-only
IER
Interrupt Enable Register
0x4
32
read-write
n
0x0
0x0
EDSSI
Enable Modem Status Interrupt
3
4
read-write
Disable
Modem Status Interrupt is disabled
0
Enable
Modem Status Interrupt is enabled
1
ELSI
Enable Receiver Line Status Interrupt
2
3
read-write
Disable
Receiver Line Status Interrupt is disabled
0
Enable
Receiver Line Status Interrupt is enabled
1
ERBFI
Enable Received Data Available Interrupt
0
1
read-write
Disable
Received Data Available Interrupt is disabled
0
Enable
Received Data Available Interrupt is enabled
1
ETBEI
Enable Transmit Holding Register Empty Interrupt
1
2
read-write
Disable
Transmit Holding Register Empty Interrupt is disabled
0
Enable
Transmit Holding Register Empty Interrupt is enabled
1
PTIME
Programmable THRE Interrupt Mode Enable
7
8
read-write
Disable
generation of THRE Interrupt is disabled
0
Enable
generation of THRE Interrupt is enabled
1
RESERVED1
reserved1
4
7
read-only
RESERVED2
reserved2
8
32
read-only
IIR
Interrupt Identity Register
0x8
32
read-only
n
0x0
FIFOSE
This is used to indicate whether the FIFOs are enabled or disabled.
6
8
read-only
Disable
FIFO is disabled
0
Enable
FIFO is enabled
1
IID
Interrupt ID
0
4
read-only
0000
modem status pending pending interrupt
0
0001
This field indicates no interrupt pending status
1
1100
Character Timeout pending interrupt
12
0010
Transmit Holding Register Empty pending interrupt
2
0100
Received Data Available pending interrupt
4
0110
Receive line status pending interrupt
6
0111
Busy detect pending interrupt
7
RESERVED1
reserved1
4
6
read-only
RESERVED2
reserved2
8
32
read-only
LCR
Line Control Register
0xC
32
read-write
n
0x0
0x0
BC
This is used to cause a break condition to be transmitted to the receiving device
6
7
read-write
SERIAL_OUTPUT_SPACING_STATE
If set to 1, the serial output is forced to the spacing (logic 0) state
0
DLAB
This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART
7
8
read-write
INIT_BAUD_RATE_SET
This bit must be cleared after initial baud rate set up
0
DLS
Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives
0
2
read-write
5_BITS_PER_CHARACTER
5 bits per character
0
6_BITS_PER_CHARACTER
6 bits per character
1
7_BITS_PER_CHARACTER
7 bits per character
2
8_BITS_PER_CHARACTER
8 bits per character
3
EPS
This is used to select between even and odd parity
4
5
read-write
Set to 0
An odd number of logic 1s is transmitted or checked
0
Set to 1
An even number of logic 1s is transmitted or checked
1
PEN
This bit is used to enable and disable parity generation and detection in transmitted and received serial character
3
4
read-write
Disable
Parity disabled
0
Enable
Parity Enabled
1
RESERVED1
reserved1
8
32
read-only
STICK_PARITY
This bit is used to force parity value
5
6
read-write
LOGIC0
When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0
0
LOGIC1
If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1
1
STOP
This is used to select the number of stop bits per character that the peripheral transmits and receives
2
3
read-write
1_STOP_BIT_PER_CHARACTER
1 stop bit per character
0
1.5_OR_2_STOPS_BIT_PER_CHARACTER
1.5 or 2 stop bits per character
1
LCR_EXT
Line Extended Control Register
0xCC
32
read-write
n
0x0
ADDR_MATCH
Address Match Mode.
1
2
read-write
DLS_E
Extension for DLS.
0
1
read-write
RESERVED1
reserved1
4
32
read-only
SEND_ADDR
Send address control bit.
2
3
read-write
TRANSMIT_MODE
Transmit mode control bit.
3
4
read-write
LPDLH
Low Power Divisor Latch High Register
0x24
32
read-write
n
0x0
0x0
LOW_POWER_DLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LPDLL
Low Power Divisor Latch Low Register
0x20
32
read-write
n
0x0
0x0
LOW_POWER_DLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K
0
8
read-write
RESERVED1
reserved1
8
32
read-only
LSR
Line Status Register
0x14
32
read-only
n
0x0
ADDRRCVD
Address Received bit
8
9
read-only
BI
his is used to indicate the detection of a break sequence on the serial input data
4
5
read-only
DR
This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO
0
1
read-only
Disabled
No data Ready
0
Enabled
Data Ready
1
FE
This is used to indicate the occurrence of a framing error in the receiver
3
4
read-only
Disabled
no framing error
0
Enabled
framing error
1
OE
This is used to indicate the occurrence of an overrun error
1
2
read-only
Disabled
no overrun error
0
Enabled
overrun error
1
PE
This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set
2
3
read-only
Disabled
no parity error
0
Enabled
parity error
1
RESERVED1
reserved1
9
32
read-only
RFE
This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO
7
8
read-only
Disabled
no error in RX FIFO
0
Enabled
error in RX FIFO
1
TEMT
Transmitter Empty bit
6
7
read-only
THRE
Transmit Holding Register Empty bit
5
6
read-only
MCR
Modem Control Register
0x10
32
read-write
n
0x0
0x0
AFCE
This is used to directly control the user-designated Output2 (out2_n) output
5
6
read-write
Disabled
Auto Flow Control Mode disabled
0
Enabled
Auto Flow Control Mode enabled
1
DTR
This is used to directly control the Data Terminal Ready (dtr_n) output
0
1
read-write
DTR_LOGIC1
dtr_n de-asserted (logic 1)
0
DTR_LOGIC0
dtr_n asserted (logic 0)
1
LB
This is used to put the UART into a diagnostic mode for test purposes
4
5
read-write
OUT1
This is used to directly control the user-designated Output1 (out1_n) output
2
3
read-write
OUT1_LOGIC1
out1_n de-asserted (logic 1)
0
OUT1_LOGIC0
out1_n asserted (logic 0)
1
OUT2
This is used to directly control the user-designated Output2 (out2_n) output
3
4
read-write
OUT2_LOGIC1
out2_n de-asserted (logic 1)
0
OUT2_LOGIC0
out2_n asserted (logic 0)
1
RESERVED1
reserved1
7
32
read-only
RTS
This is used to directly control the Request to Send (rts_n) output
1
2
read-write
SIRE
This is used to enable/disable the IrDA SIR Mode features
6
7
read-write
Disabled
IrDA SIR Mode disabled
0
Enabled
IrDA SIR Mode enabled
1
MSR
Modem Status Register
0x18
32
read-only
n
0x0
0x0
CTS
This is used to indicate the current state of the modem control line cts_n
4
5
read-only
Disabled
cts_n input is de-asserted (logic 1)
0
Enabled
cts_n input is asserted (logic 0)
1
DCD
This is used to indicate the current state of the modem control line dcd_n
7
8
read-only
Disabled
dcd_n input is de-asserted (logic 1)
0
Enabled
dcd_n input is asserted (logic 0)
1
DCTS
This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read
0
1
read-only
Disabled
no change on cts_n since last read of MSR
0
Enabled
change on cts_n since last read of MSR
1
DDCD
This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read
3
4
read-only
Disabled
no change on dcd_n since last read of MSR
0
Enabled
change on dcd_n since last read of MSR
1
DDSR
This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read
1
2
read-only
Disabled
no change on dsr_n since last read of MSR
0
Enabled
change on dsr_n since last read of MSR
1
DSR
This is used to indicate the current state of the modem control line dsr_n
5
6
read-only
Disabled
dsr_n input is de-asserted (logic 1)
0
Enabled
dsr_n input is asserted (logic 0)
1
RESERVED1
reserved1
8
32
read-only
RI
This is used to indicate the current state of the modem control line ri_n
6
7
read-only
Disabled
ri_n input is de-asserted (logic 1)
0
Enabled
ri_n input is asserted (logic 0)
1
TERI
This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state) has occurred since the last time the MSR was read
2
3
read-only
Disabled
no change on ri_n since last read of MSR
0
Enabled
change on ri_n since last read of MSR
1
RAR
Receive Address Register.
0xC4
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
RBR
Receive Buffer Register
DLL
0x0
32
read-only
n
0x0
0x0
RBR
Receive Buffer Field
0
8
read-only
RESERVED1
reserved1
8
32
read-only
RE_EN
Receiver Output Enable Register.
0xB4
32
read-write
n
0x0
RESERVED1
reserved1
1
32
read-only
RE_EN
RE Enable control.
0
1
read-write
RFL
Receive FIFO Level
0x84
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
RFW
none
0x78
32
read-write
n
0x0
RESERVED1
reserved1
10
32
read-only
RFFE
Receive FIFO Framing Error
9
10
read-write
RFPE
Receive FIFO Parity Error
8
9
read-write
RFWD
Receive FIFO Write Data
0
8
read-write
SBCR
Shadow Break Control Register
0x90
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SBCR
Shadow Break Control Bit
0
1
read-write
SCR
Scratch pad Register
0x1C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
8
32
read-only
SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose
0
8
read-write
SDMAM
Shadow DMA Mode
0x94
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SDMAM
Shadow DMA Mode
0
1
read-write
MODE0
mode 0
0
MODE1
mode 1
1
SFE
Shadow FIFO Enable
0x98
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SFE
Shadow FIFO Enable
0
1
read-write
SMCR
none
0x58
32
read-write
n
0x0
0x0
CONTI_CLK_MODE
none
4
5
read-write
NON_CONTINUOUS_CLK_MODE
Non-continuous clock mode
0
CONTINUOUS_CLK_MODE
Continuous clock mode
1
MST_MODE
none
1
2
read-write
NON_MST_MODE
Non-MST mode
0
MST_MODE
MST mode
1
RESERVED1
reserved1
6
32
read-only
START_STOP_EN
none
5
6
read-write
DISABLE_START_STOP
Disable start stop
0
ENABLE_START_STOP
Enable start stop
1
SYNC_MODE
none
0
1
read-write
NON_SYNC_MODE
Non-Sync mode
0
SYNC_MODE
Sync mode
1
SRR
Software Reset Register
0x88
32
write-only
n
0x0
RESERVED1
reserved1
3
32
write-only
RFR
RCVR FIFO Reset
1
2
write-only
UR
UART Reset
0
1
write-only
XFR
XMIT FIFO Reset
2
3
write-only
SRT
Shadow RCVR Trigger
0x9C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
SRT
Shadow RCVR Trigger
0
2
read-write
SRTS
Shadow Request to Send
0x8C
32
read-write
n
0x0
0x0
RESERVED1
reserved1
1
32
read-only
SRTS
Shadow Request to Send.
0
1
read-write
STET
Shadow TX Empty Trigger
0xA0
32
read-write
n
0x0
0x0
RESERVED1
reserved1
2
32
read-only
STET
Shadow TX Empty Trigger
0
2
read-write
TAR
Transmit Address Register.
0xC8
32
read-write
n
0x0
RAR
This is an address matching register during receive mode.
0
8
read-write
RESERVED1
reserved1
8
32
read-only
TAT
TurnAround Timing Register
0xBC
32
read-write
n
0x0
DE_RE
Driver Enable to Receiver Enable TurnAround time.
0
16
read-write
RE_DE
Receiver Enable to Driver Enable TurnAround time.
16
32
read-write
TCR
Transceiver Control Register.
0xAC
32
read-write
n
0x0
DE_POL
Driver Enable Polarity.
2
3
read-write
RESERVED1
reserved1
5
32
read-only
RE_POL
Receiver Enable Polarity.
1
2
read-write
RS485_EN
RS485 Transfer Enable.
0
1
read-write
XFER_MODE
Transfer Mode.
3
5
read-write
TFL
Transmit FIFO Level
0x80
32
read-only
n
0x0
FIFO_ADDR_WIDTH
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
30
read-only
RESERVED1
reserved1
30
32
read-only
TFR
none
0x74
32
read-only
n
0x0
RESERVED1
reserved1
8
32
read-only
TX_FIFO_RD
Transmit FIFO Read
0
8
read-only
THR
Transmit Holding Register
DLL
0x0
32
write-only
n
0x0
0x0
RESERVED1
reserved1
8
32
write-only
THR
Data to be transmitted on serial output port
0
8
write-only
UCV
UART Component Version
0xF8
32
read-only
n
0x0
UART_COMP_VER
ASCII value for each number in the version, followed by *
0
32
read-only
USR
UART Status Register
0x7C
32
read-only
n
0x0
BUSY
Indicates that a serial transfer is in progress
0
1
read-only
Disabled
UART is idle or inactive
0
Enabled
UART is busy (actively transferring data)
1
RESERVED1
reserved1
5
32
read-only
RFE
To Indicate that the receive FIFO is completely full
4
5
read-only
Disabled
Receive FIFO not full
0
Enabled
Receive FIFO Full
1
RFNE
To Indicate that the receive FIFO contains one or more entries
3
4
read-only
Disabled
Receive FIFO is empty
0
Enabled
Receive FIFO is not empty
1
TFE
To Indicate that the transmit FIFO is completely empty
2
3
read-only
Disabled
Transmit FIFO is not empty
0
Enabled
Transmit FIFO is empty
1
TFNF
To Indicate that the transmit FIFO is not full
1
2
read-only
Disabled
Transmit FIFO is full
0
Enabled
Transmit FIFO is not full
1
VAD
VAD (Voice-Activity-Detection) is an hardware accelerator to detect voice activity on the samples provided by the Processor
VAD
0x0
0x0
0x28
registers
n
VAD_INTR_PING
0
VAD_INTR_PONG
1
CONF_REG1
Configuration Registers1 for VAD
0x0
32
read-write
n
0x0
ENABLE_DC_REMOVAL
enable dc removal
23
24
read-write
FULL_WIDTH
This bit is define number of samples
24
25
read-write
1_SAMPLE
Writing 1 to this indicates that the 32-bits are used to store 1 10-bit samples
0
2_SAMPLE
Writing 1 to this indicates that the 32-bits are used to store 2 10-bit samples
1
NORMALIZE_FRAME
Normalize frame
22
23
read-write
RESERVED2
Reserved2
25
32
read-write
SAMPLS_PER_FRAME
Indicates the number of samples in one processing frame
0
10
read-write
SMPLS_PER_ADDR
Indicates the bit width of the samples
20
22
read-write
Reserved1
Reserved1
0
Sixteenbit_sample
bit width of sample is 16 bit
1
Thritytwobit_sample
bit width of sample is 32 bit
2
THRESHOLD_MAG
Indicates the magnitude threshold for the AMDF algorithm
10
20
read-write
CONF_REG10
Configuration Registers10 for VAD
0x24
32
read-write
n
0x0
PROG_DC_REMOVAL
12 bit DC correction for ADC source
0
12
read-write
RESERVED2
It is recommended to write these bits to 0
29
32
read-write
CONF_REG2
Configuration Registers2 for VAD
0x4
32
read-write
n
0x0
RESERVED1
Reserved1
10
20
read-write
RESERVED2
Reserved2
20
32
read-write
SMPLS_ZERO_CROSS
Indicates the threshold for number of zero crossings to ensure detection using ZCR algorithm
0
10
read-write
CONF_REG3
Configuration Registers3 for VAD
0x8
32
read-write
n
0x0
MAX_DELAY
Max delay used in ACF, WACF and AMDF algorithms
22
32
read-write
PROG_SMPLS_FOR_ENERGY_CHECK
Indicates the number of samples for validating the energy of the samples before further processing
20
22
read-write
four_sample
four samples for validating the energy
0
eight_sample
eight samples for validating the energy
1
Sixteen_sample
Sixteen samples for validating the energy
2
Thirtytwo_sample
Thirty two samples for validating the energy
3
THRESHOLD_FRAME_ENERGY
Indicates the threshold for energy of the samples over the entire processing frame to start the algorithm execution.
0
10
read-write
THRESHOLD_SMPL_COLLECT
Indicates the threshold for energy of the samples
10
20
read-write
CONF_REG4
Configuration Registers4 for VAD
0xC
32
read-write
n
0x0
RESERVED1
It is recommended to write these bits to 0
24
32
read-write
THRESHOLD_ACF
Energy threshold for ACF algorithm
0
12
read-write
THRESHOLD_WACF
Energy threshold for WACF algorithm
12
24
read-write
CONF_REG5
Configuration Registers5 for VAD
0x10
32
read-write
n
0x0
AMDF_BY_SQARING
Enable or disable sqaring function for ADMF
22
23
read-write
RESERVED1
It is recommended to write these bits to 0
23
32
read-write
THRESHOLD_NULL
Indicates the threshold for determining a Null for AMDF algorithm to detect Voice activity.
0
12
read-write
THRESHOLD_NULL_COUNT
Indicates the threshold for number of Null's for AMDF algorithm to detect Voice activity.
12
22
read-write
CONF_REG6
Configuration Registers6 for VAD
0x14
32
read-write
n
0x0
RESERVED1
It is recommended to write these bits to 0
22
32
read-write
THRESHOLD_PEAK
Indicates the threshold for determining a Peak for AMDF algorithm to detect Voice activity
0
12
read-write
THRESHOLD_PEAK_COUNT
Indicates the threshold for number of Peak's for AMDF algorithm to detect Voice activity.
12
22
read-write
CONF_REG7
Configuration Registers7 for VAD
0x18
32
read-write
n
0x0
CHOOSE_VAD_METHOD
Indicates the combination of Algorithms to be used for Voice Activity Detection
20
23
read-write
ZCR
Zero crossing
0x0
ACF
ACF method
0x1
AMDF
AMDF method
0x2
WACF
WACF method
0x3
ZCR_ACF_AMDF_WACF
ZCR and ACF and AMDF and WACF method
0x4
ZCR_ACF
ZCR and ACF method
0x5
Reserved1
Reserved1
0x6
ZCR_WACF
ZCR and WACF
0x7
DATA_SOURCE_SELECT
Data source input select VAD peripheral
23
25
read-write
END_DELAY_VAL
End delay used in ACF, WACF and AMDF algorithms
10
20
read-write
RESERVED1
It is recommended to write these bits to 0
25
32
read-write
START_DELAY_VAL
Start delay used in ACF, WACF and AMDF algorithms
0
10
read-write
CONF_REG8
Configuration Registers8 for VAD
0x1C
32
read-write
n
0x0
EN_VAD_PROCESS
Enable vad process
10
11
read-write
Disable
Disable vad process
0
Enable
Enable vad process
1
INP_DATA
10 bit Samples Data used for VAD
0
10
read-write
RESERVED1
It is recommended to write these bits to 0
11
22
read-write
RESERVED2
It is recommended to write these bits to 0
23
32
read-write
VAD_PROC_DONE
Indicates that the VAD processing is done
22
23
read-only
CONF_REG9
Configuration Registers9 for VAD
0x20
32
read-write
n
0x0
PING_ADDR
Indicates the Start Address of Ping Memory containing the VAD samples
1
14
read-write
PING_INT_CLEAR
clears the VAD interrupt on Ping Buffer samples
27
28
write-only
PONG_ADDR
Indicates the Start Address of Pong Memory containing the VAD samples
14
27
read-write
PONG_INT_CLEAR
clears the VAD interrupt on Pong Buffer samples
28
29
write-only
RESERVED1
It is recommended to write these bits to 0
0
1
read-write
RESERVED2
It is recommended to write these bits to 0
29
32
read-write