Toshiba
TC35680
2024.04.29
TC35680
CM0
r0p0
little
true
true
4
false
8
32
BluetoothCounter
Bluetooth Counter
BluetoothCounter
0x0
0x0
0x100
registers
n
LLC_BC_LATCH_MA
Holding Master Bit Counter
0x20
32
read-only
n
0x0
0x0
BCntMa_Hold
Master bit counter value.
0
10
read-only
LLC_LLCNT_HOLD_EN
Hold Bluetooth counter
0xC
32
read-write
n
0x0
0x0
LLCntHold
When 0 (or arbitrary value) is set this register, the following registers will hold the values: LLC_BC_LATCH_MA:Master Bit Counter. LLC_SC_LATCH_MA:Master Slot Counter. Before accessing LLC_BC_LATCH_MA or LLC_SC_LATCH_MA, please set 0 (or arbitrary value) to this register.
0
1
read-write
LLC_SC_LATCH_MA
Holding Master Slot Counter
0x24
32
read-write
n
0x0
0x0
SCntMa_Hold
Master slot counter value. This counts up every 1 slot (625 micro seconds). Before reading this value, please set 0 (or arbitrary value) to LLCntHold.
0
27
read-write
CLOCK
Clock Supply for SPI and PWM
CLOCK
0x0
0x0
0x100
registers
n
CG_CG_CTRL
ckgn config register
0x80
32
read-write
n
0x0
0x0
SoftReset
Soft-Reset control 1: Soft-Reset 0: No change
5
6
read-write
WdCountSTOP
Start or stop WDT counter. 1: Stop counter. 0: Start counter. When set 1, WDT counter suspends. When set 0, WDT counter resumes. During the system state is low power mode, WDT does not count.
2
3
read-write
CG_CLK_CTRL
SPI Clock control
0x20
32
read-write
n
0x0
0x0
BitClkEn
Enable Bit Clock
0
1
read-write
DMAClkEn
ENable DMA Clock
12
13
read-write
ESGClkEn
Enable ESG Clock
26
27
read-write
FUSEClkEn
Enable FUSE Clock
7
8
read-write
GPIOClkEn
Enable GPIO Clock
24
25
read-write
I2CClkEn
Enable I2C Clock
8
9
read-write
LELLCClkEn
Enable LELLC Clock
4
5
read-write
MPHYDMACClkEn
Enable MPHDMAC Clock
5
6
read-write
OUIClkEn
Enable OIU Clock
25
26
read-write
PPLClkEn
Enable PPL Clock
29
30
read-write
QSPIClkEn
Enable QSPI Clock
11
12
read-write
RFBClkEn
Enable RFB Clock Enable
10
11
read-write
SPIClkEn
Enable SPI clock (R/W) 1: Enable clock 0: Disable clock (default)
9
10
read-write
SyncClkEn
Enable Sync Clock
1
2
read-write
TimerClkEn
Enable Timer Clock
13
14
read-write
Uart1ClkEn
Enable UART1 Clock
2
3
read-write
CG_CLK_CTRL2
PWM Clock Control
0x24
32
read-write
n
0x0
0x0
GPADCClkEn
Enable GPADC Clock
8
9
read-write
I2C2ClkEn
Enable I2C2 Clock
11
12
read-write
PWM0ClkEn
Enable PWM ch 0 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
0
1
read-write
PWM0SlpClkEn
Enable PWM ch 0 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
4
5
read-write
PWM1ClkEn
Enable PWM ch 1 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
1
2
read-write
PWM1SlpClkEn
Enable PWM ch 1 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
5
6
read-write
PWM2ClkEn
Enable PWM ch 2 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
2
3
read-write
PWM2SlpClkEn
Enable PWM ch 2 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
6
7
read-write
PWM3ClkEn
Enable PWM ch 3 fast clock (R/W). 1: Enable clock. 0: Disable clock (default)
3
4
read-write
PWM3SlpClkEn
Enable PWM ch 3 slow clock (R/W). 1: Enable clock. 0: Disable clock (default)
7
8
read-write
SPI2ClkEn
Enable SPI2 Clock
10
11
read-write
Uart2ClkEn
Enable UART2 Clock
9
10
read-write
CG_DIVNUM3
Division ratio for PWM1 and PWM0 config
0x10
32
read-write
n
0x0
0x0
PWM0_DIVNUM
Division ratio of 32MHz clock to generate PWM0 clock. PWM0 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
0
12
read-write
PWM1_DIVNUM
Division ratio of 32MHz clock to generate PWM1 clock. PWM1 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
16
28
read-write
CG_DIVNUM4
Division ratio for PWM3 and PWM2 config
0x14
32
read-write
n
0x0
0x0
PWM2_DIVNUM
Division ratio of 32MHz clock to generate PWM2 clock. PWM2 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
0
12
read-write
PWM3_DIVNUM
Division ratio of 32MHz clock to generate PWM3 clock. PWM3 clock ON/OFF can be set on CG_CLK_CTRL2 register. This value can be changed regardless of the clock ON/OFF. However, the output clock may be unstable right after the change of this register. division ratio = (this value + 1) * 2. default value is 0x000 (Divided by 2)
16
28
read-write
CG_DIVNUM5
Division ratio for GPADC config
0x18
32
read-write
n
0x0
0x0
GPADC_DIVNUM
Division ratio of 32MHz clock to generate GPADC clock. frequency divider = (value+1)*2
0
9
read-write
CG_PWM_CTRL
PWM clock mode set
0x4
32
read-write
n
0x0
0x0
PWM0ClkSel
Select PWM0 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM0SlpClkEn and PWM0ClkEn before changing this register.
0
1
read-write
PWM1ClkSel
Select PWM1 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM1SlpClkEn and PWM1ClkEn before changing this register.
1
2
read-write
PWM2ClkSel
Select PWM2 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM2SlpClkEn and PWM2ClkEn before changing this register.
2
3
read-write
PWM3ClkSel
Select PWM3 clock. 1: MAX 13 MHz (This division ratio can be changed in CG_DIVNUM4). 0: 32 kHz. Please set disable to PWM3SlpClkEn and PWM3ClkEn before changing this register.
3
4
read-write
CG_WD_CURNT
Watchdog current register
0xA4
32
read-write
n
0x0
0x0
WDTCURNT
Watchdog current value. When the system wakes up from low power mode, this value becomes WDINIT value.
0
21
read-write
CG_WD_INIT
Watchdog initial register
0xA0
32
read-write
n
0x0
0x0
WDINIT
Set initial value of WDT counter. This value can be set from 0x1(30.5 micro seconds) to 0x1FFFFF.(64 seconds). Setting time is calculated as below: setting time = (this value) * 30.5 micro seconds. When you update this value, please wait for more than 2 clocks of SleepClk(32kHz clock) since the previous change. When the system wakes up from low power mode, WDT counter is set this value.
0
21
read-write
DMAC
DMAC
DMAC
0x0
0x0
0x200
registers
n
DMA_ch0_Config
Channel0 Configuration Register
0x110
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch0_Contrl
Channel0 Control Register
0x10C
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat.
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte.
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch0_Dest
Channel0 Destination Address Register
0x104
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel0 is disabled on DMA_ch0_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch0_Link
Channel0 Linked ListItem Register
0x108
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch0_Source
Channel0 Source Address Register
0x100
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel0 is disabled on DMA_ch0_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch1_Config
Channel1 Configuration Register
0x130
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config.. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch1_Contrl
Channel1 Control Register
0x12C
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch1_Dest
Channel1 Destination Address Register
0x124
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel1 is disabled on DMA_ch1_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch1_Link
Channel1 Linked ListItem Register
0x128
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch1_Source
Channel1 Source Address Register
0x120
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel1 is disabled on DMA_ch1_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch2_Config
Channel2 Configuration Register
0x150
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable.. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch2_Contrl
Channel2 Control Register
0x14C
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch2_Dest
Channel2 Destination Address Register
0x144
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel2 is disabled on DMA_ch2_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch2_Link
Channel2 Linked ListItem Register
0x148
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch2_Source
Channel2 Source Address Register
0x140
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel2 is disabled on DMA_ch2_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch3_Config
Channel3 Configuration Register
0x170
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch3_Contrl
Channel3 Control Register
0x16C
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch3_Dest
Channel3 Destination Address Register
0x164
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel3 is disabled on DMA_ch3_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch3_Link
Channel3 Linked ListItem Register
0x168
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch3_Source
Channel3 Source Address Register
0x160
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel3 is disabled on DMA_ch3_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch4_Config
Channel4 Configuration Register
0x190
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch4_Contrl
Channel4 Control Register
0x18C
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch4_Dest
Channel4 Destination Address Register
0x184
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel4 is disabled on DMA_ch4_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch4_Link
Channel4 Linked ListItem Register
0x188
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch4_Source
Channel4 Source Address Register
0x180
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel4 is disabled on DMA_ch4_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch5_Config
Channel5 Configuration Register
0x1B0
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable. 0: enable the interrupt. 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch5_Contrl
Channel5 Control Register
0x1AC
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch5_Dest
Channel5 Destination Address Register
0x1A4
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel5 is disabled on DMA_ch5_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch5_Link
Channel5 Linked ListItem Register
0x1A8
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch5_Source
Channel5 Source Address Register
0x1A0
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel5 is disabled on DMA_ch5_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch6_Config
Channel6 Configuration Register
0x1D0
32
read-write
n
0x0
0x0
A
Check FIFO data of channel0. 0: No data in FIFO. 1: Data exists in FIFO
17
18
read-write
DestPeripheral
DMA destination peripheral number. Min: 0000. Max: 1111. If the destination is Memory, this value is ignored.
6
10
read-write
E
Set channel enable. 0: Disable. 1: Enable. After you set up the all DMA settings, set 1 to this register. When this value set disable during transfer, FIFO data of channel0 is erased. If you want to restart the transfer, please initialize all config of channel0 and restart the DMA. If you want to stop the transfer temporarily, please perform the following sequence: (1)Set 1 to register H, then DMA requirement stop. (2)Poll FIFO data until register A becomes 0 (FIFO if empty). (3)Set 0(disable) to this register, and write 0(disable) to register E.
0
1
read-write
FlowContrl
Transfer mode config. 000: Memory to Memory. 001: Memory to Pripheral. 010: Peripheral to Memory. 011: Peripheral to Peripheral. Other: Reserved. Attention: If Memory to Memory is chosen, the transfer can be started to write 1 to E.
11
14
read-write
H
Halt DMA. 0: No halt. 1: Halt(Ignore DMA request)
18
19
read-write
IE
DMA error interrupt enable. 0: enable the interrupt 1: disable the interrupt
14
15
read-write
ITC
DMA done interrupt enable. 0: enable the interrupt. 1: disable the interrupt
15
16
read-write
L
Set bus lock transfer config. 0: Forbid bus lock transfer. 1: Allow bus lock transfer. If bus lock transfer is allowed, specified burst size is transferred without releassing the bus.
16
17
read-write
SrcPeripheral
DMA source peripheral config register. Min: 0000. Max: 1111. If the source is Memory, this value is ignored.
1
5
read-write
DMA_ch6_Contrl
Channel6 Control Register
0x1CC
32
read-write
n
0x0
0x0
DBSize
Set destination burst size. 000: 1 beat. 001: 4 beat. 010: 8 beat. 011: 16 beat. 100: 32 beat. 101: 64 beat. 110: 128 beat. 111: 256 beat
15
18
read-write
DI
Set increment config of destination address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming changes according to DWidth. Each Increment timming is as follows: Bit width is 8bit: Increment every 1Byte. Bit width is 16bit: Increment every 2Byte. Bit width is 32bit: Increment every 4Byte
27
28
read-write
DWidth
Set destination bit width. 000: 8bit (Byte). 001: 16bit (Half word). 010: 32bit (Word). Other: Reserved
21
24
read-write
I
Set interrupt enable of Terminal Count. 0: Disable. 1: Enable
31
32
read-write
SBSize
Set source burst size. Same as DBSize
12
15
read-write
SI
Set increment config of source address. 0: Do not increment (The address is fixed). 1: Increment. Increment timming is the same as DI.
26
27
read-write
SWidth
Set source bit width. Same as DWidth
18
21
read-write
TransferSize
Set the number of transfers. This value is decremented on every DMA transfer. Read this value to know the number of left transfers. When DMA_ch_Config register [0] is enabled, this value can be read. The number of transfers is in unit of source bit width. Source bit width is 8bit: Set this register in unit of Byte. Source bit width is 16bit: Set this register in unit of Half word. Source bit width is 32bit: Set this register in unit of Word. Attention: If source bit width is smaller than destination bit width, you should be careful to set this. The following condition shall be satisfied: Source bit width * TransferSize = Destinetion bit width * N (N: integer)
0
12
read-write
DMA_ch6_Dest
Channel6 Destination Address Register
0x1C4
32
read-write
n
0x0
0x0
DestAddr
Set DMA destination address. Please set this value when channel6 is disabled on DMA_ch6_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch6_Link
Channel6 Linked ListItem Register
0x1C8
32
read-write
n
0x0
0x0
LLI
Set start address of next transfer information. Please set a value of 0xFFFFFFF0 or less. When 0 is set, DMA channel will be disabled after the current DMA transfer completes. Set this register to use scatter/gather function. Scatter/gather is a function to execute DMA repeatedly according to informations which are pre-set on RAM. This address shall be 4-Byte aligned.
0
32
read-write
DMA_ch6_Source
Channel6 Source Address Register
0x1C0
32
read-write
n
0x0
0x0
SrcAddr
Set DMA source address. Please set this value when channel6 is disabled on DMA_ch6_Config register. Do not update this value while data are transferred by DMA. This address shall be 4-Byte aligned.
0
32
read-write
DMA_Config_req
Configuration Register
0x30
32
read-write
n
0x0
0x0
E
Control DMA circuit. 0: Halt. 1: Active. Set 1 to read/write DMAC registers.
0
1
read-write
DMA_Enable_ch
Enabled Channel Register
0x1C
32
read-only
n
0x0
0x0
EnabledChannel0
Enable/Disable DMAC ch0. 0: Disable. 1: Enable
0
1
read-only
EnabledChannel1
Enable/Disable DMAC ch1. 0: Disable. 1: Enable
1
2
read-only
EnabledChannel2
Enable/Disable DMAC ch2. 0: Disable. 1: Enable
2
3
read-only
EnabledChannel3
Enable/Disable DMAC ch3. 0: Disable. 1: Enable
3
4
read-only
EnabledChannel4
Enable/Disable DMAC ch4. 0: Disable. 1: Enable
4
5
read-only
EnabledChannel5
Enable/Disable DMAC ch5. 0: Disable. 1: Enable
5
6
read-only
EnabledChannel6
Enable/Disable DMAC ch6. 0: Disable. 1: Enable
6
7
read-only
DMA_Int_Err_Clr
Interrupt Error Clear Register
0x10
32
read-write
n
0x0
0x0
IntErrClr0
Clear DMAC ch0 DMA error interrupt. 0: Invalid. 1: Clear
0
1
read-write
IntErrClr1
Clear DMAC ch1 DMA error interrupt. 0: Invalid. 1: Clear
1
2
read-write
IntErrClr2
Clear DMAC ch2 DMA error interrupt. 0: Invalid. 1: Clear
2
3
read-write
IntErrClr3
Clear DMAC ch3 DMA error interrupt. 0: Invalid. 1: Clear
3
4
read-write
IntErrClr4
Clear DMAC ch4 DMA error interrupt. 0: Invalid. 1: Clear
4
5
read-write
IntErrClr5
Clear DMAC ch5 DMA error interrupt. 0: Invalid. 1: Clear
5
6
read-write
IntErrClr6
Clear DMAC ch6 DMA error interrupt. 0: Invalid. 1: Clear
6
7
read-write
DMA_Int_Err_Stat
Interrupt Error Status Register
0xC
32
read-only
n
0x0
0x0
IntErrStatus0
DMAC ch0 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
0
1
read-only
IntErrStatus1
DMAC ch1 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
1
2
read-only
IntErrStatus2
DMAC ch2 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
2
3
read-only
IntErrStatus3
DMAC ch3 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
3
4
read-only
IntErrStatus4
DMAC ch4 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
4
5
read-only
IntErrStatus5
DMAC ch5 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
5
6
read-only
IntErrStatus6
DMAC ch6 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
6
7
read-only
DMA_Int_Stat
Interrupt Status Register
0x0
32
read-only
n
0x0
0x0
IntStatus0
DMAC ch0 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
0
1
read-only
IntStatus1
DMAC ch1 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
1
2
read-only
IntStatus2
DMAC ch2 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
2
3
read-only
IntStatus3
DMAC ch3 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
3
4
read-only
IntStatus4
DMAC ch4 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
4
5
read-only
IntStatus5
DMAC ch5 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
5
6
read-only
IntStatus6
DMAC ch6 interrupt status. 0: No interrupt. 1: Interrupt asserted. Both DMA error and DMA done assert this bit.
6
7
read-only
DMA_Int_TemCo_Clr
Interrupt Terminal Count Clear Register
0x8
32
read-write
n
0x0
0x0
IntTCClear0
Clear DMAC ch0 DMA done interrupt. 0: Invalid. 1: Clear
0
1
read-only
IntTCClear1
Clear DMAC ch1 DMA done interrupt. 0: Invalid. 1: Clear
1
2
read-only
IntTCClear2
Clear DMAC ch2 DMA done interrupt. 0: Invalid. 1: Clear
2
3
read-only
IntTCClear3
Clear DMAC ch3 DMA done interrupt. 0: Invalid. 1: Clear
3
4
read-only
IntTCClear4
Clear DMAC ch4 DMA done interrupt. 0: Invalid. 1: Clear
4
5
read-only
IntTCClear5
Clear DMAC ch5 DMA done interrupt. 0: Invalid. 1: Clear
5
6
read-only
IntTCClear6
Clear DMAC ch6 DMA done interrupt. 0: Invalid. 1: Clear
6
7
read-only
DMA_Int_TemCo_Stat
Interrupt Terminal Count Status Register
0x4
32
read-only
n
0x0
0x0
IntTCStatus0
DMAC ch0 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
0
1
read-only
IntTCStatus1
DMAC ch1 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
1
2
read-only
IntTCStatus2
DMAC ch2 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
2
3
read-only
IntTCStatus3
DMAC ch3 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
3
4
read-only
IntTCStatus4
DMAC ch4 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
4
5
read-only
IntTCStatus5
DMAC ch5 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
5
6
read-only
IntTCStatus6
DMAC ch6 interrupt status of DMA done. 0: No interrupt. 1: Interrupt asserted.
6
7
read-only
DMA_RawInt_Err_Stat
Raw Interrupt Error Status Register
0x18
32
read-only
n
0x0
0x0
RawIntErrStatus0
Unmasked DMAC ch0 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
0
1
read-only
RawIntErrStatus1
Unmasked DMAC ch1 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
1
2
read-only
RawIntErrStatus2
Unmasked DMAC ch2 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
2
3
read-only
RawIntErrStatus3
Unmasked DMAC ch3 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
3
4
read-only
RawIntErrStatus4
Unmasked DMAC ch4 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
4
5
read-only
RawIntErrStatus5
Unmasked DMAC ch5 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
5
6
read-only
RawIntErrStatus6
Unmasked DMAC ch6 DMA error interrupt status. 0: No interrupt. 1: Interrupt asserted
6
7
read-only
DMA_RawInt_Tem_Stat
Raw Interrupt Terminal Count Status Register
0x14
32
read-only
n
0x0
0x0
RawIntTCStatus0
Unmasked DMAC ch0 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
0
1
read-only
RawIntTCStatus1
Unmasked DMAC ch1 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
1
2
read-only
RawIntTCStatus2
Unmasked DMAC ch2 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
2
3
read-only
RawIntTCStatus3
Unmasked DMAC ch3 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
3
4
read-only
RawIntTCStatus4
Unmasked DMAC ch4 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
4
5
read-only
RawIntTCStatus5
Unmasked DMAC ch5 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
5
6
read-only
RawIntTCStatus6
Unmasked DMAC ch6 DMA done interrupt status. 0: No interrupt. 1: Interrupt asserted
6
7
read-only
DMA_Soft_burst_req
Software Burtst Request Register
0x20
32
read-write
n
0x0
0x0
SoftBReq0
Set DMA burst request for peripheral number 0. 0: Invalid request. 1: Occur request
0
1
read-write
SoftBReq10
Set DMA burst request for peripheral number 10. 0: Invalid request. 1: Occur request
10
11
read-write
SoftBReq2
Set DMA burst request for peripheral number 2. 0: Invalid request. 1: Occur request
2
3
read-write
SoftBReq4
Set DMA burst request for peripheral number 4. 0: Invalid request. 1: Occur request
4
5
read-write
SoftBReq6
Set DMA burst request for peripheral number 6. 0: Invalid request. 1: Occur request
6
7
read-write
SoftBReq8
Set DMA burst request for peripheral number 8. 0: Invalid request. 1: Occur request
8
9
read-write
DMA_Soft_single_req
Software Single Request Register
0x24
32
read-write
n
0x0
0x0
SoftSReq1
Set DMA single request for peripheral number 1. 0: Invalid request. 1: Occur request
1
2
read-write
SoftSReq11
Set DMA single request for peripheral number 11. 0: Invalid request. 1: Occur request
11
12
read-write
SoftSReq12
Set DMA single request for peripheral number 12. 0: Invalid request. 1: Occur request
12
13
read-write
SoftSReq3
Set DMA single request for peripheral number 3. 0: Invalid request. 1: Occur request
3
4
read-write
SoftSReq5
Set DMA single request for peripheral number 5. 0: Invalid request. 1: Occur request
5
6
read-write
SoftSReq7
Set DMA single request for peripheral number 7. 0: Invalid request. 1: Occur request
7
8
read-write
SoftSReq9
Set DMA single request for peripheral number 9. 0: Invalid request. 1: Occur request
9
10
read-write
GPADC
General Purpose ADC registers
GPADC
0x0
0x0
0x20
registers
n
GPADCC_BUSYMASK
GPADC Busy signal mask setting
0x18
32
read-write
n
0x0
0x0
BusyMask
Busy Mask
0
1
read-write
GPADCC_CTRL
GPADC control
0x0
32
read-write
n
0x0
0x0
ClkAuto
Automatic clock supply On/Off
4
5
read-write
ClkOn
Clock On/Off
5
6
read-write
Cont
GPADC characteristic register
6
14
read-write
CoreOn
CoreOn signal select
2
3
read-write
DMAEN
DMA Enable/Disable
16
17
read-write
MODE
Single/Continuous ADC select
17
18
read-write
Pd
Power Down signal select
3
4
read-write
Reset
Reset Signal select
1
2
read-write
Soc
SOC output
0
1
read-write
TimerSoc
Periodic ADC feature
20
21
read-write
GPADCC_DATA
ADC Conversion Data Read register
0x8
32
read-write
n
0x0
0x0
G_D
G_D
0
12
read-write
GPADCC_INTCLR
GPADC Interrupt clear register
0x10
32
read-write
n
0x0
0x0
IntClr
Clear Interrupt
0
1
read-write
GPADCC_INTMASK
GPADC interrupt mask
0xC
32
read-write
n
0x0
0x0
IntMask
Interrupt mask
0
1
read-write
GPADCC_SELAIN
Select ADC input channel
0x4
32
read-write
n
0x0
0x0
SelAin
Analog input channel select
0
4
read-write
GPADCC_STATE
GPADC state register
0x14
32
read-write
n
0x0
0x0
G_EOC
End of Conversion
1
2
read-write
Int
Interrupt
0
1
read-write
GPIO
General Purpose Input/Output
GPIO
0x0
0x0
0x500
registers
n
CFG0
GPIO0 config
0x300
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO0 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullDownOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
CFG1
GPIO1 config
0x304
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO1 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG10
GPIO10 config
0x328
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO10 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG11
GPIO11 config
0x32C
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO11 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG12
GPIO12 config
0x330
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO12 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG13
GPIO13 config
0x334
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO13 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG14
GPIO14 config
0x338
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO14 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG15
GPIO15 config
0x33C
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO15 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG16
GPIO16 config
0x340
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO16 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG17
GPIO17 config
0x344
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO17 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG2
GPIO2 config
0x308
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO2 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG3
GPIO3 config
0x30C
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO3 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG4
GPIO4 config
0x310
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO4 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG5
GPIO5 config
0x314
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO5 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG6
GPIO6 config
0x318
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO6 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG7
GPIO7 config
0x31C
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO7 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG8
GPIO8 config
0x320
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO8 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
CFG9
GPIO9 config
0x324
32
read-write
n
0x0
0x0
GPIODrvCtrl
GPIO9 drive control. To set GPIO drive settings. 00: 1 mA. 01: 1.5 mA (default). 10: 2 mA. 11: 4 mA. Valid when the GPIO is set as output regardless of GPIOMuxCfg.
5
7
read-write
GPIOIntCfg
GPIO interrupt configuration (initial 00, R/W). Sets the polarity to use the GPIO as an external interrupt. 000: prohibit the interrupt. 001: detect rising edge. 010: detect falling edge. 011: detect both edges. 100: detect high level. 101: detect low level
0
3
read-write
GPIOPullUpOff
GPIO pull-up resister off. Turn on/off the internal pull up resiter. 1: Internal pull-up off. 0: Internal pull-up on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
4
5
read-write
GppPullUpOff
GPIO pull-down resister off. Turn on/off the internal pull down resiter. 1: Internal pull-down off. 0: Internal pull-down on. When both GPIOPullDownOff = 0 and GPIOPullUpOff = 0 are to be set, the chip forces GPIOPullDownOff = 1 and GPIOPullUpOff = 0. Valid when the GPIO is set as input regardless of the GppMuxCfg.
3
4
read-write
EDGECAPCLR
GPIO edge interrupt capture clear
0x488
32
read-write
n
0x0
0x0
GPIO0EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
0
1
read-write
GPIO10EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
10
11
read-write
GPIO11EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
11
12
read-write
GPIO12EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
12
13
read-write
GPIO13EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
13
14
read-write
GPIO14EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
14
15
read-write
GPIO15EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
15
16
read-write
GPIO16EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
16
17
read-write
GPIO17EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
17
18
read-write
GPIO1EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
1
2
read-write
GPIO2EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
2
3
read-write
GPIO3EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
3
4
read-write
GPIO4EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
4
5
read-write
GPIO5EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
5
6
read-write
GPIO6EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
6
7
read-write
GPIO7EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
7
8
read-write
GPIO8EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
8
9
read-write
GPIO9EdgeCapClr
Clear edge interrput capture on the GPIO. 1: Clear. 0: Not clear
9
10
read-write
GPIOMON0
GPIO0 input monitor
0x0
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON1
GPIO1 input monitor
0x4
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON10
GPIO10 input monitor
0x28
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON11
GPIO11 input monitor
0x2C
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON12
GPIO12 input monitor
0x30
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON13
GPIO13 input monitor
0x34
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON14
GPIO14 input monitor
0x38
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON15
GPIO15 input monitor
0x3C
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON16
GPIO16 input monitor
0x40
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON17
GPIO17 input monitor
0x44
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON2
GPIO2 input monitor
0x8
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON3
GPIO3 input monitor
0xC
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON4
GPIO4 input monitor
0x10
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON5
GPIO5 input monitor
0x14
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON6
GPIO6 input monitor
0x18
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON7
GPIO7 input monitor
0x1C
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON8
GPIO8 input monitor
0x20
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
GPIOMON9
GPIO9 input monitor
0x24
32
read-only
n
0x0
0x0
GPIOMon
GPIO input monitor data. Monitors the input of GPIO. 1: High input. 0: Low input. Not dependent on the GppOutEn or hte GppMuxCfg.
0
1
INT
GPIO interrupt read
0x480
32
read-only
n
0x0
0x0
GPIOINT0
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
0
1
read-only
GPIOINT1
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
1
2
read-only
GPIOINT10
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
10
11
read-only
GPIOINT11
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
11
12
read-only
GPIOINT12
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
12
13
read-only
GPIOINT13
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
13
14
read-only
GPIOINT14
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
14
15
read-only
GPIOINT15
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
15
16
read-only
GPIOINT16
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
16
17
read-only
GPIOINT17
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
17
18
read-only
GPIOINT2
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
2
3
read-only
GPIOINT3
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
3
4
read-only
GPIOINT4
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
4
5
read-only
GPIOINT5
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
5
6
read-only
GPIOINT6
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
6
7
read-only
GPIOINT7
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
7
8
read-only
GPIOINT8
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
8
9
read-only
GPIOINT9
Read interrupt on the GPIO. 1: Interrupted. 0: Not interrupted
9
10
read-only
MON_WRAP
GPIO Input Monitor Wrap Register
0x4C0
32
read-only
n
0x0
0x0
GPIO0Mon
GPIO0 input monitor data. Monitors the input of GPIO0. 1: High input. 0: Low input
0
1
read-only
GPIO10Mon
GPIO10 input monitor data. Monitors the input of GPIO10. 1: High input. 0: Low input
10
11
read-only
GPIO11Mon
GPIO11 input monitor data. Monitors the input of GPIO11. 1: High input. 0: Low input
11
12
read-only
GPIO12Mon
GPIO12 input monitor data. Monitors the input of GPIO12. 1: High input. 0: Low input
12
13
read-only
GPIO13Mon
GPIO13 input monitor data. Monitors the input of GPIO13. 1: High input. 0: Low input
13
14
read-only
GPIO14Mon
GPIO14 input monitor data. Monitors the input of GPIO14. 1: High input. 0: Low input
14
15
read-only
GPIO15Mon
GPIO15 input monitor data. Monitors the input of GPIO15. 1: High input. 0: Low input
15
16
read-only
GPIO16Mon
GPIO16 input monitor data. Monitors the input of GPIO16. 1: High input. 0: Low input
16
17
read-only
GPIO17Mon
GPIO17 input monitor data. Monitors the input of GPIO17. 1: High input. 0: Low input
17
18
read-only
GPIO1Mon
GPIO1 input monitor data. Monitors the input of GPIO1. 1: High input. 0: Low input
1
2
read-only
GPIO2Mon
GPIO2 input monitor data. Monitors the input of GPIO2. 1: High input. 0: Low input
2
3
read-only
GPIO3Mon
GPIO3 input monitor data. Monitors the input of GPIO3. 1: High input. 0: Low input
3
4
read-only
GPIO4Mon
GPIO4 input monitor data. Monitors the input of GPIO4. 1: High input. 0: Low input
4
5
read-only
GPIO5Mon
GPIO5 input monitor data. Monitors the input of GPIO5. 1: High input. 0: Low input
5
6
read-only
GPIO6Mon
GPIO6 input monitor data. Monitors the input of GPIO6. 1: High input. 0: Low input
6
7
read-only
GPIO7Mon
GPIO7 input monitor data. Monitors the input of GPIO7. 1: High input. 0: Low input
7
8
read-only
GPIO8Mon
GPIO8 input monitor data. Monitors the input of GPIO8. 1: High input. 0: Low input
8
9
read-only
GPIO9Mon
GPIO9 input monitor data. Monitors the input of GPIO9. 1: High input. 0: Low input
9
10
read-only
MUXCFG_H
GPIO multiplexer config H
0x408
32
read-write
n
0x0
0x0
GPI9OMuxH
Bit 2 of GPIO multiplexer configuration.
9
10
read-write
GPIO0MuxH
Bit 2 of GPIO multiplexer configuration.
0
1
read-write
GPIO10MuxH
Bit 2 of GPIO multiplexer configuration.
10
11
read-write
GPIO11MuxH
Bit 2 of GPIO multiplexer configuration.
11
12
read-write
GPIO12MuxH
Bit 2 of GPIO multiplexer configuration.
12
13
read-write
GPIO13MuxH
Bit 2 of GPIO multiplexer configuration.
13
14
read-write
GPIO14MuxH
Bit 2 of GPIO multiplexer configuration.
14
15
read-write
GPIO15MuxH
Bit 2 of GPIO multiplexer configuration.
15
16
read-write
GPIO16MuxH
Bit 2 of GPIO multiplexer configuration.
16
17
read-write
GPIO17MuxH
Bit 2 of GPIO multiplexer configuration.
17
18
read-write
GPIO1MuxH
Bit 2 of GPIO multiplexer configuration.
1
2
read-write
GPIO2MuxH
Bit 2 of GPIO multiplexer configuration.
2
3
read-write
GPIO3MuxH
Bit 2 of GPIO multiplexer configuration.
3
4
read-write
GPIO4MuxH
Bit 2 of GPIO multiplexer configuration.
4
5
read-write
GPIO5MuxH
Bit 2 of GPIO multiplexer configuration.
5
6
read-write
GPIO6MuxH
Bit 2 of GPIO multiplexer configuration.
6
7
read-write
GPIO7MuxH
Bit 2 of GPIO multiplexer configuration.
7
8
read-write
GPIO8MuxH
Bit 2 of GPIO multiplexer configuration.
8
9
read-write
MUXCFG_L
GPIO multiplexer config L
0x400
32
read-write
n
0x0
0x0
GPI9OMuxL
Bit 0 of GPIO multiplexer configuration.
9
10
read-write
GPIO0MuxL
Bit 0 of GPIO multiplexer configuration.
0
1
read-write
GPIO10MuxL
Bit 0 of GPIO multiplexer configuration.
10
11
read-write
GPIO11MuxL
Bit 0 of GPIO multiplexer configuration.
11
12
read-write
GPIO12MuxL
Bit 0 of GPIO multiplexer configuration.
12
13
read-write
GPIO13MuxL
Bit 0 of GPIO multiplexer configuration.
13
14
read-write
GPIO14MuxL
Bit 0 of GPIO multiplexer configuration.
14
15
read-write
GPIO15MuxL
Bit 0 of GPIO multiplexer configuration.
15
16
read-write
GPIO16MuxL
Bit 0 of GPIO multiplexer configuration.
16
17
read-write
GPIO17MuxL
Bit 0 of GPIO multiplexer configuration.
17
18
read-write
GPIO1MuxL
Bit 0 of GPIO multiplexer configuration.
1
2
read-write
GPIO2MuxL
Bit 0 of GPIO multiplexer configuration.
2
3
read-write
GPIO3MuxL
Bit 0 of GPIO multiplexer configuration.
3
4
read-write
GPIO4MuxL
Bit 0 of GPIO multiplexer configuration.
4
5
read-write
GPIO5MuxL
Bit 0 of GPIO multiplexer configuration.
5
6
read-write
GPIO6MuxL
Bit 0 of GPIO multiplexer configuration.
6
7
read-write
GPIO7MuxL
Bit 0 of GPIO multiplexer configuration.
7
8
read-write
GPIO8MuxL
Bit 0 of GPIO multiplexer configuration.
8
9
read-write
MUXCFG_M
GPIO multiplexer config M
0x404
32
read-write
n
0x0
0x0
GPI9OMuxM
Bit 1 of GPIO multiplexer configuration.
9
10
read-write
GPIO0MuxM
Bit 1 of GPIO multiplexer configuration.
0
1
read-write
GPIO10MuxM
Bit 1 of GPIO multiplexer configuration.
10
11
read-write
GPIO11MuxM
Bit 1 of GPIO multiplexer configuration.
11
12
read-write
GPIO12MuxM
Bit 1 of GPIO multiplexer configuration.
12
13
read-write
GPIO13MuxM
Bit 1 of GPIO multiplexer configuration.
13
14
read-write
GPIO14MuxM
Bit 1 of GPIO multiplexer configuration.
14
15
read-write
GPIO15MuxM
Bit 1 of GPIO multiplexer configuration.
15
16
read-write
GPIO16MuxM
Bit 1 of GPIO multiplexer configuration.
16
17
read-write
GPIO17MuxM
Bit 1 of GPIO multiplexer configuration.
17
18
read-write
GPIO1MuxM
Bit 1 of GPIO multiplexer configuration.
1
2
read-write
GPIO2MuxM
Bit 1 of GPIO multiplexer configuration.
2
3
read-write
GPIO3MuxM
Bit 1 of GPIO multiplexer configuration.
3
4
read-write
GPIO4MuxM
Bit 1 of GPIO multiplexer configuration.
4
5
read-write
GPIO5MuxM
Bit 1 of GPIO multiplexer configuration.
5
6
read-write
GPIO6MuxM
Bit 1 of GPIO multiplexer configuration.
6
7
read-write
GPIO7MuxM
Bit 1 of GPIO multiplexer configuration.
7
8
read-write
GPIO8MuxM
Bit 1 of GPIO multiplexer configuration.
8
9
read-write
OBSMUXCFG
GPIO Observation function selection register
0x490
32
read-write
n
0x0
0x0
ObsMuxCfg
Always set 3.
0
4
read-write
OUT0
GPIO0 output data
0x100
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX.. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT1
GPIO1 output data
0x104
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT10
GPIO10 output data
0x128
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT11
GPIO11 output data
0x12C
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT12
GPIO12 output data
0x130
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT13
GPIO13 output data
0x134
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT14
GPIO14 output data
0x138
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT15
GPIO15 output data
0x13C
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT16
GPIO16 output data
0x140
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT17
GPIO17 output data
0x144
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT2
GPIO2 output data
0x108
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT3
GPIO3 output data
0x10C
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT4
GPIO4 output data
0x110
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT5
GPIO5 output data
0x114
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT6
GPIO6 output data
0x118
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT7
GPIO7 output data
0x11C
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT8
GPIO8 output data
0x120
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT9
GPIO9 output data
0x124
32
read-write
n
0x0
0x0
GPIOOut
GPIO output data Set the output level of the GPIOX. 1: High output. 0: Low output. The value is output only when GPIOOutEnX = 1 and GPIOMuxCfgX = 0.
0
1
read-write
OUT_EN0
GPIO0 output enable
0x200
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN1
GPIO1 output enable
0x204
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN10
GPIO10 output enable
0x228
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN11
GPIO11 output enable
0x22C
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN12
GPIO12 output enable
0x230
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN13
GPIO13 output enable
0x234
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN14
GPIO14 output enable
0x238
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN15
GPIO15 output enable
0x23C
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN16
GPIO16 output enable
0x240
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN17
GPIO17 output enable
0x244
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN2
GPIO2 output enable
0x208
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN3
GPIO3 output enable
0x20C
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN4
GPIO4 output enable
0x210
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN5
GPIO5 output enable
0x214
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN6
GPIO6 output enable
0x218
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN7
GPIO7 output enable
0x21C
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN8
GPIO8 output enable
0x220
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN9
GPIO9 output enable
0x224
32
read-write
n
0x0
0x0
GPIOOutEn
GPIO output enable. Enables GPIO output. 1: output enable. 0: output disable
0
1
read-write
OUT_EN_WRAP
GPIO Output Enable Wrap Register
0x4C8
32
read-write
n
0x0
0x0
GPIOOutEn0
GPIO0 output enable. Enables GPIO0 output. 1: Output enable. 0: Output disable
0
1
read-write
GPIOOutEn1
GPIO1 output enable. Enables GPIO1 output. 1: Output enable. 0: Output disable
1
2
read-write
GPIOOutEn10
GPIO10 output enable. Enables GPIO10 output. 1: Output enable. 0: Output disable
10
11
read-write
GPIOOutEn11
GPIO11 output enable. Enables GPIO11 output. 1: Output enable. 0: Output disable
11
12
read-write
GPIOOutEn12
GPIO12 output enable. Enables GPIO12 output. 1: Output enable. 0: Output disable
12
13
read-write
GPIOOutEn13
GPIO13 output enable. Enables GPIO13 output. 1: Output enable. 0: Output disable
13
14
read-write
GPIOOutEn14
GPIO14 output enable. Enables GPIO14 output. 1: Output enable. 0: Output disable
14
15
read-write
GPIOOutEn15
GPIO15 output enable. Enables GPIO15 output. 1: Output enable. 0: Output disable
15
16
read-write
GPIOOutEn16
GPIO16 output enable. Enables GPIO16 output. 1: Output enable. 0: Output disable
16
17
read-write
GPIOOutEn17
GPIO17 output enable. Enables GPIO17 output. 1: Output enable. 0: Output disable
17
18
read-write
GPIOOutEn2
GPIO2 output enable. Enables GPIO2 output. 1: Output enable. 0: Output disable
2
3
read-write
GPIOOutEn3
GPIO3 output enable. Enables GPIO3 output. 1: Output enable. 0: Output disable
3
4
read-write
GPIOOutEn4
GPIO4 output enable. Enables GPIO4 output. 1: Output enable. 0: Output disable
4
5
read-write
GPIOOutEn5
GPIO5 output enable. Enables GPIO5 output. 1: Output enable. 0: Output disable
5
6
read-write
GPIOOutEn6
GPIO6 output enable. Enables GPIO6 output. 1: Output enable. 0: Output disable
6
7
read-write
GPIOOutEn7
GPIO7 output enable. Enables GPIO7 output. 1: Output enable. 0: Output disable
7
8
read-write
GPIOOutEn8
GPIO8 output enable. Enables GPIO8 output. 1: Output enable. 0: Output disable
8
9
read-write
GPIOOutEn9
GPIO9 output enable. Enables GPIO9 output. 1: Output enable. 0: Output disable
9
10
read-write
OUT_WRAP
GPIO Output data Wrap Register
0x4C4
32
read-write
n
0x0
0x0
GPIO0Out
GPIO0 output data. Set the output level of GPIO0. 1: High output. 0: Low output
0
1
read-write
GPIO10Out
GPIO10 output data. Set the output level of GPIO10. 1: High output. 0: Low output
10
11
read-write
GPIO11Out
GPIO11 output data. Set the output level of GPIO11. 1: High output. 0: Low output
11
12
read-write
GPIO12Out
GPIO12 output data. Set the output level of GPIO12. 1: High output. 0: Low output
12
13
read-write
GPIO13Out
GPIO13 output data. Set the output level of GPIO13. 1: High output. 0: Low output
13
14
read-write
GPIO14Out
GPIO14 output data. Set the output level of GPIO14. 1: High output. 0: Low output
14
15
read-write
GPIO15Out
GPIO15 output data. Set the output level of GPIO15. 1: High output. 0: Low output
15
16
read-write
GPIO16Out
GPIO16 output data. Set the output level of GPIO16. 1: High output. 0: Low output
16
17
read-write
GPIO17Out
GPIO17 output data. Set the output level of GPIO17. 1: High output. 0: Low output
17
18
read-write
GPIO1Out
GPIO1 output data. Set the output level of GPIO1. 1: High output. 0: Low output
1
2
read-write
GPIO2Out
GPIO2 output data. Set the output level of GPIO2. 1: High output. 0: Low output
2
3
read-write
GPIO3Out
GPIO3 output data. Set the output level of GPIO3. 1: High output. 0: Low output
3
4
read-write
GPIO4Out
GPIO4 output data. Set the output level of GPIO4. 1: High output. 0: Low output
4
5
read-write
GPIO5Out
GPIO5 output data. Set the output level of GPIO5. 1: High output. 0: Low output
5
6
read-write
GPIO6Out
GPIO6 output data. Set the output level of GPIO6. 1: High output. 0: Low output
6
7
read-write
GPIO7Out
GPIO7 output data. Set the output level of GPIO7. 1: High output. 0: Low output
7
8
read-write
GPIO8Out
GPIO8 output data. Set the output level of GPIO8. 1: High output. 0: Low output
8
9
read-write
GPIO9Out
GPIO9 output data. Set the output level of GPIO9. 1: High output. 0: Low output
9
10
read-write
I2C1
I2C1
I2C1
0x0
0x0
0x30
registers
n
I2C_AR
I2C Bus address register
0x8
32
read-write
n
0x0
0x0
ALS
Address cognition mode
0
1
read-write
SA
Slave address
1
8
read-write
I2C_AR2
I2C Bus address register
0x28
32
read-write
n
0x0
0x0
SA2
Slave Addres config 2
1
8
read-write
SA2EN
2nd Slave address enable/disable
0
1
read-write
I2C_CR1
I2C Control
0x0
32
read-write
n
0x0
0x0
ACK
Clock for Ack select
4
5
read-write
BC
Transfer bit setting
5
8
read-write
NOACK
Slave address check and general call check
3
4
read-write
SCK
Serial Clock Frequency select
0
3
read-write
I2C_CR2
I2C Control register 2
0xC
32
read-write
n
0x0
0x0
BB
Start/Stop condition
5
6
read-write
I2CM
I2C control
3
4
read-write
MST
Master / Slave select
7
8
read-write
PIN
Internal Interrupt reset
4
5
read-write
SWRST
Software Reset
0
2
read-write
TRX
Tx/Rx select
6
7
read-write
I2C_DBR
Tx Data or Rx Data register
0x4
32
read-write
n
0x0
0x0
DB
Read / Write Data
0
8
read-write
I2C_IE
I2C Interrut enable register
0x18
32
read-write
n
0x0
0x0
DMARI2CRX
DMA Request Tx enable/disable
4
5
read-write
ININACK
NACK interrupt enable/disable
3
4
read-write
INTI2C
I2C enable/disable
0
1
read-write
INTI2CAL
Arbitration lost interrupt enable/disable
1
2
read-write
INTI2CBF
Bus free interrupt enable/disable
2
3
read-write
MARI2CTX
DMA Request Rx enable/disable
5
6
read-write
SELPINCD
PIN release condition select
6
7
read-write
I2C_OP
I2C extended feature register
0x20
32
read-write
n
0x0
0x0
DISAL
Arbitration lost disable
7
8
read-write
GCDI
General Call enable/disable
2
3
read-write
MFACK
Mask ACK output
0
1
read-write
NFSEL
Select NF
4
5
read-write
RSTA
Restart Flag
3
4
read-write
SA2ST
Receive Slave address 2 check
6
7
read-write
SAST
Receive Slave address check
5
6
read-write
SREN
Restart request
1
2
read-write
I2C_PM
I2C Bus monitor
0x24
32
read-write
n
0x0
0x0
MSTCMOSEN
Master/Slave select in CMOS mode
4
5
read-write
SCL
Monitor SCL pin level
0
1
read-write
SCLCMOSEN
SCL CMOS mode select
2
3
read-write
SDA
Monitor SDA pin level
1
2
read-write
SDACMOSEN
SDA CMOS mode select
3
4
read-write
I2C_PRS
I2C Pre-scaler register
0x14
32
read-write
n
0x0
0x0
PRSCK
Select pre-scaler freqyency for serial clock
0
5
read-write
I2C_SR
I2C Status register
0x10
32
read-write
n
0x0
0x0
AAS
Slave Address Correspondence monitor
2
3
read-write
ADO
General Call monitor
1
2
read-write
AL
Arbitration Lost monitor
3
4
read-write
BB
Bus Busy monitor
5
6
read-write
LRB
Last Bit Receive monitor
0
1
read-write
MST
Master/Slave monitor
7
8
read-write
PIN
Interrupt status monitor
4
5
read-write
TRX
Tx/Rx monitor
6
7
read-write
I2C_ST
I2C Status register
0x1C
32
read-write
n
0x0
0x0
I2C
INTI2C status
0
1
read-write
I2CAL
INTI2CAL status
1
2
read-write
I2CBF
INTI2CBF status
2
3
read-write
NOACK
NOACK status
3
4
read-write
I2C2
I2C1
I2C2
0x0
0x0
0x30
registers
n
I2CPM
I2C Bus monitor
0x24
32
read-write
n
0x0
0x0
MSTCMOSEN
Master/Slave select in CMOS mode
4
5
read-write
SCL
Monitor SCL pin level
0
1
read-write
SCLCMOSEN
SCL CMOS mode select
2
3
read-write
SDA
Monitor SDA pin level
1
2
read-write
SDACMOSEN
SDA CMOS mode select
3
4
read-write
I2C_AR
I2C Bus address register
0x8
32
read-write
n
0x0
0x0
ALS
Address cognition mode
0
1
read-write
SA
Slave address
1
8
read-write
I2C_AR2
I2C Bus address register
0x28
32
read-write
n
0x0
0x0
SA2
Slave Addres config 2
1
8
read-write
SA2EN
2nd Slave address enable/disable
0
1
read-write
I2C_CR1
I2C Control
0x0
32
read-write
n
0x0
0x0
ACK
Clock for Ack select
4
5
read-write
BC
Transfer bit setting
5
8
read-write
NOACK
Slave address check and general call check
3
4
read-write
SCK
Serial Clock Frequency select
0
3
read-write
I2C_CR2
I2C Control register 2
0xC
32
read-write
n
0x0
0x0
BB
Start/Stop condition
5
6
read-write
I2CM
I2C control
3
4
read-write
MST
Master / Slave select
7
8
read-write
PIN
Internal Interrupt reset
4
5
read-write
SWRST
Software Reset
0
2
read-write
TRX
Tx/Rx select
6
7
read-write
I2C_DBR
Tx Data or Rx Data register
0x4
32
read-write
n
0x0
0x0
DB
Read / Write Data
0
8
read-write
I2C_IE
I2C Interrut enable register
0x18
32
read-write
n
0x0
0x0
DMARI2CRX
DMA Request Tx enable/disable
4
5
read-write
DMARI2CTX
DMA Request Rx enable/disable
5
6
read-write
ININACK
NACK interrupt enable/disable
3
4
read-write
INTI2C
I2C enable/disable
0
1
read-write
INTI2CAL
Arbitration lost interrupt enable/disable
1
2
read-write
INTI2CBF
Bus free interrupt enable/disable
2
3
read-write
SELPINCD
PIN release condition select
6
7
read-write
I2C_OP
I2C extended feature register
0x20
32
read-write
n
0x0
0x0
DISAL
Arbitration lost disable
7
8
read-write
GCDI
General Call enable/disable
2
3
read-write
MFACK
Mask ACK output
0
1
read-write
NFSEL
Select NF
4
5
read-write
RSTA
Restart Flag
3
4
read-write
SA2ST
Receive Slave address 2 check
6
7
read-write
SAST
Receive Slave address check
5
6
read-write
SREN
Restart request
1
2
read-write
I2C_SR
I2C Status register
0x10
32
read-write
n
0x0
0x0
AAS
Slave Address Correspondence monitor
2
3
read-write
ADO
General Call monitor
1
2
read-write
AL
Arbitration Lost monitor
3
4
read-write
BB
Bus Busy monitor
5
6
read-write
LRB
Last Bit Receive monitor
0
1
read-write
MST
Master/Slave monitor
7
8
read-write
PIN
Interrupt status monitor
4
5
read-write
TRX
Tx/Rx monitor
6
7
read-write
I2C_ST
I2C Status register
0x1C
32
read-write
n
0x0
0x0
I2C
INTI2C status
0
1
read-write
I2CAL
INTI2CAL status
1
2
read-write
I2CBF
INTI2CBF status
2
3
read-write
NOACK
NOACK status
3
4
read-write
PMU
Power Management Unit
PMU
0x0
0x0
0x200
registers
n
IOSTANDBYX
GPIO input standby
0x78
32
read-write
n
0x0
0x0
GPIO0InputStandbyRelease
Input standby release on GPIO0. 1: Release standby. 0: Standby
0
1
read-write
GPIO10InputStandbyRelease
Input standby release on GPIO10. 1: Release standby. 0: Standby
10
11
read-write
GPIO11InputStandbyRelease
Input standby release on GPIO11. 1: Release standby. 0: Standby
11
12
read-write
GPIO12InputStandbyRelease
Input standby release on GPIO12. 1: Release standby. 0: Standby
12
13
read-write
GPIO13InputStandbyRelease
Input standby release on GPIO13. 1: Release standby. 0: Standby
13
14
read-write
GPIO14InputStandbyRelease
Input standby release on GPIO14. 1: Release standby. 0: Standby
14
15
read-write
GPIO15InputStandbyRelease
Input standby release on GPIO15. 1: Release standby. 0: Standby
15
16
read-write
GPIO16InputStandbyRelease
Input standby release on GPIO16. 1: Release standby. 0: Standby
16
17
read-write
GPIO17InputStandbyRelease
Input standby release on GPIO17. 1: Release standby. 0: Standby
17
18
read-write
GPIO1InputStandbyRelease
Input standby release on GPIO1. 1: Release standby. 0: Standby
1
2
read-write
GPIO2InputStandbyRelease
Input standby release on GPIO2. 1: Release standby. 0: Standby
2
3
read-write
GPIO3InputStandbyRelease
Input standby release on GPIO3. 1: Release standby. 0: Standby
3
4
read-write
GPIO4InputStandbyRelease
Input standby release on GPIO4. 1: Release standby. 0: Standby
4
5
read-write
GPIO5InputStandbyRelease
Input standby release on GPIO5. 1: Release standby. 0: Standby
5
6
read-write
GPIO6InputStandbyRelease
Input standby release on GPIO6. 1: Release standby. 0: Standby
6
7
read-write
GPIO7InputStandbyRelease
Input standby release on GPIO7. 1: Release standby. 0: Standby
7
8
read-write
GPIO8InputStandbyRelease
Input standby release on GPIO8. 1: Release standby. 0: Standby
8
9
read-write
GPIO9InputStandbyRelease
Input standby release on GPIO9. 1: Release standby. 0: Standby
9
10
read-write
OSC32K_TRIMIN
OSC32K trimming register
0x11C
32
read-write
n
0x0
0x0
FREQTUNE_OSC32K
Freqency tune value. (eFuse)
16
21
read-write
Reserved0
Do not change this value
0
16
read-write
RTCWAKEUPCFG
RTC wakeup config register
0x5C
32
read-write
n
0x0
0x0
RTCWAKEUPEN
RTC wakeup config. 1: Enable wakeup by RTC. 0: Disable wakeup by RTC
0
1
read-write
RTC_ADJUST1S
RTC Adjust 1 Sec register
0xCC
32
read-write
n
0x0
0x0
Reserved1
Reserved (Set 0 to all the bits)
0
8
read-write
SCUT
1Hz Short Cut
8
9
read-write
RTC_CNTCFG
RTC count cnofig register
0xD8
32
read-write
n
0x0
0x0
RTCNTCFG
Set RTC config. 1: Enable RTC config. 0: Disable RTC config
0
1
read-write
RTC_DAY
RTC date register
0xB4
32
read-write
n
0x0
0x0
RTCMONTH
RTC date config of month. (Binary Coded Decimal)
16
21
read-write
RTCWEEK
RTC date config of week. (Binary Coded Decimal)
0
3
read-write
RTCYEAR
RTC date config of year. (Binary Coded Decimal)
24
32
read-write
RTC_INTCLR
RTC interrupt clear register
0xD0
32
read-write
n
0x0
0x0
RTCINTclr
Clear RTC interrupt. 1: Clear. 0: Don't care
0
1
read-write
RTC_INTEN
RTC interrupt enable register
0xD4
32
read-write
n
0x0
0x0
RTCINTEN
Enable RTC interrupt. 1: Enable interrupt request. 0: Disable interrupt request
0
1
read-write
RTC_PAGER
RTC control config register
0xB8
32
read-write
n
0x0
0x0
ENAALM
Set alarm config. 0: Disable. 1: Enable
2
3
read-write
ENATMR
Set clock config. 0: Disable. 1: Enable
3
4
read-write
INTENA
Set interrupt config. 0: Disable. 1: Enable
7
8
read-write
PAGE
Set Page config. 0: Choose Page0. 1: Choose Page1
0
1
read-write
RTC_RESTR
RTC reset register
0xBC
32
read-write
n
0x0
0x0
Reserved0
Always set 0b0000_0000_1100_0001_0000_0000_11
6
32
read-write
Reserved1
Do not change the values.
0
4
read-write
RSTALM
Reset alarm. 0: Not reset. 1: Reset. If you wan to reset an alarm, please set 1 to this value and wait to become 0.
4
5
read-write
RSTTMR
Reset clock. 0: Not reset. 1: Reset. If you wan to reset a clock, please set 1 to this value and wait to become 0.
5
6
read-write
RTC_TIME
RTC time register
0xB0
32
read-write
n
0x0
0x0
RTCDAYSET
RTC time config of day. (Binary Coded Decimal). Min=1. Max=31
24
30
read-write
RTCHOURSET
RTC time config of hour. (Binary Coded Decimal). Min: 0. Max: 23
16
22
read-write
RTCMINUTESET
RTC time config of minute. (Binary Coded Decimal). Min: 0. Max: 59
8
15
read-write
RTCSECONDSET
RTC time config of second. (Binary Coded Decimal). Min: 0. Max: 59
0
7
read-write
RTC_TIME2
RTC time register2
0xC4
32
read-write
n
0x0
0x0
RTCDAYSET
RTC time config of day. (Binary Coded Decimal). Min: 1. Max: 31
24
30
read-write
RTCHOURSET
RTC time config of hour. (Binary Coded Decimal). Min: 0. Max: 23
16
22
read-write
RTCMINUTESET
RTC time config of minute. (Binary Coded Decimal). Min: 0. Max: 59
8
15
read-write
SLEEPCLK_HL_STATUS
HL Status of Sleep Clock
0x164
32
read-write
n
0x0
0x0
SLPSLKHLSTATUS
Sleep Clock Status
0
1
read-write
SLEEPCLK_STATUS
Sleep clock status
0x160
32
read-write
n
0x0
0x0
SLPSLKTOGLE
Status toggling 1/2 of Sleep clock
0
1
read-write
XOSC_TRIMIN
XOSC trimming register
0x118
32
read-write
n
0x0
0x0
Reserved0
Do not change this value
11
32
read-write
Reserved1
Do not change this value
0
4
read-write
XO_FREQ_TUNE
Frequency tune value (eFuse)
4
11
read-write
PWM
Pulse Width Modulation
PWM
0x0
0x0
0x500
registers
n
CYCLE_CH0
PWM CH0 cycle set
0x8
32
read-write
n
0x0
0x0
Cycle
Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
0
12
read-write
CYCLE_CH1
PWM CH1 cycle set
0x108
32
read-write
n
0x0
0x0
Cycle
Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
0
12
read-write
CYCLE_CH2
PWM CH2 cycle set
0x208
32
read-write
n
0x0
0x0
Cycle
Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
0
12
read-write
CYCLE_CH3
PWM CH3 cycle set
0x308
32
read-write
n
0x0
0x0
Cycle
Cycle count register determines the PWM output period. 0 to 4095 (0x000 to 0xFFF)
0
12
read-write
DUTY_CH0
PWM CH0 duty set
0xC
32
read-write
n
0x0
0x0
Duty
Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF) duty ratio = (this value)/(cycle + 1)
0
12
read-write
DUTY_CH1
PWM CH1 duty set
0x10C
32
read-write
n
0x0
0x0
Duty
Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF). duty ratio = (this value)/(cycle + 1)
0
12
read-write
DUTY_CH2
PWM CH2 duty set
0x20C
32
read-write
n
0x0
0x0
Duty
Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF). duty ratio = (this value)/(cycle + 1)
0
12
read-write
DUTY_CH3
PWM CH3 duty set
0x30C
32
read-write
n
0x0
0x0
Duty
Determines the duty ratio. 0 to 4095 (0x000 to 0xFFF). duty ratio = (this value)/(cycle + 1)
0
12
read-write
EN_WRAP
PWM wave phase control
0x400
32
read-write
n
0x0
0x0
ch0Wpcyc_en
PWM0 enable
0
1
read-write
ch0Wpunit_en
PWM0 unit_en
1
2
read-write
ch1Wpcyc_en
PWM1 enable
2
3
read-write
ch1Wpunit_en
PWM1 unit_en
3
4
read-write
ch2Wpcyc_en
PWM2 enable
4
5
read-write
ch2Wpunit_en
PWM2 unit_en
5
6
read-write
ch3Wpcyc_en
PWM3 enable
6
7
read-write
ch3Wpunit_en
PWM3 unit_en
7
8
read-write
INTCLR_CH0
PWM CH0 interrupt clear
0x18
32
read-write
n
0x0
0x0
IntClr
PWM interrupt clear register (initial 0, W). Writeing 1 to this register clears the interrupt status.
0
1
read-write
INTCLR_CH1
PWM CH1 interrupt clear
0x118
32
read-write
n
0x0
0x0
IntClr
PWM interrupt clear register (initial 0, W). Writeing 1 to this register clears the interrupt status.
0
1
read-write
INTCLR_CH2
PWM CH2 interrupt clear
0x218
32
read-write
n
0x0
0x0
IntClr
PWM interrupt clear register (initial 0, W). Writeing 1 to this register clears the interrupt status.
0
1
read-write
INTCLR_CH3
PWM CH3 interrupt clear
0x318
32
read-write
n
0x0
0x0
IntClr
PWM interrupt clear register (initial 0, W). Writeing 1 to this register clears the interrupt status.
0
1
read-write
PATTERN_CH0
PWM CH0 output mask set
0x4
32
read-write
n
0x0
0x0
Rhythm_Pat
PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output). 1: Output mask OFF (PWM output). This has no effect when 1-s timer is OFF.
0
20
read-write
PATTERN_CH1
PWM CH1 output mask set
0x104
32
read-write
n
0x0
0x0
Rhythm_Pat
PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output). 1: Output mask OFF (PWM output). This has no effect when 1-s timer is OFF.
0
20
read-write
PATTERN_CH2
PWM CH2 output mask set
0x204
32
read-write
n
0x0
0x0
Rhythm_Pat
PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output). 1: Output mask OFF (PWM output). This has no effect when 1-s timer is OFF.
0
20
read-write
PATTERN_CH3
PWM CH3 output mask set
0x304
32
read-write
n
0x0
0x0
Rhythm_Pat
PWM is output during the time this defines. 1 bit corresponds to 50 ms. 0: Output mask ON (No PWM output). 1: Output mask OFF (PWM output). This has no effect when 1-s timer is OFF.
0
20
read-write
PCTRL_CH0
PWM CH0 enable control
0x0
32
read-write
n
0x0
0x0
ENABLE
PWM channel enable (R/W). 0: Stop (default). 1: Start. Please set cycle and duty before this is set to start.
0
1
read-write
IntMask
PWM interrupt mask (R/W). 0: Interrupt output enabled. 1: Interrupt disabled (default)
3
4
read-write
Pol
PWM output polarity control (R/W). 0: Polarity inversion OFF (default). 1: Polarity inversion ON
2
3
read-write
relLow
Keep the output when entering LowPowerMode
4
5
read-write
unit_en
1-s timer enable (R/W). 0: Timer OFF (default). 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
1
2
read-write
PCTRL_CH1
PWM CH1 enable control
0x100
32
read-write
n
0x0
0x0
ENABLE
PWM channel enable (R/W). 0: Stop (default). 1: Start. Please set cycle and duty before this is set to start.
0
1
read-write
IntMask
PWM interrupt mask (R/W). 0: Interrupt output enabled. 1: Interrupt disabled (default)
3
4
read-write
Pol
PWM output polarity control (R/W). 0: Polarity inversion OFF (default). 1: Polarity inversion ON
2
3
read-write
relLow
Keep the output when entering LowPowerMode
4
5
read-write
unit_en
1-s timer enable (R/W). 0: Timer OFF (default). 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
1
2
read-write
PCTRL_CH2
PWM CH2 enable control
0x200
32
read-write
n
0x0
0x0
ENABLE
PWM channel enable (R/W). 0: Stop (default). 1: Start. Please set cycle and duty before this is set to start.
0
1
read-write
IntMask
PWM interrupt mask (R/W). 0: Interrupt output enabled. 1: Interrupt disabled (default)
3
4
read-write
Pol
PWM output polarity control (R/W). 0: Polarity inversion OFF (default). 1: Polarity inversion ON
2
3
read-write
relLow
Keep the output when entering LowPowerMode
4
5
read-write
unit_en
1-s timer enable (R/W). 0: Timer OFF (default). 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
1
2
read-write
PCTRL_CH3
PWM CH3 enable control
0x300
32
read-write
n
0x0
0x0
ENABLE
PWM channel enable (R/W). 0: Stop (default). 1: Start. Please set cycle and duty before this is set to start.
0
1
read-write
IntMask
PWM interrupt mask (R/W). 0: Interrupt output enabled. 1: Interrupt disabled (default)
3
4
read-write
Pol
PWM output polarity control (R/W). 0: Polarity inversion OFF (default). 1: Polarity inversion ON
2
3
read-write
relLow
Keep the output when entering LowPowerMode
4
5
read-write
unit_en
1-s timer enable (R/W). 0: Timer OFF (default). 1: Timer ON Please set this off before unit_starvalue is to be changed. When this is off, rhythm settings has no effect.
1
2
read-write
STATE_CH0
PWM CH0 status
0x14
32
read-write
n
0x0
0x0
Int_state
INT status. 0: Not interrupted. 1: Interrupted. This is cleared when INTClr bit 0 is set to 1.
0
1
read-write
Pwm_state
Cycle counter status. 0: ON. 1: Idle
1
2
read-write
Timer_state
1-s timer status. 0: ON. 1: Idle
2
3
read-write
STATE_CH1
PWM CH1 status
0x114
32
read-write
n
0x0
0x0
Int_state
INT status. 0: Not interrupted. 1: Interrupted. This is cleared when INTClr bit 0 is set to 1.
0
1
read-write
Pwm_state
Cycle counter status. 0: ON. 1: Idle
1
2
read-write
Timer_state
1-s timer status. 0: ON. 1: Idle
2
3
read-write
STATE_CH2
PWM CH2 status
0x214
32
read-write
n
0x0
0x0
Int_state
INT status. 0: Not interrupted. 1: Interrupted. This is cleared when INTClr bit 0 is set to 1.
0
1
read-write
Pwm_state
Cycle counter status. 0: ON. 1: Idle
1
2
read-write
Timer_state
1-s timer status. 0: ON. 1: Idle
2
3
read-write
STATE_CH3
PWM CH3 status
0x314
32
read-write
n
0x0
0x0
Int_state
INT status. 0: Not interrupted. 1: Interrupted. This is cleared when INTClr bit 0 is set to 1.
0
1
read-write
Pwm_state
Cycle counter status. 0: ON. 1: Idle
1
2
read-write
Timer_state
1-s timer status. 0: ON. 1: Idle
2
3
read-write
UNIT_CH0
PWM CH0 rhythm counter period set
0x10
32
read-write
n
0x0
0x0
Unit_startvalue
Counter value setting to count 50 ms. 0x0665 for 32.768 kHz (default). 0x9EB0F for 13 MHz. Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
0
20
read-write
UNIT_CH1
PWM CH1 rhythm counter period set
0x110
32
read-write
n
0x0
0x0
Unit_startvalue
Counter value setting to count 50 ms. 0x0665 for 32.768 kHz (default). 0x9EB0F for 13 MHz. Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
0
20
read-write
UNIT_CH2
PWM CH2 rhythm counter period set
0x210
32
read-write
n
0x0
0x0
Unit_startvalue
Counter value setting to count 50 ms. 0x0665 for 32.768 kHz (default). 0x9EB0F for 13 MHz. Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
0
20
read-write
UNIT_CH3
PWM CH3 rhythm counter period set
0x310
32
read-write
n
0x0
0x0
Unit_startvalue
Counter value setting to count 50 ms. 0x0665 for 32.768 kHz (default). 0x9EB0F for 13 MHz. Before to change this value, please make sure that PCTRL[1] unit_en = 0, STATE[2] Timer_state = 1, Pwm_state = 1.
0
20
read-write
SPI1
Serial Peripheral Interface(Master/Slave)
SPI1
0x0
0x0
0x30
registers
n
SPI_CONTROL
SPI control
0x0
32
read-write
n
0x0
0x0
SETACT
Set operation mode (R/W). 0: Configuration mode. 1: Active mode (default)
1
2
read-write
SLAVE
Set master/slave mode (R/W). 0: Master mode (default). 1: Slave mode
31
32
read-write
SPCSEN0
Enable CS (R/W). 0: Disable. 1: Enable (default)
8
9
read-write
SPCSPL0
Set CS polarity (R/W). 0: Low active (default). 1: High active
12
13
read-write
SPDIR
Specify LSB/MSB first (R/W). 0: MSB first (default). 1: LSB first
7
8
read-write
SPSCKPH
Specify serial clock phase (R/W). 0: Sampling at the first edge (default). 1: Sampling at the second edge
5
6
read-write
SPSCKPL
Specify serial clock polarity (R/W). 0: Sampling at high (default). 1: Sampling at low
6
7
read-write
SPI_INTCONTROL
SPI intrrupt control
0x10
32
read-write
n
0x0
0x0
INTCPS
Serial Tx Complete interrupt. 0: Disable interrupt. 1: Enable interrupt.
4
5
read-write
INTCRX0
RX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
3
4
read-write
INTCTIM0
Serial Tx Wait timer 0 interrupt. 0: Disable interrupt. 1: Enable interrupt.
5
6
read-write
INTCTIM1
Serial Tx Wait timer1 interrupt. 0: Disable interrupt. 1: Enable interrupt.
6
7
read-write
INTCTX0
TX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
2
3
read-write
INTCTXCOMP
Set Tx complete interrupt. 0: Disable interrupt. 1: Enable interrupt
11
12
read-write
INTCTXCOMPSEL
Tx complete interrupt select bit. Selects the interrupt for bit 10 of interrupt status register. 0: SPI Tx complete status. 1: SPI Tx complete including SPI DMA TX
15
16
read-write
INTCTXUR
Serial Under-run interrupt. 0: Disable interrupt. 1: Enable interrupt.
7
8
read-write
INTRX
RX FIFO interrupt. Asserted when there are datas more than [18:16]. 0: Disable interrupt. 1: Enable interrupt.
1
2
read-write
INTTX
TX FIFO interrupt. Asserted when there are datas more than [10:8]. 0: Disable interrupt. 1: Enable interrupt.
0
1
read-write
RXCLR
Clear RX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
20
21
read-write
RXINUM
Watermark for Rx FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
16
19
read-write
TXCLR
Clear TX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
12
13
read-write
TXINUM
Water mark for TX FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
8
11
read-write
SPI_INTSTATUS
SPI interrupt status
0x14
32
read-write
n
0x0
0x0
INTSRX
Reads Rx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
1
2
read-write
INTSRX0
Reads Rx Fifo Overrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
3
4
read-write
INTSSPS
INTSSPS
4
5
read-write
INTSTIM0
Reads Tx Wait timer0 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
5
6
read-write
INTSTIM1
Reads Tx Wait timer1 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
6
7
read-write
INTSTX
Reads Tx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
0
1
read-write
INTSTX0
Reads Tx Fifo Overrun interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
2
3
read-write
INTSTXUR
Reads Tx Underrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
7
8
read-write
RXEMP
Read the status of RX FIFO (R). 0: RX FIFO is empty. 1: RX FIFO is not empty.
9
10
read-only
RXNUM
Read deta length in RX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
28
32
read-only
RXRPT
Rx FIFO Read pointer info
21
24
read-write
RXWPT
Rx FIFO Write pointer info
18
21
read-write
SIFACT
Read the status of serial interface (R). 0: Idle (default). 1: Operating
11
12
read-only
TXCOMP
Read the status of TX complete interrupt. 0: Exists Interrupt factor. 1: No Interrupt factor.
10
11
read-write
TXFUL
Read the status of TX FIFO (R). 0: TX FIFO is full. 1: TX FIFO is not full.
8
9
read-only
TXNUM
Read deta length in TX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
24
28
read-only
TXRPT
Tx FIFO Read pointer info
15
18
read-write
TXWPT
Tx FIFO Read pointer info
12
15
read-write
SPI_RXDATA
SPI RX Data
0xC
32
read-only
n
0x0
0x0
RX
Get RX data (R). When data is 24 bit length, [31:24] = 0x00 (default). When data is 16 bit length, [31:16] = 0x0000. When data is 8 bit length, [31:8] = 0x000000.
0
32
read-only
SPI_TIMINGCONTROL
SPI timing control
0x4
32
read-write
n
0x0
0x0
BASE
Frequency divider. 0: Forbidden. 1-255: value
8
16
read-write
CSDIS
Chip Select disable parameter. If set, CS will be deasserted at least clock*(this value +1). 0: No deassert. 1-15: Deassert
4
8
read-write
div
Change the division setting.
30
31
read-write
EXCKR
SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
22
23
read-write
EXCKW
Set Write clock extension. SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
23
24
read-write
PRS
Pre-Scaler Setting. 00: Communication clock x 1/1. 01: Communication clock x 1/2. 10: Communication clock x 1/4. 11: Communication clock x 1/8
0
2
read-write
SCKADJ
Serial Clock Adjustment. Set a value less than [15:8]. 0: Forbidden. 1-63: settingvalue
24
30
read-write
SCKMD
Serial Clock Mode. Enable/Disable Serial Clock modulation mode. 0: Disabled. 1: Enabled
3
4
read-write
SMPADJ
Sampling clock adjustment. 0: forbidden. 1-63: setting value
16
22
read-write
SMPMD
Sampling Modulation Mode.HOGEHOHGEOHGOHOGEHOGH
2
3
read-write
SPI_TIMINGCONTROL2
SPI timing control
0x20
32
read-write
n
0x0
0x0
ADDSPLDLY
Add sampling delay of RX data (R/W). 01: 1 clk delay (fixed)
16
18
read-write
DOADJ
Adjust Serial data and chip select. 0: No adjustment. Other: value
8
14
read-write
SCSMD
Chip Select output adjust timing enable/disable. 0: disable. 1: enable
1
2
read-write
SDOMD
Seriaou output adjust enable/disable. 0: Disable. 1: Enable
0
1
read-write
SPI_TXDATA
SPI TX data
0x8
32
read-write
n
0x0
0x0
BYTE
Set transfer byte length (R/W). 00: 1 byte (default). 01: 2 bytes. 10: 3 bytes (valid for read). 11: 4 bytes (valid for read)
16
18
read-write
CMD
Set transfer command (R/W). 0: Write (default). 1: Read
18
19
read-write
CONT
Set continuous transfer (R/W). 0: Deassert CS per word (default). 1: Keep CS between words
19
20
read-write
LEN
Default value is zero. When CMD is write (bit[18] = 0), set TX options (R/W). bit[31:26] Reserved bit[25] SPI DO polarity (0: L, 1: H) bit[24] SPI DO output status (0: keep the last data, 1: output H/L set at bit 25). When CMD is read (bit[18] = 1), set RX data length (R/W). bit[31:24] RX data length (unit is defined at bit[17:16])
24
32
read-write
TX
Set TX data (R/W) Default value is zero.
0
16
read-write
WRBIT
Set valid TX bit length (R/W). 0x0: The setting at bit[17:16] is applied (default). 0x1: 1 bit. 0x2: 2 bit. ... 0xF: 15 bit
20
24
read-write
SPI_TXRXLENGTH
SPI Data Langth
0x2C
32
read-write
n
0x0
0x0
RxLEN
Set the length of Rx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E:31bit. 1F:32bit
8
13
read-write
TxLEN
Set the length of Tx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E: 31bit. 1F: 32bit
0
5
read-write
SPI_TXWAITTIMER0
SPI Wait Timer 0
0x24
32
read-write
n
0x0
0x0
TIM0B
Value for Tx Waittimer0.
0
20
read-write
SPI_TXWAITTIMER1
SPI Wait Timer 1
0x28
32
read-write
n
0x0
0x0
TIM1B
Value for Tx Waittimer1.
0
20
read-write
SPI2
Serial Peripheral Interface(Master/Slave)
SPI2
0x0
0x0
0x30
registers
n
SPI_CONTROL
SPI control
0x0
32
read-write
n
0x0
0x0
SETACT
Set operation mode (R/W). 0: Configuration mode. 1: Active mode (default)
1
2
read-write
SLAVE
Set master/slave mode (R/W). 0: Master mode (default). 1: Slave mode
31
32
read-write
SPCSEN0
Enable CS (R/W). 0: Disable. 1: Enable (default)
8
9
read-write
SPCSPL0
Set CS polarity (R/W). 0: Low active (default). 1: High active
12
13
read-write
SPDIR
Specify LSB/MSB first (R/W). 0: MSB first (default). 1: LSB first
7
8
read-write
SPSCKPH
Specify serial clock phase (R/W). 0: Sampling at the first edge (default). 1: Sampling at the second edge
5
6
read-write
SPSCKPL
Specify serial clock polarity (R/W). 0: Sampling at high (default). 1: Sampling at low
6
7
read-write
SPI_INTCONTROL
SPI intrrupt control
0x10
32
read-write
n
0x0
0x0
INTCPS
Serial Tx Complete interrupt. 0: Disable interrupt. 1: Enable interrupt.
4
5
read-write
INTCRX0
RX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
3
4
read-write
INTCTIM0
Serial Tx Wait timer 0 interrupt. 0: Disable interrupt. 1: Enable interrupt.
5
6
read-write
INTCTIM1
Serial Tx Wait timer1 interrupt. 0: Disable interrupt. 1: Enable interrupt.
6
7
read-write
INTCTX0
TX FIFO Overrun interrupt. 0: Disable interrupt. 1: Enable interrupt.
2
3
read-write
INTCTXCOMP
Set Tx complete interrupt. 0: Disable interrupt. 1: Enable interrupt
11
12
read-write
INTCTXCOMPSEL
Tx complete interrupt select bit. Selects the interrupt for bit 10 of interrupt status register. 0: SPI Tx complete status. 1: SPI Tx complete including SPI DMA TX
15
16
read-write
INTCTXUR
Serial Under-run interrupt. 0: Disable interrupt. 1: Enable interrupt.
7
8
read-write
INTRX
RX FIFO interrupt. Asserted when there are datas more than [18:16]. 0: Disable interrupt. 1: Enable interrupt.
1
2
read-write
INTTX
TX FIFO interrupt. Asserted when there are datas more than [10:8]. 0: Disable interrupt. 1: Enable interrupt.
0
1
read-write
RXCLR
Clear RX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
20
21
read-write
RXINUM
Watermark for Rx FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
16
19
read-write
TXCLR
Clear TX FIFO (R/W). 0: Do not clear (default). 1: Clear After claer, this register becomes 0.
12
13
read-write
TXINUM
Water mark for TX FIFO interrupt. 000: more than 1 data. 001: more than 2 data. 010: more than 3 data. 011: more than 4 data. 100: more than 5 data. 101: more than 6 data. 110: more than 7 data. 111: more than 8 data
8
11
read-write
SPI_INTSTATUS
SPI interrupt status
0x14
32
read-write
n
0x0
0x0
INTSRX
Reads Rx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
1
2
read-write
INTSRX0
Reads Rx Fifo Overrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
3
4
read-write
INTSSPS
Reads Tx send complete interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
4
5
read-write
INTSTIM0
Reads Tx Wait timer0 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
5
6
read-write
INTSTIM1
Reads Tx Wait timer1 interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
6
7
read-write
INTSTX
Reads Tx FIFO interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
0
1
read-write
INTSTX0
Reads Tx Fifo Overrun interrupt. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
2
3
read-write
INTSTXUR
Reads Tx Underrun interrupt status. Write 1 to clear. Write 0 is don't care. 0: No interrupt. 1: Interrupt exist.
7
8
read-write
RXEMP
Read the status of RX FIFO (R). 0: RX FIFO is empty. 1: RX FIFO is not empty.
9
10
read-only
RXNUM
Read deta length in RX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
28
32
read-only
RXRPT
Rx FIFO Read pointer info
21
24
read-write
RXWPT
Rx FIFO Write pointer info
18
21
read-write
SIFACT
Read the status of serial interface (R). 0: Idle (default). 1: Operating
11
12
read-only
TXCOMP
Read the status of TX complete interrupt. 0: Exists Interrupt factor. 1: No Interrupt factor.
10
11
read-write
TXFUL
Read the status of TX FIFO (R). 0: TX FIFO is full. 1: TX FIFO is not full.
8
9
read-only
TXNUM
Read deta length in TX FIFO (R). 0000: 0 (default). 0001: 1. ... 0111: 7. 1000: 8. Others: Don't care
24
28
read-only
TXRPT
Tx FIFO Read pointer info
15
18
read-write
TXWPT
Tx FIFO Read pointer info
12
15
read-write
SPI_RXDATA
SPI RX Data
0xC
32
read-only
n
0x0
0x0
RX
Get RX data (R). When data is 24 bit length, [31:24] = 0x00 (default). When data is 16 bit length, [31:16] = 0x0000. When data is 8 bit length, [31:8] = 0x000000.
0
32
read-only
SPI_TIMINGCONTROL
SPI timing control
0x4
32
read-write
n
0x0
0x0
BASE
Frequency divider. 0: Forbidden. 1-255: value
8
16
read-write
CSDIS
Chip Select disable parameter. If set, CS will be deasserted at least clock*(this value +1). 0: No deassert. 1-15: Deassert
4
8
read-write
div
Change the division setting.
30
31
read-write
EXCKR
SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
22
23
read-write
EXCKW
Set Write clock extension. SCK will be output after the deassert of CS. The duration is set on [7:4]. 0: Disable clock extension. 1: Enable clock extension.
23
24
read-write
PRS
Pre-Scaler Setting. 00: Communication clock x 1/1. 01: Communication clock x 1/2. 10: Communication clock x 1/4. 11: Communication clock x 1/8
0
2
read-write
SCKADJ
Serial Clock Adjustment. Set a value less than [15:8]. 0: Forbidden. 1-63: settingvalue
24
30
read-write
SCKMD
Serial Clock Mode. Enable/Disable Serial Clock modulation mode. 0: Disabled. 1: Enabled
3
4
read-write
SMPADJ
Sampling clock adjustment. 0: forbidden. 1-63: setting value
16
22
read-write
SMPMD
Sampling Modulation Mode.
2
3
read-write
SPI_TIMINGCONTROL2
SPI timing control
0x20
32
read-write
n
0x0
0x0
ADDSPLDLY
Add sampling delay of RX data (R/W). 01: 1 clk delay (fixed)
16
18
read-write
DOADJ
Adjust Serial data and chip select. 0: No adjustment. Other: value
8
14
read-write
SCSMD
Chip Select output adjust timing enable/disable. 0: disable. 1: enable
1
2
read-write
SDOMD
Seriaou output adjust enable/disable. 0: Disable. 1: Enable
0
1
read-write
SPI_TXDATA
SPI TX data
0x8
32
read-write
n
0x0
0x0
BYTE
Set transfer byte length (R/W). 00: 1 byte (default). 01: 2 bytes. 10: 3 bytes (valid for read). 11: 4 bytes (valid for read)
16
18
read-write
CMD
Set transfer command (R/W). 0: Write (default). 1: Read
18
19
read-write
CONT
Set continuous transfer (R/W). 0: Deassert CS per word (default). 1: Keep CS between words
19
20
read-write
LEN
Default value is zero. When CMD is write (bit[18] = 0), set TX options (R/W). bit[31:26] Reserved bit[25] SPI DO polarity (0: L, 1: H) bit[24] SPI DO output status (0: keep the last data, 1: output H/L set at bit 25). When CMD is read (bit[18] = 1), set RX data length (R/W). bit[31:24] RX data length (unit is defined at bit[17:16])
24
32
read-write
TX
Set TX data (R/W) Default value is zero.
0
16
read-write
WRBIT
Set valid TX bit length (R/W). 0x0: The setting at bit[17:16] is applied (default). 0x1: 1 bit. 0x2: 2 bit. ... 0xF: 15 bit
20
24
read-write
SPI_TXRXLENGTH
SPI Data Langth
0x2C
32
read-write
n
0x0
0x0
RxLEN
Set the length of Rx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E:31bit. 1F:32bit
8
13
read-write
TxLEN
Set the length of Tx data length. 00-02: Forbidden. 03: 4bit. 04: 5bit. ... 1E: 31bit. 1F: 32bit
0
5
read-write
SPI_TXWAITTIMER0
SPI Wait Timer 0
0x24
32
read-write
n
0x0
0x0
TIM0B
Value for Tx Waittimer0.
0
20
read-write
SPI_TXWAITTIMER1
SPI Wait Timer 1
0x28
32
read-write
n
0x0
0x0
TIM1B
Value for Tx Waittimer1.
0
20
read-write
TimerBCG
Timer (BCTimer, GTimer)
TimerBCG
0x0
0x0
0x200
registers
n
TIM_BCTIMER_A
Bit Clock Timer A control
0x8
32
read-write
n
0x0
0x0
TimA
Start Value Timer A. Set the initial value of Timer A.
0
16
read-write
TIM_BCTIMER_A_RD
Bit Clock Timer A read
0x14
32
read-write
n
0x0
0x0
TimARd
Current Value of Timer A
0
16
read-write
TIM_BCTIMER_B
Bit Clock Timer B control
0xC
32
read-write
n
0x0
0x0
TimB
Start Value Timer B. Set the initial value of Timer B.
0
16
read-write
TIM_BCTIMER_B_RD
Bit Clock Timer B read
0x18
32
read-write
n
0x0
0x0
TimBRd
Current Value of Timer B
0
16
read-write
TIM_BCTIMER_C
Bit Clock Timer C control
0x10
32
read-write
n
0x0
0x0
TimC
Start Value Timer C. Set the initial value of Timer C.
0
16
read-write
TIM_BCTIMER_CTRL
Bit Clock Timer Control
0x0
32
read-write
n
0x0
0x0
AEn
Enable autoreload feature for timer A. 0: Stop when Timer A gets 0. 1: Reload the initial value when Timer A gets 0.
0
1
read-write
BEn
Enable autoreload feature for timer B. 0: Stop when Timer B gets 0. 1: Reload the initial value when Timer B gets 0.
1
2
read-write
CEn
Enable autoreload feature for timer C. 0: Stop when Timer C gets 0. 1: Reload the initial value when Timer C gets 0.
2
3
read-write
INTMA
Timer A Interrupt mask. 0: the interrupt is not masked. 1: the interutpt is masked
8
9
read-write
INTMB
Timer B Interrupt mask. 0: the interrupt is not masked. 1: the interutpt is masked
9
10
read-write
INTMC
Timer C Interrupt mask. 0: the interrupt is not masked. 1: the interutpt is masked
10
11
read-write
TIM_BCTIMER_C_RD
Bit Clock Timer C read
0x1C
32
read-write
n
0x0
0x0
TimCRd
Current Value of Timer C
0
16
read-write
TIM_BCTIMER_STAT
Bit Clock Timer Status
0x4
32
read-write
n
0x0
0x0
TimerAInt
Interrupt from Timer A. 0: No interrupt from Timer A. 1: Interrupt from Timer A exist.
0
1
read-write
TimerBInt
Interrupt from Timer B. 0: No interrupt from Timer B. 1: Interrupt from Timer B exist.
1
2
read-write
TimerCInt
Interrupt from Timer C. 0: No interrupt from Timer C. 1: Interrupt from Timer C exist.
2
3
read-write
TIM_GTIMER_A
Timer Initial Value
0x108
32
read-write
n
0x0
0x0
TimA
Start Value of TimerA.
0
16
read-write
TIM_GTIMER_A_RD
Timer Value read
0x114
32
read-write
n
0x0
0x0
TimerARd
Current Value of Timer A.
0
16
read-write
TIM_GTIMER_CTRL
Timer Control
0x100
32
read-write
n
0x0
0x0
AEn
Enable auto reload feature for Timer A
0
1
read-write
INTMA
Timer A Interrupt mask. 0: the interrupt is not masked. 1: the interutpt is masked
8
9
read-write
PRESCALERVAL
Settings for frequency divider of TimerSCLK to generate timer clock. 0x000 : No divide. 0x001 : 1/2. 0x002 : 1/3. ........ 0xfff : 1/4096
16
28
read-write
TIM_GTIMER_STAT
Timer Status
0x104
32
read-write
n
0x0
0x0
TimerAInt
Interrutp bit from Timer A. 0: No interrupt from Timer A. 1: Interrupt from Timer A exist.
0
1
read-write
UART1
UART1
UART1
0x0
0x0
0x40
registers
n
UART_CWTCR
CWT Control Register
0x18
32
read-write
n
0x0
0x0
RxDataMon
Monitor data existance info after Character Inteval Timeout
16
17
read-write
TimStartValue
UART Receive Timer value
0
16
read-write
UART_FBRD
Baud Rate Decimal Setting Register
0x30
32
read-write
n
0x0
0x0
UFBRD
UART Baudrate Decimal Setting
0
6
read-write
UART_IBRD
Baud Rate Setting Register
0x1C
32
read-write
n
0x0
0x0
BAUDINT
UART Baudrate Integer divisor value
0
16
read-write
UART_ICR
Interrupt Clear Register
0x4
32
read-write
n
0x0
0x0
DataSentclr
Clear DataSent Interrupt
3
4
read-write
FramingErrorclr
Clear Framing Error Interrupt
0
1
read-write
OverrunErrorclr
Clear OverrunError Interrupt
1
2
read-write
ParityErrorclr
Clear ParityError Interrupt
2
3
read-write
RxDataReadyclr
Clear RxDataReady Interrupt
5
6
read-write
TimeOutclr
Clear CWT Time Out Interrupt
6
7
read-write
TxDataCompIntClr
Clear TxDataComp Interrupt
10
11
read-write
TxDataEMPTYclr
Clear TxDataEMPTY Interrupt
4
5
read-write
UART_IER
Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
DataSentEN
DataSent Interrupt Enable
3
4
read-write
FramingErrorEN
FramingError Interrupt Enable
0
1
read-write
OverrunErrorEN
OverrunError Interrupt Enable
1
2
read-write
ParityErrorEN
ParityError Interrupt Enable
2
3
read-write
RxDataReadyEN
RxDataReady Interrupt Enable
5
6
read-write
TimeOutEN
CWT TimeOut Interrupt Enable
6
7
read-write
TxDataCompEN
TxDataComp Interrupt Enable
10
11
read-write
TxDataEMPTYEN
TxDataEMPTY Interrupt Enable
4
5
read-write
UART_ILSR
Interrupt and Line Status Register
0x8
32
read-write
n
0x0
0x0
DataSent
Data Sent Interrupt Status
3
4
read-write
FramingError
FramingError Interrupt Status
0
1
read-write
OVCRWriteBusy
Status of OVCR Write
7
8
read-write
OverrunError
OverrunError Interrupt Status
1
2
read-write
ParityError
ParityErrorr Interrupt Status
2
3
read-write
RxBusy
Indicates if Rx working
14
15
read-write
RxDataReady
RxDataReady Interupt Status
5
6
read-write
RxFC
Count in Rx FIFO
16
21
read-write
TimeOut
CWT TimeOut Interrupt Status
6
7
read-write
TxBusy
Indicates is Tx working
15
16
read-write
TxDataCompint
Tx Data Complete Interrupt
10
11
read-write
TxDataEMPTY
TxDataEMPTY Interrupt Status
4
5
read-write
TxFC
Count in Tx FIFO
24
29
read-write
UART_LFCR
Line and FIFO Control Register
0x10
32
read-write
n
0x0
0x0
ClkSel
Select Clock for BaudRate
7
8
read-write
CTSEn
Enable CTS Flow Control
16
17
read-write
InitUART
Initialize Sample Counter
5
6
read-write
ParitySel
Select Parity bit (odd or even)
3
4
read-write
RTSEn
Enable RTS Flow Control
17
18
read-write
RxDMAEn
RxDMA Request output enable
14
15
read-write
RxFIFOEn
RxFIFO Enable/Disable
10
11
read-write
RxFIFOSel
Select Rx FIFO Watermark Level
8
10
read-write
RxParityEn
Rx Data parity enable/disable
1
2
read-write
StopSel
Select Stop bit(1bit or 2bit)
4
5
read-write
TimerEnable
Tx Timer Enable/Disable
6
7
read-write
TxDMAEn
TxDMA Request output enable
15
16
read-write
TxFIFOEn
TxFIFO Enable/Disable
11
12
read-write
TxOutEn
Tx Output enable/disable
0
1
read-write
TxParityEn
Tx Data parity enable/disable
2
3
read-write
UARTRXMSK
Rx Data Mask
18
19
read-write
UART_OVCR
Sampling Control Register
0x14
32
read-write
n
0x0
0x0
OVSMPCYC
Oversample cycles setting
0
4
read-write
STDETCYC
Start bit detect cycles for UART Rx Data
4
7
read-write
UART_RBR_THR
Receiver Buffer Register/Transmitter Holding Register
0x0
32
read-write
n
0x0
0x0
RBR_THR
Tx/Rx Data
0
8
read-write
UART2
UART1
UART2
0x0
0x0
0x40
registers
n
UART_CWTCR
CWT Control Register
0x18
32
read-write
n
0x0
0x0
RxDataMon
Monitor data existance info after Character Inteval Timeout
16
17
read-write
TimStartValue
UART Receive Timer value
0
16
read-write
UART_FBRD
Baud Rate Decimal Setting Register
0x30
32
read-write
n
0x0
0x0
UFBRD
UART Baudrate Decimal Setting
0
6
read-write
UART_IBRD
Baud Rate Setting Register
0x1C
32
read-write
n
0x0
0x0
BAUDINT
UART Baudrate Integer divisor value
0
16
read-write
UART_ICR
Interrupt Clear Register
0x4
32
read-write
n
0x0
0x0
DataSentclr
Clear DataSent Interrupt
3
4
read-write
FramingErrorclr
Clear Framing Error Interrupt
0
1
read-write
OverrunErrorclr
Clear OverrunError Interrupt
1
2
read-write
ParityErrorclr
Clear ParityError Interrupt
2
3
read-write
RxDataReadyclr
Clear RxDataReady Interrupt
5
6
read-write
TimeOutclr
Clear CWT Time Out Interrupt
6
7
read-write
TxDataCompIntClr
Clear TxDataComp Interrupt
10
11
read-write
TxDataEMPTYclr
Clear TxDataEMPTY Interrupt
4
5
read-write
UART_IER
Interrupt Enable Register
0xC
32
read-write
n
0x0
0x0
DataSentEN
DataSent Interrupt Enable
3
4
read-write
FramingErrorEN
FramingError Interrupt Enable
0
1
read-write
OverrunErrorEN
OverrunError Interrupt Enable
1
2
read-write
ParityErrorEN
ParityError Interrupt Enable
2
3
read-write
RxDataReadyEN
RxDataReady Interrupt Enable
5
6
read-write
TimeOutEN
CWT TimeOut Interrupt Enable
6
7
read-write
TxDataCompEN
TxDataComp Interrupt Enable
10
11
read-write
TxDataEMPTYEN
TxDataEMPTY Interrupt Enable
4
5
read-write
UART_ILSR
Interrupt and Line Status Register
0x8
32
read-write
n
0x0
0x0
DataSent
Data Sent Interrupt Status
3
4
read-write
FramingError
FramingError Interrupt Status
0
1
read-write
OVCRWriteBusy
Status of OVCR Write
7
8
read-write
OverrunError
OverrunError Interrupt Status
1
2
read-write
ParityError
ParityErrorr Interrupt Status
2
3
read-write
RxBusy
Indicates if Rx working
14
15
read-write
RxDataReady
RxDataReady Interupt Status
5
6
read-write
RxFC
Count in Rx FIFO
16
21
read-write
TimeOut
CWT TimeOut Interrupt Status
6
7
read-write
TxBusy
Indicates is Tx working
15
16
read-write
TxDataCompint
Tx Data Complete Interrupt
10
11
read-write
TxDataEMPTY
TxDataEMPTY Interrupt Status
4
5
read-write
TxFC
Count in Tx FIFO
24
29
read-write
UART_LFCR
Line and FIFO Control Register
0x10
32
read-write
n
0x0
0x0
ClkSel
Select Clock for BaudRate
7
8
read-write
CTSEn
Enable CTS Flow Control
16
17
read-write
InitUART
Initialize Sample Counter
5
6
read-write
ParitySel
Select Parity bit (odd or even)
3
4
read-write
RTSEn
Enable RTS Flow Control
17
18
read-write
RxDMAEn
RxDMA Request output enable
14
15
read-write
RxFIFOEn
RxFIFO Enable/Disable
10
11
read-write
RxFIFOSel
Select Rx FIFO Watermark Level
8
10
read-write
RxParityEn
Rx Data parity enable/disable
1
2
read-write
StopSel
Select Stop bit(1bit or 2bit)
4
5
read-write
TimerEnable
Tx Timer Enable/Disable
6
7
read-write
TxDMAEn
TxDMA Request output enable
15
16
read-write
TxFIFOEn
TxFIFO Enable/Disable
11
12
read-write
TxOutEn
Tx Output enable/disable
0
1
read-write
TxParityEn
Tx Data parity enable/disable
2
3
read-write
UARTRXMSK
Rx Data Mask
18
19
read-write
UART_OVCR
Sampling Control Register
0x14
32
read-write
n
0x0
0x0
OVSMPCYC
Oversample cycles setting
0
4
read-write
STDETCYC
Start bit detect cycles for UART Rx Data
4
7
read-write
UART_RBR_THR
Receiver Buffer Register/Transmitter Holding Register
0x0
32
read-write
n
0x0
0x0
RBR_THR
Tx/Rx Data
0
8
read-write