WCH CH32V30xxx 2025.05.09 CH32V30xxx View File 8 32 ADC1 Analog to digital converter ADC1 0x40012400 0x0 0x400 registers n ADC ADC global interrupt 34 CTLR1 CTLR1 control register 1/TKEY_V_CTLR 0x4 32 read-write n 0x0 0xFFFFFFFF AWDCH Analog watchdog channel select bits 0 5 AWDEN Analog watchdog enable on regular channels 23 1 AWDIE Analog watchdog interrupt enable 6 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 BUFEN TKEY_BUF_Enable 26 1 DISCEN Discontinuous mode on regular channels 11 1 DISCNUM Discontinuous mode channel count 13 3 DUALMOD Dual mode selection 16 4 EOCIE Interrupt enable for EOC 5 1 JAUTO Automatic injected group conversion 10 1 JAWDEN Analog watchdog enable on injected channels 22 1 JDISCEN Discontinuous mode on injected channels 12 1 JEOCIE Interrupt enable for injected channels 7 1 PGA ADC_PGA 27 2 SCAN Scan mode enable 8 1 TKEYEN TKEY enable, including TKEY_F and TKEY_V 24 1 TKITUNE TKEY_I enable 25 1 CTLR2 CTLR2 control register 2 0x8 32 read-write n 0x0 0xFFFFFFFF ADON A/D converter ON / OFF 0 1 ALIGN Data alignment 11 1 CAL A/D calibration 2 1 CONT Continuous conversion 1 1 DMA Direct memory access mode 8 1 EXTSEL External event select for regular group 17 3 EXTTRIG External trigger conversion mode for regular channels 20 1 JEXTSEL External event select for injected group 12 3 JEXTTRIG External trigger conversion mode for injected channels 15 1 JSWSTART Start conversion of injected channels 21 1 RSTCAL Reset calibration 3 1 SWSTART Start conversion of regular channels 22 1 TSVREFE Temperature sensor and VREFINT enable 23 1 IDATAR1_CHGOFFSET IDATAR1_CHGOFFSET injected data register x_Charge data offset for injected channel x 0x3C 32 read-only n 0x0 0xFFFFFFFF IDATA0_7_TKCGOFFSET Injected data_Touch key charge data offset for injected channel x 0 8 IDATA8_15 Injected data 8 8 IDATAR2 IDATAR2 injected data register x 0x40 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IDATAR3 IDATAR3 injected data register x 0x44 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IDATAR4 IDATAR4 injected data register x 0x48 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IOFR1 IOFR1 injected channel data offset register x 0x14 32 read-write n 0x0 0xFFFFFFFF JOFFSET1 Data offset for injected channel x 0 12 IOFR2 IOFR2 injected channel data offset register x 0x18 32 read-write n 0x0 0xFFFFFFFF JOFFSET2 Data offset for injected channel x 0 12 IOFR3 IOFR3 injected channel data offset register x 0x1C 32 read-write n 0x0 0xFFFFFFFF JOFFSET3 Data offset for injected channel x 0 12 IOFR4 IOFR4 injected channel data offset register x 0x20 32 read-write n 0x0 0xFFFFFFFF JOFFSET4 Data offset for injected channel x 0 12 ISQR ISQR injected sequence register 0x38 32 read-write n 0x0 0xFFFFFFFF JL Injected sequence length 20 2 JSQ1 1st conversion in injected sequence 0 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ4 4th conversion in injected sequence 15 5 RDATAR_DR_ACT_DCG RDATAR_DR_ACT_DCG regular data register_start and discharge time register 0x4C 32 read-only_write-only n 0x0 0xFFFFFFFF DATA0_7_TKACT_DCG Regular data_Touch key start and discharge time register 0 8 DATA8_15 Regular data 8 8 RSQR1 RSQR1 regular sequence register 1 0x2C 32 read-write n 0x0 0xFFFFFFFF L Regular channel sequence length 20 4 SQ13 13th conversion in regular sequence 0 5 SQ14 14th conversion in regular sequence 5 5 SQ15 15th conversion in regular sequence 10 5 SQ16 16th conversion in regular sequence 15 5 RSQR2 RSQR2 regular sequence register 2 0x30 32 read-write n 0x0 0xFFFFFFFF SQ10 10th conversion in regular sequence 15 5 SQ11 11th conversion in regular sequence 20 5 SQ12 12th conversion in regular sequence 25 5 SQ7 7th conversion in regular sequence 0 5 SQ8 8th conversion in regular sequence 5 5 SQ9 9th conversion in regular sequence 10 5 RSQR3__CHANNEL RSQR3__CHANNEL regular sequence register 3 TKEY_V_CHANNEL 0x34 32 read-write n 0x0 0xFFFFFFFF SQ1__CHSEL 1st conversion in regular sequence TKDY_V channel select 0 5 SQ2 2nd conversion in regular sequence 5 5 SQ3 3rd conversion in regular sequence 10 5 SQ4 4th conversion in regular sequence 15 5 SQ5 5th conversion in regular sequence 20 5 SQ6 6th conversion in regular sequence 25 5 SAMPTR1_CHARGE1 SAMPTR1_CHARGE1 sample time register 1 0xC 32 read-write n 0x0 0xFFFFFFFF SMP10_TKCG10 Channel 10 sample time selection 0 3 SMP11_TKCG11 Channel 11 sample time selection 3 3 SMP12_TKCG12 Channel 12 sample time selection 6 3 SMP13_TKCG13 Channel 13 sample time selection 9 3 SMP14_TKCG14 Channel 14 sample time selection 12 3 SMP15_TKCG15 Channel 15 sample time selection 15 3 SMP16_TKCG16 Channel 16 sample time selection 18 3 SMP17_TKCG17 Channel 17 sample time selection 21 3 SAMPTR2_CHARGE2 SAMPTR2_CHARGE2 sample time register 2 0x10 32 read-write n 0x0 0xFFFFFFFF SMP0_TKCG0 Channel 0 sample time selection 0 3 SMP1_TKCG1 Channel 1 sample time selection 3 3 SMP2_TKCG2 Channel 2 sample time selection 6 3 SMP3_TKCG3 Channel 3 sample time selection 9 3 SMP4_TKCG4 Channel 4 sample time selection 12 3 SMP5_TKCG5 Channel 5 sample time selection 15 3 SMP6_TKCG6 Channel 6 sample time selection 18 3 SMP7_TKCG7 Channel 7 sample time selection 21 3 SMP8_TKCG8 Channel 8 sample time selection 24 3 SMP9_TKCG9 Channel 9 sample time selection 27 3 STATR STATR status register 0x0 32 read-write n 0x0 0xFFFFFFFF AWD Analog watchdog flag 0 1 EOC Regular channel end of conversion 1 1 JEOC Injected channel end of conversion 2 1 JSTRT Injected channel start flag 3 1 STRT Regular channel start flag 4 1 WDHTR WDHTR watchdog higher threshold register 0x24 32 read-write n 0x0 0xFFFFFFFF HT Analog watchdog higher threshold 0 12 WDLTR WDLTR watchdog lower threshold register 0x28 32 read-write n 0x0 0xFFFFFFFF LT Analog watchdog lower threshold 0 12 ADC2 Analog to digital converter ADC 0x40012800 0x0 0x400 registers n CTLR1 CTLR1 control register 1/TKEY_V_CTLR 0x4 32 read-write n 0x0 0xFFFFFFFF AWDCH Analog watchdog channel select bits 0 5 AWDEN Analog watchdog enable on regular channels 23 1 AWDIE Analog watchdog interrupt enable 6 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 BUFEN TKEY_BUF_Enable 26 1 DISCEN Discontinuous mode on regular channels 11 1 DISCNUM Discontinuous mode channel count 13 3 DUALMOD Dual mode selection 16 4 EOCIE Interrupt enable for EOC 5 1 JAUTO Automatic injected group conversion 10 1 JAWDEN Analog watchdog enable on injected channels 22 1 JDISCEN Discontinuous mode on injected channels 12 1 JEOCIE Interrupt enable for injected channels 7 1 PGA ADC_PGA 27 2 SCAN Scan mode enable 8 1 TKEYEN TKEY enable, including TKEY_F and TKEY_V 24 1 TKITUNE TKEY_I enable 25 1 CTLR2 CTLR2 control register 2 0x8 32 read-write n 0x0 0xFFFFFFFF ADON A/D converter ON / OFF 0 1 ALIGN Data alignment 11 1 CAL A/D calibration 2 1 CONT Continuous conversion 1 1 DMA Direct memory access mode 8 1 EXTSEL External event select for regular group 17 3 EXTTRIG External trigger conversion mode for regular channels 20 1 JEXTSEL External event select for injected group 12 3 JEXTTRIG External trigger conversion mode for injected channels 15 1 JSWSTART Start conversion of injected channels 21 1 RSTCAL Reset calibration 3 1 SWSTART Start conversion of regular channels 22 1 TSVREFE Temperature sensor and VREFINT enable 23 1 IDATAR1_CHGOFFSET IDATAR1_CHGOFFSET injected data register x_Charge data offset for injected channel x 0x3C 32 read-only n 0x0 0xFFFFFFFF IDATA0_7_TKCGOFFSET Injected data_Touch key charge data offset for injected channel x 0 8 IDATA8_15 Injected data 8 8 IDATAR2 IDATAR2 injected data register x 0x40 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IDATAR3 IDATAR3 injected data register x 0x44 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IDATAR4 IDATAR4 injected data register x 0x48 32 read-only n 0x0 0xFFFFFFFF JDATA Injected data 0 16 IOFR1 IOFR1 injected channel data offset register x 0x14 32 read-write n 0x0 0xFFFFFFFF JOFFSET1 Data offset for injected channel x 0 12 IOFR2 IOFR2 injected channel data offset register x 0x18 32 read-write n 0x0 0xFFFFFFFF JOFFSET2 Data offset for injected channel x 0 12 IOFR3 IOFR3 injected channel data offset register x 0x1C 32 read-write n 0x0 0xFFFFFFFF JOFFSET3 Data offset for injected channel x 0 12 IOFR4 IOFR4 injected channel data offset register x 0x20 32 read-write n 0x0 0xFFFFFFFF JOFFSET4 Data offset for injected channel x 0 12 ISQR ISQR injected sequence register 0x38 32 read-write n 0x0 0xFFFFFFFF JL Injected sequence length 20 2 JSQ1 1st conversion in injected sequence 0 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ4 4th conversion in injected sequence 15 5 RDATAR_DR_ACT_DCG RDATAR_DR_ACT_DCG regular data register_start and discharge time register 0x4C 32 read-only_write-only n 0x0 0xFFFFFFFF DATA0_7_TKACT_DCG Regular data_Touch key start and discharge time register 0 8 DATA8_15 Regular data 8 8 RSQR1 RSQR1 regular sequence register 1 0x2C 32 read-write n 0x0 0xFFFFFFFF L Regular channel sequence length 20 4 SQ13 13th conversion in regular sequence 0 5 SQ14 14th conversion in regular sequence 5 5 SQ15 15th conversion in regular sequence 10 5 SQ16 16th conversion in regular sequence 15 5 RSQR2 RSQR2 regular sequence register 2 0x30 32 read-write n 0x0 0xFFFFFFFF SQ10 10th conversion in regular sequence 15 5 SQ11 11th conversion in regular sequence 20 5 SQ12 12th conversion in regular sequence 25 5 SQ7 7th conversion in regular sequence 0 5 SQ8 8th conversion in regular sequence 5 5 SQ9 9th conversion in regular sequence 10 5 RSQR3__CHANNEL RSQR3__CHANNEL regular sequence register 3 TKEY_V_CHANNEL 0x34 32 read-write n 0x0 0xFFFFFFFF SQ1__CHSEL 1st conversion in regular sequence TKDY_V channel select 0 5 SQ2 2nd conversion in regular sequence 5 5 SQ3 3rd conversion in regular sequence 10 5 SQ4 4th conversion in regular sequence 15 5 SQ5 5th conversion in regular sequence 20 5 SQ6 6th conversion in regular sequence 25 5 SAMPTR1_CHARGE1 SAMPTR1_CHARGE1 sample time register 1 0xC 32 read-write n 0x0 0xFFFFFFFF SMP10_TKCG10 Channel 10 sample time selection 0 3 SMP11_TKCG11 Channel 11 sample time selection 3 3 SMP12_TKCG12 Channel 12 sample time selection 6 3 SMP13_TKCG13 Channel 13 sample time selection 9 3 SMP14_TKCG14 Channel 14 sample time selection 12 3 SMP15_TKCG15 Channel 15 sample time selection 15 3 SMP16_TKCG16 Channel 16 sample time selection 18 3 SMP17_TKCG17 Channel 17 sample time selection 21 3 SAMPTR2_CHARGE2 SAMPTR2_CHARGE2 sample time register 2 0x10 32 read-write n 0x0 0xFFFFFFFF SMP0_TKCG0 Channel 0 sample time selection 0 3 SMP1_TKCG1 Channel 1 sample time selection 3 3 SMP2_TKCG2 Channel 2 sample time selection 6 3 SMP3_TKCG3 Channel 3 sample time selection 9 3 SMP4_TKCG4 Channel 4 sample time selection 12 3 SMP5_TKCG5 Channel 5 sample time selection 15 3 SMP6_TKCG6 Channel 6 sample time selection 18 3 SMP7_TKCG7 Channel 7 sample time selection 21 3 SMP8_TKCG8 Channel 8 sample time selection 24 3 SMP9_TKCG9 Channel 9 sample time selection 27 3 STATR STATR status register 0x0 32 read-write n 0x0 0xFFFFFFFF AWD Analog watchdog flag 0 1 EOC Regular channel end of conversion 1 1 JEOC Injected channel end of conversion 2 1 JSTRT Injected channel start flag 3 1 STRT Regular channel start flag 4 1 WDHTR WDHTR watchdog higher threshold register 0x24 32 read-write n 0x0 0xFFFFFFFF HT Analog watchdog higher threshold 0 12 WDLTR WDLTR watchdog lower threshold register 0x28 32 read-write n 0x0 0xFFFFFFFF LT Analog watchdog lower threshold 0 12 AFIO Alternate function I/O AFIO 0x40010000 0x0 0x400 registers n ECR ECR Event Control Register (AFIO_ECR) 0x0 32 read-write n 0x0 0xFFFFFFFF EVOE Event Output Enable 7 1 PIN Pin selection 0 4 PORT Port selection 4 3 EXTICR1 EXTICR1 External interrupt configuration register 1 (AFIO_EXTICR1) 0x8 32 read-write n 0x0 0xFFFFFFFF EXTI0 EXTI0 configuration 0 4 EXTI1 EXTI1 configuration 4 4 EXTI2 EXTI2 configuration 8 4 EXTI3 EXTI3 configuration 12 4 EXTICR2 EXTICR2 External interrupt configuration register 2 (AFIO_EXTICR2) 0xC 32 read-write n 0x0 0xFFFFFFFF EXTI4 EXTI4 configuration 0 4 EXTI5 EXTI5 configuration 4 4 EXTI6 EXTI6 configuration 8 4 EXTI7 EXTI7 configuration 12 4 EXTICR3 EXTICR3 External interrupt configuration register 3 (AFIO_EXTICR3) 0x10 32 read-write n 0x0 0xFFFFFFFF EXTI10 EXTI10 configuration 8 4 EXTI11 EXTI11 configuration 12 4 EXTI8 EXTI8 configuration 0 4 EXTI9 EXTI9 configuration 4 4 EXTICR4 EXTICR4 External interrupt configuration register 4 (AFIO_EXTICR4) 0x14 32 read-write n 0x0 0xFFFFFFFF EXTI12 EXTI12 configuration 0 4 EXTI13 EXTI13 configuration 4 4 EXTI14 EXTI14 configuration 8 4 EXTI15 EXTI15 configuration 12 4 PCFR PCFR AF remap and debug I/O configuration register (AFIO_PCFR) 0x4 32 n 0x0 0xFFFFFFFF ADC1_ETRGINJ_RM ADC 1 External trigger injected conversion remapping 17 1 read-write ADC1_ETRGREG_RM ADC 1 external trigger regular conversion remapping 18 1 read-write ADC2_ETRGINJ_RM ADC 2 External trigger injected conversion remapping 19 1 read-write ADC2_ETRGREG_RM ADC 2 external trigger regular conversion remapping 20 1 read-write CAN1RM CAN1 remapping 13 2 read-write CAN2RM CAN2 remapping 22 1 read-write ETHRM Ethernet remapping 21 1 read-write I2C1RM I2C1 remapping 1 1 read-write MII_RMII_SEL MII_RMII_SEL 23 1 read-write PD01RM Port D0/Port D1 mapping on OSCIN/OSCOUT 15 1 read-write PTP_PPSP_RM Ethernet PTP_PPS remapping 30 1 read-write SPI1RM SPI1 remapping 0 1 read-write SPI3_RM SPI3 remapping 28 1 read-write SWCFG Serial wire JTAG configuration 24 3 write-only TIM1RM TIM1 remapping 6 2 read-write TIM2ITRA_RM TIM2 internally triggers 1 remapping 29 1 read-write TIM2RM TIM2 remapping 8 2 read-write TIM3RM TIM3 remapping 10 2 read-write TIM4RM TIM4 remapping 12 1 read-write TIM5CH4RM TIM5 channel4 internal remap 16 1 read-write USART1RM USART1 remapping 2 1 read-write USART2RM USART2 remapping 3 1 read-write USART3RM USART3 remapping 4 2 read-write PCFR2 PCFR2 AF remap and debug I/O configuration register (AFIO_PCFR2) 0x1C 32 n 0x0 0xFFFFFFFF FSMC_NADV FSMC_NADV 10 1 read-write TIM10_REMAP TIM10 remapping 5 2 read-write TIM8_REMAP TIM8 remapping 2 1 read-write TIM9_REMAP TIM9 remapping 3 2 read-write UART1_REMAP2 UART1 remapping 26 1 read-write UART4_REMAP UART4 remapping 16 2 read-write UART5_REMAP UART5 remapping 18 2 read-write UART6_REMAP UART6 remapping 20 2 read-write UART7_REMAP UART7 remapping 22 2 read-write UART8_REMAP UART8 remapping 24 2 read-write BKP Backup registers BKP 0x40006C00 0x0 0x400 registers n DATAR1 DATAR1 Backup data register (BKP_DR) 0x4 32 read-write n 0x0 0xFFFFFFFF D1 Backup data 0 16 DATAR10 DATAR10 Backup data register (BKP_DR) 0x28 32 read-write n 0x0 0xFFFFFFFF D10 Backup data 0 16 DATAR11 DATAR11 Backup data register (BKP_DR) 0x40 32 read-write n 0x0 0xFFFFFFFF DR11 Backup data 0 16 DATAR12 DATAR12 Backup data register (BKP_DR) 0x44 32 read-write n 0x0 0xFFFFFFFF DR12 Backup data 0 16 DATAR13 DATAR13 Backup data register (BKP_DR) 0x48 32 read-write n 0x0 0xFFFFFFFF DR13 Backup data 0 16 DATAR14 DATAR14 Backup data register (BKP_DR) 0x4C 32 read-write n 0x0 0xFFFFFFFF D14 Backup data 0 16 DATAR15 DATAR15 Backup data register (BKP_DR) 0x50 32 read-write n 0x0 0xFFFFFFFF D15 Backup data 0 16 DATAR16 DATAR16 Backup data register (BKP_DR) 0x54 32 read-write n 0x0 0xFFFFFFFF D16 Backup data 0 16 DATAR17 DATAR17 Backup data register (BKP_DR) 0x58 32 read-write n 0x0 0xFFFFFFFF D17 Backup data 0 16 DATAR18 DATAR18 Backup data register (BKP_DR) 0x5C 32 read-write n 0x0 0xFFFFFFFF D18 Backup data 0 16 DATAR19 DATAR19 Backup data register (BKP_DR) 0x60 32 read-write n 0x0 0xFFFFFFFF D19 Backup data 0 16 DATAR2 DATAR2 Backup data register (BKP_DR) 0x8 32 read-write n 0x0 0xFFFFFFFF D2 Backup data 0 16 DATAR20 DATAR20 Backup data register (BKP_DR) 0x64 32 read-write n 0x0 0xFFFFFFFF D20 Backup data 0 16 DATAR21 DATAR21 Backup data register (BKP_DR) 0x68 32 read-write n 0x0 0xFFFFFFFF D21 Backup data 0 16 DATAR22 DATAR22 Backup data register (BKP_DR) 0x6C 32 read-write n 0x0 0xFFFFFFFF D22 Backup data 0 16 DATAR23 DATAR23 Backup data register (BKP_DR) 0x70 32 read-write n 0x0 0xFFFFFFFF D23 Backup data 0 16 DATAR24 DATAR24 Backup data register (BKP_DR) 0x74 32 read-write n 0x0 0xFFFFFFFF D24 Backup data 0 16 DATAR25 DATAR25 Backup data register (BKP_DR) 0x78 32 read-write n 0x0 0xFFFFFFFF D25 Backup data 0 16 DATAR26 DATAR26 Backup data register (BKP_DR) 0x7C 32 read-write n 0x0 0xFFFFFFFF D26 Backup data 0 16 DATAR27 DATAR27 Backup data register (BKP_DR) 0x80 32 read-write n 0x0 0xFFFFFFFF D27 Backup data 0 16 DATAR28 DATAR28 Backup data register (BKP_DR) 0x84 32 read-write n 0x0 0xFFFFFFFF D28 Backup data 0 16 DATAR29 DATAR29 Backup data register (BKP_DR) 0x88 32 read-write n 0x0 0xFFFFFFFF D29 Backup data 0 16 DATAR3 DATAR3 Backup data register (BKP_DR) 0xC 32 read-write n 0x0 0xFFFFFFFF D3 Backup data 0 16 DATAR30 DATAR30 Backup data register (BKP_DR) 0x8C 32 read-write n 0x0 0xFFFFFFFF D30 Backup data 0 16 DATAR31 DATAR31 Backup data register (BKP_DR) 0x90 32 read-write n 0x0 0xFFFFFFFF D31 Backup data 0 16 DATAR32 DATAR32 Backup data register (BKP_DR) 0x94 32 read-write n 0x0 0xFFFFFFFF D32 Backup data 0 16 DATAR33 DATAR33 Backup data register (BKP_DR) 0x98 32 read-write n 0x0 0xFFFFFFFF D33 Backup data 0 16 DATAR34 DATAR34 Backup data register (BKP_DR) 0x9C 32 read-write n 0x0 0xFFFFFFFF D34 Backup data 0 16 DATAR35 DATAR35 Backup data register (BKP_DR) 0xA0 32 read-write n 0x0 0xFFFFFFFF D35 Backup data 0 16 DATAR36 DATAR36 Backup data register (BKP_DR) 0xA4 32 read-write n 0x0 0xFFFFFFFF D36 Backup data 0 16 DATAR37 DATAR37 Backup data register (BKP_DR) 0xA8 32 read-write n 0x0 0xFFFFFFFF D37 Backup data 0 16 DATAR38 DATAR38 Backup data register (BKP_DR) 0xAC 32 read-write n 0x0 0xFFFFFFFF D38 Backup data 0 16 DATAR39 DATAR39 Backup data register (BKP_DR) 0xB0 32 read-write n 0x0 0xFFFFFFFF D39 Backup data 0 16 DATAR4 DATAR4 Backup data register (BKP_DR) 0x10 32 read-write n 0x0 0xFFFFFFFF D4 Backup data 0 16 DATAR40 DATAR40 Backup data register (BKP_DR) 0xB4 32 read-write n 0x0 0xFFFFFFFF D40 Backup data 0 16 DATAR41 DATAR41 Backup data register (BKP_DR) 0xB8 32 read-write n 0x0 0xFFFFFFFF D41 Backup data 0 16 DATAR42 DATAR42 Backup data register (BKP_DR) 0xBC 32 read-write n 0x0 0xFFFFFFFF D42 Backup data 0 16 DATAR5 DATAR5 Backup data register (BKP_DR) 0x14 32 read-write n 0x0 0xFFFFFFFF D5 Backup data 0 16 DATAR6 DATAR6 Backup data register (BKP_DR) 0x18 32 read-write n 0x0 0xFFFFFFFF D6 Backup data 0 16 DATAR7 DATAR7 Backup data register (BKP_DR) 0x1C 32 read-write n 0x0 0xFFFFFFFF D7 Backup data 0 16 DATAR8 DATAR8 Backup data register (BKP_DR) 0x20 32 read-write n 0x0 0xFFFFFFFF D8 Backup data 0 16 DATAR9 DATAR9 Backup data register (BKP_DR) 0x24 32 read-write n 0x0 0xFFFFFFFF D9 Backup data 0 16 OCTLR OCTLR RTC clock calibration register (BKP_OCTLR) 0x2C 32 read-write n 0x0 0xFFFFFFFF ASOE Alarm or second output enable 8 1 ASOS Alarm or second output selection 9 1 CAL Calibration value 0 7 CCO Calibration Clock Output 7 1 TPCSR TPCSR BKP_TPCSR control/status register (BKP_CSR) 0x34 32 n 0x0 0xFFFFFFFF CTE Clear Tamper event 0 1 write-only CTI Clear Tamper Interrupt 1 1 write-only TEF Tamper Event Flag 8 1 read-only TIF Tamper Interrupt Flag 9 1 read-only TPIE Tamper Pin interrupt enable 2 1 read-write TPCTLR TPCTLR Backup control register (BKP_TPCTLR) 0x30 32 read-write n 0x0 0xFFFFFFFF TPAL Tamper pin active level 1 1 TPE Tamper pin enable 0 1 CAN1 Controller area network CAN1 0x40006400 0x0 0x400 registers n USB_HP_CAN1_TX CAN1 TX interrupts 35 USB_LP_CAN1_RX0 CAN1 RX0 interrupts 36 CAN1_RX1 CAN1 RX1 interrupt 37 CAN1_SCE CAN1 SCE interrupt 38 BTIMR BTIMR CAN bit timing register 0x1C 32 read-write n 0x1230000 0xFFFFFFFF BRP Baud rate prescaler 0 10 read-write LBKM Loop back mode (debug) 30 1 read-write SILM Silent mode (debug) 31 1 read-write SJW Resynchronization jump width 24 2 read-write TS1 Time segment 1 16 4 read-write TS2 Time segment 2 20 3 read-write CTLR CTLR CAN Master control register 0x0 32 read-write n 0x10002 0xFFFFFFFF ABOM Automatic bus-off management 6 1 read-write AWUM Automatic wakeup mode 5 1 read-write DBF Debug freeze 16 1 read-write INRQ Initialization request 0 1 read-write NART No automatic retransmission 4 1 read-write RESET Software master reset 15 1 read-write RFLM Receive FIFO locked mode 3 1 read-write SLEEP Sleep mode request 1 1 read-write TTCM Time triggered communication mode 7 1 read-write TXFP Transmit FIFO priority 2 1 read-write ERRSR ERRSR CAN error status register 0x18 32 n 0x0 0xFFFFFFFF BOFF Bus-off flag 2 1 read-only EPVF Error passive flag 1 1 read-only EWGF Error warning flag 0 1 read-only LEC Last error code 4 3 read-write REC Receive error counter 24 8 read-only TEC Least significant byte of the 9-bit transmit error counter 16 8 read-only F0R1 F0R1 Filter bank 0 register 1 0x240 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F0R2 F0R2 Filter bank 0 register 2 0x244 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R1 F10R1 Filter bank 10 register 1 0x290 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R2 F10R2 Filter bank 10 register 2 0x294 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R1 F11R1 Filter bank 11 register 1 0x298 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R2 F11R2 Filter bank 11 register 2 0x29C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R1 F12R1 Filter bank 4 register 1 0x2A0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R2 F12R2 Filter bank 12 register 2 0x2A4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R1 F13R1 Filter bank 13 register 1 0x2A8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R2 F13R2 Filter bank 13 register 2 0x2AC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R1 F14R1 Filter bank 14 register 1 0x2B0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R2 F14R2 Filter bank 14 register 2 0x2B4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R1 F15R1 Filter bank 15 register 1 0x2B8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R2 F15R2 Filter bank 15 register 2 0x2BC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R1 F16R1 Filter bank 16 register 1 0x2C0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R2 F16R2 Filter bank 16 register 2 0x2C4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R1 F17R1 Filter bank 17 register 1 0x2C8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R2 F17R2 Filter bank 17 register 2 0x2CC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R1 F18R1 Filter bank 18 register 1 0x2D0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R2 F18R2 Filter bank 18 register 2 0x2D4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R1 F19R1 Filter bank 19 register 1 0x2D8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R2 F19R2 Filter bank 19 register 2 0x2DC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R1 F1R1 Filter bank 1 register 1 0x248 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R2 F1R2 Filter bank 1 register 2 0x24C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R1 F20R1 Filter bank 20 register 1 0x2E0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R2 F20R2 Filter bank 20 register 2 0x2E4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R1 F21R1 Filter bank 21 register 1 0x2E8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R2 F21R2 Filter bank 21 register 2 0x2EC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R1 F22R1 Filter bank 22 register 1 0x2F0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R2 F22R2 Filter bank 22 register 2 0x2F4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R1 F23R1 Filter bank 23 register 1 0x2F8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R2 F23R2 Filter bank 23 register 2 0x2FC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R1 F24R1 Filter bank 24 register 1 0x300 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R2 F24R2 Filter bank 24 register 2 0x304 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R1 F25R1 Filter bank 25 register 1 0x308 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R2 F25R2 Filter bank 25 register 2 0x30C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R1 F26R1 Filter bank 26 register 1 0x310 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R2 F26R2 Filter bank 26 register 2 0x314 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R1 F27R1 Filter bank 27 register 1 0x318 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R2 F27R2 Filter bank 27 register 2 0x31C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R1 F2R1 Filter bank 2 register 1 0x250 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R2 F2R2 Filter bank 2 register 2 0x254 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R1 F3R1 Filter bank 3 register 1 0x258 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R2 F3R2 Filter bank 3 register 2 0x25C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R1 F4R1 Filter bank 4 register 1 0x260 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R2 F4R2 Filter bank 4 register 2 0x264 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R1 F5R1 Filter bank 5 register 1 0x268 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R2 F5R2 Filter bank 5 register 2 0x26C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R1 F6R1 Filter bank 6 register 1 0x270 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R2 F6R2 Filter bank 6 register 2 0x274 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R1 F7R1 Filter bank 7 register 1 0x278 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R2 F7R2 Filter bank 7 register 2 0x27C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R1 F8R1 Filter bank 8 register 1 0x280 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R2 F8R2 Filter bank 8 register 2 0x284 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R1 F9R1 Filter bank 9 register 1 0x288 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R2 F9R2 Filter bank 9 register 2 0x28C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FAFIFOR FAFIFOR CAN filter FIFO assignment register 0x214 32 read-write n 0x0 0xFFFFFFFF FFA0 Filter FIFO assignment for filter 0 0 1 read-write FFA1 Filter FIFO assignment for filter 1 1 1 read-write FFA10 Filter FIFO assignment for filter 10 10 1 read-write FFA11 Filter FIFO assignment for filter 11 11 1 read-write FFA12 Filter FIFO assignment for filter 12 12 1 read-write FFA13 Filter FIFO assignment for filter 13 13 1 read-write FFA2 Filter FIFO assignment for filter 2 2 1 read-write FFA3 Filter FIFO assignment for filter 3 3 1 read-write FFA4 Filter FIFO assignment for filter 4 4 1 read-write FFA5 Filter FIFO assignment for filter 5 5 1 read-write FFA6 Filter FIFO assignment for filter 6 6 1 read-write FFA7 Filter FIFO assignment for filter 7 7 1 read-write FFA8 Filter FIFO assignment for filter 8 8 1 read-write FFA9 Filter FIFO assignment for filter 9 9 1 read-write FCTLR FCTLR CAN filter master register 0x200 32 read-write n 0x2A1C0E01 0xFFFFFFFF CAN2SB CAN2 start bank 8 6 read-write FINIT Filter init mode 0 1 read-write FMCFGR FMCFGR CAN filter mode register 0x204 32 read-write n 0x0 0xFFFFFFFF FBM0 Filter mode 0 1 read-write FBM1 Filter mode 1 1 read-write FBM10 Filter mode 10 1 read-write FBM11 Filter mode 11 1 read-write FBM12 Filter mode 12 1 read-write FBM13 Filter mode 13 1 read-write FBM2 Filter mode 2 1 read-write FBM3 Filter mode 3 1 read-write FBM4 Filter mode 4 1 read-write FBM5 Filter mode 5 1 read-write FBM6 Filter mode 6 1 read-write FBM7 Filter mode 7 1 read-write FBM8 Filter mode 8 1 read-write FBM9 Filter mode 9 1 read-write FSCFGR FSCFGR CAN filter scale register 0x20C 32 read-write n 0x0 0xFFFFFFFF FSC0 Filter scale configuration 0 1 read-write FSC1 Filter scale configuration 1 1 read-write FSC10 Filter scale configuration 10 1 read-write FSC11 Filter scale configuration 11 1 read-write FSC12 Filter scale configuration 12 1 read-write FSC13 Filter scale configuration 13 1 read-write FSC2 Filter scale configuration 2 1 read-write FSC3 Filter scale configuration 3 1 read-write FSC4 Filter scale configuration 4 1 read-write FSC5 Filter scale configuration 5 1 read-write FSC6 Filter scale configuration 6 1 read-write FSC7 Filter scale configuration 7 1 read-write FSC8 Filter scale configuration 8 1 read-write FSC9 Filter scale configuration 9 1 read-write FWR FWR CAN filter activation register 0x21C 32 read-write n 0x0 0xFFFFFFFF FACT0 Filter active 0 1 read-write FACT1 Filter active 1 1 read-write FACT10 Filter active 10 1 read-write FACT11 Filter active 11 1 read-write FACT12 Filter active 12 1 read-write FACT13 Filter active 13 1 read-write FACT2 Filter active 2 1 read-write FACT3 Filter active 3 1 read-write FACT4 Filter active 4 1 read-write FACT5 Filter active 5 1 read-write FACT6 Filter active 6 1 read-write FACT7 Filter active 7 1 read-write FACT8 Filter active 8 1 read-write FACT9 Filter active 9 1 read-write INTENR INTENR CAN interrupt enable register 0x14 32 read-write n 0x0 0xFFFFFFFF BOFIE Bus-off interrupt enable 10 1 read-write EPVIE Error passive interrupt enable 9 1 read-write ERRIE Error interrupt enable 15 1 read-write EWGIE Error warning interrupt enable 8 1 read-write FFIE0 FIFO full interrupt enable 2 1 read-write FFIE1 FIFO full interrupt enable 5 1 read-write FMPIE0 FIFO message pending interrupt enable 1 1 read-write FMPIE1 FIFO message pending interrupt enable 4 1 read-write FOVIE0 FIFO overrun interrupt enable 3 1 read-write FOVIE1 FIFO overrun interrupt enable 6 1 read-write LECIE Last error code interrupt enable 11 1 read-write SLKIE Sleep interrupt enable 17 1 read-write TMEIE Transmit mailbox empty interrupt enable 0 1 read-write WKUIE Wakeup interrupt enable 16 1 read-write RFIFO0 RFIFO0 CAN receive FIFO 0 register 0xC 32 n 0x0 0xFFFFFFFF FMP0 FIFO 0 message pending 0 2 read-only FOVR0 FIFO 0 overrun 4 1 read-write FULL0 FIFO 0 full 3 1 read-write RFOM0 Release FIFO 0 output mailbox 5 1 read-write RFIFO1 RFIFO1 CAN receive FIFO 1 register 0x10 32 n 0x0 0xFFFFFFFF FMP1 FIFO 1 message pending 0 2 read-only FOVR1 FIFO 1 overrun 4 1 read-write FULL1 FIFO 1 full 3 1 read-write RFOM1 Release FIFO 1 output mailbox 5 1 read-write RXMDHR0 RXMDHR0 CAN receive FIFO mailbox data high register 0x1BC 32 read-only n 0x0 0xFFFFFFFF DATA4 DATA4 0 8 read-only DATA5 DATA5 8 8 read-only DATA6 DATA6 16 8 read-only DATA7 DATA7 24 8 read-only RXMDHR1 RXMDHR1 CAN receive FIFO mailbox data high register 0x1CC 32 read-only n 0x0 0xFFFFFFFF DATA4 DATA4 0 8 read-only DATA5 DATA5 8 8 read-only DATA6 DATA6 16 8 read-only DATA7 DATA7 24 8 read-only RXMDLR0 RXMDLR0 CAN receive FIFO mailbox data low register 0x1B8 32 read-only n 0x0 0xFFFFFFFF DATA0 Data Byte 0 0 8 read-only DATA1 Data Byte 1 8 8 read-only DATA2 Data Byte 2 16 8 read-only DATA3 Data Byte 3 24 8 read-only RXMDLR1 RXMDLR1 CAN receive FIFO mailbox data low register 0x1C8 32 read-only n 0x0 0xFFFFFFFF DATA0 Data Byte 0 0 8 read-only DATA1 Data Byte 1 8 8 read-only DATA2 Data Byte 2 16 8 read-only DATA3 Data Byte 3 24 8 read-only RXMDTR0 RXMDTR0 CAN receive FIFO mailbox data length control and time stamp register 0x1B4 32 read-only n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-only FMI Filter match index 8 8 read-only TIME Message time stamp 16 16 read-only RXMDTR1 RXMDTR1 CAN receive FIFO mailbox data length control and time stamp register 0x1C4 32 read-only n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-only FMI Filter match index 8 8 read-only TIME Message time stamp 16 16 read-only RXMIR0 RXMIR0 CAN receive FIFO mailbox identifier register 0x1B0 32 read-only n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-only IDE Identifier extension 2 1 read-only RTR Remote transmission request 1 1 read-only STID Standard identifier 21 11 read-only RXMIR1 RXMIR1 CAN receive FIFO mailbox identifier register 0x1C0 32 read-only n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-only IDE Identifier extension 2 1 read-only RTR Remote transmission request 1 1 read-only STID Standard identifier 21 11 read-only STATR STATR CAN master status register 0x4 32 n 0xC02 0xFFFFFFFF ERRI Error interrupt 2 1 read-write INAK Initialization acknowledge 0 1 read-only RX Rx signal 11 1 read-only RXM Receive mode 9 1 read-only SAMP Last sample point 10 1 read-only SLAK Sleep acknowledge 1 1 read-only SLAKI Sleep acknowledge interrupt 4 1 read-write TXM Transmit mode 8 1 read-only WKUI Wakeup interrupt 3 1 read-write TSTATR TSTATR CAN transmit status register 0x8 32 n 0x1C000000 0xFFFFFFFF ABRQ0 Abort request for mailbox0 7 1 read-write ABRQ1 Abort request for mailbox 1 15 1 read-write ABRQ2 Abort request for mailbox 2 23 1 read-write ALST0 Arbitration lost for mailbox0 2 1 read-write ALST1 Arbitration lost for mailbox1 10 1 read-write ALST2 Arbitration lost for mailbox 2 18 1 read-write CODE Mailbox code 24 2 read-only LOW0 Lowest priority flag for mailbox 0 29 1 read-only LOW1 Lowest priority flag for mailbox 1 30 1 read-only LOW2 Lowest priority flag for mailbox 2 31 1 read-only RQCP0 Request completed mailbox0 0 1 read-write RQCP1 Request completed mailbox1 8 1 read-write RQCP2 Request completed mailbox2 16 1 read-write TERR0 Transmission error of mailbox0 3 1 read-write TERR1 Transmission error of mailbox1 11 1 read-write TERR2 Transmission error of mailbox 2 19 1 read-write TME0 Transmit mailbox 0 empty 26 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TXOK0 Transmission OK of mailbox0 1 1 read-write TXOK1 Transmission OK of mailbox1 9 1 read-write TXOK2 Transmission OK of mailbox 2 17 1 read-write TXMDHR0 TXMDHR0 CAN mailbox data high register 0x18C 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDHR1 TXMDHR1 CAN mailbox data high register 0x19C 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDHR2 TXMDHR2 CAN mailbox data high register 0x1AC 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDLR0 TXMDLR0 CAN mailbox data low register 0x188 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDLR1 TXMDLR1 CAN mailbox data low register 0x198 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDLR2 TXMDLR2 CAN mailbox data low register 0x1A8 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDTR0 TXMDTR0 CAN mailbox data length control and time stamp register 0x184 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMDTR1 TXMDTR1 CAN mailbox data length control and time stamp register 0x194 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMDTR2 TXMDTR2 CAN mailbox data length control and time stamp register 0x1A4 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMIR0 TXMIR0 CAN TX mailbox identifier register 0x180 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write TXMIR1 TXMIR1 CAN TX mailbox identifier register 0x190 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write TXMIR2 TXMIR2 CAN TX mailbox identifier register 0x1A0 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write CAN2 Controller area network CAN1 0x40006800 0x0 0x400 registers n CAN2_TX CAN2 TX interrupts 79 CAN2_RX0 CAN2 RX0 interrupts 80 CAN2_RX1 CAN2 RX1 interrupt 81 CAN2_SCE CAN2 SCE interrupt 82 BTIMR BTIMR CAN bit timing register 0x1C 32 read-write n 0x1230000 0xFFFFFFFF BRP Baud rate prescaler 0 10 read-write LBKM Loop back mode (debug) 30 1 read-write SILM Silent mode (debug) 31 1 read-write SJW Resynchronization jump width 24 2 read-write TS1 Time segment 1 16 4 read-write TS2 Time segment 2 20 3 read-write CTLR CTLR CAN Master control register 0x0 32 read-write n 0x10002 0xFFFFFFFF ABOM Automatic bus-off management 6 1 read-write AWUM Automatic wakeup mode 5 1 read-write DBF Debug freeze 16 1 read-write INRQ Initialization request 0 1 read-write NART No automatic retransmission 4 1 read-write RESET Software master reset 15 1 read-write RFLM Receive FIFO locked mode 3 1 read-write SLEEP Sleep mode request 1 1 read-write TTCM Time triggered communication mode 7 1 read-write TXFP Transmit FIFO priority 2 1 read-write ERRSR ERRSR CAN error status register 0x18 32 n 0x0 0xFFFFFFFF BOFF Bus-off flag 2 1 read-only EPVF Error passive flag 1 1 read-only EWGF Error warning flag 0 1 read-only LEC Last error code 4 3 read-write REC Receive error counter 24 8 read-only TEC Least significant byte of the 9-bit transmit error counter 16 8 read-only F0R1 F0R1 Filter bank 0 register 1 0x240 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F0R2 F0R2 Filter bank 0 register 2 0x244 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R1 F10R1 Filter bank 10 register 1 0x290 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F10R2 F10R2 Filter bank 10 register 2 0x294 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R1 F11R1 Filter bank 11 register 1 0x298 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F11R2 F11R2 Filter bank 11 register 2 0x29C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R1 F12R1 Filter bank 4 register 1 0x2A0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F12R2 F12R2 Filter bank 12 register 2 0x2A4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R1 F13R1 Filter bank 13 register 1 0x2A8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F13R2 F13R2 Filter bank 13 register 2 0x2AC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R1 F14R1 Filter bank 14 register 1 0x2B0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F14R2 F14R2 Filter bank 14 register 2 0x2B4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R1 F15R1 Filter bank 15 register 1 0x2B8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F15R2 F15R2 Filter bank 15 register 2 0x2BC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R1 F16R1 Filter bank 16 register 1 0x2C0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F16R2 F16R2 Filter bank 16 register 2 0x2C4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R1 F17R1 Filter bank 17 register 1 0x2C8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F17R2 F17R2 Filter bank 17 register 2 0x2CC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R1 F18R1 Filter bank 18 register 1 0x2D0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F18R2 F18R2 Filter bank 18 register 2 0x2D4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R1 F19R1 Filter bank 19 register 1 0x2D8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F19R2 F19R2 Filter bank 19 register 2 0x2DC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R1 F1R1 Filter bank 1 register 1 0x248 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F1R2 F1R2 Filter bank 1 register 2 0x24C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R1 F20R1 Filter bank 20 register 1 0x2E0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F20R2 F20R2 Filter bank 20 register 2 0x2E4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R1 F21R1 Filter bank 21 register 1 0x2E8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F21R2 F21R2 Filter bank 21 register 2 0x2EC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R1 F22R1 Filter bank 22 register 1 0x2F0 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F22R2 F22R2 Filter bank 22 register 2 0x2F4 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R1 F23R1 Filter bank 23 register 1 0x2F8 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F23R2 F23R2 Filter bank 23 register 2 0x2FC 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R1 F24R1 Filter bank 24 register 1 0x300 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F24R2 F24R2 Filter bank 24 register 2 0x304 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R1 F25R1 Filter bank 25 register 1 0x308 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F25R2 F25R2 Filter bank 25 register 2 0x30C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R1 F26R1 Filter bank 26 register 1 0x310 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F26R2 F26R2 Filter bank 26 register 2 0x314 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R1 F27R1 Filter bank 27 register 1 0x318 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F27R2 F27R2 Filter bank 27 register 2 0x31C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R1 F2R1 Filter bank 2 register 1 0x250 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F2R2 F2R2 Filter bank 2 register 2 0x254 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R1 F3R1 Filter bank 3 register 1 0x258 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F3R2 F3R2 Filter bank 3 register 2 0x25C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R1 F4R1 Filter bank 4 register 1 0x260 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F4R2 F4R2 Filter bank 4 register 2 0x264 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R1 F5R1 Filter bank 5 register 1 0x268 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F5R2 F5R2 Filter bank 5 register 2 0x26C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R1 F6R1 Filter bank 6 register 1 0x270 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F6R2 F6R2 Filter bank 6 register 2 0x274 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R1 F7R1 Filter bank 7 register 1 0x278 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F7R2 F7R2 Filter bank 7 register 2 0x27C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R1 F8R1 Filter bank 8 register 1 0x280 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F8R2 F8R2 Filter bank 8 register 2 0x284 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R1 F9R1 Filter bank 9 register 1 0x288 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 F9R2 F9R2 Filter bank 9 register 2 0x28C 32 read-write n 0x0 0xFFFFFFFF FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB2 Filter bits 2 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB3 Filter bits 3 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FAFIFOR FAFIFOR CAN filter FIFO assignment register 0x214 32 read-write n 0x0 0xFFFFFFFF FFA0 Filter FIFO assignment for filter 0 0 1 read-write FFA1 Filter FIFO assignment for filter 1 1 1 read-write FFA10 Filter FIFO assignment for filter 10 10 1 read-write FFA11 Filter FIFO assignment for filter 11 11 1 read-write FFA12 Filter FIFO assignment for filter 12 12 1 read-write FFA13 Filter FIFO assignment for filter 13 13 1 read-write FFA2 Filter FIFO assignment for filter 2 2 1 read-write FFA3 Filter FIFO assignment for filter 3 3 1 read-write FFA4 Filter FIFO assignment for filter 4 4 1 read-write FFA5 Filter FIFO assignment for filter 5 5 1 read-write FFA6 Filter FIFO assignment for filter 6 6 1 read-write FFA7 Filter FIFO assignment for filter 7 7 1 read-write FFA8 Filter FIFO assignment for filter 8 8 1 read-write FFA9 Filter FIFO assignment for filter 9 9 1 read-write FCTLR FCTLR CAN filter master register 0x200 32 read-write n 0x2A1C0E01 0xFFFFFFFF CAN2SB CAN2 start bank 8 6 read-write FINIT Filter init mode 0 1 read-write FMCFGR FMCFGR CAN filter mode register 0x204 32 read-write n 0x0 0xFFFFFFFF FBM0 Filter mode 0 1 read-write FBM1 Filter mode 1 1 read-write FBM10 Filter mode 10 1 read-write FBM11 Filter mode 11 1 read-write FBM12 Filter mode 12 1 read-write FBM13 Filter mode 13 1 read-write FBM2 Filter mode 2 1 read-write FBM3 Filter mode 3 1 read-write FBM4 Filter mode 4 1 read-write FBM5 Filter mode 5 1 read-write FBM6 Filter mode 6 1 read-write FBM7 Filter mode 7 1 read-write FBM8 Filter mode 8 1 read-write FBM9 Filter mode 9 1 read-write FSCFGR FSCFGR CAN filter scale register 0x20C 32 read-write n 0x0 0xFFFFFFFF FSC0 Filter scale configuration 0 1 read-write FSC1 Filter scale configuration 1 1 read-write FSC10 Filter scale configuration 10 1 read-write FSC11 Filter scale configuration 11 1 read-write FSC12 Filter scale configuration 12 1 read-write FSC13 Filter scale configuration 13 1 read-write FSC2 Filter scale configuration 2 1 read-write FSC3 Filter scale configuration 3 1 read-write FSC4 Filter scale configuration 4 1 read-write FSC5 Filter scale configuration 5 1 read-write FSC6 Filter scale configuration 6 1 read-write FSC7 Filter scale configuration 7 1 read-write FSC8 Filter scale configuration 8 1 read-write FSC9 Filter scale configuration 9 1 read-write FWR FWR CAN filter activation register 0x21C 32 read-write n 0x0 0xFFFFFFFF FACT0 Filter active 0 1 read-write FACT1 Filter active 1 1 read-write FACT10 Filter active 10 1 read-write FACT11 Filter active 11 1 read-write FACT12 Filter active 12 1 read-write FACT13 Filter active 13 1 read-write FACT2 Filter active 2 1 read-write FACT3 Filter active 3 1 read-write FACT4 Filter active 4 1 read-write FACT5 Filter active 5 1 read-write FACT6 Filter active 6 1 read-write FACT7 Filter active 7 1 read-write FACT8 Filter active 8 1 read-write FACT9 Filter active 9 1 read-write INTENR INTENR CAN interrupt enable register 0x14 32 read-write n 0x0 0xFFFFFFFF BOFIE Bus-off interrupt enable 10 1 read-write EPVIE Error passive interrupt enable 9 1 read-write ERRIE Error interrupt enable 15 1 read-write EWGIE Error warning interrupt enable 8 1 read-write FFIE0 FIFO full interrupt enable 2 1 read-write FFIE1 FIFO full interrupt enable 5 1 read-write FMPIE0 FIFO message pending interrupt enable 1 1 read-write FMPIE1 FIFO message pending interrupt enable 4 1 read-write FOVIE0 FIFO overrun interrupt enable 3 1 read-write FOVIE1 FIFO overrun interrupt enable 6 1 read-write LECIE Last error code interrupt enable 11 1 read-write SLKIE Sleep interrupt enable 17 1 read-write TMEIE Transmit mailbox empty interrupt enable 0 1 read-write WKUIE Wakeup interrupt enable 16 1 read-write RFIFO0 RFIFO0 CAN receive FIFO 0 register 0xC 32 n 0x0 0xFFFFFFFF FMP0 FIFO 0 message pending 0 2 read-only FOVR0 FIFO 0 overrun 4 1 read-write FULL0 FIFO 0 full 3 1 read-write RFOM0 Release FIFO 0 output mailbox 5 1 read-write RFIFO1 RFIFO1 CAN receive FIFO 1 register 0x10 32 n 0x0 0xFFFFFFFF FMP1 FIFO 1 message pending 0 2 read-only FOVR1 FIFO 1 overrun 4 1 read-write FULL1 FIFO 1 full 3 1 read-write RFOM1 Release FIFO 1 output mailbox 5 1 read-write RXMDHR0 RXMDHR0 CAN receive FIFO mailbox data high register 0x1BC 32 read-only n 0x0 0xFFFFFFFF DATA4 DATA4 0 8 read-only DATA5 DATA5 8 8 read-only DATA6 DATA6 16 8 read-only DATA7 DATA7 24 8 read-only RXMDHR1 RXMDHR1 CAN receive FIFO mailbox data high register 0x1CC 32 read-only n 0x0 0xFFFFFFFF DATA4 DATA4 0 8 read-only DATA5 DATA5 8 8 read-only DATA6 DATA6 16 8 read-only DATA7 DATA7 24 8 read-only RXMDLR0 RXMDLR0 CAN receive FIFO mailbox data low register 0x1B8 32 read-only n 0x0 0xFFFFFFFF DATA0 Data Byte 0 0 8 read-only DATA1 Data Byte 1 8 8 read-only DATA2 Data Byte 2 16 8 read-only DATA3 Data Byte 3 24 8 read-only RXMDLR1 RXMDLR1 CAN receive FIFO mailbox data low register 0x1C8 32 read-only n 0x0 0xFFFFFFFF DATA0 Data Byte 0 0 8 read-only DATA1 Data Byte 1 8 8 read-only DATA2 Data Byte 2 16 8 read-only DATA3 Data Byte 3 24 8 read-only RXMDTR0 RXMDTR0 CAN receive FIFO mailbox data length control and time stamp register 0x1B4 32 read-only n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-only FMI Filter match index 8 8 read-only TIME Message time stamp 16 16 read-only RXMDTR1 RXMDTR1 CAN receive FIFO mailbox data length control and time stamp register 0x1C4 32 read-only n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-only FMI Filter match index 8 8 read-only TIME Message time stamp 16 16 read-only RXMIR0 RXMIR0 CAN receive FIFO mailbox identifier register 0x1B0 32 read-only n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-only IDE Identifier extension 2 1 read-only RTR Remote transmission request 1 1 read-only STID Standard identifier 21 11 read-only RXMIR1 RXMIR1 CAN receive FIFO mailbox identifier register 0x1C0 32 read-only n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-only IDE Identifier extension 2 1 read-only RTR Remote transmission request 1 1 read-only STID Standard identifier 21 11 read-only STATR STATR CAN master status register 0x4 32 n 0xC02 0xFFFFFFFF ERRI Error interrupt 2 1 read-write INAK Initialization acknowledge 0 1 read-only RX Rx signal 11 1 read-only RXM Receive mode 9 1 read-only SAMP Last sample point 10 1 read-only SLAK Sleep acknowledge 1 1 read-only SLAKI Sleep acknowledge interrupt 4 1 read-write TXM Transmit mode 8 1 read-only WKUI Wakeup interrupt 3 1 read-write TSTATR TSTATR CAN transmit status register 0x8 32 n 0x1C000000 0xFFFFFFFF ABRQ0 Abort request for mailbox0 7 1 read-write ABRQ1 Abort request for mailbox 1 15 1 read-write ABRQ2 Abort request for mailbox 2 23 1 read-write ALST0 Arbitration lost for mailbox0 2 1 read-write ALST1 Arbitration lost for mailbox1 10 1 read-write ALST2 Arbitration lost for mailbox 2 18 1 read-write CODE Mailbox code 24 2 read-only LOW0 Lowest priority flag for mailbox 0 29 1 read-only LOW1 Lowest priority flag for mailbox 1 30 1 read-only LOW2 Lowest priority flag for mailbox 2 31 1 read-only RQCP0 Request completed mailbox0 0 1 read-write RQCP1 Request completed mailbox1 8 1 read-write RQCP2 Request completed mailbox2 16 1 read-write TERR0 Transmission error of mailbox0 3 1 read-write TERR1 Transmission error of mailbox1 11 1 read-write TERR2 Transmission error of mailbox 2 19 1 read-write TME0 Transmit mailbox 0 empty 26 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TXOK0 Transmission OK of mailbox0 1 1 read-write TXOK1 Transmission OK of mailbox1 9 1 read-write TXOK2 Transmission OK of mailbox 2 17 1 read-write TXMDHR0 TXMDHR0 CAN mailbox data high register 0x18C 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDHR1 TXMDHR1 CAN mailbox data high register 0x19C 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDHR2 TXMDHR2 CAN mailbox data high register 0x1AC 32 read-write n 0x0 0xFFFFFFFF DATA4 Data byte 4 0 8 read-write DATA5 Data byte 5 8 8 read-write DATA6 Data byte 6 16 8 read-write DATA7 Data byte 7 24 8 read-write TXMDLR0 TXMDLR0 CAN mailbox data low register 0x188 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDLR1 TXMDLR1 CAN mailbox data low register 0x198 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDLR2 TXMDLR2 CAN mailbox data low register 0x1A8 32 read-write n 0x0 0xFFFFFFFF DATA0 Data byte 0 0 8 read-write DATA1 Data byte 1 8 8 read-write DATA2 Data byte 2 16 8 read-write DATA3 Data byte 3 24 8 read-write TXMDTR0 TXMDTR0 CAN mailbox data length control and time stamp register 0x184 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMDTR1 TXMDTR1 CAN mailbox data length control and time stamp register 0x194 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMDTR2 TXMDTR2 CAN mailbox data length control and time stamp register 0x1A4 32 read-write n 0x0 0xFFFFFFFF DLC Data length code 0 4 read-write TGT Transmit global time 8 1 read-write TIME Message time stamp 16 16 read-write TXMIR0 TXMIR0 CAN TX mailbox identifier register 0x180 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write TXMIR1 TXMIR1 CAN TX mailbox identifier register 0x190 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write TXMIR2 TXMIR2 CAN TX mailbox identifier register 0x1A0 32 read-write n 0x0 0xFFFFFFFF EXID extended identifier 3 18 read-write IDE Identifier extension 2 1 read-write RTR Remote transmission request 1 1 read-write STID Standard identifier 21 11 read-write TXRQ Transmit mailbox request 0 1 read-write CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers n CTLR CTLR Control register 0x8 32 write-only n 0x0 0xFFFFFFFF RESET Reset bit 0 1 DATAR DATAR Data register 0x0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DR Data Register 0 32 IDATAR IDATAR Independent Data register 0x4 32 read-write n 0x0 0xFFFFFFFF IDR Independent Data register 0 8 DAC Digital to analog converter DAC 0x40007400 0x0 0x400 registers n CTLR CTLR Control register (DAC_CR) 0x0 32 read-write n 0x0 0xFFFFFFFF BOFF1 DAC channel1 output buffer disable 1 1 BOFF2 DAC channel2 output buffer disable 17 1 DMAEN1 DAC channel1 DMA enable 12 1 DMAEN2 DAC channel2 DMA enable 28 1 EN1 DAC channel1 enable 0 1 EN2 DAC channel2 enable 16 1 MAMP1 DAC channel1 mask/amplitude selector 8 4 MAMP2 DAC channel2 mask/amplitude selector 24 4 TEN1 DAC channel1 trigger enable 2 1 TEN2 DAC channel2 trigger enable 18 1 TSEL1 DAC channel1 trigger selection 3 3 TSEL2 DAC channel2 trigger selection 19 3 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 DOR1 DOR1 DAC channel1 data output register (DAC_DOR1) 0x2C 32 read-only n 0x0 0xFFFFFFFF DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 DAC channel2 data output register (DAC_DOR2) 0x30 32 read-only n 0x0 0xFFFFFFFF DACC2DOR DAC channel2 data output 0 12 L12BDHR1 L12BDHR1 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) 0xC 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 12-bit left-aligned data 4 12 L12BDHR2 L12BDHR2 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) 0x18 32 read-write n 0x0 0xFFFFFFFF DACC2DHR DAC channel2 12-bit left-aligned data 4 12 LD12BDHR LD12BDHR DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved 0x24 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DACC2DHR DAC channel2 12-bit right-aligned data 20 12 R12BDHR1 R12BDHR1 DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) 0x8 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 12-bit right-aligned data 0 12 R12BDHR2 R12BDHR2 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) 0x14 32 read-write n 0x0 0xFFFFFFFF DACC2DHR DAC channel2 12-bit right-aligned data 0 12 R8BDHR1 R8BDHR1 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) 0x10 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 8-bit right-aligned data 0 8 R8BDHR2 R8BDHR2 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) 0x1C 32 read-write n 0x0 0xFFFFFFFF DACC2DHR DAC channel2 8-bit right-aligned data 0 8 RD12BDHR RD12BDHR Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved 0x20 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 RD8BDHR RD8BDHR DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved 0x28 32 read-write n 0x0 0xFFFFFFFF DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 SWTR SWTR DAC software trigger register (DAC_SWTRIGR) 0x4 32 write-only n 0x0 0xFFFFFFFF SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG2 DAC channel2 software trigger 1 1 DBG Debug support DBG 0xE000D000 0x0 0x400 registers n CFGR1 CFGR1 DBGMCU_CFGR1 0x0 32 read-write n 0x0 0xFFFFFFFF DEG_I2C1 DEG_I2C1 2 1 DEG_I2C2 DEG_I2C2 3 1 DEG_IWDG DEG_IWDG 0 1 DEG_TIM1 DEG_TIM1 4 1 DEG_TIM2 DEG_TIM2 5 1 DEG_TIM3 DEG_TIM3 6 1 DEG_TIM4 DEG_TIM4 7 1 DEG_WWDG DEG_WWDG 1 1 CFGR2 CFGR2 DBGMCU_CFGR2 0x4 32 read-write n 0x0 0xFFFFFFFF DBG_SLEEP DBG_SLEEP 0 1 DBG_STANDBY DBG_STANDBY 2 1 DBG_STOP DBG_STOP 1 1 DMA1 DMA1 controller DMA1 0x40020000 0x0 0x400 registers n DMA1_Channel1 DMA1 Channel1 global interrupt 27 DMA1_Channel2 DMA1 Channel2 global interrupt 28 DMA1_Channel3 DMA1 Channel3 global interrupt 29 DMA1_Channel4 DMA1 Channel4 global interrupt 30 DMA1_Channel5 DMA1 Channel5 global interrupt 31 DMA1_Channel6 DMA1 Channel6 global interrupt 32 DMA1_Channel7 DMA1 Channel7 global interrupt 33 CFGR1 CFGR DMA channel configuration register (DMA_CFGR) 0x8 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR2 CFGR2 DMA channel configuration register (DMA_CFGR) 0x1C 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR3 CFGR3 DMA channel configuration register (DMA_CFGR) 0x30 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR4 CFGR4 DMA channel configuration register (DMA_CFGR) 0x44 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR5 CFGR5 DMA channel configuration register (DMA_CFGR) 0x58 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR6 CFGR6 DMA channel configuration register (DMA_CFGR) 0x6C 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR7 CFGR7 DMA channel configuration register (DMA_CFGR) 0x80 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CNTR1 CNTR DMA channel 1 number of data register 0xC 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR2 CNTR2 DMA channel 2 number of data register 0x20 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR3 CNTR3 DMA channel 3 number of data register 0x34 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR4 CNTR4 DMA channel 4 number of data register 0x48 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR5 CNTR5 DMA channel 5 number of data register 0x5C 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR6 CNTR6 DMA channel 6 number of data register 0x70 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR7 CNTR7 DMA channel 7 number of data register 0x84 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 INTFCR INTFCR DMA interrupt flag clear register (DMA_INTFCR) 0x4 32 write-only n 0x0 0xFFFFFFFF CGIF1 Channel 1 Global interrupt clear 0 1 CGIF2 Channel 2 Global interrupt clear 4 1 CGIF3 Channel 3 Global interrupt clear 8 1 CGIF4 Channel 4 Global interrupt clear 12 1 CGIF5 Channel 5 Global interrupt clear 16 1 CGIF6 Channel 6 Global interrupt clear 20 1 CGIF7 Channel 7 Global interrupt clear 24 1 CHTIF1 Channel 1 Half Transfer clear 2 1 CHTIF2 Channel 2 Half Transfer clear 6 1 CHTIF3 Channel 3 Half Transfer clear 10 1 CHTIF4 Channel 4 Half Transfer clear 14 1 CHTIF5 Channel 5 Half Transfer clear 18 1 CHTIF6 Channel 6 Half Transfer clear 22 1 CHTIF7 Channel 7 Half Transfer clear 26 1 CTCIF1 Channel 1 Transfer Complete clear 1 1 CTCIF2 Channel 2 Transfer Complete clear 5 1 CTCIF3 Channel 3 Transfer Complete clear 9 1 CTCIF4 Channel 4 Transfer Complete clear 13 1 CTCIF5 Channel 5 Transfer Complete clear 17 1 CTCIF6 Channel 6 Transfer Complete clear 21 1 CTCIF7 Channel 7 Transfer Complete clear 25 1 CTEIF1 Channel 1 Transfer Error clear 3 1 CTEIF2 Channel 2 Transfer Error clear 7 1 CTEIF3 Channel 3 Transfer Error clear 11 1 CTEIF4 Channel 4 Transfer Error clear 15 1 CTEIF5 Channel 5 Transfer Error clear 19 1 CTEIF6 Channel 6 Transfer Error clear 23 1 CTEIF7 Channel 7 Transfer Error clear 27 1 INTFR INTFR DMA interrupt status register (DMA_INTFR) 0x0 32 read-only n 0x0 0xFFFFFFFF GIF1 Channel 1 Global interrupt flag 0 1 GIF2 Channel 2 Global interrupt flag 4 1 GIF3 Channel 3 Global interrupt flag 8 1 GIF4 Channel 4 Global interrupt flag 12 1 GIF5 Channel 5 Global interrupt flag 16 1 GIF6 Channel 6 Global interrupt flag 20 1 GIF7 Channel 7 Global interrupt flag 24 1 HTIF1 Channel 1 Half Transfer Complete flag 2 1 HTIF2 Channel 2 Half Transfer Complete flag 6 1 HTIF3 Channel 3 Half Transfer Complete flag 10 1 HTIF4 Channel 4 Half Transfer Complete flag 14 1 HTIF5 Channel 5 Half Transfer Complete flag 18 1 HTIF6 Channel 6 Half Transfer Complete flag 22 1 HTIF7 Channel 7 Half Transfer Complete flag 26 1 TCIF1 Channel 1 Transfer Complete flag 1 1 TCIF2 Channel 2 Transfer Complete flag 5 1 TCIF3 Channel 3 Transfer Complete flag 9 1 TCIF4 Channel 4 Transfer Complete flag 13 1 TCIF5 Channel 5 Transfer Complete flag 17 1 TCIF6 Channel 6 Transfer Complete flag 21 1 TCIF7 Channel 7 Transfer Complete flag 25 1 TEIF1 Channel 1 Transfer Error flag 3 1 TEIF2 Channel 2 Transfer Error flag 7 1 TEIF3 Channel 3 Transfer Error flag 11 1 TEIF4 Channel 4 Transfer Error flag 15 1 TEIF5 Channel 5 Transfer Error flag 19 1 TEIF6 Channel 6 Transfer Error flag 23 1 TEIF7 Channel 7 Transfer Error flag 27 1 MADDR1 MADDR1 DMA channel 1 memory address register 0x14 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR2 MADDR2 DMA channel 2 memory address register 0x28 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR3 MADDR3 DMA channel 3 memory address register 0x3C 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR4 MADDR4 DMA channel 4 memory address register 0x50 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR5 MADDR5 DMA channel 5 memory address register 0x64 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR6 MADDR6 DMA channel 6 memory address register 0x78 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR7 MADDR7 DMA channel 7 memory address register 0x8C 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 PADDR1 PADDR1 DMA channel 1 peripheral address register 0x10 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR2 PADDR2 DMA channel 2 peripheral address register 0x24 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR3 PADDR3 DMA channel 3 peripheral address register 0x38 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR4 PADDR4 DMA channel 4 peripheral address register 0x4C 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR5 PADDR5 DMA channel 5 peripheral address register 0x60 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR6 PADDR6 DMA channel 6 peripheral address register 0x74 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR7 PADDR7 DMA channel 7 peripheral address register 0x88 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 DMA2 DMA2 controller DMA2 0x40020400 0x0 0x400 registers n DMA2_Channel1 DMA2 Channel1 global interrupt 72 DMA2_Channel2 DMA2 Channel2 global interrupt 73 DMA2_Channel3 DMA2 Channel3 global interrupt 74 DMA2_Channel4 DMA2 Channel4 global interrupt 75 DMA2_Channel5 DMA2 Channel5 global interrupt 76 DMA2_Channel6 DMA2 Channel6 global interrupt 98 DMA2_Channel7 DMA2 Channel7 global interrupt 99 DMA2_Channel8 DMA2 Channel8 global interrupt 100 DMA2_Channel9 DMA2 Channel9 global interrupt 101 DMA2_Channel10 DMA2 Channel10 global interrupt 102 DMA2_Channel11 DMA2 Channel11 global interrupt 103 CFGR1 CFGR1 DMA channel configuration register (DMA_CFGR) 0x8 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR10 CFGR10 DMA channel configuration register (DMA_CFGR) used in ch32v30x_D8/D8C 0xB0 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR11 CFGR11 DMA channel configuration register (DMA_CFGR) used in ch32v30x_D8/D8C 0xC0 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR2 CFGR2 DMA channel configuration register (DMA_CFGR) 0x1C 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR3 CFGR3 DMA channel configuration register (DMA_CFGR) 0x30 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR4 CFGR4 DMA channel configuration register (DMA_CFGR) 0x44 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR5 CFGR5 DMA channel configuration register (DMA_CFGR) 0x58 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR6 CFGR6 DMA channel configuration register (DMA_CFGR) 0x6C 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR7 CFGR7 DMA channel configuration register (DMA_CFGR) 0x80 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR8 CFGR8 DMA channel configuration register (DMA_CFGR) used in ch32v30x_D8/D8C 0x90 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CFGR9 CFGR9 DMA channel configuration register (DMA_CFGR) used in ch32v30x_D8/D8C 0xA0 32 read-write n 0x0 0xFFFFFFFF CIRC Circular mode 5 1 DIR Data transfer direction 4 1 EN Channel enable 0 1 HTIE Half Transfer interrupt enable 2 1 MEM2MEM Memory to memory mode 14 1 MINC Memory increment mode 7 1 MSIZE Memory size 10 2 PINC Peripheral increment mode 6 1 PL Channel Priority level 12 2 PSIZE Peripheral size 8 2 TCIE Transfer complete interrupt enable 1 1 TEIE Transfer error interrupt enable 3 1 CNTR1 CNTR1 DMA channel 1 number of data register 0xC 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR10 CNTR10 DMA channel 10 number of data register used in ch32v30x_D8/D8C 0xB4 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR11 CNTR11 DMA channel 11 number of data register used in ch32v30x_D8/D8C 0xC4 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR2 CNTR2 DMA channel 2 number of data register 0x20 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR3 CNTR3 DMA channel 3 number of data register 0x34 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR4 CNTR4 DMA channel 4 number of data register 0x48 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR5 CNTR5 DMA channel 5 number of data register 0x5C 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR6 CNTR6 DMA channel 6 number of data register 0x70 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR7 CNTR7 DMA channel 7 number of data register 0x84 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR8 CNTR8 DMA channel 8 number of data register used in ch32v30x_D8/D8C 0x94 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 CNTR9 CNTR9 DMA channel 9 number of data register used in ch32v30x_D8/D8C 0xA4 32 read-write n 0x0 0xFFFFFFFF NDT Number of data to transfer 0 16 EXTEN_INTFCR INTFCR DMA2 EXTEN interrupt flag clear register (DMA_INTFCR)used in ch32v30x_D8/D8C 0xD4 32 write-read n 0x0 0xFFFFFFFF CGIF10 Channel 10 Global interrupt clear 8 1 CGIF11 Channel 11 Global interrupt clear 12 1 CGIF8 Channel 8 Global interrupt clear 0 1 CGIF9 Channel 9 Global interrupt clear 4 1 CHTIF10 Channel 10 Global interrupt clear 10 1 CHTIF11 Channel 11 Global interrupt clear 14 1 CHTIF8 Channel 8 Global interrupt clear 2 1 CHTIF9 Channel 9 Global interrupt clear 6 1 CTCIF10 Channel 10 Global interrupt clear 9 1 CTCIF11 Channel 11 Global interrupt clear 13 1 CTCIF8 Channel 8 Global interrupt clear 1 1 CTCIF9 Channel 9 Global interrupt clear 5 1 CTEIF10 Channel 10 Global interrupt clear 11 1 CTEIF11 Channel 11 Global interrupt clear 15 1 CTEIF8 Channel 8 Global interrupt clear 3 1 CTEIF9 Channel 9 Global interrupt clear 7 1 EXTEN_INTFR INTFR DMA2 EXTEN interrupt status register (DMA_INTFR)used in ch32v30x_D8/D8C 0xD0 32 read-only n 0x0 0xFFFFFFFF GIF10 Channel 10 Global interrupt flag 8 1 GIF11 Channel 11 Global interrupt flag 12 1 GIF8 Channel 8 Global interrupt flag 0 1 GIF9 Channel 9 Global interrupt flag 4 1 HTIF10 Channel 10 Half Transfer Complete flag 10 1 HTIF11 Channel 11 Half Transfer Complete flag 14 1 HTIF8 Channel 8 Half Transfer Complete flag 2 1 HTIF9 Channel 9 Half Transfer Complete flag 6 1 TCIF10 Channel 10 Transfer Complete flag 9 1 TCIF11 Channel 11 Transfer Complete flag 13 1 TCIF8 Channel 8 Transfer Complete flag 1 1 TCIF9 Channel 9 Transfer Complete flag 5 1 TEIF10 Channel 10 Transfer Error flag 11 1 TEIF11 Channel 11 Transfer Error flag 15 1 TEIF8 Channel 8 Transfer Error flag 3 1 TEIF9 Channel 9 Transfer Error flag 7 1 INTFCR INTFCR DMA interrupt flag clear register (DMA_INTFCR) 0x4 32 write-only n 0x0 0xFFFFFFFF CGIF1 Channel 1 Global interrupt clear 0 1 CGIF2 Channel 2 Global interrupt clear 4 1 CGIF3 Channel 3 Global interrupt clear 8 1 CGIF4 Channel 4 Global interrupt clear 12 1 CGIF5 Channel 5 Global interrupt clear 16 1 CGIF6 Channel 6 Global interrupt clear 20 1 CGIF7 Channel 7 Global interrupt clear 24 1 CHTIF1 Channel 1 Half Transfer clear 2 1 CHTIF2 Channel 2 Half Transfer clear 6 1 CHTIF3 Channel 3 Half Transfer clear 10 1 CHTIF4 Channel 4 Half Transfer clear 14 1 CHTIF5 Channel 5 Half Transfer clear 18 1 CHTIF6 Channel 6 Half Transfer clear 22 1 CHTIF7 Channel 7 Half Transfer clear 26 1 CTCIF1 Channel 1 Transfer Complete clear 1 1 CTCIF2 Channel 2 Transfer Complete clear 5 1 CTCIF3 Channel 3 Transfer Complete clear 9 1 CTCIF4 Channel 4 Transfer Complete clear 13 1 CTCIF5 Channel 5 Transfer Complete clear 17 1 CTCIF6 Channel 6 Transfer Complete clear 21 1 CTCIF7 Channel 7 Transfer Complete clear 25 1 CTEIF1 Channel 1 Transfer Error clear 3 1 CTEIF2 Channel 2 Transfer Error clear 7 1 CTEIF3 Channel 3 Transfer Error clear 11 1 CTEIF4 Channel 4 Transfer Error clear 15 1 CTEIF5 Channel 5 Transfer Error clear 19 1 CTEIF6 Channel 6 Transfer Error clear 23 1 CTEIF7 Channel 7 Transfer Error clear 27 1 INTFR INTFR DMA interrupt status register (DMA_INTFR) 0x0 32 read-only n 0x0 0xFFFFFFFF GIF1 Channel 1 Global interrupt flag 0 1 GIF2 Channel 2 Global interrupt flag 4 1 GIF3 Channel 3 Global interrupt flag 8 1 GIF4 Channel 4 Global interrupt flag 12 1 GIF5 Channel 5 Global interrupt flag 16 1 GIF6 Channel 6 Global interrupt flag 20 1 GIF7 Channel 7 Global interrupt flag 24 1 HTIF1 Channel 1 Half Transfer Complete flag 2 1 HTIF2 Channel 2 Half Transfer Complete flag 6 1 HTIF3 Channel 3 Half Transfer Complete flag 10 1 HTIF4 Channel 4 Half Transfer Complete flag 14 1 HTIF5 Channel 5 Half Transfer Complete flag 18 1 HTIF6 Channel 6 Half Transfer Complete flag 22 1 HTIF7 Channel 7 Half Transfer Complete flag 26 1 TCIF1 Channel 1 Transfer Complete flag 1 1 TCIF2 Channel 2 Transfer Complete flag 5 1 TCIF3 Channel 3 Transfer Complete flag 9 1 TCIF4 Channel 4 Transfer Complete flag 13 1 TCIF5 Channel 5 Transfer Complete flag 17 1 TCIF6 Channel 6 Transfer Complete flag 21 1 TCIF7 Channel 7 Transfer Complete flag 25 1 TEIF1 Channel 1 Transfer Error flag 3 1 TEIF2 Channel 2 Transfer Error flag 7 1 TEIF3 Channel 3 Transfer Error flag 11 1 TEIF4 Channel 4 Transfer Error flag 15 1 TEIF5 Channel 5 Transfer Error flag 19 1 TEIF6 Channel 6 Transfer Error flag 23 1 TEIF7 Channel 7 Transfer Error flag 27 1 MADDR1 MADDR1 DMA channel 1 memory address register 0x14 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR10 MADDR10 DMA channel 10 memory address register used in ch32v30x_D8/D8C 0xBC 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR11 MADDR11 DMA channel 11 memory address register used in ch32v30x_D8/D8C 0xCC 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR2 MADDR2 DMA channel 2 memory address register 0x28 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR3 MADDR3 DMA channel 3 memory address register 0x3C 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR4 MADDR4 DMA channel 4 memory address register 0x50 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR5 MADDR5 DMA channel 5 memory address register 0x64 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR6 MADDR6 DMA channel 6 memory address register 0x78 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR7 MADDR7 DMA channel 7 memory address register 0x8C 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR8 MADDR8 DMA channel 8 memory address register used in ch32v30x_D8/D8C 0x9C 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 MADDR9 MADDR9 DMA channel 9 memory address register used in ch32v30x_D8/D8C 0xAC 32 read-write n 0x0 0xFFFFFFFF MA Memory address 0 32 PADDR1 PADDR1 DMA channel 1 peripheral address register 0x10 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR10 PADDR10 DMA channel 10 peripheral address register used in ch32v30x_D8/D8C 0xB8 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR11 PADDR11 DMA channel 11 peripheral address register used in ch32v30x_D8/D8C 0xC8 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR2 PADDR2 DMA channel 2 peripheral address register 0x24 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR3 PADDR3 DMA channel 3 peripheral address register 0x38 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR4 PADDR4 DMA channel 4 peripheral address register 0x4C 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR5 PADDR5 DMA channel 5 peripheral address register 0x60 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR6 PADDR6 DMA channel 6 peripheral address register 0x74 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR7 PADDR7 DMA channel 7 peripheral address register 0x88 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR8 PADDR8 DMA channel 8 peripheral address register used in ch32v30x_D8/D8C 0x98 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 PADDR9 PADDR7 DMA channel 7 peripheral address register used in ch32v30x_D8/D8C 0xA8 32 read-write n 0x0 0xFFFFFFFF PA Peripheral address 0 32 DVP Digital Video Port DVP 0x50050000 0x0 0x400 registers n DVP DVP global Interrupt interrupt 86 CAPCNT CAPCNT Digital Video Capture count register (DVP_CAPCNT) 0x1C 16 read-write n 0x0 0xFFFFFFFF RB_DVP_CAPCNT Number of PCLK cycles captured by clipping window 0 16 read-write COL_NUM COL_NUM Image column number configuration register (DVP_COL_NUM) 0x6 16 read-write n 0x0 0xFFFFFFFF RB_DVP_COL_NUM Number of PCLK cycles for row data 0 16 read-write CR0 CR0 Digital Video control register (DVP_CR0) 0x0 8 read-write n 0x0 0xFFFFFFFF RB_DVP_ENABLE DVP enable 0 1 read-write RB_DVP_H_POLAR DVP HSYNC polarity control 2 1 read-write RB_DVP_JPEG DVP JPEG mode 6 1 read-write RB_DVP_MSK_DAT_MOD DVP data mode 4 2 RB_DVP_P_POLAR DVP PCLK polarity control 3 1 read-write RB_DVP_V_POLAR DVP VSYNC polarity control 1 1 read-write CR1 CR1 Digital Video control register (DVP_CR1) 0x1 8 read-write n 0x6 0xFFFFFFFF RB_DVP_ALL_CLR DVP all clear 1 1 read-write RB_DVP_BUF_TOG DVP bug toggle by software 3 1 read-write RB_DVP_CM DVP capture mode 4 1 read-write RB_DVP_CROP DVP Crop feature enable 5 1 read-write RB_DVP_DMA_EN DVP dma enable 0 1 read-write RB_DVP_FCRC DVP frame capture rate control 6 2 read-write RB_DVP_RCV_CLR DVP receive logic clear 2 1 read-write DMA_BUF0 DMA_BUF0 Digital Video DMA address register (DVP_DMA_BUF0) 0x8 32 read-write n 0x0 0xFFFFFFFF RB_DVP_DMA_BUF0 DMA receive address 0 0 17 read-write DMA_BUF1 DMA_BUF1 Digital Video DMA address register (DVP_DMA_BUF1) 0xC 32 read-write n 0x0 0xFFFFFFFF RB_DVP_DMA_BUF1 DMA receive address 1 0 17 read-write DR DR Digital Video Data register (DVP_DR) 0x20 32 read-only n 0x0 0xFFFFFFFF RB_DVP_DR Prevent DMA overflow 0 32 HOFFCNT HOFFCNT Digital Video horizontal displacement register (DVP_HOFFCNT) 0x18 16 read-write n 0x0 0xFFFFFFFF RB_DVP_HOFFCNT Number of PCLK cycles for row data 0 16 read-write IER IER Digital Video Interrupt register (DVP_IER) 0x2 8 read-write n 0x0 0xFFFFFFFF RB_DVP_IE_FIFO_OV DVP receive fifo overflow interrupt enable 3 1 read-write RB_DVP_IE_FRM_DONE DVP frame received done interrupt enable 2 1 read-write RB_DVP_IE_ROW_DONE DVP row received done interrupt enable 1 1 read-write RB_DVP_IE_STP_FRM DVP frame stop interrupt enable 4 1 read-write RB_DVP_IE_STR_FRM DVP frame start interrupt enable 0 1 read-write IFR IFR Digital Video Flag register (DVP_IFR) 0x10 8 read-write n 0x0 0xFFFFFFFF RB_DVP_IF_FIFO_OV DVP receive fifo overflow interrupt enable 3 1 read-write RB_DVP_IF_FRM_DONE DVP frame received done interrupt enable 2 1 read-write RB_DVP_IF_ROW_DONE DVP row received done interrupt enable 1 1 read-write RB_DVP_IF_STP_FRM DVP frame stop interrupt enable 4 1 read-write RB_DVP_IF_STR_FRM DVP frame start interrupt enable 0 1 read-write ROW_CNT ROW_CNT Digital Video line counter register (DVP_ROW_CNT) 0x14 16 read-only n 0x0 0xFFFFFFFF RB_DVP_ROW_CNT The number of rows of frame image data 0 16 read-only ROW_NUM ROW_NUM Image line count configuration register (DVP_ROW_NUM) 0x4 16 read-write n 0x0 0xFFFFFFFF RB_DVP_ROW_NUM The number of rows of frame image data 0 16 read-write STATUS STATUS Digital Video STATUS register (DVP_STATUS) 0x11 8 read-only n 0x0 0xFFFFFFFF RB_DVP_FIFO_FULL DVP row received done interrupt enable 1 1 read-only RB_DVP_FIFO_OV DVP frame received done interrupt enable 2 1 read-only RB_DVP_FIFO_RDY DVP frame start interrupt enable 0 1 read-only RB_DVP_MSK_FIFO_CNT DVP receive fifo overflow interrupt enable 4 3 read-only VLINE VLINE Digital Video Vertical line count register (DVP_VLINE) 0x1E 16 read-write n 0x0 0xFFFFFFFF RB_DVP_VLINE Crop the number of rows captured by window 0 16 read-write VST VST Digital Video line number register (DVP_VST) 0x1A 16 read-write n 0x0 0xFFFFFFFF RB_DVP_VST The number of lines captured by the image 0 16 read-write ETHERNET_DMA Ethernet: DMA controller operation ETHERNET 0x40029000 0x0 0x400 registers n DMABMR DMABMR Ethernet DMA bus mode register 0x0 32 read-write n 0x2101 0xFFFFFFFF AAB Address-aligned beats 25 1 DA DMA Arbitration 1 1 DSL Descriptor skip length 2 5 FB Fixed burst 16 1 FPM 4xPBL mode 24 1 PBL Programmable burst length 8 6 RDP Rx DMA PBL 17 6 RTPR Rx Tx priority ratio 14 2 SR Software reset 0 1 USP Use separate PBL 23 1 DMACHRBAR DMACHRBAR Ethernet DMA current host receive buffer address register 0x54 32 read-only n 0x0 0xFFFFFFFF HRBAP Host receive buffer address pointer 0 32 DMACHRDR DMACHRDR Ethernet DMA current host receive descriptor register 0x4C 32 read-only n 0x0 0xFFFFFFFF HRDAP Host receive descriptor address pointer 0 32 DMACHTBAR DMACHTBAR Ethernet DMA current host transmit buffer address register 0x50 32 read-only n 0x0 0xFFFFFFFF HTBAP Host transmit buffer address pointer 0 32 DMACHTDR DMACHTDR Ethernet DMA current host transmit descriptor register 0x48 32 read-only n 0x0 0xFFFFFFFF HTDAP Host transmit descriptor address pointer 0 32 DMAIER DMAIER Ethernet DMA interrupt enable register 0x1C 32 read-write n 0x0 0xFFFFFFFF AISE Abnormal interrupt summary enable 15 1 ERIE Early receive interrupt enable 14 1 ETIE Early transmit interrupt enable 10 1 FBEIE Fatal bus error interrupt enable 13 1 IPLE 10M Physical layer connection 31 1 NISE Normal interrupt summary enable 16 1 RBUIE Receive buffer unavailable interrupt enable 7 1 RIE Receive interrupt enable 6 1 ROIE Overflow interrupt enable 4 1 RPSIE Receive process stopped interrupt enable 8 1 RWTIE receive watchdog timeout interrupt enable 9 1 TBUIE Transmit buffer unavailable interrupt enable 2 1 TIE Transmit interrupt enable 0 1 TJTIE Transmit jabber timeout interrupt enable 3 1 TPSIE Transmit process stopped interrupt enable 1 1 TUIE Underflow interrupt enable 5 1 DMAMFBOCR DMAMFBOCR Ethernet DMA missed frame and buffer overflow counter register 0x20 32 read-only n 0x0 0xFFFFFFFF MFA Missed frames by the application 17 11 MFC Missed frames by the controller 0 16 OFOC Overflow bit for FIFO overflow counter 28 1 OMFC Overflow bit for missed frame counter 16 1 DMAOMR DMAOMR Ethernet DMA operation mode register 0x18 32 read-write n 0x0 0xFFFFFFFF DFRF DFRF 24 1 DTCEFD DTCEFD 26 1 FEF FEF 7 1 FTF FTF 20 1 FUGF FUGF 6 1 OSF OSF 2 1 RSF RSF 25 1 RTC RTC 3 2 SR SR 1 1 ST ST 13 1 TSF TSF 21 1 TTC TTC 14 3 DMARDLAR DMARDLAR Ethernet DMA receive descriptor list address register 0xC 32 read-write n 0x0 0xFFFFFFFF SRL Start of receive list 0 32 DMARPDR DMARPDR EHERNET DMA receive poll demand register 0x8 32 read-write n 0x0 0xFFFFFFFF RPD Receive poll demand 0 32 DMASR DMASR Ethernet DMA status register 0x14 32 n 0x0 0xFFFFFFFF AIS Abnormal interrupt summary 15 1 read/clear EBS Error bits status 23 3 read-only ERS Early receive status 14 1 read/clear ETS Early transmit status 10 1 read/clear FBES Fatal bus error status 13 1 read/clear IPLS 10MPHY Physical layer variation 31 1 read-only MMCS MMC status 27 1 read-only NIS Normal interrupt summary 16 1 read/clear PMTS PMT status 28 1 read-only PWTS Receive watchdog timeout status 9 1 read/clear RBUS Receive buffer unavailable status 7 1 read/clear ROS Receive overflow status 4 1 read/clear RPS Receive process state 17 3 read-only RPSS Receive process stopped status 8 1 read/clear RS Receive status 6 1 read/clear TBUS Transmit buffer unavailable status 2 1 read/clear TJTS Transmit jabber timeout status 3 1 read/clear TPS Transmit process state 20 3 read-only TPSS Transmit process stopped status 1 1 read/clear TS Transmit status 0 1 read/clear TSTS Time stamp trigger status 29 1 read-only TUS Transmit underflow status 5 1 read/clear DMATDLAR DMATDLAR Ethernet DMA transmit descriptor list address register 0x10 32 read-write n 0x0 0xFFFFFFFF STL Start of transmit list 0 32 DMATPDR DMATPDR Ethernet DMA transmit poll demand register 0x4 32 read-write n 0x0 0xFFFFFFFF TPD Transmit poll demand 0 32 ETHERNET_MAC Ethernet: media access control ETHERNET 0x40028000 0x0 0x400 registers n ETH Ethernet global interrupt 77 ETH_WKUP Ethernet Wakeup through EXTI line interrupt 78 MACA0HR MACA0HR Ethernet MAC address 0 high register (ETH_MACA0HR) 0x40 32 n 0x10FFFF 0xFFFFFFFF MACA0H MAC address0 high 0 16 read-write MO Always 1 31 1 read-only MACA0LR MACA0LR Ethernet MAC address 0 low register 0x44 32 read-write n 0xFFFFFFFF 0xFFFFFFFF MACA0L MAC address0 low 0 32 MACA1HR MACA1HR Ethernet MAC address 1 high register (ETH_MACA1HR) 0x48 32 read-write n 0xFFFF 0xFFFFFFFF AE Address enable 31 1 MACA1H MAC address1 high 0 16 MBC Mask byte control 24 6 SA Source address 30 1 MACA1LR MACA1LR Ethernet MAC address1 low register 0x4C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF MACA1L MAC address1 low 0 32 MACA2HR MACA2HR Ethernet MAC address 2 high register (ETH_MACA2HR) 0x50 32 read-write n 0xFFFF 0xFFFFFFFF AE Address enable 31 1 ETH_MACA2HR Ethernet MAC address 2 high register 0 16 MBC Mask byte control 24 6 SA Source address 30 1 MACA2LR MACA2LR Ethernet MAC address 2 low register 0x54 32 read-write n 0xFFFFFFFF 0xFFFFFFFF MACA2L MAC address2 low 0 31 MACA3HR MACA3HR Ethernet MAC address 3 high register (ETH_MACA3HR) 0x58 32 read-write n 0xFFFF 0xFFFFFFFF AE Address enable 31 1 MACA3H MAC address3 high 0 16 MBC Mask byte control 24 6 SA Source address 30 1 MACA3LR MACA3LR Ethernet MAC address 3 low register 0x5C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF MBCA3L MAC address3 low 0 32 MACCR MACCR Ethernet MAC configuration register (ETH_MACCR) 0x0 32 read-write n 0x8000 0xFFFFFFFF APCS Automatic pad/CRC stripping 7 1 BL Back-off limit 5 2 CSD Carrier sense disable 16 1 DC Deferral check 4 1 DM Duplex mode 11 1 FES Fast Ethernet speed 14 1 IFG Interframe gap 17 3 IPCO IPv4 checksum offload 10 1 IRE 10MPHY 50Ω set 20 1 JD Jabber disable 22 1 LM Loopback mode 12 1 PDI 10MPHY TX DRIVER bisa current 21 1 RD Retry disable 9 1 RE Receiver enable 2 1 ROD Receive own disable 13 1 TCD SEND clock delay 29 3 TCES Send clock selection bit 0 1 TCF Send clock reversal 1 1 TE Transmitter enable 3 1 WD Watchdog disable 23 1 MACFCR MACFCR Ethernet MAC flow control register (ETH_MACFCR) 0x18 32 read-write n 0x0 0xFFFFFFFF FCB_BPA Flow control busy/back pressure activate 0 1 PLT Pause low threshold 4 2 PT Pass control frames 16 16 RFCE Receive flow control enable 2 1 TFCE Transmit flow control enable 1 1 UPFD Unicast pause frame detect 3 1 ZQPD Zero-quanta pause disable 7 1 MACFFR MACFFR Ethernet MAC frame filter register (ETH_MACCFFR) 0x4 32 read-write n 0x0 0xFFFFFFFF BFD Broadcast frames disable 5 1 DAIF Destination address inverse filtering 3 1 HM Hash multicast 2 1 HPF Hash or perfect filter 10 1 HU Hash unicast 1 1 PAM Pass all multicast 4 1 PCF Pass control frames 6 2 PM Promiscuous mode 0 1 RA Receive all 31 1 SAF Source address filter 9 1 SAIF Source address inverse filtering 8 1 MACHTHR MACHTHR Ethernet MAC hash table high register 0x8 32 read-write n 0x0 0xFFFFFFFF HTH Hash table high 0 32 MACHTLR MACHTLR Ethernet MAC hash table low register 0xC 32 read-write n 0x0 0xFFFFFFFF HTL Hash table low 0 32 MACIMR MACIMR Ethernet MAC interrupt mask register (ETH_MACIMR) 0x3C 32 read-write n 0x0 0xFFFFFFFF PMTIM PMT interrupt mask 3 1 TSTIM Time stamp trigger interrupt mask 9 1 MACMIIAR MACMIIAR Ethernet MAC MII address register (ETH_MACMIIAR) 0x10 32 read-write n 0x0 0xFFFFFFFF CR Clock range 2 3 MB MII busy 0 1 MR MII register 6 5 MW MII write 1 1 PA PHY address 11 5 MACMIIDR MACMIIDR Ethernet MAC MII data register (ETH_MACMIIDR) 0x14 32 read-write n 0x0 0xFFFFFFFF MD MII data 0 16 MACPMTCSR MACPMTCSR Ethernet MAC PMT control and status register (ETH_MACPMTCSR) 0x2C 32 read-write n 0x0 0xFFFFFFFF GU Global unicast 9 1 MPE Magic Packet enable 1 1 MPR Magic packet received 5 1 PD Power down 0 1 WFE Wakeup frame enable 2 1 WFFRPR Wakeup frame filter register pointer reset 31 1 WFR Wakeup frame received 6 1 MACRWUFFR MACRWUFFR Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) 0x28 32 read-write n 0x0 0xFFFFFFFF MACSR MACSR Ethernet MAC interrupt status register (ETH_MACSR) 0x38 32 read-write n 0x0 0xFFFFFFFF MMCRS MMC receive status 5 1 MMCS MMC status 4 1 MMCTS MMC transmit status 6 1 PMTS PMT status 3 1 TSTS Time stamp trigger status 9 1 MACVLANTR MACVLANTR Ethernet MAC VLAN tag register (ETH_MACVLANTR) 0x1C 32 read-write n 0x0 0xFFFFFFFF VLANTC 12-bit VLAN tag comparison 16 1 VLANTI VLAN tag identifier (for receive frames) 0 16 ETHERNET_MMC Ethernet: MAC management counters ETHERNET 0x40028100 0x0 0x400 registers n MMCCR MMCCR Ethernet MMC control register (ETH_MMCCR) 0x0 32 read-write n 0x0 0xFFFFFFFF CR Counter reset 0 1 CSR Counter stop rollover 1 1 MCF MMC counter freeze 31 1 ROR Reset on read 2 1 MMCRFAECR MMCRFAECR Ethernet MMC received frames with alignment error counter register 0x98 32 read-only n 0x0 0xFFFFFFFF RFAEC Received frames with alignment error counter 0 32 MMCRFCECR MMCRFCECR Ethernet MMC received frames with CRC error counter register 0x94 32 read-only n 0x0 0xFFFFFFFF RFCFC Received frames with CRC error counter 0 32 MMCRGUFCR MMCRGUFCR MMC received good unicast frames counter register 0xC4 32 read-only n 0x0 0xFFFFFFFF RGUFC Received good unicast frames counter 0 32 MMCRIMR MMCRIMR Ethernet MMC receive interrupt mask register (ETH_MMCRIMR) 0xC 32 read-write n 0x0 0xFFFFFFFF RFAEM Received frames alignment error mask 6 1 RFCEM Received frame CRC error mask 5 1 RGUFM Received good unicast frames mask 17 1 MMCRIR MMCRIR Ethernet MMC receive interrupt register (ETH_MMCRIR) 0x4 32 read-write n 0x0 0xFFFFFFFF RFAES Received frames alignment error status 6 1 RFCES Received frames CRC error status 5 1 RGUFS Received Good Unicast Frames Status 17 1 MMCTGFCR MMCTGFCR Ethernet MMC transmitted good frames counter register 0x68 32 read-only n 0x0 0xFFFFFFFF TGFC Transmitted good frames counter 0 32 MMCTGFMSCCR MMCTGFMSCCR Ethernet MMC transmitted good frames after more than a single collision 0x50 32 read-only n 0x0 0xFFFFFFFF TGFMSCC Transmitted good frames after more than a single collision counter 0 32 MMCTGFSCCR MMCTGFSCCR Ethernet MMC transmitted good frames after a single collision counter 0x4C 32 read-only n 0x0 0xFFFFFFFF TGFSCC Transmitted good frames after a single collision counter 0 32 MMCTIMR MMCTIMR Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR) 0x10 32 read-write n 0x0 0xFFFFFFFF TGFM Transmitted good frames mask 21 1 TGFMSCM Transmitted good frames more single collision mask 15 1 TGFSCM Transmitted good frames single collision mask 14 1 MMCTIR MMCTIR Ethernet MMC transmit interrupt register (ETH_MMCTIR) 0x8 32 read-write n 0x0 0xFFFFFFFF TGFMSCS Transmitted good frames more single collision status 15 1 TGFS Transmitted good frames status 21 1 TGFSCS Transmitted good frames single collision status 14 1 ETHERNET_PTP Ethernet: Precision time protocol ETHERNET 0x40028700 0x0 0x400 registers n PTPSSIR PTPSSIR Ethernet PTP subsecond increment register 0x4 32 read-write n 0x0 0xFFFFFFFF STSSI System time subsecond increment 0 8 PTPTSAR PTPTSAR Ethernet PTP time stamp addend register 0x18 32 read-write n 0x0 0xFFFFFFFF TSA Time stamp addend 0 32 PTPTSCR PTPTSCR Ethernet PTP time stamp control register (ETH_PTPTSCR) 0x0 32 read-write n 0x0 0xFFFFFFFF TSARU Time stamp addend register update 5 1 TSE Time stamp enable 0 1 TSFCU Time stamp fine or coarse update 1 1 TSITE Time stamp interrupt trigger enable 4 1 TSSTI Time stamp system time initialize 2 1 TSSTU Time stamp system time update 3 1 PTPTSHR PTPTSHR Ethernet PTP time stamp high register 0x8 32 read-only n 0x0 0xFFFFFFFF STS System time second 0 32 PTPTSHUR PTPTSHUR Ethernet PTP time stamp high update register 0x10 32 read-write n 0x0 0xFFFFFFFF TSUS Time stamp update second 0 32 PTPTSLR PTPTSLR Ethernet PTP time stamp low register (ETH_PTPTSLR) 0xC 32 read-only n 0x0 0xFFFFFFFF STPNS System time positive or negative sign 31 1 STSS System time subseconds 0 31 PTPTSLUR PTPTSLUR Ethernet PTP time stamp low update register (ETH_PTPTSLUR) 0x14 32 read-write n 0x0 0xFFFFFFFF TSUPNS Time stamp update positive or negative sign 31 1 TSUSS Time stamp update subseconds 0 31 PTPTTHR PTPTTHR Ethernet PTP target time high register 0x1C 32 read-write n 0x0 0xFFFFFFFF TTSH Target time stamp high 0 32 PTPTTLR PTPTTLR Ethernet PTP target time low register 0x20 32 read-write n 0x0 0xFFFFFFFF TTSL Target time stamp low 0 32 EXTEND Extend configuration EXTEND 0x40023800 0x0 0x400 registers n EXTEND_CTR EXTEND EXTEND register 0x0 32 n 0xA00 0xFFFFFFFF ETH_10M_EN ETH 10M Enable 2 1 read-write ETH_RGMII_EN ETH RGMII Enable 3 1 read-write HSE_KEEP_LP HSE_KEEP_LP 12 1 read-write LDO_TRIM LDO_TRIM 10 2 read-write LOCKUP_EN LOCKUP_Eable 6 1 read-write LOCKUP_RSTF LOCKUP RESET 7 1 read/clear PLL_HSI_PRE Whether HSI is divided 4 1 read-write ULLDO_TRIM ULLDO_TRIM 8 2 read-write USBDLS USBD Lowspeed Enable 0 1 read-write USBDPU USBD pullup Enable 1 1 read-write EXTI EXTI EXTI 0x40010400 0x0 0x400 registers n TAMPER Tamper interrupt 18 EXTI0 EXTI Line0 interrupt 22 EXTI1 EXTI Line1 interrupt 23 EXTI2 EXTI Line2 interrupt 24 EXTI3 EXTI Line3 interrupt 25 EXTI4 EXTI Line4 interrupt 26 EXTI9_5 EXTI Line[9:5] interrupts 39 EXTI15_10 EXTI Line[15:10] interrupts 56 EVENR EVENR Event mask register (EXTI_EVENR) 0x4 32 read-write n 0x0 0xFFFFFFFF MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 FTENR FTENR Falling Trigger selection register (EXTI_FTENR) 0xC 32 read-write n 0x0 0xFFFFFFFF TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 INTENR INTENR Interrupt mask register (EXTI_INTENR) 0x0 32 read-write n 0x0 0xFFFFFFFF MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 INTFR INTFR Pending register (EXTI_INTFR) 0x14 32 read-write n 0x0 0xFFFFFFFF PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR17 Pending bit 17 17 1 PR18 Pending bit 18 18 1 PR19 Pending bit 19 19 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 RTENR RTENR Rising Trigger selection register (EXTI_RTENR) 0x8 32 read-write n 0x0 0xFFFFFFFF TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 SWIEVR SWIEVR Software interrupt event register (EXTI_SWIEVR) 0x10 32 read-write n 0x0 0xFFFFFFFF SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 FLASH FLASH FLASH 0x40022000 0x0 0x400 registers n FLASH Flash global interrupt 20 ADDR ADDR Flash address register 0x14 32 write-only n 0x0 0xFFFFFFFF FAR Flash Address 0 32 CTLR CTLR Control register 0x10 32 read-write n 0x80 0xFFFFFFFF BER32 Block Erase 32K 18 1 BER64 Block Erase 64K 19 1 ENHANCEMODE Flash Enhance read mode 24 1 EOPIE End of operation interrupt enable 12 1 ERRIE Error interrupt enable 10 1 FLOCK Fast programmable lock 15 1 LOCK Lock 7 1 MER Mass Erase 2 1 OBER Option byte erase 5 1 OBPG Option byte programming 4 1 OBWRE Option bytes write enable 9 1 PAGE_ER Fast erase 17 1 PAGE_PG Fast programming 16 1 PER Page Erase 1 1 PG Programming 0 1 PGSTART Page Programming Start 21 1 RSENACT Reset Flash Enhance read mode 22 1 SCKMODE Flash SCK mode 25 1 STRT Start 6 1 KEYR KEYR Flash key register 0x4 32 write-only n 0x0 0xFFFFFFFF KEYR FPEC key 0 32 MODEKEYR MODEKEYR Mode select register 0x24 32 write-only n 0x0 0xFFFFFFFF MODEKEYR Mode select 0 32 OBKEYR OBKEYR Flash option key register 0x8 32 write-only n 0x0 0xFFFFFFFF OPTKEY Option byte key 0 32 OBR OBR Option byte register 0x1C 32 read-only n 0x3FFFFFC 0xFFFFFFFF IWDG_SW IWDG_SW 2 1 OBERR Option byte error 0 1 RDPRT Read protection 1 1 SRAM_CODE_MODE SRAM_CODE_MODE 8 2 STANDY_RST STANDY_RST 4 1 STOP_RST STOP_RST 3 1 STATR STATR Status register 0xC 32 n 0x0 0xFFFFFFFF BSY Busy 0 1 read-only ENHANCE_MOD_STA Enhance mode start 7 1 read-only EOP End of operation 5 1 read-write WRPRTERR Write protection error 4 1 read-write WR_BSY Quick page programming 1 1 read-only WPR WPR Write protection register 0x20 32 read-only n 0xFFFFFFFF 0xFFFFFFFF WRP Write protect 0 32 FSMC Flexible static memory controller FSMC 0xA0000000 0x0 0x1000 registers n FSMC FSMC global interrupt 64 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 32 read-write n 0x30D0 0xFFFFFFFF ASYNCWAIT Wait signal during asynchronous transfers 15 1 read-write BURSTEN Burst enable bit 8 1 read-write CBURSTRW Write burst enable 19 1 read-write EXTMOD Extended mode enable 14 1 read-write FACCEN Flash access enable 6 1 read-write MBKEN Memory bank enable bit 0 1 read-write MTYP Memory type 2 2 read-write MUXEN Address/data multiplexing enable bit 1 1 read-write MWID Memory databus width 4 2 read-write WAITCFG Wait timing configuration 11 1 read-write WAITEN Wait enable bit 13 1 read-write WAITPOL Wait signal polarity bit 9 1 read-write WRAPMOD Wrapped burst mode support 10 1 read-write WREN Write enable bit 12 1 read-write BTR1 BTR1 SRAM/NOR-Flash chip-select timing register 1 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF ACCMOD Access mode 28 2 read-write ADDHLD Address-hold phase duration 4 4 read-write ADDSET Address setup phase duration 0 4 read-write BUSTURN Bus turnaround phase duration 16 4 read-write CLKDIV Clock divide ratio (for FSMC_CLK signal) 20 4 read-write DATAST Data-phase duration 8 8 read-write DATLAT Data latency for synchronous NOR Flash memory 24 4 read-write BWTR1 BWTR1 SRAM/NOR-Flash write timing registers 1 0x104 32 read-write n 0xFFFFFFF 0xFFFFFFFF ACCMOD Access mode 28 2 ADDHLD Address-hold phase duration 4 4 ADDSET Address setup phase duration 0 4 CLKDIV Clock divide ratio (for FSMC_CLK signal) 20 4 DATAST Data-phase duration 8 8 DATLAT Data latency for synchronous NOR Flash memory 24 4 ECCR2 ECCR2 ECC result register 2 0x74 32 read-only n 0x0 0xFFFFFFFF ECCx ECC result 0 32 PATT2 PATT2 Attribute memory space timing register 2 0x6C 32 read-write n 0xFCFCFCFC 0xFFFFFFFF ATTHIZx Attribute memory x databus HiZ time 24 8 ATTHOLDx Attribute memory x hold time 16 8 ATTSETx Attribute memory x setup time 0 8 ATTWAITx Attribute memory x wait time 8 8 PCR2 PCR2 PC Card/NAND Flash control register 2 0x60 32 read-write n 0x18 0xFFFFFFFF ECCEN ECC computation logic enable bit 6 1 ECCPS ECC page size 17 3 PBKEN PC Card/NAND Flash memory bank enable bit 2 1 PTYP Memory type 3 1 PWAITEN Wait feature enable bit 1 1 PWID Databus width 4 2 TAR ALE to RE delay 13 4 TCLR CLE to RE delay 9 4 PMEM2 PMEM2 Common memory space timing register 2 0x68 32 read-write n 0xFCFCFCFC 0xFFFFFFFF MEMHIZx Common memory x databus HiZ time 24 8 MEMHOLDx Common memory x hold time 16 8 MEMSETx Common memory x setup time 0 8 MEMWAITx Common memory x wait time 8 8 SR2 SR2 FIFO status and interrupt register 2 0x64 32 n 0x40 0xFFFFFFFF FEMPT FIFO empty 6 1 read-only IFEN Interrupt falling edge detection enable bit 5 1 read-write IFS Interrupt falling edge status 2 1 read-write ILEN Interrupt high-level detection enable bit 4 1 read-write ILS Interrupt high-level status 1 1 read-write IREN Interrupt rising edge detection enable bit 3 1 read-write IRS Interrupt rising edge status 0 1 read-write GPIOA General purpose I/O GPIO 0x40010800 0x0 0x400 registers n BCR BCR Port bit reset register (GPIOn_BCR) 0x14 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x4 32 read-write n 0x44444444 0xFFFFFFFF CNF10 Port n.10 configuration bits 10 2 CNF11 Port n.11 configuration bits 14 2 CNF12 Port n.12 configuration bits 18 2 CNF13 Port n.13 configuration bits 22 2 CNF14 Port n.14 configuration bits 26 2 CNF15 Port n.15 configuration bits 30 2 CNF8 Port n.8 configuration bits 2 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 MODE11 Port n.11 mode bits 12 2 MODE12 Port n.12 mode bits 16 2 MODE13 Port n.13 mode bits 20 2 MODE14 Port n.14 mode bits 24 2 MODE15 Port n.15 mode bits 28 2 MODE8 Port n.8 mode bits 0 2 MODE9 Port n.9 mode bits 4 2 CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 32 read-write n 0x44444444 0xFFFFFFFF CNF0 Port n.0 configuration bits 2 2 CNF1 Port n.1 configuration bits 6 2 CNF2 Port n.2 configuration bits 10 2 CNF3 Port n.3 configuration bits 14 2 CNF4 Port n.4 configuration bits 18 2 CNF5 Port n.5 configuration bits 22 2 CNF6 Port n.6 configuration bits 26 2 CNF7 Port n.7 configuration bits 30 2 MODE0 Port n.0 mode bits 0 2 MODE1 Port n.1 mode bits 4 2 MODE2 Port n.2 mode bits 8 2 MODE3 Port n.3 mode bits 12 2 MODE4 Port n.4 mode bits 16 2 MODE5 Port n.5 mode bits 20 2 MODE6 Port n.6 mode bits 24 2 MODE7 Port n.7 mode bits 28 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 32 read-only n 0x0 0xFFFFFFFF IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 LCKR LCKR Port configuration lock register 0x18 32 read-write n 0x0 0xFFFFFFFF LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCKK Lock key 16 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 32 read-write n 0x0 0xFFFFFFFF ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 GPIOB General purpose I/O GPIO 0x40010C00 0x0 0x400 registers n BCR BCR Port bit reset register (GPIOn_BCR) 0x14 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x4 32 read-write n 0x44444444 0xFFFFFFFF CNF10 Port n.10 configuration bits 10 2 CNF11 Port n.11 configuration bits 14 2 CNF12 Port n.12 configuration bits 18 2 CNF13 Port n.13 configuration bits 22 2 CNF14 Port n.14 configuration bits 26 2 CNF15 Port n.15 configuration bits 30 2 CNF8 Port n.8 configuration bits 2 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 MODE11 Port n.11 mode bits 12 2 MODE12 Port n.12 mode bits 16 2 MODE13 Port n.13 mode bits 20 2 MODE14 Port n.14 mode bits 24 2 MODE15 Port n.15 mode bits 28 2 MODE8 Port n.8 mode bits 0 2 MODE9 Port n.9 mode bits 4 2 CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 32 read-write n 0x44444444 0xFFFFFFFF CNF0 Port n.0 configuration bits 2 2 CNF1 Port n.1 configuration bits 6 2 CNF2 Port n.2 configuration bits 10 2 CNF3 Port n.3 configuration bits 14 2 CNF4 Port n.4 configuration bits 18 2 CNF5 Port n.5 configuration bits 22 2 CNF6 Port n.6 configuration bits 26 2 CNF7 Port n.7 configuration bits 30 2 MODE0 Port n.0 mode bits 0 2 MODE1 Port n.1 mode bits 4 2 MODE2 Port n.2 mode bits 8 2 MODE3 Port n.3 mode bits 12 2 MODE4 Port n.4 mode bits 16 2 MODE5 Port n.5 mode bits 20 2 MODE6 Port n.6 mode bits 24 2 MODE7 Port n.7 mode bits 28 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 32 read-only n 0x0 0xFFFFFFFF IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 LCKR LCKR Port configuration lock register 0x18 32 read-write n 0x0 0xFFFFFFFF LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCKK Lock key 16 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 32 read-write n 0x0 0xFFFFFFFF ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 GPIOC General purpose I/O GPIO 0x40011000 0x0 0x400 registers n BCR BCR Port bit reset register (GPIOn_BCR) 0x14 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x4 32 read-write n 0x44444444 0xFFFFFFFF CNF10 Port n.10 configuration bits 10 2 CNF11 Port n.11 configuration bits 14 2 CNF12 Port n.12 configuration bits 18 2 CNF13 Port n.13 configuration bits 22 2 CNF14 Port n.14 configuration bits 26 2 CNF15 Port n.15 configuration bits 30 2 CNF8 Port n.8 configuration bits 2 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 MODE11 Port n.11 mode bits 12 2 MODE12 Port n.12 mode bits 16 2 MODE13 Port n.13 mode bits 20 2 MODE14 Port n.14 mode bits 24 2 MODE15 Port n.15 mode bits 28 2 MODE8 Port n.8 mode bits 0 2 MODE9 Port n.9 mode bits 4 2 CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 32 read-write n 0x44444444 0xFFFFFFFF CNF0 Port n.0 configuration bits 2 2 CNF1 Port n.1 configuration bits 6 2 CNF2 Port n.2 configuration bits 10 2 CNF3 Port n.3 configuration bits 14 2 CNF4 Port n.4 configuration bits 18 2 CNF5 Port n.5 configuration bits 22 2 CNF6 Port n.6 configuration bits 26 2 CNF7 Port n.7 configuration bits 30 2 MODE0 Port n.0 mode bits 0 2 MODE1 Port n.1 mode bits 4 2 MODE2 Port n.2 mode bits 8 2 MODE3 Port n.3 mode bits 12 2 MODE4 Port n.4 mode bits 16 2 MODE5 Port n.5 mode bits 20 2 MODE6 Port n.6 mode bits 24 2 MODE7 Port n.7 mode bits 28 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 32 read-only n 0x0 0xFFFFFFFF IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 LCKR LCKR Port configuration lock register 0x18 32 read-write n 0x0 0xFFFFFFFF LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCKK Lock key 16 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 32 read-write n 0x0 0xFFFFFFFF ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 GPIOD General purpose I/O GPIO 0x40011400 0x0 0x400 registers n BCR BCR Port bit reset register (GPIOn_BCR) 0x14 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x4 32 read-write n 0x44444444 0xFFFFFFFF CNF10 Port n.10 configuration bits 10 2 CNF11 Port n.11 configuration bits 14 2 CNF12 Port n.12 configuration bits 18 2 CNF13 Port n.13 configuration bits 22 2 CNF14 Port n.14 configuration bits 26 2 CNF15 Port n.15 configuration bits 30 2 CNF8 Port n.8 configuration bits 2 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 MODE11 Port n.11 mode bits 12 2 MODE12 Port n.12 mode bits 16 2 MODE13 Port n.13 mode bits 20 2 MODE14 Port n.14 mode bits 24 2 MODE15 Port n.15 mode bits 28 2 MODE8 Port n.8 mode bits 0 2 MODE9 Port n.9 mode bits 4 2 CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 32 read-write n 0x44444444 0xFFFFFFFF CNF0 Port n.0 configuration bits 2 2 CNF1 Port n.1 configuration bits 6 2 CNF2 Port n.2 configuration bits 10 2 CNF3 Port n.3 configuration bits 14 2 CNF4 Port n.4 configuration bits 18 2 CNF5 Port n.5 configuration bits 22 2 CNF6 Port n.6 configuration bits 26 2 CNF7 Port n.7 configuration bits 30 2 MODE0 Port n.0 mode bits 0 2 MODE1 Port n.1 mode bits 4 2 MODE2 Port n.2 mode bits 8 2 MODE3 Port n.3 mode bits 12 2 MODE4 Port n.4 mode bits 16 2 MODE5 Port n.5 mode bits 20 2 MODE6 Port n.6 mode bits 24 2 MODE7 Port n.7 mode bits 28 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 32 read-only n 0x0 0xFFFFFFFF IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 LCKR LCKR Port configuration lock register 0x18 32 read-write n 0x0 0xFFFFFFFF LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCKK Lock key 16 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 32 read-write n 0x0 0xFFFFFFFF ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 GPIOE General purpose I/O GPIO 0x40011800 0x0 0x400 registers n BCR BCR Port bit reset register (GPIOn_BCR) 0x14 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 32 write-only n 0x0 0xFFFFFFFF BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x4 32 read-write n 0x44444444 0xFFFFFFFF CNF10 Port n.10 configuration bits 10 2 CNF11 Port n.11 configuration bits 14 2 CNF12 Port n.12 configuration bits 18 2 CNF13 Port n.13 configuration bits 22 2 CNF14 Port n.14 configuration bits 26 2 CNF15 Port n.15 configuration bits 30 2 CNF8 Port n.8 configuration bits 2 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 MODE11 Port n.11 mode bits 12 2 MODE12 Port n.12 mode bits 16 2 MODE13 Port n.13 mode bits 20 2 MODE14 Port n.14 mode bits 24 2 MODE15 Port n.15 mode bits 28 2 MODE8 Port n.8 mode bits 0 2 MODE9 Port n.9 mode bits 4 2 CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 32 read-write n 0x44444444 0xFFFFFFFF CNF0 Port n.0 configuration bits 2 2 CNF1 Port n.1 configuration bits 6 2 CNF2 Port n.2 configuration bits 10 2 CNF3 Port n.3 configuration bits 14 2 CNF4 Port n.4 configuration bits 18 2 CNF5 Port n.5 configuration bits 22 2 CNF6 Port n.6 configuration bits 26 2 CNF7 Port n.7 configuration bits 30 2 MODE0 Port n.0 mode bits 0 2 MODE1 Port n.1 mode bits 4 2 MODE2 Port n.2 mode bits 8 2 MODE3 Port n.3 mode bits 12 2 MODE4 Port n.4 mode bits 16 2 MODE5 Port n.5 mode bits 20 2 MODE6 Port n.6 mode bits 24 2 MODE7 Port n.7 mode bits 28 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 32 read-only n 0x0 0xFFFFFFFF IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 LCKR LCKR Port configuration lock register 0x18 32 read-write n 0x0 0xFFFFFFFF LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCKK Lock key 16 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 32 read-write n 0x0 0xFFFFFFFF ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers n I2C1_EV I2C1 event interrupt 47 I2C1_ER I2C1 error interrupt 48 CKCFGR CKCFGR Clock control register 0x1C 32 read-write n 0x0 0xFFFFFFFF CCR Clock control register in Fast/Standard mode (Master mode) 0 12 DUTY Fast mode duty cycle 14 1 F_S I2C master mode selection 15 1 CTLR1 CTLR1 Control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ACK Acknowledge enable 10 1 ALERT SMBus alert 13 1 ENARP ARP enable 4 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 PE Peripheral enable 0 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 SMBTYPE SMBus type 3 1 SMBUS SMBus mode 1 1 START Start generation 8 1 STOP Stop generation 9 1 SWRST Software reset 15 1 CTLR2 CTLR2 Control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF DMAEN DMA requests enable 11 1 FREQ Peripheral clock frequency 0 6 ITBUFEN Buffer interrupt enable 10 1 ITERREN Error interrupt enable 8 1 ITEVTEN Event interrupt enable 9 1 LAST DMA last transfer 12 1 DATAR DATAR Data register 0x10 32 read-write n 0x0 0xFFFFFFFF DATAR 8-bit data register 0 8 OADDR1 OADDR1 Own address register 1 0x8 32 read-write n 0x0 0xFFFFFFFF ADD0 Interface address 0 1 ADD7_1 Interface address 1 7 ADD9_8 Interface address 8 2 ADDMODE Addressing mode (slave mode) 15 1 MUST1 Must be 1 14 1 OADDR2 OADDR2 Own address register 2 0xC 32 read-write n 0x0 0xFFFFFFFF ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 RTR RTR Raise time register 0x20 32 read-write n 0x2 0xFFFFFFFF TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 STAR1 STAR1 Status register 1 0x14 32 n 0x0 0xFFFFFFFF ADD10 10-bit header sent (Master mode) 3 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write BTF Byte transfer finished 2 1 read-only OVR Overrun/Underrun 11 1 read-write PECERR PEC Error in reception 12 1 read-write RxNE Data register not empty (receivers) 6 1 read-only SB Start bit (Master mode) 0 1 read-only SMBALERT SMBus alert 15 1 read-write STOPF Stop detection (slave mode) 4 1 read-only TIMEOUT Timeout or Tlow error 14 1 read-write TxE Data register empty (transmitters) 7 1 read-only STAR2 STAR2 Status register 2 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Bus busy 1 1 DUALF Dual flag (Slave mode) 7 1 GENCALL General call address (Slave mode) 4 1 MSL Master/slave 0 1 PEC acket error checking register 8 8 SMBDEFAULT SMBus device default address (Slave mode) 5 1 SMBHOST SMBus host header (Slave mode) 6 1 TRA Transmitter/receiver 2 1 I2C2 Inter integrated circuit I2C 0x40005800 0x0 0x400 registers n I2C2_EV I2C2 event interrupt 49 I2C2_ER I2C2 error interrupt 50 CKCFGR CKCFGR Clock control register 0x1C 32 read-write n 0x0 0xFFFFFFFF CCR Clock control register in Fast/Standard mode (Master mode) 0 12 DUTY Fast mode duty cycle 14 1 F_S I2C master mode selection 15 1 CTLR1 CTLR1 Control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ACK Acknowledge enable 10 1 ALERT SMBus alert 13 1 ENARP ARP enable 4 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 PE Peripheral enable 0 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 SMBTYPE SMBus type 3 1 SMBUS SMBus mode 1 1 START Start generation 8 1 STOP Stop generation 9 1 SWRST Software reset 15 1 CTLR2 CTLR2 Control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF DMAEN DMA requests enable 11 1 FREQ Peripheral clock frequency 0 6 ITBUFEN Buffer interrupt enable 10 1 ITERREN Error interrupt enable 8 1 ITEVTEN Event interrupt enable 9 1 LAST DMA last transfer 12 1 DATAR DATAR Data register 0x10 32 read-write n 0x0 0xFFFFFFFF DATAR 8-bit data register 0 8 OADDR1 OADDR1 Own address register 1 0x8 32 read-write n 0x0 0xFFFFFFFF ADD0 Interface address 0 1 ADD7_1 Interface address 1 7 ADD9_8 Interface address 8 2 ADDMODE Addressing mode (slave mode) 15 1 MUST1 Must be 1 14 1 OADDR2 OADDR2 Own address register 2 0xC 32 read-write n 0x0 0xFFFFFFFF ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 RTR RTR Raise time register 0x20 32 read-write n 0x2 0xFFFFFFFF TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 STAR1 STAR1 Status register 1 0x14 32 n 0x0 0xFFFFFFFF ADD10 10-bit header sent (Master mode) 3 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write BTF Byte transfer finished 2 1 read-only OVR Overrun/Underrun 11 1 read-write PECERR PEC Error in reception 12 1 read-write RxNE Data register not empty (receivers) 6 1 read-only SB Start bit (Master mode) 0 1 read-only SMBALERT SMBus alert 15 1 read-write STOPF Stop detection (slave mode) 4 1 read-only TIMEOUT Timeout or Tlow error 14 1 read-write TxE Data register empty (transmitters) 7 1 read-only STAR2 STAR2 Status register 2 0x18 32 read-only n 0x0 0xFFFFFFFF BUSY Bus busy 1 1 DUALF Dual flag (Slave mode) 7 1 GENCALL General call address (Slave mode) 4 1 MSL Master/slave 0 1 PEC acket error checking register 8 8 SMBDEFAULT SMBus device default address (Slave mode) 5 1 SMBHOST SMBus host header (Slave mode) 6 1 TRA Transmitter/receiver 2 1 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers n CTLR CTLR Key register (IWDG_CTLR) 0x0 32 write-only n 0x0 0xFFFFFFFF KEY Key value 0 16 write-only PSCR PSCR Prescaler register (IWDG_PSCR) 0x4 32 read-write n 0x0 0xFFFFFFFF PR Prescaler divider 0 3 read-write RLDR RLDR Reload register (IWDG_RLDR) 0x8 32 read-write n 0xFFF 0xFFFFFFFF RL Watchdog counter reload value 0 12 read-write STATR STATR Status register (IWDG_SR) 0xC 32 read-only n 0x0 0xFFFFFFFF PVU Watchdog prescaler value update 0 1 read-only RVU Watchdog counter reload value update 1 1 read-only OPA OPA configuration OPA 0x40023804 0x0 0x200 registers n CR CR Control register 0x0 32 n 0x0 0xFFFFFFFF EN1 OPA Enable1 0 1 read-write EN2 OPA Enable2 4 1 read-write EN3 OPA Eable3 8 1 read-write EN4 OPA Enable4 12 1 read-write MODE1 OPA MODE1 1 1 read-write MODE2 OPA MODE2 5 1 read-write MODE3 OPA MODE3 9 1 read-write MODE4 OPA MODE4 13 1 read-write NSEL1 OPA NSEL1 2 1 read-write NSEL2 OPA NSEL2 6 1 read-write NSEL3 OPA NSEL3 10 1 read-write NSEL4 OPA NSEL4 14 1 read-write PSEL1 OPA PSEL1 3 1 read-write PSEL2 OPA PSEL2 7 1 read-write PSEL3 OPA PSEL3 11 1 read-write PSEL4 OPA PSEL4 15 1 read-write PFIC Programmable Fast Interrupt Controller PFIC 0xE000E000 0x0 0x1100 registers n CFGR CFGR Interrupt Config Register 0x48 32 n 0x0 0xFFFFFFFF KEYCODE KEYCODE 16 16 write-only RESETSYS RESETSYS 7 1 write-only GISR GISR Interrupt Global Register 0x4C 32 read-only n 0x0 0xFFFFFFFF GACTSTA GACTSTA 8 1 GPENDSTA GPENDSTA 9 1 NESTSTA NESTSTA 0 8 IACTR1 IACTR1 Interrupt ACTIVE Register 0x300 32 write-only n 0x0 0xFFFFFFFF IACTS12_31 IACTS 12 20 IACTS2_3 IACTS 2 2 IACTR2 IACTR2 Interrupt ACTIVE Register 0x304 32 write-only n 0x0 0xFFFFFFFF IACTS IACTS 0 32 IACTR3 IACTR3 Interrupt ACTIVE Register 0x308 32 write-only n 0x0 0xFFFFFFFF IACTS IACTS 0 32 IACTR4 IACTR4 Interrupt ACTIVE Register 0x30C 32 write-only n 0x0 0xFFFFFFFF IACTS IACTS 0 8 IENR1 IENR1 Interrupt Setting Register 0x100 32 write-only n 0x0 0xFFFFFFFF INTEN INTEN 12 20 IENR2 IENR2 Interrupt Setting Register 0x104 32 write-only n 0x0 0xFFFFFFFF INTEN INTEN 0 32 IENR3 IENR3 Interrupt Setting Register 0x108 32 write-only n 0x0 0xFFFFFFFF INTEN INTEN 0 32 IENR4 IENR4 Interrupt Setting Register 0x10C 32 write-only n 0x0 0xFFFFFFFF INTEN INTEN 0 8 IPR1 IPR1 Interrupt Pending Register 0x20 32 read-only n 0x0 0xFFFFFFFF PENDSTA12_31 PENDSTA 12 20 PENDSTA2_3 PENDSTA 2 2 IPR2 IPR2 Interrupt Pending Register 0x24 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 0 32 IPR3 IPR3 Interrupt Pending Register 0x28 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 0 32 IPR4 IPR4 Interrupt Pending Register 0x2C 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 0 8 IPRIOR0 IPRIOR0 Interrupt Priority Register 0x400 8 read-write n 0x0 0xFFFFFFFF IPRIOR1 IPRIOR1 Interrupt Priority Register 0x401 8 read-write n 0x0 0xFFFFFFFF IPRIOR10 IPRIOR10 Interrupt Priority Register 0x40A 8 read-write n 0x0 0xFFFFFFFF IPRIOR100 IPRIOR100 Interrupt Priority Register 0x464 8 read-write n 0x0 0xFFFFFFFF IPRIOR101 IPRIOR101 Interrupt Priority Register 0x465 8 read-write n 0x0 0xFFFFFFFF IPRIOR102 IPRIOR102 Interrupt Priority Register 0x466 8 read-write n 0x0 0xFFFFFFFF IPRIOR103 IPRIOR103 Interrupt Priority Register 0x467 8 read-write n 0x0 0xFFFFFFFF IPRIOR104 IPRIOR104 Interrupt Priority Register 0x468 8 read-write n 0x0 0xFFFFFFFF IPRIOR105 IPRIOR105 Interrupt Priority Register 0x469 8 read-write n 0x0 0xFFFFFFFF IPRIOR106 IPRIOR106 Interrupt Priority Register 0x46A 8 read-write n 0x0 0xFFFFFFFF IPRIOR107 IPRIOR107 Interrupt Priority Register 0x46B 8 read-write n 0x0 0xFFFFFFFF IPRIOR108 IPRIOR108 Interrupt Priority Register 0x46C 8 read-write n 0x0 0xFFFFFFFF IPRIOR109 IPRIOR109 Interrupt Priority Register 0x46D 8 read-write n 0x0 0xFFFFFFFF IPRIOR11 IPRIOR11 Interrupt Priority Register 0x40B 8 read-write n 0x0 0xFFFFFFFF IPRIOR110 IPRIOR110 Interrupt Priority Register 0x46E 8 read-write n 0x0 0xFFFFFFFF IPRIOR111 IPRIOR111 Interrupt Priority Register 0x46F 8 read-write n 0x0 0xFFFFFFFF IPRIOR112 IPRIOR112 Interrupt Priority Register 0x470 8 read-write n 0x0 0xFFFFFFFF IPRIOR113 IPRIOR113 Interrupt Priority Register 0x471 8 read-write n 0x0 0xFFFFFFFF IPRIOR114 IPRIOR114 Interrupt Priority Register 0x472 8 read-write n 0x0 0xFFFFFFFF IPRIOR115 IPRIOR115 Interrupt Priority Register 0x473 8 read-write n 0x0 0xFFFFFFFF IPRIOR116 IPRIOR16 Interrupt Priority Register 0x474 8 read-write n 0x0 0xFFFFFFFF IPRIOR117 IPRIOR17 Interrupt Priority Register 0x475 8 read-write n 0x0 0xFFFFFFFF IPRIOR118 IPRIOR18 Interrupt Priority Register 0x476 8 read-write n 0x0 0xFFFFFFFF IPRIOR119 IPRIOR19 Interrupt Priority Register 0x477 8 read-write n 0x0 0xFFFFFFFF IPRIOR12 IPRIOR12 Interrupt Priority Register 0x40C 8 read-write n 0x0 0xFFFFFFFF IPRIOR120 IPRIOR120 Interrupt Priority Register 0x478 8 read-write n 0x0 0xFFFFFFFF IPRIOR121 IPRIOR121 Interrupt Priority Register 0x479 8 read-write n 0x0 0xFFFFFFFF IPRIOR122 IPRIOR122 Interrupt Priority Register 0x47A 8 read-write n 0x0 0xFFFFFFFF IPRIOR123 IPRIOR123 Interrupt Priority Register 0x47B 8 read-write n 0x0 0xFFFFFFFF IPRIOR124 IPRIOR124 Interrupt Priority Register 0x47C 8 read-write n 0x0 0xFFFFFFFF IPRIOR125 IPRIOR125 Interrupt Priority Register 0x47D 8 read-write n 0x0 0xFFFFFFFF IPRIOR126 IPRIOR126 Interrupt Priority Register 0x47E 8 read-write n 0x0 0xFFFFFFFF IPRIOR127 IPRIOR127 Interrupt Priority Register 0x47F 8 read-write n 0x0 0xFFFFFFFF IPRIOR128 IPRIOR128 Interrupt Priority Register 0x480 8 read-write n 0x0 0xFFFFFFFF IPRIOR129 IPRIOR129 Interrupt Priority Register 0x481 8 read-write n 0x0 0xFFFFFFFF IPRIOR13 IPRIOR13 Interrupt Priority Register 0x40D 8 read-write n 0x0 0xFFFFFFFF IPRIOR130 IPRIOR130 Interrupt Priority Register 0x482 8 read-write n 0x0 0xFFFFFFFF IPRIOR131 IPRIOR131 Interrupt Priority Register 0x483 8 read-write n 0x0 0xFFFFFFFF IPRIOR132 IPRIOR132 Interrupt Priority Register 0x484 8 read-write n 0x0 0xFFFFFFFF IPRIOR133 IPRIOR133 Interrupt Priority Register 0x485 8 read-write n 0x0 0xFFFFFFFF IPRIOR134 IPRIOR134 Interrupt Priority Register 0x486 8 read-write n 0x0 0xFFFFFFFF IPRIOR135 IPRIOR135 Interrupt Priority Register 0x487 8 read-write n 0x0 0xFFFFFFFF IPRIOR136 IPRIOR136 Interrupt Priority Register 0x488 8 read-write n 0x0 0xFFFFFFFF IPRIOR137 IPRIOR137 Interrupt Priority Register 0x489 8 read-write n 0x0 0xFFFFFFFF IPRIOR138 IPRIOR138 Interrupt Priority Register 0x48A 8 read-write n 0x0 0xFFFFFFFF IPRIOR139 IPRIOR139 Interrupt Priority Register 0x48B 8 read-write n 0x0 0xFFFFFFFF IPRIOR14 IPRIOR14 Interrupt Priority Register 0x40E 8 read-write n 0x0 0xFFFFFFFF IPRIOR140 IPRIOR140 Interrupt Priority Register 0x48C 8 read-write n 0x0 0xFFFFFFFF IPRIOR141 IPRIOR141 Interrupt Priority Register 0x48D 8 read-write n 0x0 0xFFFFFFFF IPRIOR142 IPRIOR142 Interrupt Priority Register 0x48E 8 read-write n 0x0 0xFFFFFFFF IPRIOR143 IPRIOR143 Interrupt Priority Register 0x48F 8 read-write n 0x0 0xFFFFFFFF IPRIOR144 IPRIOR144 Interrupt Priority Register 0x490 8 read-write n 0x0 0xFFFFFFFF IPRIOR145 IPRIOR145 Interrupt Priority Register 0x491 8 read-write n 0x0 0xFFFFFFFF IPRIOR146 IPRIOR146 Interrupt Priority Register 0x492 8 read-write n 0x0 0xFFFFFFFF IPRIOR147 IPRIOR147 Interrupt Priority Register 0x493 8 read-write n 0x0 0xFFFFFFFF IPRIOR148 IPRIOR148 Interrupt Priority Register 0x494 8 read-write n 0x0 0xFFFFFFFF IPRIOR149 IPRIOR149 Interrupt Priority Register 0x495 8 read-write n 0x0 0xFFFFFFFF IPRIOR15 IPRIOR15 Interrupt Priority Register 0x40F 8 read-write n 0x0 0xFFFFFFFF IPRIOR150 IPRIOR150 Interrupt Priority Register 0x496 8 read-write n 0x0 0xFFFFFFFF IPRIOR151 IPRIOR151 Interrupt Priority Register 0x497 8 read-write n 0x0 0xFFFFFFFF IPRIOR152 IPRIOR152 Interrupt Priority Register 0x498 8 read-write n 0x0 0xFFFFFFFF IPRIOR153 IPRIOR153 Interrupt Priority Register 0x499 8 read-write n 0x0 0xFFFFFFFF IPRIOR154 IPRIOR154 Interrupt Priority Register 0x49A 8 read-write n 0x0 0xFFFFFFFF IPRIOR155 IPRIOR155 Interrupt Priority Register 0x49B 8 read-write n 0x0 0xFFFFFFFF IPRIOR156 IPRIOR156 Interrupt Priority Register 0x49C 8 read-write n 0x0 0xFFFFFFFF IPRIOR157 IPRIOR157 Interrupt Priority Register 0x49D 8 read-write n 0x0 0xFFFFFFFF IPRIOR158 IPRIOR158 Interrupt Priority Register 0x49E 8 read-write n 0x0 0xFFFFFFFF IPRIOR159 IPRIOR159 Interrupt Priority Register 0x49F 8 read-write n 0x0 0xFFFFFFFF IPRIOR16 IPRIOR6 Interrupt Priority Register 0x410 8 read-write n 0x0 0xFFFFFFFF IPRIOR160 IPRIOR160 Interrupt Priority Register 0x4A0 8 read-write n 0x0 0xFFFFFFFF IPRIOR161 IPRIOR161 Interrupt Priority Register 0x4A1 8 read-write n 0x0 0xFFFFFFFF IPRIOR162 IPRIOR162 Interrupt Priority Register 0x4A2 8 read-write n 0x0 0xFFFFFFFF IPRIOR163 IPRIOR163 Interrupt Priority Register 0x4A3 8 read-write n 0x0 0xFFFFFFFF IPRIOR164 IPRIOR164 Interrupt Priority Register 0x4A4 8 read-write n 0x0 0xFFFFFFFF IPRIOR165 IPRIOR165 Interrupt Priority Register 0x4A5 8 read-write n 0x0 0xFFFFFFFF IPRIOR166 IPRIOR166 Interrupt Priority Register 0x4A6 8 read-write n 0x0 0xFFFFFFFF IPRIOR167 IPRIOR167 Interrupt Priority Register 0x4A7 8 read-write n 0x0 0xFFFFFFFF IPRIOR168 IPRIOR168 Interrupt Priority Register 0x4A8 8 read-write n 0x0 0xFFFFFFFF IPRIOR169 IPRIOR169 Interrupt Priority Register 0x4A9 8 read-write n 0x0 0xFFFFFFFF IPRIOR17 IPRIOR7 Interrupt Priority Register 0x411 8 read-write n 0x0 0xFFFFFFFF IPRIOR170 IPRIOR170 Interrupt Priority Register 0x4AA 8 read-write n 0x0 0xFFFFFFFF IPRIOR171 IPRIOR171 Interrupt Priority Register 0x4AB 8 read-write n 0x0 0xFFFFFFFF IPRIOR172 IPRIOR172 Interrupt Priority Register 0x4AC 8 read-write n 0x0 0xFFFFFFFF IPRIOR173 IPRIOR173 Interrupt Priority Register 0x4AD 8 read-write n 0x0 0xFFFFFFFF IPRIOR174 IPRIOR174 Interrupt Priority Register 0x4AE 8 read-write n 0x0 0xFFFFFFFF IPRIOR175 IPRIOR175 Interrupt Priority Register 0x4AF 8 read-write n 0x0 0xFFFFFFFF IPRIOR176 IPRIOR176 Interrupt Priority Register 0x4B0 8 read-write n 0x0 0xFFFFFFFF IPRIOR177 IPRIOR177 Interrupt Priority Register 0x4B1 8 read-write n 0x0 0xFFFFFFFF IPRIOR178 IPRIOR178 Interrupt Priority Register 0x4B2 8 read-write n 0x0 0xFFFFFFFF IPRIOR179 IPRIOR179 Interrupt Priority Register 0x4B3 8 read-write n 0x0 0xFFFFFFFF IPRIOR18 IPRIOR8 Interrupt Priority Register 0x412 8 read-write n 0x0 0xFFFFFFFF IPRIOR180 IPRIOR180 Interrupt Priority Register 0x4B4 8 read-write n 0x0 0xFFFFFFFF IPRIOR181 IPRIOR181 Interrupt Priority Register 0x4B5 8 read-write n 0x0 0xFFFFFFFF IPRIOR182 IPRIOR182 Interrupt Priority Register 0x4B6 8 read-write n 0x0 0xFFFFFFFF IPRIOR183 IPRIOR183 Interrupt Priority Register 0x4B7 8 read-write n 0x0 0xFFFFFFFF IPRIOR184 IPRIOR184 Interrupt Priority Register 0x4B8 8 read-write n 0x0 0xFFFFFFFF IPRIOR185 IPRIOR185 Interrupt Priority Register 0x4B9 8 read-write n 0x0 0xFFFFFFFF IPRIOR186 IPRIOR186 Interrupt Priority Register 0x4BA 8 read-write n 0x0 0xFFFFFFFF IPRIOR187 IPRIOR187 Interrupt Priority Register 0x4BB 8 read-write n 0x0 0xFFFFFFFF IPRIOR188 IPRIOR188 Interrupt Priority Register 0x4BC 8 read-write n 0x0 0xFFFFFFFF IPRIOR189 IPRIOR189 Interrupt Priority Register 0x4BD 8 read-write n 0x0 0xFFFFFFFF IPRIOR19 IPRIOR9 Interrupt Priority Register 0x413 8 read-write n 0x0 0xFFFFFFFF IPRIOR190 IPRIOR190 Interrupt Priority Register 0x4BE 8 read-write n 0x0 0xFFFFFFFF IPRIOR191 IPRIOR191 Interrupt Priority Register 0x4BF 8 read-write n 0x0 0xFFFFFFFF IPRIOR192 IPRIOR192 Interrupt Priority Register 0x4C0 8 read-write n 0x0 0xFFFFFFFF IPRIOR193 IPRIOR193 Interrupt Priority Register 0x4C1 8 read-write n 0x0 0xFFFFFFFF IPRIOR194 IPRIOR194 Interrupt Priority Register 0x4C2 8 read-write n 0x0 0xFFFFFFFF IPRIOR195 IPRIOR195 Interrupt Priority Register 0x4C3 8 read-write n 0x0 0xFFFFFFFF IPRIOR196 IPRIOR196 Interrupt Priority Register 0x4C4 8 read-write n 0x0 0xFFFFFFFF IPRIOR197 IPRIOR197 Interrupt Priority Register 0x4C5 8 read-write n 0x0 0xFFFFFFFF IPRIOR198 IPRIOR198 Interrupt Priority Register 0x4C6 8 read-write n 0x0 0xFFFFFFFF IPRIOR199 IPRIOR199 Interrupt Priority Register 0x4C7 8 read-write n 0x0 0xFFFFFFFF IPRIOR2 IPRIOR2 Interrupt Priority Register 0x402 8 read-write n 0x0 0xFFFFFFFF IPRIOR20 IPRIOR20 Interrupt Priority Register 0x414 8 read-write n 0x0 0xFFFFFFFF IPRIOR200 IPRIOR200 Interrupt Priority Register 0x4C8 8 read-write n 0x0 0xFFFFFFFF IPRIOR201 IPRIOR201 Interrupt Priority Register 0x4C9 8 read-write n 0x0 0xFFFFFFFF IPRIOR202 IPRIOR202 Interrupt Priority Register 0x4CA 8 read-write n 0x0 0xFFFFFFFF IPRIOR203 IPRIOR203 Interrupt Priority Register 0x4CB 8 read-write n 0x0 0xFFFFFFFF IPRIOR204 IPRIOR204 Interrupt Priority Register 0x4CC 8 read-write n 0x0 0xFFFFFFFF IPRIOR205 IPRIOR205 Interrupt Priority Register 0x4CD 8 read-write n 0x0 0xFFFFFFFF IPRIOR206 IPRIOR206 Interrupt Priority Register 0x4CE 8 read-write n 0x0 0xFFFFFFFF IPRIOR207 IPRIOR207 Interrupt Priority Register 0x4CF 8 read-write n 0x0 0xFFFFFFFF IPRIOR208 IPRIOR208 Interrupt Priority Register 0x4D0 8 read-write n 0x0 0xFFFFFFFF IPRIOR209 IPRIOR209 Interrupt Priority Register 0x4D1 8 read-write n 0x0 0xFFFFFFFF IPRIOR21 IPRIOR21 Interrupt Priority Register 0x415 8 read-write n 0x0 0xFFFFFFFF IPRIOR210 IPRIOR210 Interrupt Priority Register 0x4D2 8 read-write n 0x0 0xFFFFFFFF IPRIOR211 IPRIOR211 Interrupt Priority Register 0x4D3 8 read-write n 0x0 0xFFFFFFFF IPRIOR212 IPRIOR212 Interrupt Priority Register 0x4D4 8 read-write n 0x0 0xFFFFFFFF IPRIOR213 IPRIOR213 Interrupt Priority Register 0x4D5 8 read-write n 0x0 0xFFFFFFFF IPRIOR214 IPRIOR214 Interrupt Priority Register 0x4D6 8 read-write n 0x0 0xFFFFFFFF IPRIOR215 IPRIOR215 Interrupt Priority Register 0x4D7 8 read-write n 0x0 0xFFFFFFFF IPRIOR216 IPRIOR26 Interrupt Priority Register 0x4D8 8 read-write n 0x0 0xFFFFFFFF IPRIOR217 IPRIOR27 Interrupt Priority Register 0x4D9 8 read-write n 0x0 0xFFFFFFFF IPRIOR218 IPRIOR28 Interrupt Priority Register 0x4DA 8 read-write n 0x0 0xFFFFFFFF IPRIOR219 IPRIOR29 Interrupt Priority Register 0x4DB 8 read-write n 0x0 0xFFFFFFFF IPRIOR22 IPRIOR22 Interrupt Priority Register 0x416 8 read-write n 0x0 0xFFFFFFFF IPRIOR220 IPRIOR220 Interrupt Priority Register 0x4DC 8 read-write n 0x0 0xFFFFFFFF IPRIOR221 IPRIOR221 Interrupt Priority Register 0x4DD 8 read-write n 0x0 0xFFFFFFFF IPRIOR222 IPRIOR222 Interrupt Priority Register 0x4DE 8 read-write n 0x0 0xFFFFFFFF IPRIOR223 IPRIOR223 Interrupt Priority Register 0x4DF 8 read-write n 0x0 0xFFFFFFFF IPRIOR224 IPRIOR224 Interrupt Priority Register 0x4E0 8 read-write n 0x0 0xFFFFFFFF IPRIOR225 IPRIOR225 Interrupt Priority Register 0x4E1 8 read-write n 0x0 0xFFFFFFFF IPRIOR226 IPRIOR226 Interrupt Priority Register 0x4E2 8 read-write n 0x0 0xFFFFFFFF IPRIOR227 IPRIOR227 Interrupt Priority Register 0x4E3 8 read-write n 0x0 0xFFFFFFFF IPRIOR228 IPRIOR228 Interrupt Priority Register 0x4E4 8 read-write n 0x0 0xFFFFFFFF IPRIOR229 IPRIOR229 Interrupt Priority Register 0x4E5 8 read-write n 0x0 0xFFFFFFFF IPRIOR23 IPRIOR23 Interrupt Priority Register 0x417 8 read-write n 0x0 0xFFFFFFFF IPRIOR230 IPRIOR230 Interrupt Priority Register 0x4E6 8 read-write n 0x0 0xFFFFFFFF IPRIOR231 IPRIOR231 Interrupt Priority Register 0x4E7 8 read-write n 0x0 0xFFFFFFFF IPRIOR232 IPRIOR232 Interrupt Priority Register 0x4E8 8 read-write n 0x0 0xFFFFFFFF IPRIOR233 IPRIOR233 Interrupt Priority Register 0x4E9 8 read-write n 0x0 0xFFFFFFFF IPRIOR234 IPRIOR234 Interrupt Priority Register 0x4EA 8 read-write n 0x0 0xFFFFFFFF IPRIOR235 IPRIOR235 Interrupt Priority Register 0x4EB 8 read-write n 0x0 0xFFFFFFFF IPRIOR236 IPRIOR236 Interrupt Priority Register 0x4EC 8 read-write n 0x0 0xFFFFFFFF IPRIOR237 IPRIOR237 Interrupt Priority Register 0x4ED 8 read-write n 0x0 0xFFFFFFFF IPRIOR238 IPRIOR238 Interrupt Priority Register 0x4EE 8 read-write n 0x0 0xFFFFFFFF IPRIOR239 IPRIOR239 Interrupt Priority Register 0x4EF 8 read-write n 0x0 0xFFFFFFFF IPRIOR24 IPRIOR24 Interrupt Priority Register 0x418 8 read-write n 0x0 0xFFFFFFFF IPRIOR240 IPRIOR240 Interrupt Priority Register 0x4F0 8 read-write n 0x0 0xFFFFFFFF IPRIOR241 IPRIOR241 Interrupt Priority Register 0x4F1 8 read-write n 0x0 0xFFFFFFFF IPRIOR242 IPRIOR242 Interrupt Priority Register 0x4F2 8 read-write n 0x0 0xFFFFFFFF IPRIOR243 IPRIOR243 Interrupt Priority Register 0x4F3 8 read-write n 0x0 0xFFFFFFFF IPRIOR244 IPRIOR244 Interrupt Priority Register 0x4F4 8 read-write n 0x0 0xFFFFFFFF IPRIOR245 IPRIOR245 Interrupt Priority Register 0x4F5 8 read-write n 0x0 0xFFFFFFFF IPRIOR246 IPRIOR246 Interrupt Priority Register 0x4F6 8 read-write n 0x0 0xFFFFFFFF IPRIOR247 IPRIOR247 Interrupt Priority Register 0x4F7 8 read-write n 0x0 0xFFFFFFFF IPRIOR248 IPRIOR248 Interrupt Priority Register 0x4F8 8 read-write n 0x0 0xFFFFFFFF IPRIOR249 IPRIOR249 Interrupt Priority Register 0x4F9 8 read-write n 0x0 0xFFFFFFFF IPRIOR25 IPRIOR25 Interrupt Priority Register 0x419 8 read-write n 0x0 0xFFFFFFFF IPRIOR250 IPRIOR250 Interrupt Priority Register 0x4FA 8 read-write n 0x0 0xFFFFFFFF IPRIOR251 IPRIOR251 Interrupt Priority Register 0x4FB 8 read-write n 0x0 0xFFFFFFFF IPRIOR252 IPRIOR252 Interrupt Priority Register 0x4FC 8 read-write n 0x0 0xFFFFFFFF IPRIOR253 IPRIOR253 Interrupt Priority Register 0x4FD 8 read-write n 0x0 0xFFFFFFFF IPRIOR254 IPRIOR254 Interrupt Priority Register 0x4FE 8 read-write n 0x0 0xFFFFFFFF IPRIOR255 IPRIOR255 Interrupt Priority Register 0x4FF 8 read-write n 0x0 0xFFFFFFFF IPRIOR26 IPRIOR26 Interrupt Priority Register 0x41A 8 read-write n 0x0 0xFFFFFFFF IPRIOR27 IPRIOR27 Interrupt Priority Register 0x41B 8 read-write n 0x0 0xFFFFFFFF IPRIOR28 IPRIOR28 Interrupt Priority Register 0x41C 8 read-write n 0x0 0xFFFFFFFF IPRIOR29 IPRIOR29 Interrupt Priority Register 0x41D 8 read-write n 0x0 0xFFFFFFFF IPRIOR3 IPRIOR3 Interrupt Priority Register 0x403 8 read-write n 0x0 0xFFFFFFFF IPRIOR30 IPRIOR30 Interrupt Priority Register 0x41E 8 read-write n 0x0 0xFFFFFFFF IPRIOR31 IPRIOR31 Interrupt Priority Register 0x41F 8 read-write n 0x0 0xFFFFFFFF IPRIOR32 IPRIOR32 Interrupt Priority Register 0x420 8 read-write n 0x0 0xFFFFFFFF IPRIOR33 IPRIOR33 Interrupt Priority Register 0x421 8 read-write n 0x0 0xFFFFFFFF IPRIOR34 IPRIOR34 Interrupt Priority Register 0x422 8 read-write n 0x0 0xFFFFFFFF IPRIOR35 IPRIOR35 Interrupt Priority Register 0x423 8 read-write n 0x0 0xFFFFFFFF IPRIOR36 IPRIOR36 Interrupt Priority Register 0x424 8 read-write n 0x0 0xFFFFFFFF IPRIOR37 IPRIOR37 Interrupt Priority Register 0x425 8 read-write n 0x0 0xFFFFFFFF IPRIOR38 IPRIOR38 Interrupt Priority Register 0x426 8 read-write n 0x0 0xFFFFFFFF IPRIOR39 IPRIOR39 Interrupt Priority Register 0x427 8 read-write n 0x0 0xFFFFFFFF IPRIOR4 IPRIOR4 Interrupt Priority Register 0x404 8 read-write n 0x0 0xFFFFFFFF IPRIOR40 IPRIOR40 Interrupt Priority Register 0x428 8 read-write n 0x0 0xFFFFFFFF IPRIOR41 IPRIOR41 Interrupt Priority Register 0x429 8 read-write n 0x0 0xFFFFFFFF IPRIOR42 IPRIOR42 Interrupt Priority Register 0x42A 8 read-write n 0x0 0xFFFFFFFF IPRIOR43 IPRIOR43 Interrupt Priority Register 0x42B 8 read-write n 0x0 0xFFFFFFFF IPRIOR44 IPRIOR44 Interrupt Priority Register 0x42C 8 read-write n 0x0 0xFFFFFFFF IPRIOR45 IPRIOR45 Interrupt Priority Register 0x42D 8 read-write n 0x0 0xFFFFFFFF IPRIOR46 IPRIOR46 Interrupt Priority Register 0x42E 8 read-write n 0x0 0xFFFFFFFF IPRIOR47 IPRIOR47 Interrupt Priority Register 0x42F 8 read-write n 0x0 0xFFFFFFFF IPRIOR48 IPRIOR48 Interrupt Priority Register 0x430 8 read-write n 0x0 0xFFFFFFFF IPRIOR49 IPRIOR49 Interrupt Priority Register 0x431 8 read-write n 0x0 0xFFFFFFFF IPRIOR5 IPRIOR5 Interrupt Priority Register 0x405 8 read-write n 0x0 0xFFFFFFFF IPRIOR50 IPRIOR50 Interrupt Priority Register 0x432 8 read-write n 0x0 0xFFFFFFFF IPRIOR51 IPRIOR51 Interrupt Priority Register 0x433 8 read-write n 0x0 0xFFFFFFFF IPRIOR52 IPRIOR52 Interrupt Priority Register 0x434 8 read-write n 0x0 0xFFFFFFFF IPRIOR53 IPRIOR53 Interrupt Priority Register 0x435 8 read-write n 0x0 0xFFFFFFFF IPRIOR54 IPRIOR54 Interrupt Priority Register 0x436 8 read-write n 0x0 0xFFFFFFFF IPRIOR55 IPRIOR55 Interrupt Priority Register 0x437 8 read-write n 0x0 0xFFFFFFFF IPRIOR56 IPRIOR56 Interrupt Priority Register 0x438 8 read-write n 0x0 0xFFFFFFFF IPRIOR57 IPRIOR57 Interrupt Priority Register 0x439 8 read-write n 0x0 0xFFFFFFFF IPRIOR58 IPRIOR58 Interrupt Priority Register 0x43A 8 read-write n 0x0 0xFFFFFFFF IPRIOR59 IPRIOR59 Interrupt Priority Register 0x43B 8 read-write n 0x0 0xFFFFFFFF IPRIOR6 IPRIOR6 Interrupt Priority Register 0x406 8 read-write n 0x0 0xFFFFFFFF IPRIOR60 IPRIOR60 Interrupt Priority Register 0x43C 8 read-write n 0x0 0xFFFFFFFF IPRIOR61 IPRIOR61 Interrupt Priority Register 0x43D 8 read-write n 0x0 0xFFFFFFFF IPRIOR62 IPRIOR62 Interrupt Priority Register 0x43E 8 read-write n 0x0 0xFFFFFFFF IPRIOR63 IPRIOR63 Interrupt Priority Register 0x43F 8 read-write n 0x0 0xFFFFFFFF IPRIOR64 IPRIOR64 Interrupt Priority Register 0x440 8 read-write n 0x0 0xFFFFFFFF IPRIOR65 IPRIOR65 Interrupt Priority Register 0x441 8 read-write n 0x0 0xFFFFFFFF IPRIOR66 IPRIOR66 Interrupt Priority Register 0x442 8 read-write n 0x0 0xFFFFFFFF IPRIOR67 IPRIOR67 Interrupt Priority Register 0x443 8 read-write n 0x0 0xFFFFFFFF IPRIOR68 IPRIOR68 Interrupt Priority Register 0x444 8 read-write n 0x0 0xFFFFFFFF IPRIOR69 IPRIOR69 Interrupt Priority Register 0x445 8 read-write n 0x0 0xFFFFFFFF IPRIOR7 IPRIOR7 Interrupt Priority Register 0x407 8 read-write n 0x0 0xFFFFFFFF IPRIOR70 IPRIOR70 Interrupt Priority Register 0x446 8 read-write n 0x0 0xFFFFFFFF IPRIOR71 IPRIOR71 Interrupt Priority Register 0x447 8 read-write n 0x0 0xFFFFFFFF IPRIOR72 IPRIOR72 Interrupt Priority Register 0x448 8 read-write n 0x0 0xFFFFFFFF IPRIOR73 IPRIOR73 Interrupt Priority Register 0x449 8 read-write n 0x0 0xFFFFFFFF IPRIOR74 IPRIOR74 Interrupt Priority Register 0x44A 8 read-write n 0x0 0xFFFFFFFF IPRIOR75 IPRIOR75 Interrupt Priority Register 0x44B 8 read-write n 0x0 0xFFFFFFFF IPRIOR76 IPRIOR76 Interrupt Priority Register 0x44C 8 read-write n 0x0 0xFFFFFFFF IPRIOR77 IPRIOR77 Interrupt Priority Register 0x44D 8 read-write n 0x0 0xFFFFFFFF IPRIOR78 IPRIOR78 Interrupt Priority Register 0x44E 8 read-write n 0x0 0xFFFFFFFF IPRIOR79 IPRIOR79 Interrupt Priority Register 0x44F 8 read-write n 0x0 0xFFFFFFFF IPRIOR8 IPRIOR8 Interrupt Priority Register 0x408 8 read-write n 0x0 0xFFFFFFFF IPRIOR80 IPRIOR80 Interrupt Priority Register 0x450 8 read-write n 0x0 0xFFFFFFFF IPRIOR81 IPRIOR81 Interrupt Priority Register 0x451 8 read-write n 0x0 0xFFFFFFFF IPRIOR82 IPRIOR82 Interrupt Priority Register 0x452 8 read-write n 0x0 0xFFFFFFFF IPRIOR83 IPRIOR83 Interrupt Priority Register 0x453 8 read-write n 0x0 0xFFFFFFFF IPRIOR84 IPRIOR84 Interrupt Priority Register 0x454 8 read-write n 0x0 0xFFFFFFFF IPRIOR85 IPRIOR85 Interrupt Priority Register 0x455 8 read-write n 0x0 0xFFFFFFFF IPRIOR86 IPRIOR86 Interrupt Priority Register 0x456 8 read-write n 0x0 0xFFFFFFFF IPRIOR87 IPRIOR87 Interrupt Priority Register 0x457 8 read-write n 0x0 0xFFFFFFFF IPRIOR88 IPRIOR88 Interrupt Priority Register 0x458 8 read-write n 0x0 0xFFFFFFFF IPRIOR89 IPRIOR89 Interrupt Priority Register 0x459 8 read-write n 0x0 0xFFFFFFFF IPRIOR9 IPRIOR9 Interrupt Priority Register 0x409 8 read-write n 0x0 0xFFFFFFFF IPRIOR90 IPRIOR90 Interrupt Priority Register 0x45A 8 read-write n 0x0 0xFFFFFFFF IPRIOR91 IPRIOR91 Interrupt Priority Register 0x45B 8 read-write n 0x0 0xFFFFFFFF IPRIOR92 IPRIOR92 Interrupt Priority Register 0x45C 8 read-write n 0x0 0xFFFFFFFF IPRIOR93 IPRIOR93 Interrupt Priority Register 0x45D 8 read-write n 0x0 0xFFFFFFFF IPRIOR94 IPRIOR94 Interrupt Priority Register 0x45E 8 read-write n 0x0 0xFFFFFFFF IPRIOR95 IPRIOR95 Interrupt Priority Register 0x45F 8 read-write n 0x0 0xFFFFFFFF IPRIOR96 IPRIOR96 Interrupt Priority Register 0x460 8 read-write n 0x0 0xFFFFFFFF IPRIOR97 IPRIOR97 Interrupt Priority Register 0x461 8 read-write n 0x0 0xFFFFFFFF IPRIOR98 IPRIOR98 Interrupt Priority Register 0x462 8 read-write n 0x0 0xFFFFFFFF IPRIOR99 IPRIOR99 Interrupt Priority Register 0x463 8 read-write n 0x0 0xFFFFFFFF IPRR1 IPRR1 Interrupt Pending Clear Register 0x280 32 write-only n 0x0 0xFFFFFFFF PENDRESET12_31 PENDRESET 12 20 PENDRESET2_3 PENDRESET 2 2 IPRR2 IPRR2 Interrupt Pending Clear Register 0x284 32 write-only n 0x0 0xFFFFFFFF PENDRESET PENDRESET 0 32 IPRR3 IPRR3 Interrupt Pending Clear Register 0x288 32 write-only n 0x0 0xFFFFFFFF PENDRESET PENDRESET 0 32 IPRR4 IPRR4 Interrupt Pending Clear Register 0x28C 32 write-only n 0x0 0xFFFFFFFF PENDRESET PENDRESET 0 8 IPSR1 IPSR1 Interrupt Pending Register 0x200 32 write-only n 0x0 0xFFFFFFFF PENDSET12_31 PENDSET 12 20 PENDSET2_3 PENDSET 2 2 IPSR2 IPSR2 Interrupt Pending Register 0x204 32 write-only n 0x0 0xFFFFFFFF PENDSET PENDSET 0 32 IPSR3 IPSR3 Interrupt Pending Register 0x208 32 write-only n 0x0 0xFFFFFFFF PENDSET PENDSET 0 32 IPSR4 IPSR4 Interrupt Pending Register 0x20C 32 write-only n 0x0 0xFFFFFFFF PENDSET PENDSET 0 8 IRER1 IRER1 Interrupt Clear Register 0x180 32 write-only n 0x0 0xFFFFFFFF INTRSET INTRSET 12 20 IRER2 IRER2 Interrupt Clear Register 0x184 32 write-only n 0x0 0xFFFFFFFF INTRSET INTRSET 0 32 IRER3 IRER3 Interrupt Clear Register 0x188 32 write-only n 0x0 0xFFFFFFFF INTRSET INTRSET 0 32 IRER4 IRER4 Interrupt Clear Register 0x18C 32 write-only n 0x0 0xFFFFFFFF INTRSET INTRSET 0 8 ISR1 ISR1 Interrupt Status Register 0x0 32 read-only n 0xC 0xFFFFFFFF INTENSTA12_31 Interrupt ID Status 12 20 INTENSTA2_3 Interrupt ID Status 2 2 ISR2 ISR2 Interrupt Status Register 0x4 32 read-only n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 0 32 ISR3 ISR3 Interrupt Status Register 0x8 32 read-only n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 0 32 ISR4 ISR4 Interrupt Status Register 0xC 32 read-only n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 0 8 ITHRESDR ITHRESDR Interrupt Priority Register 0x40 32 read-write n 0x0 0xFFFFFFFF THRESHOLD THRESHOLD 0 8 SCTLR SCTLR System Control Register 0xD10 32 read-write n 0x0 0xFFFFFFFF SETEVENT SETEVENT 5 1 SEVONPEND SEVONPEND 4 1 SLEEPDEEP SLEEPDEEP 2 1 SLEEPONEXIT SLEEPONEXIT 1 1 SYSRESET SYSRESET 31 1 WFITOWFE WFITOWFE 3 1 STK_CMPHR System compare high register 0x1014 32 read-write n 0x0 0xFFFFFFFF CMPH CMPH 0 32 STK_CMPLR System compare low register 0x1010 32 read-write n 0x0 0xFFFFFFFF CMPL CMPL 0 32 STK_CNTH System counter high register 0x100C 32 read-write n 0x0 0xFFFFFFFF CNTH CNTH 0 32 STK_CNTL System counter low register 0x1008 32 read-write n 0x0 0xFFFFFFFF CNTL CNTL 0 32 STK_CTLR STK_CTLR System counter control register 0x1000 32 n 0x0 0xFFFFFFFF INIT System Initialization update 5 1 read-write MODE System Mode 4 1 read-write STCLK System selects the clock source 2 1 read-write STE System counter enable 0 1 read-write STIE System counter interrupt enable 1 1 read-write STRE System reload register 3 1 read-write SWIE System software triggered interrupts enable 31 1 read-write STK_SR System START 0x1004 32 read-write n 0x0 0xFFFFFFFF CNTIF CNTIF 0 1 VTFADDRR0 VTFADDRR0 Interrupt 0 address Register 0x60 32 read-write n 0x0 0xFFFFFFFF ADDR0 ADDR0 1 31 VTF0EN VTF0EN 0 1 VTFADDRR1 VTFADDRR1 Interrupt 1 address Register 0x64 32 read-write n 0x0 0xFFFFFFFF ADDR1 ADDR1 1 31 VTF1EN VTF1EN 0 1 VTFADDRR2 VTFADDRR2 Interrupt 2 address Register 0x68 32 read-write n 0x0 0xFFFFFFFF ADDR2 ADDR2 1 31 VTF2EN VTF2EN 0 1 VTFADDRR3 VTFADDRR3 Interrupt 3 address Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ADDR3 ADDR3 1 31 VTF3EN VTF3EN 0 1 VTFIDR VTFIDR ID Config Register 0x50 32 read-write n 0x0 0xFFFFFFFF VTFID0 VTFID0 0 8 VTFID1 VTFID1 8 8 VTFID2 VTFID2 16 8 VTFID3 VTFID3 24 8 PWR Power control PWR 0x40007000 0x0 0x400 registers n PVD PVD through EXTI line detection interrupt 17 CSR CSR Power control register (PWR_CSR) 0x4 32 n 0x0 0xFFFFFFFF EWUP Enable WKUP pin 8 1 read-write PVDO PVD Output 2 1 read-only SBF STANDBY Flag 1 1 read-only WUF Wake-Up Flag 0 1 read-only CTLR CTLR Power control register (PWR_CTRL) 0x0 32 read-write n 0x0 0xFFFFFFFF CSBF Clear STANDBY Flag 3 1 CWUF Clear Wake-up Flag 2 1 DBP Disable Backup Domain write protection 8 1 LPDS Low Power Deep Sleep 0 1 PDDS Power Down Deep Sleep 1 1 PLS PVD Level Selection 5 3 PVDE Power Voltage Detector Enable 4 1 R2K_STYEN standby 2k ram enable 16 1 R2K_VBATEN VBAT 30k ram enable 18 1 R30K_STYEN standby 30k ram enable 17 1 R30K_VBATEN VBAT 30k ram enable 19 1 RAM_LVEN Ram LV Enable 20 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers n RCC RCC global interrupt 21 AHBPCENR AHBPCENR AHB Peripheral Clock enable register (RCC_AHBPCENR) 0x14 32 read-write n 0x14 0xFFFFFFFF CRCEN CRC clock enable 6 1 DMA1EN DMA clock enable 0 1 DMA2EN DMA2 clock enable 1 1 DVP_EN DVP clock enable 13 1 ETHMACEN Ethernet MAC clock enable 14 1 ETHMACRXEN Ethernet MAC RX clock enable 16 1 ETHMACTXEN Ethernet MAC TX clock enable 15 1 FLITFEN FLITF clock enable 4 1 FSMCEN FSMC clock enable 8 1 OTG_EN OTG clock enable 12 1 SDIOEN SDIO clock enable 10 1 SRAMEN SRAM interface clock enable 2 1 TRNG_EN TRNG clock enable 9 1 USBHS_EN USBHS clock enable 11 1 AHBRSTR AHBRSTR AHB reset register (RCC_APHBRSTR) 0x28 32 n 0x0 0xFFFFFFFF DVPRST DVP reset 13 1 read-only ETHMACRST Ethernet MAC reset 14 1 read-write USBHDRST USBHD reset 12 1 read-write APB1PCENR APB1PCENR APB1 peripheral clock enable register (RCC_APB1PCENR) 0x1C 32 read-write n 0x0 0xFFFFFFFF BKPEN Backup interface clock enable 27 1 CAN1EN CAN1 clock enable 25 1 CAN2EN CAN2 clock enable 26 1 DACEN DAC interface clock enable 29 1 I2C1EN I2C 1 clock enable 21 1 I2C2EN I2C 2 clock enable 22 1 PWREN Power interface clock enable 28 1 SPI2EN SPI 2 clock enable 14 1 SPI3EN SPI 3 clock enable 15 1 TIM2EN Timer 2 clock enable 0 1 TIM3EN Timer 3 clock enable 1 1 TIM4EN Timer 4 clock enable 2 1 TIM5EN Timer 5 clock enable 3 1 TIM6EN Timer 6 clock enable 4 1 TIM7EN Timer 7 clock enable 5 1 UART4EN UART 4 clock enable 19 1 UART5EN UART 5 clock enable 20 1 USART2EN USART 2 clock enable 17 1 USART3EN USART 3 clock enable 18 1 USART6_EN USART 6 clock enable 6 1 USART7_EN USART 7 clock enable 7 1 USART8_EN USART 8 clock enable 8 1 USBDEN USBD clock enable 23 1 WWDGEN Window watchdog clock enable 11 1 APB1PRSTR APB1PRSTR APB1 peripheral reset register (RCC_APB1PRSTR) 0x10 32 read-write n 0x0 0xFFFFFFFF BKPRST Backup interface reset 27 1 CAN1RST CAN1 reset 25 1 CAN2RST CAN2 reset 26 1 DACRST DAC interface reset 29 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 PWRRST Power interface reset 28 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 TIM2RST Timer 2 reset 0 1 TIM3RST Timer 3 reset 1 1 TIM4RST Timer 4 reset 2 1 TIM5RST Timer 5 reset 3 1 TIM6RST Timer 6 reset 4 1 TIM7RST Timer 7 reset 5 1 UART6RST UART 6 reset 6 1 UART7RST UART 7 reset 7 1 UART8RST UART 8 reset 8 1 USART2RST USART 2 reset 17 1 USART3RST USART 3 reset 18 1 USART4RST USART 4 reset 19 1 USART5RST USART 5 reset 20 1 USBDRST USBD reset 23 1 WWDGRST Window watchdog reset 11 1 APB2PCENR APB2PCENR APB2 peripheral clock enable register (RCC_APB2PCENR) 0x18 32 read-write n 0x0 0xFFFFFFFF ADC1EN ADC1 interface clock enable 9 1 ADC2EN ADC 2 interface clock enable 10 1 AFIOEN Alternate function I/O clock enable 0 1 IOPAEN I/O port A clock enable 2 1 IOPBEN I/O port B clock enable 3 1 IOPCEN I/O port C clock enable 4 1 IOPDEN I/O port D clock enable 5 1 IOPEEN I/O port E clock enable 6 1 SPI1EN SPI 1 clock enable 12 1 TIM10_EN TIM10 Timer clock enable 20 1 TIM1EN TIM1 Timer clock enable 11 1 TIM8EN TIM8 Timer clock enable 13 1 TIM9_EN TIM9 Timer clock enable 19 1 USART1EN USART1 clock enable 14 1 APB2PRSTR APB2PRSTR APB2 peripheral reset register (RCC_APB2PRSTR) 0xC 32 read-write n 0x0 0xFFFFFFFF ADC1RST ADC 1 interface reset 9 1 ADC2RST ADC 2 interface reset 10 1 AFIORST Alternate function I/O reset 0 1 IOPARST IO port A reset 2 1 IOPBRST IO port B reset 3 1 IOPCRST IO port C reset 4 1 IOPDRST IO port D reset 5 1 IOPERST IO port E reset 6 1 SPI1RST SPI 1 reset 12 1 TIM10RST TIM10 timer reset 20 1 TIM1RST TIM1 timer reset 11 1 TIM8RST TIM8 timer reset 13 1 TIM9RST TIM9 timer reset 19 1 USART1RST USART1 reset 14 1 BDCTLR BDCTLR Backup domain control register (RCC_BDCTLR) 0x20 32 n 0x0 0xFFFFFFFF BDRST Backup domain software reset 16 1 read-write LSEBYP External Low Speed oscillator bypass 2 1 read-write LSEON External Low Speed oscillator enable 0 1 read-write LSERDY External Low Speed oscillator ready 1 1 read-only RTCEN RTC clock enable 15 1 read-write RTCSEL RTC clock source selection 8 2 read-write CFGR0 CFGR0 Clock configuration register (RCC_CFGR0) 0x4 32 n 0x0 0xFFFFFFFF ADCPRE ADC prescaler 14 2 read-write ADC_CLK_ADJ ADC clock ADJ 31 1 read-write HPRE AHB prescaler 4 4 read-write MCO Microcontroller clock output 24 4 read-write PLLMUL PLL Multiplication Factor 18 4 read-write PLLSRC PLL entry clock source 16 1 read-write PLLXTPRE HSE divider for PLL entry 17 1 read-write PPRE1 APB Low speed prescaler (APB1) 8 3 read-write PPRE2 APB High speed prescaler (APB2) 11 3 read-write SW System clock Switch 0 2 read-write SWS System Clock Switch Status 2 2 read-only USBPRE USB prescaler 22 2 read-write CFGR2 CFGR2 Clock configuration register2 (RCC_CFGR2) 0x2C 32 read-write n 0x0 0xFFFFFFFF ETH1G_125M_EN ETH1G _125M clock enable 22 1 ETH1G_SRC ETH1G clock source 20 2 I2S2SRC I2S2 clock source 17 1 I2S3SRC I2S3 clock source 18 1 PLL2MUL PLL2 Multiplication Factor 8 4 PLL3MUL PLL3 Multiplication Factor 12 4 PREDIV1 PREDIV1 division factor 0 4 PREDIV1SRC PREDIV1 entry clock source 16 1 PREDIV2 PREDIV2 division factor 4 4 TRNG_SRC TRNG clock source 19 1 USBHS_CKPEF_SEL USB HS Peference Clock source 28 2 USBHS_CLK_SRC USB HS clock source 31 1 USBHS_PLLALIVE USB HS Multiplication control 30 1 USBHS_PLL_SRC USB HS Multiplication Factor clock source 27 1 USBHS_PREDIY USB HS PREDIV division factor 24 3 CTLR CTLR Clock control register 0x0 32 n 0x83 0xFFFFFFFF CSSON Clock Security System enable 19 1 read-write HSEBYP External High Speed clock Bypass 18 1 read-write HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSICAL Internal High Speed clock Calibration 8 8 read-only HSION Internal High Speed clock enable 0 1 read-write HSIRDY Internal High Speed clock ready flag 1 1 read-only HSITRIM Internal High Speed clock trimming 3 5 read-write PLL2ON PLL2 enable 26 1 read-write PLL2RDY PLL2 clock ready flag 27 1 read-only PLL3ON PLL3 enable 28 1 read-write PLL3RDY PLL3 clock ready flag 29 1 read-only PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only INTR INTR Clock interrupt register (RCC_INTR) 0x8 32 n 0x0 0xFFFFFFFF CSSC Clock security system interrupt clear 23 1 write-only CSSF Clock Security System Interrupt flag 7 1 read-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only HSERDYF HSE Ready Interrupt flag 3 1 read-only HSERDYIE HSE Ready Interrupt Enable 11 1 read-write HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write LSERDYC LSE Ready Interrupt Clear 17 1 write-only LSERDYF LSE Ready Interrupt flag 1 1 read-only LSERDYIE LSE Ready Interrupt Enable 9 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only LSIRDYF LSI Ready Interrupt flag 0 1 read-only LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write PLL2RDYC PLL2 Ready Interrupt Clear 21 1 write-only PLL2RDYF PLL2 Ready Interrupt flag 5 1 read-only PLL2RDYIE PLL2 Ready Interrupt Enable 13 1 read-write PLL3RDYC PLL3 Ready Interrupt Clear 22 1 write-only PLL3RDYF PLL3 Ready Interrupt flag 6 1 read-only PLL3RDYIE PLL3 Ready Interrupt Enable 14 1 read-write PLLRDYC PLL Ready Interrupt Clear 20 1 write-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write RSTSCKR RSTSCKR Control/status register (RCC_RSTSCKR) 0x24 32 n 0xC000000 0xFFFFFFFF IWDGRSTF Independent watchdog reset flag 29 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write LSION Internal low speed oscillator enable 0 1 read-write LSIRDY Internal low speed oscillator ready 1 1 read-only PINRSTF PIN reset flag 26 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write RMVF Remove reset flag 24 1 read-write SFTRSTF Software reset flag 28 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write RNG Random number generator RNG 0x40023C00 0x0 0x400 registers n RNG RNG interrupt 63 CR CR control register 0x0 32 read-write n 0x0 0xFFFFFFFF IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 DR DR data register 0x8 32 read-only n 0x0 0xFFFFFFFF RNDATA Random data 0 32 SR SR status register 0x4 32 n 0x0 0xFFFFFFFF CECS Clock error current status 1 1 read-only CEIS Clock error interrupt status 5 1 read-write DRDY Data ready 0 1 read-only SECS Seed error current status 2 1 read-only SEIS Seed error interrupt status 6 1 read-write RTC Real time clock RTC 0x40002800 0x0 0x400 registers n RTC RTC global interrupt 19 RTCAlarm RTC Alarms through EXTI line interrupt 57 ALRMH ALRMH RTC Alarm Register High 0x20 32 write-only n 0xFFFF 0xFFFFFFFF ALRH RTC alarm register high 0 16 ALRML ALRML RTC Alarm Register Low 0x24 32 write-only n 0xFFFF 0xFFFFFFFF ALRL RTC alarm register low 0 16 CNTH CNTH RTC Counter Register High 0x18 32 read-write n 0x0 0xFFFFFFFF CNTH RTC counter register high 0 16 CNTL CNTL RTC Counter Register Low 0x1C 32 read-write n 0x0 0xFFFFFFFF CNTL RTC counter register Low 0 16 CTLRH CTLRH RTC Control Register High 0x0 32 read-write n 0x0 0xFFFFFFFF ALRIE Alarm interrupt Enable 1 1 OWIE Overflow interrupt Enable 2 1 SECIE Second interrupt Enable 0 1 CTLRL CTLRL RTC Control Register Low 0x4 32 n 0x20 0xFFFFFFFF ALRF Alarm Flag 1 1 read-write CNF Configuration Flag 4 1 read-write OWF Overflow Flag 2 1 read-write RSF Registers Synchronized Flag 3 1 read-write RTOFF RTC operation OFF 5 1 read-only SECF Second Flag 0 1 read-write DIVH DIVH RTC Prescaler Divider Register High 0x10 32 read-only n 0x0 0xFFFFFFFF DIVH RTC prescaler divider register high 0 4 DIVL DIVL RTC Prescaler Divider Register Low 0x14 32 read-only n 0x8000 0xFFFFFFFF DIVL RTC prescaler divider register Low 0 16 PSCRH PSCRH RTC Prescaler Load Register High 0x8 32 write-only n 0x0 0xFFFFFFFF PRLH RTC Prescaler Load Register High 0 4 PSCRL PSCRL RTC Prescaler Load Register Low 0xC 32 write-only n 0x8000 0xFFFFFFFF PRLL RTC Prescaler Divider Register Low 0 16 SDIO Secure digital input/output interface SDIO 0x40018000 0x0 0x400 registers n SDIO SDIO global interrupt 65 ARG ARG Bits 31:0 = : Command argument 0x8 32 read-write n 0x0 0xFFFFFFFF CMDARG Command argument 0 32 CLKCR CLKCR SDI clock control register (SDIO_CLKCR) 0x4 32 read-write n 0x0 0xFFFFFFFF BYPASS Clock divider bypass enable bit 10 1 CLKDIV Clock divide factor 0 8 CLKEN Clock enable bit 8 1 HWFC_EN HW Flow Control enable 14 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 PWRSAV Power saving configuration bit 9 1 WIDBUS Wide bus mode enable bit 11 2 CMD CMD SDIO command register (SDIO_CMD) 0xC 32 read-write n 0x0 0xFFFFFFFF CE_ATACMD CE-ATA command 14 1 CMDINDEX Command index 0 6 CPSMEN Command path state machine (CPSM) Enable bit 10 1 ENCMDcompl Enable CMD completion 12 1 nIEN not Interrupt Enable 13 1 SDIOSuspend SD I/O suspend command 11 1 WAITINT CPSM waits for interrupt request 8 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) 9 1 WAITRESP Wait for response bits 6 2 DCOUNT DCOUNT Bits 24:0 = DATACOUNT: Data count value 0x30 32 read-only n 0x0 0xFFFFFFFF DATACOUNT Data count value 0 25 DCTRL DCTRL SDIO data control register (SDIO_DCTRL) 0x2C 32 read-write n 0x0 0xFFFFFFFF DBLOCKSIZE Data block size 4 4 DMAEN DMA enable bit 3 1 DTDIR Data transfer direction selection 1 1 DTEN Data transfer enabled bit 0 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer 2 1 PWSTART Read wait start 8 1 PWSTOP Read wait stop 9 1 RWMOD Read wait mode 10 1 SDIOEN SD I/O enable functions 11 1 DLEN DLEN Bits 24:0 = DATALENGTH: Data length value 0x28 32 read-write n 0x0 0xFFFFFFFF DATALENGTH Data length value 0 25 DTIMER DTIMER Bits 31:0 = DATATIME: Data timeout period 0x24 32 read-write n 0x0 0xFFFFFFFF DATATIME Data timeout period 0 32 FIFO FIFO bits 31:0 = FIFOData: Receive and transmit FIFO data 0x80 32 read-write n 0x0 0xFFFFFFFF FIFOData Receive and transmit FIFO data 0 32 FIFOCNT FIFOCNT Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO 0x48 32 read-only n 0x0 0xFFFFFFFF FIF0COUNT Remaining number of words to be written to or read from the FIFO 0 32 ICR ICR SDIO interrupt clear register (SDIO_ICR) 0x38 32 read-write n 0x0 0xFFFFFFFF CCRCFAILC CCRCFAIL flag clear bit 0 1 CEATAENDC CEATAEND flag clear bit 23 1 CMDRENDC CMDREND flag clear bit 6 1 CMDSENTC CMDSENT flag clear bit 7 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DATAENDC DATAEND flag clear bit 8 1 DBCKENDC DBCKEND flag clear bit 10 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 RXOVERRC RXOVERR flag clear bit 5 1 SDIOITC SDIOIT flag clear bit 22 1 STBITERRC STBITERR flag clear bit 9 1 TXUNDERRC TXUNDERR flag clear bit 4 1 MASK MASK SDIO mask register (SDIO_MASK) 0x3C 32 read-write n 0x0 0xFFFFFFFF CCRCFAILIE Command CRC fail interrupt enable 0 1 CEATENDIE CE-ATA command completion signal received interrupt enable 23 1 CMDACTIE Command acting interrupt enable 11 1 CMDRENDIE Command response received interrupt enable 6 1 CMDSENTIE Command sent interrupt enable 7 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DATAENDIE Data end interrupt enable 8 1 DBACKENDIE Data block end interrupt enable 10 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 DTIMEOUTIE Data timeout interrupt enable 3 1 RXACTIE Data receive acting interrupt enable 13 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 STBITERRIE Start bit error interrupt enable 9 1 TXACTIE Data transmit acting interrupt enable 12 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 POWER POWER Bits 1:0 = PWRCTRL: Power supply control bits 0x0 32 read-write n 0x0 0xFFFFFFFF PWRCTRL Power supply control bits 0 2 RESP1 RESP1 Bits 31:0 = CARDSTATUS1 0x14 32 read-only n 0x0 0xFFFFFFFF CARDSTATUS1 Card status 1 0 32 RESP2 RESP2 Bits 31:0 = CARDSTATUS2 0x18 32 read-only n 0x0 0xFFFFFFFF CARDSTATUS2 Card status 2 0 32 RESP3 RESP3 Bits 31:0 = CARDSTATUS3 0x1C 32 read-only n 0x0 0xFFFFFFFF CARDSTATUS3 Card status 3 0 32 RESP4 RESP4 Bits 31:0 = CARDSTATUS4 0x20 32 read-only n 0x0 0xFFFFFFFF CARDSTATUS4 Card status 4 0 32 RESPCMD RESPCMD SDIO command register 0x10 32 read-only n 0x0 0xFFFFFFFF RESPCMD Response command index 0 6 STA STA SDIO status register (SDIO_STA) 0x34 32 read-only n 0x0 0xFFFFFFFF CCRCFAIL Command response received (CRC check failed) 0 1 CEATAEND CE-ATA command completion signal received for CMD61 23 1 CMDACT Command transfer in progress 11 1 CMDREND Command response received (CRC check passed) 6 1 CMDSENT Command sent (no response required) 7 1 CTIMEOUT Command response timeout 2 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 DBCKEND Data block sent/received (CRC check passed) 10 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 DTIMEOUT Data timeout 3 1 RXACT Data receive in progress 13 1 RXDAVL Data available in receive FIFO 21 1 RXFIFOE Receive FIFO empty 19 1 RXFIFOF Receive FIFO full 17 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 RXOVERR Received FIFO overrun error 5 1 SDIOIT SDIO interrupt received 22 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 TXACT Data transmit in progress 12 1 TXDAVL Data available in transmit FIFO 20 1 TXFIFOE Transmit FIFO empty 18 1 TXFIFOF Transmit FIFO full 16 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 TXUNDERR Transmit FIFO underrun error 4 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers n SPI1 SPI1 global interrupt 51 CRCR CRCR CRCR polynomial register 0x10 32 read-write n 0x7 0xFFFFFFFF CRCPOLY CRC polynomial register 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF ERRIE Error interrupt enable 5 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 DATAR DATAR data register 0xC 32 read-write n 0x0 0xFFFFFFFF DATAR Data register 0 16 HSCR HSCR high speed control register 0x24 32 read-write n 0x0 0xFFFFFFFF HSRXEN High speed mode read enable 0 1 RCRCR RCRCR RX CRC register 0x14 32 read-only n 0x0 0xFFFFFFFF RXCRC Rx CRC register 0 16 SPI_I2S_CFGR SPI_I2S_CFGR SPI_I2S configure register 0x1C 32 read-write n 0x0 0xFFFFFFFF CHLEN Channel length (number of bits per audio channel) 0 1 CKPOL steady state clock polarity 3 1 DATLEN DATLEN[1:0] bits (Data length to be transferred) 1 2 I2SCFG I2SCFG[1:0] bits (I2S configuration mode) 8 2 I2SE I2S Enable 10 1 I2SMOD I2S mode selection 11 1 I2SSTD I2SSTD[1:0] bits (I2S standard selection) 4 2 PCMSYNC PCM frame synchronization 7 1 STATR STATR status register 0x8 32 n 0x2 0xFFFFFFFF BSY Busy flag 7 1 read-only CHSID Channel side 2 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only UDR Underrun flag 3 1 read-only TCRCR TCRCR TX CRC register 0x18 32 read-only n 0x0 0xFFFFFFFF TXCRC Tx CRC register 0 16 SPI2 Serial peripheral interface SPI 0x40003800 0x0 0x400 registers n SPI2 SPI2 global interrupt 52 CRCR CRCR CRCR polynomial register 0x10 32 read-write n 0x7 0xFFFFFFFF CRCPOLY CRC polynomial register 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF ERRIE Error interrupt enable 5 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 DATAR DATAR data register 0xC 32 read-write n 0x0 0xFFFFFFFF DATAR Data register 0 16 HSCR HSCR high speed control register 0x24 32 read-write n 0x0 0xFFFFFFFF HSRXEN High speed mode read enable 0 1 I2SCFGR I2SCFGR I2S configuration register 0x1C 32 read-write n 0x0 0xFFFFFFFF CHLEN Channel length (number of bits per audio channel) 0 1 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 I2SCFG I2S configuration mode 8 2 I2SE I2S Enable 10 1 I2SMOD I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSYNC PCM frame synchronization 7 1 I2SPR I2SPR I2S prescaler register 0x20 32 read-write n 0xA 0xFFFFFFFF I2SDIV I2S Linear prescaler 0 8 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 RCRCR RCRCR RX CRC register 0x14 32 read-only n 0x0 0xFFFFFFFF RXCRC Rx CRC register 0 16 STATR STATR status register 0x8 32 n 0x2 0xFFFFFFFF BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only TCRCR TCRCR TX CRC register 0x18 32 read-only n 0x0 0xFFFFFFFF TXCRC Tx CRC register 0 16 SPI3 Serial peripheral interface SPI 0x40003C00 0x0 0x400 registers n SPI3 SPI3 global interrupt 67 CRCR CRCR CRCR polynomial register 0x10 32 read-write n 0x7 0xFFFFFFFF CRCPOLY CRC polynomial register 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF ERRIE Error interrupt enable 5 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 DATAR DATAR data register 0xC 32 read-write n 0x0 0xFFFFFFFF DATAR Data register 0 16 HSCR HSCR high speed control register 0x24 32 read-write n 0x0 0xFFFFFFFF HSRXEN High speed mode read enable 0 1 I2SCFGR I2SCFGR I2S configuration register 0x1C 32 read-write n 0x0 0xFFFFFFFF CHLEN Channel length (number of bits per audio channel) 0 1 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 I2SCFG I2S configuration mode 8 2 I2SE I2S Enable 10 1 I2SMOD I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSYNC PCM frame synchronization 7 1 I2SPR I2SPR I2S prescaler register 0x20 32 read-write n 0xA 0xFFFFFFFF I2SDIV I2S Linear prescaler 0 8 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 RCRCR RCRCR RX CRC register 0x14 32 read-only n 0x0 0xFFFFFFFF RXCRC Rx CRC register 0 16 STATR STATR status register 0x8 32 n 0x2 0xFFFFFFFF BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only TCRCR TCRCR TX CRC register 0x18 32 read-only n 0x0 0xFFFFFFFF TXCRC Tx CRC register 0 16 TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers n TIM1_BRK TIM1 Break interrupt 40 TIM1_UP_ TIM1 Update interrupt 41 TIM1_TRG_COM TIM1 Trigger and Commutation interrupts 42 TIM1_CC TIM1 Capture Compare interrupt 43 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 RPTCR RPTCR repetition counter register 0x30 32 read-write n 0x0 0xFFFFFFFF RPTCR Repetition counter value 0 8 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM10 Advanced timer TIM 0x40015000 0x0 0x400 registers n TIM10_BRK TIM10 Break interrupt 94 TIM10_UP_ TIM10 Update interrupt 95 TIM10_TRG_COM TIM10 Trigger and Commutation interrupts 96 TIM10_CC TIM10 Capture Compare interrupt 97 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 RPTCR RPTCR repetition counter register 0x30 32 read-write n 0x0 0xFFFFFFFF RPTCR Repetition counter value 0 8 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM2 General purpose timer TIM 0x40000000 0x0 0x400 registers n TIM2 TIM2 global interrupt 44 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Compare selection 0 1 CCUS Update selection 2 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Brake generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/compare generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM3 General purpose timer TIM 0x40000400 0x0 0x400 registers n TIM3 TIM3 global interrupt 45 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Compare selection 0 1 CCUS Update selection 2 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Brake generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/compare generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM4 General purpose timer TIM 0x40000800 0x0 0x400 registers n TIM4 TIM4 global interrupt 46 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Compare selection 0 1 CCUS Update selection 2 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Brake generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/compare generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM5 General purpose timer TIM 0x40000C00 0x0 0x400 registers n TIM5 TIM5 global interrupt 66 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1FE Output compare 1 fast enable 2 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC2CE Output compare 2 clear enable 15 1 OC2FE Output compare 2 fast enable 10 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Compare selection 0 1 CCUS Update selection 2 1 MMS Master mode selection 4 3 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Brake generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/compare generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM6 Basic timer TIM 0x40001000 0x0 0x400 registers n TIM6 TIM6 Basic interrupt 70 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF MMS Master mode selection 4 3 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF UG Update generation 0 1 TIM7 Basic timer TIM 0x40001400 0x0 0x400 registers n TIM7 TIM8 Basic interrupt 71 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF MMS Master mode selection 4 3 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF UG Update generation 0 1 TIM8 Advanced timer TIM 0x40013400 0x0 0x400 registers n TIM8_BRK TIM8 Break interrupt 59 TIM8_UP_ TIM8 Update interrupt 60 TIM8_TRG_COM TIM8 Trigger and Commutation interrupts 61 TIM8_CC TIM8 Capture Compare interrupt 62 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 RPTCR RPTCR repetition counter register 0x30 32 read-write n 0x0 0xFFFFFFFF RPTCR Repetition counter value 0 8 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 TIM9 Advanced timer TIM 0x40014C00 0x0 0x400 registers n TIM9_BRK TIM9 Break interrupt 90 TIM9_UP_ TIM9 Update interrupt 91 TIM9_TRG_COM TIM9 Trigger and Commutation interrupts 92 TIM9_CC TIM9 Capture Compare interrupt 93 ATRLR ATRLR auto-reload register 0x2C 32 read-write n 0x0 0xFFFFFFFF ATRLR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0xFFFFFFFF AOE Automatic output enable 14 1 BKE Break enable 12 1 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0xFFFFFFFF CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4P Capture/Compare 3 output Polarity 13 1 CH1CVR CH1CVR capture/compare register 1 0x34 32 read-write n 0x0 0xFFFFFFFF CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 32 read-write n 0x0 0xFFFFFFFF CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 32 read-write n 0x0 0xFFFFFFFF CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 32 read-write n 0x0 0xFFFFFFFF CH4CVR Capture/Compare value 0 16 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0xFFFFFFFF CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 32 read-write n 0x0 0xFFFFFFFF CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 CNT CNT counter 0x24 32 read-write n 0x0 0xFFFFFFFF CNT counter value 0 16 CTLR1 CTLR1 control register 1 0x0 32 read-write n 0x0 0xFFFFFFFF ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 URS Update request source 2 1 CTLR2 CTLR2 control register 2 0x4 32 read-write n 0x0 0xFFFFFFFF CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 TI1S TI1 selection 7 1 DMAADR DMAADR DMA address for full transfer 0x4C 32 read-write n 0x0 0xFFFFFFFF DMAADR DMA register for burst accesses 0 16 DMACFGR DMACFGR DMA control register 0x48 32 read-write n 0x0 0xFFFFFFFF DBA DMA base address 0 5 DBL DMA burst length 8 5 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 32 read-write n 0x0 0xFFFFFFFF BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 32 read-write n 0x0 0xFFFFFFFF BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0xFFFFFFFF PSC Prescaler value 0 16 RPTCR RPTCR repetition counter register 0x30 32 read-write n 0x0 0xFFFFFFFF RPTCR Repetition counter value 0 8 SMCFGR SMCFGR slave mode control register 0x8 32 read-write n 0x0 0xFFFFFFFF ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 TS Trigger selection 4 3 SWEVGR SWEVGR event generation register 0x14 32 write-only n 0x0 0xFFFFFFFF BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 UART4 Universal synchronous asynchronous receiver transmitter USART 0x40004C00 0x0 0x400 registers n UART4 UART4 global interrupt 68 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only UART5 Universal synchronous asynchronous receiver transmitter USART 0x40005000 0x0 0x400 registers n UART5 UART5 global interrupt 69 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only UART6 Universal synchronous asynchronous receiver transmitter USART 0x40001800 0x0 0x400 registers n UART6 UART6 global interrupt 87 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only UART7 Universal synchronous asynchronous receiver transmitter USART 0x40001C00 0x0 0x400 registers n UART7 UART7 global interrupt 88 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only UART8 Universal synchronous asynchronous receiver transmitter USART 0x40002000 0x0 0x400 registers n UART8 UART8 global interrupt 89 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers n USART1 USART1 global interrupt 53 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only USART2 Universal synchronous asynchronous receiver transmitter USART 0x40004400 0x0 0x400 registers n USART2 USART2 global interrupt 54 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only USART3 Universal synchronous asynchronous receiver transmitter USART 0x40004800 0x0 0x400 registers n USART3 USART3 global interrupt 55 BRR BRR Baud rate register 0x8 32 read-write n 0x0 0xFFFFFFFF DIV_Fraction fraction of USARTDIV 0 4 DIV_Mantissa mantissa of USARTDIV 4 12 CTLR1 CTLR1 Control register 1 0xC 32 read-write n 0x0 0xFFFFFFFF IDLEIE IDLE interrupt enable 4 1 M Word length 12 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 RXNEIE RXNE interrupt enable 5 1 SBK Send break 0 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE TXE interrupt enable 7 1 UE USART enable 13 1 WAKE Wakeup method 11 1 CTLR2 CTLR2 Control register 2 0x10 32 read-write n 0x0 0xFFFFFFFF ADD Address of the USART node 0 4 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CTLR3 CTLR3 Control register 3 0x14 32 read-write n 0x0 0xFFFFFFFF CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NACK Smartcard NACK enable 4 1 RTSE RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATAR DATAR Data register 0x4 32 read-write n 0x0 0xFFFFFFFF DR Data value 0 9 GPR GPR Guard time and prescaler register 0x18 32 read-write n 0x0 0xFFFFFFFF GT Guard time value 8 8 PSC Prescaler value 0 8 STATR STATR Status register 0x0 32 n 0xC0 0xFFFFFFFF CTS CTS flag 9 1 read-write FE Framing error 1 1 read-only IDLE IDLE line detected 4 1 read-only LBD LIN break detection flag 8 1 read-write NE Noise error flag 2 1 read-only ORE Overrun error 3 1 read-only PE Parity error 0 1 read-only RXNE Read data register not empty 5 1 read-write TC Transmission complete 6 1 read-write TXE Transmit data register empty 7 1 read-only USB Universal serial bus full-speed device interface USB 0x40005C00 0x0 0x400 registers n USBWakeUp USB Device WakeUp from suspend through EXTI Line Interrupt 58 BTABLE BTABLE Buffer table address 0x50 32 read-write n 0x0 0xFFFFFFFF BTABLE Buffer table 3 13 CNTR USB_CNTR control register 0x40 16 read-write n 0x3 0xFFFFFFFF CTRM Correct transfer interrupt mask 15 1 ERRM Error interrupt mask 13 1 ESOFM Expected start of frame interrupt mask 8 1 FRES Force USB Reset 0 1 FSUSP Force suspend 3 1 LPMODE Low-power mode 2 1 PDWN Power down 1 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 RESETM USB reset interrupt mask 10 1 RESUME Resume request 4 1 SOFM Start of frame interrupt mask 9 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 DADDR DADDR device address 0x4C 16 read-write n 0x0 0xFFFFFFFF ADD Device address 0 7 EF Enable function 7 1 EP0R EP0R endpoint 0 register 0x0 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP1R EP1R endpoint 1 register 0x4 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP2R EP2R endpoint 2 register 0x8 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP3R EP3R endpoint 3 register 0xC 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP4R EP4R endpoint 4 register 0x10 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP5R EP5R endpoint 5 register 0x14 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP6R EP6R endpoint 6 register 0x18 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 EP7R EP7R endpoint 7 register 0x1C 16 read-write n 0x0 0xFFFFFFFF CTR_RX Correct transfer for reception 15 1 CTR_TX Correct Transfer for transmission 7 1 DTOG_RX Data Toggle, for reception transfers 14 1 DTOG_TX Data Toggle, for transmission transfers 6 1 EA Endpoint address 0 4 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 STAT_TX Status bits, for transmission transfers 4 2 FNR FNR frame number register 0x48 16 read-only n 0x0 0xFFFFFFFF FN Frame number 0 11 LCK Locked 13 1 LSOF Lost SOF 11 2 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 ISTR ISTR interrupt status register 0x44 16 read-write n 0x0 0xFFFFFFFF CTR Correct transfer 15 1 DIR Direction of transaction 4 1 EP_ID Endpoint Identifier 0 4 ERR Error 13 1 ESOF Expected start frame 8 1 PMAOVR Packet memory area over / underrun 14 1 RESET reset request 10 1 SOF start of frame 9 1 SUSP Suspend mode request 11 1 WKUP Wakeup 12 1 USBHD USB register USBHD 0x40023400 0x0 0x400 registers n USBHSWakeup USBHSWakeup 84 USBHS USBHS 85 UEP0_DMA B endpoint 0 DMA buffer address 0x1C 16 read-write n 0x0 0xFFFFFFFF UEP0_DMA endpoint 0 DMA buffer address 0 16 read-write UEP0_MAX_LEN endpoint 0 max acceptable length 0x98 16 read-write n 0x0 0xFFFFFFFF UEP0_MAX_LEN endpoint 0 max acceptable length 0 11 read-write UEP0_R_CTRL endpoint 0 send control 0xDB 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 0 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 0 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 0 synchronous trigger bit for the accept to prepare 3 2 read-write UEP0_T_CTRL endpoint 0 send control 0xDA 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 0 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 0 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 0 synchronous trigger bit for the sender to prepare 3 2 read-write UEP0_T_LEN endpoint 0 send the length 0xD8 16 read-write n 0x0 0xFFFFFFFF UEP0_T_LEN endpoint 0 send the length 0 11 read-write UEP10_MAX_LEN endpoint 10 max acceptable length 0xC0 16 read-write n 0x0 0xFFFFFFFF UEP10_MAX_LEN endpoint 10 max acceptable length 0 11 read-write UEP10_RX_DMA endpoint 10 DMA RX buffer address 0x44 16 read-write n 0x0 0xFFFFFFFF UEP10_RX_DMA endpoint 10 DMA buffer address 0 16 read-write UEP10_R_CTRL endpoint 10 send control 0x103 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 10 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 10 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 10 synchronous trigger bit for the accept to prepare 3 2 read-write UEP10_TX_DMA endpoint 10 DMA TX buffer address 0x80 16 read-write n 0x0 0xFFFFFFFF UEP10_TX_DMA endpoint 10 DMA buffer address 0 16 read-write UEP10_T_CTRL endpoint 10 send control 0x102 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 10 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 10 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 10 synchronous trigger bit for the sender to prepare 3 2 read-write UEP10_T_LEN endpoint 10 send the length 0x100 16 read-write n 0x0 0xFFFFFFFF UEP10_T_LEN endpoint 10 send the length 0 11 read-write UEP11_MAX_LEN endpoint 11 max acceptable length 0xC4 16 read-write n 0x0 0xFFFFFFFF UEP11_MAX_LEN endpoint 11 max acceptable length 0 11 read-write UEP11_RX_DMA endpoint 11 DMA RX buffer address 0x48 16 read-write n 0x0 0xFFFFFFFF UEP11_RX_DMA endpoint 11 DMA buffer address 0 16 read-write UEP11_R_CTRL endpoint 11 send control 0x107 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 11 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 11 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 11 synchronous trigger bit for the accept to prepare 3 2 read-write UEP11_TX_DMA endpoint 11 DMA TX buffer address 0x84 16 read-write n 0x0 0xFFFFFFFF UEP11_TX_DMA endpoint 11 DMA buffer address 0 16 read-write UEP11_T_CTRL endpoint 11 send control 0x106 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 11 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 11 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 11 synchronous trigger bit for the sender to prepare 3 2 read-write UEP11_T_LEN endpoint 11 send the length 0x104 16 read-write n 0x0 0xFFFFFFFF UEP0_T_LEN endpoint 11 send the length 0 11 read-write UEP12_MAX_LEN endpoint 12 max acceptable length 0xC8 16 read-write n 0x0 0xFFFFFFFF UEP12_MAX_LEN endpoint 12 max acceptable length 0 11 read-write UEP12_RX_DMA endpoint 12 DMA RX buffer address 0x4C 16 read-write n 0x0 0xFFFFFFFF UEP12_RX_DMA endpoint 12 DMA buffer address 0 16 read-write UEP12_R_CTRL endpoint 12 send control 0x10B 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 12 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 12 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 12 synchronous trigger bit for the accept to prepare 3 2 read-write UEP12_TX_DMA____UH_SPLIT_DATA endpoint 12 DMA TX buffer address 0x88 16 read-write n 0x0 0xFFFFFFFF UEP12_TX_DMA___UH_SPLIT_DATA endpoint 12 DMA buffer address 0 16 read-write UEP12_T_CTRL endpoint 12 send control 0x10A 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 12 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 12 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 12 synchronous trigger bit for the sender to prepare 3 2 read-write UEP12_T_LEN endpoint 12 send the length 0x108 16 read-write n 0x0 0xFFFFFFFF UEP0_T_LEN endpoint 12 send the length 0 11 read-write UEP13_MAX_LEN endpoint 13 max acceptable length 0xCC 16 read-write n 0x0 0xFFFFFFFF UEP13_MAX_LEN endpoint 13 max acceptable length 0 11 read-write UEP13_RX_DMA endpoint 13 DMA RX buffer address 0x50 16 read-write n 0x0 0xFFFFFFFF UEP13_RX_DMA endpoint 13 DMA buffer address 0 16 read-write UEP13_R_CTRL endpoint 13 send control 0x10F 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 13 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 13 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 13 synchronous trigger bit for the accept to prepare 3 2 read-write UEP13_TX_DMA endpoint 13 DMA TX buffer address 0x8C 16 read-write n 0x0 0xFFFFFFFF UEP13_TX_DMA endpoint 13 DMA buffer address 0 16 read-write UEP13_T_CTRL endpoint 13 send control 0x10E 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 13 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 13 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 13 synchronous trigger bit for the sender to prepare 3 2 read-write UEP13_T_LEN endpoint 13 send the length 0x10C 16 read-write n 0x0 0xFFFFFFFF UEP13_T_LEN endpoint 13 send the length 0 11 read-write UEP14_MAX_LEN endpoint 14 max acceptable length 0xD0 16 read-write n 0x0 0xFFFFFFFF UEP14_MAX_LEN endpoint 14 max acceptable length 0 11 read-write UEP14_RX_DMA endpoint 14 DMA RX buffer address 0x54 16 read-write n 0x0 0xFFFFFFFF UEP14_RX_DMA endpoint 14 DMA buffer address 0 16 read-write UEP14_R_CTRL endpoint 14 send control 0x113 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 14 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 14 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 14 synchronous trigger bit for the accept to prepare 3 2 read-write UEP14_TX_DMA endpoint 14 DMA TX buffer address 0x90 16 read-write n 0x0 0xFFFFFFFF UEP14_TX_DMA endpoint 14 DMA buffer address 0 16 read-write UEP14_T_CTRL endpoint 14 send control 0x112 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 14 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 14 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 14 synchronous trigger bit for the sender to prepare 3 2 read-write UEP14_T_LEN endpoint 14 send the length 0x110 16 read-write n 0x0 0xFFFFFFFF UEP14_T_LEN endpoint 14 send the length 0 11 read-write UEP15_MAX_LEN endpoint 15 max acceptable length 0xD4 16 read-write n 0x0 0xFFFFFFFF UEP15_MAX_LEN endpoint 15 max acceptable length 0 11 read-write UEP15_RX_DMA endpoint 15 DMA RX buffer address 0x58 16 read-write n 0x0 0xFFFFFFFF UEP15_RX_DMA endpoint 15 DMA buffer address 0 16 read-write UEP15_R_CTRL endpoint 15 send control 0x117 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 15 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 15 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 15 synchronous trigger bit for the accept to prepare 3 2 read-write UEP15_TX_DMA endpoint 15 DMA TX buffer address 0x94 16 read-write n 0x0 0xFFFFFFFF UEP15_TX_DMA endpoint 15 DMA buffer address 0 16 read-write UEP15_T_CTRL endpoint 15 send control 0x116 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 15 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 15 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 15 synchronous trigger bit for the sender to prepare 3 2 read-write UEP15_T_LEN endpoint 15 send the length 0x114 16 read-write n 0x0 0xFFFFFFFF UEP0_T_LEN endpoint 15 send the length 0 11 read-write UEP1_MAX_LEN endpoint 1 max acceptable length 0x9C 16 read-write n 0x0 0xFFFFFFFF UEP1_MAX_LEN endpoint 1 max acceptable length 0 11 read-write UEP1_RX_DMA endpoint 1 DMA RX buffer address 0x20 16 read-write n 0x0 0xFFFFFFFF UEP1_RX_DMA endpoint 1 DMA buffer address 0 16 read-write UEP1_R_CTRL endpoint 1 send control 0xDF 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 1 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 1 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 1 synchronous trigger bit for the accept to prepare 3 2 read-write UEP1_TX_DMA endpoint 1 DMA TX buffer address 0x5C 16 read-write n 0x0 0xFFFFFFFF UEP1_TX_DMA endpoint 1 DMA buffer address 0 16 read-write UEP1_T_CTRL endpoint 1 send control 0xDE 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 1 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 1 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 1 synchronous trigger bit for the sender to prepare 3 2 read-write UEP1_T_LEN endpoint 1 send the length 0xDC 16 read-write n 0x0 0xFFFFFFFF UEP1_T_LEN endpoint 1 send the length 0 11 read-write UEP2_MAX_LEN__UH_RX_MAX_LEN endpoint 2 max acceptable length 0xA0 16 read-write n 0x0 0xFFFFFFFF UEP2_MAX_LEN__UH_RX_MAX_LEN endpoint 2 max acceptable length 0 11 read-write UEP2_RX_DMA__UH_RX_DMA endpoint 2 DMA RX buffer address/UH_RX_DMA 0x24 16 read-write n 0x0 0xFFFFFFFF UEP2_RX_DMA__UH_RX_DMA endpoint 2 DMA buffer address 0 16 read-write UEP2_R_CTRL__UH_RX_CTRL endpoint 2 send control 0xE3 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO__bUH_R_AUTO_TOG endpoint 2 synchronous trigger bit automatic filp enables the control bit 5 1 read-only bUH_R_DATA_NO bUH_R_DATA_NO 6 1 read-write bUH_R_RES_NO bUH_R_RES_NO 2 1 read-write MASK_UEP_R_RES__MASK_UH_R_RES endpoint 2 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG__MASK_UH_R_TOG endpoint 2 synchronous trigger bit for the accept to prepare 3 2 read-write UEP2_TX_DMA endpoint 2 DMA TX buffer address 0x60 16 read-write n 0x0 0xFFFFFFFF UEP2_TX_DMA endpoint 2 DMA buffer address 0 16 read-write UEP2_T_CTRL endpoint 2 send control 0xE2 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 2 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 2 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 2 synchronous trigger bit for the sender to prepare 3 2 read-write UEP2_T_LEN__UH_EP_PID endpoint 2 send the length 0xE0 16 read-write n 0x0 0xFFFFFFFF UEP2_T_LEN__MASK_UH_ENDP__MASK_UH_TOKEN endpoint 2 send the length 0 11 read-write UEP3_MAX_LEN endpoint 3 MAX_LEN TX 0xA4 16 read-write n 0x0 0xFFFFFFFF UEP3_MAX_LEN endpoint 3 max acceptable length 0 11 read-write UEP3_RX_DMA endpoint 3 DMA RX buffer address 0x28 16 read-write n 0x0 0xFFFFFFFF UEP3_RX_DMA endpoint 3 DMA buffer address 0 16 read-write UEP3_R_CTRL endpoint 3 send control 0xE7 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 3 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 3 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 3 synchronous trigger bit for the accept to prepare 3 2 read-write UEP3_TX_DMA__UH_TX_DMA endpoint 3 DMA TX buffer address 0x64 16 read-write n 0x0 0xFFFFFFFF UEP3_TX_DMA__UH_TX_DMA endpoint 3 DMA buffer address 0 16 read-write UEP3_T_CTRL___UH_TX_CTRL endpoint 3 send control 0xE6 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO____bUH_T_AUTO_TOG endpoint 3 synchronous trigger bit automatic filp enables the control bit 5 1 read-write bUH_T_DATA_NO bUH_T_DATA_NO 6 1 read-write bUH_T_RES_NO bUH_T_RES_NO 2 1 read-write MASK_UEP_T_RES_____MASK_UH_T_RES endpoint 3 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG____MASK_UH_T_TOG endpoint 3 synchronous trigger bit for the sender to prepare 3 2 read-write UEP3_T_LEN___UH_TX_LEN_H endpoint 3 send the length 0xE4 16 read-write n 0x0 0xFFFFFFFF UEP3_T_LEN___UH_TX_LEN_H endpoint 3 send the length 0 11 read-write UEP4_MAX_LEN endpoint 4 max acceptable length 0xA8 16 read-write n 0x0 0xFFFFFFFF UEP4_MAX_LEN endpoint 4 max acceptable length 0 11 read-write UEP4_RX_DMA endpoint 4 DMA RX buffer address 0x2C 16 read-write n 0x0 0xFFFFFFFF UEP4_RX_DMA endpoint 4 DMA buffer address 0 16 read-write UEP4_R_CTRL endpoint 4 send control 0xEB 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 4 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 4 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 4 synchronous trigger bit for the accept to prepare 3 2 read-write UEP4_TX_DMA endpoint 4 DMA TX buffer address 0x68 16 read-write n 0x0 0xFFFFFFFF UEP4_TX_DMA endpoint 4 DMA buffer address 0 16 read-write UEP4_T_CTRL endpoint 4 send control 0xEA 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 4 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 4 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 4 synchronous trigger bit for the sender to prepare 3 2 read-write UEP4_T_LEN endpoint 4 send the length 0xE8 16 read-write n 0x0 0xFFFFFFFF UEP4_T_LEN endpoint 0 send the length 0 11 read-write UEP5_MAX_LEN endpoint 5 max acceptable length 0xAC 16 read-write n 0x0 0xFFFFFFFF UEP5_MAX_LEN endpoint 5 max acceptable length 0 11 read-write UEP5_RX_DMA endpoint 5 DMA RX buffer address 0x30 16 read-write n 0x0 0xFFFFFFFF UEP5_DMA endpoint 5 DMA buffer address 0 16 read-write UEP5_R_CTRL endpoint 5 send control 0xEF 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 5 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 5 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 5 synchronous trigger bit for the accept to prepare 3 2 read-write UEP5_TX_DMA endpoint 5 DMA TX buffer address 0x6C 16 read-write n 0x0 0xFFFFFFFF UEP5_TX_DMA endpoint 5 DMA buffer address 0 16 read-write UEP5_T_CTRL endpoint 5 send control 0xEE 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 5 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 5 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 5 synchronous trigger bit for the sender to prepare 3 2 read-write UEP5_T_LEN endpoint 5 send the length 0xEC 16 read-write n 0x0 0xFFFFFFFF UEP5_T_LEN endpoint 5 send the length 0 11 read-write UEP6_MAX_LEN endpoint 6 max acceptable length 0xB0 16 read-write n 0x0 0xFFFFFFFF UEP6_MAX_LEN endpoint 6 max acceptable length 0 11 read-write UEP6_RX_DMA endpoint 6 DMA RX buffer address 0x34 16 read-write n 0x0 0xFFFFFFFF UEP6_RX_DMA endpoint 6 DMA buffer address 0 16 read-write UEP6_R_CTRL endpoint 6 send control 0xF3 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 6 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 6 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 6 synchronous trigger bit for the accept to prepare 3 2 read-write UEP6_TX_DMA endpoint 6 DMA TX buffer address 0x70 16 read-write n 0x0 0xFFFFFFFF UEP6_TX_DMA endpoint 6 DMA buffer address 0 16 read-write UEP6_T_CTRL endpoint 6 send control 0xF2 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 6 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 6 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 6 synchronous trigger bit for the sender to prepare 3 2 read-write UEP6_T_LEN endpoint 6 send the length 0xF0 16 read-write n 0x0 0xFFFFFFFF UEP6_T_LEN endpoint 6 send the length 0 11 read-write UEP7_MAX_LEN endpoint 7 max acceptable length 0xB4 16 read-write n 0x0 0xFFFFFFFF UEP7_MAX_LEN endpoint 7 max acceptable length 0 11 read-write UEP7_RX_DMA endpoint 7 DMA RX buffer address 0x38 16 read-write n 0x0 0xFFFFFFFF UEP7_RX_DMA endpoint 7 DMA buffer address 0 16 read-write UEP7_R_CTRL endpoint 7 send control 0xF7 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 7 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 7 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 7 synchronous trigger bit for the accept to prepare 3 2 read-write UEP7_TX_DMA endpoint 7 DMA TX buffer address 0x74 16 read-write n 0x0 0xFFFFFFFF UEP7_TX_DMA endpoint 7 DMA buffer address 0 16 read-write UEP7_T_CTRL endpoint 7 send control 0xF6 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 7 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 7 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 7 synchronous trigger bit for the sender to prepare 3 2 read-write UEP7_T_LEN endpoint 7 send the length 0xF4 16 read-write n 0x0 0xFFFFFFFF UEP7_T_LEN endpoint 7 send the length 0 11 read-write UEP8_MAX_LEN endpoint 8 max acceptable length 0xB8 16 read-write n 0x0 0xFFFFFFFF UEP8_MAX_LEN endpoint 8 max acceptable length 0 11 read-write UEP8_RX_DMA endpoint 8 DMA RX buffer address 0x3C 16 read-write n 0x0 0xFFFFFFFF UEP8_RX_DMA endpoint 8 DMA buffer address 0 16 read-write UEP8_R_CTRL endpoint 8 send control 0xFB 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 8 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 8 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 8 synchronous trigger bit for the accept to prepare 3 2 read-write UEP8_TX_DMA endpoint 8 DMA TX buffer address 0x78 16 read-write n 0x0 0xFFFFFFFF UEP8_TX_DMA endpoint 8 DMA buffer address 0 16 read-write UEP8_T_CTRL endpoint 8 send control 0xFA 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 8 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 8 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 8 synchronous trigger bit for the sender to prepare 3 2 read-write UEP8_T_LEN endpoint 8 send the length 0xF8 16 read-write n 0x0 0xFFFFFFFF UEP8_T_LEN endpoint 8 send the length 0 11 read-write UEP9_MAX_LEN endpoint 9 max acceptable length 0xBC 16 read-write n 0x0 0xFFFFFFFF UEP9_MAX_LEN endpoint 9 max acceptable length 0 11 read-write UEP9_RX_DMA endpoint 9 DMA RX buffer address 0x40 16 read-write n 0x0 0xFFFFFFFF UEP9_RX_DMA endpoint 9 DMA buffer address 0 16 read-write UEP9_R_CTRL endpoint 9 send control 0xFF 8 read-write n 0x0 0xFFFFFFFF bUEP_R_TOG_AUTO endpoint 9 synchronous trigger bit automatic filp enables the control bit 5 1 read-only MASK_UEP_R_RES endpoint 9 control of the accept response to OUT transactions 0 2 read-write MASK_UEP_R_TOG endpoint 9 synchronous trigger bit for the accept to prepare 3 2 read-write UEP9_TX_DMA endpoint 9 DMA TX buffer address 0x7C 16 read-write n 0x0 0xFFFFFFFF UEP9_TX_DMA endpoint 9 DMA buffer address 0 16 read-write UEP9_T_CTRL endpoint 9 send control 0xFE 8 read-write n 0x0 0xFFFFFFFF bUEP_T_TOG_AUTO endpoint 9 synchronous trigger bit automatic filp enables the control bit 5 1 read-write MASK_UEP_T_RES endpoint 9 control of the send response to IN transactions 0 2 read-write MASK_UEP_T_TOG endpoint 9 synchronous trigger bit for the sender to prepare 3 2 read-write UEP9_T_LEN endpoint9 send the length 0xFC 16 read-write n 0x0 0xFFFFFFFF UEP9_T_LEN endpoint 9 send the length 0 11 read-write UEP_BUF_MOD USB endpoint buffer mode 0x18 32 read-write n 0x0 0xFFFFFFFF bUEP_BUF_MOD buffer mode of USB endpoint 0 16 read-write bUEP_ISO_BUF_MOD buffer mode of USB endpoint 16 16 read-write UEP_CONFIG USB endpoint configuration 0x10 32 read-write n 0x0 0xFFFFFFFF bUEP_R_EN__UH_EP_MOD endpoint RX enable/bUH_TX_EN 17 15 read-write bUEP_T_EN_bUH_TX_EN endpoint TX enable/bUH_TX_EN 1 15 read-write UEP_TYPE USB endpoint type 0x14 32 read-write n 0x0 0xFFFFFFFF bUEP_R_TYPE endpoint RX type 17 15 read-write bUEP_T_TYPE endpoint TX type 1 15 read-write UHOST_CTRL USB HOST control 0x1 8 n 0x0 0xFFFFFFFF bUH_PHY_SUSPENDM USB-PHY thesuspended state the internal USB-PLL is turned off 4 1 read-write bUH_REMOTE_WKUP the remoke wake-up 3 1 read-write bUH_SOF_EN automatically generate the SOF packet enabling control bit 7 1 read-write bUH_SOF_FREE the bus is idle 6 1 read-only bUH_TX_BUS_RESET USB host bus reset status 0 1 read-write bUH_TX_BUS_RESUME host wake up device 2 1 read-write bUH_TX_BUS_SUSPEND the host sends hang sigal 1 1 read-write USB_CTRL USB base control 0x0 8 read-write n 0x6 0xFFFFFFFF RB_UC_CLR_ALL force clear FIFO and count of USB 1 1 RB_UC_DEV_PU_EN USB device enable and internal pullup resistance enable 4 1 RB_UC_DMA_EN DMA enable and DMA interrupt enable for USB 0 1 RB_UC_HOST_MODE enable USB host mode: 0=device mode, 1=host mode 7 1 RB_UC_INT_BUSY enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 3 1 RB_UC_RESET_SIE force reset USB SIE, need software clear 2 1 RB_UC_SPEED_TYPE enable USB low speed: 00=full speed, 01=high speed, 10 =low speed 5 2 USB_DEV_AD USB device address 0x3 8 read-write n 0x0 0xFFFFFFFF MASK_USB_ADDR bit mask for USB device address 0 7 RB_UDA_GP_BIT general purpose bit 7 1 USB_FRAME_NO USB_FRAME_NO 0x4 16 read-only n 0x0 0xFFFFFFFF USB_FRAME_NO USB_FRAME_NO 0 16 USB_INT_EN USB interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_UIE_BUS_RST__RB_UIE_DETECT enable interrupt for USB bus reset event for USB device mode enable interrupt for USB device detected event for USB host mode 0 1 RB_UIE_DEV_NAK enable interrupt for NAK responded for USB device mode 7 1 RB_UIE_FIFO_OV enable interrupt for FIFO overflow 4 1 RB_UIE_ISO_ACT enable interrupt for NAK responded for USB device mode 6 1 RB_UIE_SETUP_ACT indicate host SETUP timer action status for USB host 5 1 RB_UIE_SOF_ACT indicate host SOF timer action status for USB host 3 1 RB_UIE_SUSPEND enable interrupt for USB suspend or resume event 2 1 RB_UIE_TRANSFER enable interrupt for USB transfer completion 1 1 USB_INT_FG USB interrupt flag 0xA 8 n 0x20 0xFFFFFFFF RB_UIF_BUS_RST RB_UIF_BUS_RST 0 1 read-write RB_UIF_FIFO_OV FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 4 1 read-write RB_UIF_HST_SOF host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 3 1 read-write RB_UIF_SUSPEND USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 2 1 read-write RB_UIF_TRANSFER USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 1 1 read-write RB_U_IS_NAK RO, indicate current USB transfer is NAK received 7 1 read-only RB_U_SETUP_ACT USB_SETUP_ACT 5 1 read-only UIF_ISO_ACT UIF_ISO_ACT 6 1 read-only USB_INT_ST USB interrupt status 0xB 8 read-only n 0x0 0xFFFFFFFF MASK_UIS_H_RES__MASK_UIS_ENDP RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received RO, bit mask of current transfer endpoint number for USB device mode 0 4 MASK_UIS_TOKEN RO, bit mask of current token PID code received for USB device mode 4 2 RB_UIS_IS_NAK RO, indicate current USB transfer is NAK received for USB device mode 7 1 RB_UIS_TOG_OK RO, indicate current USB transfer toggle is OK 6 1 USB_MIS_ST USB miscellaneous status 0x9 8 read-only n 0x0 0xFFFFFFFF RB_UMS_ATTACH RO, indicate UDM level saved at device attached to USB host 1 1 RB_UMS_BUS_RESET RO, indicate USB bus reset status 3 1 RB_UMS_R_FIFO_RDY RO, indicate USB receiving FIFO ready status (not empty) 4 1 RB_UMS_SIE_FREE RO, indicate USB SIE free status 5 1 RB_UMS_SOF_ACT RO, indicate host SOF timer action status for USB host 6 1 RB_UMS_SOF_PRES RO, indicate host SOF timer presage status 7 1 RB_UMS_SPLIT_CAN RO, indicate device attached status on USB host 0 1 RB_UMS_SUSPEND RO, indicate USB suspend status 2 1 USB_RX_LEN USB receiving length 0xC 16 read-only n 0x0 0xFFFFFFFF R16_USB_RX_LEN length of received bytes 0 16 USB_SPEED_TYPE USB_SPEED_TYPE 0x8 8 read-only n 0x0 0xFFFFFFFF USB_SPEED_TYPE USB_SPEED_TYPE 0 2 USB_USB_SUSPEND indicate USB suspend status 0x6 8 read-write n 0x0 0xFFFFFFFF USB_LINESTATE USB_LINESTATE 4 2 USB_SYS_MOD USB_SYS_MOD 0 2 USB_WAKEUP remote resume 2 1 USB_OTG_FS USB FS OTG register USB_OTG_FS 0x50000000 0x0 0x40000 registers n OTG_FS OTG_FS 83 USBHSWakeup USBHSWakeup 84 USBHS USBHS 85 R16_USB_RX_LEN USB receiving length 0x8 16 read-only n 0x0 0xFFFFFFFF R32_UEP0_DMA endpoint 0 DMA buffer address 0x10 32 read-write n 0x0 0xFFFFFFFF R32_UEP1_DMA endpoint 1 DMA buffer address 0x14 32 read-write n 0x0 0xFFFFFFFF R32_UEP2_DMA__R32_UH_RX_DMA endpoint 2 DMA buffer address host rx endpoint buffer high address 0x18 32 read-write n 0x0 0xFFFFFFFF R32_UEP3_DMA__R32_UH_TX_DMA endpoint 3 DMA buffer address host tx endpoint buffer high address 0x1C 32 read-write n 0x0 0xFFFFFFFF R32_UEP4_DMA endpoint 4 DMA buffer address 0x20 32 read-write n 0x0 0xFFFFFFFF R32_UEP5_DMA endpoint 5 DMA buffer address 0x24 32 read-write n 0x0 0xFFFFFFFF R32_UEP6_DMA endpoint 6 DMA buffer address 0x28 32 read-write n 0x0 0xFFFFFFFF R32_UEP7_DMA endpoint 7 DMA buffer address 0x2C 32 read-write n 0x0 0xFFFFFFFF R8_UEP0_R_CTRL endpoint 0 control 0x33 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP0_T_CTRL endpoint 0 control 0x32 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP0_T_LEN endpoint 0 transmittal length 0x30 8 read-write n 0x0 0xFFFFFFFF R8_UEP1_R_CTRL endpoint 1 control 0x37 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP1_T_CTRL___USBHD_UH_SETUP endpoint 1 control 0x36 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG_ prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 USBHD_UH_PRE_PID_EN USB host PRE PID enable for low speed device via hub 7 1 USBHD_UH_SOF_EN USB host automatic SOF enable 6 1 R8_UEP1_T_LEN endpoint 1 transmittal length 0x34 8 read-write n 0x0 0xFFFFFFFF R8_UEP2_3_MOD__R8_UH_EP_MOD endpoint 2/3 mode host endpoint mode 0xD 8 read-write n 0x0 0xFFFFFFFF RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD buffer mode of USB endpoint 2 buffer mode of USB host IN endpoint 0 1 RB_UEP2_RX_EN__RB_UH_EP_RX_EN enable USB endpoint 2 receiving (OUT) enable USB host IN endpoint receiving 3 1 RB_UEP2_TX_EN enable USB endpoint 2 transmittal (IN) 2 1 RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD buffer mode of USB endpoint 3 buffer mode of USB host OUT endpoint 4 1 RB_UEP3_RX_EN enable USB endpoint 3 receiving (OUT) 7 1 RB_UEP3_TX_EN__RB_UH_EP_TX_EN enable USB endpoint 3 transmittal (IN) enable USB host OUT endpoint transmittal 6 1 R8_UEP2_R_CTRL__USBHD_UH_RX_CTRL endpoint 2 control 0x3B 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES___USBHD_UH_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG___USBHD_UH_R_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG___USBHD_UH_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP2_T_CTRL endpoint 2 control 0x3A 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG_ prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP2_T_LEN__USBHD_UH_EP_PID endpoint 2 transmittal length 0x38 8 read-write n 0x0 0xFFFFFFFF USBHD_UH_ENDP_MASK bit mask of endpoint number for USB host transfer 0 4 USBHD_UH_TOKEN_MASK bit mask of token PID for USB host transfer 4 4 R8_UEP3_R_CTRL_ endpoint 3 control 0x3F 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP3_T_CTRL__USBHD_UH_TX_CTRL endpoint 3 control 0x3E 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES___USBHD_UH_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG___USBHD_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP3_T_LEN__USBHD_UH_TX_LEN endpoint 3 transmittal length 0x3C 8 read-write n 0x0 0xFFFFFFFF R8_UEP4_1_MOD endpoint 4/1 mode 0xC 8 read-write n 0x0 0xFFFFFFFF RB_UEP1_BUF_MOD buffer mode of USB endpoint 1 4 1 RB_UEP1_RX_EN enable USB endpoint 1 receiving (OUT) 7 1 RB_UEP1_TX_EN enable USB endpoint 1 transmittal (IN) 6 1 RB_UEP4_RX_EN enable USB endpoint 4 receiving (OUT) 3 1 RB_UEP4_TX_EN enable USB endpoint 4 transmittal (IN) 2 1 R8_UEP4_R_CTRL_ endpoint 4 control 0x43 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP4_T_CTRL endpoint 4 control 0x42 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG___USBHD_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP4_T_LEN endpoint 4 transmittal length 0x40 8 read-write n 0x0 0xFFFFFFFF R8_UEP5_6_MOD endpoint 5/6 mode 0xE 8 read-write n 0x0 0xFFFFFFFF RB_UEP3_RX_EN enable USB endpoint 6 receiving (OUT) 7 1 RB_UEP5_BUF_MOD buffer mode of USB endpoint 5 0 1 RB_UEP5_RX_EN enable USB endpoint 5 receiving (OUT) 3 1 RB_UEP5_TX_EN enable USB endpoint 5 transmittal (IN) 2 1 RB_UEP6_BUF_MOD buffer mode of USB endpoint 6 4 1 RB_UEP6_TX_EN enable USB endpoint 6 transmittal (IN) 6 1 R8_UEP5_R_CTRL_ endpoint 5 control 0x47 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP5_T_CTRL endpoint 5 control 0x46 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG___USBHD_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP5_T_LEN endpoint 5 transmittal length 0x44 8 read-write n 0x0 0xFFFFFFFF R8_UEP6_R_CTRL_ endpoint 6 control 0x4B 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP6_T_CTRL endpoint 6 control 0x4A 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG___USBHD_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP6_T_LEN endpoint 6 transmittal length 0x48 8 read-write n 0x0 0xFFFFFFFF R8_UEP7_MOD endpoint 7 mode 0xF 8 read-write n 0x0 0xFFFFFFFF RB_UEP7_BUF_MOD buffer mode of USB endpoint 7 0 1 RB_UEP7_RX_EN enable USB endpoint 7 receiving (OUT) 3 1 RB_UEP7_TX_EN enable USB endpoint 7 transmittal (IN) 2 1 R8_UEP7_R_CTRL_ endpoint 7 control 0x4F 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 USBHD_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 2 1 R8_UEP7_T_CTRL endpoint 7 control 0x4E 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 USBHD_UEP_AUTO_TOG__USBHD_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 3 1 USBHD_UEP_T_TOG___USBHD_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 2 1 R8_UEP7_T_LEN endpoint 7 transmittal length 0x4C 8 read-write n 0x0 0xFFFFFFFF R8_USB_DEV_AD USB device address 0x3 8 read-write n 0x0 0xFFFFFFFF MASK_USB_ADDR bit mask for USB device address 0 7 read-write RB_UDA_GP_BIT general purpose bit 7 1 R8_USB_INT_EN USB interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF USBHD_UIE_BUS_RST__USBHD_UIE_DETECT enable interrupt for USB bus reset event for USB device mode 0 1 USBHD_UIE_DEV_NAK enable interrupt for NAK responded for USB device mode 6 1 USBHD_UIE_DEV_SOF enable interrupt for SOF received for USB device mode 7 1 USBHD_UIE_FIFO_OV enable interrupt for FIFO overflow 4 1 USBHD_UIE_HST_SOF enable interrupt for host SOF timer action for USB host mode 3 1 USBHD_UIE_SUSPEND enable interrupt for USB suspend or resume event 2 1 USBHD_UIE_TRANSFER enable interrupt for USB transfer completion 1 1 R8_USB_INT_FG USB interrupt flag 0x6 8 read-write n 0x0 0xFFFFFFFF RB_UIF_BUS_RST__RB_UIF_DETECT bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear 0 1 RB_UIF_FIFO_OV FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 4 1 RB_UIF_HST_SOF host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 3 1 RB_UIF_SUSPEND USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 2 1 RB_UIF_TRANSFER USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 1 1 RB_U_IS_NAK RO, indicate current USB transfer is NAK received 7 1 read-only RB_U_SIE_FREE RO, indicate USB SIE free status 5 1 read-only RB_U_TOG_OK RO, indicate current USB transfer toggle is OK 6 1 read-only R8_USB_INT_ST USB interrupt status 0x7 8 read-only n 0x0 0xFFFFFFFF MASK_UIS_H_RES__MASK_UIS_ENDP RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received RO, bit mask of current transfer endpoint number for USB device mode 0 4 MASK_UIS_TOKEN RO, bit mask of current token PID code received for USB device mode 4 2 RB_UIS_IS_NAK RO, indicate current USB transfer is NAK received for USB device mode 7 1 RB_UIS_TOG_OK RO, indicate current USB transfer toggle is OK 6 1 R8_USB_MIS_ST USB miscellaneous status 0x5 8 read-only n 0x0 0xFFFFFFFF RB_UMS_BUS_RESET RO, indicate USB bus reset status 3 1 RB_UMS_DEV_ATTACH RO, indicate device attached status on USB host 0 1 RB_UMS_DM_LEVEL RO, indicate UDM level saved at device attached to USB host 1 1 RB_UMS_R_FIFO_RDY RO, indicate USB receiving FIFO ready status (not empty) 4 1 RB_UMS_SIE_FREE RO, indicate USB SIE free status 5 1 RB_UMS_SOF_ACT RO, indicate host SOF timer action status for USB host 6 1 RB_UMS_SOF_PRES RO, indicate host SOF timer presage status 7 1 RB_UMS_SUSPEND RO, indicate USB suspend status 2 1 USBHD_BASE_CTRL USB base control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_UC_HOST_MODE enable USB host mode: 0=device mode, 1=host mode 7 1 USBHD_UC_CLR_ALL force clear FIFO and count of USB 1 1 USBHD_UC_DMA_EN DMA enable and DMA interrupt enable for USB 0 1 USBHD_UC_INT_BUSY enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 3 1 USBHD_UC_LOW_SPEED enable USB low speed: 0=12Mbps, 1=1.5Mbps 6 1 USBHD_UC_RESET_SIE force reset USB SIE, need software clear 2 1 USBHD_UC_SYS_CTRL_MASK USB device enable and internal pullup resistance enable 4 2 USBHD_UDEV_CTRL__USBHD_UHOST_CTRL USB device/host physical prot control 0x1 8 read-write n 0x0 0xFFFFFFFF USBHD_UH_BUS_RESET__USBHD_UD_GP_BIT force clear FIFO and count of USB 1 1 USBHD_UH_DM_PIN__USBHD_UD_DM_PIN ReadOnly: indicate current UDM pin level 4 1 read-opnly USBHD_UH_DP_PIN__USBHD_UD_DP_PIN USB device enable and internal pullup resistance enable 5 1 read-opnly USBHD_UH_LOW_SPEED__USBHD_UD_LOW_SPEED enable USB port low speed: 0=full speed, 1=low speed 2 1 USBHD_UH_PD_DIS__USBHD_UD_PD_DIS disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable 7 1 USBHD_UH_PORT_EN__USBHD_UD_PORT_EN enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached 0 1 USB_OTG_CR usb otg control 0x54 32 read-write n 0x0 0xFFFFFFFF USB_OTG_CR_CHARGEVBUS usb otg control 1 1 USB_OTG_CR_DISCHARGEVBUS usb otg control 0 1 USB_OTG_CR_IDPU usb otg control 2 1 USB_OTG_CR_OTG_EN usb otg control 3 1 USB_OTG_CR_SESS usb otg control 5 1 USB_OTG_CR_VBUS usb otg control 4 1 USB_OTG_SR usb otg status 0x58 32 read-write n 0x0 0xFFFFFFFF USB_OTG_SR_ID_DIG usb otg status 3 1 USB_OTG_SR_SESS_END usb otg status 2 1 USB_OTG_SR_SESS_VLD usb otg status 1 1 USB_OTG_SR_VBUS_VLD usb otg status 0 1 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers n WWDG Window Watchdog interrupt 16 CFGR CFGR Configuration register (WWDG_CFR) 0x4 32 read-write n 0x7F 0xFFFFFFFF EWI Early Wakeup Interrupt 9 1 read-write W 7-bit window value 0 7 read-write WDGTB Timer Base 7 2 read-write CTLR CTLR Control register (WWDG_CR) 0x0 32 read-write n 0x7F 0xFFFFFFFF T 7-bit counter (MSB to LSB) 0 7 read-write WDGA Activation bit 7 1 read-write STATR STATR Status register (WWDG_SR) 0x8 32 read-write n 0x0 0xFFFFFFFF WEIF Early Wakeup Interrupt Flag 0 1 read-write