WCH CH569 2025.05.09 CH569 View File 8 64 DVP DVP register DVP 0x4000E000 0x0 0x400 registers n R16_DVP_COL_CNT DVP col count value 0x16 16 read-only n 0x0 0xFFFFFFFF RB_DVP_COL_CNT DVP receive fifo ready 0 16 R16_DVP_COL_NUM DVP row number of a frame indicator register 0x6 16 read-write n 0x0 0xFFFFFFFF RB_DVP_COL_NUM the number of PCLK cyccles contained in a row of data in RGB mode 0 16 R16_DVP_ROW_CNT DVP row count value 0x14 16 read-only n 0x0 0xFFFFFFFF RB_DVP_ROW_CNT DVP receive fifo full 0 16 R16_DVP_ROW_NUM DVP row number of a frame indicator register 0x4 16 read-write n 0x0 0xFFFFFFFF RB_DVP_ROW_NUM the number of rows contained in a frame of image data 0 16 R32_DVP_DMA_BUF0 DVP dma buffer0 addr 0x8 32 read-write n 0x0 0xFFFFFFFF RB_DVP_DMA_BUF0 the receiving address 0 of DMA 0 17 R32_DVP_DMA_BUF1 DVP dma buffer1 addr 0xC 32 read-write n 0x0 0xFFFFFFFF RB_DVP_DMA_BUF1 the receiving address1 of DMA 0 17 R8_DVP_CR0 DVP control register0 0x0 8 read-write n 0x0 0xFFFFFFFF RB_DVP_ENABLE DVP enable 0 1 RB_DVP_H_POLAR DVP HSYNC polarity control 2 1 RB_DVP_JPEG DVP JPEG mode 6 1 RB_DVP_MSK_DAT_MOD DVP data bit width confguration 4 2 RB_DVP_P_POLAR DVP PCLK polarity control 3 1 RB_DVP_RAW_CM DVP row count mode 7 1 RB_DVP_V_POLAR DVP VSYNC polarity control 1 1 R8_DVP_CR1 DVP control register1 0x1 8 read-write n 0x6 0xFFFFFFFF RB_DVP_ALL_CLR DVP all clear, high action 1 1 RB_DVP_BUF_TOG DVP bug toggle by software 3 1 RB_DVP_DMA_ENABLE DVP dma enable 0 1 RB_DVP_RCV_CLR DVP receive logic clear, high action 2 1 R8_DVP_FIFO_ST DVP receive fifo status 0x11 8 read-only n 0x0 0xFFFFFFFF RB_DVP_FIFO_FULL DVP receive fifo full 1 1 RB_DVP_FIFO_OV DVP receive fifo overflow 2 1 RB_DVP_FIFO_RDY DVP receive fifo ready 0 1 RB_DVP_MSK_FIFO_CNT DVP receive fifo count 4 3 R8_DVP_INT_EN DVP interrupt enable register 0x2 8 read-write n 0x0 0xFFFFFFFF RB_DVP_IE_FIFO_OV DVP receive fifo overflow interrupt enable 3 1 RB_DVP_IE_FRM_DONE DVP frame received done interrupt enable 2 1 RB_DVP_IE_ROW_DONE DVP row received done interrupt enable 1 1 RB_DVP_IE_STP_FRM DVP frame stop interrupt enable 4 1 RB_DVP_IE_STR_FRM DVP frame start interrupt enable 0 1 R8_DVP_INT_FLAG DVP interrupt flag register 0x10 32 read-write n 0x0 0xFFFFFFFF RB_DVP_IF_FIFO_OV interrupt flag for DVP receive fifo overflow 3 1 RB_DVP_IF_FRM_DONE interrupt flag for DVP frame receive done 2 1 RB_DVP_IF_ROW_DONE interrupt flag for DVP row receive done 1 1 RB_DVP_IF_STP_FRM interrupt flag for DVP frame stop 4 1 RB_DVP_IF_STR_FRM interrupt flag for DVP frame start 0 1 ECDC ECDC register ECDC 0x40007000 0x0 0x400 registers n R16_ECEC_CTRL ECED AES/SM4 register 0x0 16 n 0x20 0xFFFFFFFF RB_ECDC_ALGRM_MOD Encryption and decryption algorithm mode selection 8 1 read-write RB_ECDC_CIPHER_MOD Block cipher mode selection 9 1 read-write RB_ECDC_CLKDIV_MASK Clock divide factor 4 3 read-write RB_ECDC_DAT_MOD source data and result data is bit endian 13 1 write-only RB_ECDC_KEYEX_EN enable key expansion 0 1 read-write RB_ECDC_KLEN_MASK Key length setting 10 2 read-write RB_ECDC_MODE_SEL ECDC mode select 3 1 read-write RB_ECDC_RDPERI_EN when write data to dma 1 1 read-write RB_ECDC_WRPERI_EN when read data from dma 2 1 read-write RB_ECDC_WRSRAM_EN module dma enable 7 1 read-write R32_ECDC_IV_127T96 CTR mode count 96-127 register 0x28 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_IV_127T96 CTR mode count 96-127 register 0 32 R32_ECDC_IV_31T0 CTR mode count 0-31 register 0x34 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_IV_31T0 CTR mode count 0-31 register 0 32 R32_ECDC_IV_63T32 CTR mode count 32-63 register 0x30 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_IV_63T32 CTR mode count 32-63 register 0 32 R32_ECDC_IV_95T64 CTR mode count 64-95 register 0x2C 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_IV_95T64 CTR mode count 64-95 register 0 32 R32_ECDC_KEY_127T96 User key 96-127 register 0x18 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_127T96 User key 96-127 register 0 32 R32_ECDC_KEY_159T128 User key 128-159 register 0x14 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_159T128 User key 128-159 register 0 32 R32_ECDC_KEY_191T160 User key 160-191 register 0x10 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_191T160 User key 160-191 register 0 32 R32_ECDC_KEY_223T192 User key 192-223 register 0xC 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_223T192 User key 192-223 register 0 32 R32_ECDC_KEY_255T224 User key 224-255 register 0x8 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_255T224 User key 224-255 register 0 32 R32_ECDC_KEY_31T0 User key 0-31 register 0x24 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_31T0 User key 0-31 register 0 32 R32_ECDC_KEY_63T32 User key 32-63 register 0x20 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_63T32 User key 32-63 register 0 32 R32_ECDC_KEY_95T64 User key 64-95 register 0x1C 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_KEY_95T64 User key 64-95 register 0 32 R32_ECDC_SGRT_127T96 Single encryption and decryption result 96-127 register 0x50 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGRT_127T96 Single encryption and decryption result 96-127 register 0 32 R32_ECDC_SGRT_63T32 Single encryption and decryption result 0-31 register 0x58 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGRT_63T32 Single encryption and decryption result 0-31 register 0 32 R32_ECDC_SGRT_95T64 Single encryption and decryption result 64-95 register 0x54 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGRT_95T64 Single encryption and decryption result 64-95 register 0 32 R32_ECDC_SGSD_127T96 Single encryption and decryption of original data 96-127 register 0x40 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGSD_127T96 Single encryption and decryption of original data 96-127 register 0 32 R32_ECDC_SGSD_31T0 Single encryption and decryption of original data 0-31 register 0x4C 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGSD_31T0 Single encryption and decryption of original data 0-31 register 0 32 R32_ECDC_SGSD_63T32 Single encryption and decryption of original data 32-63 register 0x48 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGSD_63T32 Single encryption and decryption of original data 32-63 register 0 32 R32_ECDC_SGSD_95T64 Single encryption and decryption of original data 64-95 register 0x44 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGSD_95T64 Single encryption and decryption of original data 64-95 register 0 32 R32_ECDC_SRAM_ADDR encryption and decryption sram start address register 0x60 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SRAM_ADDR encryption and decryption sram start address register 0 17 R32_ECDC_SRAM_LEN encryption and decryption sram size register 0x64 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SRAM_LEN encryption and decryption sram size register 0 13 R8_ECDC_INT_EN Interupt enable register 0x2 8 n 0x0 0xFFFFFFFF RB_ECDC_IE_EKDONE Key extension completion interrupt enable 0 1 read-write RB_ECDC_IE_SINGLE Single encryption and decryption completion interrupt enable 1 1 read-write RB_ECDC_IE_WRSRAM Memory to memory encryption and decryption completion interrupt enable 2 1 write-only R8_ECDC_INT_FG Interupt flag register 0x6 8 read-write n 0x0 0xFFFFFFFF RB_ECDC_IF_EKDONE Key extension completion interrupt flag 0 1 RB_ECDC_IF_SINGLE Single encryption and decryption completion interrupt flag 1 1 RB_ECDC_IF_WRSRAM Memory to memory encryption and decryption completion interrupt flag 2 1 RB_ECDC_SGRT_31T0 Single encryption and decryption result 0-31 register 0x5C 32 read-write n 0x0 0xFFFFFFFF RB_ECDC_SGRT_31T0 Single encryption and decryption result 0-31 register 0 32 EMMC EMMC register EMMC 0x4000A000 0x0 0x400 registers n R16_EMMC_CLK_DIV SD clock divider register 0x38 16 read-write n 0x213 0xFFFFFFFF RB_EMMC_CLKMode EMMC clock frequency mode selection bit 9 1 RB_EMMC_CLKOE chip output sdclk oe 8 1 RB_EMMC_DIV_MASK clk div 0 5 RB_EMMC_PHASEINV invert chip output sdclk phase 10 1 R16_EMMC_CMD_SET SD 16bits cmd setting register 0x4 16 read-write n 0x0 0xFFFFFFFF RB_EMMC_CKCRC check the response CRC 10 1 RB_EMMC_CKIDX check the response command index 11 1 RB_EMMC_CMDIDX_MASK the index number of the currently sent command 0 6 RB_EMMC_RPTY_MASK current respone type 8 2 R16_EMMC_INT_EN SD 16bits interrupt enable register 0x28 16 read-write n 0x0 0xFFFFFFFF RB_EMMC_IE_BKGAP single block transmission completion interrupt enable 7 1 RB_EMMC_IE_CMDDONE command completion interrupt enable 3 1 RB_EMMC_IE_DATTMO data timeout interrupt enable 4 1 RB_EMMC_IE_FIFO_OV FIFO overflow interrupt enable 8 1 RB_EMMC_IE_RECRC_WR response CRC check error interrupt enable 1 1 RB_EMMC_IE_REIDX_ER response index check error interrupt enable 2 1 RB_EMMC_IE_RE_TMOUT command response timeout interrupt enable 0 1 RB_EMMC_IE_SDIOINT SDIO card interrupt enable 9 1 RB_EMMC_IE_TRANDONE all blocks transfer complete interrupt enable 6 1 RB_EMMC_IE_TRANERR blocks transfer CRC error interrupt enable 5 1 R16_EMMC_INT_FG SD 16bits interrupt flag register 0x24 16 read-write n 0x0 0xFFFFFFFF RB_EMMC_IF_BKGAP every block gap interrupt when multiple read/write, allow drive change the DMA address at this moment 7 1 RB_EMMC_IF_CMDDONE when cmd hasn't response, indicate cmd has been sent, when cmd has a response, indicate cmd has bee sent and has received the response 3 1 RB_EMMC_IF_DATTMO data line busy timeout 4 1 RB_EMMC_IF_FIFO_OV fifo overflow, when write sd, indicate empty overflow, when read sd, indicate full overflow 8 1 RB_EMMC_IF_RECRC_WR indicate CRC error of the response 1 1 RB_EMMC_IF_REIDX_ER indicate INDEX error of the response 2 1 RB_EMMC_IF_RE_TMOUT indicate when expect the response, timeout 0 1 RB_EMMC_IF_SDIOINT interrupt from SDIO card inside 9 1 RB_EMMC_IF_TRANDONE all the blocks have been tran/recv successfully 6 1 RB_EMMC_IF_TRANERR last block have encountered a CRC error 5 1 R32_EMMC_ARGUMENT SD 32bits command argument register 0x0 32 read-write n 0x0 0xFFFFFFFF EMMC_ARGUMENT 32 bit command parameter register 0 32 R32_EMMC_BLOCK_CFG SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte number) of every block in this time tran/recv 0x30 32 read-write n 0x0 0xFFFFFFFF RB_EMMC_BKNUM_MASK the number of blocks to be transferred 0 16 RB_EMMC_BKSIZE_MASK single block transfer size 16 12 R32_EMMC_DMA_BEG1 SD 16bits DMA start address register when to operate 0x2C 32 read-write n 0x0 0xFFFFFFFF RB_EMMC_DMAAD1_MASK start address of read-write data buffer,the lower 4 bits are fixed to 0 0 17 R32_EMMC_DMA_BEG2 SD 16bits DMA start address register when to operate 0x3C 32 read-write n 0x0 0xFFFFFFFF RB_EMMC_DMAAD2_MASK start address of read-write data buffer,the lower 4 bits are fixed to 0 0 17 R32_EMMC_RESPONSE0 SD 128bits response register, [31:0] 32bits 0x8 32 read-only n 0x0 0xFFFFFFFF R32_EMMC_RESPONSE0 response parameter register 0 32 R32_EMMC_RESPONSE1 SD 128bits response register, [63:32] 32bits 0xC 32 read-only n 0x0 0xFFFFFFFF R32_EMMC_RESPONSE1 response parameter register 0 32 R32_EMMC_RESPONSE2 SD 128bits response register, [95:64] 32bits 0x10 32 read-only n 0x0 0xFFFFFFFF R32_EMMC_RESPONSE2 response parameter register 0 32 R32_EMMC_RESPONSE3 SD 128bits response register, [127:96] 32bits 0x14 32 read-only n 0x0 0xFFFFFFFF R32_EMMC_RESPONSE3 response parameter register 0 32 R32_EMMC_STATUS SD status 0x20 32 read-only n 0x0 0xFFFFFFFF MASK_BLOCK_NUM the number of blocks successfully transmitted in the current multi-block transmission 0 16 RB_EMMC_CMDSTA indicate cmd line is high level now 16 1 RB_EMMC_DAT0STA indicate dat[0] line is high level now 17 1 R32_EMMC_TRAN_MODE SD TRANSFER MODE register 0x34 32 read-write n 0x0 0xFFFFFFFF RB_EMMC_AUTOGAPSTOP enable auto set bTM_GAP_STOP when tran start 4 1 RB_EMMC_DMATN_CNT in double buffer mode,set the block count value of buffer switch 8 7 RB_EMMC_DMA_DIR set DMA direction is controller to emmc card 0 1 RB_EMMC_DULEDMA_EN enable double buffer dma 16 1 RB_EMMC_FIFO_RDY FIFO ready select signal when writing EMMC 6 2 RB_EMMC_GAP_STOP clock stop mode after block completion 1 1 RB_EMMC_MODE_BOOT enable emmc boot mode 2 1 R32_EMMC_WRITE_CONT Multiplexing register of the EMMC_RESPONSE3,[127:96] 32bits 0x14 32 write-only n 0x0 0xFFFFFFFF R32_EMMC_WRITE_CONT response parameter register 0 32 R8_EMMC_CONTROL SD 8bits control register 0x18 8 read-write n 0x15 0xFFFFFFFF RB_EMMC_ALL_CLR reset all the inner logic, default is valid 2 1 RB_EMMC_DMAEN enable the dma 3 1 RB_EMMC_LW_MASK effctive data width for sending or receiving data 0 2 RB_EMMC_NEGSMP controller use nagedge sample cmd 5 1 RB_EMMC_RST_LGC reset the data tran/recv logic 4 1 R8_EMMC_TIMEOUT SD 8bits data timeout value 0x1C 8 read-write n 0xC 0xFFFFFFFF RB_EMMC_TOCNT_MASK response data timeout configuration 0 4 ETH ETH register (Please refer to subprogram library) ETH 0x4000C000 0x0 0x400 registers n HSPI HSPI register HSPI 0x40006000 0x0 0x400 registers n HSPI_RX_SC parallel RX sequence ctrl 0x2B 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_RX_NUM parallel if rx sequence num 0 4 RB_HSPI_RX_TOG parallel if rx addr toggle flag 4 1 R16_HSPI_BURST_CFG parallel if tx burst config register 0x1C 16 read-write n 0x0 0xFFFFFFFF RB_HSPI_BURST_EN burst transmit enable 0 1 RB_HSPI_BURST_LEN burst transmit length 8 8 R16_HSPI_DMA_LEN0 parallel if dma length0 0x14 16 read-write n 0x0 0xFFFFFFFF RB_HSPI_DMA_LEN0 parallel if dma length0 0 12 R16_HSPI_DMA_LEN1 parallel if dma length1 0x18 16 read-write n 0x0 0xFFFFFFFF RB_HSPI_DMA_LEN1 parallel if dma length1 0 12 R16_HSPI_RX_LEN0 parallel if receive length0 0x16 16 read-write n 0x0 0xFFFFFFFF RB_HSPI_RX_LEN0 parallel if dma length0 0 12 R16_HSPI_RX_LEN1 parallel if receive length1 0x1A 16 read-write n 0x0 0xFFFFFFFF RB_HSPI_RX_LEN1 parallel if dma length1 0 12 R32_HSPI_RX_ADDR0 parallel if dma rx addr0 0xC 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_RX_ADDR0 parallel if dma rx addr0 0 17 R32_HSPI_RX_ADDR1 parallel if dma rx addr1 0x10 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_RX_ADDR1 parallel if dma rx addr1 0 17 R32_HSPI_TX_ADDR0 parallel if dma tx addr0 0x4 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_TX_ADDR0 parallel if dma tx addr0 0 17 R32_HSPI_TX_ADDR1 parallel if dma tx addr1 0x8 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_TX_ADDR1 parallel if dma tx addr1 0 17 R32_HSPI_UDF0 parallel if user defined field 0 register 0x20 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_UDF0 parallel if user defined field 0 register 0 26 R32_HSPI_UDF1 parallel if user defined field 1 register 0x24 32 read-write n 0x0 0xFFFFFFFF RB_HSPI_UDF1 parallel if user defined field 1 register 0 26 R8_HSPI_AUX parallel if aux 0x3 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_ACK_CNT_SEL delay time of parallel if send ack when receive done 3 2 RB_HSPI_ACK_TX_MOD parallel if tx ack mode cfg 2 1 RB_HSPI_RCK_MOD parallel if rx clk polar control 1 1 RB_HSPI_TCK_MOD parallel if tx clk polar control 0 1 R8_HSPI_BURST_CNT parallel if tx burst count 0x1E 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_BURST_CNT parallel if tx burst count 0 8 R8_HSPI_CFG parallel if tx/rx cfg 0x0 8 read-write n 0x82 0xFFFFFFFF RB_HSPI_DUALDMA parallel if dualdma mode enable 1 1 RB_HSPI_HW_ACK parallel if tx ack by hardware 7 1 RB_HSPI_MODE parallel if mode 0 1 RB_HSPI_MSK_SIZE parallel if data mode 2 2 RB_HSPI_RX_TOG_EN parallel if rx addr toggle enable 6 1 RB_HSPI_TX_TOG_EN parallel if tx addr toggle enable 5 1 R8_HSPI_CTRL parallel if tx/rx control 0x1 8 read-write n 0x18 0xFFFFFFFF RB_HSPI_ALL_CLR parallel if all clear 3 1 RB_HSPI_DMA_EN parallel if dma enable 1 1 RB_HSPI_ENABLE parallel if enable 0 1 RB_HSPI_SW_ACT parallel if transmit software trigger 2 1 RB_HSPI_TRX_RST parallel if tx and rx logic clear, high action 4 1 R8_HSPI_INT_EN parallel if interrupt enable register 0x2 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_IE_B_DONE parallel if tx burst done interrupt enable 3 1 RB_HSPI_IE_FIFO_OV parallel if fifo overflow interrupt enable 2 1 RB_HSPI_IE_R_DONE parallel if receive done interrupt enable 1 1 RB_HSPI_IE_T_DONE parallel if transmit done interrupt enable 0 1 R8_HSPI_INT_FLAG parallel if interrupt flag 0x28 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_IF_B_DONE interrupt flag for parallel if tx burst done 3 1 RB_HSPI_IF_FIFO_OV interrupt flag for parallel if FIFO overflow 2 1 RB_HSPI_IF_R_DONE interrupt flag for parallel if receive done 1 1 RB_HSPI_IF_T_DONE interrupt flag for parallel if transmit done 0 1 R8_HSPI_RTX_STATUS parallel rtx status 0x29 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_CRC_ERR CRC error occur 1 1 RB_HSPI_NUM_MIS rx and tx sequence number mismatch 2 1 R8_HSPI_TX_SC parallel TX sequence ctrl 0x2A 8 read-write n 0x0 0xFFFFFFFF RB_HSPI_TX_NUM parallel if tx sequence num 0 4 RB_HSPI_TX_TOG parallel if tx addr toggle flag 4 1 PFIC Program Fast Interrupt Controller PFIC 0xE000E000 0x0 0x1000 registers n CFGR CFGR Interrupt Config Register 0x48 32 n 0x0 0xFFFFFFFF EXCRESET EXCRESET 5 1 write-only EXCSET EXCSET 4 1 write-only HWSTKCTRL HWSTKCTRL 0 1 read-write KEYCODE KEYCODE 16 16 write-only NESTCTRL NESTCTRL 1 1 read-write NMIRESET NMIRESET 3 1 write-only NMISET NMISET 2 1 write-only PFICRSET PFICRSET 6 1 write-only SYSRESET SYSRESET 7 1 write-only FIBADDRR FIBADDRR Interrupt Fast Address Register 0x44 32 read-write n 0x0 0xFFFFFFFF BASEADDR BASEADDR 28 4 FIFOADDRR0 FIFOADDRR0 Interrupt 0 address Register 0x60 32 read-write n 0x0 0xFFFFFFFF IRQID0 IRQID0 24 8 OFFADDR0 OFFADDR0 0 24 FIFOADDRR1 FIFOADDRR1 Interrupt 1 address Register 0x64 32 read-write n 0x0 0xFFFFFFFF IRQID1 IRQID1 24 8 OFFADDR1 OFFADDR1 0 24 FIFOADDRR2 FIFOADDRR2 Interrupt 2 address Register 0x68 32 read-write n 0x0 0xFFFFFFFF IRQID2 IRQID2 24 8 OFFADDR2 OFFADDR2 0 24 FIFOADDRR3 FIFOADDRR3 Interrupt 3 address Register 0x6C 32 read-write n 0x0 0xFFFFFFFF IRQID3 IRQID3 24 8 OFFADDR3 OFFADDR3 0 24 GISR GISR Interrupt Global Register 0x4C 32 read-only n 0x0 0xFFFFFFFF GACTSTA GACTSTA 8 1 GPENDSTA GPENDSTA 9 1 NESTSTA NESTSTA 0 8 IACTR1 IACTR1 Interrupt ACTIVE Register 0x300 32 read-write n 0x0 0xFFFFFFFF IACTS IACTS 12 20 IACTR2 IACTR2 Interrupt ACTIVE Register 0x304 32 read-write n 0x0 0xFFFFFFFF IACTS IACTS 0 28 IENR1 IENR1 Interrupt Setting Register 0x100 32 read-write n 0x0 0xFFFFFFFF INTEN INTEN 12 20 IENR2 IENR2 Interrupt Setting Register 0x104 32 read-write n 0x0 0xFFFFFFFF INTEN INTEN 0 28 IPR1 IPR1 Interrupt Pending Register 0x20 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 12 20 IPR2 IPR2 Interrupt Pending Register 0x24 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 0 28 IPRIOR0 IPRIOR0 Interrupt Priority configuration Register 0x400 32 read-write n 0x0 0xFFFFFFFF IPRIOR0 IPRIOR0 0 32 IPRIOR1 IPRIOR1 Interrupt Priority configuration Register 0x420 32 read-write n 0x0 0xFFFFFFFF IPRIOR1 IPRIOR1 0 32 IPRIOR10 IPRIOR10 Interrupt Priority configuration Register 0x540 32 read-write n 0x0 0xFFFFFFFF IPRIOR10 IPRIOR10 0 32 IPRIOR11 IPRIOR11 Interrupt Priority configuration Register 0x560 32 read-write n 0x0 0xFFFFFFFF IPRIOR11 IPRIOR11 0 32 IPRIOR12 IPRIOR12 Interrupt Priority configuration Register 0x580 32 read-write n 0x0 0xFFFFFFFF IPRIOR12 IPRIOR12 0 32 IPRIOR13 IPRIOR13 Interrupt Priority configuration Register 0x5A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR13 IPRIOR13 0 32 IPRIOR14 IPRIOR14 Interrupt Priority configuration Register 0x5C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR14 IPRIOR14 0 32 IPRIOR15 IPRIOR15 Interrupt Priority configuration Register 0x5E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR15 IPRIOR15 0 32 IPRIOR16 IPRIOR16 Interrupt Priority configuration Register 0x600 32 read-write n 0x0 0xFFFFFFFF IPRIOR16 IPRIOR16 0 32 IPRIOR17 IPRIOR17 Interrupt Priority configuration Register 0x620 32 read-write n 0x0 0xFFFFFFFF IPRIOR17 IPRIOR17 0 32 IPRIOR18 IPRIOR18 Interrupt Priority configuration Register 0x640 32 read-write n 0x0 0xFFFFFFFF IPRIOR18 IPRIOR18 0 32 IPRIOR19 IPRIOR19 Interrupt Priority configuration Register 0x660 32 read-write n 0x0 0xFFFFFFFF IPRIOR19 IPRIOR19 0 32 IPRIOR2 IPRIOR2 Interrupt Priority configuration Register 0x440 32 read-write n 0x0 0xFFFFFFFF IPRIOR2 IPRIOR2 0 32 IPRIOR20 IPRIOR20 Interrupt Priority configuration Register 0x680 32 read-write n 0x0 0xFFFFFFFF IPRIOR20 IPRIOR20 0 32 IPRIOR21 IPRIOR21 Interrupt Priority configuration Register 0x6A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR21 IPRIOR21 0 32 IPRIOR22 IPRIOR22 Interrupt Priority configuration Register 0x6C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR22 IPRIOR22 0 32 IPRIOR23 IPRIOR23 Interrupt Priority configuration Register 0x6E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR23 IPRIOR23 0 32 IPRIOR24 IPRIOR24 Interrupt Priority configuration Register 0x700 32 read-write n 0x0 0xFFFFFFFF IPRIOR24 IPRIOR24 0 32 IPRIOR25 IPRIOR25 Interrupt Priority configuration Register 0x720 32 read-write n 0x0 0xFFFFFFFF IPRIOR25 IPRIOR25 0 32 IPRIOR26 IPRIOR26 Interrupt Priority configuration Register 0x740 32 read-write n 0x0 0xFFFFFFFF IPRIOR26 IPRIOR26 0 32 IPRIOR27 IPRIOR27 Interrupt Priority configuration Register 0x760 32 read-write n 0x0 0xFFFFFFFF IPRIOR27 IPRIOR27 0 32 IPRIOR28 IPRIOR28 Interrupt Priority configuration Register 0x780 32 read-write n 0x0 0xFFFFFFFF IPRIOR28 IPRIOR28 0 32 IPRIOR29 IPRIOR29 Interrupt Priority configuration Register 0x7A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR29 IPRIOR29 0 32 IPRIOR3 IPRIOR3 Interrupt Priority configuration Register 0x460 32 read-write n 0x0 0xFFFFFFFF IPRIOR3 IPRIOR3 0 32 IPRIOR30 IPRIOR30 Interrupt Priority configuration Register 0x7C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR30 IPRIOR30 0 32 IPRIOR31 IPRIOR31 Interrupt Priority configuration Register 0x7E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR31 IPRIOR31 0 32 IPRIOR32 IPRIOR32 Interrupt Priority configuration Register 0x800 32 read-write n 0x0 0xFFFFFFFF IPRIOR32 IPRIOR32 0 32 IPRIOR33 IPRIOR33 Interrupt Priority configuration Register 0x820 32 read-write n 0x0 0xFFFFFFFF IPRIOR33 IPRIOR33 0 32 IPRIOR34 IPRIOR34 Interrupt Priority configuration Register 0x840 32 read-write n 0x0 0xFFFFFFFF IPRIOR34 IPRIOR34 0 32 IPRIOR35 IPRIOR35 Interrupt Priority configuration Register 0x860 32 read-write n 0x0 0xFFFFFFFF IPRIOR35 IPRIOR35 0 32 IPRIOR36 IPRIOR36 Interrupt Priority configuration Register 0x880 32 read-write n 0x0 0xFFFFFFFF IPRIOR36 IPRIOR36 0 32 IPRIOR37 IPRIOR37 Interrupt Priority configuration Register 0x8A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR37 IPRIOR37 0 32 IPRIOR38 IPRIOR38 Interrupt Priority configuration Register 0x8C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR38 IPRIOR38 0 32 IPRIOR39 IPRIOR39 Interrupt Priority configuration Register 0x8E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR39 IPRIOR39 0 32 IPRIOR4 IPRIOR4 Interrupt Priority configuration Register 0x480 32 read-write n 0x0 0xFFFFFFFF IPRIOR4 IPRIOR4 0 32 IPRIOR40 IPRIOR40 Interrupt Priority configuration Register 0x900 32 read-write n 0x0 0xFFFFFFFF IPRIOR40 IPRIOR40 0 32 IPRIOR41 IPRIOR41 Interrupt Priority configuration Register 0x920 32 read-write n 0x0 0xFFFFFFFF IPRIOR41 IPRIOR41 0 32 IPRIOR42 IPRIOR42 Interrupt Priority configuration Register 0x940 32 read-write n 0x0 0xFFFFFFFF IPRIOR42 IPRIOR42 0 32 IPRIOR43 IPRIOR43 Interrupt Priority configuration Register 0x960 32 read-write n 0x0 0xFFFFFFFF IPRIOR43 IPRIOR43 0 32 IPRIOR44 IPRIOR44 Interrupt Priority configuration Register 0x980 32 read-write n 0x0 0xFFFFFFFF IPRIOR44 IPRIOR44 0 32 IPRIOR45 IPRIOR45 Interrupt Priority configuration Register 0x9A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR45 IPRIOR45 0 32 IPRIOR46 IPRIOR46 Interrupt Priority configuration Register 0x9C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR46 IPRIOR46 0 32 IPRIOR47 IPRIOR47 Interrupt Priority configuration Register 0x9E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR47 IPRIOR47 0 32 IPRIOR48 IPRIOR48 Interrupt Priority configuration Register 0xA00 32 read-write n 0x0 0xFFFFFFFF IPRIOR48 IPRIOR48 0 32 IPRIOR49 IPRIOR49 Interrupt Priority configuration Register 0xA20 32 read-write n 0x0 0xFFFFFFFF IPRIOR49 IPRIOR49 0 32 IPRIOR5 IPRIOR5 Interrupt Priority configuration Register 0x4A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR5 IPRIOR5 0 32 IPRIOR50 IPRIOR50 Interrupt Priority configuration Register 0xA40 32 read-write n 0x0 0xFFFFFFFF IPRIOR50 IPRIOR50 0 32 IPRIOR51 IPRIOR51 Interrupt Priority configuration Register 0xA60 32 read-write n 0x0 0xFFFFFFFF IPRIOR51 IPRIOR51 0 32 IPRIOR52 IPRIOR52 Interrupt Priority configuration Register 0xA80 32 read-write n 0x0 0xFFFFFFFF IPRIOR52 IPRIOR52 0 32 IPRIOR53 IPRIOR53 Interrupt Priority configuration Register 0xAA0 32 read-write n 0x0 0xFFFFFFFF IPRIOR53 IPRIOR53 0 32 IPRIOR54 IPRIOR54 Interrupt Priority configuration Register 0xAC0 32 read-write n 0x0 0xFFFFFFFF IPRIOR54 IPRIOR54 0 32 IPRIOR55 IPRIOR55 Interrupt Priority configuration Register 0xAE0 32 read-write n 0x0 0xFFFFFFFF IPRIOR55 IPRIOR55 0 32 IPRIOR56 IPRIOR56 Interrupt Priority configuration Register 0xB00 32 read-write n 0x0 0xFFFFFFFF IPRIOR56 IPRIOR56 0 32 IPRIOR57 IPRIOR57 Interrupt Priority configuration Register 0xB20 32 read-write n 0x0 0xFFFFFFFF IPRIOR57 IPRIOR57 0 32 IPRIOR58 IPRIOR58 Interrupt Priority configuration Register 0xB40 32 read-write n 0x0 0xFFFFFFFF IPRIOR58 IPRIOR58 0 32 IPRIOR59 IPRIOR59 Interrupt Priority configuration Register 0xB60 32 read-write n 0x0 0xFFFFFFFF IPRIOR59 IPRIOR59 0 32 IPRIOR6 IPRIOR6 Interrupt Priority configuration Register 0x4C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR6 IPRIOR6 0 32 IPRIOR60 IPRIOR60 Interrupt Priority configuration Register 0xB80 32 read-write n 0x0 0xFFFFFFFF IPRIOR60 IPRIOR60 0 32 IPRIOR61 IPRIOR61 Interrupt Priority configuration Register 0xBA0 32 read-write n 0x0 0xFFFFFFFF IPRIOR61 IPRIOR61 0 32 IPRIOR62 IPRIOR62 Interrupt Priority configuration Register 0xBC0 32 read-write n 0x0 0xFFFFFFFF IPRIOR62 IPRIOR62 0 32 IPRIOR63 IPRIOR63 Interrupt Priority configuration Register 0xBE0 32 read-write n 0x0 0xFFFFFFFF IPRIOR63 IPRIOR63 0 32 IPRIOR7 IPRIOR7 Interrupt Priority configuration Register 0x4E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR7 IPRIOR7 0 32 IPRIOR8 IPRIOR8 Interrupt Priority configuration Register 0x500 32 read-write n 0x0 0xFFFFFFFF IPRIOR8 IPRIOR8 0 32 IPRIOR9 IPRIOR9 Interrupt Priority configuration Register 0x520 32 read-write n 0x0 0xFFFFFFFF IPRIOR9 IPRIOR9 0 32 IPRR1 IPRR1 Interrupt Pending Clear Register 0x280 32 read-write n 0x0 0xFFFFFFFF PENDRESET PENDRESET 12 20 IPRR2 IPRR2 Interrupt Pending Clear Register 0x284 32 read-write n 0x0 0xFFFFFFFF PENDRESET PENDRESET 0 28 IPSR1 IPSR1 Interrupt Pending Register 0x200 32 read-write n 0x0 0xFFFFFFFF PENDSET PENDSET 12 20 IPSR2 IPSR2 Interrupt Pending Register 0x204 32 read-write n 0x0 0xFFFFFFFF PENDSET PENDSET 0 28 IRER1 IRER1 Interrupt Clear Register 0x180 32 read-write n 0x0 0xFFFFFFFF INTRSET INTRSET 12 20 IRER2 IRER2 Interrupt Clear Register 0x184 32 read-write n 0x0 0xFFFFFFFF INTRSET INTRSET 0 28 ISR1 ISR1 Interrupt Status Register 0x0 32 read-only n 0x0 0xFFFFFFFF INTSTA Interrupt ID Status 12 20 ISR2 ISR2 Interrupt Status Register 0x4 32 read-only n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 0 28 ITHRESDR ITHRESDR Interrupt Priority Register 0x40 32 read-write n 0x0 0xFFFFFFFF THRESHOLD THRESHOLD 0 8 SCTLR SCTLR System Control Register 0xD10 32 read-write n 0x0 0xFFFFFFFF SETEVENT SETEVENT 5 1 SEVONPEND SEVONPEND 4 1 SLEEPDEEP SLEEPDEEP 2 1 SLEEPONEXIT SLEEPONEXIT 1 1 WFITOWFE WFITOWFE 3 1 PWMX PWMX register PWMX 0x40005000 0x0 0x400 registers n R32_PWM_DATA PWM data holding 0x4 32 read-write n 0x0 0xFFFFFFFF R8_PWM0_DATA PWM0 data holding 0 8 R8_PWM1_DATA PWM1 data holding 8 8 R8_PWM2_DATA PWM2 data holding 16 8 R8_PWM3_DATA PWM3 data holding 24 8 R8_PWM_CLOCK_DIV PWM clock divisor 0x2 8 read-write n 0x0 0xFFFFFFFF R8_PWM_CLOCK_DIV PWM clock divisor 0 8 R8_PWM_CTRL_CFG PWM configuration control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_PWM_CYCLE_SEL PWM cycle selection 0 1 R8_PWM_CTRL_MOD PWM mode control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_PWM0_OUT_EN PWM0 output enable 0 1 RB_PWM0_POLAR PWM0 output polarity 4 1 RB_PWM1_OUT_EN PWM1 output enable 1 1 RB_PWM1_POLAR PWM1 output polarity 5 1 RB_PWM2_OUT_EN PWM2 output enable 2 1 RB_PWM2_POLAR PWM2 output polarity 6 1 RB_PWM3_OUT_EN PWM3 output enable 3 1 RB_PWM3_POLAR PWM3 output polarity 7 1 SERDES SERDES register (Please refer to subprogram library) SERDES 0x4000B000 0x0 0x400 registers n SPI0 SPI0 register SPI0 0x40004000 0x0 0x400 registers n R16_SPI0_TOTAL_CNT SPI0 total byte count, only low 12 bit 0xC 16 read-write n 0x0 0xFFFFFFFF R16_SPI0_TOTAL_CNT SPI total byte count, only low 12 bit 0 16 R32_SPI0_DMA_BEG SPI0 DMA begin address 0x18 32 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_BEG SPI DMA begin address 0 18 R32_SPI0_DMA_END SPI0 DMA end address 0x1C 32 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_END SPI DMA end address 0 18 R32_SPI0_DMA_NOW SPI0 DMA current address 0x14 32 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_NOW SPI DMA current address 0 18 R8_SPI0_BUFFER SPI0 data buffer 0x4 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_BUFFER SPI data buffer 0 8 R8_SPI0_CLOCK_DIV_R8_SPI0_SLAVE_PRE SPI0 master clock divisor / SPI0 slave preset value 0x3 8 read-write n 0x10 0xFFFFFFFF R8_SPI0_CLOCK_DIV_R8_SPI0_SLAVE_PRE master clock divisor / SPI0 slave preset value 0 8 R8_SPI0_CTRL_CFG SPI0 configuration control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_SPI_AUTO_IF enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag 4 1 RB_SPI_BIT_ORDER SPI bit data order 5 1 RB_SPI_DMA_ENABLE SPI DMA enable 0 1 RB_SPI_DMA_LOOP SPI DMA address loop enable 2 1 R8_SPI0_CTRL_MOD SPI0 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_SPI_2WIRE_MOD SPI enable 2 wire mode 2 1 RB_SPI_ALL_CLEAR force clear SPI FIFO and count 1 1 RB_SPI_FIFO_DIR SPI FIFO direction 4 1 RB_SPI_MISO_OE SPI MISO output enable 7 1 RB_SPI_MODE_SLAVE SPI slave mode 0 1 RB_SPI_MOSI_OE SPI MOSI output enable 6 1 RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD SPI master clock mode _ SPI slave command mode 3 1 RB_SPI_SCK_OE SPI SCK output enable 5 1 R8_SPI0_FIFO SPI0 FIFO register 0x10 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_FIFO SPI FIFO register 0 8 R8_SPI0_FIFO_COUNT SPI0 FIFO count status 0x7 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_FIFO_COUNT SPI FIFO count status 0 8 R8_SPI0_FIFO_COUNT1 SPI0 FIFO count status 0x13 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_FIFO_COUNT1 SPI FIFO count statu 0 8 R8_SPI0_INTER_EN SPI0 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_SPI_IE_BYTE_END enable interrupt for SPI byte exchanged 1 1 RB_SPI_IE_CNT_END enable interrupt for SPI total byte count end 0 1 RB_SPI_IE_DMA_END enable interrupt for SPI DMA completion 3 1 RB_SPI_IE_FIFO_HF enable interrupt for SPI FIFO half 2 1 RB_SPI_IE_FIFO_OV enable interrupt for SPI FIFO overflow 4 1 RB_SPI_IE_FST_BYTE enable interrupt for SPI slave mode first byte received 7 1 R8_SPI0_INT_FLAG SPI0 interrupt flag 0x6 8 read-write n 0x40 0xFFFFFFFF RB_SPI_FREE current SPI free status 6 1 RB_SPI_IF_BYTE_END interrupt flag for SPI byte exchanged 1 1 RB_SPI_IF_CNT_END interrupt flag for SPI total byte count end 0 1 RB_SPI_IF_DMA_END interrupt flag for SPI DMA completion 3 1 RB_SPI_IF_FIFO_HF interrupt flag for SPI FIFO half 2 1 RB_SPI_IF_FIFO_OV interrupt flag for SPI FIFO overflow 4 1 RB_SPI_IF_FST_BYTE interrupt flag for SPI slave mode first byte received 7 1 R8_SPI0_RUN_FLAG SPI0 work flag 0x5 8 read-only n 0x0 0xFFFFFFFF RB_SPI_FIFO_READY SPI FIFO ready status 5 1 RB_SPI_SLV_CMD_ACT SPI slave command flag 4 1 RB_SPI_SLV_CS_LOAD SPI slave chip-select loading status 6 1 RB_SPI_SLV_SELECT SPI slave selection status 7 1 SPI1 SPI1 register SPI1 0x40004400 0x0 0x400 registers n R16_SPI1_TOTAL_CNT SPI1 total byte count, only low 12 bit 0xC 16 read-write n 0x0 0xFFFFFFFF R16_SPI1_TOTAL_CNT SPI total byte count, only low 12 bit 0 16 R32_SPI1_DMA_BEG SPI1 DMA begin address 0x18 32 read-write n 0x0 0xFFFFFFFF R16_SPI1_DMA_BEG SPI DMA begin address 0 18 R32_SPI1_DMA_END SPI1 DMA end address 0x1C 32 read-write n 0x0 0xFFFFFFFF R16_SPI1_DMA_END SPI DMA end address 0 18 R32_SPI1_DMA_NOW SPI1 DMA current address 0x14 32 read-write n 0x0 0xFFFFFFFF R16_SPI1_DMA_NOW SPI DMA current address 0 18 R8_SPI1_BUFFER SPI1 data buffer 0x4 8 read-write n 0x0 0xFFFFFFFF R8_SPI1_BUFFER SPI data buffer 0 8 R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE SPI1 master clock divisor / SPI0 slave preset value 0x3 8 read-write n 0x10 0xFFFFFFFF R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRESET master clock divisor / SPI0 slave preset value 0 8 R8_SPI1_CTRL_CFG SPI1 configuration control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_SPI_AUTO_IF enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag 4 1 RB_SPI_BIT_ORDER SPI bit data order 5 1 RB_SPI_DMA_ENABLE SPI DMA enable 0 1 RB_SPI_DMA_LOOP SPI DMA address loop enable 2 1 R8_SPI1_CTRL_MOD SPI1 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_SPI_2WIRE_MOD SPI enable 2 wire mode 2 1 RB_SPI_ALL_CLEAR force clear SPI FIFO and count 1 1 RB_SPI_FIFO_DIR SPI FIFO direction 4 1 RB_SPI_MISO_OE SPI MISO output enable 7 1 RB_SPI_MODE_SLAVE SPI slave mode 0 1 RB_SPI_MOSI_OE SPI MOSI output enable 6 1 RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD SPI master clock mode / SPI slave command mode 3 1 RB_SPI_SCK_OE SPI SCK output enable 5 1 R8_SPI1_FIFO SPI1 FIFO register 0x10 8 read-write n 0x0 0xFFFFFFFF R8_SPI1_FIFO SPI FIFO register 0 8 R8_SPI1_FIFO_COUNT SPI1 FIFO count status 0x7 8 read-write n 0x0 0xFFFFFFFF R8_SPI1_FIFO_COUNT SPI FIFO count status 0 8 R8_SPI1_FIFO_COUNT1 SPI0 FIFO count status 0x13 8 read-write n 0x0 0xFFFFFFFF R8_SPI1_FIFO_COUNT1 SPI FIFO count statu 0 8 R8_SPI1_INTER_EN SPI1 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_SPI_IE_BYTE_END enable interrupt for SPI byte exchanged 1 1 RB_SPI_IE_CNT_END enable interrupt for SPI total byte count end 0 1 RB_SPI_IE_DMA_END enable interrupt for SPI DMA completion 3 1 RB_SPI_IE_FIFO_HF enable interrupt for SPI FIFO half 2 1 RB_SPI_IE_FIFO_OV enable interrupt for SPI FIFO overflow 4 1 RB_SPI_IE_FST_BYTE enable interrupt for SPI slave mode first byte received 7 1 R8_SPI1_INT_FLAG SPI1 interrupt flag 0x6 8 read-write n 0x40 0xFFFFFFFF RB_SPI_FREE current SPI free status 6 1 RB_SPI_IF_BYTE_END interrupt flag for SPI byte exchanged 1 1 RB_SPI_IF_CNT_END interrupt flag for SPI total byte count end 0 1 RB_SPI_IF_DMA_END interrupt flag for SPI DMA completion 3 1 RB_SPI_IF_FIFO_HF interrupt flag for SPI FIFO half 2 1 RB_SPI_IF_FIFO_OV interrupt flag for SPI FIFO overflow 4 1 RB_SPI_IF_FST_BYTE interrupt flag for SPI slave mode first byte received 7 1 R8_SPI1_RUN_FLAG SPI1 work flag 0x5 8 read n 0x0 0xFFFFFFFF RB_SPI_FIFO_READY SPI FIFO ready status 5 1 RB_SPI_SLV_CMD_ACT SPI slave command flag 4 1 RB_SPI_SLV_CS_LOAD SPI slave chip-select loading status 6 1 RB_SPI_SLV_SELECT SPI slave selection status 7 1 SYS SYS register SYS 0x40001000 0x0 0x400 registers n R16_SERD_ANA_CFG1 Serdes Analog parameter configuration1 0x20 16 read-write n 0x5A 0xFFFFFFFF RB_SERD_30M_SEL SerDes PHY reference clock source seletion 8 1 RB_SERD_DN_TST Enable SerDes PHY GXM test pin 9 1 RB_SERD_PLL_CFG SerDes PHY internal configuration bit 0 8 R32_PA_CLR GPIO PA clear output 0x4C 32 write-only n 0x0 0xFFFFFFFF R32_PA_CLR GPIO PA clear output 0 24 R32_PA_DIR GPIO PA I/O direction 0x40 32 read-write n 0x0 0xFFFFFFFF R32_PA_DIR GPIO PA I/O direction 0 24 R32_PA_DRV GPIO PA driving capability 0x58 32 read-write n 0x0 0xFFFFFFFF R32_PA_DRV GPIO PA driving capability 0 24 R32_PA_OUT GPIO PA output 0x48 32 read-write n 0x0 0xFFFFFFFF R32_PA_OUT GPIO PA output 0 24 R32_PA_PD GPIO PA output open-drain_input pulldown resistance enable 0x54 32 read-write n 0x0 0xFFFFFFFF R32_PA_PD GPIO PA output open-drain_input pulldown resistance enable 0 24 R32_PA_PIN GPIO PA input 0x44 32 read-only n 0x0 0xFFFFFFFF R32_PA_PIN GPIO PA input 0 24 R32_PA_PU GPIO PA pullup resistance enable 0x50 32 read-write n 0x0 0xFFFFFFFF R32_PA_PU GPIO PA pullup resistance enable 0 24 R32_PA_SMT GPIO PA output slew rate_input schmitt trigger 0x5C 32 read-write n 0x0 0xFFFFFFFF R32_PA_SMT GPIO PA output slew rate_input schmitt trigger 0 24 R32_PB_CLR GPIO PB clear output 0x6C 32 write-only n 0x0 0xFFFFFFFF R32_PB_CLR GPIO PB clear output 0 25 R32_PB_DIR GPIO PB I/O direction 0x60 32 read-write n 0x0 0xFFFFFFFF R32_PB_DIR GPIO PB I/O direction 0 25 R32_PB_DRV GPIO PB driving capability 0x78 32 read-write n 0x0 0xFFFFFFFF R32_PB_DRV GPIO PB driving capability 0 25 R32_PB_OUT GPIO PB output 0x68 32 read-write n 0x0 0xFFFFFFFF R32_PB_OUT GPIO PB output 0 25 R32_PB_PD GPIO PB output open-drain_input pulldown resistance enable 0x74 32 read-write n 0x0 0xFFFFFFFF R32_PB_PD GPIO PB output open-drain_input pulldown resistance enable 0 25 R32_PB_PIN GPIO PB input 0x64 32 read-only n 0x0 0xFFFFFFFF R32_PB_PIN GPIO PB input 0 25 R32_PB_PU GPIO PB pullup resistance enable 0x70 32 read-write n 0x0 0xFFFFFFFF R32_PB_PU GPIO PB pullup resistance enable 0 25 R32_PB_SMT GPIO PB output slew rate_input schmitt trigger 0x7C 32 read-write n 0x0 0xFFFFFFFF R32_PB_SMT GPIO PB output slew rate_input schmitt trigger 0 25 R32_SERD_ANA_CFG2 Serdes Analog parameter configuration2 0x24 32 read-write n 0x423015 0xFFFFFFFF RB_SERD_TRX_CFG Tx and RX parameter setting 0 25 R8_CHIP_ID chip ID register 0x1 8 read-only n 0x69 0xFFFFFFFF R8_CHIP_ID chip ID 0 8 R8_CLK_CFG_CTRL clock control 0xA 8 read-write n 0x80 0xFFFFFFFF RB_CLK_PLL_SLEEP PLL sleep control 0 1 RB_CLK_SEL_PLL clock source selection 1 1 R8_CLK_MOD_AUX clock mode aux register 0xB 8 read-write n 0x0 0xFFFFFFFF RB_EXT_125M_EN clock from pin_PA[16] 1 1 RB_INT_125M_EN clock from USB_PHY PCLK(125MHz) 0 1 RB_MCO_EN MCO output enable 4 1 RB_MCO_SEL_MSK MCO output selection 2 2 R8_CLK_PLL_DIV output clock divider from PLL 0x8 8 read-write n 0x42 0xFFFFFFFF R8_CLK_PLL_DIV output clock divider from PLL 0 8 R8_GLOB_RESET_KEEP value keeper during global reset 0x7 8 read-write n 0x0 0xFFFFFFFF R8_GLOB_RESET_KEEP value keeper during global reset 0 8 R8_GLOB_ROM_CFG flash ROM configuration register 0x4 8 n 0x80 0xFFFFFFFF RB_CODE_RAM_WE enable code RAM being write 1 1 read-write RB_ROM_CODE_OFS Config the start offset address of user code in Flash 4 1 read-write RB_ROM_CODE_WE enable flash ROM code_data area being erase/write 3 1 read-write RB_ROM_DATA_WE enable flash ROM data area being erase/write 2 1 read-write RB_ROM_EXT_RE enable flash ROM being read by external programmer 0 1 read-only R8_GPIO_INT_ENABLE GPIO interrupt enable 0x1D 8 read-write n 0x0 0xFFFFFFFF RB_GPIO_PB15_IE PB15 pin interrupt enable 7 1 R8_GPIO_INT_FLAG GPIO interrupt control 0x1C 8 read-write n 0x0 0xFFFFFFFF RB_GPIO_PB15_IF PB15 pin interrupt flag 7 1 R8_GPIO_INT_MODE GPIO interrupt mode 0x1E 8 read-write n 0x0 0xFFFFFFFF RB_GPIO_PB15_IM PB15 pin interrupt mode 7 1 R8_GPIO_INT_POLAR GPIO interrupt polarity 0x1F 8 read-write n 0x0 0xFFFFFFFF RB_GPIO_PB15_IP PB15 pin interrupt mode 7 1 R8_PIN_ALTERNATE alternate pin control 0x12 8 read-write n 0x0 0xFFFFFFFF RB_PIN_MII ETH mii interface selection 0 1 RB_PIN_TMR1 TMR1 alternate pin enable 1 1 RB_PIN_TMR2 TMR2 alternate pin enable 2 1 RB_PIN_UART0 RXD0/TXD0 alternate pin enable 4 1 R8_RST_BOOT_STAT reset status and boot/debug status 0x5 8 read-only n 0xC8 0xFFFFFFFF RB_BOOT_LOADER indicate boot loader status 5 1 RB_CFG_BOOT_EN boot-loader enable status 3 1 RB_CFG_DEBUG_EN debug enable status 4 1 RB_CFG_RESET_EN manual reset input enable status 2 1 RB_RESET_FLAG recent reset flag 0 2 R8_RST_WDOG_CTRL reset and watch-dog control 0x6 8 n 0x0 0xFFFFFFFF RB_SOFTWARE_RESET global software reset 0 1 write-only RB_WDOG_INT_EN watch-dog interrupt enable or INT_ID_WDOG interrupt source selection: 0=software interrupt 2 1 read-write RB_WDOG_INT_FLAG watch-dog timer overflow interrupt flag 3 1 read-write RB_WDOG_RST_EN enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow 1 1 read-write R8_SAFE_ACCESS_ID safe accessing ID register 0x2 8 read-only n 0x2 0xFFFFFFFF R8_SAFE_ACCESS_ID safe accessing ID 0 8 R8_SAFE_ACCESS_SIG safe accessing sign register 0x0 8 n 0x0 0xFFFFFFFF RB_SAFE_ACC_MODE current safe accessing mode 0 2 read-only RB_SAFE_ACC_TIMER safe accessing timer bit mask 4 3 read-only R8_SLP_CLK_OFF0 sleep clock off control byte 0 0xC 8 read-write n 0x0 0xFFFFFFFF RB_SLP_CLK_PWMX sleep PWMX clock 3 1 RB_SLP_CLK_TMR0 sleep TMR0 clock 0 1 RB_SLP_CLK_TMR1 sleep TMR1 clock 1 1 RB_SLP_CLK_TMR2 sleep TMR2 clock 2 1 RB_SLP_CLK_UART0 sleep UART0 clock 4 1 RB_SLP_CLK_UART1 sleep UART1 clock 5 1 RB_SLP_CLK_UART2 sleep UART2 clock 6 1 RB_SLP_CLK_UART3 sleep UART3 clock 7 1 R8_SLP_CLK_OFF1 sleep clock off control byte 1 0xD 8 n 0x0 0xFFFFFFFF RB_SLP_CLK_DVP sleep DVP clock 7 1 read-only RB_SLP_CLK_EMMC sleep EMMC clock 2 1 read-write RB_SLP_CLK_HSPI sleep HSPI clock 3 1 read-write RB_SLP_CLK_SERD sleep SERD clock 6 1 read-write RB_SLP_CLK_SPI0 sleep SPI0 clock 0 1 read-write RB_SLP_CLK_SPI1 sleep SPI1 clock 1 1 read-write RB_SLP_CLK_USBHS sleep USBHS clock 4 1 read-write RB_SLP_CLK_USBSS sleep USBSS clock 5 1 read-write R8_SLP_POWER_CTRL power control 0xF 8 read-write n 0x0 0xFFFFFFFF RB_SLP_USBHS_PWRDN enable USBHS power down 0 1 R8_SLP_WAKE_CTRL wake control 0xE 8 read-write n 0x0 0xFFFFFFFF RB_SLP_CLK_ECDC sleep ECDC clock 3 1 RB_SLP_CLK_ETH sleep ETH clock 2 1 RB_SLP_ETH_WAKE enable Eth waking 5 1 RB_SLP_GPIO_WAKE enable GPIO waking 4 1 RB_SLP_USBHS_WAKE enable USBHS waking 0 1 RB_SLP_USBSS_WAKE enable USBSS waking 1 1 R8_WDOG_COUNT watch-dog count register 0x3 8 read-write n 0x0 0xFFFFFFFF R8_WDOG_COUNT watch-dog count 0 8 R8_XBUS_CONFIG external bus configuration 0x10 8 read-write n 0x0 0xFFFFFFFF RB_XBUS_ADDR_OE external bus address output enable 2 2 RB_XBUS_ENABLE external bus enable 0 1 RB_XBUS_HOLD external bus hold time 6 1 RB_XBUS_SETUP external bus setup time 7 1 RB_XBUS_WIDTH external bus access pulse width 4 2 Systick Systick register Systick 0xE000F000 0x0 0x100 registers n STK_CMPHR Systick compare high register 0x10 32 read-write n 0x0 0xFFFFFFFF CMPH CMPH 0 32 STK_CMPLR Systick compare low register 0xC 32 read-write n 0x0 0xFFFFFFFF CMPL CMPL 0 32 STK_CNTFG Systick counter flag 0x14 32 read-write n 0x0 0xFFFFFFFF CNTIF Systick counter clear zero flag 1 1 SWIE System soft interrupt enable 0 1 STK_CNTH Systick counter high register 0x8 32 read-write n 0x0 0xFFFFFFFF CNTH CNTH 0 32 STK_CNTL Systick counter low register 0x4 32 read-write n 0x0 0xFFFFFFFF CNTL CNTL 0 32 STK_CTLR STK_CTLR Systick counter control register 0x0 32 n 0x0 0xFFFFFFFF STCLK System counter clock Source selection 2 1 read-write STE Systick counter enable 0 1 read-write STIE Systick counter interrupt enable 1 1 read-write STRELOAD System counter reload control 8 1 read-write TMR0 TMR0 register TMR0 0x40002000 0x0 0x400 registers n R32_TMR0_CNT_END TMR0 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR0_COUNT TMR0 current count 0 32 R32_TMR0_COUNT TMR0 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR0_COUNT TMR0 current count 0 32 R32_TMR0_FIFO TMR0 FIFO register, only low 26 bit 0x10 32 read-only/write-only n 0x0 0xFFFFFFFF R32_TMR0_FIFO TMR0 FIFO current count 0 32 R8_TMR0_CTRL_MOD TMR0 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN timer count enable 2 1 RB_TMR_MODE_IN timer in mode 0 1 RB_TMR_OUT_EN timer output enable 3 1 RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT timer PWM output polarity / Count sub-mode 4 1 RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE timer PWM repeat mode / timer capture edge mode 6 2 R8_TMR0_FIFO_COUNT TMR0 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR0_FIFO_COUNT TMR0 FIFO count status 0 8 R8_TMR0_INTER_EN TMR0 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3) 2 1 RB_TMR_IE_FIFO_OV enable interrupt for timer FIFO overflow 4 1 R8_TMR0_INT_FLAG TMR0 interrupt flag 0x6 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3) 2 1 RB_TMR_IF_FIFO_OV interrupt flag for timer FIFO overflow 4 1 TMR1 TMR1 register TMR1 0x40002400 0x0 0x400 registers n R32_TMR1_CNT_END TMR1 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR1_CNT_END TMR current count 0 32 R32_TMR1_COUNT TMR1 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR1_COUNT TMR current count 0 32 R32_TMR1_DMA_BEG TMR1 DMA begin address 0x18 32 read-write n 0x0 0xFFFFFFFF R16_TMR1_DMA_BEG TMR1 DMA begin address 0 18 R32_TMR1_DMA_END TMR1 DMA end address 0x1C 32 read-write n 0x0 0xFFFFFFFF R16_TMR1_DMA_END TMR1 DMA end address 0 18 R32_TMR1_DMA_NOW TMR1 DMA current address 0x14 32 read-write n 0x0 0xFFFFFFFF R16_TMR1_DMA_NOW TMR DMA current address 0 18 R32_TMR1_FIFO TMR1 FIFO only low 26 bit 0x10 32 read-only/write-only n 0x0 0xFFFFFFFF R32_TMR1_FIFO TMR current count 0 32 R8_TMR1_CTRL_DMA TMR1 DMA control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_TMR_DMA_ENABLE timer1/2 DMA enable 0 1 RB_TMR_DMA_LOOP timer1/2 DMA address loop enable 2 1 R8_TMR1_CTRL_MOD TMR1 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN timer count enable 2 1 RB_TMR_MODE_IN timer in mode 0 1 RB_TMR_OUT_EN timer output enable 3 1 RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT timer PWM output polarity / Count sub-mode 4 1 RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE timer PWM repeat mode / timer capture edge mode 6 2 R8_TMR1_FIFO_COUNT TMR1 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR1_FIFO_COUNT TMR FIFO count status 0 8 R8_TMR1_INTER_EN TMR1 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3) 2 1 RB_TMR_IE_FIFO_OV enable interrupt for timer FIFO overflow 4 1 R8_TMR1_INT_FLAG TMR1 interrupt flag 0x6 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3) 2 1 RB_TMR_IF_FIFO_OV interrupt flag for timer FIFO overflow 4 1 TMR2 TMR2 register TMR2 0x40002800 0x0 0x400 registers n R32_TMR2_CNT_END TMR2 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR2_CNT_END TMR current count 0 32 R32_TMR2_COUNT TMR2 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR2_COUNT TMR current count 0 32 R32_TMR2_DMA_BEG TMR2 DMA begin address 0x18 32 read-write n 0x0 0xFFFFFFFF R16_TMR2_DMA_BEG TMR2 DMA begin address 0 18 R32_TMR2_DMA_END TMR2 DMA end address 0x1C 32 read-write n 0x0 0xFFFFFFFF R16_TMR2_DMA_END TMR2 DMA begin address 0 18 R32_TMR2_DMA_NOW TMR2 DMA current address 0x14 32 read-write n 0x0 0xFFFFFFFF R16_TMR2_DMA_NOW TMR DMA current address 0 18 R32_TMR2_FIFO TMR2 end count value, only low 26 bit 0x10 32 read-only/write-only n 0x0 0xFFFFFFFF R32_TMR2_FIFO TMR current count 0 32 R8_TMR2_CTRL_DMA TMR2 DMA control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_TMR_DMA_ENABLE timer1/2 DMA enable 0 1 RB_TMR_DMA_LOOP timer1/2 DMA address loop enable 2 1 R8_TMR2_CTRL_MOD TMR2 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN timer count enable 2 1 RB_TMR_MODE_IN timer in mode 0 1 RB_TMR_OUT_EN timer output enable 3 1 RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT timer PWM output polarity / Count sub-mode 4 1 RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE timer PWM repeat mode / timer capture edge mode 6 2 R8_TMR2_FIFO_COUNT TMR2 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR2_FIFO_COUNT TMR FIFO count status 0 8 R8_TMR2_INTER_EN TMR2 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3) 2 1 RB_TMR_IE_FIFO_OV enable interrupt for timer FIFO overflow 4 1 R8_TMR2_INT_FLAG TMR2 interrupt flag 0x6 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3) 2 1 RB_TMR_IF_FIFO_OV interrupt flag for timer FIFO overflow 4 1 UART0 UART0 register UART0 0x40003000 0x0 0x400 registers n R16_UART0_DL UART0 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART0_DL UART divisor latch 0 16 R8_UART0_ADR UART0 slave address 0xF 8 read-write n 0xFF 0xFFFFFFFF R8_UART0_ADR UART0 slave address 0 8 R8_UART0_DIV UART0 pre-divisor latch byte 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART0_ADR UART pre-divisor latch byte 0 8 R8_UART0_FCR UART0 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN UART FIFO enable 0 1 RB_FCR_FIFO_TRIG UART receiver FIFO trigger level 6 2 RB_FCR_RX_FIFO_CLR clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART0_IER UART0 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_DTR_EN UART0 DTR/TNOW output pin enable 4 1 RB_IER_LINE_STAT UART interrupt enable for receiver line status 2 1 RB_IER_MODEM_CHG UART0 interrupt enable for modem status change 3 1 RB_IER_RECV_RDY UART interrupt enable for receiver data ready 0 1 RB_IER_RESET UART software reset control, high action, auto clear 7 1 RB_IER_RTS_EN UART0 RTS output pin enable 5 1 RB_IER_THR_EMPTY UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN UART TXD pin enable 6 1 R8_UART0_IIR UART0 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID UART FIFO enabled flag 6 2 RB_IIR_INT_MASK UART interrupt flag bit mask 1 3 RB_IIR_NO_INT UART no interrupt flag 0 1 R8_UART0_LCR UART0 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN UART break control enable 6 1 RB_LCR_DLAB_RB_LCR_GP_BIT UART reserved bit / UART general purpose bit 7 1 RB_LCR_PAR_EN UART parity enable 3 1 RB_LCR_PAR_MOD UART parity mode 4 2 RB_LCR_STOP_BIT UART stop bit length 2 1 RB_LCR_WORD_SZ UART word bit length 0 2 R8_UART0_LSR UART0 line status 0x5 8 read-only n 0xC0 0xFFFFFFFF RB_LSR_BREAK_ERR UART receiver break error 4 1 RB_LSR_DATA_RDY UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR UART receiver frame error 3 1 RB_LSR_OVER_ERR UART receiver overrun error 1 1 RB_LSR_PAR_ERR UART receiver frame error 2 1 RB_LSR_TX_ALL_EMP UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP UART transmitter fifo empty status 5 1 R8_UART0_MCR UART0 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_AU_FLOW_EN UART0 enable autoflow control 5 1 RB_MCR_DTR UART0 control DTR 0 1 RB_MCR_HALF UART0 enable half-duplex 7 1 RB_MCR_LOOP UART0 enable local loop back 4 1 RB_MCR_OUT1 UART0 control OUT1 2 1 RB_MCR_OUT2 UART control OUT2 3 1 RB_MCR_RTS UART0 control RTS 1 1 RB_MCR_TNOW UART0 enable TNOW output on DTR pin 6 1 R8_UART0_MSR UART0 modem status 0x6 8 read-only n 0x0 0xFFFFFFFF RB_MSR_CTS UART0 CTS action status 4 1 RB_MSR_CTS_CHG UART0 CTS changed status, high action 0 1 RB_MSR_DCD UART0 DCD action status 7 1 RB_MSR_DCD_CHG UART0 DCD changed status, high action 3 1 RB_MSR_DSR UART0 DSR action status 5 1 RB_MSR_DSR_CHG UART0 DSR changed status, high action 1 1 RB_MSR_RI UART0 RI action status 6 1 RB_MSR_RI_CHG UART0 RI changed status, high action 2 1 R8_UART0_RBR_R8_UART0_THR UART0 receiver buffer, receiving byte / UART0 transmitter holding, transmittal byte 0x8 8 read-write n 0x0 0xFFFFFFFF R8_UART0_RBR_R8_UART0_THR UART receiver buffer, receiving byte / UART transmitter holding, transmittal byte 0 8 R8_UART0_RFC UART0 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART_RFC UART receiver FIFO count 0 8 R8_UART0_TFC UART0 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART0_TFC UART transmitter FIFO count 0 8 UART1 UART1 register UART1 0x40003400 0x0 0x400 registers n R16_UART1_DL UART1 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART1_DL UART divisor latch 0 16 R8_UART1_DIV UART1 pre-divisor latch byte 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART1_DIV UART pre-divisor latch byte 0 8 R8_UART1_FCR UART1 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN UART FIFO enable 0 1 RB_FCR_FIFO_TRIG UART receiver FIFO trigger level 6 2 RB_FCR_RX_FIFO_CLR clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART1_IER UART1 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY UART interrupt enable for receiver data ready 0 1 RB_IER_RESET UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN UART TXD pin enable 6 1 R8_UART1_IIR UART1 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID UART FIFO enabled flag 6 2 RB_IIR_INT_MASK UART interrupt flag bit mask 1 3 RB_IIR_NO_INT UART no interrupt flag 0 1 R8_UART1_LCR UART1 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN UART break control enable 6 1 RB_LCR_DLAB_RB_LCR_GP_BIT UART reserved bit / UART general purpose bit 7 1 RB_LCR_PAR_EN UART parity enable 3 1 RB_LCR_PAR_MOD UART parity mode 4 2 RB_LCR_STOP_BIT UART stop bit length 2 1 RB_LCR_WORD_SZ UART word bit length 0 2 R8_UART1_LSR UART1 line status 0x5 8 read-only n 0xC0 0xFFFFFFFF RB_LSR_BREAK_ERR UART receiver break error 4 1 RB_LSR_DATA_RDY UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR UART receiver frame error 3 1 RB_LSR_OVER_ERR UART receiver overrun error 1 1 RB_LSR_PAR_ERR UART receiver frame error 2 1 RB_LSR_TX_ALL_EMP UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP UART transmitter fifo empty status 5 1 R8_UART1_MCR UART1 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_AU_FLOW_EN UART0 enable autoflow control 5 1 RB_MCR_OUT2 UART1 control OUT2 3 1 R8_UART1_RBR_R8_UART1_THR UART1 receiver buffer, receiving byte / UART1 transmitter holding, transmittal byte 0x8 8 read-write n 0x0 0xFFFFFFFF R8_UART1_RBR_R8_UART1_THR UART receiver buffer, receiving byte / UART transmitter holding, transmittal byte 0 8 R8_UART1_RFC UART1 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART1_RFC UART receiver FIFO count 0 8 R8_UART1_TFC UART1 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART1_TFC UART transmitter FIFO count 0 8 UART2 UART2 register UART2 0x40003800 0x0 0x400 registers n R16_UART2_DL UART2 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART2_DL UART divisor latch 0 16 R8_UART2_DIV UART2 pre-divisor latch byte 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART2_DIV UART pre-divisor latch byte 0 8 R8_UART2_FCR UART2 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN UART FIFO enable 0 1 RB_FCR_FIFO_TRIG UART receiver FIFO trigger level 6 2 RB_FCR_RX_FIFO_CLR clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART2_IER UART2 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY UART interrupt enable for receiver data ready 0 1 RB_IER_RESET UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN UART TXD pin enable 6 1 R8_UART2_IIR UART2 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID UART FIFO enabled flag 6 2 RB_IIR_INT_MASK UART interrupt flag bit mask 1 3 RB_IIR_NO_INT UART no interrupt flag 0 1 R8_UART2_LCR UART2 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN UART break control enable 6 1 RB_LCR_DLAB_RB_LCR_GP_BIT UART reserved bit / UART general purpose bit 7 1 RB_LCR_PAR_EN UART parity enable 3 1 RB_LCR_PAR_MOD UART parity mode 4 2 RB_LCR_STOP_BIT UART stop bit length 2 1 RB_LCR_WORD_SZ UART word bit length 0 2 R8_UART2_LSR UART2 line status 0x5 8 read-only n 0xC0 0xFFFFFFFF RB_LSR_BREAK_ERR UART receiver break error 4 1 RB_LSR_DATA_RDY UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR UART receiver frame error 3 1 RB_LSR_OVER_ERR UART receiver overrun error 1 1 RB_LSR_PAR_ERR UART receiver frame error 2 1 RB_LSR_TX_ALL_EMP UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP UART transmitter fifo empty status 5 1 R8_UART2_MCR UART2 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_AU_FLOW_EN UART0 enable autoflow control 5 1 RB_MCR_OUT2 UART2 control OUT2 3 1 R8_UART2_RBR_R8_UART2_THR UART2 receiver buffer, receiving byte / UART2 transmitter holding, transmittal byte 0x8 8 read-write n 0x0 0xFFFFFFFF R8_UART2_RBR_R8_UART2_THR UART receiver buffer, receiving byte / UART transmitter holding, transmittal byte 0 8 R8_UART2_RFC UART2 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART2_RFC UART receiver FIFO count 0 8 R8_UART2_TFC UART2 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART2_TFC UART transmitter FIFO count 0 8 UART3 UART3 register UART3 0x40003C00 0x0 0x400 registers n R16_UART3_DL UART3 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART3_DL UART divisor latch 0 16 R8_UART3_DIV UART3 pre-divisor latch byte 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART3_DIV UART pre-divisor latch byte 0 8 R8_UART3_FCR UART3 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN UART FIFO enable 0 1 RB_FCR_FIFO_TRIG UART receiver FIFO trigger level 6 2 RB_FCR_RX_FIFO_CLR clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART3_IER UART3 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY UART interrupt enable for receiver data ready 0 1 RB_IER_RESET UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN UART TXD pin enable 6 1 R8_UART3_IIR UART3 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID UART FIFO enabled flag 6 2 RB_IIR_INT_MASK UART interrupt flag bit mask 1 3 RB_IIR_NO_INT UART no interrupt flag 0 1 R8_UART3_LCR UART3 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN UART break control enable 6 1 RB_LCR_DLAB_RB_LCR_GP_BIT UART reserved bit / UART general purpose bit 7 1 RB_LCR_PAR_EN UART parity enable 3 1 RB_LCR_PAR_MOD UART parity mode 4 2 RB_LCR_STOP_BIT UART stop bit length 2 1 RB_LCR_WORD_SZ UART word bit length 0 2 R8_UART3_LSR UART3 line status 0x5 8 read-only n 0xC0 0xFFFFFFFF RB_LSR_BREAK_ERR UART receiver break error 4 1 RB_LSR_DATA_RDY UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR UART receiver frame error 3 1 RB_LSR_OVER_ERR UART receiver overrun error 1 1 RB_LSR_PAR_ERR UART receiver frame error 2 1 RB_LSR_TX_ALL_EMP UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP UART transmitter fifo empty status 5 1 R8_UART3_MCR UART3 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_AU_FLOW_EN UART0 enable autoflow control 5 1 RB_MCR_OUT2 UART3 control OUT2 3 1 R8_UART3_RBR_R8_UART3_THR UART3 receiver buffer, receiving byte / UART3 transmitter holding, transmittal byte 0x8 8 read-write n 0x0 0xFFFFFFFF R8_UART3_RBR_R8_UART3_THR UART receiver buffer, receiving byte / UART transmitter holding, transmittal byte 0 8 R8_UART3_RFC UART3 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART3_RFC UART receiver FIFO count 0 8 R8_UART3_TFC UART3 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART3_TFC UART transmitter FIFO count 0 8 USBHS USBHS register USBHS 0x40009000 0x0 0x400 registers n R16_UEP0_MAX_LEN endpoint 0 receive max length 0x50 16 read-write n 0x0 0xFFFFFFFF UEP0_MAX_LEN endpoint 0 receive max length 0 16 R16_UEP0_T_LEN endpoint 0 transmittal length 0x70 16 read-write n 0x0 0xFFFFFFFF UEP0_T_LEN endpoint 0 transmittal length 0 16 R16_UEP1_MAX_LEN endpoint 1 receive max length 0x54 16 read-write n 0x0 0xFFFFFFFF UEP1_MAX_LEN endpoint 1 receive max length 0 16 R16_UEP1_T_LEN endpoint 1 transmittal length 0x74 16 read-write n 0x0 0xFFFFFFFF UEP1_T_LEN endpoint 1 transmittal length 0 16 R16_UEP2_MAX_LEN_R16_UH_MAX_LEN endpoint 2 receive max length / USB host receive max packet length register 0x58 16 read-write n 0x0 0xFFFFFFFF UEP2_MAX_LEN_UH_MAX_LEN endpoint 2 receive max length / USB host receive max packet length register 0 16 R16_UEP2_T_LEN_R16_UH_EP_PID endpoint 2 transmittal length / Set usb host token register 0x78 16 read-write n 0x0 0xFFFFFFFF RB_UH_EPNUM_MASK_UEP2_T_LEN_0_3 The endpoint number of the target of this operation 0 4 RB_UH_TOKEN_MASK_UEP2_T_LEN_4_7 The token PID packet identification of this USB transfer transaction 4 4 UEP2_T_LEN_8_15 endpoint 2 transmittal length 8 8 R16_UEP3_MAX_LEN endpoint 3 receive max length 0x5C 16 read-write n 0x0 0xFFFFFFFF UEP3_MAX_LEN endpoint 3 receive max length 0 16 R16_UEP3_T_LEN_R16_UH_TX_LEN endpoint 3 transmittal length / host transmittal endpoint transmittal length 0x7C 16 read-write n 0x0 0xFFFFFFFF UEP3_T_LEN_UH_TX_LEN endpoint 3 transmittal length / host transmittal endpoint transmittal length 0 16 R16_UEP4_MAX_LEN endpoint 4 receive max length 0x60 16 read-write n 0x0 0xFFFFFFFF UEP4_MAX_LEN endpoint 4 receive max length 0 16 R16_UEP4_T_LEN_R16_UH_SPLIT_DATA endpoint 4 transmittal length / USB host Tx SPLIT packet data 0x80 16 read-write n 0x0 0xFFFFFFFF UEP4_T_LEN_UH_SPLIT_DATA endpoint 4 transmittal length / USB host Tx SPLIT packet data 0 16 R16_UEP5_MAX_LEN endpoint 5 receive max length 0x64 16 read-write n 0x0 0xFFFFFFFF UEP5_MAX_LEN endpoint 5 receive max length 0 16 R16_UEP5_T_LEN endpoint 5 transmittal length 0x84 16 read-write n 0x0 0xFFFFFFFF UEP5_T_LEN endpoint 5 transmittal length 0 16 R16_UEP6_MAX_LEN endpoint 6 receive max length 0x68 16 read-write n 0x0 0xFFFFFFFF UEP6_MAX_LEN endpoint 6 receive max length 0 16 R16_UEP6_T_LEN endpoint 6 transmittal length 0x88 16 read-write n 0x0 0xFFFFFFFF UEP6_T_LEN endpoint 6 transmittal length 0 16 R16_UEP7_MAX_LEN endpoint 7 receive max length 0x6C 16 read-write n 0x0 0xFFFFFFFF UEP7_MAX_LEN endpoint 7 receive max length 0 16 R16_UEP7_T_LEN endpoint 7 transmittal length 0x8C 16 read-write n 0x0 0xFFFFFFFF UEP7_T_LEN endpoint 7 transmittal length 0 16 R16_USB_FRAME_NO USB frame number register 0x4 16 read-only n 0x0 0xFFFFFFFF USB_FRAME_NO USB frame number 0 16 R32_UEP0_RT_DMA endpoint 0 DMA buffer address 0x14 32 read-write n 0x0 0xFFFFFFFF UEP0_RT_DMA endpoint 0 DMA buffer address 0 17 R32_UEP1_RX_DMA endpoint 1 DMA buffer address 0x18 32 read-write n 0x0 0xFFFFFFFF UEP1_RX_DMA endpoint 1 DMA buffer address 0 17 R32_UEP1_TX_DMA endpoint 1 DMA TX buffer address 0x34 32 read-write n 0x0 0xFFFFFFFF UEP1_TX_DMA endpoint 1 DMA TX buffer address 0 17 R32_UEP2_RX_DMA_R32_UH_RX_DMA endpoint 2 DMA buffer address / host rx endpoint buffer start address 0x1C 32 read-write n 0x0 0xFFFFFFFF UEP2_RX_DMA_UH_RX_DMA endpoint 2 DMA buffer address / host rx endpoint buffer start address 0 17 R32_UEP2_TX_DMA endpoint 2 DMA TX buffer address 0x38 32 read-write n 0x0 0xFFFFFFFF UEP2_TX_DMA endpoint 2 DMA TX buffer address 0 17 R32_UEP3_RX_DMA endpoint 3 DMA buffer address host tx endpoint buffer high address 0x20 32 read-write n 0x0 0xFFFFFFFF UEP3_RX_DMA endpoint 3 DMA buffer address 0 17 R32_UEP3_TX_DMA_R32_UH_TX_DMA endpoint 3 DMA TX buffer address / host tx endpoint buffer start address 0x3C 32 read-write n 0x0 0xFFFFFFFF UEP3_TX_DMA_UH_TX_DMA endpoint 3 DMA TX buffer address / host tx endpoint buffer start address 0 17 R32_UEP4_RX_DMA endpoint 4 DMA buffer address 0x24 32 read-write n 0x0 0xFFFFFFFF UEP4_RX_DMA endpoint 4 DMA buffer address 0 17 R32_UEP4_TX_DMA endpoint 4 DMA TX buffer address 0x40 32 read-write n 0x0 0xFFFFFFFF UEP4_TX_DMA endpoint 4 DMA TX buffer address 0 17 R32_UEP5_RX_DMA endpoint 5 DMA buffer address 0x28 32 read-write n 0x0 0xFFFFFFFF UEP5_RX_DMA endpoint 5 DMA buffer address 0 17 R32_UEP5_TX_DMA endpoint 5 DMA TX buffer address 0x44 32 read-write n 0x0 0xFFFFFFFF UEP5_TX_DMA endpoint 5 DMA TX buffer address 0 17 R32_UEP6_RX_DMA endpoint 6 DMA buffer address 0x2C 32 read-write n 0x0 0xFFFFFFFF UEP6_RX_DMA endpoint 6 DMA buffer address 0 17 R32_UEP6_TX_DMA endpoint 6 DMA TX buffer address 0x48 32 read-write n 0x0 0xFFFFFFFF UEP6_TX_DMA endpoint 6 DMA TX buffer address 0 17 R32_UEP7_RX_DMA endpoint 7 DMA buffer address 0x30 32 read-write n 0x0 0xFFFFFFFF UEP7_RX_DMA endpoint 7 DMA buffer address 0 17 R32_UEP7_TX_DMA endpoint 7 DMA TX buffer address 0x4C 32 read-write n 0x0 0xFFFFFFFF UEP7_TX_DMA endpoint 7 DMA TX buffer address 0 17 R6_USB_RX_LEN USB receiving length 0xC 16 read-only n 0x0 0xFFFFFFFF USB_RX_LEN length of received bytes 0 16 R8_UEP0_RX_CTRL endpoint 0 rx control 0x73 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP0_TX_CTRL endpoint 0 tx control 0x72 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP1_RX_CTRL endpoint 1 rx control 0x77 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP1_TX_CTRL endpoint 1 tx control 0x76 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP2_3_MOD_R8_UH_EP_MOD endpoint 2(10)/3(11) mode / USB host endpoint mode control register 0x11 8 read-write n 0x0 0xFFFFFFFF RB_UEP2_BUF_MOD_RB_UH_RX_EN buffer mode of USB endpoint 2(10) / USB host receive endpoint (IN) enable 0 1 RB_UEP2_RX_EN enable USB endpoint 2(10) receiving (OUT) 3 1 RB_UEP2_TX_EN enable USB endpoint 2(10) transmittal (IN) 2 1 RB_UEP3_BUF_MOD buffer mode of USB endpoint 3(11) 4 1 RB_UEP3_RX_EN enable USB endpoint 3(11) receiving (OUT) 7 1 RB_UEP3_TX_EN_RB_UH_TX_EN enable USB endpoint 3(11) transmittal (IN) / USB host send endpoint (SETUP/OUT) enable 6 1 R8_UEP2_RX_CTRL_R8_UH_RX_CTRL endpoint 2 rx control / USb host receive endpoint control register 0x7B 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK_RB_UH_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) / Host reeiver response control bit 0 2 RB_UEP_RRES_NO_RB_UH_RRES_NO prepared no response / Response control bit of host receiver 2 1 RB_UEP_R_AUTOTOG_RB_UH_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint / enable automatic toggle after successful receiver completion 5 1 RB_UEP_R_TOG_MASK_RB_UH_R_TOG_MASK expected data toggle flag of USB endpoint X receiving / expected data toggle flag of host receiving (IN) 3 2 RB_UH_RDATA_NO expect no data packet, for high speed hub in host mode 6 1 R8_UEP2_TX_CTRL endpoint 2 tx control 0x7A 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP3_RX_CTRL endpoint 3 rx control 0x7F 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP3_TX_CTRL_R8_UH_TX_CTRL endpoint 3 tx control / host transmittal endpoint control 0x7E 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK_RB_UH_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) / expected handshake response type for host transmittal (SETUP/OUT) 0 2 RB_UEP_TRES_NO_RB_UH_TRES_NO expected no response / expected no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions 2 1 RB_UEP_T_AUTOTOG_RB_UH_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 / enable automatic toggle after successful transfer completion 5 1 RB_UEP_T_TOG_MASK_RB_UH_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal / prepared data toggle flag of host transmittal (SETUP/OUT) 3 2 RB_UH_TDATA_NO prepared no data packet, for high speed hub in host mode 6 1 R8_UEP4_1_MOD endpoint 1(9)/4(8/12) mode 0x10 8 read-write n 0x0 0xFFFFFFFF RB_UEP1_BUF_MOD buffer mode of USB endpoint 1(9) 4 1 RB_UEP1_RX_EN enable USB endpoint 1(9) receiving (OUT) 7 1 RB_UEP1_TX_EN enable USB endpoint 1(9) transmittal (IN) 6 1 RB_UEP4_BUF_MOD buffer mode of USB endpoint 4(8/12) 0 1 RB_UEP4_RX_EN enable USB endpoint 4(8/12) receiving (OUT) 3 1 RB_UEP4_TX_EN enable USB endpoint 4(8/12) transmittal (IN) 2 1 R8_UEP4_RX_CTRL endpoint 4 rx control 0x83 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP4_TX_CTRL endpoint 4 tx control 0x82 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP5_6_MOD endpoint 5(13)/6(14) mode 0x12 8 read-write n 0x0 0xFFFFFFFF RB_UEP5_BUF_MOD buffer mode of USB endpoint 5(13) 0 1 RB_UEP5_RX_EN enable USB endpoint 5(13) receiving (OUT) 3 1 RB_UEP5_TX_EN enable USB endpoint 5(13) transmittal (IN) 2 1 RB_UEP6_BUF_MOD buffer mode of USB endpoint 6(14) 4 1 RB_UEP6_RX_EN enable USB endpoint 6(14) receiving (OUT) 7 1 RB_UEP6_TX_EN enable USB endpoint 6(14) transmittal (IN) 6 1 R8_UEP5_RX_CTRL endpoint 5 rx control 0x87 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP5_TX_CTRL endpoint 5 tx control 0x86 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP6_RX_CTRL endpoint 6 rx control 0x8B 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP6_TX_CTRL endpoint 6 tx control 0x8A 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UEP7_MOD endpoint 7(15) mode 0x13 8 read-write n 0x0 0xFFFFFFFF RB_UEP7_BUF_MOD buffer mode of USB endpoint 7(15) 0 1 RB_UEP7_RX_EN enable USB endpoint 7(15) receiving (OUT) 3 1 RB_UEP7_TX_EN enable USB endpoint 7(15) transmittal (IN) 2 1 R8_UEP7_RX_CTRL endpoint 7 rx control 0x8F 8 read-write n 0x0 0xFFFFFFFF RB_UEP_RRES_MASK bit mask of handshake response type for USB endpoint X receiving (OUT) 0 2 RB_UEP_RRES_NO prepared no response 2 1 RB_UEP_R_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 5 1 RB_UEP_R_TOG_MASK expected data toggle flag of USB endpoint X receiving 3 2 R8_UEP7_TX_CTRL endpoint 7 tx control 0x8E 8 read-write n 0x0 0xFFFFFFFF RB_UEP_TRES_MASK bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_TRES_NO expected no response 2 1 RB_UEP_T_AUTOTOG enable automatic toggle after successful transfer completion on endpoint 0 5 1 RB_UEP_T_TOG_MASK prepared data toggle flag of USB endpoint X transmittal 3 2 R8_UHOST_CTRL USB host control register 0x1 8 read-write n 0x0 0xFFFFFFFF RB_UH_AUTOSOF_EN Automatically generate sof packet enable control 7 1 RB_UH_BUS_RESET USB host send bus reset signal 0 1 RB_UH_BUS_RESUME USB host suspend state and wake up device 2 1 RB_UH_BUS_SUSPEND USB host send bus suspend signal 1 1 R8_USB_CTRL USB base control 0x0 8 read-write n 0x6 0xFFFFFFFF RB_DEV_PU_EN USB device enable and internal pullup resistance enable 4 1 RB_USB_CLR_ALL force clear FIFO and count of USB 1 1 RB_USB_DMA_EN DMA enable and DMA interrupt enable for USB 0 1 RB_USB_INT_BUSY enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 3 1 RB_USB_MODE enable USB host mode: 0=device mode, 1=host mode 7 1 RB_USB_RESET_SIE force reset USB SIE, need software clear 2 1 RB_USB_SPTP_MASK enable USB low speed 5 2 R8_USB_DEV_AD USB device address 0x3 8 read-write n 0x0 0xFFFFFFFF USB_ADDR_MASK bit mask for USB device address 0 7 R8_USB_INT_EN USB interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_USB_IE_BUSRST_RB_USB_IE_DETECT enable interrupt for USB bus reset event for USB device mode / enable interrupt for USB device detected event for USB host mode 0 1 RB_USB_IE_DEV_NAK enable interrupt for NAK responded for USB device mode 7 1 RB_USB_IE_FIFOOV enable interrupt for FIFO overflow 4 1 RB_USB_IE_ISOACT Synchronous transmission received control token packet interrupt 6 1 RB_USB_IE_SETUPACT Setup packet end interrupt 5 1 RB_USB_IE_SOF enable interrupt for host SOF timer action for USB host mode 3 1 RB_USB_IE_SUSPEND enable interrupt for USB suspend or resume event 2 1 RB_USB_IE_TRANS enable interrupt for USB transfer completion 1 1 R8_USB_INT_FG USB interrupt flag 0xA 8 read-write n 0x0 0xFFFFFFFF RB_USB_IF_BUSRST_RB_USB_IF_DETECT bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear 0 1 RB_USB_IF_FIFOOV FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 4 1 RB_USB_IF_HST_SOF host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 3 1 RB_USB_IF_ISOACT RO, Synchronous transmission received control token packet interrupt flag 6 1 RB_USB_IF_SETUOACT RO, Setup transaction end interrupt flag 5 1 RB_USB_IF_SUSPEND USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 2 1 RB_USB_IF_TRANSFER USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 1 1 R8_USB_INT_ST USB interrupt status 0xB 8 read-only n 0x0 0xFFFFFFFF RB_DEV_TOKEN_MASK RO, bit mask of current token PID code received for USB device mode 4 2 RB_HOST_RES_MASK_RB_DEV_ENDP_MASK RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received RO, bit mask of current transfer endpoint number for USB device mode 0 4 RB_USB_ST_NAK RO, indicate current USB transfer is NAK received for USB device mode 7 1 RB_USB_ST_TOGOK RO, indicate current USB transfer toggle is OK 6 1 R8_USB_MIS_ST USB miscellaneous status 0x9 8 read-only n 0x20 0xFFFFFFFF RB_USBBUS_RESET RO, indicate USB bus reset status 3 1 RB_USBBUS_SUSPEND RO, indicate USB suspend status 2 1 RB_USB_ATTACH RO, indicate device attached status on USB host 1 1 RB_USB_FIFO_RDY RO, indicate USB receiving FIFO ready status (not empty) 4 1 RB_USB_SIE_FREE RO, indicate USB SIE free status 5 1 RB_USB_SOF_ACT RO, indicate host SOF timer action status for USB host 6 1 RB_USB_SOF_PRES RO, indicate host SOF timer presage status 7 1 RB_USB_SPLIT_EN RO,indicate host allow SPLIT packet 0 1 R8_USB_SPD_TYPE USB actual speed register 0x8 8 read-only n 0x0 0xFFFFFFFF RB_USBSPEED_MASK USB actual speed 0 2 R8_USB_SUSPEND USB suspend register 0x6 8 read-write n 0x0 0xFFFFFFFF RB_DEV_WAKEUP Remote wake-up control bit 1 1 USBSS USBSS register (Please refer to subprogram library) USBSS 0x40008000 0x0 0x400 registers n