WCH CH573SFR 2025.05.09 WCH wireless MCU CH57x Family Support, Drivers RISC-V r0p0 little 2 false 8 32 BLE USB register USB 0x4000C000 0x0 0x1400 registers n BLEL LLE_IRQHandler 6 BLEB BB_IRQHandler 6 PFIC Program Fast Interrupt Controller PFIC 0xE000E000 0x0 0x1000 registers n R32_PFIC_CFGR CFGR Interrupt Config Register 0x48 32 read-write n 0x0 0xFFFFFFFF EXCRESET WO,EXCRESET 5 1 EXCSET WO,EXCSET 4 1 HWSTKCTRL RW,HWSTKCTRL 0 1 KEYCODE WO,KEYCODE 16 16 NESTCTRL RW,NESTCTRL 1 1 NMIRESET WO,NMIRESET 3 1 NMISET WO,NMISET 2 1 PFICRESET WO,PFICRSET 6 1 SYSRESET WO,SYSRESET 7 1 R32_PFIC_FIBADDRR FIBADDRR RW,Interrupt Fast Address Register 0x44 32 read-write n 0x0 0xFFFFFFFF BASEADDR BASEADDR 28 4 R32_PFIC_FIFOADDRR0 FIFOADDRR0 Interrupt 0 address Register 0x60 32 read-write n 0x0 0xFFFFFFFF IRQID0 RW,IRQID0 24 8 OFFADDR0 RW,OFFADDR0 0 24 R32_PFIC_FIFOADDRR1 FIFOADDRR1 Interrupt 1 address Register 0x64 32 read-write n 0x0 0xFFFFFFFF IRQID1 RW,IRQID1 24 8 OFFADDR1 RW,OFFADDR1 0 24 R32_PFIC_FIFOADDRR2 FIFOADDRR2 Interrupt 2 address Register 0x68 32 read-write n 0x0 0xFFFFFFFF IRQID2 RW,IRQID2 24 8 OFFADDR2 RW,OFFADDR2 0 24 R32_PFIC_FIFOADDRR3 FIFOADDRR3 Interrupt 3 address Register 0x6C 32 read-write n 0x0 0xFFFFFFFF IRQID3 RW,IRQID3 24 8 OFFADDR3 RW,OFFADDR3 0 24 R32_PFIC_GISR GISR Interrupt Global Register 0x4C 32 read-only n 0x0 0xFFFFFFFF GACTSTA RO,GACTSTA 8 1 GPENDSTA RO,GPENDSTA 9 1 NESTSTA RO,NESTSTA 0 8 R32_PFIC_IACTR1 IACTR1 Interrupt ACTIVE Register 0x300 32 read-write n 0x0 0xFFFFFFFF IACTS RW1,IACTS 12 20 R32_PFIC_IACTR2 IACTR2 Interrupt ACTIVE Register 0x304 32 read-write n 0x0 0xFFFFFFFF IACTS RW1,IACTS 0 4 R32_PFIC_IENR1 IENR1 Interrupt Setting Register 0x100 32 read-write n 0x0 0xFFFFFFFF INTEN RW1,INTEN 12 20 R32_PFIC_IENR2 IENR2 Interrupt Setting Register 0x104 32 read-write n 0x0 0xFFFFFFFF INTEN RW1,INTEN 0 4 R32_PFIC_IPR1 IPR1 RO,Interrupt Pending Register 0x20 32 n 0x0 0xFFFFFFFF PENDSTA PENDSTA 12 20 R32_PFIC_IPR2 IPR2 RO,Interrupt Pending Register 0x24 32 read-only n 0x0 0xFFFFFFFF PENDSTA PENDSTA 0 4 R32_PFIC_IPRIOR0 IPRIOR0 Interrupt Priority configuration Register 0x400 32 read-write n 0x0 0xFFFFFFFF IPRIOR0 RW,IPRIOR0 0 32 R32_PFIC_IPRIOR1 IPRIOR1 Interrupt Priority configuration Register 0x420 32 read-write n 0x0 0xFFFFFFFF IPRIOR1 >RW,IPRIOR1 0 32 R32_PFIC_IPRIOR10 IPRIOR10 Interrupt Priority configuration Register 0x540 32 read-write n 0x0 0xFFFFFFFF IPRIOR10 >RW,IPRIOR10 0 32 R32_PFIC_IPRIOR11 IPRIOR11 Interrupt Priority configuration Register 0x560 32 read-write n 0x0 0xFFFFFFFF IPRIOR11 RW,IPRIOR11 0 32 R32_PFIC_IPRIOR12 IPRIOR12 Interrupt Priority configuration Register 0x580 32 read-write n 0x0 0xFFFFFFFF IPRIOR12 RW,IPRIOR12 0 32 R32_PFIC_IPRIOR13 IPRIOR13 Interrupt Priority configuration Register 0x5A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR13 RW,IPRIOR13 0 32 R32_PFIC_IPRIOR14 IPRIOR14 Interrupt Priority configuration Register 0x5C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR14 RW,IPRIOR14 0 32 R32_PFIC_IPRIOR15 IPRIOR15 Interrupt Priority configuration Register 0x5E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR15 RW,IPRIOR15 0 32 R32_PFIC_IPRIOR16 IPRIOR16 Interrupt Priority configuration Register 0x600 32 read-write n 0x0 0xFFFFFFFF IPRIOR16 RW,IPRIOR16 0 32 R32_PFIC_IPRIOR17 IPRIOR17 Interrupt Priority configuration Register 0x620 32 read-write n 0x0 0xFFFFFFFF IPRIOR17 RW,IPRIOR17 0 32 R32_PFIC_IPRIOR18 IPRIOR18 Interrupt Priority configuration Register 0x640 32 read-write n 0x0 0xFFFFFFFF IPRIOR18 RW,IPRIOR18 0 32 R32_PFIC_IPRIOR19 IPRIOR19 Interrupt Priority configuration Register 0x660 32 read-write n 0x0 0xFFFFFFFF IPRIOR19 RW,IPRIOR19 0 32 R32_PFIC_IPRIOR2 IPRIOR2 Interrupt Priority configuration Register 0x440 32 read-write n 0x0 0xFFFFFFFF IPRIOR2 >RW,IPRIOR2 0 32 R32_PFIC_IPRIOR20 IPRIOR20 Interrupt Priority configuration Register 0x680 32 read-write n 0x0 0xFFFFFFFF IPRIOR20 RW,IPRIOR20 0 32 R32_PFIC_IPRIOR21 IPRIOR21 Interrupt Priority configuration Register 0x6A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR21 RW,IPRIOR21 0 32 R32_PFIC_IPRIOR22 IPRIOR22 Interrupt Priority configuration Register 0x6C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR22 RW,IPRIOR22 0 32 R32_PFIC_IPRIOR23 IPRIOR23 Interrupt Priority configuration Register 0x6E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR23 RW,IPRIOR23 0 32 R32_PFIC_IPRIOR24 IPRIOR24 Interrupt Priority configuration Register 0x700 32 read-write n 0x0 0xFFFFFFFF IPRIOR24 RW,IPRIOR24 0 32 R32_PFIC_IPRIOR25 IPRIOR25 Interrupt Priority configuration Register 0x720 32 read-write n 0x0 0xFFFFFFFF IPRIOR25 RW,IPRIOR25 0 32 R32_PFIC_IPRIOR26 IPRIOR26 Interrupt Priority configuration Register 0x740 32 read-write n 0x0 0xFFFFFFFF IPRIOR26 RW,IPRIOR26 0 32 R32_PFIC_IPRIOR27 IPRIOR27 Interrupt Priority configuration Register 0x760 32 read-write n 0x0 0xFFFFFFFF IPRIOR27 RW,IPRIOR27 0 32 R32_PFIC_IPRIOR28 IPRIOR28 Interrupt Priority configuration Register 0x780 32 read-write n 0x0 0xFFFFFFFF IPRIOR28 RW,IPRIOR28 0 32 R32_PFIC_IPRIOR29 IPRIOR29 Interrupt Priority configuration Register 0x7A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR29 RW,IPRIOR29 0 32 R32_PFIC_IPRIOR3 IPRIOR3 Interrupt Priority configuration Register 0x460 32 read-write n 0x0 0xFFFFFFFF IPRIOR3 >RW,IPRIOR3 0 32 R32_PFIC_IPRIOR30 IPRIOR30 Interrupt Priority configuration Register 0x7C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR30 RW,IPRIOR30 0 32 R32_PFIC_IPRIOR31 IPRIOR31 Interrupt Priority configuration Register 0x7E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR31 RW,IPRIOR31 0 32 R32_PFIC_IPRIOR32 IPRIOR32 Interrupt Priority configuration Register 0x800 32 read-write n 0x0 0xFFFFFFFF IPRIOR32 RW,IPRIOR32 0 32 R32_PFIC_IPRIOR33 IPRIOR33 Interrupt Priority configuration Register 0x820 32 read-write n 0x0 0xFFFFFFFF IPRIOR33 RW,IPRIOR33 0 32 R32_PFIC_IPRIOR34 IPRIOR34 Interrupt Priority configuration Register 0x840 32 read-write n 0x0 0xFFFFFFFF IPRIOR34 RW,IPRIOR34 0 32 R32_PFIC_IPRIOR35 IPRIOR35 Interrupt Priority configuration Register 0x860 32 read-write n 0x0 0xFFFFFFFF IPRIOR35 RW,IPRIOR35 0 32 R32_PFIC_IPRIOR36 IPRIOR36 Interrupt Priority configuration Register 0x880 32 read-write n 0x0 0xFFFFFFFF IPRIOR36 RW,IPRIOR36 0 32 R32_PFIC_IPRIOR37 IPRIOR37 Interrupt Priority configuration Register 0x8A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR37 RW,IPRIOR37 0 32 R32_PFIC_IPRIOR38 IPRIOR38 Interrupt Priority configuration Register 0x8C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR38 RW,IPRIOR38 0 32 R32_PFIC_IPRIOR39 IPRIOR39 Interrupt Priority configuration Register 0x8E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR39 RW,IPRIOR39 0 32 R32_PFIC_IPRIOR4 IPRIOR4 Interrupt Priority configuration Register 0x480 32 read-write n 0x0 0xFFFFFFFF IPRIOR4 >RW,IPRIOR4 0 32 R32_PFIC_IPRIOR40 IPRIOR40 Interrupt Priority configuration Register 0x900 32 read-write n 0x0 0xFFFFFFFF IPRIOR40 RW,IPRIOR40 0 32 R32_PFIC_IPRIOR41 IPRIOR41 Interrupt Priority configuration Register 0x920 32 read-write n 0x0 0xFFFFFFFF IPRIOR41 RW,IPRIOR41 0 32 R32_PFIC_IPRIOR42 IPRIOR42 Interrupt Priority configuration Register 0x940 32 read-write n 0x0 0xFFFFFFFF IPRIOR42 RW,IPRIOR42 0 32 R32_PFIC_IPRIOR43 IPRIOR43 Interrupt Priority configuration Register 0x960 32 read-write n 0x0 0xFFFFFFFF IPRIOR43 RW,IPRIOR43 0 32 R32_PFIC_IPRIOR44 IPRIOR44 Interrupt Priority configuration Register 0x980 32 read-write n 0x0 0xFFFFFFFF IPRIOR44 RW,IPRIOR44 0 32 R32_PFIC_IPRIOR45 IPRIOR45 Interrupt Priority configuration Register 0x9A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR45 RW,IPRIOR45 0 32 R32_PFIC_IPRIOR46 IPRIOR46 Interrupt Priority configuration Register 0x9C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR46 RW,IPRIOR46 0 32 R32_PFIC_IPRIOR47 IPRIOR47 Interrupt Priority configuration Register 0x9E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR47 RW,IPRIOR47 0 32 R32_PFIC_IPRIOR48 IPRIOR48 Interrupt Priority configuration Register 0xA00 32 read-write n 0x0 0xFFFFFFFF IPRIOR48 RW,IPRIOR48 0 32 R32_PFIC_IPRIOR49 IPRIOR49 Interrupt Priority configuration Register 0xA20 32 read-write n 0x0 0xFFFFFFFF IPRIOR49 RW,IPRIOR49 0 32 R32_PFIC_IPRIOR5 IPRIOR5 Interrupt Priority configuration Register 0x4A0 32 read-write n 0x0 0xFFFFFFFF IPRIOR5 >RW,IPRIOR5 0 32 R32_PFIC_IPRIOR50 IPRIOR50 Interrupt Priority configuration Register 0xA40 32 read-write n 0x0 0xFFFFFFFF IPRIOR50 RW,IPRIOR50 0 32 R32_PFIC_IPRIOR51 IPRIOR51 Interrupt Priority configuration Register 0xA60 32 read-write n 0x0 0xFFFFFFFF IPRIOR51 RW,IPRIOR51 0 32 R32_PFIC_IPRIOR52 IPRIOR52 Interrupt Priority configuration Register 0xA80 32 read-write n 0x0 0xFFFFFFFF IPRIOR52 RW,IPRIOR52 0 32 R32_PFIC_IPRIOR53 IPRIOR53 Interrupt Priority configuration Register 0xAA0 32 read-write n 0x0 0xFFFFFFFF IPRIOR53 RW,IPRIOR53 0 32 R32_PFIC_IPRIOR54 IPRIOR54 Interrupt Priority configuration Register 0xAD0 32 read-write n 0x0 0xFFFFFFFF IPRIOR54 RW,IPRIOR54 0 32 R32_PFIC_IPRIOR55 IPRIOR55 Interrupt Priority configuration Register 0xAE0 32 read-write n 0x0 0xFFFFFFFF IPRIOR55 RW,IPRIOR55 0 32 R32_PFIC_IPRIOR56 IPRIOR56 Interrupt Priority configuration Register 0xB00 32 read-write n 0x0 0xFFFFFFFF IPRIOR56 RW,IPRIOR56 0 32 R32_PFIC_IPRIOR57 IPRIOR57 Interrupt Priority configuration Register 0xB20 32 read-write n 0x0 0xFFFFFFFF IPRIOR57 RW,IPRIOR57 0 32 R32_PFIC_IPRIOR58 IPRIOR58 Interrupt Priority configuration Register 0xB40 32 read-write n 0x0 0xFFFFFFFF IPRIOR58 RW,IPRIOR58 0 32 R32_PFIC_IPRIOR59 IPRIOR59 Interrupt Priority configuration Register 0xB60 32 read-write n 0x0 0xFFFFFFFF IPRIOR59 RW,IPRIOR59 0 32 R32_PFIC_IPRIOR6 IPRIOR6 Interrupt Priority configuration Register 0x4C0 32 read-write n 0x0 0xFFFFFFFF IPRIOR6 >RW,IPRIOR6 0 32 R32_PFIC_IPRIOR60 IPRIOR60 Interrupt Priority configuration Register 0xB80 32 read-write n 0x0 0xFFFFFFFF IPRIOR60 RW,IPRIOR60 0 32 R32_PFIC_IPRIOR61 IPRIOR61 Interrupt Priority configuration Register 0xBA0 32 read-write n 0x0 0xFFFFFFFF IPRIOR61 RW,IPRIOR61 0 32 R32_PFIC_IPRIOR62 IPRIOR62 Interrupt Priority configuration Register 0xBE0 32 read-write n 0x0 0xFFFFFFFF IPRIOR62 RW,IPRIOR62 0 32 R32_PFIC_IPRIOR63 IPRIOR63 Interrupt Priority configuration Register 0xC00 32 read-write n 0x0 0xFFFFFFFF IPRIOR63 RW,IPRIOR63 0 32 R32_PFIC_IPRIOR7 IPRIOR7 Interrupt Priority configuration Register 0x4E0 32 read-write n 0x0 0xFFFFFFFF IPRIOR7 >RW,IPRIOR7 0 32 R32_PFIC_IPRIOR8 IPRIOR8 Interrupt Priority configuration Register 0x500 32 read-write n 0x0 0xFFFFFFFF IPRIOR8 >RW,IPRIOR8 0 32 R32_PFIC_IPRIOR9 IPRIOR9 Interrupt Priority configuration Register 0x520 32 read-write n 0x0 0xFFFFFFFF IPRIOR9 >RW,IPRIOR9 0 32 R32_PFIC_IPRR1 IPRR1 Interrupt Pending Clear Register 0x280 32 read-write n 0x0 0xFFFFFFFF PENDRESET RW1,PENDRESET 12 20 R32_PFIC_IPRR2 IPRR2 Interrupt Pending Clear Register 0x284 32 read-write n 0x0 0xFFFFFFFF PENDRESET RW1,PENDRESET 0 4 R32_PFIC_IPSR1 IPSR1 Interrupt Pending Register 0x200 32 read-write n 0x0 0xFFFFFFFF PENDSET RW1,PENDSET 12 20 R32_PFIC_IPSR2 IPSR2 Interrupt Pending Register 0x204 32 read-write n 0x0 0xFFFFFFFF PENDSET RW1,PENDSET 0 4 R32_PFIC_IRER1 IRER1 Interrupt Clear Register 0x180 32 read-write n 0x0 0xFFFFFFFF INTRESET RW1,INTRESET 12 20 R32_PFIC_IRER2 IRER2 Interrupt Clear Register 0x184 32 read-write n 0x0 0xFFFFFFFF INTRESET RW1,INTRESET 0 4 R32_PFIC_ISR1 ISR1 RO,Interrupt Status Register 0x0 32 n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 12 20 R32_PFIC_ISR2 ISR2 RO,Interrupt Status Register 0x4 32 n 0x0 0xFFFFFFFF INTENSTA Interrupt ID Status 0 4 R32_PFIC_ITHRESDR ITHRESDR RW,Interrupt Priority Register 0x40 32 read-write n 0x0 0xFFFFFFFF THRESHOLD RW,THRESHOLD 0 8 R32_PFIC_SCTLR SCTLR System Control Register 0xD10 32 read-write n 0x0 0xFFFFFFFF SETEVENT WO,SETEVENT 5 1 SEVONPEND RW,SEVONPEND 4 1 SLEEPDEEP RW,SLEEPDEEP 2 1 SLEEPONEXIT RW,SLEEPONEXIT 1 1 WFITOWFE RW,WFITOWFE 3 1 R32_PFIC_VTCTLR VTCTLR System Control Register 0xD14 32 read-write n 0x0 0xFFFFFFFF VTADDR VTADDR 0 1 PWMx PWMx register PWMx 0x40005000 0x0 0x400 registers n R8_PWM10_DATA RW, PWM10 data holding 0xA 8 read-write n 0x0 0xFFFFFFFF R8_PWM10_DATA RW, PWM10 data holding 0 8 R8_PWM11_DATA RW, PWM11 data holding 0xB 8 read-write n 0x0 0xFFFFFFFF R8_PWM11_DATA RW, PWM11 data holding 0 8 R8_PWM4_DATA RW, PWM4 data holding 0x4 8 read-write n 0x0 0xFFFFFFFF R8_PWM4_DATA RW, PWM4 data holding 0 8 R8_PWM5_DATA RW, PWM5 data holding 0x5 8 read-write n 0x0 0xFFFFFFFF R8_PWM5_DATA RW, PWM5 data holding 0 8 R8_PWM6_DATA RW, PWM6 data holding 0x6 8 read-write n 0x0 0xFFFFFFFF R8_PWM6_DATA RW, PWM6 data holding 0 8 R8_PWM7_DATA RW, PWM7 data holding 0x7 8 read-write n 0x0 0xFFFFFFFF R8_PWM7_DATA RW, PWM7 data holding 0 8 R8_PWM8_DATA RW, PWM8 data holding 0x8 8 read-write n 0x0 0xFFFFFFFF R8_PWM8_DATA RW, PWM8 data holding 0 8 R8_PWM9_DATA RW, PWM9 data holding 0x9 8 read-write n 0x0 0xFFFFFFFF R8_PWM9_DATA RW, PWM9 data holding 0 8 R8_PWM_CLOCK_DIV RW, PWM clock divisor 0x3 8 read-write n 0x0 0xFFFFFFFF R8_PWM_CLOCK_DIV RW, PWM clock divisor 0 8 R8_PWM_CONFIG RW, PWM configuration 0x2 8 read-write n 0x0 0xFFFFFFFF RB_PWM10_11_STAG_EN RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output 7 1 RB_PWM4_5_STAG_EN RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output 4 1 RB_PWM6_7_STAG_EN RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output 5 1 RB_PWM8_9_STAG_EN RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output 6 1 RB_PWM_CYCLE_SEL RW, PWM cycle selection: 0=256 128 64 32 clocks, 1=255 127 63 31 clocks 0 1 RB_PWM_CYC_MOD RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data 2 2 RB_PWM_STAG_ST RO, PWM stagger cycle status 1 1 read-only R8_PWM_INT_CTRL RW, PWM interrupt control 0xC 8 read-write n 0x0 0xFFFFFFFF RB_PWM_CYC_PRE RW, select PWM cycle interrupt point 1 1 RB_PWM_IE_CYC RW, enable interrupt for PWM cycle end 0 1 RB_PWM_IF_CYC RW1, interrupt flag for PWM cycle end 7 1 R8_PWM_OUT_EN RW, PWM output enable control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_PWM10_OUT_EN RW, PWM10 output enable 6 1 RB_PWM11_OUT_EN RW, PWM11 output enable 7 1 RB_PWM4_OUT_EN RW, PWM4 output enable 0 1 RB_PWM5_OUT_EN RW, PWM5 output enable 1 1 RB_PWM6_OUT_EN RW, PWM6 output enable 2 1 RB_PWM7_OUT_EN RW, PWM7 output enable 3 1 RB_PWM8_OUT_EN RW, PWM8 output enable 4 1 RB_PWM9_OUT_EN RW, PWM9 output enable 5 1 R8_PWM_POLAR RW, PWM output polarity control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_PWM10_POLAR RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action 6 1 RB_PWM11_POLAR RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action 7 1 RB_PWM4_POLAR RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action 0 1 RB_PWM5_POLAR RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action 1 1 RB_PWM6_POLAR RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action 2 1 RB_PWM7_POLAR RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action 3 1 RB_PWM8_POLAR RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action 4 1 RB_PWM9_POLAR RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action 5 1 SPI0 SPI0 register SPI 0x40004000 0x0 0x400 registers n SPI0 SPI0_IRQHandler 5 R16_SPI0_DMA_BEG RW, SPI0 DMA begin address 0x18 16 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_BEG RW, SPI0 DMA begin address 0 16 R16_SPI0_DMA_END RW, SPI0 DMA end address 0x1C 16 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_END RW, SPI0 DMA end address 0 16 R16_SPI0_DMA_NOW RW, SPI0 DMA current address 0x14 16 read-write n 0x0 0xFFFFFFFF R16_SPI0_DMA_NOW RW, SPI0 DMA current address 0 16 R16_SPI0_TOTAL_CNT RW, SPI0 total byte count, only low 12 bit 0xC 16 read-write n 0x0 0xFFFFFFFF R16_SPI0_TOTAL_CNT RW, SPI0 total byte count, only low 12 bit 0 16 R8_SPI0_BUFFER RW, SPI0 data buffer 0x4 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_BUFFER RW, SPI0 data buffer 0 8 R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE RW, SPI0 master clock divisor RW, SPI0 slave preset value 0x3 8 read-write n 0x10 0xFFFFFFFF R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE RW, SPI0 master clock divisor RW, SPI0 slave preset value 0 8 R8_SPI0_CTRL_CFG RW, SPI0 configuration control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_SPI_AUTO_IF RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag 4 1 RB_SPI_BIT_ORDER RW, SPI bit data order: 0=MSB first, 1=LSB first 5 1 RB_SPI_DMA_ENABLE RW, SPI0 DMA enable 0 1 RB_SPI_DMA_LOOP RW, SPI0 DMA address loop enable 2 1 RB_SPI_MST_DLY_EN RW, SPI master input delay enable 6 1 R8_SPI0_CTRL_MOD RW, SPI0 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_SPI_2WIRE_MOD RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX) 2 1 RB_SPI_ALL_CLEAR RW, force clear SPI FIFO and count 1 1 RB_SPI_FIFO_DIR RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) 4 1 RB_SPI_MISO_OE RW, SPI MISO output enable 7 1 RB_SPI_MODE_SLAVE RW, SPI0 slave mode: 0=master or host, 1=slave or device 0 1 RB_SPI_MOSI_OE RW, SPI MOSI output enable 6 1 RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD RW, SPI master clock mode: 0=mode 0, 1=mode 3 RW, SPI0 slave command mode: 0=byte stream, 1=first byte command 3 1 RB_SPI_SCK_OE RW, SPI SCK output enable 5 1 R8_SPI0_FIFO RO/WO, SPI0 FIFO register 0x10 8 read-write n 0x0 0xFFFFFFFF R8_SPI0_FIFO RO/WO, SPI0 FIFO register 0 8 R8_SPI0_FIFO_COUNT RO, SPI0 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_SPI0_FIFO_COUNT RO, SPI0 FIFO count status 0 8 R8_SPI0_FIFO_COUNT1 RO, SPI0 FIFO count status 0x13 8 read-only n 0x0 0xFFFFFFFF R8_SPI0_FIFO_COUNT1 RO, SPI0 FIFO count status 0 8 R8_SPI0_INTER_EN RW, SPI0 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_SPI_IE_BYTE_END RW, enable interrupt for SPI byte exchanged 1 1 RB_SPI_IE_CNT_END RW, enable interrupt for SPI total byte count end 0 1 RB_SPI_IE_DMA_END RW, enable interrupt for SPI0 DMA completion 3 1 RB_SPI_IE_FIFO_HF RW, enable interrupt for SPI FIFO half 2 1 RB_SPI_IE_FIFO_OV RW, enable interrupt for SPI0 FIFO overflow 4 1 RB_SPI_IE_FST_BYTE RW, enable interrupt for SPI0 slave mode first byte received 7 1 R8_SPI0_INT_FLAG RW1, SPI0 interrupt flag 0x6 8 read-write n 0x40 0xFFFFFFFF RB_SPI_FREE RO, current SPI free status 6 1 RB_SPI_IF_BYTE_END RW1, interrupt flag for SPI byte exchanged 1 1 RB_SPI_IF_CNT_END RW1, interrupt flag for SPI total byte count end 0 1 RB_SPI_IF_DMA_END RW1, interrupt flag for SPI0 DMA completion 3 1 RB_SPI_IF_FIFO_HF RW1, interrupt flag for SPI FIFO half 2 1 RB_SPI_IF_FIFO_OV RW1, interrupt flag for SPI0 FIFO overflow 4 1 RB_SPI_IF_FST_BYTE RW1, interrupt flag for SPI0 slave mode first byte received 7 1 R8_SPI0_RUN_FLAG RO, SPI0 work flag 0x5 8 read-only n 0x0 0xFFFFFFFF RB_SPI_FIFO_READY RO, SPI FIFO ready status 5 1 RB_SPI_SLV_CMD_ACT RO, SPI0 slave first byte or command flag 4 1 RB_SPI_SLV_CS_LOAD RO, SPI0 slave chip-select loading status 6 1 RB_SPI_SLV_SELECT RO, SPI0 slave selection status 7 1 SYS System Control Register SystemControl 0x40001000 0x0 0x400 registers n TMR0 TMR0_IRQHandler 1 GPIO_A GPIO_IRQHandler 3 GPIO_B GPIO_IRQHandler 4 SPI0 SPI0_IRQHandler 5 BLEL LLE_IRQHandler 6 BLEB BB_IRQHandler 7 USB USB_IRQHandler 8 TMR1 TMR1_IRQHandler 10 TMR2 TMR2_IRQHandler 11 UART0 UART0_IRQHandler 12 UART1 UART1_IRQHandler 13 RTC RTC_IRQHandler 14 ADC ADC_IRQHandler 15 PWMX PWMX_IRQHandler 17 TMR3 TMR3_IRQHandler 18 UART2 UART2_IRQHandler 19 UART3 UART3_IRQHandler 20 WDOG_BAT WDT_IRQHandler 21 R16_ADC_DATA RO, ADC data 0x5C 16 read-only n 0x0 0xFFFFFFFF RB_ADC_DATA RO, ADC conversion data 0 12 R16_ADC_DMA_BEG RW, ADC DMA begin address 0x68 8 write-read n 0x0 0xFFFFFFFF R16_ADC_DMA_BEG ADC DMA begin address 0 16 R16_ADC_DMA_END RW, ADC DMA end address 0x6C 8 write-read n 0x0 0xFFFFFFFF R16_ADC_DMA_END ADC DMA end address 0 16 R16_ADC_DMA_NOW RO, ADC DMA current address 0x64 8 read-only n 0x0 0xFFFFFFFF R16_ADC_DMA_NOW ADC DMA current address 0 16 R16_CLK_SYS_CFG RWA, system clock configuration, SAM 0x8 16 read-write n 0x5 0xFFFFFFFF RB_CLK_PLL_DIV RWA, output clock divider from PLL or CK32M 0 5 read-write RB_CLK_SYS_MOD RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz 6 2 read-write R16_INT32K_TUNE RWA, internal 32KHz oscillator tune control, SAM 0x2C 16 Read or Write under safe Accessing mode n 0x800 0xFFFFFFFF RB_INT32K_TUNE RWA, internal 32KHz oscillator frequency tune 0 12 R16_OSC_CAL_CNT RO, system clock count value for 32KHz 5 cycles 0x50 16 read-only n 0x0 0xFFFFFFFF RB_OSC_CAL_CNT RO, system clock count value for 32KHz 5 cycles 0 14 R16_PA_INT_EN RW, GPIO PA interrupt enable 0x90 16 read-write n 0x0 0xFFFFFFFF R16_PA_INT_EN GPIO PA interrupt enable 0 16 R16_PA_INT_IF RW1, GPIO PA interrupt flag 0x9C 16 read-write n 0x0 0xFFFFFFFF R16_PA_INT_IF GPIO PA interrupt flag 0 16 R16_PA_INT_MODE RW, GPIO PA interrupt mode: 0=level action, 1=edge action 0x94 16 read-write n 0x0 0xFFFFFFFF R16_PA_INT_MODE GPIO PA interrupt mode 0 16 R16_PB_INT_EN RW, GPIO PB interrupt enable 0x92 16 read-write n 0x0 0xFFFFFFFF R16_PB_INT_EN GPIO PB interrupt enable 0 16 R16_PB_INT_IF RW1, GPIO PB interrupt flag 0x9E 16 read-write n 0x0 0xFFFFFFFF R16_PB_INT_IF GPIO PB interrupt flag 0 16 R16_PB_INT_MODE RW, GPIO PB interrupt mode: 0=level action, 1=edge action RW, status for parallel slave read 0x96 16 read-write n 0x0 0xFFFFFFFF R16_PB_INT_MODE GPIO PB interrupt mode 0 16 R16_PIN_ALTERNATE RW, function pin alternate configuration 0x18 16 read-write n 0x0 0xFFFFFFFF RB_PIN_SPI0 RW, SCS/SCK0/MOSI/MISO alternate pin enable 8 1 RB_PIN_TMR0 RW, TMR0 alternate pin enable 0 1 RB_PIN_TMR1 RW, TMR1 alternate pin enable 1 1 RB_PIN_TMR2 RW, TMR2 alternate pin enable 2 1 RB_PIN_UART0 RW, RXD0/TXD0 alternate pin enable 4 1 RB_PIN_UART1 RW, RXD1/TXD1 alternate pin enable 5 1 R16_PIN_ANALOG_IE RW, analog pin enable and digital input disable 0x1A 16 read-write n 0x0 0xFFFFFFFF RB_PIN_ADC0_IE RW, ADC/TouchKey channel0 digital input disable: 0=digital input enable, 1=digital input disable 9 1 RB_PIN_ADC12_IE RW, ADC/TouchKey channel12 digital input disable: 0=digital input enable, 1=digital input disable 11 1 RB_PIN_ADC13_IE RW, ADC/TouchKey channel13 digital input disable: 0=digital input enable, 1=digital input disable 12 1 RB_PIN_ADC1_IE RW, ADC/TouchKey channel1 digital input disable: 0=digital input enable, 1=digital input disable 10 1 RB_PIN_ADC2_3_IE RW, ADC/TouchKey channel 2/3 digital input disable: 0=digital input enable, 1=digital input disable 14 1 RB_PIN_ADC4_5_IE RW, ADC/TouchKey channel 4/5 digital input disable: 0=digital input enable, 1=digital input disable 15 1 RB_PIN_ADC8_9_IE RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable 8 1 RB_PIN_USB_DP_PU RW,USB UDP internal pullup resistance enable 6 1 RB_PIN_USB_IE RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable 7 1 RB_PIN_XT32K_IE RW, external 32KHz oscillator digital input disable: 0=digital input enable, 1=digital input disable 13 1 R16_POWER_PLAN RWA, power plan before sleep instruction, SAM 0x20 16 Read or Write under safe Accessing mode n 0x11DF 0xFFFFFFFF RB_PWR_CORE RWA, power retention for core and base peripherals 2 1 RB_PWR_DCDC_EN RWA, DC/DC converter enable: 0=DC/DC disable and bypass, 1=DC/DC enable 9 1 RB_PWR_DCDC_PRE RWA, DC/DC converter pre-enable 10 1 RB_PWR_EXTEND RWA, power retention for USB and BLE 3 1 RB_PWR_LDO_EN RWA, LDO enable 8 1 RB_PWR_MUST_0010 RWA, power plan enable, auto clear after sleep executed 11 4 read-only RB_PWR_PLAN_EN RWA, must write 0010 15 1 read-only RB_PWR_RAM16K RWA, power for main SRAM 4 1 RB_PWR_RAM2K RWA, power for retention 2KB SRAM 1 1 RB_PWR_SYS_EN RWA, power for system 7 1 RB_PWR_XROM RWA, power for retention 2KB SRAM 0 1 R16_RTC_CNT_2S RO, RTC count based 2 second 0x3A 16 read-only n 0x0 0xFFFFFFFF R16_RTC_CNT_2S RO, RTC count based 2 second 0 16 R16_RTC_CNT_32K RO, RTC count based 32KHz 0x38 16 read-only n 0x0 0xFFFFFFFF R16_RTC_CNT_32K RWA,RTC count based 32KHz 0 16 R32_ADC_DMA_CTRL RO, ADC DMA control and status register 0x60 8 write-read n 0x0 0xFFFFFFFF R32_ADC_DMA_CTRL RW, ADC DMA enable 0 8 R32_PA_CLR WZ, GPIO PA clear output: 0=keep, 1=clear 0xAC 32 read-write n 0x0 0xFFFFFFFF R8_PA_CLR_0 GPIO PA clear output byte 0 0 8 R8_PA_CLR_1 GPIO PA clear output byte 1 8 8 R32_PA_DIR RW, GPIO PA I/O direction: 0=in, 1=out 0xA0 32 read-write n 0x0 0xFFFFFFFF R8_PA_DIR_0 GPIO PA I/O direction byte 0 0 8 R8_PA_DIR_1 GPIO PA I/O direction byte 1 8 8 R32_PA_OUT RW, GPIO PA output 0xA8 32 read-write n 0x0 0xFFFFFFFF R8_PA_OUT_0 GPIO PA output byte 0 0 8 R8_PA_OUT_1 GPIO PA output byte 1 8 8 R32_PA_PD_DRV RW, PA pulldown for input or PA driving capability for output 0xB4 32 read-write n 0x0 0xFFFFFFFF R8_PA_PD_DRV_0 PA pulldown for input or PA driving capability for output byte 0 0 8 R8_PA_PD_DRV_1 PA pulldown for input or PA driving capability for output byte 1 8 8 R32_PA_PIN RO, GPIO PA input 0xA4 32 read-only n 0x0 0xFFFFFFFF R8_PA_PIN_0 GPIO PA input byte 0 0 8 R8_PA_PIN_1 GPIO PA input byte 1 8 8 R32_PA_PU RW, GPIO PA pullup resistance enable 0xB0 32 read-write n 0x0 0xFFFFFFFF R8_PA_PU_0 GPIO PA pullup resistance enable byte 0 0 8 R8_PA_PU_1 GPIO PA pullup resistance enable byte 0 8 8 R32_PB_CLR WZ, GPIO PB clear output: 0=keep, 1=clear 0xCC 32 read-write n 0x0 0xFFFFFFFF R8_PB_CLR_0 GPIO PB clear output byte 0 0 8 R8_PB_CLR_1 GPIO PB clear output byte 1 8 8 R8_PB_CLR_2 GPIO PB clear output byte 2 16 8 R32_PB_DIR RW, GPIO PB I/O direction: 0=in, 1=out 0xC0 32 read-write n 0x0 0xFFFFFFFF R8_PB_DIR_0 GPIO PB I/O direction byte 0 0 8 R8_PB_DIR_1 GPIO PB I/O direction byte 1 8 8 R8_PB_DIR_2 GPIO PB I/O direction byte 2 16 8 R32_PB_OUT__R8_SLV_RD_DATA RW, GPIO PB output RW, data for parallel slave read 0xC8 32 read-write n 0x0 0xFFFFFFFF R8_PB_OUT_0 GPIO PB output byte 0 0 8 R8_PB_OUT_1 GPIO PB output byte 1 8 8 R8_PB_OUT_2 GPIO PB output byte 2 16 8 R32_PB_PD_DRV RW, PB pulldown for input or PB driving capability for output 0xD4 32 read-write n 0x0 0xFFFFFFFF R8_PB_PD_DRV_0 PB pulldown for input or PB driving capability for output byte 0 0 8 R8_PB_PD_DRV_1 PB pulldown for input or PB driving capability for output byte 0 8 8 R8_PB_PD_DRV_2 PB pulldown for input or PB driving capability for output byte 0 16 8 R32_PB_PIN RO, GPIO PB input 0xC4 32 read-only n 0x0 0xFFFFFFFF R8_PB_PIN_0 GPIO PB input byte 0 0 8 R8_PB_PIN_1 GPIO PB input byte 1 8 8 R8_PB_PIN_2 GPIO PB input byte 2 16 8 R32_PB_PU RW, GPIO PB pullup resistance enable 0xD0 32 read-write n 0x0 0xFFFFFFFF R8_PB_PU_0 GPIO PB pullup resistance enable byte 0 0 8 R8_PB_PU_1 GPIO PB pullup resistance enable byte 1 8 8 R8_PB_PU_2 GPIO PB pullup resistance enable byte 2 16 8 R32_RTC_CNT_DAY RO, RTC count based one day, only low 14 bit 0x3C 32 read-only n 0x0 0xFFFFFFFF R32_RTC_CNT_DAY RWA,RTC count based one day 0 14 R32_RTC_TRIG RWA, RTC trigger value, SAM 0x34 32 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF R32_RTC_TRIG RWA, RTC trigger value 0 32 R8_ADC_AUTO_CYCLE RO, ADC interrupt flag 0x63 8 write-read n 0x0 0xFFFFFFFF R8_ADC_AUTO_CYCLE auto ADC cycle value, unit is 16 Fsys 0 8 R8_ADC_CFG RW, ADC configure 0x59 8 read-write n 0xA0 0xFFFFFFFF RB_ADC_BUF_EN RW, ADC input buffer enable 1 1 RB_ADC_CLK_DIV RW, select ADC clock frequency: 00=3.2MHz, 01=2.67MHz, 10=5.33MHz, 11=4MHz 6 2 RB_ADC_DIFF_EN RW, ADC input channel mode: 0=single-end, 1=differnetial 2 1 RB_ADC_OFS_TEST RW, enable ADC offset test mode: 0=normal mode, 1=short port4 to test offset 3 1 RB_ADC_PGA_GAIN RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB 4 2 RB_ADC_POWER_ON RW, ADC power control: 0=power down, 1=power on 0 1 R8_ADC_CHANNEL RW, ADC input channel selection 0x58 8 read-write n 0xF 0xFFFFFFFF RB_ADC_CH_INX RW, ADC input channel index 0 4 R8_ADC_CONVERT RW, ADC convert control 0x5A 8 read-write n 0x0 0xFFFFFFFF RB_ADC_EOC_X RO, end of ADC conversion flag 7 1 read-only RB_ADC_START RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear 0 1 read-write R8_ADC_CTRL_DMA RW, ADC DMA control 0x61 8 write-read n 0x0 0xFFFFFFFF RB_ADC_AUTO_EN RW, enable auto continuing ADC for DMA 7 1 RB_ADC_DMA_ENABLE RW, ADC DMA enable 0 1 RB_ADC_DMA_LOOP RW, ADC DMA address loop enable 2 1 RB_ADC_IE_DMA_END RW, enable interrupt for ADC DMA completion 3 1 RB_ADC_IE_EOC RW, enable interrupt for end of ADC conversion 4 1 R8_ADC_DMA_IF RO, ADC interrupt flag register 0x5E 8 read-only n 0x0 0xFFFFFFFF RB_ADC_IF_EOC RW, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, write R8_ADC_CONVERT to clear flag 7 1 R8_ADC_DMA_IF RO, ADC interrupt flag 0x62 8 write-read n 0x0 0xFFFFFFFF RB_ADC_IF_DMA_END interrupt flag for ADC DMA completion 3 1 RB_ADC_IF_END_ADC interrupt flag for end of ADC conversion 4 1 R8_ADC_INT_FLAG RO, ADC interrupt flag register 0x5E 8 read-only n 0x0 0xFFFFFFFF RB_ADC_IF_EOC RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, write R8_ADC_CONVERT to clear flag 7 1 R8_AUX_POWER_ADJ RWA, aux power adjust control, SAM 0x22 8 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_ULPLDO_ADJ RWA, Ultra-Low-Power LDO voltage adjust 0 3 read-write R8_BAT_DET_CFG RWA, battery voltage detector configuration, SAM 0x25 8 Read or Write under safe Accessing mode n 0x1 0xFFFFFFFF RB_BAT_LOW_VTH RWA, select threshold voltage of battery voltage low 0 2 R8_BAT_DET_CTRL RWA, battery voltage detector control, SAM 0x24 8 Read / Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_BAT_DET_EN/RB_BAT_LOW_VTHX RWA, battery voltage detector enable/select monitor threshold voltage 0 1 RB_BAT_LOWER_IE RWA, interrupt enable for battery lower voltage 2 1 RB_BAT_LOW_IE RWA, interrupt enable for battery low voltage 3 1 RB_BAT_MON_EN RWA, battery voltage monitor enable under sleep mode 1 1 R8_BAT_STATUS RO, battery status 0x26 8 read-only n 0x0 0xFFFFFFFF RB_BAT_STAT_LOW RO, battery low voltage status, high action 1 1 RB_BAT_STAT_LOWER RO, battery lower voltage status, high action 0 1 R8_CHIP_ID RF, chip ID register, always is ID_CH57* 0x41 8 -Read only for Fixed value n 0x73 0xFFFFFFFF R8_CHIP_ID RF,chip ID register 0 8 R8_CK32K_CONFIG RWA, 32KHz oscillator configure 0x2F 8 Read or Write under safe Accessing mode n 0x2 0xFFFFFFFF RB_32K_CLK_PIN RO, 32KHz oscillator clock pin status 7 1 read-only RB_CLK_INT32K_PON RWA, internal 32KHz oscillator power on 1 1 read-write RB_CLK_OSC32K_XT RWA, 32KHz oscillator source selection: 0=RC, 1=XT 2 1 read-write RB_CLK_XT32K_PON RWA, external 32KHz oscillator power on 0 1 read-write R8_GLOB_CFG_INFO RO, global configuration information and status 0x45 8 read-only n 0xE 0xFFFFFFFF RB_BOOT_LOADER RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status 5 1 RB_CFG_BOOT_EN RO, boot-loader enable status 3 1 RB_CFG_DEBUG_EN RO, debug enable status 4 1 RB_CFG_RESET_EN RO, manual reset input enable status 2 1 RB_CFG_ROM_READ RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer 0 1 R8_GLOB_RESET_KEEP RW, value keeper during global reset 0x47 8 read-write n 0x0 0xFFFFFFFF R8_GLOB_RESET_KEEP RW, value keeper during global reset 0 8 R8_HFCK_PWR_CTRL RWA, high frequency clock module power control, SAM 0xA 8 read-write n 0x4 0xFFFFFFFF RB_CLK_PLL_PON RWA, PLL power control: 0=power down, 1-power on 4 1 RB_CLK_XT32M_PON RWA, external 32MHz oscillator power control: 0=power down, 1-power on 2 1 R8_OSC_CAL_CTRL RWA, oscillator frequency calibration control, SAM 0x52 8 Read or Write under safe Accessing mode n 0x2 0xFFFFFFFF RB_OSC_CNT_EN RWA, calibration counter enable 0 1 read-write RB_OSC_CNT_HALT RO, calibration counter halt status: 0=counting, 1=halt for reading count value 1 1 read-only R8_PLL_CONFIG RWA, PLL configuration control, SAM 0x4B 8 Read or Write under safe Accessing mode n 0x4A 0xFFFFFFFF RB_PLL_CFG_DAT RWA, PLL configure data 0 7 read-write R8_RESET_STATUS/R8_GLOB_ROM_CFG RWA, reset status, SAM or flash ROM configuration 0x4 8 -Read only for Fixed value n 0x1 0xFFFFFFFF RB_RESET_FLAG RO, recent reset flag 0 3 read-only RB_ROM_CODE_OFS RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x008000 4 1 read-write RB_ROM_CODE_WE RWA, enable flash ROM code area being erase or write 7 1 read-write RB_ROM_CTRL_EN RWA, enable flash ROM control interface enable 5 1 read-write RB_ROM_DATA_WE RWA,enable flash ROM data and code area being erase/write 6 1 read-write R8_RST_WDOG_CTRL RWA, reset and watch-dog control, SAM 0x46 8 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_SOFTWARE_RESET WA or WZ, global software reset, high action, auto clear 0 1 RB_WDOG_INT_EN RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable 2 1 RB_WDOG_INT_FLAG RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event) 4 1 RB_WDOG_RST_EN RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow 1 1 R8_RTC_FLAG_CTRL RW, RTC flag and clear control 0x30 8 read-write n 0x30 0xFFFFFFFF RB_RTC_TMR_CLR RW, set 1 to clear RTC timer action flag, auto clear 4 1 read-write RB_RTC_TMR_FLAG RO, RTC timer action flag 6 1 read-only RB_RTC_TRIG_CLR RW, set 1 to clear RTC trigger action flag, auto clear 5 1 read-write RB_RTC_TRIG_FLAG RO, RTC trigger action flag 7 1 read-only R8_RTC_MODE_CTRL RWA, RTC mode control, SAM 0x31 8 Read or Write under safe Accessing mode n 0x2 0xFFFFFFFF RB_RTC_IGNORE_B0 RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0 3 1 RB_RTC_LOAD_HI RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded 7 1 RB_RTC_LOAD_LO RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded 6 1 RB_RTC_TMR_EN RWA, RTC timer mode enable 4 1 RB_RTC_TMR_MODE RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S 0 3 RB_RTC_TRIG_EN RWA, RTC trigger mode enable 5 1 R8_SAFE_ACCESS_ID RF, safe accessing ID register, always 0x04 0x42 8 -Read only for Fixed value n 0x4 0xFFFFFFFF R8_SAFE_ACCESS_ID RF,safe accessing ID register 0 8 R8_SAFE_ACCESS_SIG WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode 0x40 8 read/write n 0x0 0xFFFFFFFF R8_SAFE_ACCESS_SIG WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode 0 8 RB_SAFE_ACC_ACT RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled 3 1 RB_SAFE_ACC_MODE RO, current safe accessing mode: 11=safe unlocked (SAM), other=locked (00..01..10..11) 0 2 RB_SAFE_ACC_TIMER RO, safe accessing timer bit mask (16*clock number) 4 3 R8_SLP_CLK_OFF0 RWA, sleep clock off control byte 0, SAM 0xC 8 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_SLP_CLK_TMR0 RWA, close TMR0 clock 0 1 RB_SLP_CLK_TMR1 RWA, close TMR1 clock 1 1 RB_SLP_CLK_TMR2 RWA, close TMR2 clock 2 1 RB_SLP_CLK_TMR3 RWA, close TMR3 clock 3 1 RB_SLP_CLK_UART0 RWA, close UART0 clock 4 1 RB_SLP_CLK_UART1 RWA, close UART1 clock 5 1 RB_SLP_CLK_UART2 RWA, close UART2 clock 6 1 RB_SLP_CLK_UART3 RWA, close UART3 clock 7 1 R8_SLP_CLK_OFF1 RWA, sleep clock off control byte 1, SAM 0xD 8 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_SLP_CLK_BLE RWA, close BLE clock 7 1 RB_SLP_CLK_PWMX RWA, close PWMx clock 2 1 RB_SLP_CLK_SPI0 RWA, close SPI0 clock 0 1 RB_SLP_CLK_USB RWA, close USB clock 4 1 R8_SLP_POWER_CTRL RWA, peripherals power down control, SAM 0xF 8 Read or Write under safe Accessing mode n 0x0 0xFFFFFFFF RB_RAM_RET_LV RWA, SRAM retention voltage selection 6 1 RB_SLP_CLK_RAM2K RWA, close retention 2KB SRAM clock 5 1 RB_SLP_CLK_RAMX RWA, close main SRAM clock 4 1 R8_SLP_WAKE_CTRL RWA, wake control, SAM 0xE 8 Read or Write under safe Accessing mode n 0x20 0xFFFFFFFF RB_SLP_BAT_WAKE RWA, enable BAT waking 5 1 RB_SLP_GPIO_WAKE RWA, enable GPIO waking 4 1 RB_SLP_RTC_WAKE RWA, enable RTC waking 3 1 RB_SLP_USB_WAKE RWA, enable USB waking 0 1 RB_WAKE_DELAY RWA, wakeup delay 7 1 RB_WAKE_EV_MODE RWA, event wakeup mode 6 1 R8_TEM_SENSOR RW, temperature sensor control 0x5B 8 read-write n 0x0 0xFFFFFFFF RB_TEM_SEN_PWR_ON RW, temperature sensor power control: 0=power down, 1=power on 7 1 R8_TKEY_CFG RW, Touchkey configure 0x57 8 read-write n 0x0 0xFFFFFFFF RB_TKEY_CURRENT RW, Touchkey charge current selection 1 1 RB_TKEY_PGA_ADJ RW, ADC input PGA speed selection 3 1 RB_TKEY_PWR_ON RW, Touchkey power on 0 1 R8_TKEY_CONVERT RW, Touchkey convert start control 0x56 8 read-write n 0x0 0xFFFFFFFF RB_TKEY_START RW, Touchkey convert start control 0 1 R8_TKEY_COUNT RW, Touchkey charge and discharge count 0x54 8 read-write n 0x0 0xFFFFFFFF RB_TKEY_CHARG_CNT RW, Touchkey charge count 0 5 RB_TKEY_DISCH_CNT RW, Touchkey discharge count 5 3 R8_WDOG_COUNT RW, watch-dog count, count by clock frequency Fsys/131072 0x43 8 read-write n 0x0 0xFFFFFFFF R8_WDOG_COUNT RF,watch-dog count, count by clock frequency Fsys/131072 0 8 R8_XT32K_TUNE RWA, external 32KHz oscillator tune control, SAM 0x2E 8 Read or Write under safe Accessing mode n 0xC3 0xFFFFFFFF RB_XT32K_C_LOAD RWA, external 32KHz oscillator load capacitor tune: Cap = RB_XT32K_C_LOAD + 12pF 4 4 RB_XT32K_I_TUNE RWA, external 32KHz oscillator current tune: 00=75% current, 01=standard current, 10=150% current, 11=200% current 0 2 R8_XT32M_TUNE RWA, external 32MHz oscillator tune control, SAM 0x4E 8 Read or Write under safe Accessing mode n 0x31 0xFFFFFFFF RB_XT32M_C_LOAD RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF 4 3 read-write RB_XT32M_I_BIAS RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current 0 2 read-write Systick Systick register Systick 0xE000F000 0x0 0x100 registers n R32_STK_CMPHR Systick compare high register 0x10 32 read-write n 0x0 0xFFFFFFFF CMPH RW,CMPH 0 32 R32_STK_CMPLR Systick compare low register 0xC 32 read-write n 0x0 0xFFFFFFFF CMPL RW,CMPL 0 32 R32_STK_CNTFG Systick counter flag 0x14 32 read-write n 0x0 0xFFFFFFFF CNTIF RW,Systick counter clear zero flag 1 1 SWIE RW0,System soft interrupt enable 0 1 R32_STK_CNTH Systick counter high register 0x8 32 read-write n 0x0 0xFFFFFFFF CNTH RW,CNTH 0 32 R32_STK_CNTL Systick counter low register 0x4 32 read-write n 0x0 0xFFFFFFFF CNTL RW,CNTL 0 32 R32_STK_CTLR STK_CTLR Systick counter control register 0x0 32 n 0x0 0xFFFFFFFF STCLK System counter clock Source selection 2 1 read-write STE Systick counter enable 0 1 read-write STIE Systick counter interrupt enable 1 1 read-write STRELOAD System counter reload control 8 1 read-write TMR0 Timer0 register TMR 0x40002000 0x0 0x400 registers n TMR0 TMR0_IRQHandler 0 R32_TMR0_CNT_END RW, TMR0 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR0_CNT_END RW1,TMR0 end count value 0 32 R32_TMR0_COUNT RO, TMR0 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR0_COUNT RW1,TMR0 current count 0 32 R32_TMR0_FIFO RO/WO, TMR0 FIFO register, only low 26 bit 0x10 32 read-only n 0x0 0xFFFFFFFF R32_TMR0_FIFO RW1,TMR0 FIFO register 0 32 R8_TMR0_CTRL_MOD RW, TMR0 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR RW, force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN RW, timer count enable 2 1 RB_TMR_MODE_IN RW, timer in mode: 0=timer/PWM, 1=capture/count 0 1 RB_TMR_OUT_EN RW, timer output enable 3 1 RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count 4 1 RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise 6 2 R8_TMR0_FIFO_COUNT RO, TMR0 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR0_FIFO_COUNT RW1,TMR0 FIFO count status 0 8 R8_TMR0_INTER_EN RW, TMR0 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END RW, enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT RW, enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END RW, enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3) 2 1 RB_TMR_IE_FIFO_OV RW, enable interrupt for timer FIFO overflow 4 1 R8_TMR0_INT_FLAG RW1, TMR0 interrupt flag 0x6 8 Read / Write 1 to Clear n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END RW1, interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT RW1, interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END RW1, interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3 2 1 RB_TMR_IF_FIFO_OV RW1, interrupt flag for timer FIFO overflow 4 1 TMR1 Timer1 register TMR 0x40002400 0x0 0x400 registers n TMR1 TMR1_IRQHandler 8 R16_TMR1_DMA_BEG RW, TMR1 DMA begin address 0x18 16 read-write n 0x0 0xFFFFFFFF R16_TMR1_DMA_BEG RW1,TMR1 FIFO register 0 16 R16_TMR1_DMA_END RW, TMR1 DMA end address 0x1C 16 read-write n 0x0 0xFFFFFFFF R16_TMR1_DMA_END RW1,TMR1 FIFO register 0 16 R16_TMR1_DMA_NOW RO, TMR1 DMA current address 0x14 16 read-only n 0x0 0xFFFFFFFF R16_TMR1_DMA_NOW RW1,TMR1 FIFO register 0 16 R32_TMR1_CNT_END RW, TMR1 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR1_CNT_END RW1,TMR1 end count value, 0 32 R32_TMR1_COUNT RO, TMR1 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR1_COUNT RW1,TMR1 current count 0 32 R32_TMR1_FIFO RO, TMR1 FIFO register, only low 26 bit 0x10 32 read-only n 0x0 0xFFFFFFFF R32_TMR1_FIFO RW1,TMR1 FIFO register 0 32 R8_TMR1_CTRL_DMA RW, TMR1 DMA control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_TMR_DMA_ENABLE RW, timer1/2 DMA enable 0 1 RB_TMR_DMA_LOOP RW, timer1/2 DMA address loop enable 2 1 R8_TMR1_CTRL_MOD RW, TMR1 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR RW, force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN RW, timer count enable 2 1 RB_TMR_MODE_IN RW, timer in mode: 0=timer/PWM, 1=capture/count 0 1 RB_TMR_OUT_EN RW, timer output enable 3 1 RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count 4 1 RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise 6 2 R8_TMR1_FIFO_COUNT RO, TMR1 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR1_FIFO_COUNT RW1, TMR1 FIFO count status 0 32 R8_TMR1_INTER_EN RW, TMR1 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END RW, enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT RW, enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END RW, enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3) 2 1 RB_TMR_IE_FIFO_OV RW, enable interrupt for timer FIFO overflow 4 1 R8_TMR1_INT_FLAG RW1, TMR1 interrupt flag 0x6 8 Read or Write 1 to Clear n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END RW1, interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT RW1, interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END RW1, interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3 2 1 RB_TMR_IF_FIFO_OV RW1, interrupt flag for timer FIFO overflow 4 1 TMR2 Timer2 register TMR 0x40002800 0x0 0x400 registers n TMR2 TMR2_IRQHandler 9 R16_TMR2_DMA_BEG RW, TMR2 DMA begin address 0x18 16 read-write n 0x0 0xFFFFFFFF R16_TMR2_DMA_BEG RW, TMR2 DMA begin address 0 32 R16_TMR2_DMA_END RW, TMR2 DMA end address 0x1C 16 read-write n 0x0 0xFFFFFFFF R16_TMR2_DMA_END RW, TMR2 DMA end address 0 32 R16_TMR2_DMA_NOW RO, TMR2 DMA current address 0x14 16 read-only n 0x0 0xFFFFFFFF R32_TMR2_FIFO RW, TMR2 current count 0 32 R32_TMR2_CNT_END RW, TMR2 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR2_COUNT RW, TMR2 current count 0 32 R32_TMR2_COUNT RO, TMR2 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR2_COUNT RW, TMR2 current count 0 32 R32_TMR2_COUNT RO, TMR2 FIFO register, only low 26 bit 0x10 32 write-only or read-only n 0x0 0xFFFFFFFF R32_TMR2_FIFO RW, TMR2 current count 0 32 R8_TMR2_CTRL_DMA RW, TMR2 DMA control 0x1 8 read-write n 0x0 0xFFFFFFFF RB_TMR_DMA_ENABLE RW, timer1_2 DMA enable 0 1 RB_TMR_DMA_LOOP RW, timer1_2 DMA address loop enable 2 1 R8_TMR2_CTRL_MOD RW, TMR2 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR RW, force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN RW, timer count enable 2 1 RB_TMR_MODE_IN RW, timer in mode: 0=timer_PWM, 1=capture_count 0 1 RB_TMR_OUT_EN RW, timer output enable 3 1 RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count 4 1 RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise 6 2 R8_TMR2_FIFO_COUNT RO, TMR2 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR2_FIFO_COUNT RW, TMR2 FIFO count status 0 8 R8_TMR2_INTER_EN RW, TMR2 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END RW, enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT RW, enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END RW, enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3) 2 1 RB_TMR_IE_FIFO_OV RW, enable interrupt for timer FIFO overflow 4 1 R8_TMR2_INT_FLAG RW1, TMR2 interrupt flag 0x6 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END RW1, interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT RW1, interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END RW1, interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3 2 1 RB_TMR_IF_FIFO_OV RW1, interrupt flag for timer FIFO overflow 4 1 TMR3 Timer3 register TMR 0x40002C00 0x0 0x400 registers n TMR3 TMR3_IRQHandler 16 R32_TMR3_CNT_END RW, TMR3 end count value, only low 26 bit 0xC 32 read-write n 0x0 0xFFFFFFFF R32_TMR3_CNT_END RW, TMR3 end count value, only low 26 bit 0 32 R32_TMR3_COUNT RO, TMR3 current count 0x8 32 read-only n 0x0 0xFFFFFFFF R32_TMR3_COUNT R0, TMR3 current count 0 32 R32_TMR3_FIFO RO/WO, TMR3 FIFO register, only low 26 bit 0x10 32 read-only or write-only n 0x0 0xFFFFFFFF R32_TMR3_FIFO RO/WO, TMR3 FIFO register, only low 26 bit 0 32 R8_TMR3_CTRL_MOD RW, TMR3 mode control 0x0 8 read-write n 0x2 0xFFFFFFFF RB_TMR_ALL_CLEAR RW, force clear timer FIFO and count 1 1 RB_TMR_COUNT_EN RW, timer count enable 2 1 RB_TMR_MODE_IN RW, timer in mode: 0=timer/PWM, 1=capture/count 0 1 RB_TMR_OUT_EN RW, timer output enable 3 1 RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count 4 1 RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise 6 2 R8_TMR3_FIFO_COUNT RO, TMR3 FIFO count status 0x7 8 read-only n 0x0 0xFFFFFFFF R8_TMR3_FIFO_COUNT R0, TMR3 FIFO count status 0 8 R8_TMR3_INTER_EN RW, TMR3 interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_TMR_IE_CYC_END RW, enable interrupt for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IE_DATA_ACT RW, enable interrupt for timer capture input action or PWM trigger 1 1 RB_TMR_IE_DMA_END RW, enable interrupt for timer1/2 DMA completion 3 1 RB_TMR_IE_FIFO_HF RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3) 2 1 RB_TMR_IE_FIFO_OV RW, enable interrupt for timer FIFO overflow 4 1 R8_TMR3_INT_FLAG RW1, TMR3 interrupt flag 0x6 8 Read or Write 1 to Clear n 0x0 0xFFFFFFFF RB_TMR_IF_CYC_END RW1, interrupt flag for timer capture count timeout or PWM cycle end 0 1 RB_TMR_IF_DATA_ACT RW1, interrupt flag for timer capture input action or PWM trigger 1 1 RB_TMR_IF_DMA_END RW1, interrupt flag for timer1/2 DMA completion 3 1 RB_TMR_IF_FIFO_HF RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3 2 1 RB_TMR_IF_FIFO_OV RW1, interrupt flag for timer FIFO overflow 4 1 UART0 UART0 register UART 0x40003000 0x0 0x400 registers n UART0 UART0_IRQHandler 10 R16_UART0_DL RW, UART0 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART0_DL RW, UART0 divisor latch 0 16 R8_UART0_ADR RW, UART0 slave address: 0xFF=disable, other=enable 0xF 8 read-write n 0xFF 0xFFFFFFFF R8_UART0_ADR RW,UART0 slave address: 0xFF=disable, other=enable 0 8 R8_UART0_DIV RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART0_DIV RW,UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 0 8 R8_UART0_FCR RW, UART0 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN RW, UART FIFO enable 0 1 RB_FCR_FIFO_TRIG RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes 6 2 RB_FCR_RX_FIFO_CLR WZ, clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR WZ, clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART0_IER RW, UART0 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_DTR_EN RW, UART0 DTR/TNOW output pin enable 4 1 RB_IER_LINE_STAT RW, UART interrupt enable for receiver line status 2 1 RB_IER_MODEM_CHG RW, UART0 interrupt enable for modem status change 3 1 RB_IER_RECV_RDY RW, UART interrupt enable for receiver data ready 0 1 RB_IER_RESET WZ, UART software reset control, high action, auto clear 7 1 RB_IER_RTS_EN RW, UART0 RTS output pin enable 5 1 RB_IER_THR_EMPTY RW, UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN RW, UART TXD pin enable 6 1 R8_UART0_IIR RO, UART0 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID RO, UART FIFO enabled flag 6 2 RB_IIR_INT_MASK RO, UART interrupt flag bit mask 0 4 RB_IIR_NO_INT RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt 0 1 R8_UART0_LCR RW, UART0 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN RW, UART break control enable 6 1 RB_LCR_GP_BIT/RB_LCR_DLAB RW, UART general purpose bit RW, UART reserved bit 7 1 RB_LCR_PAR_EN RW, UART parity enable 3 1 RB_LCR_PAR_MOD RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space 4 2 RB_LCR_STOP_BIT RW, UART stop bit length: 0-1bit, 1-2bit 2 1 RB_LCR_WORD_SZ RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit 0 2 R8_UART0_LSR RO, UART0 line status 0x5 8 read-only n 0x60 0xFFFFFFFF RB_LSR_BREAK_ERR RZ, UART receiver break error 4 1 RB_LSR_DATA_RDY RO, UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO RO, indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR RZ, UART receiver frame error 3 1 RB_LSR_OVER_ERR RZ, UART receiver overrun error 1 1 RB_LSR_PAR_ERR RZ, UART receiver parity error 2 1 RB_LSR_TX_ALL_EMP RO, UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP RO, UART transmitter fifo empty status 5 1 R8_UART0_MCR RW, UART0 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_AU_FLOW_EN RW, UART0 enable autoflow control 5 1 RB_MCR_DTR RW, UART0 control DTR 0 1 RB_MCR_HALF RW, UART0 enable half-duplex 7 1 RB_MCR_LOOP RW, UART0 enable local loop back 4 1 RB_MCR_OUT1 RW, UART0 control OUT1 2 1 RB_MCR_OUT2/RB_MCR_INT_OE RW, UART control OUT2/ UART interrupt output enable 3 1 RB_MCR_RTS RW, UART0 control RTS 1 1 RB_MCR_TNOW RW, UART0 enable TNOW output on DTR pin 6 1 R8_UART0_MSR RO, UART0 modem status 0x6 8 read-only n 0x0 0xFFFFFFFF RB_MSR_CTS RO, UART0 CTS action status 4 1 RB_MSR_CTS_CHG RZ, UART0 CTS changed status, high action 0 1 read-only RB_MSR_DCD RO, UART0 DCD action status 7 1 RB_MSR_DCD_CHG RZ, UART0 DCD changed status, high action 3 1 RB_MSR_DSR RO, UART0 DSR action statusv 5 1 RB_MSR_DSR_CHG RZ, UART0 DSR changed status, high action 1 1 read-only RB_MSR_RI RO, UART0 RI action status 6 1 RB_MSR_RI_CHG RZ, UART0 RI changed status, high action 2 1 R8_UART0_RBR RO, UART0 receiver buffer, receiving byte 0x8 8 read-only n 0x0 0xFFFFFFFF R8_UART0_RBR RO, UART0 receiver buffer, receiving byte 0 8 R8_UART0_RFC RO, UART0 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART0_RFC RO, UART0 receiver FIFO count 0 8 R8_UART0_TFC RO, UART0 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART0_TFC RO, UART0 transmitter FIFO count 0 8 R8_UART0_THR WO, UART0 transmitter holding, transmittal byte 0x8 8 write-only n 0x0 0xFFFFFFFF R8_UART0_THR RO, UART0 transmitter holding, transmittal byte 0 8 UART1 UART1 register UART 0x40003400 0x0 0x400 registers n UART1 UART1_IRQHandler 11 R16_UART1_DL RW, UART1 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART1_DL RW, UART1 divisor latch 0 16 R8_UART1_DIV RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 128 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART1_DIV RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 128 0 8 R8_UART1_FCR RW, UART1 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN RW, UART FIFO enable 0 1 RB_FCR_FIFO_TRIG RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes 6 2 RB_FCR_RX_FIFO_CLR WZ, clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR WZ, clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART1_IER RW, UART1 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT RW, UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY RW, UART interrupt enable for receiver data ready 0 1 RB_IER_RESET WZ, UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY RW, UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN RW, UART TXD pin enable 6 1 R8_UART1_IIR RO, UART1 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID RO, UART FIFO enabled flag 7 1 RB_IIR_INT_MASK RO, UART interrupt flag bit mask 0 4 RB_IIR_NO_INT RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt 0 1 R8_UART1_LCR RW, UART1 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN RW, UART break control enable 6 1 RB_LCR_GP_BIT/RB_LCR_DLAB RW, UART general purpose bit RW, UART reserved bit 7 1 RB_LCR_PAR_EN RW, UART parity enable 3 1 RB_LCR_PAR_MOD RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space 4 2 RB_LCR_STOP_BIT RW, UART stop bit length: 0-1bit, 1-2bit 2 1 RB_LCR_WORD_SZ RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit 0 2 R8_UART1_LSR RO, UART1 line status 0x5 8 read-only n 0x60 0xFFFFFFFF RB_LSR_BREAK_ERR RZ, UART receiver break error 4 1 RB_LSR_DATA_RDY RO, UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO RO, indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR RZ, UART receiver frame error 3 1 RB_LSR_OVER_ERR RZ, UART receiver overrun error 1 1 RB_LSR_PAR_ERR RZ, UART receiver parity error 2 1 RB_LSR_TX_ALL_EMP RO, UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP RO, UART transmitter fifo empty status 5 1 R8_UART1_MCR RW, UART1 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_OUT2/RB_MCR_INT_OE RW, UART control OUT2/UART interrupt output enable 3 1 R8_UART1_RBR RO, UART1 receiver buffer, receiving byte 0x8 8 read-only n 0x0 0xFFFFFFFF R8_UART1_RBR RO, UART1 receiver buffer, receiving byte 0 8 R8_UART1_RFC RO, UART1 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART1_RFC RO, UART1 receiver FIFO count 0 8 R8_UART1_TFC RO, UART1 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART1_TFC RO, UART1 receiver FIFO count 0 8 R8_UART1_THR WO, UART1 transmitter holding, transmittal byte 0x8 8 write-only n 0x0 0xFFFFFFFF R8_UART1_RBR WO, UART1 transmitter holding, transmittal byte 0 8 UART2 UART2 register UART 0x40003800 0x0 0x400 registers n UART2 UART1_IRQHandler 17 R16_UART2_DL RW, UART2 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART2_DL RW, UART2 divisor latch 0 16 R8_UART2_DIV RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 128 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART2_DIV RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 128 0 8 R8_UART2_FCR RW, UART2 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN RW, UART FIFO enable 0 1 RB_FCR_FIFO_TRIG RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes 6 2 RB_FCR_RX_FIFO_CLR WZ, clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR WZ, clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART2_IER RW, UART2 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT RW, UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY RW, UART interrupt enable for receiver data ready 0 1 RB_IER_RESET WZ, UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY RW, UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN RW, UART TXD pin enable 6 1 R8_UART2_IIR RO, UART2 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID RO, UART FIFO enabled flag 7 1 RB_IIR_INT_MASK RO, UART interrupt flag bit mask 0 4 RB_IIR_NO_INT RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt 0 1 R8_UART2_LCR RW, UART2 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN RW, UART break control enable 6 1 RB_LCR_GP_BIT/RB_LCR_DLAB RW, UART general purpose bit RW, UART reserved bit 7 1 RB_LCR_PAR_EN RW, UART parity enable 3 1 RB_LCR_PAR_MOD RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space 4 2 RB_LCR_STOP_BIT RW, UART stop bit length: 0-1bit, 1-2bit 2 1 RB_LCR_WORD_SZ RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit 0 2 R8_UART2_LSR RO, UART2 line status 0x5 8 read-only n 0x60 0xFFFFFFFF RB_LSR_BREAK_ERR RZ, UART receiver break error 4 1 RB_LSR_DATA_RDY RO, UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO RO, indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR RZ, UART receiver frame error 3 1 RB_LSR_OVER_ERR RZ, UART receiver overrun error 1 1 RB_LSR_PAR_ERR RZ, UART receiver parity error 2 1 RB_LSR_TX_ALL_EMP RO, UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP RO, UART transmitter fifo empty status 5 1 R8_UART2_MCR RW, UART2 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_OUT2/RB_MCR_INT_OE RW, UART control OUT2 UART interrupt output enable 3 1 R8_UART2_RBR RO, UART2 receiver buffer, receiving byte 0x8 8 read-only n 0x0 0xFFFFFFFF R8_UART2_RBR RO, UART2 receiver buffer, receiving byte 0 8 R8_UART2_RFC RO, UART2 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART2_RFC RO, UART2 receiver FIFO count 0 8 R8_UART2_TFC RO, UART2 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART2_TFC RO, UART2 transmitter FIFO count 0 8 R8_UART2_THR WO, UART2 transmitter holding, transmittal byte 0x8 8 write-only n 0x0 0xFFFFFFFF R8_UART2_THR WO, UART2 transmitter holding, transmittal byte 0 8 UART3 UART3 register UART 0x40003C00 0x0 0x400 registers n UART3 UART3_IRQHandler 18 R16_UART3_DL RW, UART3 divisor latch 0xC 16 read-write n 0x0 0xFFFFFFFF R16_UART3_DL RW, UART3 divisor latch 0 16 R8_UART3_DIV RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 128 0xE 8 read-write n 0x0 0xFFFFFFFF R8_UART3_DIV RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 128 0 8 R8_UART3_FCR RW, UART3 FIFO control 0x2 8 read-write n 0x0 0xFFFFFFFF RB_FCR_FIFO_EN RW, UART FIFO enable 0 1 RB_FCR_FIFO_TRIG RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes 6 2 RB_FCR_RX_FIFO_CLR WZ, clear UART receiver FIFO, high action, auto clear 1 1 RB_FCR_TX_FIFO_CLR WZ, clear UART transmitter FIFO, high action, auto clear 2 1 R8_UART3_IER RW, UART3 interrupt enable 0x1 8 read-write n 0x0 0xFFFFFFFF RB_IER_LINE_STAT RW, UART interrupt enable for receiver line status 2 1 RB_IER_RECV_RDY RW, UART interrupt enable for receiver data ready 0 1 RB_IER_RESET WZ, UART software reset control, high action, auto clear 7 1 RB_IER_THR_EMPTY RW, UART interrupt enable for THR empty 1 1 RB_IER_TXD_EN RW, UART TXD pin enable 6 1 R8_UART3_IIR RO, UART3 interrupt identification 0x4 8 read-only n 0x1 0xFFFFFFFF RB_IIR_FIFO_ID RO, UART FIFO enabled flag 7 1 RB_IIR_INT_MASK RO, UART interrupt flag bit mask 1 3 RB_IIR_NO_INT RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt 0 1 R8_UART3_LCR RW, UART3 line control 0x3 8 read-write n 0x0 0xFFFFFFFF RB_LCR_BREAK_EN RW, UART break control enable 6 1 RB_LCR_GP_BIT/RB_LCR_DLAB RW, UART general purpose bit RW, UART reserved bit 7 1 RB_LCR_PAR_EN RW, UART parity enable 3 1 RB_LCR_PAR_MOD RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space 4 2 RB_LCR_STOP_BIT RW, UART stop bit length: 0-1bit, 1-2bit 2 1 RB_LCR_WORD_SZ RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit 0 2 R8_UART3_LSR RO, UART3 line status 0x5 8 read-only n 0x60 0xFFFFFFFF RB_LSR_BREAK_ERR RZ, UART receiver break error 4 1 RB_LSR_DATA_RDY RO, UART receiver fifo data ready status 0 1 RB_LSR_ERR_RX_FIFO RO, indicate error in UART receiver fifo 7 1 RB_LSR_FRAME_ERR RZ, UART receiver frame error 3 1 RB_LSR_OVER_ERR RZ, UART receiver overrun error 1 1 RB_LSR_PAR_ERR RZ, UART receiver parity error 2 1 RB_LSR_TX_ALL_EMP RO, UART transmitter all empty status 6 1 RB_LSR_TX_FIFO_EMP RO, UART transmitter fifo empty status 5 1 R8_UART3_MCR RW, UART3 modem control 0x0 8 read-write n 0x0 0xFFFFFFFF RB_MCR_OUT2/RB_MCR_INT_OE RW, UART control OUT2 UART interrupt output enable 3 1 R8_UART3_RBR RO, UART3 receiver buffer, receiving byte 0x8 8 read-only n 0x0 0xFFFFFFFF R8_UART3_RBR RO, UART3 receiver buffer, receiving byte 0 8 R8_UART3_RFC RO, UART3 receiver FIFO count 0xA 8 read-only n 0x0 0xFFFFFFFF R8_UART3_RFC RO, UART3 receiver FIFO count 0 8 R8_UART3_TFC RO, UART3 transmitter FIFO count 0xB 8 read-only n 0x0 0xFFFFFFFF R8_UART3_TFC RO, UART3 transmitter FIFO count 0 8 R8_UART3_THR WO, UART3 transmitter holding, transmittal byte 0x8 8 write-only n 0x0 0xFFFFFFFF R8_UART3_THR WO, UART3 transmitter holding, transmittal byte 0 8 USB USB register USB 0x40008000 0x0 0x400 registers n USB USB_IRQHandler 8 R16_UEP0_DMA endpoint 0 DMA buffer address 0x10 16 read-write n 0x0 0xFFFFFFFF R16_UEP0_DMA RW,endpoint 0 DMA buffer address 0 16 R16_UEP1_DMA endpoint 1 DMA buffer address 0x14 16 read-write n 0x0 0xFFFFFFFF R16_UEP1_DMA RW,endpoint 1 DMA buffer address 0 16 R16_UEP2_DMA__R16_UH_RX_DMA endpoint 2 DMA buffer address host rx endpoint buffer high address 0x18 16 read-write n 0x0 0xFFFFFFFF R16_UEP2_DMA RW,endpoint 2 DMA buffer address host rx endpoint buffer high address 0 16 R16_UEP3_DMA__R16_UH_TX_DMA endpoint 3 DMA buffer address host tx endpoint buffer high address 0x1C 16 read-write n 0x0 0xFFFFFFFF R8_UDEV_CTRL__R8_UHOST_CTRL USB device physical prot control 0x1 8 n 0x0 0xFFFFFFFF RB_UD_DM_PIN__RB_UH_DM_PIN ReadOnly: indicate current UDM pin level 4 1 read-only RB_UD_DP_PIN__RB_UH_DP_PIN ReadOnly: indicate current UDP pin level 5 1 read-only RB_UD_GP_BIT__RB_UH_BUS_RESET general purpose bit control USB bus reset: 0=normal, 1=force bus reset 1 1 read-write RB_UD_LOW_SPEED__RB_UH_LOW_SPEED enable USB physical port low speed: 0=full speed, 1=low speed enable USB port low speed: 0=full speed, 1=low speed 2 1 read-write RB_UD_PD_DIS__RB_UH_PD_DIS disable USB UDP-UDM pulldown resistance: 0=enable pulldown, 1=disable 7 1 read-only RB_UD_PORT_EN__RB_UH_PORT_EN enable USB physical port I-O: 0=disable, 1=enable enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached 0 1 read-write R8_UEP0_CTRL endpoint 0 control 0x22 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 2 MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle 4 1 RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 7 1 RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 6 1 R8_UEP0_T_LEN endpoint 0 transmittal length 0x20 8 read-write n 0x0 0xFFFFFFFF R8_UEP0_T_LEN endpoint 0 transmittal length 0 8 R8_UEP1_CTRL__R8_UH_SETUP endpoint 1 control host aux setup 0x26 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 2 MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle 4 1 RB_UEP_R_TOG__RB_UH_PRE_PID_EN expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 RB_UH_PRE_PID_EN USB host PRE PID enable for low speed device via hub 7 1 RB_UEP_T_TOG__RB_UH_SOF_EN prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 USB host automatic SOF enable 6 1 R8_UEP1_T_LEN endpoint 1 transmittal length 0x24 8 read-write n 0x0 0xFFFFFFFF R8_UEP1_T_LEN endpoint 1 transmittal length 0 8 R8_UEP2_3_MOD__R8_UH_EP_MOD endpoint 2_3 mode host endpoint mode 0xD 8 read-write n 0x0 0xFFFFFFFF RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD buffer mode of USB endpoint 2 buffer mode of USB host IN endpoint 0 1 RB_UEP2_RX_EN__RB_UH_EP_RX_EN enable USB endpoint 2 receiving (OUT) enable USB host IN endpoint receiving 3 1 RB_UEP2_TX_EN enable USB endpoint 2 transmittal (IN) 2 1 RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD buffer mode of USB endpoint 3 buffer mode of USB host OUT endpoint 4 1 RB_UEP3_RX_EN enable USB endpoint 3 receiving (OUT) 7 1 RB_UEP3_TX_EN__RB_UH_EP_TX_EN enable USB endpoint 3 transmittal (IN) enable USB host OUT endpoint transmittal 6 1 R8_UEP2_CTRL_R8_UH_RX_CTRL endpoint 2 control host receiver endpoint control 0x2A 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 2 MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 MASK_UH_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 1 RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle 4 1 RB_UEP_R_TOG__RB_UH_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 7 1 RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 6 1 R8_UEP2_T_LEN_R8_UH_EP_PID endpoint 2 transmittal length host endpoint and PID 0x28 8 read-write n 0x0 0xFFFFFFFF MASK_UH_ENDP bit mask of endpoint number for USB host transfer 0 4 MASK_UH_TOKEN bit mask of token PID for USB host transfer 4 4 R8_UEP2_T_LEN endpoint 2 transmittal length 0 8 R8_UEP3_CTRL__R8_UH_TX_CTRL endpoint 3 control host transmittal endpoint control 0x2E 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 2 MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_AUTO_TOG_RB_UH_T_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle 4 1 RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 7 1 RB_UEP_T_TOG_RB_UH_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 6 1 RB_UH_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 R8_UEP3_T_LEN__R8_UH_TX_LEN endpoint 3 transmittal length host transmittal endpoint transmittal length 0x2C 8 read-write n 0x0 0xFFFFFFFF R8_UEP3_T_LEN__R8_UH_TX_LEN endpoint 1 transmittal length 0 8 R8_UEP4_1_MOD endpoint 4/1 mode 0xC 8 read-write n 0x0 0xFFFFFFFF RB_UEP1_BUF_MOD buffer mode of USB endpoint 1 4 1 RB_UEP1_RX_EN enable USB endpoint 1 receiving (OUT) 7 1 RB_UEP1_TX_EN enable USB endpoint 1 transmittal (IN) 6 1 RB_UEP4_RX_EN enable USB endpoint 4 receiving (OUT) 3 1 RB_UEP4_TX_EN enable USB endpoint 4 transmittal (IN) 2 1 R8_UEP4_CTRL endpoint 4 control 0x32 8 read-write n 0x0 0xFFFFFFFF MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) 2 2 MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) 0 2 RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1_2_3: 0=manual toggle, 1=automatic toggle 4 1 RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 7 1 RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 6 1 R8_UEP4_T_LEN endpoint 4 transmittal length 0x30 8 read-write n 0x0 0xFFFFFFFF R8_UEP4_T_LEN endpoint 4transmittal length 0 8 R8_USB_CTRL USB base control 0x0 8 read-write n 0x6 0xFFFFFFFF MASK_UC_SYS_CTRL bit mask of USB system control 4 2 RB_UC_CLR_ALL force clear FIFO and count of USB 1 1 RB_UC_DEV_PU_EN USB device enable and internal pullup resistance enable 5 1 RB_UC_DMA_EN DMA enable and DMA interrupt enable for USB 0 1 RB_UC_HOST_MODE enable USB host mode: 0=device mode, 1=host mode 7 1 RB_UC_INT_BUSY enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 3 1 RB_UC_LOW_SPEED enable USB low speed: 0=12Mbps, 1=1.5Mbps 6 1 RB_UC_RESET_SIE force reset USB SIE, need software clear 2 1 R8_USB_DEV_AD USB device address 0x3 8 read-write n 0x0 0xFFFFFFFF MASK_USB_ADDR bit mask for USB device address 0 7 RB_UDA_GP_BIT general purpose bit 7 1 R8_USB_INT_EN USB interrupt enable 0x2 8 read-write n 0x0 0xFFFFFFFF RB_UIE_BUS_RST__RB_UIE_DETECT enable interrupt for USB bus reset event for USB device mode enable interrupt for USB device detected event for USB host mode 0 1 RB_UIE_DEV_NAK enable interrupt for NAK responded for USB device mode 6 1 RB_UIE_DEV_SOF enable interrupt for SOF received for USB device mode 7 1 RB_UIE_FIFO_OV enable interrupt for FIFO overflow 4 1 RB_UIE_HST_SOF enable interrupt for host SOF timer action for USB host mode 3 1 RB_UIE_SUSPEND enable interrupt for USB suspend or resume event 2 1 RB_UIE_TRANSFER enable interrupt for USB transfer completion 1 1 R8_USB_INT_FG USB interrupt flag 0x6 8 read-write n 0x20 0xFFFFFFFF RB_UIF_BUS_RST__RB_UIF_DETECT RW,bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear 0 1 RB_UIF_FIFO_OV RW,FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 4 1 RB_UIF_HST_SOF RW,host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 3 1 RB_UIF_SUSPEND RW,USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 2 1 RB_UIF_TRANSFER RW,USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 1 1 RB_U_IS_NAK RO, indicate current USB transfer is NAK received 7 1 read-only RB_U_SIE_FREE RO, indicate USB SIE free status 5 1 read-only RB_U_TOG_OK RO, indicate current USB transfer toggle is OK 6 1 read-only R8_USB_INT_ST USB interrupt status 0x7 8 read-only n 0x0 0xFFFFFFFF MASK_UIS_H_RES__MASK_UIS_ENDP RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received RO, bit mask of current transfer endpoint number for USB device mode 0 4 MASK_UIS_TOKEN RO, bit mask of current token PID code received for USB device mode 4 2 RB_UIS_SETUP_ACT RO, indicate current USB transfer is NAK received for USB device mode 7 1 RB_UIS_TOG_OK RO, indicate current USB transfer toggle is OK 6 1 R8_USB_MIS_ST USB miscellaneous status 0x5 8 read-only n 0x200000 0xFFFFFFFF RB_UMS_BUS_RESET RO, indicate USB bus reset status 3 1 RB_UMS_DEV_ATTACH RO, indicate device attached status on USB host 0 1 RB_UMS_DM_LEVEL RO, indicate UDM level saved at device attached to USB host 1 1 RB_UMS_R_FIFO_RDY RO, indicate USB receiving FIFO ready status (not empty) 4 1 RB_UMS_SIE_FREE RO, indicate USB SIE free status 5 1 RB_UMS_SOF_ACT RO, indicate host SOF timer action status for USB host 6 1 RB_UMS_SOF_PRES RO, indicate host SOF timer presage status 7 1 RB_UMS_SUSPEND RO, indicate USB suspend status 2 1 R8_USB_RX_LEN USB receiving length 0x8 8 read-only n 0x0 0xFFFFFFFF R8_USB_RX_LEN RO,USB receiving length 0 8