Zilog, Inc Z32F0642 2026.10.10 ARM 32-bit Cortex-M0 Microcontroller based device. CM0 r1p0 little 2 false 8 32 AD 12-BIT A/D CONVERTER ADC 0x4000B000 0x0 0x100 registers n ADC 25 CCR Clock Control Register 0x8 32 read-write n 0x0 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 CR ADCn Control Register 0x20 32 read-write n 0x0 0xFFFF ASTART ADC conversion start 0 1 read-write ASTOP ADC Stop 7 1 write-only CSCR Current Sequence/Channel Register 0x4 32 read-write n 0x0 0xFF CACH Current Active Channel 0 4 CSEQN CSEQN 4 3 DR0 ADC Data Register 0 0x30 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR1 ADC Data Register 1 0x34 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR2 ADC Data Register 2 0x38 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR3 ADC Data Register 3 0x3C 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR4 ADC Data Register 4 0x40 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR5 ADC Data Register 5 0x44 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR6 ADC Data Register 6 0x48 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 DR7 ADC Data Register 7 0x4C 32 read-write n 0x0 0xFFFF ADCDATA ADC conversion result data 4 12 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF EOCIRQE ADC single conversion interrupt enable 0 1 EOSIRQE ADC sequence conversion interrupt enable 2 1 TRGIRQE ADC trigger conversion interrupt enable 3 1 MR ADC Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADEN ADC Enable 7 1 ADMOD ADC convert mode 4 2 ARST ARST 6 1 SEQCNT SEQCNT 8 3 STSEL STSEL 12 5 TRGSEL TRGSEL 0 2 SCSR ADC Sequence Channel Selection Register 0x18 32 read-write n 0x0 0xFFFFFFFF SEQ0CH 1st conversion sequence channel selection 0 4 SEQ1CH 2nd conversion sequence channel selection 4 4 SEQ2CH 3rd conversion sequence channel selection 8 4 SEQ3CH 4th conversion sequence channel selection 12 4 SEQ4CH 5th conversion sequence channel selection 16 4 SEQ5CH 6th conversion sequence channel selection 20 4 SEQ6CH 7th conversion sequence channel selection 24 4 SEQ7CH 8th conversion sequence channel selection 28 4 SR ADCn Status Register 0x24 32 read-write n 0x0 0xFFFFFFFF ABUSY ADC conversion busy flag 6 1 EOC ADC End Flag 7 1 EOCIRQ EOCIRQ 0 1 EOSIRQ EOSIRQ 2 1 TRGIRQ ADC Trigger interrupt flag 3 1 TRG ADC Trigger Selection Register 0xC 32 read-write n 0x0 0xFFFFFFFF SEQTRG0 1st Sequence Trigger Source 0 4 SEQTRG1 2nd Sequence Trigger Source 4 4 SEQTRG2 3rd Sequence Trigger Source 8 4 SEQTRG3 4th Sequence Trigger Source 12 4 SEQTRG4 5th Sequence Trigger Source 16 4 SEQTRG5 6th Sequence Trigger Source 20 4 SEQTRG6 7th Sequence Trigger Source 24 4 SEQTRG7 8th Sequence Trigger Source 28 4 DIV64 DIVIDER DIV64 0x40000500 0x0 0x100 registers n AREGH AREG (Dividend) High 32bit Register 0x8 32 read-write n 0x0 0xFFFFFFFF AREGL AREGL (Dividend) Low 32bit Register 0x4 32 read-write n 0x0 0xFFFFFFFF BREG BREG (Divisor) Register 0xC 32 read-write n 0x0 0xFFFFFFFF CR Divider Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF BUSY Divider is now under operating 9 1 DONE Divider operation done flag 8 1 I_ERROR Divide by zero flag 10 1 MODE Start operation mode 4 1 START Divide operation start command. 0 1 QREGH QREG (Quotient) High 32bit Register 0x14 32 read-write n 0x0 0xFFFFFFFF QREGL QREG (Quotient) Low 32bit Register 0x10 32 read-write n 0x0 0xFFFFFFFF RREG RREG (Remainter) Register 0x18 32 read-write n 0x0 0xFFFFFFFF FM FLASH MEMORY CONTROLLER FMC 0x40000100 0x0 0x100 registers n AR Flash Memory Address Register 0xC 32 read-write n 0x0 0xFFFF FADDR 16K words address 0 15 BOOTCR Boot ROM Remap Clear Register 0x74 32 read-write n 0x1 0xFF BOOTROM Boot mode 0 1 SREMAP SRAM remap enable 4 1 CFG Flash Memory CONFIG value register 0x30 32 read-write n 0x0 0xFFFFFFFF CRCEN CRC16 Enable 6 1 CRCINIT CRCINIT 7 1 HRESPD HRESPD 15 1 TESTCLK TESTCLK 12 1 WAIT WAIT 8 2 WRITEKEY WRITEKEY 16 16 CR Flash Memory Control Register 0x8 32 read-write n 0x5000000 0xFFFFFFFF AEE AEE 9 1 AEF All Erase 8 1 BLKE 128page write enable for full chip writing to save program time 12 1 DMYE DUMMY Area enable 11 1 ERS program mode/erase mode Enable 1 1 EVER Erase verify Mode 14 1 OTP0 OTP0 28 1 OTP1 OTP1 29 1 OTP2 OTP2 30 1 OTP3 OTP3 31 1 OTPE OTP area a,b,c,d enable 10 1 PBLD page buffer load 3 1 PBR page buffer reset 0 1 PGM PGM 2 1 PMODE Pmode Enable 5 1 PPGM PPGM 6 1 PVER Program verify mode 13 1 SUBACT SUBACT 7 1 TEST TEST 16 2 TMREN program timer enable 20 1 read-write VPPOUT Charge pump Vpp Output 15 1 WE write Enable 4 1 CRC Flash Memory CRC value register 0x20 32 read-write n 0x0 0xFFFFFFFF CRC CRC16 Value 0 16 DIRTY Flash Memory Dirty Register 0x18 32 write-only n 0x0 0xFFFFFFFF FDIRTY Write any value to clear the Cache line fill 0 32 DR Flash Memory Data Register 0x10 32 read-write n 0x0 0xFFFFFFFF FDATA Flash PGM data 0 32 HWID Flash Hardware ID Register 0x40 32 read-only n 0x0 0xFFFFFFFF FHWID FHWID Value 0 32 MR Flash Memory Mode Register 0x4 32 read-write n 0x1000000 0xFFFFFFFF ACODE Flash Mode/Trim Mode 0 8 read-write AMBAEN AMBA mode enable 22 1 read-only FEMOD Flash Mode entry status 9 1 read-only FMOD Flash Mode status 8 1 read-only IDLE Idle mode status 24 1 read-only PROTEN Flash protection 21 1 read-only TESTEN Flash test 23 1 read-only TRM Trim Mode status 16 1 read-only TRMEN Trim Mode entry status 17 1 read-only RPROT Flash Memory Read Protection Register 0x7C 32 read-write n 0x0 0xFFFFFFFF JTAGDIS JTAG Disable State Flag 29 1 read-only LOCK1 Read Protection Level 1 State Flag 30 1 read-only LOCK2 Read Protection Level 2 State Flag 31 1 read-only RPEN Read Protection Enable 0 8 read-write TICK Flash Memory Tick Timer register 0x1C 32 read-write n 0x0 0xFFFFFFFF FTICK TICK 0 32 TMR Flash Memory Timer Register 0x14 32 read-write n 0xBB 0xFFFF TMR Erase/PGM timer 0 18 WPROT Flash Memory Write Protection Register 0x78 32 read-write n 0xFFFF01 0xFFFFFFFF WP Sector protect 0 16 WPEN WP access enable 24 8 FRT Free-run Timer FRT 0x40000600 0x0 0x100 registers n FRT 9 CNT Free Run Timer Counter Register 0xC 32 read-write n 0x0 0xFFFFFFFF CR FRT Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF CLR FRT Counter register clear bit 2 1 EN FRT enable bit 0 1 HOLD FRT Counter register hold bit 1 1 RREQ FRT Counter read request bit 3 1 MR FRT Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF CLKSEL FRT Counter clock source control 4 2 MCD Counter Match Clear Disable bit 2 1 MIE Match Interrupt Enable bit 0 1 OVIE Over Flow Interrupt Enable bit 1 1 PER Free Run Timer Period Match Register 0x8 32 read-write n 0x0 0xFFFFFFFF SR Free Run Timer Status Register 0x10 32 read-write n 0x0 0x3 MF Interrupt Flag 0 1 OVF Overflow Interrupt Flag 1 1 RACK Read Counter Acknowledge bit 2 1 IC I2C Interface I2C 0x4000A000 0x0 0x100 registers n I2C 21 CR I2C Control Register 0x14 32 read-write n 0x0 0x3FF ACKEN ACK enabit bit in receiver mode 3 1 IIF Interrupt flag bit 7 1 INTDEL Interval delay value between address and data transfer 8 2 INTEN Interrupt enable bit 4 1 SOFTRST Soft reset enable bit 5 1 START transmission start bit in master mode 0 1 STOP Stop enable bit 1 1 DR I2C Data Register 0x0 32 read-write n 0x0 0xFF DR Data 0 8 SAR I2C Slave Address Register 0xC 32 read-write n 0x0 0xFF GCEN general call enable bit 0 1 SVAD 7 bits slave address 1 7 SCLH I2C SCL HIGH duration Register 0x1C 32 read-write n 0xFFFF 0xFFFF SCLH SCL High duration value 0 16 SCLL I2C SCL LOW duration Register 0x18 32 read-write n 0xFFFF 0xFFFF SCLL SCL Low duration value 0 16 SDH SDA Hold Register 0x20 32 read-write n 0x0 0x7F SDH SDA Hold time 0 15 SR SR Status register 0x8 32 read-write n 0x0 0xFFFFFFFF BUSY busy flag 2 1 GCALL General call flag 7 1 MLOST Mastership lost flag 3 1 RXACK RX ack flag 0 1 SSEL slave flag 4 1 STOP Stop Flag 5 1 TEND 1 byte transmission complete flag 6 1 TMODE Transmit/reciever mode flag 1 1 MP MOTOR PULSE-WIDTH-MODULATOR MPWM 0x40004000 0x0 0x1000 registers n MPWM 18 MPWMPROT 19 MPWMOVV 20 ATR1 MPWMn ADC Trigger Counter 1 Register 0x58 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR2 MPWMn ADC Trigger Counter 2 Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR3 MPWMn ADC Trigger Counter 3 Register 0x60 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR4 MPWMn ADC Trigger Counter 4 Register 0x64 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR5 MPWMn ADC Trigger Counter 5 Register 0x68 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR6 MPWMn ADC Trigger Counter 6 Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 CNT MPWM Counter Register 0x38 32 read-write n 0x0 0xFFFF CNT pwm counter value 0 16 CR1 MPWM Control Register 1 0x28 32 read-write n 0x0 0xFFFF IRQN IRQ intervel Number 8 3 PWMEN PWMEN 0 1 CR2 MPWM Control Register 2 0x2C 32 read-write n 0x0 0xFF HALT HALT 7 1 PSTART PWM start 0 1 DTR MPWM Dead Time Register 0x3C 32 read-write n 0x0 0xFFFF DT dead time value 0 8 DTCLK dead time clk select 8 1 DTEN dead time Enable 15 1 PSHRT PSHRT 14 1 DUH MPWM Duty UH Register 0x10 32 read-write n 0x0 0xFFFF DUTY duty of UH output 0 16 DUL MPWM Duty UL Register 0x1C 32 read-write n 0x0 0xFFFF DUTY duty of UL output 0 16 DVH MPWM Duty VH Register 0x14 32 read-write n 0x0 0xFFFF DUTY duty of VH data 0 16 DVL MPWM Duty UL Register 0x20 32 read-write n 0x0 0xFFFF DUTY duty of VL output 0 16 DWH MPWM Duty WH Register 0x18 32 read-write n 0x0 0xFFFF DUTY duty of WH output 0 16 DWL MPWM Duty WL Register 0x24 32 read-write n 0x0 0xFFFF DUTY duty of WL output 0 16 FOR MPWM Force Output Register 0x8 32 read-write n 0x0 0xFF UHFL UHFL 3 1 ULFL ULFL 0 1 VHFL VHFL 4 1 VLFL VLFL 1 1 WHFL WHFL 5 1 WLFL WLFL 2 1 IER MPWM Interrupt Enable Register 0x34 32 read-write n 0x0 0xFF BOTIE bottom interrupt enable 6 1 PRDIEN Period interrupt enable 7 1 UHIE UHIE 3 1 ULIE ULIE 0 1 VHIE VHIE 4 1 VLIE VLIE 1 1 WHIE WHIE 5 1 WLIE WLIE 2 1 MR MPWM Mode Register 0x0 32 read-write n 0x0 0xFFFF BUP BUP 4 1 MCHMOD MCHMOD 1 2 MOTORB MOTORB 15 1 TUP TUP 5 1 UAO UAO 7 1 UPDOWN PWM counter mode 0 1 OLR MPWM Port Mode Register 0x4 32 read-write n 0x0 0xFFFF UHL UHL 3 1 ULL ULL 0 1 VHL VHL 4 1 VLL VLL 1 1 WHL WHL 5 1 WLL WLL 2 1 PCR0 MPWM Protection control Register 0 0x40 32 read-write n 0x0 0xFFFFFFFF PROTD PROTD 8 3 PROTEN PROTEN 15 1 PROTIE PROTIE 7 1 PROTPOL PROTPOL 14 1 UHPROTM UHPROTM 3 1 ULPROTM ULPROTM 0 1 VHPROTM VHPROTM 4 1 VLPROTM VLPROTM 1 1 WHPROTM WHPROTM 5 1 WLPROTM WLPROTM 2 1 PCR1 MPWM Protection control Register 1 0x48 32 read-write n 0x0 0xFFFFFFFF PROTD PROTD 8 3 PROTEN PROTEN 15 1 PROTIE PROTIE 7 1 PROTPOL PROTPOL 14 1 UHPROTM UHPROTM 3 1 ULPROTM ULPROTM 0 1 VHPROTM VHPROTM 4 1 VLPROTM VLPROTM 1 1 WHPROTM WHPROTM 5 1 WLPROTM WLPROTM 2 1 PRD MPWM Period Register 0xC 32 read-write n 0x0 0xFFFF PERIOD PWM period 0 16 PSR0 MPWM Protection Status Register 0 0x44 32 read-write n 0x0 0xFFFFFFFF PROTIF PROTIF 7 1 PROTKEY PROTKEY(0xCA) 8 8 UHPROTF UHPROTF 3 1 ULPROTF ULPROTF 0 1 VHPROTF VHPROTF 4 1 VLPROTF VLPROTF 1 1 WHPROTF WHPROTF 5 1 WLPROTF WLPROTF 2 1 PSR1 MPWM Protection Status Register 1 0x4C 32 read-write n 0x0 0xFFFFFFFF PROTIF PROTIF 7 1 PROTKEY PROTKEY(0xAC) 8 8 UHPROTF UHPROTF 3 1 ULPROTF ULPROTF 0 1 VHPROTF VHPROTF 4 1 VLPROTF VLPROTF 1 1 WHPROTF WHPROTF 5 1 WLPROTF WLPROTF 2 1 SR MPWM Status Register 0x30 32 read-write n 0x0 0xFFFF BOTIRQ PWM bottom interrupt flag 6 1 DOWN PWM count up/down 15 1 DUHIF DUHIF 3 1 DULIF DULIF 0 1 DVHIF DVHIF 4 1 DVLIF DVLIF 1 1 DWHIF DWHIF 5 1 DWLIF DWLIF 2 1 IRQCNT PWM count number of period match 12 3 PRDIRQ PWM period interrupt flag 7 1 PA GENERAL PURPOSE I/O GPIO 0x40002000 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PB GENERAL PURPOSE I/O GPIO 0x40002100 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PC GENERAL PURPOSE I/O GPIO 0x40002200 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PCA PORT CONTROL UNIT PCU 0x40001000 0x0 0x100 registers n GPIOAE 10 GPIOAO 11 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control SEL 2 2 P10 P10 control SEL 20 2 P11 P11 control SEL 22 2 P12 P12 control SEL 24 2 P13 P13 control SEL 26 2 P14 P14 control SEL 28 2 P15 P15 control SEL 30 2 P2 P2 control SEL 4 2 P3 P3 control SEL 6 2 P4 P4 control SEL 8 2 P5 P5 control SEL 10 2 P6 P6 control SEL 12 2 P7 P7 control SEL 14 2 P8 P8 control SEL 16 2 P9 P9 control SEL 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt enable 2 2 P10 P10 interrupt enable 20 2 P11 P11 interrupt enable 22 2 P12 P12 interrupt enable 24 2 P13 P13 interrupt enable 26 2 P14 P14 interrupt enable 28 2 P15 P15 interrupt enable 30 2 P2 P2 interrupt enable 4 2 P3 P3 interrupt enable 6 2 P4 P4 interrupt enable 8 2 P5 P5 interrupt enable 10 2 P6 P6 interrupt enable 12 2 P7 P7 interrupt enable 14 2 P8 P8 interrupt enable 16 2 P9 P9 interrupt enable 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 MUX SEL 2 2 P10 P10 MUX SEL 20 2 P11 P11 MUX SEL 22 2 P12 P12 MUX SEL 24 2 P13 P13 MUX SEL 26 2 P14 P14 MUX SEL 28 2 P15 P15 MUX SEL 30 2 P2 P2 MUX SEL 4 2 P3 P3 MUX SEL 6 2 P4 P4 MUX SEL 8 2 P5 P5 MUX SEL 10 2 P6 P6 MUX SEL 12 2 P7 P7 MUX SEL 14 2 P8 P8 MUX SEL 16 2 P9 P9 MUX SEL 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCB PORT CONTROL UNIT PCU 0x40001100 0x0 0x100 registers n GPIOBE 12 GPIOBO 13 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control SEL 2 2 P10 P10 control SEL 20 2 P11 P11 control SEL 22 2 P12 P12 control SEL 24 2 P13 P13 control SEL 26 2 P14 P14 control SEL 28 2 P15 P15 control SEL 30 2 P2 P2 control SEL 4 2 P3 P3 control SEL 6 2 P4 P4 control SEL 8 2 P5 P5 control SEL 10 2 P6 P6 control SEL 12 2 P7 P7 control SEL 14 2 P8 P8 control SEL 16 2 P9 P9 control SEL 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt enable 2 2 P10 P10 interrupt enable 20 2 P11 P11 interrupt enable 22 2 P12 P12 interrupt enable 24 2 P13 P13 interrupt enable 26 2 P14 P14 interrupt enable 28 2 P15 P15 interrupt enable 30 2 P2 P2 interrupt enable 4 2 P3 P3 interrupt enable 6 2 P4 P4 interrupt enable 8 2 P5 P5 interrupt enable 10 2 P6 P6 interrupt enable 12 2 P7 P7 interrupt enable 14 2 P8 P8 interrupt enable 16 2 P9 P9 interrupt enable 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 MUX SEL 2 2 P10 P10 MUX SEL 20 2 P11 P11 MUX SEL 22 2 P12 P12 MUX SEL 24 2 P13 P13 MUX SEL 26 2 P14 P14 MUX SEL 28 2 P15 P15 MUX SEL 30 2 P2 P2 MUX SEL 4 2 P3 P3 MUX SEL 6 2 P4 P4 MUX SEL 8 2 P5 P5 MUX SEL 10 2 P6 P6 MUX SEL 12 2 P7 P7 MUX SEL 14 2 P8 P8 MUX SEL 16 2 P9 P9 MUX SEL 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCC PORT CONTROL UNIT PCU 0x40001200 0x0 0x100 registers n GPIOCE 14 GPIOCO 15 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control SEL 2 2 P10 P10 control SEL 20 2 P11 P11 control SEL 22 2 P12 P12 control SEL 24 2 P13 P13 control SEL 26 2 P14 P14 control SEL 28 2 P15 P15 control SEL 30 2 P2 P2 control SEL 4 2 P3 P3 control SEL 6 2 P4 P4 control SEL 8 2 P5 P5 control SEL 10 2 P6 P6 control SEL 12 2 P7 P7 control SEL 14 2 P8 P8 control SEL 16 2 P9 P9 control SEL 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt enable 2 2 P10 P10 interrupt enable 20 2 P11 P11 interrupt enable 22 2 P12 P12 interrupt enable 24 2 P13 P13 interrupt enable 26 2 P14 P14 interrupt enable 28 2 P15 P15 interrupt enable 30 2 P2 P2 interrupt enable 4 2 P3 P3 interrupt enable 6 2 P4 P4 interrupt enable 8 2 P5 P5 interrupt enable 10 2 P6 P6 interrupt enable 12 2 P7 P7 interrupt enable 14 2 P8 P8 interrupt enable 16 2 P9 P9 interrupt enable 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 MUX SEL 2 2 P10 P10 MUX SEL 20 2 P11 P11 MUX SEL 22 2 P12 P12 MUX SEL 24 2 P13 P13 MUX SEL 26 2 P14 P14 MUX SEL 28 2 P15 P15 MUX SEL 30 2 P2 P2 MUX SEL 4 2 P3 P3 MUX SEL 6 2 P4 P4 MUX SEL 8 2 P5 P5 MUX SEL 10 2 P6 P6 MUX SEL 12 2 P7 P7 MUX SEL 14 2 P8 P8 MUX SEL 16 2 P9 P9 MUX SEL 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCD PORT CONTROL UNIT PCU 0x40001300 0x0 0x100 registers n GPIODE 16 GPIODO 17 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control SEL 2 2 P10 P10 control SEL 20 2 P11 P11 control SEL 22 2 P12 P12 control SEL 24 2 P13 P13 control SEL 26 2 P14 P14 control SEL 28 2 P15 P15 control SEL 30 2 P2 P2 control SEL 4 2 P3 P3 control SEL 6 2 P4 P4 control SEL 8 2 P5 P5 control SEL 10 2 P6 P6 control SEL 12 2 P7 P7 control SEL 14 2 P8 P8 control SEL 16 2 P9 P9 control SEL 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt enable 2 2 P10 P10 interrupt enable 20 2 P11 P11 interrupt enable 22 2 P12 P12 interrupt enable 24 2 P13 P13 interrupt enable 26 2 P14 P14 interrupt enable 28 2 P15 P15 interrupt enable 30 2 P2 P2 interrupt enable 4 2 P3 P3 interrupt enable 6 2 P4 P4 interrupt enable 8 2 P5 P5 interrupt enable 10 2 P6 P6 interrupt enable 12 2 P7 P7 interrupt enable 14 2 P8 P8 interrupt enable 16 2 P9 P9 interrupt enable 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 MUX SEL 2 2 P10 P10 MUX SEL 20 2 P11 P11 MUX SEL 22 2 P12 P12 MUX SEL 24 2 P13 P13 MUX SEL 26 2 P14 P14 MUX SEL 28 2 P15 P15 MUX SEL 30 2 P2 P2 MUX SEL 4 2 P3 P3 MUX SEL 6 2 P4 P4 MUX SEL 8 2 P5 P5 MUX SEL 10 2 P6 P6 MUX SEL 12 2 P7 P7 MUX SEL 14 2 P8 P8 MUX SEL 16 2 P9 P9 MUX SEL 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PD GENERAL PURPOSE I/O GPIO 0x40002300 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PORTEN Port Control Mode Enable Register PORTEN 0x40001FF0 0x0 0x10 registers n EN Port Access Enable 0x15->0x51 0x0 32 read-write n 0x0 0xFFFF SCU SYSTEM CONTROL UNIT SCU 0x40000000 0x0 0x100 registers n LVDDETECT 0 SYSCLKFAIL 1 MOSCFAIL 2 SOSCFAIL 3 BISCCON Build in self calibration control Register 0x70 32 read-write n 0x0 0xFFFFFFFF INTOSC_COMP INTOSC_COMP 16 16 write-only XTAL_COMP XTAL_COMP 0 16 read-write CMR Clock Monitoring Register 0x48 32 read-write n 0x90 0xFFFF MCLKFAIL MCLK Failed flag 5 1 read-write MCLKIE MCLK fail Interrupt enable 6 1 read-write MCLKMNT MCLK monitor enable 7 1 read-write MCLKREC MCLK failed auto recovery 15 1 read-write MCLKSTS MCLK clock status 4 1 read-write MOSCFAIL external OSC failed flag 1 1 read-write MOSCIE external OSC failed interrupt enable 2 1 read-write MOSCMNT External OSC monitor enable 3 1 read-write MOSCSTS external OSC status 0 1 read-write SOSCFAIL Sub Oscillator fail interrupt flag 9 1 read-write SOSCIE Sub Oscillator fail interrupt enable 10 1 read-write SOSCMNT Sub Oscillator monitoring enable 11 1 read-write SOSCSTS Sub Oscillator clock status 8 1 read-write COR Clock Output Register 0x50 32 read-write n 0xF 0xFF CLKODIV clock output divider value 0 4 read-write CLKOEN clock output enable 4 1 read-write CSCR Clock Source Control Register 0x40 32 read-write n 0x20 0xFF HSICON High speed internal oscillator control 2 2 LSICON Low speed internal oscillator control 4 2 MOSCCON External crystal main oscillator control 0 2 SOSCCON External crystal sub oscillator control 6 2 DBCLK1 Debounce Clock Control Register 1 0x9C 32 read-write n 0x10001 0xFFFFFFFF PADCSEL Debounce Clock for Port A source select 8 3 PADDIV PORT A Debounce Clock N divider 0 8 PBDCSEL Debounce Clock for Port B source select 24 3 PBDDIV PORT B Debounce Clock N divider 16 8 DBCLK2 Debounce Clock Control Register 2 0xA0 32 read-write n 0x10001 0xFFFFFFFF PCDCSEL debouce clock for port C source clock sel 8 3 PCDDIV PORT C debounce divider 0 8 PDDCSEL debouce clock for port D source clock sel 24 3 PDDDIV PORT D debounce divider 16 8 EMODR External Mode Status Register 0x84 32 read-only n 0x0 0xFF BOOT boot pin level 0 1 EMOSCR External Main Oscillator Control Register 0x80 32 read-write n 0x300 0xFFFF FILSKIPEN Control External Main Oscillator Filter Skip 8 1 read-write FILSKIPWEN Write enable of bit field FILSKIPEN 15 1 write-only INVCLKEN Control External Main Oscillator CLK invert 0 1 read-write INVCLKWEN Write enable of bit field FILSKIPEN 7 1 write-only HSIOSCTRIM High Speed Internal OSC Trim Register 0x6C 32 read-write n 0x7780FF 0xFFFFFFFF BISCON Build in self calibration function enable 31 1 read-write REFSEL Reference clock select for self-calibration 30 1 read-write LVDCON LVD Control Register 0x68 32 read-write n 0x1 0xFFFFFFFF LVDEN LVDEN 0 1 read-write LVDLVL LVDLVL 1 1 read-only LVDSEL LVDSEL 8 2 read-write SELEN SELEN 15 1 write-only MCCR1 Miscellaneous Clock Control Register 1 0x90 32 read-write n 0x0 0xFFFFFFFF STCDIV systick divider 0 8 read-write STCSEL systick clock source sel 8 3 read-write MCCR2 Miscellaneous Clock Control Register 2 0x94 32 read-write n 0x0 0xFFFFFFFF PWMCSEL MPWM Clock source sel 8 3 PWMDIV MPWM clock n divider 0 8 MCCR3 Miscellaneous Clock Control Register 3 0x98 32 read-write n 0x1 0xFFFFFFFF TIMERCSEL Timer Clock source sel 24 3 TIMERDIV Timer Clock divider 16 8 WDTCSEL WDT clock sel 8 3 WDTDIV WDT divider 0 8 MCCR4 Miscellaneous Clock Control Register 4 0xA8 32 read-write n 0x10000 0xFFFFFFFF ADCCDIV ADC Clock N divider 16 8 ADCCSEL ADC clock source select bit 24 3 UARTCDIV UART Clock N divider 0 8 UARTCSEL UART clock source select bit 8 3 NMIR NMI Control Register 0x4C 32 read-write n 0x3 0xFFFF ACODE 0xA32C to write 16 16 LVDEN LVDEN 0 1 LVDSTS LVDSTS 8 1 read-only MCLKFAILEN MCLKFAILEN 1 1 MCLKFAILSTS MCLKFAILSTS 9 1 read-only OVPEN OVPEN 3 1 OVPSTS OVPSTS 11 1 read-only PROTEN PROTEN 4 1 PROTSTS PROTSTS 12 1 read-only WDTINTEN WDTINTEN 2 1 WDTINTSTS WDTINTSTS 10 1 read-only PCER1 Peripheral Clock Enable Register 1 0x30 32 read-write n 0xF 0xFFFFFFFF DIV64 DIV64 5 1 FRT FRT clock enable 26 1 GPIOA GPIOA clock enable 8 1 GPIOB GPIOB clock enable 9 1 GPIOC GPIOC clock enable 10 1 GPIOD GPIOD clock enable 11 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 clock enable 17 1 TIMER2 TIMER2 clock enable 18 1 TIMER3 Timer3 clock enable 19 1 PCER2 Peripheral Clock Enable Register 2 0x34 32 read-write n 0x101 0xFFFFFFFF ADC ADC clock enable 20 1 I2C I2C clock enable 4 1 MPWM MPWM clock enable 16 1 SPI SPI clock enable 0 1 UART0 UART0 8 1 UART1 UART1 clock enable 9 1 PER1 Peripheral Enable Register 1 0x28 32 read-write n 0xF 0xFFFFFFFF DIV64 DIV64 5 1 FRT FRT 26 1 GPIOA GPIOA 8 1 GPIOB GPIOB 9 1 GPIOC GPIOC 10 1 GPIOD GPIOD 11 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 17 1 TIMER2 TIMER2 18 1 TIMER3 TIMER3 19 1 PER2 Peripheral Enable Register 2 0x2C 32 read-write n 0x101 0xFFFFFFFF ADC ADC 20 1 I2C I2C 4 1 MPWM MPWM 16 1 SPI SPI Enable 0 1 UART0 UART0 8 1 UART1 UART1 9 1 PRER1 Peripheral Reset Enable Register 1 0x20 32 read-write n 0x40F0F2F 0xFFFFFFFF DIV64 DIV64 Reset enable 5 1 FMC Flash Memory controller Reset enable 1 1 FRT FRT Reset enable 26 1 GPIOA GPIOA Reset enable 8 1 GPIOB GPIOB Reset enable 9 1 GPIOC GPIOC Reset enable 10 1 GPIOD GPIOD Reset enable 11 1 PCU Port Controller unit reset enable 3 1 SCU Power Management Unit Reset enable 0 1 TIMER0 TIMER0 Reset enable 16 1 TIMER1 TIMER1 reset enable 17 1 TIMER2 TIMER2 Reset enable 18 1 TIMER3 TIMER3 Reset enable 19 1 WDT WatchDog timer reset enable 2 1 PRER2 Peripheral Reset Enable Register 2 0x24 32 read-write n 0x110311 0xFFFFFFFF ADC ADC Reset enable 20 1 I2C I2C Reset enable 4 1 MPWM MPWM Reset enable 16 1 SPI SPI Reset enable 0 1 UART0 UART0 Reset enable 8 1 UART1 UART1 Reset enable 9 1 RSER Reset Source Enable Register 0x18 32 read-write n 0x69 0xFF CPURST CPU request reset enable 5 1 LOCKUPRST CPU Lock up reset enable bit 7 1 LVDRST LVD reset enable 0 1 MCKFRST MCLK Clock fail reset enable 2 1 MOFRST MOSC Clock fail reset enable 1 1 PINRST external pin reset enable 6 1 SWRST software reset enable 4 1 WDTRST watch dog reset enable 3 1 RSSR Reset Source Status Register 0x1C 32 read-write n 0x80 0x1FF CPURST cpu request reset status 5 1 LOCKUPRST CPU Lock up reset status 8 1 LVDRST lvd reset status 0 1 MCKFRST MCLK failed reset status 2 1 MOFRST MOSC Clock fail reset status 1 1 PINRST extenral pin reset status 6 1 PORST power on reset status 7 1 SWRST software reset status 4 1 WDTRST watchdog timer reset status 3 1 SCCR System Clock Control Register 0x44 32 read-write n 0x0 0xFF MCLKSEL System clock select 0 3 SMR System Mode Register 0x4 32 read-write n 0x0 0x330 LSIAON LSIAON 9 1 PREVMODE PREVMODE 4 2 read-only VDCAON VDCAON 8 1 SRCR System Reset Control Register 0x8 32 read-write n 0x0 0x11 STBOP STBOP pin output polarity select bit 4 1 SWRST Internal soft reset activation 0 1 VDCCON VDC Control Register 0x64 32 read-write n 0x7F 0xFFFFFFFF STOPSEL VDC STOP MODE Select bit 25 1 write-only VDCDE VDCWDLY value write enable. Write only with VDCWDLY value 8 1 write-only VDCME VDCMODE value write enable. Write only with VDCMODE value 31 1 write-only VDCWDLY VDC warm up delay count 0 4 write-only WUER Wakeup Source Enable Register 0x10 32 read-write n 0x0 0xF07 FRTWUE FRTWUE 2 1 GPIOAWUE GPIOAWUE 8 1 GPIOBWUE GPIOBWUE 9 1 GPIOCWUE GPIOCWUE 10 1 GPIODWUE GPIODWUE 11 1 LVDWUE LVDWUE 0 1 WDTWUE WDTWUE 1 1 WUSR Wakeup Source Status Register 0x14 32 read-only n 0x0 0xF07 FRTWU FRTWU 2 1 GPIOAWU GPIOAWU 8 1 GPIOBWU GPIOBWU 9 1 GPIOCWU GPIOCWU 10 1 GPIODWU GPIODWU 11 1 LVDWU LVDWU 0 1 WDTWU WDTWU 1 1 SP SERIAL PERIPHERAL INTERFACE SPI 0x40009000 0x0 0x100 registers n SPI 22 BR SPI n Baud Rate Register 0xC 32 read-write n 0x0 0xFFFF BR buadrate 0 16 CR SPI n Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF BITSZ Transmit/receive Data bits select bit 0 2 CPHA SPI clock phase bit 3 1 CPOL SPI clock polarity bit 2 1 LBE Loop-back mode select bit in master mode 11 1 MS master/slaver select bit 5 1 MSBF MSB/LSB transmit select bit 4 1 RXBC Rx buffer clear bit 19 1 RXIE Receive interrupt enable bit 14 1 SSCIE SSn Edge Change Interrupt enable bit 16 1 SSMASK SS Signal masking bit in slave mode 10 1 SSMO SS output signal select bit 9 1 SSMOD SS Auto/Manual Output select bit 13 1 SSOUT SS output signal select bit 12 1 SSPOL SS Signal polarity select bit 8 1 TXBC Tx buffer clear bit 20 1 TXIE Transmit interrupt enable bit 15 1 EN SPI n Enable register 0x10 32 read-write n 0x0 0xFF ENABLE SPI ENABLE bit 0 1 LR SPI n delay Length Register 0x14 32 read-write n 0x0 0xFFFFFFFF BTL Burst delay length 8 8 SPL Stop delay length 16 8 STL Start delay length 0 8 RDR SPI n Receive Data Register 0x0 32 read-only n 0x0 0xFFFF RDR Data 0 17 SR SPI n Status Register 0x8 32 read-write n 0x0 0xFFFF OVRF receive overrun error flag 4 1 read-write RRDY receive buffer ready flag 0 1 read-only SSDET The rising edge of SS detect flag 6 1 read-write SSON SS signal status flag 5 1 read-write TRDY Transmit buffer empty flag 1 1 read-only TXIDLE transmit/receive operation flag 2 1 read-only UDRF transmit underrun error flag 3 1 read-write TDR SPI n Transmit Data Register 0x0 32 write-only n 0x0 0xFFFF TDR Data 0 17 T0 16-BIT TIMER TIMER 0x40003000 0x0 0x20 registers n TIMER0 5 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 PRECLR Prescaler Initialized for counting 16 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronize clear counter with other synchronized tip 14 1 MODE Timer operation mode control 0 2 OUTPOL timer output polarity 12 1 SSYNC Synchronize start counter with other synchronized timers 15 1 STARTLVL STARTLVL 7 1 UAO Select GRA,GRB Update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 PWMO Timer PWM Output Flag 7 1 read-only TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A (Duty) 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B (Period) 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x7 MAIE GRA Match interrupt enable 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA GRA Match flag 2 1 MFB GRB Match flag 1 1 OVF counter overflow flag 0 1 T1 16-BIT TIMER TIMER 0x40003020 0x0 0x20 registers n TIMER1 6 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 PRECLR Prescaler Initialized for counting 16 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronize clear counter with other synchronized tip 14 1 MODE Timer operation mode control 0 2 OUTPOL timer output polarity 12 1 SSYNC Synchronize start counter with other synchronized timers 15 1 STARTLVL STARTLVL 7 1 UAO Select GRA,GRB Update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 PWMO Timer PWM Output Flag 7 1 read-only TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A (Duty) 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B (Period) 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x7 MAIE GRA Match interrupt enable 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA GRA Match flag 2 1 MFB GRB Match flag 1 1 OVF counter overflow flag 0 1 T2 16-BIT TIMER TIMER 0x40003040 0x0 0x20 registers n TIMER2 7 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 PRECLR Prescaler Initialized for counting 16 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronize clear counter with other synchronized tip 14 1 MODE Timer operation mode control 0 2 OUTPOL timer output polarity 12 1 SSYNC Synchronize start counter with other synchronized timers 15 1 STARTLVL STARTLVL 7 1 UAO Select GRA,GRB Update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 PWMO Timer PWM Output Flag 7 1 read-only TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A (Duty) 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B (Period) 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x7 MAIE GRA Match interrupt enable 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA GRA Match flag 2 1 MFB GRB Match flag 1 1 OVF counter overflow flag 0 1 T3 16-BIT TIMER TIMER 0x40003060 0x0 0x20 registers n TIMER3 8 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 PRECLR Prescaler Initialized for counting 16 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronize clear counter with other synchronized tip 14 1 MODE Timer operation mode control 0 2 OUTPOL timer output polarity 12 1 SSYNC Synchronize start counter with other synchronized timers 15 1 STARTLVL STARTLVL 7 1 UAO Select GRA,GRB Update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 PWMO Timer PWM Output Flag 7 1 read-only TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A (Duty) 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B (Period) 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x7 MAIE GRA Match interrupt enable 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA GRA Match flag 2 1 MFB GRB Match flag 1 1 OVF counter overflow flag 0 1 U0 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008000 0x0 0x100 registers n UART0 23 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF DMS Data Bit Multi sampling enable 6 1 SMS Start Bit Multi sampling enable 7 1 WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFFFFFFFF DR Data Receive Interrupt Flag 16 1 read-only IID Interrupt source ID 1 3 read-only IPEN Interrupt pending bit 0 1 read-only RLS Receiver line status flag 18 1 read-only THRE Transmit Holding register empty flag 17 1 read-only TXE Interrupt source ID 4 1 read-only LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR received/transmit data 0 8 U1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008100 0x0 0x100 registers n UART1 24 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF DMS Data Bit Multi sampling enable 6 1 SMS Start Bit Multi sampling enable 7 1 WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFFFFFFFF DR Data Receive Interrupt Flag 16 1 read-only IID Interrupt source ID 1 3 read-only IPEN Interrupt pending bit 0 1 read-only RLS Receiver line status flag 18 1 read-only THRE Transmit Holding register empty flag 17 1 read-only TXE Interrupt source ID 4 1 read-only LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR received/transmit data 0 8 WDT WATCH-DOG TIMER WDT 0x40000200 0x0 0x100 registers n WDT 4 CNT Watchdog Timer Current Counter Register 0x4 32 read-write n 0xFFFF 0xFFFFFFFF CON Watchdog Timer Control Register 0x8 32 read-write n 0x805C 0xFFFF CKSEL WDTCLKIN clock source select 3 1 WDBG WDT operation in debug mode 15 1 WDTEN WDT counter enable 4 1 WDTIE WDT interrupt enable 7 1 WDTRE WDT interrupt reset 6 1 WPRS counter prescaler 0 3 WUF WDT underflow flag 8 1 LR Watchdog Timer Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF