Zilog, Inc Z32F12811ARS 2025.11.19 Z32F12811ARS false AD0 12-BIT A/D CONVERTER ADC 0x4000B000 0x0 0x100 registers n ADC0 43 BCSR ADC Burst Mode Channel select 0x18 32 read-write n 0x0 0xFFFFFFFF BST1CH 1st burst mode coversion channel selection 0 4 BST2CH 2nd burst mode coversion channel selection 4 4 BST3CH 3rd burst mode coversion channel selection 8 4 BST4CH 4th burst mode coversion channel selection 12 4 BST5CH 5th burst mode coversion channel selection 16 4 BST6CH 6th burst mode coversion channel selection 20 4 BST7CH 7th burst mode coversion channel selection 24 4 BST8CH 8th burst mode coversion channel selection 28 4 CCR ADC Channel Compare Control Register 0x70 32 read-write n 0x0 0xFFFFFFFF CCH compare channel select 16 4 COMPOUT ADC compare operation enable 23 1 read-only CVAL compare value 4 12 LTE compare direction(greater/less) 20 1 CR1 ADCn Control Register 1 0x8 32 read-write n 0x0 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 STSEL Sampling time selection 0 5 CR2 ADCn Control Register 2 0x20 32 read-write n 0x0 0xFFFF ASTART ADC conversion start 0 1 read-write ASTOP ADC Stop 4 1 write-only CSR ADCn Channel Select Register 0x4 32 read-write n 0x0 0xFF CHSEL channel select 0 4 DDR ADC 0/1/2 DMA Data Register 0x2C 32 read-write n 0x0 0xFFFF ADDMAR ADC conversion result data 4 12 ADMACH ADC data channel indicator 0 4 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF BIEN ADC burst conversion interrupt enable 2 1 CIEN ADC continus conversion interrupt enable 1 1 DIEN DMA done interrupt enable 4 1 SIEN ADC single conversion intterupt enable 0 1 TIEN ADC Trigger conversion intterupt enable 3 1 MR ADCn Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADCEN ADC Enable 7 1 ADCMOD ADC convert mode 4 2 BSTCNT No Burst Mode 8 3 BWAIT burst wait count value 24 8 BWAITEN Burst wait enable 12 1 DMACH DMA channel option 16 1 DMAEN DMA enable 17 1 TRGEN Trigger sources enable 3 1 TRGSRC ADC Trigger source sel 0 3 SR ADCn Status Register 0x24 32 read-write n 0x0 0xFFFFFFFF ABUSY ADC conversion busy flag 6 1 ADCH ADC channel bits of present operation 12 4 ADEND ADC End Flag 7 1 BIRQ ADC burst interrupt flag 2 1 BSTAT Burst mode operation count status 8 3 CIRQ ADC continuous interrupt flag 1 1 DMAIRQ DMA received/transfer is done 4 1 DOVRUN DMA overrun flag 5 1 MPWM0TRG MPWM0TRG 16 6 MPWM1TRG MPWM1TRG 24 6 SIRQ ADC single interrupt flag 0 1 TIRQ ADC Trigger interrupt flag 3 1 TRG Trigger event status 11 1 TRG0 ADC Trigger 0 Channel Register 0xC 32 read-write n 0x0 0xFFFFFFFF MP0TRG1 ADC channel n select for MPWM0 ADC trigger1 operation 0 4 MP0TRG2 ADC channel n select for MPWM0 ADC trigger2 operation 4 4 MP0TRG3 ADC channel n select for MPWM0 ADC trigger3 operation 8 4 MP0TRG4 ADC channel n select for MPWM0 ADC trigger4 operation 12 4 MP0TRG5 ADC channel n select for MPWM0 ADC trigger5 operation 16 4 MP0TRG6 ADC channel n select for MPWM0 ADC trigger6 operation 20 4 TRG0EN MP0TRGn enable 24 6 TRG1 ADC Trigger 1 Channel Register 0x10 32 read-write n 0x0 0xFFFFFFFF MP1TRG1 ADC channel n select for MPWM1 ADC trigger1 operation 0 4 MP1TRG2 ADC channel n select for MPWM1 ADC trigger2 operation 4 4 MP1TRG3 ADC channel n select for MPWM1 ADC trigger3 operation 8 4 MP1TRG4 ADC channel n select for MPWM1 ADC trigger4 operation 12 4 MP1TRG5 ADC channel n select for MPWM1 ADC trigger5 operation 16 4 MP1TRG6 ADC channel n select for MPWM1 ADC trigger6 operation 20 4 TRG1EN MP1TRGn enable 24 6 TRG2 ADC Trigger 2 Channel Register 0x14 32 read-write n 0x0 0xFFFFFFFF EXTCH ADC channel n select for external trigger operation 8 4 T0CH ADC channel n select for timer0 trigger operation 0 4 T1CH ADC channel n select for timer1 trigger operation 4 4 AD1 12-BIT A/D CONVERTER ADC 0x4000B100 0x0 0x100 registers n ADC1 44 BCSR ADC Burst Mode Channel select 0x18 32 read-write n 0x0 0xFFFFFFFF BST1CH 1st burst mode coversion channel selection 0 4 BST2CH 2nd burst mode coversion channel selection 4 4 BST3CH 3rd burst mode coversion channel selection 8 4 BST4CH 4th burst mode coversion channel selection 12 4 BST5CH 5th burst mode coversion channel selection 16 4 BST6CH 6th burst mode coversion channel selection 20 4 BST7CH 7th burst mode coversion channel selection 24 4 BST8CH 8th burst mode coversion channel selection 28 4 CCR ADC Channel Compare Control Register 0x70 32 read-write n 0x0 0xFFFFFFFF CCH compare channel select 16 4 COMPOUT ADC compare operation enable 23 1 read-only CVAL compare value 4 12 LTE compare direction(greater/less) 20 1 CR1 ADCn Control Register 1 0x8 32 read-write n 0x0 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 STSEL Sampling time selection 0 5 CR2 ADCn Control Register 2 0x20 32 read-write n 0x0 0xFFFF ASTART ADC conversion start 0 1 read-write ASTOP ADC Stop 4 1 write-only CSR ADCn Channel Select Register 0x4 32 read-write n 0x0 0xFF CHSEL channel select 0 4 DDR ADC 0/1/2 DMA Data Register 0x2C 32 read-write n 0x0 0xFFFF ADDMAR ADC conversion result data 4 12 ADMACH ADC data channel indicator 0 4 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF BIEN ADC burst conversion interrupt enable 2 1 CIEN ADC continus conversion interrupt enable 1 1 DIEN DMA done interrupt enable 4 1 SIEN ADC single conversion intterupt enable 0 1 TIEN ADC Trigger conversion intterupt enable 3 1 MR ADCn Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADCEN ADC Enable 7 1 ADCMOD ADC convert mode 4 2 BSTCNT No Burst Mode 8 3 BWAIT burst wait count value 24 8 BWAITEN Burst wait enable 12 1 DMACH DMA channel option 16 1 DMAEN DMA enable 17 1 TRGEN Trigger sources enable 3 1 TRGSRC ADC Trigger source sel 0 3 SR ADCn Status Register 0x24 32 read-write n 0x0 0xFFFFFFFF ABUSY ADC conversion busy flag 6 1 ADCH ADC channel bits of present operation 12 4 ADEND ADC End Flag 7 1 BIRQ ADC burst interrupt flag 2 1 BSTAT Burst mode operation count status 8 3 CIRQ ADC continuous interrupt flag 1 1 DMAIRQ DMA received/transfer is done 4 1 DOVRUN DMA overrun flag 5 1 MPWM0TRG MPWM0TRG 16 6 MPWM1TRG MPWM1TRG 24 6 SIRQ ADC single interrupt flag 0 1 TIRQ ADC Trigger interrupt flag 3 1 TRG Trigger event status 11 1 TRG0 ADC Trigger 0 Channel Register 0xC 32 read-write n 0x0 0xFFFFFFFF MP0TRG1 ADC channel n select for MPWM0 ADC trigger1 operation 0 4 MP0TRG2 ADC channel n select for MPWM0 ADC trigger2 operation 4 4 MP0TRG3 ADC channel n select for MPWM0 ADC trigger3 operation 8 4 MP0TRG4 ADC channel n select for MPWM0 ADC trigger4 operation 12 4 MP0TRG5 ADC channel n select for MPWM0 ADC trigger5 operation 16 4 MP0TRG6 ADC channel n select for MPWM0 ADC trigger6 operation 20 4 TRG0EN MP0TRGn enable 24 6 TRG1 ADC Trigger 1 Channel Register 0x10 32 read-write n 0x0 0xFFFFFFFF MP1TRG1 ADC channel n select for MPWM1 ADC trigger1 operation 0 4 MP1TRG2 ADC channel n select for MPWM1 ADC trigger2 operation 4 4 MP1TRG3 ADC channel n select for MPWM1 ADC trigger3 operation 8 4 MP1TRG4 ADC channel n select for MPWM1 ADC trigger4 operation 12 4 MP1TRG5 ADC channel n select for MPWM1 ADC trigger5 operation 16 4 MP1TRG6 ADC channel n select for MPWM1 ADC trigger6 operation 20 4 TRG1EN MP1TRGn enable 24 6 TRG2 ADC Trigger 2 Channel Register 0x14 32 read-write n 0x0 0xFFFFFFFF EXTCH ADC channel n select for external trigger operation 8 4 T0CH ADC channel n select for timer0 trigger operation 0 4 T1CH ADC channel n select for timer1 trigger operation 4 4 AD2 12-BIT A/D CONVERTER ADC 0x4000B200 0x0 0x100 registers n ADC2 45 BCSR ADC Burst Mode Channel select 0x18 32 read-write n 0x0 0xFFFFFFFF BST1CH 1st burst mode coversion channel selection 0 4 BST2CH 2nd burst mode coversion channel selection 4 4 BST3CH 3rd burst mode coversion channel selection 8 4 BST4CH 4th burst mode coversion channel selection 12 4 BST5CH 5th burst mode coversion channel selection 16 4 BST6CH 6th burst mode coversion channel selection 20 4 BST7CH 7th burst mode coversion channel selection 24 4 BST8CH 8th burst mode coversion channel selection 28 4 CCR ADC Channel Compare Control Register 0x70 32 read-write n 0x0 0xFFFFFFFF CCH compare channel select 16 4 COMPOUT ADC compare operation enable 23 1 read-only CVAL compare value 4 12 LTE compare direction(greater/less) 20 1 CR1 ADCn Control Register 1 0x8 32 read-write n 0x0 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 STSEL Sampling time selection 0 5 CR2 ADCn Control Register 2 0x20 32 read-write n 0x0 0xFFFF ASTART ADC conversion start 0 1 read-write ASTOP ADC Stop 4 1 write-only CSR ADCn Channel Select Register 0x4 32 read-write n 0x0 0xFF CHSEL channel select 0 4 DDR ADC 0/1/2 DMA Data Register 0x2C 32 read-write n 0x0 0xFFFF ADDMAR ADC conversion result data 4 12 ADMACH ADC data channel indicator 0 4 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF BIEN ADC burst conversion interrupt enable 2 1 CIEN ADC continus conversion interrupt enable 1 1 DIEN DMA done interrupt enable 4 1 SIEN ADC single conversion intterupt enable 0 1 TIEN ADC Trigger conversion intterupt enable 3 1 MR ADCn Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADCEN ADC Enable 7 1 ADCMOD ADC convert mode 4 2 BSTCNT No Burst Mode 8 3 BWAIT burst wait count value 24 8 BWAITEN Burst wait enable 12 1 DMACH DMA channel option 16 1 DMAEN DMA enable 17 1 TRGEN Trigger sources enable 3 1 TRGSRC ADC Trigger source sel 0 3 SR ADCn Status Register 0x24 32 read-write n 0x0 0xFFFFFFFF ABUSY ADC conversion busy flag 6 1 ADCH ADC channel bits of present operation 12 4 ADEND ADC End Flag 7 1 BIRQ ADC burst interrupt flag 2 1 BSTAT Burst mode operation count status 8 3 CIRQ ADC continuous interrupt flag 1 1 DMAIRQ DMA received/transfer is done 4 1 DOVRUN DMA overrun flag 5 1 MPWM0TRG MPWM0TRG 16 6 MPWM1TRG MPWM1TRG 24 6 SIRQ ADC single interrupt flag 0 1 TIRQ ADC Trigger interrupt flag 3 1 TRG Trigger event status 11 1 TRG0 ADC Trigger 0 Channel Register 0xC 32 read-write n 0x0 0xFFFFFFFF MP0TRG1 ADC channel n select for MPWM0 ADC trigger1 operation 0 4 MP0TRG2 ADC channel n select for MPWM0 ADC trigger2 operation 4 4 MP0TRG3 ADC channel n select for MPWM0 ADC trigger3 operation 8 4 MP0TRG4 ADC channel n select for MPWM0 ADC trigger4 operation 12 4 MP0TRG5 ADC channel n select for MPWM0 ADC trigger5 operation 16 4 MP0TRG6 ADC channel n select for MPWM0 ADC trigger6 operation 20 4 TRG0EN MP0TRGn enable 24 6 TRG1 ADC Trigger 1 Channel Register 0x10 32 read-write n 0x0 0xFFFFFFFF MP1TRG1 ADC channel n select for MPWM1 ADC trigger1 operation 0 4 MP1TRG2 ADC channel n select for MPWM1 ADC trigger2 operation 4 4 MP1TRG3 ADC channel n select for MPWM1 ADC trigger3 operation 8 4 MP1TRG4 ADC channel n select for MPWM1 ADC trigger4 operation 12 4 MP1TRG5 ADC channel n select for MPWM1 ADC trigger5 operation 16 4 MP1TRG6 ADC channel n select for MPWM1 ADC trigger6 operation 20 4 TRG1EN MP1TRGn enable 24 6 TRG2 ADC Trigger 2 Channel Register 0x14 32 read-write n 0x0 0xFFFFFFFF EXTCH ADC channel n select for external trigger operation 8 4 T0CH ADC channel n select for timer0 trigger operation 0 4 T1CH ADC channel n select for timer1 trigger operation 4 4 AFE ANALOG FRONT END AFE 0x4000B300 0x0 0x100 registers n COMP0 46 COMP1 47 COMP2 48 COMP3 49 CMP0CR Comparator 0 Control Register 0x20 32 read-write n 0x0 0xFF CINSEL Comparator input select 1 1 CMPEN Comparator enable(0)/disable(1) 4 1 REFSEL Comparator reference selection 0 1 CMP1CR Comparator 1 Control Register 0x24 32 read-write n 0x0 0xFF CINSEL Comparator input select 1 1 CMPEN Comparator enable 4 1 REFSEL Comparator reference selection 0 1 CMP2CR Comparator 2 Control Register 0x28 32 read-write n 0x0 0xFF CINSEL Comparator input select 1 1 CMPEN Comparator enable 4 1 REFSEL Comparator reference selection 0 1 CMP3CR Comparator 3 Control Register 0x2C 32 read-write n 0x0 0xFF CINSEL Comparator input select 1 1 CMPEN Comparator enable 4 1 REFSEL Comparator reference selection 0 1 CMPDBR Comparator de-bounce Register 0x30 32 read-write n 0x0 0xFFFFFFFF C0DBNC 0 C1DBNC 4 C2DBNC 8 C3DBNC Debouce shift selection 12 4 DBNCTB Debounce time base counter 16 8 CMPICR Comparator Interrupt Control Register 0x34 32 read-write n 0x0 0xFFFF C0IMOD 0 C1IMOD 2 C2IMOD 4 C3IMOD Comparator interrupt mode selection 6 2 read-write IPOL0 8 IPOL1 9 IPOL2 10 IPOL3 Comparator outs low/high IRQ selection 11 1 read-write PPOL0 12 PPOL1 13 PPOL2 14 PPOL3 Comparator outs for PWM invert selection 15 1 read-write CMPIER Comparator Interrupt Enable Register 0x38 32 read-write n 0x0 0xFF CMP0IE 0 CMP1IE 1 CMP2IE 2 CMP3IE Comparator Interrupt enable 3 1 read-write CMPSR Comparator Status Register 0x3C 32 read-write n 0x0 0xFFFF C0IRQ 0 C0OUT 8 C0RAW 12 C1IRQ 1 C1OUT 9 C1RAW 13 C2IRQ 2 C2OUT 10 C2RAW 14 C3IRQ Comparator interrupt flag 3 1 read-write C3OUT Comparator raw output after debounce 11 1 read-only C3RAW Comparator raw output before debounce 15 1 read-only OPA0CR OPAMP 0 Control Registers 0x0 32 read-write n 0x0 0xFF GAIN OPAMP Gain select 0 4 OPAEN OPAMP enable 4 1 OPA1CR OPAMP 1 Control Registers 0x4 32 read-write n 0x0 0xFF GAIN OPAMP Gain select 0 4 OPAEN OPAMP enable 4 1 OPA2CR OPAMP 2 Control Registers 0x8 32 read-write n 0x0 0xFF GAIN OPAMP Gain select 0 4 OPAEN OPAMP enable 4 1 OPA3CR OPAMP 3 Control Registers 0xC 32 read-write n 0x0 0xFF GAIN OPAMP Gain select 0 4 OPAEN OPAMP enable 4 1 DC0 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000400 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC1 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000410 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC10 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x400004A0 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC11 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x400004B0 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC12 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x400004C0 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC13 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x400004D0 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC14 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x400004E0 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC2 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000420 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC3 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000430 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC4 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000440 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC5 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000450 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC6 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000460 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC7 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000470 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC8 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000480 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC9 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000490 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR PAR 0 32 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only FM FLASH MEMORY CONTROLLER FMC 0x40000100 0x0 0x100 registers n AR Flash Memory Address Register 0xC 32 read-write n 0x0 0xFFFF FADDR 32K words address 0 15 BOOTCR Boot ROM Remap Clear Register 0x74 32 read-write n 0x1 0xFF BOOTROM Boot mode 0 1 CR Flash Memory Control Register 0x8 32 read-write n 0x82000000 0xFFFFFFFF AE All Erase 8 1 CLK3 flash access CLK 24 1 CLK4 flash access CLK 25 1 CRCEN CRC16 Enable 22 1 CRCINIT CRCINIT 23 1 ERS program mode/erase mode Enable 1 1 EVER Erase verify Mode 14 1 HRESPD HRESPD 31 1 OTPAE OTP area A enable 10 1 OTPBE OTP area B enable 11 1 PBLD page buffer load 3 1 PBR page buffer reset 0 1 PCLK2 PCLK=HCLK*1/2 27 1 PGM PGM 2 1 PMODE Pmode Enable 5 1 PVER Program verify mode 13 1 TEST TEST 16 2 TIMER program timer enable 20 1 TRIM TRIM 28 3 VPPOUT Charge pump Vpp Output 15 1 WE write Enable 4 1 CRC Flash Memory CRC value register 0x20 32 read-write n 0x0 0xFFFFFFFF CRC CRC16 Value 0 16 DR Flash Memory Data Register 0x10 32 read-write n 0x0 0xFFFFFFFF FDATA Flash PGM data 0 32 DRTY Flash Memory Dirty bit Register 0x18 32 write-only n 0x0 0xFFFFFFFF FDRTY Write any value,cache line fill falg will be cleared 0 32 MR Flash Memory Mode Register 0x4 32 read-write n 0x1000000 0x81C303FF ACODE Flash Mode/Trim Mode 0 8 read-write AMBAEN AMBA mode enable 22 1 read-write BOOT Boot Mode enable status 31 1 read-only FEMOD Flash Mode entry status 9 1 read-only FMOD Flash Mode status 8 1 read-only IDLE Idle mode enable status 24 1 read-only TRM Trim Mode status 16 1 read-only TRMEN Trim Mode entry status 17 1 read-only VERIFY Flash verify Mode enable status 23 1 read-only TICK Flash Memory Tick Timer register 0x1C 32 read-write n 0x0 0xFFFFFFFF FTICK TICK 0 18 TMR Flash Memory Timer Register 0x14 32 read-write n 0xBB 0x1FF TMR Erase/PGM timer 0 9 IC0 I2C Interface I2C 0x4000A000 0x0 0x100 registers n I2C0 36 CR I2C Control Register 0x14 32 read-write n 0x0 0xFF ACKEN ACK enabit bit in receiver mode 3 1 IIF Interrupt flag bit 7 1 INTEN Interrupt enable bit 4 1 SOFTRST Soft reset enable bit 5 1 START transmission start bit in master mode 0 1 STOP Stop enable bit 1 1 DR I2C Data Register 0x0 32 read-write n 0x0 0xFF DR Data 0 8 SAR I2C Slave Address Register 0xC 32 read-write n 0x0 0xFF GCEN general call enable bit 0 1 SVAD 7 bits slave address 1 7 SCLH I2C SCL HIGH duration Register 0x1C 32 read-write n 0xFFFF 0xFFFF SCLH SCL High duration value 0 16 SCLL I2C SCL LOW duration Register 0x18 32 read-write n 0xFFFF 0xFFFF SCLL SCL Low duration value 0 16 SDH SDA Hold Register 0x20 32 read-write n 0x0 0x7F SDH SDA Hold time 0 15 SR SR Status register 0x8 32 read-write n 0x0 0xFFFFFFFF BUSY busy flag 2 1 GCALL General call flag 7 1 MLOST Mastership lost flag 3 1 RXACK RX ack flag 0 1 SSEL slave flag 4 1 STOP Stop Flag 5 1 TEND 1 byte transmission complete flag 6 1 TMOD Transmit/reciever mode flag 1 1 IC1 I2C Interface I2C 0x4000A100 0x0 0x100 registers n I2C1 37 CR I2C Control Register 0x14 32 read-write n 0x0 0xFF ACKEN ACK enabit bit in receiver mode 3 1 IIF Interrupt flag bit 7 1 INTEN Interrupt enable bit 4 1 SOFTRST Soft reset enable bit 5 1 START transmission start bit in master mode 0 1 STOP Stop enable bit 1 1 DR I2C Data Register 0x0 32 read-write n 0x0 0xFF DR Data 0 8 SAR I2C Slave Address Register 0xC 32 read-write n 0x0 0xFF GCEN general call enable bit 0 1 SVAD 7 bits slave address 1 7 SCLH I2C SCL HIGH duration Register 0x1C 32 read-write n 0xFFFF 0xFFFF SCLH SCL High duration value 0 16 SCLL I2C SCL LOW duration Register 0x18 32 read-write n 0xFFFF 0xFFFF SCLL SCL Low duration value 0 16 SDH SDA Hold Register 0x20 32 read-write n 0x0 0x7F SDH SDA Hold time 0 15 SR SR Status register 0x8 32 read-write n 0x0 0xFFFFFFFF BUSY busy flag 2 1 GCALL General call flag 7 1 MLOST Mastership lost flag 3 1 RXACK RX ack flag 0 1 SSEL slave flag 4 1 STOP Stop Flag 5 1 TEND 1 byte transmission complete flag 6 1 TMOD Transmit/reciever mode flag 1 1 MP0 MOTOR PULSE-WIDTH-MODULATOR MPWM 0x40004000 0x0 0x1000 registers n MPWM0 24 MPWM0PROT 25 MPWM0OVV 26 ATCR MPWM ADC Trigger Control Register 0x54 32 read-write n 0x0 0xFFFF ATRGALL ADC Trigger register 0 match event 8 1 ATRGEN ADC Trigger Mode Enable 7 1 ATRGM ADC Trigger Mode 0 2 ATR1 MPWMn ADC Trigger Counter 1 Register 0x58 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR2 MPWMn ADC Trigger Counter 2 Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR3 MPWMn ADC Trigger Counter 3 Register 0x60 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR4 MPWMn ADC Trigger Counter 4 Register 0x64 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR5 MPWMn ADC Trigger Counter 5 Register 0x68 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR6 MPWMn ADC Trigger Counter 6 Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 CNT MPWM Counter Register 0x38 32 read-write n 0x0 0xFFFF CNT pwm counter value 0 16 CR1 MPWM Control Register 1 0x28 32 read-write n 0x0 0xFFFF HALT PWM HALT 0 1 INTVEN IRQ intervel mode 15 1 IRQMD IRQ mode 12 2 IRQN IRQ intervel Number 8 3 PWMEN PWM enable 7 1 CR2 MPWM Control Register 2 0x2C 32 read-write n 0x0 0xFF PSTART PWM start 0 1 DTR MPWM Dead Time Register 0x3C 32 read-write n 0x0 0xFFFF DT dead time value 0 8 DTCLK dead time clk select 8 1 DTEN dead time Enable 15 1 DUH MPWM Duty UH Register 0x10 32 read-write n 0x0 0xFFFF DUTY duty of UH output 0 16 DUL MPWM Duty UL Register 0x1C 32 read-write n 0x0 0xFFFF DUTY duty of UL output 0 16 DVH MPWM Duty VH Register 0x14 32 read-write n 0x0 0xFFFF DUTY duty of VH output 0 16 DVL MPWM Duty UL Register 0x20 32 read-write n 0x0 0xFFFF DUTY duty of VL output 0 16 DWH MPWM Duty WH Register 0x18 32 read-write n 0x0 0xFFFF DUTY duty of WH output 0 16 DWL MPWM Duty WL Register 0x24 32 read-write n 0x0 0xFFFF DUTY duty of WL output 0 16 IER MPWM Interrupt Enable Register 0x34 32 read-write n 0x0 0xFF BOTIE bottom interrupt enable 6 1 DUHIEN duty UH interrupt enable 5 1 DULIEN duty UL interrupt enable 4 1 DVHIEN duty VH interrupt enable 3 1 DVLIEN duty VL interrupt enable 2 1 DWHIEN duty WH interrupt enable 1 1 DWLIEN duty WL interrupt enable 0 1 PRDIEN Period interrupt enable 7 1 MR MPWM Mode Register 0x0 32 read-write n 0x0 0xFFFF FORCEN force mode 7 1 FORCM force mode 4 2 MCHMOD Motor control channel mode 12 2 MOTOR Normal/Motor mode 15 1 PDUP period duty update at .. 1 1 UALL Update all duty register 8 1 UPDATE update 9 1 UPDOWN PWM counter mode 0 1 OCR MPWM Output Control Register 0x8 32 read-write n 0x0 0xFF UHVAL PWM UH output control in force mode 5 1 ULVAL PWM UL output control in force mode 4 1 VHVAL PWM VH output control in force mode 3 1 VLVAL PWM VL output control in force mode 2 1 WHVAL PWM WH output control in force mode 1 1 WLEN PWM WL output control in force mode 0 1 OVCR MPWM Over Voltage control Register 0x48 32 read-write n 0x0 0xFFFFFFFF AD0IN ADC0 Comparator output 16 1 AD1IN ADC1 Comparator output 17 1 AD2IN ADC2 Comparator output 18 1 C0IN comparator 0 output 19 1 C1IN comparator 1 output 20 1 C2IN comparator 2 output 21 1 C3IN comparator 3 output 22 1 OVCLR OV protection clear 7 1 OVDBC OV voltage protection signal debounce 4 3 OVEN over voltage protection mode 15 1 OVIN ext OV pin input 23 1 OVSEL OV voltage proection mode select 0 2 OVSR MPWM Over Voltage Status Register 0x4C 32 read-write n 0x0 0xFF OVPIN Over voltage protection input status 0 1 OVSTAT Over voltage protection mode status 7 1 PCR MPWM Protection control Register 0x40 32 read-write n 0x0 0xFFFFFFFF AD0IN ADC0 Comparator output 16 1 AD1IN ADC1 Comparator output 17 1 AD2IN ADC2 Comparator output 18 1 C0IN comparator 0 output 19 1 C1IN comparator 1 output 20 1 C2IN comparator 2 output 21 1 C3IN comparator 3 output 22 1 PROTCLR protection clear 7 1 PROTDIS Protect mode disable 15 1 PRTIN External PRTIN pin input (active high) 23 1 PTDBC protection signal debounce 4 3 PTSEL protection mode sel 0 2 UHPROT UH protection output 13 1 ULPROT UL protection output 12 1 VHPROT VH protection output 11 1 VLPROT VL protection output 10 1 WHPROT WH protection output 9 1 WLPROT WL protection output 8 1 PMR MPWM Port Mode Register 0x4 32 read-write n 0x0 0xFFFF PMOD PWM pulse mode 8 2 POLUH Polarity of UH PIN 5 1 POLUL Polarity of UL PIN 4 1 POLVH Polarity of UH PIN 3 1 POLVL Polarity of UL PIN 2 1 POLWH Polarity of UH PIN 1 1 POLWL Polarity of UL PIN 0 1 PRD MPWM Period Register 0xC 32 read-write n 0x0 0xFFFF PERIOD PWM period 0 16 PSR MPWM Protection Status Register 0x44 32 read-write n 0x0 0xFFFFFFFF PROTEN Protection mode enable status 7 1 PROTIN Protection Input status 0 1 PROTPAT lock safety pattern to set or reset protection 16 16 SR MPWM Status Register 0x30 32 read-write n 0x0 0xFFFF BOTIRQ PWM bottom interrupt flag 6 1 DOWN PWM count up/down 15 1 DUHIRQ duty UH interrupt flag 5 1 DULIRQ duty UL interrupt flag 4 1 DVHIRQ duty VH interrupt flag 3 1 DVLIRQ duty VL interrupt flag 2 1 DWHIRQ duty WH interrupt flag 1 1 DWLIRQ duty WL interrupt flag 0 1 IRQCNT PWM count number of period match 12 3 PRDIRQ PWM period interrupt flag 7 1 MP1 MOTOR PULSE-WIDTH-MODULATOR MPWM 0x40005000 0x0 0x1000 registers n MPWM1 27 MPWM1PROT 28 MPWM1OVV 29 ATCR MPWM ADC Trigger Control Register 0x54 32 read-write n 0x0 0xFFFF ATRGALL ADC Trigger register 0 match event 8 1 ATRGEN ADC Trigger Mode Enable 7 1 ATRGM ADC Trigger Mode 0 2 ATR1 MPWMn ADC Trigger Counter 1 Register 0x58 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR2 MPWMn ADC Trigger Counter 2 Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR3 MPWMn ADC Trigger Counter 3 Register 0x60 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR4 MPWMn ADC Trigger Counter 4 Register 0x64 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR5 MPWMn ADC Trigger Counter 5 Register 0x68 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR6 MPWMn ADC Trigger Counter 6 Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 CNT MPWM Counter Register 0x38 32 read-write n 0x0 0xFFFF CNT pwm counter value 0 16 CR1 MPWM Control Register 1 0x28 32 read-write n 0x0 0xFFFF HALT PWM HALT 0 1 INTVEN IRQ intervel mode 15 1 IRQMD IRQ mode 12 2 IRQN IRQ intervel Number 8 3 PWMEN PWM enable 7 1 CR2 MPWM Control Register 2 0x2C 32 read-write n 0x0 0xFF PSTART PWM start 0 1 DTR MPWM Dead Time Register 0x3C 32 read-write n 0x0 0xFFFF DT dead time value 0 8 DTCLK dead time clk select 8 1 DTEN dead time Enable 15 1 DUH MPWM Duty UH Register 0x10 32 read-write n 0x0 0xFFFF DUTY duty of UH output 0 16 DUL MPWM Duty UL Register 0x1C 32 read-write n 0x0 0xFFFF DUTY duty of UL output 0 16 DVH MPWM Duty VH Register 0x14 32 read-write n 0x0 0xFFFF DUTY duty of VH output 0 16 DVL MPWM Duty UL Register 0x20 32 read-write n 0x0 0xFFFF DUTY duty of VL output 0 16 DWH MPWM Duty WH Register 0x18 32 read-write n 0x0 0xFFFF DUTY duty of WH output 0 16 DWL MPWM Duty WL Register 0x24 32 read-write n 0x0 0xFFFF DUTY duty of WL output 0 16 IER MPWM Interrupt Enable Register 0x34 32 read-write n 0x0 0xFF BOTIE bottom interrupt enable 6 1 DUHIEN duty UH interrupt enable 5 1 DULIEN duty UL interrupt enable 4 1 DVHIEN duty VH interrupt enable 3 1 DVLIEN duty VL interrupt enable 2 1 DWHIEN duty WH interrupt enable 1 1 DWLIEN duty WL interrupt enable 0 1 PRDIEN Period interrupt enable 7 1 MR MPWM Mode Register 0x0 32 read-write n 0x0 0xFFFF FORCEN force mode 7 1 FORCM force mode 4 2 MCHMOD Motor control channel mode 12 2 MOTOR Normal/Motor mode 15 1 PDUP period duty update at .. 1 1 UALL Update all duty register 8 1 UPDATE update 9 1 UPDOWN PWM counter mode 0 1 OCR MPWM Output Control Register 0x8 32 read-write n 0x0 0xFF UHVAL PWM UH output control in force mode 5 1 ULVAL PWM UL output control in force mode 4 1 VHVAL PWM VH output control in force mode 3 1 VLVAL PWM VL output control in force mode 2 1 WHVAL PWM WH output control in force mode 1 1 WLEN PWM WL output control in force mode 0 1 OVCR MPWM Over Voltage control Register 0x48 32 read-write n 0x0 0xFFFFFFFF AD0IN ADC0 Comparator output 16 1 AD1IN ADC1 Comparator output 17 1 AD2IN ADC2 Comparator output 18 1 C0IN comparator 0 output 19 1 C1IN comparator 1 output 20 1 C2IN comparator 2 output 21 1 C3IN comparator 3 output 22 1 OVCLR OV protection clear 7 1 OVDBC OV voltage protection signal debounce 4 3 OVEN over voltage protection mode 15 1 OVIN ext OV pin input 23 1 OVSEL OV voltage proection mode select 0 2 OVSR MPWM Over Voltage Status Register 0x4C 32 read-write n 0x0 0xFF OVPIN Over voltage protection input status 0 1 OVSTAT Over voltage protection mode status 7 1 PCR MPWM Protection control Register 0x40 32 read-write n 0x0 0xFFFFFFFF AD0IN ADC0 Comparator output 16 1 AD1IN ADC1 Comparator output 17 1 AD2IN ADC2 Comparator output 18 1 C0IN comparator 0 output 19 1 C1IN comparator 1 output 20 1 C2IN comparator 2 output 21 1 C3IN comparator 3 output 22 1 PROTCLR protection clear 7 1 PROTDIS Protect mode disable 15 1 PRTIN External PRTIN pin input (active high) 23 1 PTDBC protection signal debounce 4 3 PTSEL protection mode sel 0 2 UHPROT UH protection output 13 1 ULPROT UL protection output 12 1 VHPROT VH protection output 11 1 VLPROT VL protection output 10 1 WHPROT WH protection output 9 1 WLPROT WL protection output 8 1 PMR MPWM Port Mode Register 0x4 32 read-write n 0x0 0xFFFF PMOD PWM pulse mode 8 2 POLUH Polarity of UH PIN 5 1 POLUL Polarity of UL PIN 4 1 POLVH Polarity of UH PIN 3 1 POLVL Polarity of UL PIN 2 1 POLWH Polarity of UH PIN 1 1 POLWL Polarity of UL PIN 0 1 PRD MPWM Period Register 0xC 32 read-write n 0x0 0xFFFF PERIOD PWM period 0 16 PSR MPWM Protection Status Register 0x44 32 read-write n 0x0 0xFFFFFFFF PROTEN Protection mode enable status 7 1 PROTIN Protection Input status 0 1 PROTPAT lock safety pattern to set or reset protection 16 16 SR MPWM Status Register 0x30 32 read-write n 0x0 0xFFFF BOTIRQ PWM bottom interrupt flag 6 1 DOWN PWM count up/down 15 1 DUHIRQ duty UH interrupt flag 5 1 DULIRQ duty UL interrupt flag 4 1 DVHIRQ duty VH interrupt flag 3 1 DVLIRQ duty VL interrupt flag 2 1 DWHIRQ duty WH interrupt flag 1 1 DWLIRQ duty WL interrupt flag 0 1 IRQCNT PWM count number of period match 12 3 PRDIRQ PWM period interrupt flag 7 1 PA GENERAL PURPOSE I/O GPIO 0x40002000 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-write n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PB GENERAL PURPOSE I/O GPIO 0x40002100 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-write n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PC GENERAL PURPOSE I/O GPIO 0x40002200 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-write n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PCA PORT CONTROL UNIT PCU 0x40001000 0x0 0x100 registers n GPIOAE 16 GPIOAO 17 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCB PORT CONTROL UNIT PCU 0x40001100 0x0 0x100 registers n GPIOBE 18 GPIOBO 19 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCC PORT CONTROL UNIT PCU 0x40001200 0x0 0x100 registers n GPIOCE 20 GPIOCO 21 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCD PORT CONTROL UNIT PCU 0x40001300 0x0 0x100 registers n GPIODE 22 GPIODO 23 CR PORT n Pin Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PD GENERAL PURPOSE I/O GPIO 0x40002300 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-write n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PORTEN Port Access Eable PORTEN 0x40001FF0 0x0 0x10 registers n EN Port Access Eable 0x15->0x51 0x0 32 read-write n 0x0 0xFFFF SCU SYSTEM CONTROL UNIT SCU 0x40000000 0x0 0x100 registers n LVDDETECT 0 SYSCLKFAIL 1 XOSCFAIL 2 CIDR Chip ID Register 0x0 32 read-only n 0xAC338128 0xFFFFFFFF CMR Clock Monitoring Register 0x48 32 read-write n 0x3 0xFFFF EOSCFAIL external OSC failed flag 1 1 read-write EOSCIE external OSC failed interrupt enable 2 1 read-write EOSCMNT Externaler OSC monitor enable 3 1 read-write EOSCSTS external OSC status 0 1 read-write MCLKFAIL MCLK Failed flag 5 1 read-write MCLKIE MCLK fail Interrupt enable 6 1 read-write MCLKMNT MCLK monitor enable 7 1 read-write MCLKREC MCLK failed auto recovery 15 1 read-only MCLKSTS MCLK clock status 4 1 read-write COR Clock Output Register 0x50 32 read-write n 0xF 0xFF CLKODIV clock output divider value 0 4 read-write CLKOEN clock output enable 4 1 read-write CSCR Clock Source Control Register 0x40 32 read-write n 0x20 0xFF EOSCON External crystal OSC control 0 2 IOSCCON Internal OSC control 2 2 RINGOSCCON Internal ring OSC control 4 2 DBCLK1 Debounce Clock Control Register 1 0x9C 32 read-write n 0x10001 0xFFFFFFFF PADCSEL debouce clock for port A source clock sel 8 3 PADDIV PORT A debounce divider 0 8 PBDDIV PORT B debounce divider 16 8 PBDSEL debouce clock for port B source clock sel 24 3 DBCLK2 Debounce Clock Control Register 2 0xA0 32 read-write n 0x10001 0xFFFFFFFF PCDDIV PORT C debounce divider 0 8 PCDSEK debouce clock for port C source clock sel 8 3 PDDCSEL debouce clock for port D source clock sel 24 3 PDDDIV PORT D debounce divider 16 8 EMODR External Mode Status Register 0x84 32 read-write n 0x0 0xFFFFFFFF BOOT boot pin level 0 1 SCANMD scan mode pin level 2 1 TEST TEST PIN level 1 1 EOSCR External Oscillator Control Register 0x80 32 read-write n 0x300 0xFFFF AMPEN write enable for bit field AMPSEL 7 1 write-only AMPSEL Select AMP type 0 1 read-write ISEL select current 8 2 read-write ISELEN write enable for bit field ISEL 15 1 write-only IOSCTRIM Internal OSC Trim Register 0x6C 32 read-write n 0x0 0xFFFFFFFF LT interal oscillator LT trim value 10 4 LTEN LTEN 15 1 LTM interal oscillator LT trim value 8 2 TSL TSL 16 3 TSLEN TSLEN 23 1 UDCEN UDCEN 7 1 UDCH UDCH 3 2 UDCL UDCL 0 3 LVDCON LVD Control Register 0x68 32 read-write n 0x1 0xFFFFFFFF LVDEN LVD function enable 0 1 LVDLVL LVD Level state 1 1 read-only LVDSEL LVD detect level select 8 2 LVDTE LVDTRIM value write enable 23 1 write-only LVDTRIM LVD voltage level trim value 16 2 SELEN LVDSEL value write enable 15 1 write-only MCCR1 Miscellaneous Clock Control Register 1 0x90 32 read-write n 0x4040001 0xFFFFFFFF STCSEL systick clock source sel 8 3 read-write STDIV systick divider 0 8 read-write TRACEDIV TRACEDIV 16 8 read-write TRCPOL TRCPOL 31 1 write-only TRCSEL trace clock source sel 24 3 read-write MCCR2 Miscellaneous Clock Control Register 2 0x94 32 read-write n 0x0 0xFFFFFFFF PWM0CSEL pwm0 clock sel 8 3 PWM0DIV PWM0 divider 0 8 PWM1CSEL PWM1 clock sel 24 3 PWM1DIV pwm1 divider 16 8 MCCR3 Miscellaneous Clock Control Register 3 0x98 32 read-write n 0x10001 0xFFFFFFFF TEXT0CSEL text0 clock sel 24 3 TEXT0DIV text0 divider 16 8 WDTCSEL WDT clock sel 8 3 WDTDIV WDT divider 0 8 MCCR4 Miscellaneous Clock Control Register 4 0xA4 32 read-write n 0x1 0xFFFFFFFF ADCCDIV ADC Clock N divider 16 8 ADCCSEL ADC clock source select bitl 24 3 ETCDCSEL Debouce clock for ETC source clock sel 8 3 ETCDDIV ETC Debounce clock divider 0 8 NMIR NMI Control Register 0x4C 32 read-write n 0x0 0xFFFF NMIDBEN NMI Debounce enable 1 1 NMIEN NMIEN 0 1 NMIFLAG NMI interrupt flag 2 1 NMISTAT NMI Pin status 3 1 OPA0TRIM Internal OPAMP 0 Trim Register 0x70 32 read-write n 0x200 0xFFFFFFFF ABM OPAMP BIAS trim value 16 2 read-write ABMEN ABM trim value write enable 23 1 write-only ATRIM OPAMP VIO (offset) Trim 0 4 read-write ATRIMEN ATRIM value write enable 7 1 write-only GTRIM Opamp Gain Trim value 8 4 read-write GTRIMEN GTRIM value write enable 15 1 write-only OPA1TRIM Internal OPAMP 1 Trim Register 0x74 32 read-write n 0x200 0xFFFFFFFF ABM OPAMP BIAS trim value 16 2 read-write ABMEN ABM trim value write enable 23 1 write-only ATRIM OPAMP VIO (offset) Trim 0 4 read-write ATRIMEN ATRIM value write enable 7 1 write-only GTRIM Opamp Gain Trim value 8 4 read-write GTRIMEN GTRIM value write enable 15 1 write-only OPA2TRIM Internal OPAMP 2 Trim Register 0x78 32 read-write n 0x200 0xFFFFFFFF ABM OPAMP BIAS trim value 16 2 read-write ABMEN ABM trim value write enable 23 1 write-only ATRIM OPAMP VIO (offset) Trim 0 4 read-write ATRIMEN ATRIM value write enable 7 1 write-only GTRIM Opamp Gain Trim value 8 4 read-write GTRIMEN GTRIM value write enable 15 1 write-only OPA3TRIM Internal OPAMP 3 Trim Register 0x7C 32 read-write n 0x200 0xFFFFFFFF ABM OPAMP BIAS trim value 16 2 read-write ABMEN ABM trim value write enable 23 1 write-only ATRIM OPAMP VIO (offset) Trim 0 4 read-write ATRIMEN ATRIM value write enable 7 1 write-only GTRIM Opamp Gain Trim value 8 4 read-write GTRIMEN GTRIM value write enable 15 1 write-only PCER1 Peripheral Clock Enable Register 1 0x30 32 read-write n 0xF 0xFFFFFFFF DMA DMA Function Enable 4 1 GPIOA GPIOA 8 1 GPIOB GPIOB 9 1 GPIOC GPIOC 10 1 GPIOD GPIOD 11 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 17 1 TIMER2 TIMER2 18 1 TIMER3 TIMER3 19 1 TIMER8 TIMER8 Enable 24 1 TIMER9 TIMER9 Enable 25 1 PCER2 Peripheral Clock Enable Register 2 0x34 32 read-write n 0x101 0xFFFFFFFF ADC0 ADC0 20 1 ADC1 ADC1 21 1 ADC2 ADC2 22 1 AFE AFE 23 1 I2C0 I2C0 Enable 4 1 I2C1 I2C1 Enable 5 1 MPWM0 MPWM0 Enable 16 1 MPWM1 MPWM1 Enable 17 1 SPI0 SPI0 Enable 0 1 SPI1 SPI1 Enable 1 1 UART0 UART0 Enable 8 1 UART1 UART1 Enable 9 1 UART2 UART2 Enable 10 1 UART3 UART3 Enable 11 1 PER1 Peripheral Enable Register 1 0x28 32 read-write n 0xF 0xFFFFFFFF DMA DMA Function Enable 4 1 GPIOA GPIOA 8 1 GPIOB GPIOB 9 1 GPIOC GPIOC 10 1 GPIOD GPIOD 11 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 17 1 TIMER2 TIMER2 18 1 TIMER3 TIMER3 19 1 TIMER8 TIMER8 Enable 24 1 TIMER9 TIMER9 Enable 25 1 PER2 Peripheral Enable Register 2 0x2C 32 read-write n 0x101 0xFFFFFFFF ADC0 ADC0 20 1 ADC1 ADC1 21 1 ADC2 ADC2 22 1 AFE AFE 23 1 I2C0 I2C0 Enable 4 1 I2C1 I2C1 Enable 5 1 MPWM0 MPWM0 Enable 16 1 MPWM1 MPWM1 Enable 17 1 SPI0 SPI0 Enable 0 1 SPI1 SPI1 Enable 1 1 UART0 UART0 Enable 8 1 UART1 UART1 Enable 9 1 UART2 UART2 Enable 10 1 UART3 UART3 Enable 11 1 PLLCON PLL Control Register 0x60 32 read-write n 0x0 0xFFFF BYPASS FIN Bypass to FOUT 13 1 read-write FBCTRL Feedback control 4 4 read-write LOCKSTS PLL Lock state 12 1 read-only PLLEN PLL Enable 14 1 read-write PLLRSTB PLL reset 15 1 read-write POSTDIV post divider 0 4 read-write PREDIV FIN pre divider 8 1 read-write PRER1 Peripheral Reset Enable Register 1 0x20 32 read-write n 0x3FF0F1F 0xFFFFFFFF DMA DMA Reset 4 1 FMC Flash Memory controll Reset 1 1 GPIOA GPIOA Reset 8 1 GPIOB GPIOB Reset 9 1 GPIOC GPIOC Reset 10 1 GPIOD GPIOD Reset 11 1 PCU Port controll Reset 3 1 SCU Power Management Unit Reset 0 1 TIMER0 TIMER0 reset 16 1 TIMER1 TIMER1 Reset 17 1 TIMER2 TIMER2 Reset 18 1 TIMER3 TIMER3 Reset 19 1 TIMER8 TIMER8 Reset 24 1 TIMER9 TIMER9 Reset 25 1 WDT Watch Dog Timer Reset 2 1 PRER2 Peripheral Reset Enable Register 2 0x24 32 read-write n 0xF30F33 0xFFFFFFFF ADC0 ADC0 Reset 20 1 ADC1 ADC1 Reset 21 1 ADC2 ADC2 Reset 22 1 AFE AFE Reset 23 1 I2C0 I2C0 Reset 4 1 I2C1 I2C1 Reset 5 1 MPWM0 MPWM0 Reset 16 1 MPWM1 MPWM1 Reset 17 1 SPI0 SPI0 Reset 0 1 SPI1 SPI1 Reset 1 1 UART0 UART0 Reset 8 1 UART1 UART1 9 1 UART2 UART2 10 1 UART3 UART3 11 1 RSER Reset Source Enable Register 0x18 32 read-write n 0x49 0xFF CPURST CPU request reset enable 5 1 LVDRST LVD reset enable 0 1 MCKFRST MCLK failed reset enable 2 1 PINRST external pin reset enable 6 1 SWRST software reset enable 4 1 WDTRST watch dog reset enable 3 1 XFRST external OSC clock failed enable 1 1 RSSR Reset Source Status Register 0x1C 32 read-write n 0x80 0xFF CPURST cpu request reset status 5 1 LVDRST lvd reset status 0 1 MCKFRST MCLK failed reset status 2 1 PINRST extenral pin reset status 6 1 PORST power on reset status 7 1 SWRST software reset status 4 1 WDTRST watchdog timer reset status 3 1 XFRST clock failed reset status 1 1 SCCR System Clock Control Register 0x44 32 read-write n 0x0 0xFF FINSEL PLL Input source FIN Select 2 1 MCLKSEL System clock select 0 2 SMR System Mode Register 0x4 32 read-write n 0x0 0x30 PREVMODE PREVMODE 4 2 SRCR System Reset Control Register 0x8 32 read-write n 0x0 0x1 SWRST Internal soft reset activation 0 1 VDCCON VDC Control Register 0x64 32 read-write n 0xF 0xFFFFFFFF BMRTE Reference BGR Trim write enable 31 1 write-only BMRTRIM Reference BGR output voltage trim value 24 3 read-write VDCDE VDC Warm-up Delay value write enable 8 1 write-only VDCTE VDCTRIM Value write enable 23 1 write-only VDCTRIM VDC output voltage trim value 16 4 read-write VDCWDLY VDC warm up delay count 0 8 read-write WUER Wakeup Source Enable Register 0x10 32 read-write n 0x0 0xF03 GPIOAWUE GPIOAWUE 8 1 GPIOBWUE GPIOBWUE 9 1 GPIOCWUE GPIOCWUE 10 1 GPIODWUE GPIODWUE 11 1 LVDWUE LVDWUE 0 1 WDTWUE WDTWUE 1 1 WUSR Wakeup Source Status Register 0x14 32 read-only n 0x0 0xF03 GPIOAWU GPIOAWU 8 1 GPIOBWU GPIOBWU 9 1 GPIOCWU GPIOCWU 10 1 GPIODWU GPIODWU 11 1 LVDWU LVDWU 0 1 WDTWU WDTWU 1 1 SP0 SERIAL PERIPHERAL INTERFACE SPI 0x40009000 0x0 0x100 registers n SPI0 32 BR SPI n Baud Rate Register 0xC 32 read-write n 0x0 0xFFFF BR buadrate 0 16 CR SPI n Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF BITSZ Transmit/receive Data bits select bit 0 2 CPHA SPI clock phase bit 3 1 CPOL SPI clock polarity bit 2 1 LBE Loop-back mode select bit in master mode 11 1 MS master/slaver select bit 5 1 MSBF MSB/LSB transmit select bit 4 1 RXBC Recieve buffer clear bit 19 1 RXDIE DMA Rx Deone Interrupt enable bit 17 1 RXIE Receive interrupt enable bit 14 1 SSCIE SSn Edge Chagne Interrupt enable bit 16 1 SSMASK SS Signal masking bit in slave mode 10 1 SSMO SS output signal select bit 9 1 SSMOD SS Auto/Manual Output select bit 13 1 SSOUT SS output signal select bit 12 1 SSPOL SS Signal polarity select bit 8 1 TXBC TX Buffer clear bit 20 1 TXDIE DMA TX Done Interrupt enable bit 18 1 TXIE Transmit interrupt enable bit 15 1 EN SPI n Enable register 0x10 32 read-write n 0x0 0xFF ENABLE SPI ENABLE bit 0 1 LR SPI n delay Length Register 0x14 32 read-write n 0x10101 0xFFFFFFFF BTL Burst delay length 8 8 SPL Stop delay length 16 8 STL Start delay length 0 8 RDR SPI n Receive Data Register 0x0 32 read-only n 0x0 0x1FFFF RDR Data 0 17 SR SPI n Status Register 0x8 32 read-write n 0x0 0xFFFF OVRF receive overrun error flag 4 1 read-write RRDY receive buffer ready flag 0 1 read-only RXDMAF DMA receive Operation complete flag 8 1 read-write SSDET The rising edge of SS detect flag 6 1 read-write SSON SS signal status flag 5 1 read-write TRDY Transmit buffer empty flag 1 1 read-only TXDMAF DMA transmit Operation complete flag 9 1 read-write TXIDLE transmit/receive operation flag 2 1 read-only UDRF transmit underrun error flag 3 1 read-write TDR SPI n Transmit Data Register 0x0 32 write-only n 0x0 0x1FFFF TDR Data 0 17 SP1 SERIAL PERIPHERAL INTERFACE SPI 0x40009100 0x0 0x100 registers n SPI1 33 BR SPI n Baud Rate Register 0xC 32 read-write n 0x0 0xFFFF BR buadrate 0 16 CR SPI n Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF BITSZ Transmit/receive Data bits select bit 0 2 CPHA SPI clock phase bit 3 1 CPOL SPI clock polarity bit 2 1 LBE Loop-back mode select bit in master mode 11 1 MS master/slaver select bit 5 1 MSBF MSB/LSB transmit select bit 4 1 RXBC Recieve buffer clear bit 19 1 RXDIE DMA Rx Deone Interrupt enable bit 17 1 RXIE Receive interrupt enable bit 14 1 SSCIE SSn Edge Chagne Interrupt enable bit 16 1 SSMASK SS Signal masking bit in slave mode 10 1 SSMO SS output signal select bit 9 1 SSMOD SS Auto/Manual Output select bit 13 1 SSOUT SS output signal select bit 12 1 SSPOL SS Signal polarity select bit 8 1 TXBC TX Buffer clear bit 20 1 TXDIE DMA TX Done Interrupt enable bit 18 1 TXIE Transmit interrupt enable bit 15 1 EN SPI n Enable register 0x10 32 read-write n 0x0 0xFF ENABLE SPI ENABLE bit 0 1 LR SPI n delay Length Register 0x14 32 read-write n 0x10101 0xFFFFFFFF BTL Burst delay length 8 8 SPL Stop delay length 16 8 STL Start delay length 0 8 RDR SPI n Receive Data Register 0x0 32 read-only n 0x0 0x1FFFF RDR Data 0 17 SR SPI n Status Register 0x8 32 read-write n 0x0 0xFFFF OVRF receive overrun error flag 4 1 read-write RRDY receive buffer ready flag 0 1 read-only RXDMAF DMA receive Operation complete flag 8 1 read-write SSDET The rising edge of SS detect flag 6 1 read-write SSON SS signal status flag 5 1 read-write TRDY Transmit buffer empty flag 1 1 read-only TXDMAF DMA transmit Operation complete flag 9 1 read-write TXIDLE transmit/receive operation flag 2 1 read-only UDRF transmit underrun error flag 3 1 read-write TDR SPI n Transmit Data Register 0x0 32 write-only n 0x0 0x1FFFF TDR Data 0 17 T0 16-BIT TIMER TIMER 0x40003000 0x0 0x20 registers n TIMER0 5 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 T1 16-BIT TIMER TIMER 0x40003020 0x0 0x20 registers n TIMER1 6 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 T2 16-BIT TIMER TIMER 0x40003040 0x0 0x20 registers n TIMER2 7 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 T3 16-BIT TIMER TIMER 0x40003060 0x0 0x20 registers n TIMER3 8 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 T8 16-BIT TIMER TIMER 0x40003100 0x0 0x20 registers n TIMER8 13 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 T9 16-BIT TIMER TIMER 0x40003120 0x0 0x20 registers n TIMER9 14 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMOD clear select when capture mode 2 2 MODE Timer operatin mode control 0 2 STARTLVL STARTLVL 7 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0x77 MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 QDIRCHIE Quadrature decoder direction change interrupt enable 9 1 QRIE Quadrature decoder revolution interrupt enable 8 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x37 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 QDIR Quadrature direction flag 10 1 QDIRCH Quadrature direction change 9 1 QRF Quadrature revolution flag 8 1 TGECR Timer Group Encoder Control Register TGECR 0x40003140 0x0 0x10 registers n CR Timer Group Encoder Control Register 0x0 32 read-write n 0x0 0xFFFF ADIRCON PHASE A counter direction control 8 1 BDIRCON Phase B counter direction control 9 1 PDIRCON Position counter direction control 10 1 QDMOD Quadrature decoder mode 0 1 QDPHAEG Quadrature mode phase A count for position count 4 2 QDPHBEG Quadrature mode phase B count for position count 6 2 QDPHSWAP Quadrature mode phase Z count for Revolution 2 1 QDPHZEG Quadrature mode phase Z count for Revolution 3 1 RDIRCON Revolution counter direction control 11 1 U0 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008000 0x0 0x100 registers n UART0 38 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008100 0x0 0x100 registers n UART1 39 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U2 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008200 0x0 0x100 registers n UART2 40 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U3 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008300 0x0 0x100 registers n UART3 41 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF LBON Local loopback test mode enable 4 1 RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decied by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 IIR UART Interrupt ID Register 0x8 32 read-write n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 DR Data recevied 0 1 FE frame error 3 1 OE overrun error 1 1 PE parity error 2 1 TEMT Transmit empty 6 1 THRE Transmit holding register empty 5 1 RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 WDT WATCH-DOG TIMER WDT 0x40000200 0x0 0x100 registers n WDT 3 CNT Watchdog Timer Current Counter Register 0x4 32 read-write n 0xFFFF 0xFFFFFFFF CON Watchdog Timer Control Register 0x8 32 read-write n 0x805C 0xFFFF CKSEL WDTCLKIN clock source select 3 1 WDBG WDT operation in debug mode 15 1 WDTEN WDT counter enable 4 1 WDTIE WDT interrupt enable 7 1 WDTRE WDT interrupt reset 6 1 WPRS counter prescaler 0 3 WUF WDT underflow falg 8 1 LR Watchdog Timer Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF