RP2350A

Vendor Web: Raspberry Pi

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Name : RP2350A

max Clock : 150 MHz

RAM : 520 kB

description : Dual Cortex-M33 or Hazard3 processors at 150MHz 520kB on-chip SRAM, in 10 independent banks Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD 8kB of one-time-programmable storage (OTP) Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus Additional 16MB flash/PSRAM accessible via optional second chip-select On-chip switched-mode power supply to generate core voltage Low-quiescent-current LDO mode can be enabled for sleep states 2x on-chip PLLs for internal or external clock generation GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) Security features: Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP Protected OTP storage for optional boot decryption key Global bus filtering based on Arm or RISC-V security/privilege levels Peripherals, GPIOs and DMA channels individually assignable to security domains Hardware mitigations for fault injection attacks Hardware SHA-256 accelerator Peripherals: 2x UARTs 2x SPI controllers 2x I2C controllers 24x PWM channels USB 1.1 controller and PHY, with host and device support 12x PIO state machines 1x HSTX peripheral

Documentation

rp2350-datasheet.pdf
rp2350-datasheet.pdf online view

Architecture

Architecture : CM33 (CM33)

revision : r1p0

endian : little

Memory Protection Unit (MPU) : available

Floating Point Unit (FPU) : available

Number of relevant bits in Interrupt priority : 4

Peripherals

name : ACCESSCTRL
description : Hardware access control registers
base address : 0x0

name : ADC
description : Control and data interface to SAR ADC
base address : 0x0
Interrupt (35) ADC_IRQ_FIFO

name : BOOTRAM
description : Additional registers mapped adjacent to the bootram, for use by the bootrom.
base address : 0x0

name : BUSCTRL
description : Register block for busfabric control signals and performance counters
base address : 0x0

name : CLOCKS
base address : 0x0
Interrupt (30) CLOCKS_IRQ

name : CORESIGHT_TRACE
description : Coresight block - RP specific registers
base address : 0x0

name : DMA
description : DMA with separate read and write masters
base address : 0x0
Interrupt (10) DMA_IRQ_0
Interrupt (11) DMA_IRQ_1
Interrupt (12) DMA_IRQ_2
Interrupt (13) DMA_IRQ_3

name : EPPB
description : Cortex-M33 EPPB vendor register block for RP2350
base address : 0x0

name : GLITCH_DETECTOR
description : Glitch detector controls
base address : 0x0

name : HSTX_CTRL
description : Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block.
base address : 0x0

name : HSTX_FIFO
description : FIFO status and write access for HSTX
base address : 0x0

name : I2C0
description : DW_apb_i2c address block

List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header these are *fixed* values, set at hardware design time):

IC_ULTRA_FAST_MODE ................ 0x0
IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
IC_UFM_SCL_LOW_COUNT .............. 0x0008
IC_UFM_SCL_HIGH_COUNT ............. 0x0006
IC_TX_TL .......................... 0x0
IC_TX_CMD_BLOCK ................... 0x1
IC_HAS_DMA ........................ 0x1
IC_HAS_ASYNC_FIFO ................. 0x0
IC_SMBUS_ARP ...................... 0x0
IC_FIRST_DATA_BYTE_STATUS ......... 0x1
IC_INTR_IO ........................ 0x1
IC_MASTER_MODE .................... 0x1
IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
IC_INTR_POL ....................... 0x1
IC_OPTIONAL_SAR ................... 0x0
IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
IC_DEFAULT_SLAVE_ADDR ............. 0x055
IC_DEFAULT_HS_SPKLEN .............. 0x1
IC_FS_SCL_HIGH_COUNT .............. 0x0006
IC_HS_SCL_LOW_COUNT ............... 0x0008
IC_DEVICE_ID_VALUE ................ 0x0
IC_10BITADDR_MASTER ............... 0x0
IC_CLK_FREQ_OPTIMIZATION .......... 0x0
IC_DEFAULT_FS_SPKLEN .............. 0x7
IC_ADD_ENCODED_PARAMS ............. 0x0
IC_DEFAULT_SDA_HOLD ............... 0x000001
IC_DEFAULT_SDA_SETUP .............. 0x64
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
IC_CLOCK_PERIOD ................... 100
IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
IC_RESTART_EN ..................... 0x1
IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
IC_BUS_CLEAR_FEATURE .............. 0x0
IC_CAP_LOADING .................... 100
IC_FS_SCL_LOW_COUNT ............... 0x000d
APB_DATA_WIDTH .................... 32
IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
IC_SLV_DATA_NACK_ONLY ............. 0x1
IC_10BITADDR_SLAVE ................ 0x0
IC_CLK_TYPE ....................... 0x0
IC_SMBUS_UDID_MSB ................. 0x0
IC_SMBUS_SUSPEND_ALERT ............ 0x0
IC_HS_SCL_HIGH_COUNT .............. 0x0006
IC_SLV_RESTART_DET_EN ............. 0x1
IC_SMBUS .......................... 0x0
IC_OPTIONAL_SAR_DEFAULT ........... 0x0
IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
IC_USE_COUNTS ..................... 0x0
IC_RX_BUFFER_DEPTH ................ 16
IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
IC_RX_FULL_HLD_BUS_EN ............. 0x1
IC_SLAVE_DISABLE .................. 0x1
IC_RX_TL .......................... 0x0
IC_DEVICE_ID ...................... 0x0
IC_HC_COUNT_VALUES ................ 0x0
I2C_DYNAMIC_TAR_UPDATE ............ 0
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
IC_HS_MASTER_CODE ................. 0x1
IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
IC_SS_SCL_HIGH_COUNT .............. 0x0028
IC_SS_SCL_LOW_COUNT ............... 0x002f
IC_MAX_SPEED_MODE ................. 0x2
IC_STAT_FOR_CLK_STRETCH ........... 0x0
IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
IC_DEFAULT_UFM_SPKLEN ............. 0x1
IC_TX_BUFFER_DEPTH ................ 16
base address : 0x0
Interrupt (36) I2C0_IRQ

name : I2C1
description : DW_apb_i2c address block

List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header these are *fixed* values, set at hardware design time):

IC_ULTRA_FAST_MODE ................ 0x0
IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
IC_UFM_SCL_LOW_COUNT .............. 0x0008
IC_UFM_SCL_HIGH_COUNT ............. 0x0006
IC_TX_TL .......................... 0x0
IC_TX_CMD_BLOCK ................... 0x1
IC_HAS_DMA ........................ 0x1
IC_HAS_ASYNC_FIFO ................. 0x0
IC_SMBUS_ARP ...................... 0x0
IC_FIRST_DATA_BYTE_STATUS ......... 0x1
IC_INTR_IO ........................ 0x1
IC_MASTER_MODE .................... 0x1
IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
IC_INTR_POL ....................... 0x1
IC_OPTIONAL_SAR ................... 0x0
IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
IC_DEFAULT_SLAVE_ADDR ............. 0x055
IC_DEFAULT_HS_SPKLEN .............. 0x1
IC_FS_SCL_HIGH_COUNT .............. 0x0006
IC_HS_SCL_LOW_COUNT ............... 0x0008
IC_DEVICE_ID_VALUE ................ 0x0
IC_10BITADDR_MASTER ............... 0x0
IC_CLK_FREQ_OPTIMIZATION .......... 0x0
IC_DEFAULT_FS_SPKLEN .............. 0x7
IC_ADD_ENCODED_PARAMS ............. 0x0
IC_DEFAULT_SDA_HOLD ............... 0x000001
IC_DEFAULT_SDA_SETUP .............. 0x64
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
IC_CLOCK_PERIOD ................... 100
IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
IC_RESTART_EN ..................... 0x1
IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
IC_BUS_CLEAR_FEATURE .............. 0x0
IC_CAP_LOADING .................... 100
IC_FS_SCL_LOW_COUNT ............... 0x000d
APB_DATA_WIDTH .................... 32
IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
IC_SLV_DATA_NACK_ONLY ............. 0x1
IC_10BITADDR_SLAVE ................ 0x0
IC_CLK_TYPE ....................... 0x0
IC_SMBUS_UDID_MSB ................. 0x0
IC_SMBUS_SUSPEND_ALERT ............ 0x0
IC_HS_SCL_HIGH_COUNT .............. 0x0006
IC_SLV_RESTART_DET_EN ............. 0x1
IC_SMBUS .......................... 0x0
IC_OPTIONAL_SAR_DEFAULT ........... 0x0
IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
IC_USE_COUNTS ..................... 0x0
IC_RX_BUFFER_DEPTH ................ 16
IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
IC_RX_FULL_HLD_BUS_EN ............. 0x1
IC_SLAVE_DISABLE .................. 0x1
IC_RX_TL .......................... 0x0
IC_DEVICE_ID ...................... 0x0
IC_HC_COUNT_VALUES ................ 0x0
I2C_DYNAMIC_TAR_UPDATE ............ 0
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
IC_HS_MASTER_CODE ................. 0x1
IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
IC_SS_SCL_HIGH_COUNT .............. 0x0028
IC_SS_SCL_LOW_COUNT ............... 0x002f
IC_MAX_SPEED_MODE ................. 0x2
IC_STAT_FOR_CLK_STRETCH ........... 0x0
IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
IC_DEFAULT_UFM_SPKLEN ............. 0x1
IC_TX_BUFFER_DEPTH ................ 16
base address : 0x0
Interrupt (37) I2C1_IRQ

name : IO_BANK0
base address : 0x0
Interrupt (21) IO_IRQ_BANK0
Interrupt (22) IO_IRQ_BANK0_NS

name : IO_QSPI
base address : 0x0
Interrupt (23) IO_IRQ_QSPI
Interrupt (24) IO_IRQ_QSPI_NS

name : OTP
description : SNPS OTP control IF (SBPI and RPi wrapper control)
base address : 0x0
Interrupt (38) OTP_IRQ

name : OTP_DATA
description : Predefined OTP data layout for RP2350
base address : 0x0

name : OTP_DATA_RAW
description : Predefined OTP data layout for RP2350
base address : 0x0

name : PADS_BANK0
base address : 0x0

name : PADS_QSPI
base address : 0x0

name : PIO0
description : Programmable IO block
base address : 0x0
Interrupt (15) PIO0_IRQ_0
Interrupt (16) PIO0_IRQ_1

name : PIO1
description : Programmable IO block
base address : 0x0
Interrupt (17) PIO1_IRQ_0
Interrupt (18) PIO1_IRQ_1

name : PIO2
description : Programmable IO block
base address : 0x0
Interrupt (19) PIO2_IRQ_0
Interrupt (20) PIO2_IRQ_1

name : PLL_SYS
base address : 0x0
Interrupt (42) PLL_SYS_IRQ

name : PLL_USB
base address : 0x0
Interrupt (43) PLL_USB_IRQ

name : POWMAN
description : Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use
base address : 0x0
Interrupt (44) POWMAN_IRQ_POW
Interrupt (45) POWMAN_IRQ_TIMER

name : PPB
description : TEAL registers accessible through the debug interface
base address : 0x0

name : PPB_NS
description : TEAL registers accessible through the debug interface
base address : 0x0

name : PSM
base address : 0x0

name : PWM
description : Simple PWM
base address : 0x0
Interrupt (8) PWM_IRQ_WRAP_0
Interrupt (9) PWM_IRQ_WRAP_1

name : QMI
description : QSPI Memory Interface.

Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device.
base address : 0x0

name : RESETS
base address : 0x0

name : ROSC
base address : 0x0

name : SHA256
description : SHA-256 hash function implementation
base address : 0x0

name : SIO
description : Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.
base address : 0x0
Interrupt (25) SIO_IRQ_FIFO
Interrupt (26) SIO_IRQ_BELL
Interrupt (27) SIO_IRQ_FIFO_NS
Interrupt (28) SIO_IRQ_BELL_NS
Interrupt (29) SIO_IRQ_MTIMECMP

name : SIO_NS
description : Single-cycle IO block
Provides core-local and inter-core hardware for the two processors, with single-cycle access.
base address : 0x0
Interrupt (25) SIO_IRQ_FIFO
Interrupt (26) SIO_IRQ_BELL
Interrupt (27) SIO_IRQ_FIFO_NS
Interrupt (28) SIO_IRQ_BELL_NS
Interrupt (29) SIO_IRQ_MTIMECMP

name : SPI0
base address : 0x0
Interrupt (31) SPI0_IRQ

name : SPI1
base address : 0x0
Interrupt (32) SPI1_IRQ

name : SYSCFG
description : Register block for various chip control signals
base address : 0x0

name : SYSINFO
base address : 0x0

name : TBMAN
description : For managing simulation testbenches
base address : 0x0

name : TICKS
base address : 0x0

name : TIMER0
description : Controls time and alarms

time is a 64 bit value indicating the time since power-on

timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr

An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing
base address : 0x0
Interrupt (0) TIMER0_IRQ_0
Interrupt (1) TIMER0_IRQ_1
Interrupt (2) TIMER0_IRQ_2
Interrupt (3) TIMER0_IRQ_3

name : TIMER1
description : Controls time and alarms

time is a 64 bit value indicating the time since power-on

timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr

An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing
base address : 0x0
Interrupt (4) TIMER1_IRQ_0
Interrupt (5) TIMER1_IRQ_1
Interrupt (6) TIMER1_IRQ_2
Interrupt (7) TIMER1_IRQ_3

name : TRNG
description : ARM TrustZone RNG register block
base address : 0x0
Interrupt (39) TRNG_IRQ

name : UART0
base address : 0x0
Interrupt (33) UART0_IRQ

name : UART1
base address : 0x0
Interrupt (34) UART1_IRQ

name : USB
description : USB FS/LS controller device registers
base address : 0x0
Interrupt (14) USBCTRL_IRQ

name : USB_DPRAM
description : DPRAM layout for USB device.
base address : 0x0

name : WATCHDOG
base address : 0x0

name : XIP_AUX
description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access
base address : 0x0

name : XIP_CTRL
description : QSPI flash execute-in-place block
base address : 0x0

name : XOSC
description : Controls the crystal oscillator
base address : 0x0


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