max32650

Vendor Web: Maxim

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Name : max32650

Flash : 3072 kB

Flash bank : 0x300000 Bytes @ 0x10000000

RAM : 1024 kB

RAM : 0x00100000 Bytes @ 0x00100000

description : MAX32650 32-bit ARM Cortex-M4 microcontroller with 1MB of system RAM and 3MB of flash memory.

Architecture

Architecture : ARM Cortex-M4 (CM4)

revision : r2p1

endian : little

Memory Protection Unit (MPU) : available

Floating Point Unit (FPU) : available

Number of relevant bits in Interrupt priority : 3

Peripherals

name : ADC
description : 10-bit Analog to Digital Converter
base address : 0x0
Interrupt (20) ADC : ADC IRQ

name : AES_KEY
description : AES Keys.
base address : 0x0

name : BBFC
description : Battery-Backed Function Control.
base address : 0x0

name : BBSIR
description : Battery-Backed Registers.
base address : 0x0

name : CLCD
description : Color LCD Controller
base address : 0x0

name : CRYPTO
description : The Cryptographic Accelerator used to assist the computationally intensive operations of several common algorithms.
base address : 0x0
Interrupt (27) Crypto_Engine : Crypto Engine interrupt.

name : DMA
description : DMA Controller Fully programmable, chaining capable DMA channels.
base address : 0x0
Interrupt (28) DMA0 : DMA Channel 0 IRQ
Interrupt (29) DMA1 : DMA Channel 1 IRQ
Interrupt (30) DMA2 : DMA Channel 2 IRQ
Interrupt (31) DMA3 : DMA Channel 3 IRQ
Interrupt (68) DMA4 : DMA Channel 4 IRQ
Interrupt (69) DMA5 : DMA Channel 5 IRQ
Interrupt (70) DMA6 : DMA Channel 6 IRQ
Interrupt (71) DMA7 : DMA Channel 7 IRQ
Interrupt (72) DMA8 : DMA Channel 8 IRQ
Interrupt (73) DMA9 : DMA Channel 9 IRQ
Interrupt (74) DMA10 : DMA Channel 10 IRQ
Interrupt (75) DMA11 : DMA Channel 11 IRQ
Interrupt (76) DMA12 : DMA Channel 12 IRQ
Interrupt (77) DMA13 : DMA Channel 13 IRQ
Interrupt (78) DMA14 : DMA Channel 14 IRQ
Interrupt (79) DMA15 : DMA Channel 15 IRQ

name : EMCC
description : External Memory Cache Controller Registers.
base address : 0x0

name : FLC
description : Flash Memory Control.
base address : 0x0
Interrupt (23) Flash_Controller : Flash Controller interrupt.

name : GCR
description : Global Control Registers.
base address : 0x0

name : GPIO0
description : Individual I/O for each GPIO
base address : 0x0
Interrupt (24) GPIO0 : GPIO0 interrupt.

name : GPIO1
description : Individual I/O for each GPIO 1
base address : 0x0
Interrupt (25) GPIO1 : GPIO1 IRQ

name : GPIO2
description : Individual I/O for each GPIO 2
base address : 0x0
Interrupt (26) GPIO2 : GPIO2 IRQ

name : GPIO3
description : Individual I/O for each GPIO 3
base address : 0x0
Interrupt (58) GPIO3 : GPIO3 IRQ

name : HPB
description : HyperBus.
base address : 0x0
Interrupt (61) HPB : HPB Interrupt.

name : I2C0
description : Inter-Integrated Circuit.
base address : 0x0
Interrupt (13) I2C0 : I2C0 IRQ

name : I2C1
description : Inter-Integrated Circuit. 1
base address : 0x0
Interrupt (36) I2C1 : I2C1 IRQ

name : ICC0
description : Instruction Cache Controller Registers
base address : 0x0

name : ICC1
description : Instruction Cache Controller Registers 1
base address : 0x0

name : NBBFC
description : Non Battery-Backed Function Control.
base address : 0x0

name : OTP
description : One Time Programmable Memory controller.
base address : 0x0

name : OWM
description : 1-Wire Master Interface.
base address : 0x0
Interrupt (67) OneWire : 1-Wire IRQ

name : PT
description : Pulse Train
base address : 0x0

name : PT1
description : Pulse Train 1
base address : 0x0

name : PT10
description : Pulse Train 10
base address : 0x0

name : PT11
description : Pulse Train 11
base address : 0x0

name : PT12
description : Pulse Train 12
base address : 0x0

name : PT13
description : Pulse Train 13
base address : 0x0

name : PT14
description : Pulse Train 14
base address : 0x0

name : PT15
description : Pulse Train 15
base address : 0x0

name : PT2
description : Pulse Train 2
base address : 0x0

name : PT3
description : Pulse Train 3
base address : 0x0

name : PT4
description : Pulse Train 4
base address : 0x0

name : PT5
description : Pulse Train 5
base address : 0x0

name : PT6
description : Pulse Train 6
base address : 0x0

name : PT7
description : Pulse Train 7
base address : 0x0

name : PT8
description : Pulse Train 8
base address : 0x0

name : PT9
description : Pulse Train 9
base address : 0x0

name : PTG
description : Pulse Train Generation
base address : 0x0
Interrupt (59) PT : Pulse Train IRQ

name : PWRSEQ
description : Power Sequencer / Low Power Control Register.
base address : 0x0

name : RTC
description : Real Time Clock and Alarm.
base address : 0x0
Interrupt (3) RTC : RTC interrupt.

name : SDHC
description : SDHC/SDIO Controller
base address : 0x0
Interrupt (66) SDHC : SDHC IRQ

name : SDMA
description : Smart DMA
base address : 0x0
Interrupt (60) SmartDMA : Smart DMA interrupt.

name : SEMA
description : The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.
base address : 0x0

name : SIR
description : System Initialization Registers.
base address : 0x0

name : SMON
description : The Security Monitor block used to monitor system threat conditions.
base address : 0x0

name : SPI17Y
description : SPI peripheral.
base address : 0x0
Interrupt (16) SPI0 : SPI0 IRQ

name : SPI17Y1
description : SPI peripheral. 1
base address : 0x0
Interrupt (17) SPI17Y1 : SPI17Y1 IRQ

name : SPI17Y2
description : SPI peripheral. 2
base address : 0x0
Interrupt (18) SPI17Y2 : SPI17Y2 IRQ

name : SPID
description : SPID peripheral.
base address : 0x0

name : SPIMSS
description : Serial Peripheral Interface.
base address : 0x0

name : SPIXC_FIFO
description : SPI XiP Master Controller FIFO.
base address : 0x0

name : SPIXF
description : SPIXF Master
base address : 0x0

name : SPIXFC
description : SPI XiP Flash Configuration Controller
base address : 0x0
Interrupt (38) SPIXFC : SPIXFC IRQ

name : TMR0
description : 32-bit reloadable timer that can be used for timing and event counting.
base address : 0x0
Interrupt (5) TMR0 : TMR0 IRQ

name : TMR1
description : 32-bit reloadable timer that can be used for timing and event counting. 1
base address : 0x0
Interrupt (6) TMR1 : TMR1 IRQ

name : TMR2
description : 32-bit reloadable timer that can be used for timing and event counting. 2
base address : 0x0
Interrupt (7) TMR2 : TMR2 IRQ

name : TMR3
description : 32-bit reloadable timer that can be used for timing and event counting. 3
base address : 0x0
Interrupt (8) TMR3 : TMR3 IRQ

name : TMR4
description : 32-bit reloadable timer that can be used for timing and event counting. 4
base address : 0x0
Interrupt (9) TMR4 : TMR4 IRQ

name : TMR5
description : 32-bit reloadable timer that can be used for timing and event counting. 5
base address : 0x0
Interrupt (10) TMR5 : TMR5 IRQ

name : TRNG
description : Random Number Generator.
base address : 0x0
Interrupt (4) TRNG : TRNG interrupt.

name : UART0
description : UART
base address : 0x0
Interrupt (14) UART0 : UART0 IRQ

name : UART1
description : UART 1
base address : 0x0
Interrupt (15) UART1 : UART1 IRQ

name : UART2
description : UART 2
base address : 0x0
Interrupt (34) UART2 : UART2 IRQ

name : USBHS
description : USB 2.0 High-speed Controller.
base address : 0x0
Interrupt (2) USB : USB IRQ

name : WDT0
description : Watchdog Timer 0
base address : 0x0
Interrupt (1) WDT0 : WDT0 IRQ

name : WDT1
description : Watchdog Timer 0 1
base address : 0x0
Interrupt (57) WDT1 : WDT1 IRQ


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