nuvoTon DTS_ISD91500_EN_A1_0_20200713 2024.04.29 DTS_ISD91500_EN_A1_0_20200713 SVD file 8 32 ANA ANA Register Map ANA 0x0 0x0 0x8 registers n MICBCTR ANA_MICBCTR Microphone Bias Control Register 0x4 -1 read-write n 0x0 0x0 MICBEN MICBIAS enable 0: Disable MIC_BIAS 1: Enable MIC_BIAS 0 1 read-write MICBMODE Select Reference Source For MICBIAS Generator VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used as reference. 3 1 read-write 0 VMID ( VCCA/2) is reference source. MICBIAS output ratio of VCCA #0 1 VBG (bandgap voltage reference) is reference source. MICBIAS output fixed DC voltage #1 MICBVSEL Select Microphone Bias Voltage 0: 2.4V 1: 1.7V 2: 2.0V 3: 1.3V 1 2 read-write VMID ANA_VMID VMID Reference Control Register 0x0 -1 read-write n 0x0 0x0 VMIDHPD VMIDH Pulldown 0 1 read-write 0 Release VMIDH pin for reference operation #0 1 Pull VMIDH pin to ground. Default power down and reset condition #1 VMIDHRH Power Down VMIDH High (360kΩ) Resistance Reference 2 1 read-write 0 Connect the High Resistance reference to VMIDH. Use this setting for minimum power consumption #0 1 The High Resistance reference is disconnected from VMIDH. Default power down and reset condition #1 VMIDHRL Power Down VMIDH Low (4.8kΩ) Resistance Reference 1 1 read-write 0 Connect the Low Resistance reference to VMIDH. Use this setting for fast power up of VMIDH. Can be turned off after 50ms to save power #0 1 The Low Resistance reference is disconnected from VMIDH. Default power down and reset condition #1 VMIDLPD VMIDH Pulldown 4 1 read-write 0 Release VMIDL pin for reference operation #0 1 Pull VMIDL pin to ground. Default power down and reset condition #1 VMIDLRH Power Down VMIDL High (360kΩ) Resistance Reference 6 1 read-write 0 Connect the High Resistance reference to VMIDL. Use this setting for minimum power consumption #0 1 The High Resistance reference is disconnected from VMIDL. Default power down and reset condition #1 VMIDLRL Power Down VMIDL Low (4.8kΩ) Resistance Reference 5 1 read-write 0 Connect the Low Resistance reference to VMIDL. Use this setting for fast power up of VMIDH. Can be turned off after 50ms to save power #0 1 The Low Resistance reference is disconnected from VMIDL. Default power down and reset condition #1 BIQ BIQ Register Map BIQ 0x0 0x0 0x78 registers n 0x80 0x8 registers n COEFF0 BIQ_COEFF0 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 1st Stage BIQ Coefficients 0x0 -1 read-write n 0x0 0x0 COEFFDAT Coefficient Data 0 32 read-write COEFF1 BIQ_COEFF1 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 1st Stage BIQ Coefficients 0x4 -1 read-write n 0x0 0x0 COEFF10 BIQ_COEFF10 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 3rd Stage BIQ Coefficients 0x28 -1 read-write n 0x0 0x0 COEFF11 BIQ_COEFF11 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 3rd Stage BIQ Coefficients 0x2C -1 read-write n 0x0 0x0 COEFF12 BIQ_COEFF12 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 3rd Stage BIQ Coefficients 0x30 -1 read-write n 0x0 0x0 COEFF13 BIQ_COEFF13 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 3rd Stage BIQ Coefficients 0x34 -1 read-write n 0x0 0x0 COEFF14 BIQ_COEFF14 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 3rd Stage BIQ Coefficients 0x38 -1 read-write n 0x0 0x0 COEFF15 BIQ_COEFF15 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 4st Stage BIQ Coefficients 0x3C -1 read-write n 0x0 0x0 COEFF16 BIQ_COEFF16 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 4st Stage BIQ Coefficients 0x40 -1 read-write n 0x0 0x0 COEFF17 BIQ_COEFF17 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 4st Stage BIQ Coefficients 0x44 -1 read-write n 0x0 0x0 COEFF18 BIQ_COEFF18 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 4st Stage BIQ Coefficients 0x48 -1 read-write n 0x0 0x0 COEFF19 BIQ_COEFF19 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 4st Stage BIQ Coefficients 0x4C -1 read-write n 0x0 0x0 COEFF2 BIQ_COEFF2 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 1st Stage BIQ Coefficients 0x8 -1 read-write n 0x0 0x0 COEFF20 BIQ_COEFF20 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 5nd Stage BIQ Coefficients 0x50 -1 read-write n 0x0 0x0 COEFF21 BIQ_COEFF21 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 5nd Stage BIQ Coefficients 0x54 -1 read-write n 0x0 0x0 COEFF22 BIQ_COEFF22 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 5nd Stage BIQ Coefficients 0x58 -1 read-write n 0x0 0x0 COEFF23 BIQ_COEFF23 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 5nd Stage BIQ Coefficients 0x5C -1 read-write n 0x0 0x0 COEFF24 BIQ_COEFF24 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 5nd Stage BIQ Coefficients 0x60 -1 read-write n 0x0 0x0 COEFF25 BIQ_COEFF25 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 6rd Stage BIQ Coefficients 0x64 -1 read-write n 0x0 0x0 COEFF26 BIQ_COEFF26 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 6rd Stage BIQ Coefficients 0x68 -1 read-write n 0x0 0x0 COEFF27 BIQ_COEFF27 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 6rd Stage BIQ Coefficients 0x6C -1 read-write n 0x0 0x0 COEFF28 BIQ_COEFF28 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 6rd Stage BIQ Coefficients 0x70 -1 read-write n 0x0 0x0 COEFF29 BIQ_COEFF29 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 6rd Stage BIQ Coefficients 0x74 -1 read-write n 0x0 0x0 COEFF3 BIQ_COEFF3 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 1st Stage BIQ Coefficients 0xC -1 read-write n 0x0 0x0 COEFF4 BIQ_COEFF4 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 1st Stage BIQ Coefficients 0x10 -1 read-write n 0x0 0x0 COEFF5 BIQ_COEFF5 Coefficient B0 in H(z) Transfer Function (3.16 Format) - 2nd Stage BIQ Coefficients 0x14 -1 read-write n 0x0 0x0 COEFF6 BIQ_COEFF6 Coefficient B1 in H(z) Transfer Function (3.16 Format) - 2nd Stage BIQ Coefficients 0x18 -1 read-write n 0x0 0x0 COEFF7 BIQ_COEFF7 Coefficient B2 in H(z) Transfer Function (3.16 Format) - 2nd Stage BIQ Coefficients 0x1C -1 read-write n 0x0 0x0 COEFF8 BIQ_COEFF8 Coefficient A1 in H(z) Transfer Function (3.16 Format) - 2nd Stage BIQ Coefficients 0x20 -1 read-write n 0x0 0x0 COEFF9 BIQ_COEFF9 Coefficient A2 in H(z) Transfer Function (3.16 Format) - 2nd Stage BIQ Coefficients 0x24 -1 read-write n 0x0 0x0 CTL BIQ_CTL BIQ Control Register 0x80 -1 read-write n 0x0 0x0 BIQEN BIQ Filter Start to Run 0 1 read-write 0 BIQ filter is not processing #0 1 BIQ filter is on #1 DLCOEFF Move BIQ Out of Reset State 3 1 read-write 0 BIQ filter is in reset state #0 1 When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on #1 HPFON High Pass Filter On Note : If this register is on, BIQ only 5 stage left. SDADC path sixth stage coefficient is for HPF filter coefficient. DAC path first stage coefficient is for HPF filter coefficient. 1 1 read-write 0 disable high pass filter #0 1 enable high pass filter #1 PATHSEL AC Path Selection for BIQ 2 1 read-write 0 used in SDADC path #0 1 used in DAC path #1 PRGCOEFF Programming Mode Coefficient Control Bit This bit must be turned off when BIQEN in on. 7 1 read-write 0 Coefficient RAM is in normal mode #0 1 coefficient RAM is under programming mode #1 SDADCWNSR SDADC Down Sample 001--- 1x (no down sample) 010 --- 2x 011 --- 3x 100 --- 4x 11 0--- 6x Others reserved 4 3 read-write STAGE BIQ Stage Number Control 11 1 read-write 0 6 stage #0 1 5 stage #1 STS BIQ_STS BIQ Status Register 0x84 -1 read-write n 0x0 0x0 BIST1D RAM BIST1 testing DONE flag for internal use 2 1 read-write BIST1EN RAM BIST1 testing Enable for internal use (Only test load coeficient and verify) 0 1 read-write BIST1F RAM BIST1 testing FAILED indicator for internal use 1 1 read-write BIST2D RAM BIST2 testing DONE flag for internal use 10 1 read-write BIST2EN RAM BIST2 testing Enable for internal use (Test RAM write/read with several values) 8 1 read-write BIST2F RAM BIST2 testing FAILED indicator for internal use 9 1 read-write RAMINITF Coefficient Ram Initial Default Done Flag 31 1 read-write 0 initial default value done #0 1 still working on #1 CLK CLK Register Map CLK 0x0 0x0 0x34 registers n 0x38 0x4 registers n 0xB4 0x4 registers n 0xF0 0x4 registers n AHBCLK CLK_AHBCLK AHB Device Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CPDCKEN Companding Clock Enable Control 1 1 read-write 0 Companding engine clock Disabled #0 1 Companding engine clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Control. The Flash ISP engine clock always is from 49 MHz RC oscillator. 2 1 read-write 0 Flash ISP engine clock Disabled #0 1 Flash ISP engine clock Enabled #1 PDMACKEN PDMA Clock Enable Control 0 1 read-write 0 PDMA engine clock Disabled #0 1 PDMA engine clock Enabled #1 APBCLK CLK_APBCLK APB Device Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ANAEN Analog Block Clock Enable Control 31 1 read-write 0 Analog block clock Disabled #0 1 Analog block clock Enabled #1 BIQEN Biquad Filter(BIQ) Block Clock Enable Control 18 1 read-write 0 BIQ clock Disabled #0 1 BIQ clock Enabled #1 DACEN DAC Clock Enable Control 29 1 read-write 0 DAC clock Disabled #0 1 DAC clock Enabled #1 I2C0EN I2C0 Clock Enable Control 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 I2C1EN I2C1 Clock Enable Control 9 1 read-write 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 I2SEN I2S Clock Enable Control 13 1 read-write 0 I2S clock Disabled #0 1 I2S clock Enabled #1 PWM0EN PWM0 Block Clock Enable Control 20 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1EN PWM1 Block Clock Enable Control 21 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 SARADCEN Analog-Digital-Converter (SARADC) Clock Enable Control 28 1 read-write 0 SARADC clock Disabled #0 1 SARADC clock Enabled #1 SDADCEN SDADC Clock Enable Control 30 1 read-write 0 SDADC clock Disabled #0 1 SDADC clock Enabled #1 SPI0EN SPI0 Clock Enable Control 12 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 SPI1EN SPI1 Clock Enable Control 11 1 read-write 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 TMR0EN Timer0 Clock Enable Control 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1EN Timer1 Clock Enable Control 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2EN Timer2 Clock Enable Control 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 UART0EN UART0 Block Clock Enable Control 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1EN UART1 Block Clock Enable Control 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 USBEN USB Clock Enable Control 24 1 read-write 0 USB clock Disabled #0 1 USB clock Enabled #1 WDTEN Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. 0 1 read-write 0 WDT clock Disabled #0 1 WDT clock Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x18 -1 read-write n 0x0 0x0 HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write SARADCDIV SARADC Clock Divide Number From ADC Clock Source 16 7 read-write UART0DIV UART0 Clock Divide Number From UART0 Clock Source Note: UART0 engine clock must smaller or equal to PCLK. 4 4 read-write UART1DIV UART1 Clock Divide Number From UART1 Clock Source Note: UART1 engine clock must smaller or equal to PCLK. 8 4 read-write USBDIV USB Clock Divide Number From PLL Clock 12 4 read-write CLKDIV1 CLK_CLKDIV1 Clock Divider Number Register 1 0x1C -1 read-write n 0x0 0x0 BIQDIV BIQ Clock Divide Number From HCLK Note: BIQ clock frequency must keep PCLK/2 8 4 read-write DACDIV DAC Clock Divide Number From DAC Clock Source 0 8 read-write SDADCDIV SDADC Clock Divide Number From SDADC Clock Source 16 8 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 FCLK_MUX_STATE These register state shows the current HCLK is from which source clock Others reserved. 16 3 read-write 0 clock source from HXT #000 1 clock source from PLLFOUT #001 2 clock source from LIRC #010 3 clock source from HIRC #011 HCLKSEL HCLK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 0 2 read-write 0 clock source from HXT #00 1 clock source from PLLFOUT #01 2 clock source from LIRC #10 3 clock source from HIRC #11 OSCFSEL HIRC Frequency Selection register These bits are protected, to write to bits first perform the unlock sequence (see Register Lock Control Register (SYS_REGLCTL)) 6 2 read-write 0 Trim for 49.152MHz@VCC=3.3V selected #00 1 Trim for 49.152MHz@VCC=1.8V selected. Trim for 48MHz@VCC=3.3V selected #01 STICKSEL SYS_TICK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 3. SysTick clock source must less than or equal to HCLK/2. 3 2 read-write 0 clock source from HXT #00 1 clock source from HXT/2 #01 2 clock source from HCLK/2 #10 3 clock source from HIRC/2 #11 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 I2SSEL I2S Clock Source Select 20 3 read-write 0 Clock source from HXT #000 1 Clock source from PLLFOUT #001 2 Clock source from PCLK #010 3 Clock source from HIRC #011 4 Clock source from MCLKI #100 5 Clock source from XCLK #101 PWM0SEL PWM Timer Clock Source Select 28 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from PCLK #10 3 Clock source from HIRC #11 PWM1SEL PWM Timer Clock Source Select 30 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from PCLK #10 3 Clock source from HIRC #11 SARADCSEL SARADC Clock Source Select 2 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from PCLK #10 3 Clock source from HIRC #11 SPI0SEL SPI0 Clock Source Select Note: SPI0 engine clock must be same clock source as PCLK 4 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from PCLK #10 3 Clock source from HIRC #11 SPI1SEL SPI1 Clock Source Select Note: SPI1 engine clock must be same clock source as PCLK 6 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from PCLK #10 3 Clock source from HIRC #11 TMR0SEL Timer0 Clock Source Select 8 3 read-write 0 Clock source from HXT #000 1 Clock source from PCLK #001 2 Clock source from External Trigger #010 3 Clock source from LIRC #011 4 Clock source from HIRC #100 TMR1SEL Timer1 Clock Source Select 12 3 read-write 0 Clock source from HXT #000 1 Clock source from PCLK #001 2 Clock source from External Trigger #010 3 Clock source from LIRC #011 4 Clock source from HIRC #100 TMR2SEL Timer2 Clock Source Select 16 3 read-write 0 Clock source from HXT #000 1 Clock source from PCLK #001 2 Clock source from External Trigger #010 3 Clock source from LIRC #011 4 Clock source from HIRC #100 UART0SEL UART0 Clock Source Select 24 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from HIRC #10 3 Clock source from HIRC #11 UART1SEL UART1 Clock Source Select 26 2 read-write 0 Clock source from HXT #00 1 Clock source from PLLFOUT #01 2 Clock source from HIRC #10 3 Clock source from HIRC #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.. 0 1 read-write 0 Clock source from LIRC #0 1 Clock source from HCLK/2048 #1 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x28 -1 read-write n 0x0 0x0 DACSEL DAC Clock Source Select 8 3 read-write 0 Clock source from HXT #000 1 Clock source from PLLFOUT #001 2 Clock source from PCLK #010 3 Clock source from HIRC #011 4 Clock source from MCLKI #100 5 Clock source from XCLK #101 SDADCSEL SDADC Clock Source Select 12 3 read-write 0 Clock source from HXT #000 1 Clock source from PLLFOUT #001 2 Clock source from PCLK #010 3 Clock source from HIRC #011 4 Clock source from MCLKI #100 5 Clock source from XCLK #101 USBSEL USB Clock Source Select 0 1 read-write 0 Clock source from HIRC #0 1 Clock source from PLLFOUT #1 XCLKSEL Clock Doubler Source Selection 4 1 read-write 0 Clock source from MCLK input (MCLKI) #0 1 Clock source from BCLK of I2S (I2S_BCLK) #1 DPDFLR CLK_DPDFLR DPD State Register and Flash Regulator Control 0xC -1 read-write n 0x0 0x0 PD_STATE An 8bit register that is preserved when DPD (Deep Power Down) state is entered and after wakeup is available by reading PD_STATE_RB. 0 8 read-write PD_STATE_RB Current values of PD_STATE register. 8 8 read-write HXTFSEL CLK_HXTFSEL HXT Filter Select Control Register 0xB4 -1 read-write n 0x0 0x0 HXTFSEL HXT Filter Select Note: This bit is auto cleared by hardware. 0 1 read-write 0 HXT frequency is > 12 MHz #0 1 HXT frequency is <= 12 MHz #1 HXTGEN HXT output gating enable 1 1 read-write 0 Gating HXT output disable #0 1 Gating HXT output enable #1 PFLAG CLK_PFLAG Power Down Flag Register 0x24 -1 read-write n 0x0 0x0 DSF Deep Sleep Flag This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag. 0 1 read-write STOPF Stop Flag This flag is set if core logic was stopped but not powered down. Write '1' to clear flag. 1 1 read-write PLLCTL CLK_PLLCTL PLL Control Register 0x30 -1 read-write n 0x0 0x0 BP PLL Bypass Control (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 6 read-write FTREN Fliter Enable Control 22 1 read-write 0 Disable Filter #0 1 Enable Filter #1 INDIV PLL Input Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 9 4 read-write OE PLL OE (FOUT Enable) Pin Control (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control (Write Protected) Refer to the formulas below the table. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 14 2 read-write PD Power-down Mode (Write Protected) If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in Power-down mode (default) #1 PLLSRC PLL Source Clock Selection (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 19 2 read-write 0 PLL source clock from external high-speed crystal oscillator (HXT) #00 1 PLL source clock from clock doubler output (XCLK) #01 2 Reserved. Do not use #10 3 PLL source clock from internal high-speed oscillator (HIRC) #11 STBSEL PLL Stable Counter Selection (Write Protected) Note: This bit is write protected. Refer to the SYS_REGLCTL register. 23 1 read-write 0 PLL stable time is 1293 PLL source clock (suitable for source clock is equal to or less than 12 MHz) #0 1 PLL stable time is 5044 PLL source clock (suitable for source clock is larger than 12 MHz) #1 PLLTEST CLK_PLLTEST PLL TEST Control Register 0x38 -1 read-write n 0x0 0x0 ICP PLL charge Pump Current (Write Protect) Adjust PLL charge pump current by these register. Default value is 0x1. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 4 read-write ICPMIS PLL charge Pump Current Mismatch Compensation Selection (Write Protect) Compensation PLL charge pump current mismatch by these registers. Default value is 0x0. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 8 4 read-write IVCO VCO Current Current (Write Protect) Control VCO current. Default value is 0x0. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 16 2 read-write PWRCTL CLK_PWRCTL System Power Control Register 0x0 -1 read-write n 0x0 0x0 CLKRDDLY Enable the Clock Ready Delay Counter When HXT enable, the clock control will delay certain clock cycles to wait clock stable. The delayed clock cycle is 4096 clock cycles when external high speed crystal oscillator (HXT) enable. 8 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 DPDEN Deep Power Down (DPD) bit. Set to '1' and issue WFI/WFE instruction to enter DPD mode. 10 1 read-write FLASHEN Determine whether FLASH memory enters deep power down. If FLASHEN is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence. Trade-off is wakeup time for standby power. 18 2 read-write FWKEN STOP/DeepSleep mode fast wakeup enable control Note: Normal wake up will count 2 LIRC first, and then switch to original HCLK source. Fast wakeup will direct switch to original HCLK source without any LIRC counting. 0 1 read-write 0 Normal wake up #0 1 Fast wake up (default) #1 HIRCEN Internal high speed RC Oscillator Control After reset, this bit is 1 . 2 1 read-write 0 Internal high speed oscillation Disabled #0 1 Internal high speed oscillation Enabled #1 HXTEN External high speed Crystal Oscillator Control After reset, this bit is 0 . 1 1 read-write 0 External high speed crystal oscillation Disabled #0 1 External high speed crystal oscillation Enabled #1 HXTGAIN HXT Gain Control Bit This is a protected register. Please refer to open lock sequence to program it. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. 3 3 read-write 0 HXT frequency is from 1 MHz to4 MHz #000 1 HXT frequency is from 4 MHz to 8 MHz #001 2 HXT frequency is from 8 MHz to 12 MHz #010 3 HXT frequency is from 12 MHz to 16 MHz #011 4 HXT frequency is higher than 16 MHz #100 HXTTBEN HXT Crystal TURBO Mode (Write Protect) This is a protected register. Please refer to open lock sequence to program it. 6 1 read-write 0 HXT Crystal TURBO mode disabled #0 1 HXT Crystal TURBO mode enabled #1 IOFWK All IO pin is enabled fast wakeup in STOP/DeepSleep mode. When this bit set 0'b, trigger IO will delay 3 LIRC and then trigger wakeup from STOP/DeepSleep mode. When this bit set 1'b, trigger IO will wakeup from STOP/DeepSleep mode immediately. 7 1 read-write 0 Slow wakeup #0 1 Fast wakeup #1 LIRCEN Internal 10kHz Oscillator Control After reset, this bit is 0 . 12 1 read-write 0 Internal 10 KHz oscillator Disabled #0 1 Internal 10 KHz oscillator Enabled #1 SELWKTMR Select WAKEUP Timer: 20 3 read-write 0 Time-out interval is 128 LIRC clocks (About 12.8 ms) #000 1 Time-out interval is 256 LIRC clocks (About 25.6 ms) #001 2 Time-out interval is 512 LIRC clocks (About 51.2 ms) #010 3 Time-out interval is 1024 LIRC clocks (About 102.4ms) #011 4 Time-out interval is 4096 LIRC clocks (About 409.6ms) #100 5 Time-out interval is 8192 LIRC clocks (About 819.2ms) #101 6 Time-out interval is 16384 LIRC clocks (About 1638.4ms) #110 7 Time-out interval is 65536 LIRC clocks (About 6553.6ms) #111 STOPEN STOP mode bit. Set to '1' and issue WFI/WFE instruction to enter STOP mode. 9 1 read-write TMRWKF Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10Khz oscillator. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC [10:8]) are cleared. 25 1 read-write VSET Adjusts the digital supply voltage. Should be left as default. 13 3 read-write WK10KEN Determines whether OSC10K is enabled in DPD mode. Note: If WK10KEN is disabled, device cannot wake from DPD with SELWKTMR delay. 17 1 read-write 0 Enabled in DPD #0 1 Disabled in DPD #1 WKPINEN Determines whether WAKEUP pin(PA15) is enabled in DPD mode. 16 1 read-write 0 Enabled #0 1 Disabled #1 WKPINWKF Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC[10:8]) are cleared. 24 1 read-write WKPUEN Wakeup Pin Pull-up Control This signal is latched in deep power down and preserved. 27 1 read-write 0 pull-up enable #0 1 tri-state (default) #1 WKTMRSTS Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode. 28 4 read-write STATUS CLK_STATUS Clock Status Monitor Register 0x20 -1 read-only n 0x0 0x0 HIRCSTB HIRC clock source stable flag(Read only) 2 1 read-only 0 Internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 Internal high speed RC oscillator (HIRC) clock is stable and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 External high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 External high speed crystal oscillator (HXT) clock is stabled and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 1 1 read-only 0 Internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 Internal low speed RC oscillator (LIRC) clock is stable and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only) 3 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 XCLKSTB XCLK Clock Source Stable Flag (Read Only) 4 1 read-only 0 Clock doubler (XCLK) clock is not stable or disabled #0 1 Clock doubler (XCLK) clock is stable and enabled #1 TESTCLK CLK_TESTCLK TEST Clock Control Register 0xF0 -1 read-write n 0x0 0x0 TCLKSEL Test Clock Source Selection 0 3 read-write 0 HCLK #000 1 HIRC #001 2 HXT #010 3 LIRC #011 4 PLLFout #100 5 XCLK #101 TESTCKDIV Test Clock Output Divider 8 3 read-write 0 Test clock divide by 1 #000 1 Test clock divide by 2 #001 2 Test clock divide by 4 #010 3 Test clock divide by 8 #011 4 Test clock divide by 16 #100 5 Test clock divide by 32 #101 6 Test clock divide by 64 #110 TESTEN Test Clock Output Enable Bit Test clock will output through PD0 pin 7 1 read-write 0 Test clock function Disable #0 1 Test clock function Enable #1 XCLKCTL CLK_XCLKCTL Clock Doubler Output Control Register 0x2C -1 read-write n 0x0 0x0 RELOCK XCLK relock enable setting When write this bit to 1'b, the XCLK will execute relock action. And this bit will auto clear to 0'b after relock finish and XCLK output clock stable. 5 1 read-write XCLKEN XCLK Enable Bit 4 1 read-write 0 Clock doubler (XCLK) Disabled #0 1 Clock doubler (XCLK) Enabled #1 XCLKFDEN XCLK Clock Fail Detector Enable Bit 12 1 read-write 0 Clock doubler clock (XCLK) fail detector Disabled #0 1 Clock doubler clock (XCLK) fail detector Enabled #1 XCLKFIEN XCLK Clock Fail Interrupt Enable Bit 13 1 read-write 0 Clock doubler clock (XCLK) fail interrupt Disabled #0 1 Clock doubler clock (XCLK) fail interrupt Enabled #1 XCLKFIF XCLK Clock Fail Interrupt Flag Note: Write 1 to clear the bit to 0. 14 1 read-write 0 Clock doubler clock (XCLK) clock is normal #0 1 Clock doubler clock (XCLK) stops #1 XCLKMUL Clock doubler Output Frequency Multiplication 0 2 read-write 0 Output frequency multiply by 1 (Bypass) #00 1 Output frequency multiply by 2 #01 2 Output frequency multiply by 4 #10 3 Output frequency multiply by 8 #11 CPD CPD Register Map CPD 0x0 0x0 0x18 registers n CTRL CPD_CTRL CPD Control Register 0x0 -1 read-write n 0x0 0x0 BITRATE CPD ADPCM bitrate select 4 2 read-write 0 16K bit/s (2 bits per sample) 0 1 24K bit/s (3 bits per sample) 1 2 32K bit/s (4 bits per sample) 2 3 40K bit/s (5 bits per sample) 3 DECRST Decoder reset register Write 1 to this bit will reset decoder state machine and clear input/output FIFO. This bit will auto change to 0 after reset done. 9 1 read-write DITH Decoder input FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to DITH (CPD_CTRL[26:24]) setting, the DITHIF (CPD_STS[19]) will set to 1, else the DITHIF (CPD_STS[19]) will be cleared to 0. 24 3 read-write DITHIE Decoder input FIFO Threshold Interrupt 27 1 read-write 0 Decoder input FIFO threshold interrupt Disabled #0 1 Decoder input FIFO threshold interrupt Enabled #1 DOTH Decoder output FIFO Threshold Level If the valid data count of the FIFO data buffer is larger than or equal to DOTH (CPD_CTRL[30:28]) setting, the DOTHIF (CPD_STS[27]) will set to 1, else the DOTHIF (CPD_STS[27]) will be cleared to 0. 28 3 read-write DOTHIE Decoder output FIFO Threshold Interrupt 31 1 read-write 0 Decoder output FIFO threshold interrupt Disabled #0 1 Decoder output FIFO threshold interrupt Enabled #1 EITH Encoder input FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to EITH (CPD_CTRL[18:16]) setting, the EITHIF (CPD_STS[3]) will set to 1, else the DITHIF (CPD_STS[3]) will be cleared to 0. 16 3 read-write EITHIE Encoder input FIFO Threshold Interrupt 19 1 read-write 0 Encoder input FIFO threshold interrupt Disabled #0 1 Encoder input FIFO threshold interrupt Enabled #1 EN CPD enable control 0 1 read-write 0 CPD disable #0 1 CPD enable #1 ENCRST Encoder reset register Write 1 to this bit will reset encoder state machine and clear input/output FIFO. This bit will auto change to 0 after reset done. 8 1 read-write EOTH Encoder output FIFO Threshold Level If the valid data count of the FIFO data buffer is larger than or equal to EOTH (CPD_CTRL[22:20]) setting, the EOTHIF (CPD_STS[11]) will set to 1, else the EOTHIF (CPD_STS[11]) will be cleared to 0. 20 3 read-write EOTHIE Encoder output FIFO Threshold Interrupt 23 1 read-write 0 Encoder output FIFO threshold interrupt Disabled #0 1 Encoder output FIFO threshold interrupt Enabled #1 LAW CPD A-law / u-law select 3 1 read-write 0 u-law #0 1 A-law #1 MODE CPD encode/decode algorithm select 1 1 read-write 0 ADPCM (G.726) #0 1 A-law / u-law (G.711) #1 TYPE CPD encoder input and decoder output type select 2 1 read-write 0 A-law / u-law #0 1 PCM #1 DECIN CPD_DECIN CPD Decoder Input FIFO 0x10 -1 write-only n 0x0 0x0 DECIN CPD decoder input FIFO By writing to this register, decoder input data will be pushed onto the transmit FIFO. CPD will start encoding if this FIFO is not empty. 0 8 write-only DECOUT CPD_DECOUT CPD Decoder Output FIFO 0x14 -1 read-only n 0x0 0x0 DECOUT CPD decoder output FIFO Reading this register will return data from decoder output data FIFO. 0 16 read-only ENCIN CPD_ENCIN CPD Encoder Input FIFO 0x8 -1 write-only n 0x0 0x0 ENCIN CPD encoder input FIFO By writing to this register, encoder input data will be pushed onto the transmit FIFO. CPD will start encoding if this FIFO is not empty. 0 16 write-only ENCOUT CPD_ENCOUT CPD Encoder Output FIFO 0xC -1 read-only n 0x0 0x0 ENCOUT CPD encoder output FIFO Reading this register will return data from encoder output data FIFO. 0 8 read-only STS CPD_STS CPD FIFO Status Register 0x4 -1 read-write n 0x0 0x0 DIE CPD decoder input FIFO empty flag 17 1 read-write 0 CPD decoder input FIFO is NOT empty #0 1 CPD decoder input FIFO is empty #1 DIF CPD decoder input FIFO full flag 16 1 read-write 0 CPD decoder input FIFO is NOT full #0 1 CPD decoder input FIFO is full #1 DIFPTR CPD decoder input FIFO Pointer (Read Only) The FULL (CPD_STS[16]) and FIFOPTR (CPD_STS[23:20]) indicates the field that the valid data count within the decoder input FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of decoder input FIFO buffer equal to 8, The FULL (CPD_STS[16]) is set to 1. 20 4 read-only DIOV CPD decoder input FIFO overflow flag If decoder input FIFO (CPD->CPD_DEC_IN) is full, and an additional data is written to the FIFO, an overflow condition will occur and set this bit to logic 1. 18 1 read-write DITHIF CPD decoder input FIFO Threshold Interrupt Status (Read Only) 19 1 read-only 0 The valid data count within the FIFO data buffer is more than the setting value of DITH (CPD_CTL[26:24]) #0 1 The valid data count within the FIFO data buffer is less than or equal to the setting value of DITH (CPD_CTL[26:24]) #1 DOE CPD decoder output FIFO empty flag 25 1 read-write 0 CPD decoder output FIFO is NOT empty #0 1 CPD decoder output FIFO is empty #1 DOF CPD decoder output FIFO full flag 24 1 read-write 0 CPD decoder output FIFO is NOT full #0 1 CPD decoder output FIFO is full #1 DOFPTR CPD decoder output FIFO Pointer (Read Only) The FULL (CPD_STS[24]) and FIFOPTR (CPD_STS[31:28]) indicates the field that the valid data count within the Decoder output FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of decoder output FIFO buffer equal to 8, The FULL (CPD_STS[24]) is set to 1. 28 4 read-only DOOV CPD decoder output FIFO overflow flag If decoder output FIFO (CPD->CPD_DEC_OUT) is full, and an additional converted data is written to the FIFO, an overflow condition will occur and set this bit to logic 1. 26 1 read-write DOTHIF CPD decoder output FIFO Threshold Interrupt Status (Read Only) 27 1 read-only 0 The valid data count within the FIFO data buffer is less than the setting value of DOTH (CPD_CTL[30:28]) #0 1 The valid data count within the FIFO data buffer is more than or equal to the setting value of DOTH (CPD_CTL[30:28]) #1 EIE CPD encoder input FIFO empty flag 1 1 read-write 0 CPD encoder input FIFO is NOT empty #0 1 CPD encoder input FIFO is empty #1 EIF CPD encoder input FIFO full flag 0 1 read-write 0 CPD encoder input FIFO is NOT full #0 1 CPD encoder input FIFO is full #1 EIFPTR CPD encoder input FIFO Pointer (Read Only) The FULL (CPD_STS[0]) and FIFOPTR (CPD_STS[7:4]) indicates the field that the valid data count within the encoder input FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of encoder input FIFO buffer equal to 8, The FULL (CPD_STS[0]) is set to 1. 4 4 read-only EIOV CPD encoder input FIFO overflow flag If encoder input FIFO (CPD->CPD_ENC_IN) is full, and an additional data is written to the FIFO, an overflow condition will occur and set this bit to logic 1. 2 1 read-write EITHIF CPD encoder input FIFO Threshold Interrupt Status (Read Only) 3 1 read-only 0 The valid data count within the FIFO data buffer is more than the setting value of EITH (CPD_CTL[18:16]) #0 1 The valid data count within the FIFO data buffer is less than or equal to the setting value of EITH (CPD_CTL[18:16]) #1 EOE CPD encoder output FIFO empty flag 9 1 read-write 0 CPD encoder output FIFO is NOT empty #0 1 CPD encoder output FIFO is empty #1 EOF CPD encoder output FIFO full flag 8 1 read-write 0 CPD encoder output FIFO is NOT full #0 1 CPD encoder output FIFO is full #1 EOFPTR CPD encoder output FIFO Pointer (Read Only) The FULL (CPD_STS[8]) and FIFOPTR (CPD_STS[15:12]) indicates the field that the valid data count within the encoder output FIFO buffer. The maximum value shown in FIFOPTR is 8. When the using level of encoder output FIFO buffer equal to 8, The FULL (CPD_STS[8]) is set to 1. 12 4 read-only EOOV CPD encoder output FIFO overflow flag If encoder output FIFO (CPD->CPD_ENC_OUT) is full, and an additional converted data is written to the FIFO, an overflow condition will occur and set this bit to logic 1. 10 1 read-write EOTHIF CPD encoder output FIFO Threshold Interrupt Status (Read Only) 11 1 read-only 0 The valid data count within the FIFO data buffer is less than the setting value of EOTH (CPD_CTL[22:20]) #0 1 The valid data count within the FIFO data buffer is more than or equal to the setting value of EOTH (CPD_CTL[22:20]) #1 DAC DAC Register Map DAC 0x0 0x0 0x1C registers n 0x200 0x10 registers n 0x300 0x8 registers n ANA0 DAC_ANA0 DAC Analog Block Control Register 0 0x300 -1 read-write n 0x0 0x0 BV1P5 HP output Volume Control 0 6 read-write CAPV1P5 Bypass cap setting 6 2 read-write 0 0C(default) #00 1 1C #01 2 2C #10 3 3C #11 CKDLYV1P5 Delay clock choice for DAC 8 3 read-write 0 clk_3(default) #000 1 clk_4 #001 2 clk_5 #010 3 clk_6 #011 4 clk_7 #100 5 clk_0 #101 6 clk_1 #110 7 clk_2 #111 CLKINV Clock input inverse 15 1 read-write 0 not inverse(default) #0 1 inverse #1 IBADJV1P5 BIAS current adjust control 11 2 read-write 0 20uA(default) #00 1 25uA #01 2 17uA #10 3 10.8uA #11 VREFSEL DAC Vref select control 13 2 read-write 0 vccx(default) #00 1 2.2V(@VCC=3.3V) #01 2 2.4V(@VCC=3.3V) #10 3 2.6V(@VCC=3.3V) #11 ANA1 DAC_ANA1 DAC Analog Block Control Register 1 0x304 -1 read-write n 0x0 0x0 ENCLK1 Left channel DAC clock enable control 0 1 read-write 0 Disable(default) #0 1 Enable #1 ENCLK2 Right channel DAC clock enable control 1 1 read-write 0 Disable(default) #0 1 Enable #1 ENDAC1 Left channel DAC enable control 2 1 read-write 0 Disable(default) #0 1 Enable #1 ENDAC2 Right channel DAC enable control 3 1 read-write 0 Disable(default) #0 1 Enable #1 ENHP1 Left channel headphone driver block enable control 4 2 read-write 0 Disable(default) #00 ENHP2 Right channel headphone driver block enable control 6 2 read-write 0 Disable(default) #00 PDBDAC1 Left DAC power down control 17 1 read-write 0 power off(default) #0 1 power on #1 PDBDAC2 Right DAC power down control 18 1 read-write 0 power off(default) #0 1 power on #1 PDBIAS 13 2 read-write 3 (default) #11 PDBIAS2 15 2 read-write 3 (default) #11 PDFLITSM1 Left channel smooth filter block power down control 8 1 read-write 0 power on #0 1 power down(default) #1 PDFLITSM2 Right channel smooth filter block power down control 9 1 read-write 0 power on #0 1 power down(default) #1 PDIBGEN IBGEN block power down control 12 1 read-write 0 power on #0 1 power off(default) #1 PDVBUF1 Left channel VMID buffer block power down control 10 1 read-write 0 power on #0 1 power off(default) #1 PDVBUF2 Right channel VMID buffer block power down control 11 1 read-write 0 power on #0 1 power off(default) #1 TEST Test mode enable 23 1 read-write 0 Disable (default) #0 1 Enable #1 TESTDACIN DAC input while in active mode 24 2 read-write 0 (default) #00 VOLEN1 Left volume enable control 19 1 read-write 0 Disable(default)(Connect to VMID) #0 1 Enable (Connect to signal) #1 VOLEN2 Right volume enable control 20 1 read-write 0 Disable(default)(Connect to VMID) #0 1 Enable (Connect to signal) #1 VOLMUTE Volume mute control 21 1 read-write 0 mute(default) #0 1 unmute #1 VROI VROI Control(for pop control) 22 1 read-write 0 (default) #0 CTL0 DAC_CTL0 DAC Control Register 0 0x4 -1 read-write n 0x0 0x0 CLKSET Working Clock Selection 31 1 read-write 0 the sampling rate is DACCLK/512 #0 1 the sampling rate is DACCLK/500 #1 FCLR FIFO Clear Note 1: To clear the FIFO, need to write FCLR (DAC_CTL[29:28]) to 11b, and can read the EMPTY (DAC_FIFOSTS[1]) bit to make sure that the FIFO has been cleared. Note 2: This field is auto cleared by hardware. 28 2 read-write 3 Clear the FIFO #11 FIFOEN DAC FIFO enable control 6 2 read-write 0 FIFO disable #00 3 FIFO enable #11 FIFOWIDTH FIFO Data Width This bit field is used to define the bit-width of data word and valid bits in register DAC_DAT. 0 2 read-write 0 The bit-width of data word is 32-bit, valid bits is DAC_DAT[31:0] #00 1 The bit-width of data word is 16-bit, valid bits is DAC_DAT[15:0] #01 2 The bit-width of data word is 8-bit, valid bits is DAC_DAT[7:0] #10 3 The bit-width of data word is 24-bit, valid bits is DAC_DAT[23:0] #11 MODESEL Data Control in FIFO 4 2 read-write 0 Data is stereo format #00 1 Data is monaural format #01 SWRST State Machine Software Reset 30 1 read-write 0 State Machine normal operation #0 1 State Machine Reset #1 TH FIFO Threshold Level If the valid data count of the FIFO data buffer is less than or equal to TH (DAC_CTL[16:12]) setting, the THIF (DAC_FIFOSTS[2]) will set to 1, else the THIF (DAC_FIFOSTS[2]) will be cleared to 0. 12 5 read-write THIE FIFO Threshold Interrupt 11 1 read-write 0 FIFO threshold interrupt Disabled #0 1 FIFO threshold interrupt Enabled #1 CTL1 DAC_CTL1 DAC Control Register 1 0x200 -1 read-write n 0x0 0x0 DACENL SDMOD enable control for left channel 0 1 read-write DACENR SDMOD enable control for right channel 1 1 read-write DACOSR128 DAC Oversample Rate 128 Selection 14 1 read-write DACOSR256 DAC Oversample Rate 256 Selection 15 1 read-write DACOSR32 DAC Oversample Rate 32 Selection 13 1 read-write DEMDITHER DEM dither control Set Probability of DEM Dithering Set probability of first order DEM dithering. Each level increments probability by 1/16 7 4 read-write 0 No dithering #0000 1 1/16 #0001 2 2/16 #0010 15 15/16 #1111 DISDEM Disable DEM (dynamic element matching) 17 1 read-write 0 Enable #0 1 Disable #1 MIPS500 12 1 read-write OSR100 11 1 read-write SDDITHER SDMOD dither control Number of bits of dithering on SD Modulator . Each level increments dithering by 1 bit 2 5 read-write 0 No Dithering 0000 1 1 0001 1111 15 1111 CTL12 DAC_CTL12 DAC Control Register 12 (All Reserved) 0x208 -1 read-write n 0x0 0x0 ACLKSEL Analog DAC clock source selection 2 1 read-write 0 provide engine clock for analog DAC #0 1 provide data clock for analog DAC #1 CTL2 DAC_CTL2 DAC Control Register 2 0x204 -1 read-write n 0x0 0x0 CICCLPOFF Digital filter control ??? 16 1 read-write CICGADJ DAC Output Fine Tuning 17 3 read-write CICIADJ Digital filter control ??? 0 16 read-write CLKSYNC Keep dault 21 1 read-write COFFSEL Digital filter control ??? 20 1 read-write SDSEL Digital filter control ??? 24 8 read-write CTL3 DAC_CTL3 DAC Control Register 3 0x20C -1 read-write n 0x0 0x0 DACENSM DACEN Soft Mute enable DAC volume ramping up of a channel on a rising edge of when it turned on. 3 1 read-write 0 Disable #0 1 Enable #1 SMCTL Soft mute control 0 1 read-write 0 Gradually increase DAC volume to volume register setting #0 1 Gradually decrease DAC volume to zero #1 UNMUTECTL Power-up soft unmute control 1 2 read-write 0 No soft digital unmute on PWRUPEN and MUTEB events #00 1 512 MCLK per step soft unmute #01 3 32 MCLK per step soft unmute #11 ZCEN DAC zero cross enable 4 1 read-write 0 Disable #0 1 Enable #1 DAT DAC_DAT DAC FIFO Data Write Register 0x0 -1 read-write n 0x0 0x0 FIFO FIFO Data Input Register DAC contains 32 words (32x32 bit) data buffer for data transmit. A write to this register pushes data onto the FIFO data buffer and increments the write pointer. This is the address that CPU/PDMA writes audio data to. The remaining word number is indicated by FIFOPTR (DAC_FIFOSTS[9:4]). 0 32 read-write DVOL DAC_DVOL DAC Digital Volume Control Register 0x8 -1 read-write n 0x0 0x0 DACLVOL DACL Digital Volume Control Register Note: Volume per step 0.5dB 0 8 read-write 0 Mute 0x00 1 Reserved 0x01 82 Reserved 0x52 83 -80dB 0x53 242 -0.5dBdB 0xf2 243 0dB 0xf3 254 +5.5dB 0xfe 255 +6dB 0xff DACRVOL DACR Digital Volume Control Register Note: Volume per step 0.5dB 8 8 read-write 0 Mute 0x00 1 Reserved 0x01 82 Reserved 0x52 83 -80dB 0x53 242 -0.5dBdB 0xf2 243 0dB 0xf3 254 +5.5dB 0xfe 255 +6dB 0xff FIFOSTS DAC_FIFOSTS DAC FIFO Status Register 0xC -1 read-write n 0x0 0x0 BISTEN BIST Enable(internal use) Bit[30]: Interpolator RAM BIST Mode control Bit[29]: FIFO BIST Mode control Note: FIFO can be testing by Cortex-M0 29 2 read-write 0 Disable BIST testing 0 1 Enable BIST testing 1 EMPTY FIFO Empty (Read Only) 1 1 read-only 0 FIFO is not empty #0 1 FIFO is empty #1 FIFOEND FIFO TEST Finish flag 13 1 read-write 0 is not finishing, if set BISTEN[0] to 1 #0 1 finished, if set BISTEN[0] to 1 #1 FIFOFAIL FIFO TEST Failed flag 12 1 read-write 0 memory bist pass, if set BISTEN[0] to 1 and FIFOEND is 1 #0 1 memory bist fail, if set BISTEN[0] to 1 and FIFOEND is 1 #1 FIFOPTR FIFO Pointer (Read Only) The FULL (DAC_FIFOSTS[0]) and FIFOPTR (DAC_FIFOSTS[9:4]) indicates the field that the valid data count within the DAC FIFO buffer. The maximum value shown in FIFOPTR is 32. When the using level of DAC FIFO buffer equal to 32, The FULL (DAC_FIFOSTS[0]) is set to 1. The minimum value shown in FIFOPTR is 0. When the using level of DAC FIFO buffer equal to 0, The EMPTY (DAC_FIFOSTS[1]) is set to 1. 4 6 read-only FIFOTEST Enable FIFO test mode 28 1 read-write 0 Disable FIFO test, FIFO only write #0 1 Enable FIFO test, FIFO can read and write #1 FULL FIFO Full (Read Only) 0 1 read-only 0 FIFO is not full #0 1 FIFO is full #1 RAMEND RAM TEST Finish Flag(internal use) 15 1 read-write 0 is not finishing, if set BISTEN[1] to 1 #0 1 finish, if set BISTEN[1] to 1 #1 RAMFAIL RAM TEST Failed Flag(internal use) 14 1 read-write 0 memory bist pass, if set BISTEN[1] to 1 and RAMEND is 1 #0 1 memory bist fail, if set BISTEN[1] to 1 and RAMEND is 1 #1 THIF FIFO Threshold Interrupt Status (Read Only) 2 1 read-only 0 The valid data count within the FIFO data buffer is more than the setting value of TH (DAC_CTL[24:20]) #0 1 The valid data count within the FIFO data buffer is less than or equal to the setting value of TH (DAC_CTL[24:20]) #1 HPVOL DAC_HPVOL DAC Headphone Volume Control Register 0x14 -1 read-write n 0x0 0x0 HPLM HP Output Left Channel Mute Control Register 15 1 read-write 0 Unmute #0 1 Mute #1 HPLVOL HP Output Left Channel Volume Control Register Note: Volume per step 0.5dB 0 6 read-write 0 -57dB 0x00 1 -56dB 0x01 56 -1dB 0x38 57 0dB 0x39 62 +5dB 0x3e 63 +6dB 0x3f HPRM HP Output Right Channel Mute Control Register 31 1 read-write 0 Unmute #0 1 Mute #1 HPRVOL HP Output Right Channel Volume Control Register Note: Volume per step 0.5dB 16 6 read-write 0 -57dB 0x00 1 -56dB 0x01 56 -1dB 0x38 57 0dB 0x39 62 +5dB 0x3e 63 +6dB 0x3f PDMACTL DAC_PDMACTL DAC PDMA Control Register 0x10 -1 read-write n 0x0 0x0 PDMAEN PDMA Transfer Enable Bit 0 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer Enabled #1 ZOHDIV DAC_ZOHDIV DAC Zero Order Hold Division Register 0x18 -1 read-write n 0x0 0x0 ZOHDIV Zero Order Hold, Down-sampling Divisor The input sample rate of the DPWM is set by DAC_CLK frequency and the divisor set in this register by the following formula: 0 8 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n 0x1C 0xC registers n DFBADR FMC_DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address This register reports the data flash starting address. It is a read only register. Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset. 0 32 read-only ICPCON FMC_ICPCON ICP Control Register 0x1C -1 read-write n 0x0 0x0 ICP_EN ICP control enable 0 1 read-write 0 disable #0 1 enable #1 ICPRMP FMC_ICPRMP ICP ROM Map Control Register 0x20 -1 read-write n 0x0 0x0 ICPRMP ICP ROM MAP control enable When write ICP_EN to 0 , clear ICPRMP_EN to 0 If ICP_EN is 1 and ICPRMP_EN is 1 , ISP can access MAP 0 24 read-write ISPADR FMC_ISPADR ISP Address Register 0x4 -1 read-write n 0x0 0x0 ISPADR ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD [1:0] must be 00b for correct ISP operation. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC -1 read-write n 0x0 0x0 ISPCMD ISP Command 0 6 read-write ISPCTL FMC_ISPCTL ISP Control Register 0x0 -1 read-write n 0x0 0x0 APUWEN APU Write Enable 3 1 read-write 0 APROM can't write itself. ISPFF with 1 #0 1 APROM write to itself #1 BS Boot Select 0: APROM 1: LDROM This bit functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event. 1 1 read-write CACHE_DIS Cache Disable When set to 1, caching of flash memory reads is disabled. 21 1 read-write CFGUEN CONFIG Update Enable When enabled, ISP functions can access the CONFIG address space and modify device configuration area. 4 1 read-write 0 Disable #0 1 Enable #1 ISPEN ISP Enable 0 1 read-write 0 Disable ISP function #0 1 Enable ISP function #1 ISPFF ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. (2) LDROM writes to itself. (3) Destination address is illegal, such as over an available range. (4) BOD event happen Write 1 to clear. 6 1 read-write LDUEN LDROM Update Enable LDROM update enable bit. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 WAIT_CFG Flash Access Wait State Configuration Before changing WAIT_CFG, ensure HCLK speed is < 25 MHz. 16 3 read-write 0 Three wait state 0x0 1 Two wait state 0x1 2 One wait states. HCLK <= 50 MHz 0x2 3 Zero wait states. HCLK < 24 MHz 0x3 ISPDAT FMC_ISPDAT ISP Data Register 0x8 -1 read-write n 0x0 0x0 ISPDAT ISP Data Register Write data to this register before an ISP program operation. Read data from this register after an ISP read operation 0 32 read-write ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 -1 read-write n 0x0 0x0 ISPGO ISP Start Trigger Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished. After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity. This is a protected register, user must first follow the unlock sequence see Register Lock Control Register (SYS_REGLCTL)) to gain access. 0 1 read-write 0 ISP operation is finished #0 1 ISP is on going #1 RMPRD FMC_RMPRD MAP READ Control Register 0x24 -1 read-write n 0x0 0x0 RMPRD_EN ROM MAP RD control enable ICP_EN is 1 and ICPRMP_EN is 1 , ISP can access MAP 0 1 read-write 0 disable #0 1 enable ISP access map memory #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x18 0xC registers n 0x40 0x4 registers n 0x48 0x4 registers n 0x50 0x4 registers n 0x58 0xC registers n 0x8 0x4 registers n 0x80 0x4 registers n 0x800 0x70 registers n 0x88 0x4 registers n 0x880 0x80 registers n 0x90 0x4 registers n 0x98 0xC registers n 0xC0 0x4 registers n 0xC8 0x4 registers n 0xD0 0x4 registers n 0xD8 0xC registers n PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 -1 read-write n 0x0 0x0 PDIO GPIO Px.n Pin Data Input/Output Writing this bit can control one GPIO pin output value. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output Register 0x828 -1 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output Register 0x82C -1 read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output Register 0x830 -1 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output Register 0x834 -1 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output Register 0x838 -1 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output Register 0x83C -1 read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 -1 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 -1 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C -1 read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output Register 0x810 -1 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output Register 0x814 -1 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output Register 0x818 -1 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output Register 0x81C -1 read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output Register 0x820 -1 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output Register 0x824 -1 read-write n 0x0 0x0 PA_DOUT PA_DOUT GPIO PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port [A/B/C/D] Pin[N] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output or open-drain mode. Note: PB_DOUT [15:2] are reserved to 0. 0 16 read-write 0 GPIO port [A/B/C/D] Pin[n] will drive Low if the corresponding output mode bit is set 0 1 GPIO port [A/B/C/D] Pin[n] will drive High if the corresponding output mode bit is set 1 PA_INTEN PA_INTEN GPIO PA Interrupt Enable 0x1C -1 read-write n 0x0 0x0 FLIEN0 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 0 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN1 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 1 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN10 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 10 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN11 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 11 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN12 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 12 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN13 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 13 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN14 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 14 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN15 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 15 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN2 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 2 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN3 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 3 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN4 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 4 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN5 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 5 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN6 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 6 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN7 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 7 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN8 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 8 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 FLIEN9 Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low. Note: PB_FLIEN [15:2] are reserved to 0. 9 1 read-write 0 Disable Px.n for low-level or high-to-low interrupt #0 1 Enable Px.n for low-level or high-to-low interrupt #1 RHIEN0 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 16 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN1 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 17 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN10 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 26 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN11 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 27 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN12 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 28 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN13 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 29 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN14 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 30 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN15 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 31 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN2 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 18 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN3 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 19 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN4 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 20 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN5 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 21 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN6 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 22 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN7 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 23 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN8 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 24 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 RHIEN9 Port [A/B/C/D] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high. Note: PB_RHIEN [15:2] are reserved to 0. 25 1 read-write 0 Disable Px.n for low-to-high or level-high interrupt #0 1 Enable Px.n for low-to-high or level-high interrupt #1 PA_INTSRC PA_INTSRC GPIO PA Interrupt Source Flag 0x20 -1 read-write n 0x0 0x0 INTSRC Port [A/B/C/D] Interrupt Source Flag Read operation: Note: PB_INTSRC [15:2] are reserved to 0. 0 16 read-write 0 No interrupt from Px.n. No action 0 1 Px.n generated an interrupt. Clear the corresponding pending interrupt 1 PA_INTTYPE PA_INTTYPE GPIO PA Interrupt Trigger Type 0x18 -1 read-write n 0x0 0x0 TYPE Port [A/B/C/D] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt Note 1: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur Note 2: PB_INTTYPE [15:2] are reserved to 0. 0 16 read-write 0 Edge triggered interrupt 0 1 Level triggered interrupt 1 PA_MODE PA_MODE GPIO PA Pin I/O Mode Control 0x0 -1 read-write n 0x0 0x0 MODE0 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 0 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE1 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 2 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE10 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 20 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE11 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 22 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE12 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 24 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE13 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 26 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE14 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 28 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE15 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 30 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE2 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 4 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE3 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 6 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE4 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 8 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE5 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 10 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE6 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 12 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE7 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 14 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE8 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 16 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 MODE9 Port [A/B/C/D] Pin[N] I/O Mode Control Each GPIO Px pin has four modes: Note: PB_MODE [31:4] are reserved to 0. 18 2 read-write 0 GPIO Px[n] pin is in INPUT mode #00 1 GPIO Px[n] pin is in OUTPUT mode #01 2 GPIO Px[n] pin is in Open-Drain mode #10 3 GPIO Px[n] pin is in INPUT with internal PULLUP resister mode #11 PA_PIN PA_PIN GPIO PA Pin Value 0x10 -1 read-only n 0x0 0x0 PIN Port [A/B/C/D] Pin[N] Pin Values Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note: PB_PIN [15:2] are reserved to 0. 0 16 read-only PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 -1 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output Register 0x868 -1 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output Register 0x86C -1 read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 -1 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 -1 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C -1 read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 -1 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 -1 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 -1 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C -1 read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output Register 0x860 -1 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output Register 0x864 -1 read-write n 0x0 0x0 PB_DOUT PB_DOUT GPIO PB Data Output Value 0x48 -1 read-write n 0x0 0x0 PB_INTEN PB_INTEN GPIO PB Interrupt Enable 0x5C -1 read-write n 0x0 0x0 PB_INTSRC PB_INTSRC GPIO PB Interrupt Source Flag 0x60 -1 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE GPIO PB Interrupt Trigger Type 0x58 -1 read-write n 0x0 0x0 PB_MODE PB_MODE GPIO PB Pin I/O Mode Control 0x40 -1 read-write n 0x0 0x0 PB_PIN PB_PIN GPIO PB Pin Value 0x50 -1 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 -1 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A8 -1 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output Register 0x8AC -1 read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B0 -1 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B4 -1 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output Register 0x8B8 -1 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output Register 0x8BC -1 read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 -1 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 -1 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C -1 read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 -1 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 -1 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 -1 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C -1 read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A0 -1 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output Register 0x8A4 -1 read-write n 0x0 0x0 PC_DOUT PC_DOUT GPIO PC Data Output Value 0x88 -1 read-write n 0x0 0x0 PC_INTEN PC_INTEN GPIO PC Interrupt Enable 0x9C -1 read-write n 0x0 0x0 PC_INTSRC PC_INTSRC GPIO PC Interrupt Source Flag 0xA0 -1 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE GPIO PC Interrupt Trigger Type 0x98 -1 read-write n 0x0 0x0 PC_MODE PC_MODE GPIO PC Pin I/O Mode Control 0x80 -1 read-write n 0x0 0x0 PC_PIN PC_PIN GPIO PC Pin Value 0x90 -1 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C0 -1 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E8 -1 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output Register 0x8EC -1 read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F0 -1 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F4 -1 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F8 -1 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output Register 0x8FC -1 read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 -1 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 -1 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC -1 read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 -1 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 -1 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 -1 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC -1 read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E0 -1 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E4 -1 read-write n 0x0 0x0 PD_DOUT PD_DOUT GPIO PD Data Output Value 0xC8 -1 read-write n 0x0 0x0 PD_INTEN PD_INTEN GPIO PD Interrupt Enable 0xDC -1 read-write n 0x0 0x0 PD_INTSRC PD_INTSRC GPIO PD Interrupt Source Flag 0xE0 -1 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE GPIO PD Interrupt Trigger Type 0xD8 -1 read-write n 0x0 0x0 PD_MODE PD_MODE GPIO PD Pin I/O Mode Control 0xC0 -1 read-write n 0x0 0x0 PD_PIN PD_PIN GPIO PD Pin Value 0xD0 -1 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x34 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 -1 read-write n 0x0 0x0 ADDR I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched. 1 7 read-write GC General Call Function 0 1 read-write 0 Disable General Call Function #0 1 Enable General Call Function #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 -1 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C -1 read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 -1 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 -1 read-write n 0x0 0x0 ADDRMSK I2C Address Mask Register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 1 7 read-write 0 Mask disable 0 1 Mask enable (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 -1 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C -1 read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 -1 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 -1 read-write n 0x0 0x0 DIVIDER I2C Clock Divided Register 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 -1 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 2 1 read-write I2CEN I2C Controller Enable Bit Set to enable I2C serial function block. 6 1 read-write 0 Disable #0 1 Enable #1 INTEN Enable Interrupt 7 1 read-write 0 Disable interrupt #0 1 Enable interrupt CPU #1 SI I2C Interrupt Flag When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit I2CEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit. 3 1 read-write STA I2C START Control Bit Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device. 4 1 read-write I2C_DAT I2C_DAT I2C DATA Register 0x8 -1 read-write n 0x0 0x0 DAT I2C Data Register During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 STATUS I2C Status Register The status register of I2C: 0 8 read-only I2C_TOCTL I2C_TOCTL I2C Time Out Control Register 0x14 -1 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divide by 4 When enabled, the time-out clock is PCLK/4. 1 1 read-write 0 Disable #0 1 Enable #1 TOCEN Time-out Counter Control Bit When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Disable #0 1 Enable #1 TOIF Time-out Flag 0 1 read-write 0 No time-out #0 1 Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear. #1 I2C1 I2C Register Map I2C 0x0 0x0 0x34 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 -1 read-write n 0x0 0x0 ADDR I2C Address Register The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched. 1 7 read-write GC General Call Function 0 1 read-write 0 Disable General Call Function #0 1 Enable General Call Function #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 -1 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C -1 read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 -1 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 -1 read-write n 0x0 0x0 ADDRMSK I2C Address Mask Register I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison. 1 7 read-write 0 Mask disable 0 1 Mask enable (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 -1 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C -1 read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 -1 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 -1 read-write n 0x0 0x0 DIVIDER I2C Clock Divided Register 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 -1 read-write n 0x0 0x0 AA Assert Acknowledge Control Bit 2 1 read-write I2CEN I2C Controller Enable Bit Set to enable I2C serial function block. 6 1 read-write 0 Disable #0 1 Enable #1 INTEN Enable Interrupt 7 1 read-write 0 Disable interrupt #0 1 Enable interrupt CPU #1 SI I2C Interrupt Flag When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit I2CEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit. 3 1 read-write STA I2C START Control Bit Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control Bit In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device. 4 1 read-write I2C_DAT I2C_DAT I2C DATA Register 0x8 -1 read-write n 0x0 0x0 DAT I2C Data Register During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 STATUS I2C Status Register The status register of I2C: 0 8 read-only I2C_TOCTL I2C_TOCTL I2C Time Out Control Register 0x14 -1 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divide by 4 When enabled, the time-out clock is PCLK/4. 1 1 read-write 0 Disable #0 1 Enable #1 TOCEN Time-out Counter Control Bit When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Disable #0 1 Enable #1 TOIF Time-out Flag 0 1 read-write 0 No time-out #0 1 Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear #1 I2S I2S Register Map I2S 0x0 0x0 0x1C registers n 0x20 0x8 registers n CLKDIV I2S_CLKDIV I2S Clock Divider Register 0x4 -1 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider The I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency. Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK 8 10 read-write MCLKDIV Master Clock Divider If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input. Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK 0 7 read-write CTL0 I2S_CTL0 I2S Control Register 0 0x0 -1 read-write n 0x0 0x0 CHWIDTH Channel Width This bit fields are used to define the length of audio channel. If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. 28 2 read-write 0 The bit-width of each audio channel is 8-bit #00 1 The bit-width of each audio channel is 16-bit #01 2 The bit-width of each audio channel is 24-bit #10 3 The bit-width of each audio channel is 32-bit #11 DATWIDTH Data Width This bit field is used to define the bit-width of data word in each audio channel 4 2 read-write 0 The bit-width of data word is 8-bit #00 1 The bit-width of data word is 16-bit #01 2 The bit-width of data word is 24-bit #10 3 The bit-width of data word is 32-bit #11 FLZCDEN Force Left Channel Zero Cross Data Option Bit If this bit set to 1, when channel data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation. 17 1 read-write 0 Keep channel data, when zero crossing flag on #0 1 Force channel data to zero, when zero crossing flag on #1 FORMAT Data Format Selection 24 3 read-write 0 I2S standard data format #000 1 I2S with MSB justified #001 2 I2S with LSB justified #010 3 Reserved. Do not use #011 4 PCM standard data format #100 5 PCM with MSB justified #101 6 PCM with LSB justified #110 7 Reserved. Do not use #111 FRZCDEN Force Right Channel Zero Cross Data Option Bit If this bit set to 1, when channel data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation. 16 1 read-write 0 Keep channel data, when zero crossing flag on #0 1 Force channel data to zero, when zero crossing flag on #1 I2SEN I2S Controller Enable Control 0 1 read-write 0 I2S controller Disabled #0 1 I2S controller Enabled #1 MCLKEN Master Clock Enable Control If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data Control Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Control 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Send zero on transmit channel #1 ORDER Stereo Data Order in FIFO In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. 7 1 read-write 0 Even channel data at high byte in 8-bit/16-bit data width #0 1 Even channel data at low byte #1 PCMSYNC PCM Synchronization Pulse Length Selection This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol Note: This bit is only available in master mode 27 1 read-write 0 One BCLK period #0 1 One channel period #1 RXEN Receive Enable Control 2 1 read-write 0 Data receiving Disabled #0 1 Data receiving Enabled #1 RXFBCLR Receive FIFO Buffer Clear Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. Note2: This bit is cleared by hardware automatically, read it return zero. 19 1 read-write 0 No Effect #0 1 Clear RX FIFO #1 RXLCH Receive Left Channel Enable Control 23 1 read-write 0 Receives channel1 data in MONO mode #0 1 Receives channel0 data in MONO mode #1 RXPDMAEN Receive PDMA Enable Control 21 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 SLAVE Slave Mode Enable Control Note: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Control 1 1 read-write 0 Data transmission Disabled #0 1 Data transmission Enabled #1 TXFBCLR Transmit FIFO Buffer Clear Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. Note2: This bit is clear by hardware automatically, read it return zero. 18 1 read-write 0 No Effect #0 1 Clear TX FIFO #1 TXPDMAEN Transmit PDMA Enable Control 20 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 CTL1 I2S_CTL1 I2S Control Register 1 0x20 -1 read-write n 0x0 0x0 CH0ZCEN Channel0 Zero-cross Detection Enable Control Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. 0 1 read-write 0 channel0 zero-cross detect Disabled #0 1 channel0 zero-cross detect Enabled #1 CH1ZCEN Channel1 Zero-cross Detect Enable Control Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. 1 1 read-write 0 channel1 zero-cross detect Disabled #0 1 channel1 zero-cross detect Enabled #1 PB16ORD FIFO Read/Write Order in 16-bit Width of Peripheral Bus 25 1 read-write 0 Low 16-bit read/write access first #0 1 High 16-bit read/write access first #1 PBWIDTH Peripheral Bus Data Width Selection This bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode 24 1 read-write 0 32 bits data width #0 1 16 bits data width #1 RXTH Receive FIFO Threshold Level Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. 16 4 read-write 0 1 data word in receive FIFO #0000 1 2 data words in receive FIFO #0001 2 3 data words in receive FIFO #0010 14 15 data words in receive FIFO #1110 15 16 data words in receive FIFO #1111 TXTH Transmit FIFO Threshold Level Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. 8 4 read-write 0 0 data word in transmit FIFO #0000 1 1 data word in transmit FIFO #0001 2 2 data words in transmit FIFO #0010 14 14 data words in transmit FIFO #1110 15 15 data words in transmit FIFO #1111 IEN I2S_IEN I2S Interrupt Enable Register 0x8 -1 read-write n 0x0 0x0 CH0ZCIEN Channel0 Zero-cross Interrupt Enable Control 16 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 CH1ZCIEN Channel1 Zero-cross Interrupt Enable Control 17 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXOVFIEN Receive FIFO Overflow Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 1 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXTHIEN Receive FIFO Threshold Level Interrupt Enable Control Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1. If RXTHIEN bit is enabled, interrupt occur. 2 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXUDFIEN Receive FIFO Underflow Interrupt E Enable Control Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. 0 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXOVFIEN Transmit FIFO Overflow Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 9 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXTHIEN Transmit FIFO Threshold Level Interrupt Enable Control Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). 10 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXUDFIEN Transmit FIFO Underflow Interrupt Enable Control Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. 8 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXFIFO I2S_RXFIFO I2S Receive FIFO Register 0x14 -1 read-only n 0x0 0x0 RXFIFO Receive FIFO Bits I2S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). 0 32 read-only STATUS0 I2S_STATUS0 I2S Status Register 0 0xC -1 read-write n 0x0 0x0 DATACH Transmission Data Channel (Read Only) This bit fields are used to indicate which audio channel is current transmit data belong. 3 1 read-only 0 channel0 (means left channel while 2-channel I2S/PCM mode) #0 1 channel1 (means right channel while 2-channel I2S/PCM mode) #1 I2SINT I2S Interrupt Flag (Read Only) Note: It is wire-OR of I2STXINT and I2SRXINT bits. 0 1 read-only 0 No I2S interrupt #0 1 I2S interrupt #1 I2SRXINT I2S Receive Interrupt (Read Only) 1 1 read-only 0 No receive interrupt #0 1 Receive interrupt #1 I2STXINT I2S Transmit Interrupt (Read Only) 2 1 read-only 0 No transmit interrupt #0 1 Transmit interrupt #1 RXEMPTY Receive FIFO Empty (Read Only) Note: This bit reflects data words number in receive FIFO is zero 12 1 read-only 0 Not empty #0 1 Empty #1 RXFULL Receive FIFO Full (Read Only) Note: This bit reflects data words number in receive FIFO is 12. 11 1 read-only 0 Not full #0 1 Full #1 RXOVIF Receive FIFO Overflow Interrupt Flag Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. Note2: Write 1 to clear this bit to 0. 9 1 read-write 0 No overflow occur #0 1 Overflow occur #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. 10 1 read-only 0 Data word(s) in FIFO is not higher than threshold level #0 1 Data word(s) in FIFO is higher than threshold level #1 RXUDIF Receive FIFO Underflow Interrupt Flag Note1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs. Note2: Write 1 to clear this bit to zero 8 1 read-write 0 No underflow occur #0 1 Underflow occur #1 TXBUSY Transmit Busy (Read Only) Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. 21 1 read-only 0 Transmit shift buffer is empty #0 1 Transmit shift buffer is busy #1 TXEMPTY Transmit FIFO Empty (Read Only) This bit reflect data word number in transmit FIFO is zero 20 1 read-only 0 Not empty #0 1 Empty #1 TXFULL Transmit FIFO Full (Read Only) This bit reflect data word number in transmit FIFO is 12 19 1 read-only 0 Not full #0 1 Full #1 TXOVIF Transmit FIFO Overflow Interrupt Flag Note1: Write data to transmit FIFO when it is full and this bit set to 1 Note2: Write 1 to clear this bit to 0. 17 1 read-write 0 No overflow #0 1 Overflow #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. 18 1 read-only 0 Data word(s) in FIFO is higher than threshold level #0 1 Data word(s) in FIFO is equal or lower than threshold level #1 TXUDIF Transmit FIFO Underflow Interrupt Flag Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. Note2: Write 1 to clear this bit to 0. 16 1 read-write 0 No underflow #0 1 Underflow #1 STATUS1 I2S_STATUS1 I2S Status Register 1 0x24 -1 read-write n 0x0 0x0 CH0ZCIF Channel0 Zero-cross Interrupt Flag It indicates channel0 next sample data sign bit is changed or all data bits are zero. 0 1 read-write 0 No zero-cross in channel0 #0 1 Channel0 zero-cross is detected #1 CH1ZCIF Channel1 Zero-cross Interrupt Flag It indicates channel1 next sample data sign bit is changed or all data bits are zero. 1 1 read-write 0 No zero-cross in channel1 #0 1 Channel1 zero-cross is detected #1 RXCNT Receive FIFO Level (Read Only) These bits indicate the number of available entries in receive FIFO Others are reserved. Do not use. 16 5 read-only 0 No data #00000 1 1 word in receive FIFO #00001 2 2 words in receive FIFO #00010 14 14 words in receive FIFO #01110 15 15 words in receive FIFO #01111 16 16 words in receive FIFO #10000 TXCNT Transmit FIFO Level (Read Only) These bits indicate the number of available entries in transmit FIFO Others are reserved. Do not use. 8 5 read-only 0 No data #00000 1 1 word in transmit FIFO #00001 2 2 words in transmit FIFO #00010 14 14 words in transmit FIFO #01110 15 15 words in transmit FIFO #01111 16 16 words in transmit FIFO #10000 TEST I2S_TEST Internal Use 0x18 -1 read-write n 0x0 0x0 BCLKINV BCLK Invert Control 1 1 read-write 0 BCLK invert Disabled #0 1 BCLK invert Enabled #1 LOOKBACK Look Back Control Set this bit, the TX and RX are connected 0 1 read-write 0 Look back control disabled #0 1 Look back control enabled #1 TXFIFO I2S_TXFIFO I2S Transmit FIFO Register 0x10 -1 write-only n 0x0 0x0 TXFIFO Transmit FIFO Bits I2S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). 0 32 write-only INT INT Register Map INT 0x0 0x0 0x6C registers n 0x80 0x4 registers n IRQ0_SRC IRQ0_SRC IRQ0 (WDT) Interrupt Source Identity Register 0x0 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: WDT_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (GPC) Interrupt Source Identity Register 0x28 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: GPC_INT 0 3 read-only IRQ11_SRC IRQ11_SRC IRQ11 (GPD) Interrupt Source Identity Register 0x2C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: GPD_INT 0 3 read-only IRQ12_SRC IRQ12_SRC IRQ12 (SPI0) Interrupt Source Identity Register 0x30 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPI0_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (PWM0) Interrupt Source Identity Register 0x34 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWM0_INT 0 3 read-only IRQ14_SRC IRQ14_SRC IRQ14 (PWM1) Interrupt Source Identity Register 0x38 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PWM1_INT 0 3 read-only IRQ15_SRC IRQ15_SRC IRQ15 (PDMA) Interrupt Source Identity Register 0x3C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: PDMA_INT 0 3 read-only IRQ16_SRC IRQ16_SRC IRQ16 (I2C0) Interrupt Source Identity Register 0x40 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: I2C0_INT 0 3 read-only IRQ17_SRC IRQ17_SRC IRQ17 (I2C1) Interrupt Source Identity Register 0x44 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: I2C1_INT 0 3 read-only IRQ18_SRC IRQ18_SRC IRQ18 (BOD) Interrupt Source Identity Register 0x48 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: BOD_INT 0 3 read-only IRQ19_SRC IRQ19_SRC Reserved IRQ19 (MAC) Interrupt Source Identity Register 0x4C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: MAC_INT 0 3 read-only IRQ1_SRC IRQ1_SRC IRQ1 (DAC) Interrupt Source Identity Register 0x4 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: DAC_INT 0 3 read-only IRQ20_SRC IRQ20_SRC IRQ20 (UART0) Interrupt Source Identity Register 0x50 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: UART0_INT 0 3 read-only IRQ21_SRC IRQ21_SRC IRQ21 (UART1) Interrupt Source Identity Register 0x54 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: UART1_INT 0 3 read-only IRQ22_SRC IRQ22_SRC IRQ22 (IRCTRIM) Interrupt Source Identity Register 0x58 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: IRCTRIM_INT 0 3 read-only IRQ23_SRC IRQ23_SRC IRQ23 (USB) Interrupt Source Identity Register 0x5C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: USB_INT 0 3 read-only IRQ24_SRC IRQ24_SRC IRQ24 (CPD) Interrupt Source Identity Register 0x60 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: CPD_INT 0 3 read-only IRQ25_SRC IRQ25_SRC IRQ25 (XCLKF) Interrupt Source Identity Register 0x64 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: XCLKF_INT 0 3 read-only IRQ26_SRC IRQ26_SRC IRQ26 (SPI1) Interrupt Source Identity Register 0x68 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SPI1_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (SARADC) Interrupt Source Identity Register 0x8 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SARADC_INT 0 3 read-only IRQ3_SRC IRQ3_SRC IRQ3 (SDADC) Interrupt Source Identity Register 0xC -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: SDADC_INT 0 3 read-only IRQ4_SRC IRQ4_SRC IRQ4 (I2S) Interrupt Source Identity Register 0x10 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: I2S_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (Timer0) Interrupt Source Identity Register 0x14 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer0_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (Timer1) Interrupt Source Identity Register 0x18 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer1_INT 0 3 read-only IRQ7_SRC IRQ7_SRC IRQ7 (Timer2) Interrupt Source Identity Register 0x1C -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: Timer2_INT 0 3 read-only IRQ8_SRC IRQ8_SRC IRQ8 (GPA) Interrupt Source Identity Register 0x20 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: GPA_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (GPB) Interrupt Source Identity Register 0x24 -1 read-only n 0x0 0x0 INT_SRC Interrupt Source Identity Bit2: 0 Bit1: 0 Bit0: GPB_INT 0 3 read-only NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 -1 read-write n 0x0 0x0 NMI_SEL NMI Source Interrupt Select The NMI interrupt to Cortex-M0 can be selected from one of the interrupt [0:25]. The NMI_SEL bit is used to select the NMI interrupt source. Note: IRQ19 are reserved in ISD91500. 0 5 read-write MAC MAC Register Map MAC 0x0 0x0 0x20 registers n ACCCLIP MAC_ACCCLIP Accumlator Clipped Data Register 0x1C -1 read-only n 0x0 0x0 CLIP Read operation of this register will get clipped data in MAC ACC[39:0] register but clipped with the range: 0x00-7fff-ffff ~ 0xff-8000-0000. The content of ACC[39:0] will not be changed. 0 32 read-only ACCR1R0 MAC_ACCR1R0 Accumlator R1 and R0 Register 0x14 -1 read-write n 0x0 0x0 R1R0 Write operation to this register will update ACC[31:0] (i.e. ACC_R1R0), and ACC[39:32] will sign extention from ACC_R1R0[31] automatically. Read operation from this register will get data in ACC[31:0]. 0 32 read-write ACCR2 MAC_ACCR2 Accumlator R2 Register 0x18 -1 read-write n 0x0 0x0 R2 Write operation to this register will update ACC[39:32] (i.e. ACC_R2[7:0]). Data in ACC_R2[31:8] will be ignored. Read operation from this register will get data in ACC[39:32] and show in ACC_R2[7:0], ACC_R2[31:8] is sign extension of bit ACC_R2[7] automatically . 0 32 read-write ARYPTR0 MAC_ARYPTR0 Array 0 Pointer Register 0xC -1 read-write n 0x0 0x0 ARYPTR0 Address pointer point to short integer data in Array0[ ]. ARYPTR0 will be revised after every MAC operation depend on MODIFY0. The value of ARYPTR0 is bytewise and must be even byte aligned. LSB ARYPTR0[0] will be treat as 0 always This pointer only points to RAM space. 0 15 read-write ARYPTR1 MAC_ARYPTR1 Array 1 Pointer Register 0x10 -1 read-write n 0x0 0x0 ARYPTR1 Address pointer points to a short integer data in Array1[ ]. ARYPTR1 will be revised after every MAC operation depending on value of MODIFY1. The value of ARYPTR1 is bytewise and must be even byte aligned. LSB of ARYPTR1[0] will be treated as 0 always This pointer can point to RAM space or Flash ROM space, depends on bit 29. 0 16 read-write RAM_SEL 0: ARYPTR1 points to FLASH Space 1: ARYPTR1 points to RAM Space As RAM is mapped at 0x2000_0000 user can simply load MAC_ARYPTR1 with a RAM or ROM address. 29 1 read-write CTL MAC_CTL MAC Operation Control Register 0x0 -1 read-write n 0x0 0x0 BUSY MAC operation flag 0: MAC operation completed 1: MAC is under operation. 8 1 read-write CNT When this register was written, MAC operation will start to execute (CNT+ 1) times. Only LSByte of CNT is valid. 0 8 read-write MODIFY MAC_MODIFY ARYPTR Post Modify Register 0x4 -1 read-write n 0x0 0x0 INT_EN MAC Interrupt enable. 30 1 read-write MAC_INT MAC Interrupt flag. Write 1 to clear 31 1 read-write MODIFY0 Post modify register of address pointer ARYPTR0 of short integer Array_0[ ]. ARYPTR0 will update and point to next #MODIFY0 short integer in Array0[ ] after every MAC operation. MODIFY0 range from -16 ~ +15 in 2's complement format. 0 5 read-write MODIFY1 Post modify register of address pointer ARYPTR1 of short integer Array_1[ ]. ARYPTR1 will update and point to next #MODIFY1 short integer in Array1[ ] after every MAC operation. MODIFY1 range from -16 ~ +15 in 2's complement format. 8 5 read-write SHIFTCTL MAC_SHIFTCTL Accumlator Shift Control Register 0x8 -1 write-only n 0x0 0x0 SHIFTCNT Shift the content of Accumulator ACCR2:ACCR1R0. 0000: No Shift 0001: Right shift 1 bits 0100: Right shift 4 bits 1001: Left shift 1 bit 1100: Left shift 4 bits Others: reserved Note: Right shift with Sign extension in MSB and L.S with 0 filled in LSB 0 4 write-only PDMA0 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA1 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA2 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA3 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA4 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA5 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA6 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA7 PDMA Register Map PDMA 0x0 0x0 0x28 registers n PDMA_BCR PDMA_BCR PDMA Channel x Transfer Byte Count Register 0xC -1 read-write n 0x0 0x0 BCR PDMA Transfer Byte Count Register This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF. Note: The transfer byte count must be word aligned, that is multiples of 4bytes. 0 16 read-write PDMA_CBCR PDMA_CBCR PDMA Channel x Current Transfer Byte Count Register 0x1C -1 read-only n 0x0 0x0 CBCR PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs 0 16 read-only PDMA_CDAR PDMA_CDAR PDMA Channel x Current Destination Address Register 0x18 -1 read-only n 0x0 0x0 CDAR PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Channel x Current Source Address Register 0x14 -1 read-only n 0x0 0x0 CSAR PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Channel x Control Register 0x0 -1 read-write n 0x0 0x0 APBTWS Peripheral Transfer Width Select. This parameter determines the data width to be transferred each PDMA transfer operation. Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB). 19 2 read-write 0 One word (32 bits) is transferred for every PDMA operation #00 1 One byte (8 bits) is transferred for every PDMA operation #01 2 One half-word (16 bits) is transferred for every PDMA operation #10 3 Reserved #11 DASEL Destination Address Select This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 6 2 read-write 0 Transfer Destination Address is incremented #00 1 Reserved #01 2 Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input) #10 3 Transfer Destination Address is wrapped. When CBCR (Current Byte Count) equals zero, the CDAR (Current Destination Address) and CBCR registers will be reloaded from the DAR (Destination Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 MODESEL PDMA Mode Select This parameter selects to transfer direction of the PDMA channel. Possible values are: 2 2 read-write 0 Memory to Memory mode (SRAM-to-SRAM) #00 1 IP to Memory mode (APB-to-SRAM) #01 2 Memory to IP mode (SRAM-to-APB) #10 PDMACEN PDMA Channel Enable Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SASEL Source Address Select This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped. 4 2 read-write 0 Transfer Source address is incremented #00 1 Reserved #01 2 Transfer Source address is fixed #10 3 Transfer Source address is wrapped. When CBCR (Current Byte Count) equals zero, the CSAR (Current Source Address) and CBCR registers will be reloaded from the SAR (Source Address) and BCR (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMACEN=0. When PDMACEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address #11 SWRST Software Engine Reset 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles #1 TRGEN Trigger Enable - Start a PDMA operation. Note: When PDMA transfer completed, this bit will be cleared automatically. If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again. 23 1 read-write 0 Write: no effect. Read: Idle/Finished #0 1 Enable PDMA data read or write transfer #1 WAINTSEL Wrap Interrupt Select x1x1: Both half and w interrupts generated. 12 4 read-write PDMA_DAR PDMA_DAR PDMA Channel x Destination Address Register 0x8 -1 read-write n 0x0 0x0 DAR PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned. 0 32 read-write PDMA_IER PDMA_IER PDMA Channel x Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 ABTIEN PDMA Read/Write Target Abort Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation. 0 1 read-write 0 Disable PDMA transfer target abort interrupt generation #0 1 Enable PDMA transfer target abort interrupt generation #1 TXIEN PDMA Transfer Done Interrupt Enable If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete. 1 1 read-write 0 Disable PDMA transfer done interrupt generation #0 1 Enable PDMA transfer done interrupt generation #1 WRAPIEN Wraparound Interrupt Enable If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of CSR.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA. 2 1 read-write 0 Disable Wraparound PDMA interrupt generation #0 1 Enable Wraparound interrupt generation #1 PDMA_ISR PDMA_ISR PDMA Channel x Interrupt Status Register 0x24 -1 read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 INTR Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel. 31 1 read-only TXIF Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit. 1 1 read-write 0 Transfer ongoing or Idle #0 1 Transfer Complete #1 WRAPIF Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits. 8 4 read-write 1 Current transfer finished flag (CBCR==0) #0001 4 Current transfer half complete flag (CBCR==BCR/2) #0100 PDMA_POINT PDMA_POINT PDMA Channel x Internal Buffer Pointer Register 0x10 -1 read-only n 0x0 0x0 POINT PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction. 0 4 read-only PDMA_SAR PDMA_SAR PDMA Channel x Source Address Register 0x4 -1 read-write n 0x0 0x0 SAR PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned. 0 32 read-write PDMA_GCR PDMA Register Map PDMA 0x0 0x0 0x10 registers n PDMA_GCRCSR PDMA_GCRCSR PDMA Global Control Register 0x0 -1 read-write n 0x0 0x0 HCLKEN PDMA Controller Channel Clock Enable Control To enable clock for channel n HCLKEN[n] must be set. 8 8 read-write RST PDMA Software Reset Note: This bit can reset all channels register(global reset) , but not reset each channel internal state machine. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will be cleared. This bit will auto clear after several clock cycles #1 PDMA_GCRISR PDMA_GCRISR PDMA Global Interrupt Status Register 0xC -1 read-only n 0x0 0x0 GCRISR Interrupt Pin Status (Read Only) GCRISR[n] is the interrupt status of PDMA channel n. 0 8 read-only PDMA_PDSSR0 PDMA_PDSSR0 PDMA Service Selection Control Register 0 0x4 -1 read-write n 0x0 0x0 I2SRXSEL PDMA I2S Receive Selection This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request. 8 4 read-write I2STXSEL PDMA I2S Transmit Selection This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request. 12 4 read-write SPI0RXSEL PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request. 0 4 read-write SPI0TXSEL PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request. 4 4 read-write UART0RXSEL PDMA UART0 Receive Selection This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request. 24 4 read-write UART0TXSEL PDMA UART0 Transmit Selection This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request. 28 4 read-write UART1RXSEL PDMA UART1 Receive Selection This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request. 16 4 read-write UART1TXSEL PDMA UART1 Transmit Selection This field defines which PDMA channel is connected to UART1 peripheral transmit (PDMA destination) request. 20 4 read-write PDMA_PDSSR1 PDMA_PDSSR1 PDMA Service Selection Control Register 1 0x8 -1 read-write n 0x0 0x0 DACTXSEL PDMA DAC Transmit Selection This field defines which PDMA channel is connected to DAC peripheral transmit (PDMA destination) request. 4 4 read-write SARADCSEL PDMA SARADC Receive Selection This field defines which PDMA channel is connected to SARADC peripheral receive (PDMA source) request. 8 4 read-write SDADCSEL PDMA SDADC Receive Selection This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request. 0 4 read-write SPI1RXSEL PDMA SPI1 Receive Selection This field defines which PDMA channel is connected to SPI1 peripheral receive (PDMA source) request. 16 4 read-write SPI1TXSEL PDMA SPI1 Transmit Selection This field defines which PDMA channel is connected to SPI1 peripheral transmit (PDMA destination) request. 20 4 read-write PWM0 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x4 registers n 0x28 0x4 registers n 0x34 0x4 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x8 registers n 0x7C 0x4 registers n PWM_CAPCTL PWM_CAPCTL Capture Control Register 0x50 -1 read-write n 0x0 0x0 CAPEN Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function #0 1 Enable capture function #1 CAPIF Capture Indication Flag Note:If this bit is 1 (not clear by SW), PWM counter will not be reloaded when next capture event occurs. 4 1 read-write CAPINV Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLIEN Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFLIF PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CRLIEN Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRLIF PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write PWM_CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1 0 3 read-write PWM_CLKPSC PWM_CLKPSC PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CLKPSC Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1) 0 8 read-write DZI0 Dead Zone Interval Register 0 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 16 8 read-write DZI1 Dead Zone Interval Register 1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 24 8 read-write PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x1C -1 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x28 -1 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x34 -1 read-write n 0x0 0x0 PWM_CNT PWM_CNT PWM Counter Register 0x14 -1 read-only n 0x0 0x0 CNT PWM Counter Register Reports the current value of the 16-bit down counter. 0 16 read-only PWM_CTL PWM_CTL PWM Control Register 0x8 -1 read-write n 0x0 0x0 CNTEN PWM-Timer Enable 0 1 read-write 0 Stop PWM-Timer Running #0 1 Enable PWM-Timer #1 CNTMODE PWM-Timer Auto-Reload/One-Shot Mode 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DTEN0 Dead-Zone 0 Generator Enable/Disable 4 1 read-write 0 Disable #0 1 Enable #1 DTEN1 Dead-Zone 1 Generator Enable/Disable 5 1 read-write 0 Disable #0 1 Enable #1 PINV PWM-Timer Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 PWM_FCAPDAT PWM_FCAPDAT Capture Falling Latch Register 0x5C -1 read-only n 0x0 0x0 FCAPDAT Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only PWM_INTEN PWM_INTEN PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PIEN PWM Timer Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWM_INTSTS PWM_INTSTS PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PIF PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PWM_PCEN PWM_PCEN PWM Output and Capture Input Enable Register 0x7C -1 read-write n 0x0 0x0 CAPINEN Capture Input Enable Register 8 1 read-write 0 OFF (PA.7/PB.4 pin input disconnected from Capture block) #0 1 ON (PA.7/PB.4 pin, if in PWM alternative function, will be configured as an input and fed to capture function) #1 POEN0 PWM Channel0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 0 1 read-write 0 Disable PWM Channel0 output to pin #0 1 Enable PWM Channel0 output to pin #1 POEN1 PWM Channel 1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 1 1 read-write 0 Disable PWM Channel 1 output to pin #0 1 Enable PWM Channel 1 output to pin #1 POEN2 PWM Channel 2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 2 1 read-write 0 Disable PWM Channel 2output to pin #0 1 Enable PWM Channel 2 output to pin #1 POEN3 PWM Channel 3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 3 1 read-write 0 Disable PWM Channel 3 output to pin #0 1 Enable PWM Channel 3 output to pin #1 PWM_PERIOD PWM_PERIOD PWM Period Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Reload Value PERIOD determines the PWM period. 0 16 read-write PWM_RCAPDAT PWM_RCAPDAT Capture Rising Latch Register 0x58 -1 read-only n 0x0 0x0 RCAPDAT Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only PWM1 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x4 registers n 0x28 0x4 registers n 0x34 0x4 registers n 0x40 0x8 registers n 0x50 0x4 registers n 0x58 0x8 registers n 0x7C 0x4 registers n PWM_CAPCTL PWM_CAPCTL Capture Control Register 0x50 -1 read-write n 0x0 0x0 CAPEN Capture Channel Input Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt. 3 1 read-write 0 Disable capture function #0 1 Enable capture function #1 CAPIF Capture Indication Flag Note:If this bit is 1 (not clear by SW), PWM counter will not be reloaded when next capture event occurs. 4 1 read-write CAPINV Inverter ON/OFF 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 CFLIEN Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input. 2 1 read-write 0 Disable falling latch interrupt #0 1 Enable falling latch interrupt #1 CFLIF PWM_FCAPDAT Latched Indicator Bit When input channel has a falling transition, PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 7 1 read-write CRLIEN Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input. 1 1 read-write 0 Disable rising latch interrupt #0 1 Enable rising latch interrupt #1 CRLIF PWM_RCAPDAT Latched Indicator Bit When input channel has a rising transition, PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it. 6 1 read-write PWM_CLKDIV PWM_CLKDIV PWM Clock Select Register 0x4 -1 read-write n 0x0 0x0 CLKDIV PWM Timer Clock Source Selection Value : Input clock divided by 000 : 2 001 : 4 010 : 8 011 : 16 1xx : 1 0 3 read-write PWM_CLKPSC PWM_CLKPSC PWM Prescaler Register 0x0 -1 read-write n 0x0 0x0 CLKPSC Clock Prescaler For PWM Timer Clock input is divided by (CLKPSC + 1) 0 8 read-write DZI0 Dead Zone Interval Register 0 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 16 8 read-write DZI1 Dead Zone Interval Register 1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector. 24 8 read-write PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x10 -1 read-write n 0x0 0x0 CMP PWM Comparator Register CMP determines the PWM duty ratio. Assumption: PWM output initial is high Note2: Any write to CMP will take effect in next PWM cycle. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x1C -1 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x28 -1 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x34 -1 read-write n 0x0 0x0 PWM_CNT PWM_CNT PWM Counter Register 0x14 -1 read-only n 0x0 0x0 CNT PWM Counter Register Reports the current value of the 16-bit down counter. 0 16 read-only PWM_CTL PWM_CTL PWM Control Register 0x8 -1 read-write n 0x0 0x0 CNTEN PWM-Timer Enable 0 1 read-write 0 Stop PWM-Timer Running #0 1 Enable PWM-Timer #1 CNTMODE PWM-Timer Auto-Reload/One-Shot Mode 3 1 read-write 0 One-Shot Mode #0 1 Auto-reload Mode #1 DTEN0 Dead-Zone 0 Generator Enable/Disable 4 1 read-write 0 Disable #0 1 Enable #1 DTEN1 Dead-Zone 1 Generator Enable/Disable 5 1 read-write 0 Disable #0 1 Enable #1 PINV PWM-Timer Output Inverter ON/OFF 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 PWM_FCAPDAT PWM_FCAPDAT Capture Falling Latch Register 0x5C -1 read-only n 0x0 0x0 FCAPDAT Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal. 0 16 read-only PWM_INTEN PWM_INTEN PWM Interrupt Enable Register 0x40 -1 read-write n 0x0 0x0 PIEN PWM Timer Interrupt Enable 0 1 read-write 0 Disable #0 1 Enable #1 PWM_INTSTS PWM_INTSTS PWM Interrupt Flag Register 0x44 -1 read-write n 0x0 0x0 PIF PWM Timer Interrupt Flag Flag is set by hardware when PWM down counter reaches zero, software can clear this bit by writing '1' to it. 0 1 read-write PWM_PCEN PWM_PCEN PWM Output and Capture Input Enable Register 0x7C -1 read-write n 0x0 0x0 CAPINEN Capture Input Enable Register 8 1 read-write 0 OFF (PA.7/PB.4 pin input disconnected from Capture block) #0 1 ON (PA.7/PB.4 pin, if in PWM alternative function, will be configured as an input and fed to capture function) #1 POEN0 PWM Channel0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 0 1 read-write 0 Disable PWM Channel0 output to pin #0 1 Enable PWM Channel0 output to pin #1 POEN1 PWM Channel 1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 1 1 read-write 0 Disable PWM Channel 1 output to pin #0 1 Enable PWM Channel 1 output to pin #1 POEN2 PWM Channel 2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 2 1 read-write 0 Disable PWM Channel 2output to pin #0 1 Enable PWM Channel 2 output to pin #1 POEN3 PWM Channel 3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP) 3 1 read-write 0 Disable PWM Channel 3 output to pin #0 1 Enable PWM Channel 3 output to pin #1 PWM_PERIOD PWM_PERIOD PWM Period Register 0xC -1 read-write n 0x0 0x0 PERIOD PWM Counter/Timer Reload Value PERIOD determines the PWM period. 0 16 read-write PWM_RCAPDAT PWM_RCAPDAT Capture Rising Latch Register 0x58 -1 read-only n 0x0 0x0 RCAPDAT Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal. 0 16 read-only SARADC SARADC Register Map SARADC 0x0 0x0 0x60 registers n CHSEQ0 SARADC_CHSEQ0 SARADC Channel Sequence Register0 0x40 -1 read-write n 0x0 0x0 CHSEQ0 Select Channel N As The 1st Conversion In Scan Sequence 0 4 read-write CHSEQ1 Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 4 4 read-write CHSEQ2 Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 8 4 read-write CHSEQ3 Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 12 4 read-write CHSEQ4 Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 16 4 read-write CHSEQ5 Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 20 4 read-write CHSEQ6 Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 24 4 read-write CHSEQ7 Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 28 4 read-write CHSEQ1 SARADC_CHSEQ1 SARADC Channel Sequence Register1 0x44 -1 read-write n 0x0 0x0 CHSEQ10 Select Channel N As The 11th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 8 4 read-write CHSEQ11 Select Channel N As The 12th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 12 4 read-write CHSEQ12 Select Channel N As The 13th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 16 4 read-write CHSEQ13 Select Channel N As The 14th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 20 4 read-write CHSEQ14 Select Channel N As The 15th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 24 4 read-write CHSEQ8 Select Channel N As The 9th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 0 4 read-write CHSEQ9 Select Channel N As The 10th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0. 4 4 read-write CMP0 SARADC_CMP0 SARADC Compare Register 0 0x48 -1 read-write n 0x0 0x0 ADCMPEN Compare Enable Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into SARADC_DAT register. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 ADCMPIE Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable #0 1 Enable #1 CMPCH Compare Channel Selection 3 4 read-write 0 Channel 0 conversion result is selected to be compared #0000 1 Channel 1 conversion result is selected to be compared #0001 2 Channel 2 conversion result is selected to be compared #0010 3 Channel 3 conversion result is selected to be compared #0011 4 Channel 4 conversion result is selected to be compared #0100 5 Channel 5 conversion result is selected to be compared #0101 6 Channel 6 conversion result is selected to be compared #0110 7 Channel 7 conversion result is selected to be compared #0111 8 Channel 8 conversion result is selected to be compared #1000 9 Channel 9 conversion result is selected to be compared #1001 10 Channel 10 conversion result is selected to be compared #1010 11 Channel 11 conversion result is selected to be compared #1011 12 Channel 12 conversion result is selected to be compared #1100 13 Channel 13 conversion result is selected to be compared #1101 14 Channel 14 conversion result is selected to be compared #1110 CMPCOND Compare Condition 2 1 read-write 0 ADCMPFx bit is set if conversion result is less than CMPDAT #0 1 ADCMPFx bit is set if conversion result is greater or equal to CMPDAT, #1 CMPDAT Compare Data This field possessing 12-bit compare data, is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit. 16 12 read-write CMPMCNT Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit. 8 4 read-write CMP1 SARADC_CMP1 SARADC Compare Register 1 0x4C -1 read-write n 0x0 0x0 CTL SARADC_CTL SARADC Control Register 0x3C -1 read-write n 0x0 0x0 ADCEN A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disable #0 1 Enable #1 ADCFM Data Format Of ADC Conversion Result 12 1 read-write 0 Unsigned #0 1 2's Complement #1 ADCIE A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1. 1 1 read-write 0 Disable A/D interrupt function #0 1 Enable A/D interrupt function #1 DLYTRIM Trim bit for SARADC speed 6 2 read-write 0 636.5284ns #00 1 720.5ns #01 2 807ns #10 3 976.5ns #11 MODESEL SARADC conversion speed mode selection 9 1 read-write 0 High speed(500KSPS) #0 1 Low speed(200KSPS) #1 MUXEN Input channel MUX enable control 8 1 read-write 0 Disable(MUX output floating) #0 1 Enable #1 MUXSW MUXEN software control register 0 : MUX always enable turn on 1 : MUX control by MUXEN 5 1 read-write OPMODE A/D Converter Operation Mode Note 1: When changing the operation mode, software should disable SWTRG bit firstly. 2 2 read-write 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 OVRIE Sample rate over interrupt enable 10 1 read-write 0 Disable #0 1 Enable #1 PDMAEN PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADC_DATn (n: 0 ~ 1314) register, user can enable this bit to generate a PDMA data transfer request. 4 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer Enabled #1 SWTRG A/D Conversion Start Note1: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets. Note2: Before trigger SWTRG to start ADC convert , the ADC relative setting should be completed. 11 1 read-write 0 Conversion is stopped and A/D converter enters idle state #0 1 Start conversion #1 DAT0 SARADC_DAT0 SARADC Data Register for the Channel Defined in CHSEQ0 0x0 -1 read-only n 0x0 0x0 EXTS Extension Bits Of RESULT for Different Data Format If ADCFM is 0 , EXTS all are read as 0 . If ADCFM is 1 , EXTS all are read as bit RESULT [11]. 12 4 read-only OV Over Run Flag If converted data in RESULT [11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read. 16 1 read-only 0 Data in RESULT are recent conversion result #0 1 Data in RESULT are overwritten #1 RESULT A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit. 0 12 read-only VALID Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read. 17 1 read-only 0 Data in RESULT are not valid #0 1 Data in RESULT are valid #1 DAT1 SARADC_DAT1 SARADC Data Register for the Channel Defined in CHSEQ1 0x4 -1 read-write n 0x0 0x0 DAT10 SARADC_DAT10 SARADC Data Register for the Channel Defined in CHSEQ10 0x28 -1 read-write n 0x0 0x0 DAT11 SARADC_DAT11 SARADC Data Register for the Channel Defined in CHSEQ11 0x2C -1 read-write n 0x0 0x0 DAT12 SARADC_DAT12 SARADC Data Register for the Channel Defined in CHSEQ12 0x30 -1 read-write n 0x0 0x0 DAT13 SARADC_DAT13 SARADC Data Register for the Channel Defined in CHSEQ13 0x34 -1 read-write n 0x0 0x0 DAT14 SARADC_DAT14 SARADC Data Register for the Channel Defined in CHSEQ14 0x38 -1 read-write n 0x0 0x0 DAT2 SARADC_DAT2 SARADC Data Register for the Channel Defined in CHSEQ2 0x8 -1 read-write n 0x0 0x0 DAT3 SARADC_DAT3 SARADC Data Register for the Channel Defined in CHSEQ3 0xC -1 read-write n 0x0 0x0 DAT4 SARADC_DAT4 SARADC Data Register for the Channel Defined in CHSEQ4 0x10 -1 read-write n 0x0 0x0 DAT5 SARADC_DAT5 SARADC Data Register for the Channel Defined in CHSEQ5 0x14 -1 read-write n 0x0 0x0 DAT6 SARADC_DAT6 SARADC Data Register for the Channel Defined in CHSEQ6 0x18 -1 read-write n 0x0 0x0 DAT7 SARADC_DAT7 SARADC Data Register for the Channel Defined in CHSEQ7 0x1C -1 read-write n 0x0 0x0 DAT8 SARADC_DAT8 SARADC Data Register for the Channel Defined in CHSEQ8 0x20 -1 read-write n 0x0 0x0 DAT9 SARADC_DAT9 SARADC Data Register for the Channel Defined in CHSEQ9 0x24 -1 read-write n 0x0 0x0 HWPARA SARADC_HWPARA SARADC H/W Parameter Control Register 0x5C -1 read-write n 0x0 0x0 CONVN Specify SARADC conversion clock number To update this field, programmer can only revise bit [14:8] and keep other bits the same as before. Note: CONVN value must bigger than SHCLKN value and should bigger than 2us(500KSPS). 8 7 read-write SHCLKN Specify the high level of SARADC start signal. Note: SHCLKN must larger than 400ns. 0 6 read-write PDMADAT SARADC_PDMADAT SARADC PDMA Result Register 0x58 -1 read-write n 0x0 0x0 DATA SARADC PDMA transfer data This is a read only register. 0 16 read-write STATUS0 SARADC_STATUS0 SARADC Status Register0 0x50 -1 read-write n 0x0 0x0 ADCMPF0 Compare Flag0 When the selected channel A/D conversion result meets setting conditions in SARADC_CMP0, then this bit is set to 1. And it is cleared by write 1. 1 1 read-write 0 Converted result RESULT in SARADC_DAT does not meet SARADC_CMP0 setting #0 1 Converted result RESULT in SARADC_DAT meets SARADC_CMP0 setting, #1 ADCMPF1 Compare Flag1 When the selected channel A/D conversion result meets setting conditions in SARADC_CMP1, then this bit is set to 1. And it is cleared by write 1. 2 1 read-write 0 Converted result RESULT in SARADC_DAT does not meet SARADC_CMP1 setting #0 1 Converted result RESULT in SARADC_DAT meets SARADC_CMP1 setting, #1 ADIF A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written. 0 1 read-write BUSY BUSY/IDLE This bit is mirror of SWTRG bit in SARADC_CTL. It is read only. 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel It is read only. 4 4 read-write OVRF Sampling rate over flag It is cleared when 1 is written. 8 1 read-write 0 user setting sample rate not exceed real conversion rate #0 1 user setting sample rate exceed real conversion rate #1 STATUS1 SARADC_STATUS1 SARADC Status Register1 0x54 -1 read-write n 0x0 0x0 OV Over Run Flag It is a mirror to OV bit in SARADC_DATn. 16 15 read-write VALID Data Valid Flag It is a mirror of VALID bit in SARADC_DATn. 0 15 read-write SDADC SDADC Register Map SDADC 0x0 0x0 0x24 registers n 0x28 0x8 registers n ANA0 SDADC_ANA0 SD ADC Analog Block Control Register 0 0x20 -1 read-write n 0x0 0x0 BIAS SDADC Bias Current Selection 1 2 read-write 0 1.35 #00 1 1 #01 2 0.67 #10 3 1.68 #11 CHOPCKPH SDADC Chopper Clock phase selection 25 1 read-write 0 chopper transition after falling edge of SD_CLK (default) #0 1 chopper transition after rising edge of SD_CLK #1 CHOPEN SDADC chopper enable 29 1 read-write 0 disable (default) #0 1 enable #1 CHOPF SDADC Chopper Frequency in fixed chop mode 23 2 read-write 0 Fs/2 (default) #00 1 Fs/4 #01 2 Fs/8 #10 3 Fs/16 #11 CHOPFIX SDADC Chopper Fixed Frequency 26 1 read-write 0 dither chopper frequency (default) #0 1 choose fixed frequency #1 CHOPORD SDADC Chopper Order 27 1 read-write 0 1st order dithering of chopper frequency (default) #0 1 2nd order dithering of chopper frequency #1 CHOPPH SDADC chopper phase When chopper is off: 28 1 read-write 0 chopper switches in default state #0 1 invert chopper switches #1 CLASSA Enable PGA Class A mode of operation 18 1 read-write 0 Class AB #0 1 Class A (default) #1 CMLCK PGA Common mode Threshold lock adjust enable 15 1 read-write 0 Enable #0 1 Disable #1 CMLCKADJ 16 2 read-write 0 0.98 (default) #00 1 0.96 #01 2 1.01 #10 3 1.04 #11 IBCTR Trim PGA Current 9 3 read-write 0 default 0 IBLOOP Trim PGA current 12 1 read-write 1 default #1 MODE PGA mode selection 6 2 read-write 0 Disable 0 1 Enable 1 MUTE PGA Mute control signal 5 1 read-write 0 disable #0 1 enable #1 PD SDADC Power Down 0 1 read-write 0 SDADC power on #0 1 SDADC power off #1 PU Power up PGA 4 1 read-write 0 disable #0 1 enable #1 TRIMOBC Trim PGA current in output driver 19 1 read-write 0 disable #0 1 enable (default) #1 VREF SDADC Chopper in Reference Buffer 3 1 read-write 0 chopper off #0 1 chopper on #1 ANA1 SDADC_ANA1 SD ADC Analog Block Control Register 1 0x28 -1 read-write n 0x0 0x0 ACDC BST ACDC Control register 16 2 read-write 0 Default #00 BSTMODE BST mode selection 9 4 read-write 0 Disable 0 1 Enable 1 BSTMUTE Boost mute 13 1 read-write 0 Unmute #0 1 Mute(default) #1 BSTPUP Boost power on 14 1 read-write 0 Power off(default) #0 1 Power on #1 BSTTRIMOBC Trim Current: BST driver Keep default 0'b 15 1 read-write CLASSAEN 3 1 read-write 0 (default) #0 1 #1 CMLCKADJ Default 00'b 0 2 read-write CMLCKEN 2 1 read-write 0 #0 1 (default) #1 DISCHRG BST Charge inputs selected by ACDC[1:0] to VMID 4 1 read-write 0 Disable #0 1 Enable #1 IBCTRCODE Trim Current of BST Keep default 000'b 5 3 read-write IBLOOPCTR Trim Current of BST Keep default 0'b 8 1 read-write ANA2 SDADC_ANA2 SD ADC Analog Block Control Register 2 0x2C -1 read-write n 0x0 0x0 GAINSET Select The PGA Gain Setting From -12dB to 34.5dB in 1.5dB step size. 0x00 is lowest gain setting at -12dB and 0x1F is largest gain at 34.5dB.(0x8 is 0 dB) 0 5 read-write CLKDIV SDADC_CLKDIV SD ADC Clock Divider Register 0x8 -1 read-write n 0x0 0x0 CLKDIV SDADC Clock Divider This register determines the clock division ration between the incoming SD_CLK and the Sigma-Delta sampling clock of the ADC. This together with the over-sampling ratio (OSR) determines the audio sample rate of the converter. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. CLKDIV must be greater than or equal 4. 0 8 read-write CMPR0 SDADC_CMPR0 SD ADC Comparator 0 Control Register 0x18 -1 read-write n 0x0 0x0 ADCMPEN Compare Enable Set this bit to 1 to enable compare CMPDAT with FIFO data output. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 CMPCOND Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set. 2 1 read-write 0 Set the compare condition that result is less than CMPD #0 1 Set the compare condition that result is greater or equal to CMPD #1 CMPD Comparison Data 23 bit value to compare to FIFO output word. 8 23 read-write CMPF Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self. 3 1 read-write CMPIE Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable compare function interrupt #0 1 Enable compare function interrupt #1 CMPMATCNT Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. 4 4 read-write CMPOEN Compare Match output FIFO zero 31 1 read-write 0 FIFO data keep original one #0 1 compare match then FIFO out zero #1 CMPR1 SDADC_CMPR1 SD ADC Comparator 1 Control Register 0x1C -1 read-write n 0x0 0x0 ADCMPEN Compare Enable Set this bit to 1 to enable compare CMPDAT with FIFO data output. 0 1 read-write 0 Disable compare #0 1 Enable compare #1 CMPCOND Compare Condition Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set. 2 1 read-write 0 Set the compare condition that result is less than CMPD #0 1 Set the compare condition that result is greater or equal to CMPD #1 CMPD Comparison Data 23 bit value to compare to FIFO output word. 8 23 read-write CMPF Compare Flag When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self. 3 1 read-write CMPIE Compare Interrupt Enable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Disable compare function interrupt #0 1 Enable compare function interrupt #1 CMPMATCNT Compare Match Count When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. 4 4 read-write CMPOEN Compare Match output FIFO zero 31 1 read-write 0 FIFO data keep original one #0 1 compare match then FIFO out zero #1 CTL SDADC_CTL SD ADC Control Register 0xC -1 read-write n 0x0 0x0 DSRATE Down Sampling Ratio 0 2 read-write 0 reserved #00 1 down sample X 16 #01 2 down sample X 32 #10 3 down sample X 64 when SPDS = 0 . 11 = down sample X 62.5 when SPDS = 1 #11 FIFOBITS FIFO Data Bits Selection 2 2 read-write 0 32 bits #00 1 16 bits #01 2 8 bits #10 3 24 bits #11 FIFOTH FIFO Threshold: Determines at what level the ADC FIFO will generate a interrupt. Interrupt will be generated when number of words present in ADC FIFO is > FIFOTH. 4 4 read-write FIFOTHIE FIFO Threshold Interrupt Enable 8 1 read-write 0 disable interrupt whenever FIFO level exceeds that set in FIFOTH #0 1 enable interrupt whenever FIFO level exceeds that set in FIFOTH #1 SPDS Specific down sampling ratio control 12 1 read-write 0 Disable specific DS rate #0 1 Enable specific DS rate #1 DAT SDADC_DAT SD ADC FIFO Data Read Register 0x0 -1 read-only n 0x0 0x0 RESULT Delta-Sigma ADC DATA FIFO Read A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with SDADC_FIFOSTS.THIF interrupt to determine if valid data is present in FIFO. Data width can be selected by SDADC_CTL.FIFO_BITS 0 32 read-only EN SDADC_EN SD ADC Enable Register 0x4 -1 read-write n 0x0 0x0 DINBYPS SDADC data input bypass (internal debug) 2 1 read-write 0 normal mode #0 1 analog 5bits to FIFO for testing #1 DINEDGE SDADC data input clock edge selection 1 1 read-write 0 ADC clock negetive edge latch #0 1 ADC clock positive edge latch #1 SDADCEN SDADC Enable 0 1 read-write 0 Conversion stopped and ADC is reset including FIFO pointers #0 1 ADC Conversion enabled #1 FIFOSTS SDADC_FIFOSTS SD ADC FIFO Status Register 0x10 -1 read-write n 0x0 0x0 BISTEN SDADC BIST Enable(internal use) 24 1 read-write 0 Disable BIST testing #0 1 Enable BIST testing #1 BISTEND SDADC BIST TEST Finish Flag(internal use) 26 1 read-write 0 is not finishing, if set BISTEN to 1 #0 1 finish, if set BISTEN to 1 #1 BISTFAIL SDADC BIST TEST Failed Flag(internal use) 25 1 read-write 0 memory bist pass, if set BISTEN to 1 and BISTEND is 1 #0 1 memory bist fail, if set BISTEN to 1 and BISTEND is 1 #1 EMPTY FIFO Empty 1 1 read-write 0 FIFO is not empty #0 1 FIFO is empty #1 FIFOTEST Enable FIFO test mode Internal use 31 1 read-write 0 Disable ADC FIFO testing #0 1 Enable ADC FIFO testing ADC FIFO can be testing by Cortex-M0 #1 FULL FIFO Full 0 1 read-write 0 FIFO is not full #0 1 FIFO is full #1 POINTER ADC FIFO Pointer (Read Only) The FULL bit and FIFOPOINTER[4:0] indicates the field that the valid data count within the SDADC FIFO buffer. The Maximum value shown in FIFOPOINTER is 31. When the using level of SDADC FIFO Buffer equal to 32, The FULL bit is set to 1. 4 5 read-only THIF ADC FIFO Threshold Interrupt Status (Read Only) 2 1 read-only 0 The valid data count within the transmit FIFO buffer is less than to the setting value of FIFOTH #0 1 The valid data count within the ADC FIFO buffer is larger than or equal the setting value of FIFOTH #1 PDMACTL SDADC_PDMACTL SD ADC PDMA Control Register 0x14 -1 read-write n 0x0 0x0 PDMAEN Enable SDADC PDMA Receive Channel 0 1 read-write 0 Disable SDADC PDMA #0 1 Enable SDADC PDMA #1 SPI0 SPI Register Map SPI 0x0 0x0 0x1C registers n 0x20 0x4 registers n 0x30 0x8 registers n SPI_BIST SPI_BIST SPI BIST Control Register 0x34 -1 read-write n 0x0 0x0 RXBISTEF SPI RX SRAM BIST Fail Flag 2 1 read-write 0 SPI RX SRAM BIST pass #0 1 SPI RX SRAM BIST fail #1 RXBISTEN SPI RX SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for ADC SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 SPI RX SRAM BIST Disabled #0 1 SPI RX SRAM BIST Enabled #1 RXBISTEND SPI RX SRAM BIST Test Finish 1 1 read-write 0 SPI RX SRAM BIST active #0 1 SPI RX SRAM BIST finish #1 TXBISTEF SPI TX SRAM BIST Fail Flag 6 1 read-write 0 SPI TX SRAM BIST pass #0 1 SPI TX SRAM BIST fail #1 TXBISTEN SPI TX SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for ADC SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 SPI TX SRAM BIST Disabled #0 1 SPI TX SRAM BIST Enabled #1 TXBISTEND SPI TX SRAM BIST Test Finish 5 1 read-write 0 SPI TX SRAM BIST active #0 1 SPI TX SRAM BIST finish #1 SPI_CLKDIV SPI_CLKDIV Clock Divider Register (Master Only) 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider Register The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. where Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control, CLKSEL1 register. Note: SPI engine clock must smaller than PCLK/2 0 8 read-write SPI_CTL SPI_CTL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity 3 1 read-write 0 SCLK idle low #0 1 SCLK idle high #1 DUALIOEN Dual I/O Mode Enable 21 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 DWIDTH DWIDTH - Data Word Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. 8 5 read-write IE Unit Transfer Interrupt Enable 17 1 read-write 0 Disable SPI Unit Transfer Interrupt #0 1 Enable SPI Unit Transfer Interrupt to CPU #1 LSB LSB First Note: For DUAL and QUAD transactions with LSB must be set to 0. 13 1 read-write 0 The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field) #0 1 The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX) #1 QDIODIR Quad or Dual I/O Mode Direction Control 20 1 read-write 0 Quad or Dual Input mode #0 1 Quad or Dual Output mode #1 QUADIOEN Quad I/O Mode Enable 22 1 read-write 0 Quad I/O mode Disabled #0 1 Quad I/O mode Enabled #1 REORDER Byte Reorder Function Enable Note: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. REORDER is only available for Receive mode in DUAL and QUAD transactions. For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXMODEEN FIFO Receive Mode Enable 24 1 read-write 0 Disable function #0 1 Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0 #1 RXNEG Receive at Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SCLK #0 1 The received data input signal is latched at the falling edge of SCLK #1 RXTCNTEN DMA Receive Transaction Count Enable 23 1 read-write 0 Disable function #0 1 Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller #1 SLAVE Master Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Enable In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to 1. Note: All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG, RXNEG, DWIDTH, LSB, CLKP, and so on). 0 1 read-write 0 Disable SPI Transfer #0 1 Enable SPI Transfer #1 SUSPITV Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and QUAD mode transactions. (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle Example: Note: For DUAL and QUAD transactions with SUSPITV must be set to 0. 4 4 read-write TWOBIT Two Bits Transfer Mode When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 16 1 read-write 0 Disable two-bit transfer mode #0 1 Enable two-bit transfer mode #1 TXNEG Transmit at Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SCLK #0 1 The transmitted data output signal is changed at the falling edge of SCLK #1 SPI_FIFOCTL SPI_FIFOCTL FIFO Control/Status Register 0x10 -1 read-write n 0x0 0x0 RXOVIEN Receive FIFO Overrun Interrupt Enable 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Clear Receive FIFO Buffer Note: If there is slave receive time out event, the RXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled. 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1 #1 RXTH Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 000: 1 word will transmit 001: 2 word will transmit 010: 3 word will transmit 011: 4 word will transmit 100: 5 word will transmit 101: 6 word will transmit 110: 7 word will transmit 111: 8 word will transmit 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXRST Clear Transmit FIFO Buffer Note: If there is slave receive time out event, the TXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled. 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1 #1 TXTH Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 000: 1 word will transmit 001: 2 word will transmit 010: 3 word will transmit 011: 4 word will transmit 100: 5 word will transmit 101: 6 word will transmit 110: 7 word will transmit 111: 8 word will transmit 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUDFIEN Slave Transmit Under Run Interrupt Enable 7 1 read-write 0 Slave Transmit FIFO under-run interrupt Disabled #0 1 Slave Transmit FIFO under-run interrupt Enabled #1 TXUDFPOL Transmit Under-run Data Out Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data. Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time to report the transmit under-run data out. 6 1 read-write 0 The SPI data out is 0 if there is transmit under-run event in Slave mode #0 1 The SPI data out is 1 if there is transmit under-run event in Slave mode #1 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0xC -1 read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically #1 RXPDMAEN Receive PDMA Enable Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done. 1 1 read-write TXPDMAEN Transmit DMA Enable Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done. 0 1 read-write SPI_RX SPI_RX FIFO Data Receive Register 0x30 -1 read-only n 0x0 0x0 RX Data Receive Register A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register. 0 32 read-only SPI_RXTSNCNT SPI_RXTSNCNT Receive Transaction Count Register 0x18 -1 read-write n 0x0 0x0 RXTSNCNT DMA Receive Transaction Count When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate. 0 16 read-write SPI_SSCTL SPI_SSCTL Slave Select Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI_SSCTL[1:0] #0 1 If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 SLV3WIRE Slave 3-wire Mode Enable This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI. 4 1 read-write 0 4-wire bi-directional interface #0 1 3-wire bi-directional interface #1 SLVBCEIEN Slave Mode Error 0 Interrupt Enable 8 1 read-write 0 Slave mode error 0 interrupt Disable #0 1 Slave mode error 0 interrupt Enable #1 SLVTOCNT Slave Mode Time-out Period In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled. 16 16 read-write SLVTOIEN Slave Mode Time-out Interrupt Enable 5 1 read-write 0 Slave mode time-out interrupt Disabled #0 1 Slave mode time-out interrupt Enabled #1 SLVTORST Slave Mode Time-out FIFO Clear 6 1 read-write 0 Function disabled #0 1 Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event #1 SLVUDRIEN Slave Mode Error 1 Interrupt Enable 9 1 read-write 0 Slave mode error 1 interrupt Disable #0 1 Slave mode error 1 interrupt Enable #1 SS Slave Select Control Bits (Master Only) If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SSLVL. Note: SPI_SS0 is defined as the slave select input in Slave mode. 0 2 read-write SSACTIEN Slave Select Active Interrupt Enable 12 1 read-write 0 Slave select active interrupt Disable #0 1 Slave select active interrupt Enable #1 SSINAIEN Slave Select Inactive Interrupt Enable 13 1 read-write 0 Slave select inactive interrupt Disable #0 1 Slave select inactive interrupt Enable #1 SSLVL Slave Select Active Level This bit defines the active status of slave select signal (SPI_SS0/1). 2 1 read-write 0 The slave select signal SPI_SS0/1 is active on low-level/falling-edge #0 1 The slave select signal SPI_SS0/1 is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS Status Register 0x14 -1 read-write n 0x0 0x0 BUSY SPI Unit Bus Status (Read Only) 0 1 read-only 0 No transaction in the SPI bus #0 1 SPI controller unit is in busy state #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Status When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to itself. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Status (Read Only) 10 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Status Note: This bit will be cleared by writing 1 to itself. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Error 0 Interrupt Status (Read Only) In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state. Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state. 6 1 read-only 0 No Slave mode error 0 event #0 1 Slave mode error 0 occurs #1 SLVTOIF Slave Time-out Interrupt Status (Read Only) When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active. Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period. 5 1 read-only 0 Slave time-out is not active #0 1 Slave time-out is active #1 SLVURIF Slave Mode Error 1 Interrupt Status (Read Only) In Slave mode, transmit under-run occurs when the slave select line goes to inactive state. 7 1 read-only 0 No Slave mode error 1 event #0 1 Slave mode error 1 occurs #1 SPIENSTS SPI Enable Bit Status (Read Only) Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user. 15 1 read-only 0 Indicate the transmit control bit is disabled #0 1 Indicate the transfer control bit is active #1 SSACTIF Slave Select Active Interrupt Status Note: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 Slave select active interrupt is clear or not occur #0 1 Slave select active interrupt event has occur #1 SSINAIF Slave Select Inactive Interrupt Status Note: This bit will be cleared by writing 1 to itself. 3 1 read-write 0 Slave select inactive interrupt is clear or not occur #0 1 Slave select inactive interrupt event has occur #1 SSLINE Slave Select Line Bus Status (Read Only) Note: If SPI_SSCTL.SSLVL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 Indicates the slave select line bus status is 0 #0 1 Indicates the slave select line bus status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST FIFO CLR Status (Read Only) Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done. 23 1 read-only 0 Done the FIFO buffer clear function of TXRST and RXRST #0 1 Doing the FIFO buffer clear function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Status (Read Only) 18 1 read-only 0 The valid data count of the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Slave Transmit FIFO Under-run Interrupt Status (Read Only) When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set. Note: This bit will be cleared by writing 1 to itself. 19 1 read-only UNITIF Unit Transfer Interrupt Status Note: This bit will be cleared by writing 1 to itself. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPI_TX SPI_TX FIFO Data Transmit Register 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register. For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0x1C registers n 0x20 0x4 registers n 0x30 0x8 registers n SPI_BIST SPI_BIST SPI BIST Control Register 0x34 -1 read-write n 0x0 0x0 RXBISTEF SPI RX SRAM BIST Fail Flag 2 1 read-write 0 SPI RX SRAM BIST pass #0 1 SPI RX SRAM BIST fail #1 RXBISTEN SPI RX SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for ADC SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 SPI RX SRAM BIST Disabled #0 1 SPI RX SRAM BIST Enabled #1 RXBISTEND SPI RX SRAM BIST Test Finish 1 1 read-write 0 SPI RX SRAM BIST active #0 1 SPI RX SRAM BIST finish #1 TXBISTEF SPI TX SRAM BIST Fail Flag 6 1 read-write 0 SPI TX SRAM BIST pass #0 1 SPI TX SRAM BIST fail #1 TXBISTEN SPI TX SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for ADC SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 SPI TX SRAM BIST Disabled #0 1 SPI TX SRAM BIST Enabled #1 TXBISTEND SPI TX SRAM BIST Test Finish 5 1 read-write 0 SPI TX SRAM BIST active #0 1 SPI TX SRAM BIST finish #1 SPI_CLKDIV SPI_CLKDIV Clock Divider Register (Master Only) 0x4 -1 read-write n 0x0 0x0 DIVIDER Clock Divider Register The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. where Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control, CLKSEL1 register. Note: SPI engine clock must smaller than PCLK/2 0 8 read-write SPI_CTL SPI_CTL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity 3 1 read-write 0 SCLK idle low #0 1 SCLK idle high #1 DUALIOEN Dual I/O Mode Enable 21 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 DWIDTH DWIDTH - Data Word Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. 8 5 read-write IE Unit Transfer Interrupt Enable 17 1 read-write 0 Disable SPI Unit Transfer Interrupt #0 1 Enable SPI Unit Transfer Interrupt to CPU #1 LSB LSB First Note: For DUAL and QUAD transactions with LSB must be set to 0. 13 1 read-write 0 The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field) #0 1 The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX) #1 QDIODIR Quad or Dual I/O Mode Direction Control 20 1 read-write 0 Quad or Dual Input mode #0 1 Quad or Dual Output mode #1 QUADIOEN Quad I/O Mode Enable 22 1 read-write 0 Quad I/O mode Disabled #0 1 Quad I/O mode Enabled #1 REORDER Byte Reorder Function Enable Note: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. REORDER is only available for Receive mode in DUAL and QUAD transactions. For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0. 19 1 read-write 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXMODEEN FIFO Receive Mode Enable 24 1 read-write 0 Disable function #0 1 Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0 #1 RXNEG Receive at Negative Edge 1 1 read-write 0 The received data input signal is latched at the rising edge of SCLK #0 1 The received data input signal is latched at the falling edge of SCLK #1 RXTCNTEN DMA Receive Transaction Count Enable 23 1 read-write 0 Disable function #0 1 Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller #1 SLAVE Master Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Enable In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to 1. Note: All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG, RXNEG, DWIDTH, LSB, CLKP, and so on). 0 1 read-write 0 Disable SPI Transfer #0 1 Enable SPI Transfer #1 SUSPITV Suspend Interval (Master Only) The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and QUAD mode transactions. (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle Example: Note: For DUAL and QUAD transactions with SUSPITV must be set to 0. 4 4 read-write TWOBIT Two Bits Transfer Mode When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 16 1 read-write 0 Disable two-bit transfer mode #0 1 Enable two-bit transfer mode #1 TXNEG Transmit at Negative Edge 2 1 read-write 0 The transmitted data output signal is changed at the rising edge of SCLK #0 1 The transmitted data output signal is changed at the falling edge of SCLK #1 SPI_FIFOCTL SPI_FIFOCTL FIFO Control/Status Register 0x10 -1 read-write n 0x0 0x0 RXOVIEN Receive FIFO Overrun Interrupt Enable 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Clear Receive FIFO Buffer Note: If there is slave receive time out event, the RXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled. 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1 #1 RXTH Receive FIFO Threshold If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 000: 1 word will transmit 001: 2 word will transmit 010: 3 word will transmit 011: 4 word will transmit 100: 5 word will transmit 101: 6 word will transmit 110: 7 word will transmit 111: 8 word will transmit 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXRST Clear Transmit FIFO Buffer Note: If there is slave receive time out event, the TXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled. 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1 #1 TXTH Transmit FIFO Threshold If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 000: 1 word will transmit 001: 2 word will transmit 010: 3 word will transmit 011: 4 word will transmit 100: 5 word will transmit 101: 6 word will transmit 110: 7 word will transmit 111: 8 word will transmit 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUDFIEN Slave Transmit Under Run Interrupt Enable 7 1 read-write 0 Slave Transmit FIFO under-run interrupt Disabled #0 1 Slave Transmit FIFO under-run interrupt Enabled #1 TXUDFPOL Transmit Under-run Data Out Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data. Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time to report the transmit under-run data out. 6 1 read-write 0 The SPI data out is 0 if there is transmit under-run event in Slave mode #0 1 The SPI data out is 1 if there is transmit under-run event in Slave mode #1 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0xC -1 read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically #1 RXPDMAEN Receive PDMA Enable Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done. 1 1 read-write TXPDMAEN Transmit DMA Enable Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done. 0 1 read-write SPI_RX SPI_RX FIFO Data Receive Register 0x30 -1 read-only n 0x0 0x0 RX Data Receive Register A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register. 0 32 read-only SPI_RXTSNCNT SPI_RXTSNCNT Receive Transaction Count Register 0x18 -1 read-write n 0x0 0x0 RXTSNCNT DMA Receive Transaction Count When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate. 0 16 read-write SPI_SSCTL SPI_SSCTL Slave Select Register 0x8 -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI_SSCTL[1:0] #0 1 If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 SLV3WIRE Slave 3-wire Mode Enable This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI. 4 1 read-write 0 4-wire bi-directional interface #0 1 3-wire bi-directional interface #1 SLVBCEIEN Slave Mode Error 0 Interrupt Enable 8 1 read-write 0 Slave mode error 0 interrupt Disable #0 1 Slave mode error 0 interrupt Enable #1 SLVTOCNT Slave Mode Time-out Period In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled. 16 16 read-write SLVTOIEN Slave Mode Time-out Interrupt Enable 5 1 read-write 0 Slave mode time-out interrupt Disabled #0 1 Slave mode time-out interrupt Enabled #1 SLVTORST Slave Mode Time-out FIFO Clear 6 1 read-write 0 Function disabled #0 1 Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event #1 SLVUDRIEN Slave Mode Error 1 Interrupt Enable 9 1 read-write 0 Slave mode error 1 interrupt Disable #0 1 Slave mode error 1 interrupt Enable #1 SS Slave Select Control Bits (Master Only) If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SSLVL. Note: SPI_SS0 is defined as the slave select input in Slave mode. 0 2 read-write SSACTIEN Slave Select Active Interrupt Enable 12 1 read-write 0 Slave select active interrupt Disable #0 1 Slave select active interrupt Enable #1 SSINAIEN Slave Select Inactive Interrupt Enable 13 1 read-write 0 Slave select inactive interrupt Disable #0 1 Slave select inactive interrupt Enable #1 SSLVL Slave Select Active Level This bit defines the active status of slave select signal (SPI_SS0/1). 2 1 read-write 0 The slave select signal SPI_SS0/1 is active on low-level/falling-edge #0 1 The slave select signal SPI_SS0/1 is active on high-level/rising-edge #1 SPI_STATUS SPI_STATUS Status Register 0x14 -1 read-write n 0x0 0x0 BUSY SPI Unit Bus Status (Read Only) 0 1 read-only 0 No transaction in the SPI bus #0 1 SPI controller unit is in busy state #1 RXCNT Receive FIFO Data Count (Read Only) This bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Status When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. Note: This bit will be cleared by writing 1 to itself. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Status (Read Only) 10 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Status Note: This bit will be cleared by writing 1 to itself. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Error 0 Interrupt Status (Read Only) In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state. Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state. 6 1 read-only 0 No Slave mode error 0 event #0 1 Slave mode error 0 occurs #1 SLVTOIF Slave Time-out Interrupt Status (Read Only) When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active. Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period. 5 1 read-only 0 Slave time-out is not active #0 1 Slave time-out is active #1 SLVURIF Slave Mode Error 1 Interrupt Status (Read Only) In Slave mode, transmit under-run occurs when the slave select line goes to inactive state. 7 1 read-only 0 No Slave mode error 1 event #0 1 Slave mode error 1 occurs #1 SPIENSTS SPI Enable Bit Status (Read Only) Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user. 15 1 read-only 0 Indicate the transmit control bit is disabled #0 1 Indicate the transfer control bit is active #1 SSACTIF Slave Select Active Interrupt Status Note: This bit will be cleared by writing 1 to itself. 2 1 read-write 0 Slave select active interrupt is clear or not occur #0 1 Slave select active interrupt event has occur #1 SSINAIF Slave Select Inactive Interrupt Status Note: This bit will be cleared by writing 1 to itself. 3 1 read-write 0 Slave select inactive interrupt is clear or not occur #0 1 Slave select inactive interrupt event has occur #1 SSLINE Slave Select Line Bus Status (Read Only) Note: If SPI_SSCTL.SSLVL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 Indicates the slave select line bus status is 0 #0 1 Indicates the slave select line bus status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only) This bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST FIFO CLR Status (Read Only) Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done. 23 1 read-only 0 Done the FIFO buffer clear function of TXRST and RXRST #0 1 Doing the FIFO buffer clear function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Status (Read Only) 18 1 read-only 0 The valid data count of the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Slave Transmit FIFO Under-run Interrupt Status (Read Only) When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set. Note: This bit will be cleared by writing 1 to itself. 19 1 read-only UNITIF Unit Transfer Interrupt Status Note: This bit will be cleared by writing 1 to itself. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPI_TX SPI_TX FIFO Data Transmit Register 0x20 -1 write-only n 0x0 0x0 TX Data Transmit Register A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register. For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x10 registers n 0x110 0x14 registers n 0x130 0x14 registers n 0x150 0x4 registers n 0x18 0x18 registers n 0x1F0 0x8 registers n 0x40 0x10 registers n 0x54 0xC registers n 0x64 0xC registers n 0x74 0xC registers n 0xD0 0x8 registers n 0xF0 0x14 registers n BGAPTRIM SYS_BGAPTRIM Bandgap Trim Control Register 0x140 -1 read-write n 0x0 0x0 TM Bandgap test modes Bandgap output to IO(TBD) enable 7 1 read-write 0 Disable #0 1 Enable #1 TRIM 4 bit trim for Bandgap. 0 4 read-write BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODEN Brown-Out Detector Threshold Voltage Selection Extension (Initialized and Protected Bit) The default value is set by flash controller as inverse of user configuration CBODEN bit (config0 [20]). 0 1 read-write 0 Brown-Out Detector function is disabled #0 1 Brown-Out Detector function enabled #1 BODHYS Brown-Out Detector Hysteresis (Initialized and Protected Bit) The default value is set by flash controller user configuration CBOV [4] bit (config0 [26]). 6 1 read-write 0 No hysteresis on BOD detection #0 1 BOD hysteresis enabled #1 BODINT Brown-Out Dectector Interrupt 8 1 read-write 1 indicates BOD_INT is active. Write 1 to clear #1 BODLVL Brown-Out Detector Threshold Voltage Selection (Initialized and Protected Bit) 2 4 read-write BODOUT Brown-Out Detector Output State 7 1 read-write 0 Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting #0 1 Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting #1 BODRSTEN Brown-Out Detector Reset or Interrupt Bit (Initialized and Protected Bit) The default value is set by flash controller as inverse of user configuration CBORST bit (config0 [21]). When the BOD is enabled and the interrupt is asserted, the interrupt will be kept till the BOD is disabled. The interrupt for CPU can be blocked either by disabling the interrupt in the NVIC or by disabling the interrupt source by disabling the BOD. BOD can then be re-enabled as required. 1 1 read-write 0 Brown-Out Detector generate an interrupt #0 1 Brown-Out Detector will reset chip #1 LVREN Low Voltage Reset (LVR) Enable (Initialized and Protected Bit) The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config 0[27]. 16 1 read-write 0 Disable LVR function #0 1 Enable LVR function #1 LVRFILTER Default value is 00. 17 2 read-write 0 LVR output will be filtered by 1 HCLK #00 1 LVR output will be filtered by 2 HCLK #01 2 LVR output will be filtered by 8 HCLK #10 3 LVR output will be filtered by 15 HCLK #11 DEVICEID SYS_DEVICEID Device ID Register 0xF4 -1 read-only n 0x0 0x0 DEVICEID Device ID Data This register provides specific read-only information for the Device ID 0 16 read-only FPGADAT SYS_FPGADAT FPGA Date Register 0x1F0 -1 read-only n 0x0 0x0 DATE FPGA Date register This register provides the FPGA date 0 32 read-only FPGAVER SYS_FPGAVER FPGA Version Register 0x1F4 -1 read-only n 0x0 0x0 VERSION FPGA Version register This register provides the FPGA version 0 32 read-only GPA_HR SYS_GPA_HR PA.15 ~ PA.0 Pull Resistance Select Control Register 0x48 -1 read-write n 0x0 0x0 PUHR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 GPA_IEN SYS_GPA_IEN PA.15 ~ PA.0 Digital and Analog Input Buffer Control Register 0x4C -1 read-write n 0x0 0x0 IEN 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPA_MFP SYS_GPA_MFP GPIO PA Multiple Alternate Functions and Input Type Control Register 0x20 -1 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 2 read-write PA10MFP PA.10 Multi-function Pin Selection 20 2 read-write PA11MFP PA.11 Multi-function Pin Selection 22 2 read-write PA12MFP PA.12 Multi-function Pin Selection 24 2 read-write PA13MFP PA.13 Multi-function Pin Selection 26 2 read-write PA14MFP PA.14 Multi-function Pin Selection 28 2 read-write PA15MFP PA.15 Multi-function Pin Selection 30 2 read-write PA1MFP PA.1 Multi-function Pin Selection 2 2 read-write PA2MFP PA.2 Multi-function Pin Selection 4 2 read-write PA3MFP PA.3 Multi-function Pin Selection 6 2 read-write PA4MFP PA.4 Multi-function Pin Selection 8 2 read-write PA5MFP PA.5 Multi-function Pin Selection 10 2 read-write PA6MFP PA.6 Multi-function Pin Selection 12 2 read-write PA7MFP PA.7 Multi-function Pin Selection 14 2 read-write PA8MFP PA.8 Multi-function Pin Selection 16 2 read-write PA9MFP PA.9 Multi-function Pin Selection 18 2 read-write GPA_PULL SYS_GPA_PULL PA.15 ~ PA.0 Pull Resistance Control Register 0x44 -1 read-write n 0x0 0x0 PUEN0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPB_HR SYS_GPB_HR PB.1 ~ PB.0 Pull Resistance Select Control Register 0x58 -1 read-write n 0x0 0x0 PUHR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 GPB_IEN SYS_GPB_IEN PB.1 ~ PB.0 Digital Input Buffer Control Register 0x5C -1 read-write n 0x0 0x0 IEN0 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 IEN1 1 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPB_MFP SYS_GPB_MFP GPIO PB Multiple Alternate Functions and Input Type Control Register 0x24 -1 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 2 read-write PB1MFP PB.1 Multi-function Pin Selection 2 2 read-write GPB_PULL SYS_GPB_PULL PB.1 ~ PB.0 Pull Resistance Control Register 0x54 -1 read-write n 0x0 0x0 PUEN0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPC_HR SYS_GPC_HR PC.15 ~ PC.0 Pull Resistance Select Control Register 0x68 -1 read-write n 0x0 0x0 PUHR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 GPC_IEN SYS_GPC_IEN PC.15 ~ PC.0 Digital Input Buffer Control Register 0x6C -1 read-write n 0x0 0x0 IEN 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPC_MFP SYS_GPC_MFP GPIO PC Multiple Alternate Functions and Input Type Control Register 0x28 -1 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 2 read-write PC10MFP PC.10 Multi-function Pin Selection 20 2 read-write PC11MFP PC.11 Multi-function Pin Selection 22 2 read-write PC12MFP PC.12 Multi-function Pin Selection 24 2 read-write PC13MFP PC.13 Multi-function Pin Selection 26 2 read-write PC14MFP PC.14 Multi-function Pin Selection 28 2 read-write PC15MFP PC.15 Multi-function Pin Selection 30 2 read-write PC1MFP PC.1 Multi-function Pin Selection 2 2 read-write PC2MFP PC.2 Multi-function Pin Selection 4 2 read-write PC3MFP PC.3 Multi-function Pin Selection 6 2 read-write PC4MFP PC.4 Multi-function Pin Selection 8 2 read-write PC5MFP PC.5 Multi-function Pin Selection 10 2 read-write PC6MFP PC.6 Multi-function Pin Selection 12 2 read-write PC7MFP PC.7 Multi-function Pin Selection 14 2 read-write PC8MFP PC.8 Multi-function Pin Selection 16 2 read-write PC9MFP PC.9 Multi-function Pin Selection 18 2 read-write GPC_PULL SYS_GPC_PULL PC.15 ~ PC.0 Pull Resistance Control Register 0x64 -1 read-write n 0x0 0x0 PUEN0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPD_HR SYS_GPD_HR PD.15 ~ PD.0 Pull Resistance Select Control Register 0x78 -1 read-write n 0x0 0x0 PUHR0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 PUHR9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up 100K resistance #0 1 Pull-Up 1M resistance #1 GPD_IEN SYS_GPD_IEN PD.15 ~ PD.0 Digital Input Buffer Control Register 0x7C -1 read-write n 0x0 0x0 IEN 0 1 read-write 0 Input buffer Enabled #0 1 Input buffer disabled, and input signal always equals to 0 #1 GPD_MFP SYS_GPD_MFP GPIO PD Multiple Alternate Functions and Input Type Control Register 0x2C -1 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 2 read-write PD10MFP PD.10 Multi-function Pin Selection 20 2 read-write PD11MFP PD.11 Multi-function Pin Selection 22 2 read-write PD12MFP PD.12 Multi-function Pin Selection 24 2 read-write PD13MFP PD.13 Multi-function Pin Selection 26 2 read-write PD14MFP PD.14 Multi-function Pin Selection 28 2 read-write PD15MFP PD.15 Multi-function Pin Selection 30 2 read-write PD1MFP PD.1 Multi-function Pin Selection 2 2 read-write PD2MFP PD.2 Multi-function Pin Selection 4 2 read-write PD3MFP PC.3 Multi-function Pin Selection 6 2 read-write PD4MFP PC.4 Multi-function Pin Selection 8 2 read-write PD5MFP PD.5 Multi-function Pin Selection 10 2 read-write PD6MFP PD.6 Multi-function Pin Selection 12 2 read-write PD7MFP PD.7 Multi-function Pin Selection 14 2 read-write PD8MFP PD.8 Multi-function Pin Selection 16 2 read-write PD9MFP PD.9 Multi-function Pin Selection 18 2 read-write GPD_PULL SYS_GPD_PULL PD.15 ~ PD.0 Pull Resistance Control Register 0x74 -1 read-write n 0x0 0x0 PUEN0 This function only for the GPIO Px[n] pin as an INPUT mode. 0 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN1 This function only for the GPIO Px[n] pin as an INPUT mode. 1 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN10 This function only for the GPIO Px[n] pin as an INPUT mode. 10 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN11 This function only for the GPIO Px[n] pin as an INPUT mode. 11 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN12 This function only for the GPIO Px[n] pin as an INPUT mode. 12 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN13 This function only for the GPIO Px[n] pin as an INPUT mode. 13 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN14 This function only for the GPIO Px[n] pin as an INPUT mode. 14 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN15 This function only for the GPIO Px[n] pin as an INPUT mode. 15 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN2 This function only for the GPIO Px[n] pin as an INPUT mode. 2 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN3 This function only for the GPIO Px[n] pin as an INPUT mode. 3 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN4 This function only for the GPIO Px[n] pin as an INPUT mode. 4 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN5 This function only for the GPIO Px[n] pin as an INPUT mode. 5 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN6 This function only for the GPIO Px[n] pin as an INPUT mode. 6 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN7 This function only for the GPIO Px[n] pin as an INPUT mode. 7 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN8 This function only for the GPIO Px[n] pin as an INPUT mode. 8 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 PUEN9 This function only for the GPIO Px[n] pin as an INPUT mode. 9 1 read-write 0 Pull-Up function Disable #0 1 Pull-Up function Enable #1 GPIO_INTP SYS_GPIO_INTP GPIO Input Type and Slew Rate Control 0x40 -1 read-write n 0x0 0x0 GPxSSGPxHS This register controls whether the GPIO input buffer Schmitt trigger is enabled and whether high or low slew rate is selected for output driver. 0 14 read-write IMGMAP0 SYS_IMGMAP0 MAP0 Data Image Register 0xF8 -1 read-only n 0x0 0x0 IMG0 Data Image of MAP0 Data in MAP0 of information block are copied to this register after power on. 0 32 read-only IMGMAP1 SYS_IMGMAP1 MAP1 Data Image Register 0xFC -1 read-only n 0x0 0x0 IMG1 Data Image of MAP1 Data in MAP1 of information block are copied to this register after power on. 0 32 read-only IMGMAP3 SYS_IMGMAP3 MAP3 Data Image Register 0xF0 -1 read-only n 0x0 0x0 IMG3 Data Image of MAP3 Data in MAP3 of information block are copied to this register after power on. 0 32 read-only IPRST0 SYS_IPRST0 IP Reset Control Resister0 0x8 -1 read-write n 0x0 0x0 CHIPRST CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles. CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPURST CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller (FMC), this bit will automatically return to 0 after the 2 clock cycles 1 1 read-write 0 Normal #0 1 Reset CPU #1 IPRST1 SYS_IPRST1 IP Reset Control Resister1 0xC -1 read-write n 0x0 0x0 ANARST Analog Block Controller Reset 31 1 read-write 0 Normal Operation #0 1 Reset #1 BIQRST BIQ Controller Reset 18 1 read-write 0 Normal Operation #0 1 Reset #1 CPDRST Companding Controller Reset 6 1 read-write 0 Normal operation #0 1 Reset #1 DACRST DAC Controller Reset 29 1 read-write 0 Normal Operation #0 1 Reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 Normal operation #0 1 Reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 Normal operation #0 1 Reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 Normal operation #0 1 Reset #1 I2SRST I2S Controller Reset 13 1 read-write 0 Normal Operation #0 1 Reset #1 PDMARST PDMA Controller Reset 7 1 read-write 0 Normal operation #0 1 Reset #1 PWM0RST PWM0 Controller Reset 20 1 read-write 0 Normal Operation #0 1 Reset #1 PWM1RST PWM1 Controller Reset 21 1 read-write 0 Normal Operation #0 1 Reset #1 SARADCRST SARADC Controller Reset 28 1 read-write 0 Normal Operation #0 1 Reset #1 SDADCRST SDADC Controller Reset 30 1 read-write 0 Normal Operation #0 1 Reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 Normal Operation #0 1 Reset #1 SPI1RST SPI1 Controller Reset 11 1 read-write 0 Normal Operation #0 1 Reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Normal Operation #0 1 Reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Normal Operation #0 1 Reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Normal operation #0 1 Reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 Normal Operation #0 1 Reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 Normal Operation #0 1 Reset #1 USBRST USB Controller Reset 24 1 read-write 0 Normal Operation #0 1 Reset #1 IRCTCKRF SYS_IRCTCKRF HIRC Trim Clock Reference Frequency Register 0x13C -1 read-write n 0x0 0x0 HXTFREQ HIRC Trim reference clock frequency value when reference clock from HXT User can insert the HXT frequency on PCB to this register for internal trim. The insert frequency value is unit KHz. For example: Note1: The HXT frequency register should set correct value before HIRC auto trim enable. Note2: It recommends the HXT should be multiple of 4MHz or 4.096MHz. 0 15 read-write IRCTCTL SYS_IRCTCTL HIRC Trim Control Register 0x130 -1 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection This field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 48 MHz #01 2 Disable HIRC auto trim function #10 3 Enable HIRC auto trim function and trim HIRC to 49.152 MHz #11 IGNORE Ignore HIRC Unstable Period Selection Note: For the current version of HIRC, its clock frequency will shift when trim bits change from 0 to 1 or 1 to 0. To solve this problem, RC_TRIM ignore the counting clock of unstable HIRC clock period to prevent trim bit Inaccuracies. 11 1 read-write 0 Enable function of ignoring the counting cycles in HIRC unstable period #0 1 Disable function of ignoring the counting cycles in HIRC unstable period #1 LOOPSEL Trim Calculation Loop Selection This field defines that trim value calculation is based on how many internal reference clocks. Note1: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. Note2: If source clock from HXT , the internal reference clock is 32 KHz If source clock from SOF , the internal reference clock is 1 KHz. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection Note: HIRC trim reference clock is 20K Hz in test mode 10 1 read-write 0 HIRC trim reference clock is from HXT (4~24.576 MHz) #0 1 HIRC trim reference clock USB SOF (Start-Of-Frame) packet #1 RETRYCNT Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0x134 -1 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF (SYS_IRCTSTS [2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF (SYS_IRCTSTS [2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL (SYS_IRCTCTL [1:0]). If this bit is high and TFAILIF (SYS_IRCTSTS [1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF (SYS_IRCTSTS [1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0x138 -1 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status When the frequency of external high speed crystal oscillator (HXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRCTCL [1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRCTCTL [8]) is set to 1. If this bit is set and CLKEIEN (SYS_IRCTIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. 0 1 read-write 0 The internal high-speed oscillator frequency doesn't lock at target frequency yet #0 1 The internal high-speed oscillator frequency locked at target frequency #1 TFAILIF Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRCTCTL [1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN (SYS_IRCTIEN [1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 OSC10K SYS_OSC10K 10KHz Oscillator and Bias Trim Register 0x114 -1 read-write n 0x0 0x0 OSC10K_TRIM 23bit trim for 10 KHz oscillator. 0 23 read-write TM_REG Analog test modes 24 4 read-write TRM_CLK Must be toggled to load a new OSC10K_TRIM 31 1 read-write OSCTRIM SYS_OSCTRIM Internal Oscillator Trim Register 0x110 -1 read-write n 0x0 0x0 EN2MHZ 1: High frequency mode (20-50 MHz) 0: Low Frequency mode of oscillator active (2 MHz). 15 1 read-write TRIM 10 bit trim for oscillator, 0 10 read-write OSC_TRIM0 SYS_OSC_TRIM0 Oscillator Frequency Adjustment Control Register 0x118 -1 read-write n 0x0 0x0 EN2MHZ 1: High frequency mode (20-50 MHz) 0: Low Frequency mode of oscillator active (2 MHz). 31 1 read-write TC Temperature compensation setting. Set by factory 16 5 read-write TRIM 16bit sign extended representation of 10bit trim. SYS_OSC_TRIM[n] load from factory trim value after reset. One of SYS_OSC_TRIM[n] will map to SYS_OSCTRIM base on OSCFSEL 0 16 read-write OSC_TRIM1 SYS_OSC_TRIM1 Oscillator Frequency Adjustment Control Register 0x11C -1 read-write n 0x0 0x0 OSC_TRIM2 SYS_OSC_TRIM2 Oscillator Frequency Adjustment Control Register 0x120 -1 read-write n 0x0 0x0 PDID SYS_PDID Product Identifier Register 0x0 -1 read-only n 0x0 0x0 IMG2 Product Identifier Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton. 0 32 read-only PORCTL SYS_PORCTL Power-On-reset Controller Register 0x1C -1 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protected) When power is applied to device, the POR circuit generates a reset signal to reset the entire chip function. Noise on the power may cause the POR to become active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note1: This bit does write protected. Refer to the SYS_REGLCTL register. Note2: This function will not work under DPD mode. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 -1 read-write n 0x0 0x0 SYS_REGLCTL_REGLCTL Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Protected Register Lock/Unlock Index (Read Only) 0 8 write-only 0 Protected registers are locked. Any write to the target register is ignored 0 1 Protected registers are unlocked 1 RSTSTS SYS_RSTSTS System Reset Source Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown Out Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 BOD controller had issued the reset signal to reset the system #1 LVRF LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: If power rising reach 1.6V under 20us when fast power on, the LVRF will not happen. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF nRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PINWK Wakeup from DPD From PIN The device was woken from Deep Power Down by a low transition on the RESETn pin. Note: Write 1 to this register to clear all wakeup flags. 8 1 read-write 0 No wakeup from RESETn pin #0 1 The device was issued a wakeup from DPD by a RESETn pin trasition #1 PMURSTF Reset Source From PMU The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 6 1 read-write 0 No reset from PMU #0 1 The PMU has issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR #0 1 Power-on Reset (POR) Controller had issued the reset signal to reset the system #1 PORWK Wakeup from DPD From POR The device was woken from Deep Power Down by a Power On Reset. 10 1 read-write 0 No wakeup from POR #0 1 The device was issued a wakeup from DPD by a POR #1 TIMWK Wakeup from DPD From TIMER The device was woken from Deep Power Down by count of 10 KHz timer. 9 1 read-write 0 No wakeup from TIMER #0 1 The device was issued a wakeup from DPD by a TIMER event #1 WDTRF Reset Source From WDG The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. Note: Write 1 to clear this bit to 0. 2 1 read-write 0 No reset from Watch-Dog #0 1 The Watch-Dog module issued the reset signal to reset the system #1 SRAM_BISTCTL SYS_SRAM_BISTCTL System SRAM BIST Test Control Register 0xD0 -1 read-write n 0x0 0x0 CACHEBIST CACHE SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for CACHE SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 CACHE SRAM BIST Disabled #0 1 CACHE SRAM BIST Enabled #1 SRAMBIST SRAM BIST Enable Bit (Write Protect) This bit enables BIST test for SRAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 system SRAM BIST Disabled #0 1 system SRAM BIST Enabled #1 SRAM_BISTSTS SYS_SRAM_BISTSTS System SRAM BIST Test Status Register 0xD4 -1 read-only n 0x0 0x0 CACHEBEND CACHE SRAM BIST Test Finish 18 1 read-only 0 CACHE SRAM BIST is active #0 1 CACHE SRAM BIST finish #1 CACHEBISTEF CACHE SRAM BIST Fail Flag 2 1 read-only 0 CACHE SRAM BIST test pass #0 1 CACHE SRAM BIST test fail #1 SRAMBEND System SRAM BIST Test Finish 16 1 read-only 0 system SRAM BIST active #0 1 system SRAM BIST finish #1 SRAMBISTEF System SRAM BIST Fail Flag 0 1 read-only 0 system SRAM BIST test pass #0 1 system SRAM BIST test fail #1 UCIDn SYS_UCIDn Specified ID Register for Library and Customized Feature Checking 0x150 -1 read-only n 0x0 0x0 UCID UCID Value This register provides specific read-only information for the UCID 0 32 read-only SYSINFO SYSINFO Register Map SYSINFO 0x0 0x0 0x8 registers n 0x1C 0x8 registers n 0xC 0x8 registers n AIRCTL SYSINFO_AIRCTL Application Interrupt and Reset Control Register 0xC -1 read-write n 0x0 0x0 CLRACTVT Clear All Active Vector Clears all active state information for fixed and configurable exceptions. The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE. 1 1 read-write 0 do not clear state information #0 1 clear state information #1 ENDIANES Endianness Read Only. Reads 0 indicating little endian machine. 15 1 read-write SRSTREQ System Reset Request Writing 1 to this bit asserts a signal to request a reset by the external system. 2 1 read-write 0 do not request a reset #0 1 request reset #1 VTKEY Vector Key The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE. 16 16 read-write CPUID SYSINFO_CPUID CPUID Base Register 0x0 -1 read-only n 0x0 0x0 IMPCODE Implementer Code Assigned by ARM 24 8 read-only PART ARMv6-m Parts Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number Reads as 0xC20. 4 12 read-only REVISION Revision Reads as 0x0 0 4 read-only ICSR SYSINFO_ICSR Interrupt Control State Register 0x4 -1 read-write n 0x0 0x0 ISRPEND ISR Pending Indicates if an external configurable (NVIC generated) interrupt is pending. 22 1 read-write ISRPREEM ISR Preemptive If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-write NMIPNSET NMI Pending Set Control Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 31 1 read-write PPSVICLR Clear a Pending PendSV Interrupt Write 1 to clear a pending PendSV interrupt. 27 1 read-write PPSVISET Set a Pending PendSV Interrupt This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not). 28 1 read-write PSTKICLR Clear a Pending SYST Write 1 to clear a pending SYST. 25 1 read-write PSTKISET Set a Pending SYST Reads back with current state (1 if Pending, 0 if not). 26 1 read-write VTACT Vector Active 0: Thread mode Value > 1: the exception number for the current executing exception. 0 9 read-write VTPEND Vector Pending Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. 12 9 read-write SCR SYSINFO_SCR System Control Register 0x10 -1 read-write n 0x0 0x0 SEVNONPN Send Event on Pending Bit When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. 4 1 read-write 0 only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLPDEEP Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states. 2 1 read-write 0 sleep #0 1 deep sleep #1 SLPONEXC Sleep on Exception When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write SHPR2 SYSINFO_SHPR2 System Handler Priority Register 2 0x1C -1 read-write n 0x0 0x0 PRI11 Priority of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SHPR3 SYSINFO_SHPR3 System Handler Priority Register 3 0x20 -1 read-write n 0x0 0x0 PRI14 Priority of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority 22 2 read-write PRI15 Priority of System Handler 15 - SYST 0 denotes the highest priority and 3 denotes lowest priority 30 2 read-write SYSTICK SYSTICK Register Map SYSTICK 0x0 0x10 0xC registers n SYST_CSR SYST_CSR SYST Control and Status Register 0x10 -1 read-write n 0x0 0x0 CLKSRC Clock Source 2 1 read-write 0 Clock selected from CLK_CLKSEL0.STCLKSEL is used as clock source #0 1 Core clock used for SYST #1 COUNTFLAG Count Flag Returns 1 if timer counted to 0 since last time this register was read. 16 1 read-write 0 Cleared on read or by a write to the Current Value register #0 1 Set by a count transition from 1 to 0 #1 ENABLE ENABLE 0 1 read-write 0 The counter is disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT Enables SYST Exception Request 1 1 read-write 0 Counting down to 0 does not cause the SYST exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause SYST exception to be pended. Clearing the SYST Current Value register by a register write in software will not cause SYST to be pended #1 SYST_CVR SYST_CVR SYST Current Value Register 0x18 -1 read-write n 0x0 0x0 CURRENT Current Counter Value This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit. 0 24 read-write SYST_RVR SYST_RVR SYST Reload Value Register 0x14 -1 read-write n 0x0 0x0 RELOAD SYST Reload Value to load into the Current Value register when the counter reaches 0. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SYST interrupt is required every 200 clock pulses, set RELOAD to 199. 0 24 read-write TMR TMR Register Map TMR 0x0 0x0 0x10 registers n 0x20 0x10 registers n 0x34 0x4 registers n 0x40 0x10 registers n IR_CTL IR_CTL IR Carrier Output Control Register 0x34 -1 read-write n 0x0 0x0 IRCEN IR carrier output enable 1 1 read-write 0 Disable IR carrier output, #0 1 Enable IR carrier output. Timer1 time out will toggle the output state on IROUT pin #1 NONCS Non-carrier state 0 1 read-write 0 IROUT keeps low when IRCEN is 0, #0 1 IROUT keeps high when IRCEN is 0 #1 TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 -1 read-write n 0x0 0x0 CMPDAT Timer Comparison Value CMPDAT is a 16-bit comparison register. When the 16-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer out flag (TIF) is requested. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly. Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count. 0 16 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC -1 read-only n 0x0 0x0 CNT Timer Data Register User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1, 0 16 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only) This bit indicates the counter status of Timer. 25 1 read-only 0 Timer is not active #0 1 Timer is active #1 CNTEN Counter Enable Bit 30 1 read-write 0 Stop/Suspend counting #0 1 Start counting #1 INTEN Interrupt Enable Bit If timer interrupt is enabled, and time-out flag (TIF) is 1'b .The timer asserts its interrupt signal to CPU. 29 1 read-write 0 Disable TIMER Interrupt #0 1 Enable TIMER Interrupt #1 OPMODE Timer Operating Mode Note: When changing the Timer Operating Mode, the CNTEN bit should be set to 0 disable first. 27 2 read-write 0 The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware #00 1 The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1) #01 2 Reserved #10 3 The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset #11 PSC Timer Clock Prescaler Note: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count. 0 8 read-write RSTCNT Counter Reset Bit Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0. 26 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 -1 read-write n 0x0 0x0 TIF Timer Interrupt Flag (Read Only) This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself 0 1 read-only 0 No effect #0 1 CNT (TIMERx_CNT [15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value #1 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 -1 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C -1 read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 -1 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 -1 read-write n 0x0 0x0 TIMER2_CMP TIMER2_CMP Timer2 Compare Register 0x44 -1 read-write n 0x0 0x0 TIMER2_CNT TIMER2_CNT Timer2 Data Register 0x4C -1 read-write n 0x0 0x0 TIMER2_CTL TIMER2_CTL Timer2 Control and Status Register 0x40 -1 read-write n 0x0 0x0 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x48 -1 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x28 registers n UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 Refer to Table 5.155 for more information. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 Refer to Table 5.155 for more information. NOTE: When in IrDA mode, this bit must disabled. 29 1 read-write 0 Disable divider X ( M = 16) #0 1 Enable divider X (M = EDIVM1+1, with EDIVM1 ≥8) #1 BRD Baud Rate Divider. Refer to Table 5.155 for more information. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit FIFO Register. 0x0 -1 read-write n 0x0 0x0 DAT Receive/Transmit FIFO Register Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first). By writing to this register, transmit data will be pushed onto the transmit FIFO. The UART will send out an 8-bit data through the Tx pin (LSB first). 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register. 0x8 -1 read-write n 0x0 0x0 RFITL Receive FIFO Interrupt (RDA_INT) Trigger Level 4 4 read-write RTSTRGLV RTS Trigger Level for Auto-flow Control 16 4 read-write RXRST Receive FIFO Reset When RFR is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the receive internal state machine and pointers #1 TXRST Transmit FIFO Reset When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the transmit internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag This bit is set to a logic 1 whenever the receive data input(Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit. 6 1 read-write FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),and is reset whenever the CPU writes 1 to this bit. 5 1 read-write PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. 4 1 read-write RXEMPTY Receive FIFO Empty(Read Only) This bit indicates whether the Rx FIFO is empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RXFULL Receive FIFO Full(Read Only) This bit indicates whether the Rx FIFO is full or not. This bit is set when RxFIFO is full otherwise it is cleared by hardware. 15 1 read-only RXOVIF Rx Overflow Error Interrupt Flag If the Rx FIFO (UART->DATA) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. Note: This bit is cleared by writing 1 to itself. 0 1 read-write RXPTR Rx FIFO pointer (Read Only) This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented. 8 6 read-only TXEMPTY Transmit FIFO Empty(Read Only) This bit indicates whether the Tx FIFO is empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty). 22 1 read-only TXEMPTYF Transmitter Empty (Read Only) Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. Note: This bit is read only. 28 1 read-only TXFULL Transmit FIFO Full(Read Only) This bit indicates whether the Tx FIFO is full or not. 23 1 read-only TXOVIF Tx Overflow Error Interrupt Flag If the Tx FIFO (UART->DATA) is full, an additional write to UART->DATA will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. Note: This bit is cleared by writing 1 to itself. 24 1 read-write TXPTR Tx FIFO Pointer (Read Only) This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the TxFIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented. 16 6 read-only UART_INTEN UART_INTEN UART Interrupt Enable Register. 0x4 -1 read-write n 0x0 0x0 ATOCTSEN CTS Auto Flow Control Enable When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is de-asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 ATORTSEN RTS Auto Flow Control Enable When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals FCR.RTS_TRIG_LEVEL, the UART will de-assert the RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 BUFERRIEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off BUF_ERR_INT #0 1 Enable IBUF_ERR_INT #1 DMARXEN Receive DMA Enable If enabled, the UART will request DMA service when data is available in receive FIFO. 15 1 read-write DMATXEN Transmit DMA Enable If enabled, the UART will request DMA service when space is available in transmit FIFO. 14 1 read-write MODEMIEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off MODEM_INT #0 1 Enable MODEM_INT #1 RDAIEN Receive Data Available Interrupt Enable. 0 1 read-write 0 Mask off RDA_INT #0 1 Enable RDA_INT #1 RLSIEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off RLS_INT #0 1 EnableRLS_INT #1 RXTOIEN Receive Time out Interrupt Enable 4 1 read-write 0 Mask off TOUT_INT #0 1 Enable TOUT_INT #1 THREIEN Transmit FIFO Register Empty Interrupt Enable 1 1 read-write 0 Mask off THRE_INT #0 1 Enable THRE_INT #1 TOCNTEN Time-Out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (FSR.TXOVIF or FSR.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If IER.BUFERRIEN is enabled a CPU interrupt request will be generated. Note: This bit is cleared when both FSR.TXOVIF and FSR.RXOVIF are cleared. 5 1 read-only BUFERRINT Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of IER.BUFERRIEN and BUFERRIF 13 1 read-write DBERRIF DMA MODE Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated. NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared. 21 1 read-only DBERRINT DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF. 29 1 read-write DMODIF DMA MODE MODEM Interrupt Flag (Read Only) NOTE: This bit is read only and reset when bit UART_MODEMSTS.DCTSF is cleared by a write 1. 19 1 read-only DMODINT DMA MODE MODEM Status Interrupt Indicator to Interrupt Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF. 27 1 read-write DRLSIF DMA MODE Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 18 1 read-only DRLSINT DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF. 26 1 read-write DRXTOIF DMA MODE Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.RXTOIEN is enabled a CPU interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it. 20 1 read-only DRXTOINT DMA MODE Time Out Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF. 28 1 read-write MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset when bit MSR.DCTSF is cleared by a write 1. 3 1 read-only MODEMINT MODEM Status Interrupt Indicator to Interrupt Logical AND of IER.MSIEN and MODEMIF 11 1 read-write RDAIF Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If IER.RDA_IEN is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL). 0 1 read-only RDAINT Receive Data Available Interrupt Indicator to Interrupt Controller Logical AND of IER.RDAIEN and RDAIF 8 1 read-write RLSIF Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity, framing or break error (at least one of, FSR.BIF, FSR.FEF and FSR.PEF, is set). If IER.RLS_IEN is enabled, the RLS interrupt will be generated. Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLSINT Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of IER.RLSIEN and RLSIF 10 1 read-write RXTOIF Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If IER.RXTOIEN is enabled a CPU interrupt request will be generated. Note: This bit is read only and user can read FIFO to clear it. 4 1 read-only RXTOINT Time Out Interrupt Indicator to Interrupt Controller Logical AND of IER.RXTOIEN and RXTOIF 12 1 read-write THREIF Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER.THRE_IEN is enabled, the THRE interrupt will be generated. Note: This bit is read only and it will be cleared when writing data into the Tx FIFO. 1 1 read-only THREINT Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller Logical AND of IER.THREIEN and THREIF 9 1 read-write UART_LINE UART_LINE UART Line Control Register. 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable This bit has effect only when PBE (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or checked in the data word and parity bits #0 1 Even number of logic 1's are transmitted or checked in the data word and parity bits #1 NSB Number of STOP bits 2 1 read-write 0 One STOP bit is generated after the transmitted data #0 1 Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable 3 1 read-write 0 Parity bit is not generated (transmit data) or checked (receive data) during transfer #0 1 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #1 SPE Stick Parity Enable 5 1 read-write 0 Disable stick parity #0 1 When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared #1 WLS Word Length Select 0 2 read-write UART_MODEM UART_MODEM UART Modem Control Register. 0x10 -1 read-write n 0x0 0x0 LBMEN Loopback Mode Enable. 4 1 read-write RTS RTS (Request-To-Send) Signal 1 1 read-write RTSACTLV Request-to-Send (RTS)Active Trigger Level This bit can change the RTS trigger level. 9 1 read-write 0 RTS is active high level #0 1 RTS is active low level #1 RTSSTS RTS Pin State(read only) This bit is the pin status of RTS. 13 1 read-only UART_MODEMSTS UART_MODEMSTS UART Modem Status Register. 0x14 -1 read-write n 0x0 0x0 CTSACTLV Clear-to-Send (CTS)Active Trigger Level This bit can change the CTS trigger level. 8 1 read-write 0 CTS is active high level #0 1 CTS is active low level #1 CTSDETF Detect CTS State Change Flag Note: This bit is cleared by writing 1 to itself. 0 1 read-write CTSSTS CTS Pin Status (read only) This bit is the pin status of CTS. 4 1 read-only UART_TOUT UART_TOUT UART Time Out Register 0x20 -1 read-write n 0x0 0x0 TOIC Time Out Interrupt Comparator The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter (TOIC) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if IER.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate. 0 7 read-write UART1 UART Register Map UART 0x0 0x0 0x28 registers n UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0 Refer to Table 5.155 for more information. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1 Refer to Table 5.155 for more information. NOTE: When in IrDA mode, this bit must disabled. 29 1 read-write 0 Disable divider X ( M = 16) #0 1 Enable divider X (M = EDIVM1+1, with EDIVM1 ≥8) #1 BRD Baud Rate Divider. Refer to Table 5.155 for more information. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit FIFO Register. 0x0 -1 read-write n 0x0 0x0 DAT Receive/Transmit FIFO Register Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first). By writing to this register, transmit data will be pushed onto the transmit FIFO. The UART will send out an 8-bit data through the Tx pin (LSB first). 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register. 0x8 -1 read-write n 0x0 0x0 RFITL Receive FIFO Interrupt (RDA_INT) Trigger Level 4 4 read-write RTSTRGLV RTS Trigger Level for Auto-flow Control 16 4 read-write RXRST Receive FIFO Reset When RFR is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 1 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the receive internal state machine and pointers #1 TXRST Transmit FIFO Reset When TFR is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset. Note: This bit will auto-clear after 3 UART engine clock cycles. 2 1 read-write 0 Writing 0 to this bit has no effect #0 1 Writing 1 to this bit will reset the transmit internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag This bit is set to a logic 1 whenever the receive data input(Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit. 6 1 read-write FEF Framing Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),and is reset whenever the CPU writes 1 to this bit. 5 1 read-write PEF Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. 4 1 read-write RXEMPTY Receive FIFO Empty(Read Only) This bit indicates whether the Rx FIFO is empty or not. When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RXFULL Receive FIFO Full(Read Only) This bit indicates whether the Rx FIFO is full or not. This bit is set when RxFIFO is full otherwise it is cleared by hardware. 15 1 read-only RXOVIF Rx Overflow Error Interrupt Flag If the Rx FIFO (UART->DATA) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. Note: This bit is cleared by writing 1 to itself. 0 1 read-write RXPTR Rx FIFO pointer (Read Only) This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented. 8 6 read-only TXEMPTY Transmit FIFO Empty(Read Only) This bit indicates whether the Tx FIFO is empty or not. When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty). 22 1 read-only TXEMPTYF Transmitter Empty (Read Only) Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted. Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed. Note: This bit is read only. 28 1 read-only TXFULL Transmit FIFO Full(Read Only) This bit indicates whether the Tx FIFO is full or not. 23 1 read-only TXOVIF Tx Overflow Error Interrupt Flag If the Tx FIFO (UART->DATA) is full, an additional write to UART->DATA will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled. Note: This bit is cleared by writing 1 to itself. 24 1 read-write TXPTR Tx FIFO Pointer (Read Only) This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the TxFIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented. 16 6 read-only UART_INTEN UART_INTEN UART Interrupt Enable Register. 0x4 -1 read-write n 0x0 0x0 ATOCTSEN CTS Auto Flow Control Enable When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is de-asserted). 13 1 read-write 0 Disable CTS auto flow control #0 1 Enable CTS auto flow control #1 ATORTSEN RTS Auto Flow Control Enable When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals FCR.RTS_TRIG_LEVEL, the UART will de-assert the RTS signal. 12 1 read-write 0 Disable RTS auto flow control #0 1 Enable RTS auto flow control #1 BUFERRIEN Buffer Error Interrupt Enable 5 1 read-write 0 Mask off BUF_ERR_INT #0 1 Enable IBUF_ERR_INT #1 DMARXEN Receive DMA Enable If enabled, the UART will request DMA service when data is available in receive FIFO. 15 1 read-write DMATXEN Transmit DMA Enable If enabled, the UART will request DMA service when space is available in transmit FIFO. 14 1 read-write MODEMIEN Modem Status Interrupt Enable 3 1 read-write 0 Mask off MODEM_INT #0 1 Enable MODEM_INT #1 RDAIEN Receive Data Available Interrupt Enable. 0 1 read-write 0 Mask off RDA_INT #0 1 Enable RDA_INT #1 RLSIEN Receive Line Status Interrupt Enable 2 1 read-write 0 Mask off RLS_INT #0 1 EnableRLS_INT #1 RXTOIEN Receive Time out Interrupt Enable 4 1 read-write 0 Mask off TOUT_INT #0 1 Enable TOUT_INT #1 THREIEN Transmit FIFO Register Empty Interrupt Enable 1 1 read-write 0 Mask off THRE_INT #0 1 Enable THRE_INT #1 TOCNTEN Time-Out Counter Enable 11 1 read-write 0 Disable Time-out counter #0 1 Enable Time-out counter #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (FSR.TXOVIF or FSR.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If IER.BUFERRIEN is enabled a CPU interrupt request will be generated. Note: This bit is cleared when both FSR.TXOVIF and FSR.RXOVIF are cleared. 5 1 read-only BUFERRINT Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of IER.BUFERRIEN and BUFERRIF 13 1 read-write DBERRIF DMA MODE Buffer Error Interrupt Flag (Read Only) This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated. NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared. 21 1 read-only DBERRINT DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF. 29 1 read-write DMODIF DMA MODE MODEM Interrupt Flag (Read Only) NOTE: This bit is read only and reset when bit UART_MODEMSTS.DCTSF is cleared by a write 1. 19 1 read-only DMODINT DMA MODE MODEM Status Interrupt Indicator to Interrupt Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF. 27 1 read-write DRLSIF DMA MODE Receive Line Status Interrupt Flag (Read Only) This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated. NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 18 1 read-only DRLSINT DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF. 26 1 read-write DRXTOIF DMA MODE Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.RXTOIEN is enabled a CPU interrupt request will be generated. NOTE: This bit is read only and user can read FIFO to clear it. 20 1 read-only DRXTOINT DMA MODE Time Out Interrupt Indicator to Interrupt Controller Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF. 28 1 read-write MODEMIF MODEM Interrupt Flag (Read Only) Note: This bit is read only and reset when bit MSR.DCTSF is cleared by a write 1. 3 1 read-only MODEMINT MODEM Status Interrupt Indicator to Interrupt Logical AND of IER.MSIEN and MODEMIF 11 1 read-write RDAIF Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the Rx FIFO equals FCR.RFITL then the RDA_IF will be set. If IER.RDA_IEN is enabled, the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL). 0 1 read-only RDAINT Receive Data Available Interrupt Indicator to Interrupt Controller Logical AND of IER.RDAIEN and RDAIF 8 1 read-write RLSIF Receive Line Status Interrupt Flag (Read Only). This bit is set when the Rx receive data has a parity, framing or break error (at least one of, FSR.BIF, FSR.FEF and FSR.PEF, is set). If IER.RLS_IEN is enabled, the RLS interrupt will be generated. Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only RLSINT Receive Line Status Interrupt Indicator to Interrupt Controller Logical AND of IER.RLSIEN and RLSIF 10 1 read-write RXTOIF Time Out Interrupt Flag (Read Only) This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If IER.RXTOIEN is enabled a CPU interrupt request will be generated. Note: This bit is read only and user can read FIFO to clear it. 4 1 read-only RXTOINT Time Out Interrupt Indicator to Interrupt Controller Logical AND of IER.RXTOIEN and RXTOIF 12 1 read-write THREIF Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If IER.THRE_IEN is enabled, the THRE interrupt will be generated. Note: This bit is read only and it will be cleared when writing data into the Tx FIFO. 1 1 read-only THREINT Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller Logical AND of IER.THREIEN and THREIF 9 1 read-write UART_LINE UART_LINE UART Line Control Register. 0xC -1 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic. 6 1 read-write EPE Even Parity Enable This bit has effect only when PBE (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or checked in the data word and parity bits #0 1 Even number of logic 1's are transmitted or checked in the data word and parity bits #1 NSB Number of STOP bits 2 1 read-write 0 One STOP bit is generated after the transmitted data #0 1 Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected #1 PBE Parity Bit Enable 3 1 read-write 0 Parity bit is not generated (transmit data) or checked (receive data) during transfer #0 1 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #1 SPE Stick Parity Enable 5 1 read-write 0 Disable stick parity #0 1 When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared #1 WLS Word Length Select 0 2 read-write UART_MODEM UART_MODEM UART Modem Control Register. 0x10 -1 read-write n 0x0 0x0 LBMEN Loopback Mode Enable. 4 1 read-write RTS RTS (Request-To-Send) Signal 1 1 read-write RTSACTLV Request-to-Send (RTS)Active Trigger Level This bit can change the RTS trigger level. 9 1 read-write 0 RTS is active high level #0 1 RTS is active low level #1 RTSSTS RTS Pin State(read only) This bit is the pin status of RTS. 13 1 read-only UART_MODEMSTS UART_MODEMSTS UART Modem Status Register. 0x14 -1 read-write n 0x0 0x0 CTSACTLV Clear-to-Send (CTS)Active Trigger Level This bit can change the CTS trigger level. 8 1 read-write 0 CTS is active high level #0 1 CTS is active low level #1 CTSDETF Detect CTS State Change Flag Note: This bit is cleared by writing 1 to itself. 0 1 read-write CTSSTS CTS Pin Status (read only) This bit is the pin status of CTS. 4 1 read-only UART_TOUT UART_TOUT UART Time Out Register 0x20 -1 read-write n 0x0 0x0 TOIC Time Out Interrupt Comparator The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter (TOIC) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if IER.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate. 0 7 read-write USBD USBD Register Map USBD 0x0 0x0 0x1C registers n 0x20 0x8 registers n 0x500 0xC0 registers n 0x88 0xC registers n 0xA0 0x4 registers n 0xA8 0x8 registers n 0xFFC 0x4 registers n ATTR USBD_ATTR USB Device Bus Status and Attribution Register 0x10 -1 read-write n 0x0 0x0 BYTEM CPU Access USB SRAM Size Mode Selection 10 1 read-write 0 Word mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 DPPUEN Pull-up Resistor on USB_DP Enable Bit 8 1 read-write 0 Pull-up resistor in USB_D+ bus Disabled #0 1 Pull-up resistor in USB_D+ bus Active #1 PHYEN PHY Transceiver Function Enable Bit 4 1 read-write 0 PHY transceiver function Disabled #0 1 PHY transceiver function Enabled #1 PHYPD PHY Power Down Control 9 1 read-write 0 Power Down #0 1 Power On #1 RESUME Resume Status Note: This bit is read only. 2 1 read-write 0 No bus resume #0 1 Resume from suspend #1 RWAKEUP Remote Wake-up 5 1 read-write 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up #1 SUSPEND Suspend Status Note: This bit is read only. 1 1 read-write 0 Bus no suspend #0 1 Bus idle more than 3ms, either cable is plugged off or host is sleeping #1 TOUT Time-out Status Note: This bit is read only. 3 1 read-write 0 No time-out #0 1 No Bus response more than 18 bits time #1 USBEN USB Controller Enable Bit 7 1 read-write 0 USB Controller Disabled #0 1 USB Controller Enabled #1 USBRST USB Reset Status Note: This bit is read only. 0 1 read-write 0 Bus no reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5us #1 BIST USBD_BIST USB Buffer Self-test Control 0xA0 -1 read-write n 0x0 0x0 BISTEN BIST Mode Enable (Internal Only) 0 1 read-write 0 BIST is disabled or completed (automatically cleared by BIST controller) #0 1 BIST is enabled begin to perform BIST on selected memory group #1 BISTFAIL BISTFAIL (Internal Only) The BistFail indicates if the BIST test fails or succeeds. 2 1 read-write 0 If the BistFail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty #0 1 The BistFail will be high once the BIST detects the error and remains high during the BIST operation #1 FINISH BIST Operation Finish (Internal Only) It indicates the end of the BIST operation. 1 1 read-write 0 When the BIST controller doesn't finish all operation, this bit will keep as low #0 1 When the BIST controller finishes all operation, this bit will be set as high #1 BUFSEG0 USBD_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x500 -1 read-write n 0x0 0x0 BUFSEG Endpoint Buffer Segmentation It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is USBD_SRAM address + { BUFSEG, 3'b000} Refer to the section 5.17.5.7 for the endpoint SRAM structure and its description. 3 6 read-write BUFSEG1 USBD_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x510 -1 read-write n 0x0 0x0 BUFSEG10 USBD_BUFSEG10 Endpoint 10 Buffer Segmentation Register 0x5A0 -1 read-write n 0x0 0x0 BUFSEG11 USBD_BUFSEG11 Endpoint 11 Buffer Segmentation Register 0x5B0 -1 read-write n 0x0 0x0 BUFSEG2 USBD_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x520 -1 read-write n 0x0 0x0 BUFSEG3 USBD_BUFSEG3 Endpoint 3 Buffer Segmentation Register 0x530 -1 read-write n 0x0 0x0 BUFSEG4 USBD_BUFSEG4 Endpoint 4 Buffer Segmentation Register 0x540 -1 read-write n 0x0 0x0 BUFSEG5 USBD_BUFSEG5 Endpoint 5 Buffer Segmentation Register 0x550 -1 read-write n 0x0 0x0 BUFSEG6 USBD_BUFSEG6 Endpoint 6 Buffer Segmentation Register 0x560 -1 read-write n 0x0 0x0 BUFSEG7 USBD_BUFSEG7 Endpoint 7 Buffer Segmentation Register 0x570 -1 read-write n 0x0 0x0 BUFSEG8 USBD_BUFSEG8 Endpoint 8 Buffer Segmentation Register 0x580 -1 read-write n 0x0 0x0 BUFSEG9 USBD_BUFSEG9 Endpoint 9 Buffer Segmentation Register 0x590 -1 read-write n 0x0 0x0 CFG0 USBD_CFG0 Endpoint 0 Configuration Register 0x508 -1 read-write n 0x0 0x0 CSTALL Clear STALL Response 9 1 read-write 0 Disable the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQSYNC Data Sequence Synchronization Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EPNUM Endpoint Number These bits are used to define the endpoint number of the current endpoint 0 4 read-write ISOCH Isochronous Endpoint This bit is used to set the endpoint as Isochronous endpoint, no handshake. 4 1 read-write 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 STATE Endpoint STATE 5 2 read-write 0 Endpoint is Disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 CFG1 USBD_CFG1 Endpoint 1 Configuration Register 0x518 -1 read-write n 0x0 0x0 CFG10 USBD_CFG10 Endpoint 10 Configuration Register 0x5A8 -1 read-write n 0x0 0x0 CFG11 USBD_CFG11 Endpoint 11 Configuration Register 0x5B8 -1 read-write n 0x0 0x0 CFG2 USBD_CFG2 Endpoint 2 Configuration Register 0x528 -1 read-write n 0x0 0x0 CFG3 USBD_CFG3 Endpoint 3 Configuration Register 0x538 -1 read-write n 0x0 0x0 CFG4 USBD_CFG4 Endpoint 4 Configuration Register 0x548 -1 read-write n 0x0 0x0 CFG5 USBD_CFG5 Endpoint 5 Configuration Register 0x558 -1 read-write n 0x0 0x0 CFG6 USBD_CFG6 Endpoint 6 Configuration Register 0x568 -1 read-write n 0x0 0x0 CFG7 USBD_CFG7 Endpoint 7 Configuration Register 0x578 -1 read-write n 0x0 0x0 CFG8 USBD_CFG8 Endpoint 8 Configuration Register 0x588 -1 read-write n 0x0 0x0 CFG9 USBD_CFG9 Endpoint 9 Configuration Register 0x598 -1 read-write n 0x0 0x0 CFGP0 USBD_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x50C -1 read-write n 0x0 0x0 CLRRDY Clear Ready When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. For IN token, write '1' to clear the IN token had ready to transmit the data to USB. For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. This bit is write 1 only and is always 0 when it is read back. 0 1 read-write SSTALL Set STALL 1 1 read-write 0 Disable the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFGP1 USBD_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x51C -1 read-write n 0x0 0x0 CFGP10 USBD_CFGP10 Endpoint 10 Set Stall and Clear In/Out Ready Control Register 0x5AC -1 read-write n 0x0 0x0 CFGP11 USBD_CFGP11 Endpoint 11 Set Stall and Clear In/Out Ready Control Register 0x5BC -1 read-write n 0x0 0x0 CFGP2 USBD_CFGP2 Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x52C -1 read-write n 0x0 0x0 CFGP3 USBD_CFGP3 Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x53C -1 read-write n 0x0 0x0 CFGP4 USBD_CFGP4 Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x54C -1 read-write n 0x0 0x0 CFGP5 USBD_CFGP5 Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x55C -1 read-write n 0x0 0x0 CFGP6 USBD_CFGP6 Endpoint 6 Set Stall and Clear In/Out Ready Control Register 0x56C -1 read-write n 0x0 0x0 CFGP7 USBD_CFGP7 Endpoint 7 Set Stall and Clear In/Out Ready Control Register 0x57C -1 read-write n 0x0 0x0 CFGP8 USBD_CFGP8 Endpoint 8 Set Stall and Clear In/Out Ready Control Register 0x58C -1 read-write n 0x0 0x0 CFGP9 USBD_CFGP9 Endpoint 9 Set Stall and Clear In/Out Ready Control Register 0x59C -1 read-write n 0x0 0x0 EPSTS USBD_EPSTS USB Device Endpoint Status Register 0xC -1 read-only n 0x0 0x0 OV Overrun It indicates that the received data is over the maximum payload number or not. 7 1 read-only 0 No overrun #0 1 Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes #1 EPSTS0 USBD_EPSTS0 USB Device Endpoint Status Register 0 0x20 -1 read-only n 0x0 0x0 EPSTS0 Endpoint 0 Status These bits are used to indicate the current status of this endpoint 0 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS1 Endpoint 1 Status These bits are used to indicate the current status of this endpoint 4 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS2 Endpoint 2 Status These bits are used to indicate the current status of this endpoint 8 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS3 Endpoint 3 Status These bits are used to indicate the current status of this endpoint 12 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS4 Endpoint 4 Status These bits are used to indicate the current status of this endpoint 16 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS5 Endpoint 5 Status These bits are used to indicate the current status of this endpoint 20 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS6 Endpoint 6 Status These bits are used to indicate the current status of this endpoint 24 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS7 Endpoint 7 Status These bits are used to indicate the current status of this endpoint 28 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS1 USBD_EPSTS1 USB Device Endpoint Status Register 1 0x24 -1 read-only n 0x0 0x0 EPSTS10 Endpoint 10 Status These bits are used to indicate the current status of this endpoint 8 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS11 Endpoint 11 Status These bits are used to indicate the current status of this endpoint 12 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS8 Endpoint 8 Status These bits are used to indicate the current status of this endpoint 0 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 EPSTS9 Endpoint 9 Status These bits are used to indicate the current status of this endpoint 4 4 read-only 0 In ACK #0000 1 In NAK #0001 2 Out Packet Data0 ACK #0010 3 Setup ACK #0011 6 Out Packet Data1 ACK #0110 7 Isochronous transfer end #0111 FADDR USBD_FADDR USB Device Function Address Register 0x8 -1 read-write n 0x0 0x0 FADDR USB Device Function Address 0 7 read-write FN USBD_FN USB Frame Number Register 0x8C -1 read-only n 0x0 0x0 FN Frame Number These bits contain the 11-bits frame number in the last received SOF packet. 0 11 read-only INTEN USBD_INTEN USB Device Interrupt Enable Register 0x0 -1 read-write n 0x0 0x0 BUSIEN Bus Event Interrupt Enable Bit 0 1 read-write 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 INNAKEN Active NAK Function and Its Status in IN Token 15 1 read-write 0 When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1, so that the USB interrupt event will not be asserted #0 1 IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token #1 NEVWKIEN USB No-event-wake-up Interrupt Enable Bit 3 1 read-write 0 No-event-wake-up Interrupt Disabled #0 1 No-event-wake-up Interrupt Enabled #1 SOFIEN Start of Frame Interrupt Enable Bit 4 1 read-write 0 SOF Interrupt Disabled #0 1 SOF Interrupt Enabled #1 USBIEN USB Event Interrupt Enable Bit 1 1 read-write 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 VBDETIEN VBUS Detection Interrupt Enable Bit 2 1 read-write 0 VBUS detection Interrupt Disabled #0 1 VBUS detection Interrupt Enabled #1 WKEN Wake-up Function Enable Bit 8 1 read-write 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 INTSTS USBD_INTSTS USB Device Interrupt Event Status Register 0x4 -1 read-write n 0x0 0x0 BUSIF BUS Interrupt Status The BUS event means that there is one of the suspend or the resume function in the bus. 0 1 read-write 0 No BUS event occurred #0 1 Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0] #1 EPEVT0 Endpoint 0's USB Event Status 16 1 read-write 0 No event occurred in endpoint 0 #0 1 USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1] #1 EPEVT1 Endpoint 1's USB Event Status 17 1 read-write 0 No event occurred in endpoint 1 #0 1 USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1] #1 EPEVT10 Endpoint 10's USB Event Status 26 1 read-write 0 No event occurred in endpoint 10 #0 1 USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1] #1 EPEVT11 Endpoint 11's USB Event Status 27 1 read-write 0 No event occurred in endpoint 11 #0 1 USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1] #1 EPEVT2 Endpoint 2's USB Event Status 18 1 read-write 0 No event occurred in endpoint 2 #0 1 USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1] #1 EPEVT3 Endpoint 3's USB Event Status 19 1 read-write 0 No event occurred in endpoint 3 #0 1 USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1] #1 EPEVT4 Endpoint 4's USB Event Status 20 1 read-write 0 No event occurred in endpoint 4 #0 1 USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1] #1 EPEVT5 Endpoint 5's USB Event Status 21 1 read-write 0 No event occurred in endpoint 5 #0 1 USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1] #1 EPEVT6 Endpoint 6's USB Event Status 22 1 read-write 0 No event occurred in endpoint 6 #0 1 USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1] #1 EPEVT7 Endpoint 7's USB Event Status 23 1 read-write 0 No event occurred in endpoint 7 #0 1 USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1] #1 EPEVT8 Endpoint 8's USB Event Status 24 1 read-write 0 No event occurred in endpoint 8 #0 1 USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1] #1 EPEVT9 Endpoint 9's USB Event Status 25 1 read-write 0 No event occurred in endpoint 9 #0 1 USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1] #1 NEVWKIF No-event-wake-up Interrupt Status 3 1 read-write 0 NEVWK event does not occur #0 1 No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3] #1 SETUP Setup Event Status 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by writing 1 to USBD_INTSTS[31] #1 SOFIF Start of Frame Interrupt Status 4 1 read-write 0 SOF event does not occur #0 1 SOF event occurred, cleared by write 1 to USBD_INTSTS[4] #1 USBIF USB Event Interrupt Status The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 1 1 read-write 0 No USB event occurred #0 1 USB event occurred, check EPSTS (USBD_EPSTS0 and USBD_EPSTS1) to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPEVT11~0 (USBD_INTSTS[27:16] and SETUP (USBD_INTSTS[31]) #1 VBDETIF VBUS Detection Interrupt Status 2 1 read-write 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2] #1 LPMATTR USBD_LPMATTR USB LPM Attribution Register 0x88 -1 read-only n 0x0 0x0 LPMBESL LPM Best Effort Service Latency These bits contain the BESL value received with last ACK LPM Token 4 4 read-only LPMLINKSTS LPM Link State These bits contain the bLinkState received with last ACK LPM Token 0 4 read-only LPMRWAKUP LPM Remote Wake-up This bit contains the bRemoteWake value received with last ACK LPM Token 8 1 read-only MXPLD0 USBD_MXPLD0 Endpoint 0 Maximal Payload Register 0x504 -1 read-write n 0x0 0x0 MXPLD Maximal Payload Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. When the register is written by CPU, For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. When the register is read by CPU, For IN token, the value of MXPLD is indicated by the data length be transmitted to host For OUT token, the value of MXPLD is indicated the actual data length receiving from host. Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write MXPLD1 USBD_MXPLD1 Endpoint 1 Maximal Payload Register 0x514 -1 read-write n 0x0 0x0 MXPLD10 USBD_MXPLD10 Endpoint 10 Maximal Payload Register 0x5A4 -1 read-write n 0x0 0x0 MXPLD11 USBD_MXPLD11 Endpoint 11 Maximal Payload Register 0x5B4 -1 read-write n 0x0 0x0 MXPLD2 USBD_MXPLD2 Endpoint 2 Maximal Payload Register 0x524 -1 read-write n 0x0 0x0 MXPLD3 USBD_MXPLD3 Endpoint 3 Maximal Payload Register 0x534 -1 read-write n 0x0 0x0 MXPLD4 USBD_MXPLD4 Endpoint 4 Maximal Payload Register 0x544 -1 read-write n 0x0 0x0 MXPLD5 USBD_MXPLD5 Endpoint 5 Maximal Payload Register 0x554 -1 read-write n 0x0 0x0 MXPLD6 USBD_MXPLD6 Endpoint 6 Maximal Payload Register 0x564 -1 read-write n 0x0 0x0 MXPLD7 USBD_MXPLD7 Endpoint 7 Maximal Payload Register 0x574 -1 read-write n 0x0 0x0 MXPLD8 USBD_MXPLD8 Endpoint 8 Maximal Payload Register 0x584 -1 read-write n 0x0 0x0 MXPLD9 USBD_MXPLD9 Endpoint 9 Maximal Payload Register 0x594 -1 read-write n 0x0 0x0 PHYTYPE USBD_PHYTYPE USB PHY Type Control 0xAC -1 read-write n 0x0 0x0 PHYTYPE PHY Type Selection Bit 0 1 read-write 0 Nuvoton CR30 PHY #0 1 OTG PHY #1 SE0 USBD_SE0 USB Device Drive SE0 Control Register 0x90 -1 read-write n 0x0 0x0 SE0 Drive Single Ended Zero in USB Bus The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 0 1 read-write 0 Normal operation #0 1 Force USB PHY transceiver to drive SE0 #1 STBUFSEG USBD_STBUFSEG SETUP Token Buffer Segmentation Register 0x18 -1 read-write n 0x0 0x0 STBUFSEG SETUP Token Buffer Segmentation It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is USBD_SRAM address + {STBUFSEG, 3'b000} Note: It is used for SETUP token only. 3 6 read-write TEST USBD_TEST USB Test Control 0xA8 -1 read-write n 0x0 0x0 VDDIS VBUS Detection De-bounce Disable Bit Note: When this bit is set as 1, it must be set after USB interrupt (USBD_INTEN) configured. 0 1 read-write 0 VBUS debounce control enabled #0 1 VBUS debounce control disabled #1 VBUSDET USBD_VBUSDET USB Device VBUS Detection Register 0x14 -1 read-only n 0x0 0x0 PULLD VBUS pull down resistor enable(50k ohm) 0: Pull down disable(open) 1: Pull down enable(short) 8 1 read-only VBUSDET Device VBUS Detection 0 1 read-only 0 Controller is not attached to the USB host #0 1 Controller is attached to the USB host #1 VERSION USBD_VERSION USB Version Number Register 0xFFC -1 read-write n 0x0 0x0 MAJOR RTL Design SUB Version Number Major version number is correlated to Product Line 0x02: (Current Major Version Number) 24 8 read-write MINOR RTL Design MINOR Version Number Minor version number is dependent on module's ECO version control 0x0000: (Current Minor Version Number) 0 16 read-write SUB RTL Design SUB Version Number Sub version number is correlated to module's key feature 0x01: (Current Sub Version Number) 16 8 read-write WDT WDT Register Map WDT 0x0 0x0 0x4 registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 IF Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. Note: This bit is cleared by writing 1 to this bit. 3 1 read-write 0 Watchdog timer interrupt has not occurred #0 1 Watchdog timer interrupt has occurred #1 INTEN Watchdog Time-Out Interrupt Enable 6 1 read-write 0 Disable the WDT time-out interrupt #0 1 Enable the WDT time-out interrupt #1 RSTCNT Clear Watchdog Timer (Write Protected) Set this bit will clear the Watchdog timer. Note1: This bit will be automatically cleared by hardware. Note2: This bit is writing protected. Refer to the SYS_REGLCTL. 0 1 read-write 0 Writing 0 to this bit has no effect #0 1 Reset the contents of the Watchdog timer #1 RSTEN Watchdog Timer Reset Enable(Write Protected) Setting this bit will enable the Watchdog timer reset function. Note: This bit is writing protected. Refer to the SYS_REGLCTL. 1 1 read-write 0 Disable Watchdog timer reset function #0 1 Enable Watchdog timer reset function #1 RSTF Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is cleared by writing 1 to this bit. 2 1 read-write 0 Watchdog timer reset has not occurred #0 1 Watchdog timer reset has occurred #1 TOUTSEL Watchdog Timer Interval Select These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset. The WDT interrupt timeout is given by: Where WDT_CLK is the period of the Watchdog Timer clock source. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN Watchdog Timer Enable 7 1 read-write 0 Disable the WDT(Watchdog timer) (This action will reset the internal counter) #0 1 Enable the WDT(Watchdog timer) #1 WKEN WDT Time-Out Wake-Up Function Control If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. 4 1 read-write 0 Enable the Wakeup function that WDT timeout can wake up CPU from power-down mode #0 1 Disable WDT Wakeup CPU function #1 WKF WDT Time-Out Wake-Up Flag If WDT causes CPU wake up from sleep or power-down mode, this bit will be set to high. Note: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause CPU wake-up #0 1 CPU wakes up from sleep or power-down mode by WDT time-out interrupt #1