nuvoTon
I96100_v1
2024.05.02
I96100_v1
8
32
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
0x34
0x4
registers
n
0x40
0x4
registers
n
0x50
0x4
registers
n
0x60
0x8
registers
n
0x70
0x10
registers
n
0x90
0x24
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
CRPTCKEN
Cryptographic Accelerator Clock Enable Bit
12
1
read-write
0
Cryptographic controller clock Disabled
#0
1
Cryptographic controller clock Enabled
#1
DSPCKEN
DSP Clock Enable Bit
4
1
read-write
0
DSP clock Disabled
#0
1
DSP clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
OMCIDLE
OTP Memory Controller Clock Enable Bit in IDLE Mode
15
1
read-write
0
OMC clock Disabled when chip is under IDLE mode
#0
1
OMC clock Enabled when chip is under IDLE mode
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
SPIMCKEN
SPIM Controller Clock Enable Bit
14
1
read-write
0
SPIM controller clock Disabled
#0
1
SPIM controller clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
DMICCKEN
DMIC Clock Enable Bit
15
1
read-write
0
DMIC clock Disabled
#0
1
DMIC clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
I2S0CKEN
I2S0 Clock Enable Bit
29
1
read-write
0
I2S0 Clock Disabled
#0
1
I2S0 Clock Enabled
#1
I2S1CKEN
I2S1 Clock Enable Bit
30
1
read-write
0
I2S1 Clock Disabled
#0
1
I2S1 Clock Enabled
#1
RTCCKEN
Real-time-clock APB Interface Clock Enable Bit
This bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
12
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
SPI2CKEN
SPI2 Clock Enable Bit
14
1
read-write
0
SPI2 clock Disabled
#0
1
SPI2 clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
USBDCKEN
USB Device Clock Enable Bit
27
1
read-write
0
USB Device clock Disabled
#0
1
USB Device clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
-1
read-write
n
0x0
0x0
DPWMCKEN
DPWM Clock Enable Bit
6
1
read-write
0
DPWM clock Disabled
#0
1
DPWM clock Enabled
#1
PWM0CKEN
PWM0 Clock Enable Bit
16
1
read-write
0
PWM0 clock Disabled
#0
1
PWM0 clock Enabled
#1
CDLOWB
CLK_CDLOWB
Clock Frequency Range Detector Lower Boundary Register
0x7C
-1
read-write
n
0x0
0x0
LOWERBD
HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
The HXT detected frequency value is 512 * (the frequency of HXT / the frequency of HIRC)
If the HXT detected frequency value lower than this minimum frequency value (LOWERBD), the HXT Clock Frequency Range Detector Interrupt Flag (HXTFQIF(CLK_CLKDSTS[8])) will set to 1.
0
10
read-write
CDUPB
CLK_CDUPB
Clock Frequency Range Detector Upper Boundary Register
0x78
-1
read-write
n
0x0
0x0
UPERBD
HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
The HXT detected frequency value is 512 * (the frequency of HXT / the frequency of HIRC)
If the HXT detected frequency value higher than this maximum frequency value (UPERBD), the HXT Clock Frequency Range Detector Interrupt Flag (HXTFQIF(CLK_CLKDSTS[8])) will set to 1.
0
10
read-write
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
-1
read-write
n
0x0
0x0
HXTFDEN
HXT Clock Fail Detector Enable Bit
4
1
read-write
0
External high speed crystal oscillator (HXT) clock fail detector Disabled
#0
1
External high speed crystal oscillator (HXT) clock fail detector Enabled
#1
HXTFIEN
HXT Clock Fail Interrupt Enable Bit
5
1
read-write
0
External high speed crystal oscillator (HXT) clock fail interrupt Disabled
#0
1
External high speed crystal oscillator (HXT) clock fail interrupt Enabled
#1
HXTFQDEN
HXT Clock Frequency Monitor Enable Bit
16
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency Range Detector Disabled
#0
1
External high speed crystal oscillator (HXT) clock frequency Range Detector Enabled
#1
HXTFQIEN
HXT Clock Frequency Range Detector Interrupt Enable Bit
17
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency Range Detector fail interrupt Disabled
#0
1
External high speed crystal oscillator (HXT) clock frequency Range Detector fail interrupt Enabled
#1
LXTFDEN
LXT Clock Fail Detector Enable Bit
12
1
read-write
0
External low speed crystal oscillator (LXT) clock fail detector Disabled
#0
1
External low speed crystal oscillator (LXT) clock fail detector Enabled
#1
LXTFIEN
LXT Clock Fail Interrupt Enable Bit
13
1
read-write
0
External low speed crystal oscillator (LXT) clock fail interrupt Disabled
#0
1
External low speed crystal oscillator (LXT) clock fail interrupt Enabled
#1
XCLKFDEN
XCLK Clock Fail Detector Enable Bit
6
1
read-write
0
Clock doubler clock (XCLK) fail detector Disabled
#0
1
Clock doubler clock (XCLK) fail detector Enabled
#1
XCLKFIEN
XCLK Clock Fail Interrupt Enable Bit
7
1
read-write
0
Clock doubler clock (XCLK) fail interrupt Disabled
#0
1
Clock doubler clock (XCLK) fail interrupt Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
-1
read-write
n
0x0
0x0
DSPCLKDIV
DSPCLK Clock Divide Number From DSPCLK Clock Source
24
4
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
UART1DIV
UART1 Clock Divide Number From UART1 Clock Source
12
4
read-write
USBDIV
USB Clock Divide Number From PLL Clock
4
4
read-write
CLKDSTS
CLK_CLKDSTS
Clock Fail Detector Status Register
0x74
-1
read-write
n
0x0
0x0
HXTFIF
HXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
0
1
read-write
0
External high speed crystal oscillator (HXT) clock is normal
#0
1
External high speed crystal oscillator (HXT) clock stops
#1
HXTFQIF
HXT Clock Frequency Range Detector Interrupt Flag
Note: Write 1 to clear the bit to 0.
8
1
read-write
0
External high speed crystal oscillator (HXT) clock frequency is normal
#0
1
External high speed crystal oscillator (HXT) clock frequency is abnormal
#1
LXTFIF
LXT Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
1
1
read-write
0
External low speed crystal oscillator (LXT) clock is normal
#0
1
External low speed crystal oscillator (LXT) stops
#1
XCLKFIF
XCLK Clock Fail Interrupt Flag
Note: Write 1 to clear the bit to 0.
2
1
read-write
0
Clock doubler clock (XCLK) clock is normal
#0
1
Clock doubler clock (XCLK) stops
#1
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
-1
read-write
n
0x0
0x0
CLK1HZEN
Clock Output 1Hz Enable Bit
Note: RTC IP need to be enabled.
6
1
read-write
0
1 Hz clock output for RTC frequency compensation Disabled
#0
1
1 Hz clock output for RTC frequency compensation Enabled
#1
CLKOEN
Clock Output Enable Bit
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protected)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on and stable flag must be 1.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from PLL
#010
3
Clock source from LIRC
#011
7
Clock source from HIRC
#111
HIRCFSEL
Internal High Speed RC Oscillator Frequency Selection. (Write Protect)
Determines which trim setting to use for internal high speed RC oscillator.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
24
1
read-write
0
49.152 MHz
#0
1
48.0 MHz
#1
STCLKSEL
SysTick Clock Source Selection (Write Protected)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
3
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from HXT/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/2
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection
28
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from external low speed crystal oscillator (LXT)
#01
2
Clock source from HCLK
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
TMR0SEL
TIMER0 Clock Source Selection
8
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock TM0 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection
12
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock TM1 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR2SEL
TIMER2 Clock Source Selection
16
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock TM2 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR3SEL
TIMER3 Clock Source Selection
20
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock TM3 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
UART0SEL
UART0 Clock Source Selection
24
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from external low speed crystal oscillator (LXT)
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
UART1SEL
UART1 Clock Source Selection
26
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from external low speed crystal oscillator (LXT)
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
WDTSEL
Watchdog Timer Clock Source Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
2
read-write
0
Reserved. Do not use
#00
1
Clock source from external low speed crystal oscillator (LXT)
#01
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection
30
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
-1
read-write
n
0x0
0x0
DMICSEL
DMIC Clock Source Selection
9
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from PCLK1
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from Clock Doubler output (XCLK)
#100
5
Clock source from external pin MCLKI
#101
DPWMSEL
DPWM Clock Source Selection
12
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from PCLK0
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from Clock Doubler output (XCLK)
#100
5
Clock source from external pin MCLKI
#101
PWM0SEL
PWM0 Clock Source Selection
The peripheral clock source of PWM0 is defined by PWM0SEL.
0
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK0
#1
SPI0SEL
SPI0 Clock Source Selection
2
2
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK0
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
SPI2SEL
SPI2 Clock Source Selection
6
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from PCLK0
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from Clock Doubler output (XCLK)
#100
5
Clock source from external pin MCLKI
#101
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x1C
-1
read-write
n
0x0
0x0
I2S0SEL
I2S0 Clock Source Selection
16
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from PCLK0
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from Clock Doubler output (XCLK)
#100
5
Clock source from external pin MCLKI
#101
I2S1SEL
I2S1 Clock Source Selection
20
3
read-write
0
Clock source from external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from PCLK1
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from Clock Doubler output (XCLK)
#100
5
Clock source from external pin MCLKI
#101
RTCSEL
RTC Clock Source Selection
8
1
read-write
0
Clock source from external low speed crystal oscillator (LXT)
#0
1
Clock source from internal low speed RC oscillator (LIRC)
#1
XCLKSEL
Clcok Doubler Source Selection
10
2
read-write
0
Clock source from MCLK input (MCLKI)
#00
1
Clock source from BCLK of I2S0 (I2S0_BCLK)
#01
2
Clock source from BCLK of I2S1 (I2S1_BCLK)
#10
3
Clock source from BCLK of SPI2/I2S (SPI2_CLK)
#11
CLKSEL4
CLK_CLKSEL4
Clock Source Select Control Register 4
0x24
-1
read-write
n
0x0
0x0
USBSEL
USB Clock Source Selection
24
1
read-write
0
Clock source from internal high speed RC oscillator (HIRC)
#0
1
Clock source from PLL
#1
IOPDCTL
CLK_IOPDCTL
GPIO Standby Power-down Control Register
0xB0
-1
read-write
n
0x0
0x0
IOHR
GPIO Hold Release
When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status.
This bit is auto cleared by hardware.
0
1
read-write
LDOCTL
CLK_LDOCTL
Chip LDO Control Register
0x98
-1
read-write
n
0x0
0x0
OVEN
LDO over Drive Enable Bit
Note1: CPU can run up to 200 MHz only when OVEN set to 1.
Note2: If OVEN and LPEN are set to 1 at the same time, LDO over drive will be enabled.
8
1
read-write
0
LDO keep standard voltage operating
#0
1
LDO over drive voltage operating
#1
PASWKCTL
CLK_PASWKCTL
GPA Standby Power-down Wakeup Control Register
0xA0
-1
read-write
n
0x0
0x0
DBEN
PA Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
8
1
read-write
0
Standby power-down wake-up pin De-bounce function disable
#0
1
Standby power-down wake-up pin De-bounce function enable
#1
PFWKEN
Pin Falling Edge Wake-up Enable Bit
2
1
read-write
0
PA group pin falling edge wake-up function disabled
#0
1
PA group pin falling edge wake-up function enabled
#1
PRWKEN
Pin Rising Edge Wake-up Enable Bit
1
1
read-write
0
PA group pin rising edge wake-up function disabled
#0
1
PA group pin rising edge wake-up function enabled
#1
WKEN
Standby Power-down Pin Wake-up Enable Bit
0
1
read-write
0
PA group pin wake-up function disabled
#0
1
PA group pin wake-up function enabled
#1
WKPSEL
PA Standby Power-down Wake-up Pin Select
4
4
read-write
0
PA.0 wake-up function enabled
#0000
1
PA.1 wake-up function enabled
#0001
2
PA.2 wake-up function enabled
#0010
3
PA.3 wake-up function enabled
#0011
4
PA.4 wake-up function enabled
#0100
5
PA.5 wake-up function enabled
#0101
6
PA.6 wake-up function enabled
#0110
7
PA.7 wake-up function enabled
#0111
8
PA.8 wake-up function enabled
#1000
9
PA.9 wake-up function enabled
#1001
10
PA.10 wake-up function enabled
#1010
11
PA.11 wake-up function enabled
#1011
12
PA.12 wake-up function enabled
#1100
13
PA.13 wake-up function enabled
#1101
14
PA.14 wake-up function enabled
#1110
15
PA.15 wake-up function enabled
#1111
PBSWKCTL
CLK_PBSWKCTL
GPB Standby Power-down Wakeup Control Register
0xA4
-1
read-write
n
0x0
0x0
DBEN
PB Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
8
1
read-write
0
Standby power-down wake-up pin De-bounce function disable
#0
1
Standby power-down wake-up pin De-bounce function enable
#1
PFWKEN
Pin Falling Edge Wake-up Enable Bit
2
1
read-write
0
PB group pin falling edge wake-up function disabled
#0
1
PB group pin falling edge wake-up function enabled
#1
PRWKEN
Pin Rising Edge Wake-up Enable Bit
1
1
read-write
0
PB group pin rising edge wake-up function disabled
#0
1
PB group pin rising edge wake-up function enabled
#1
WKEN
Standby Power-down Pin Wake-up Enable Bit
0
1
read-write
0
PB group pin wake-up function disabled
#0
1
PB group pin wake-up function enabled
#1
WKPSEL
PB Standby Power-down Wake-up Pin Select
4
4
read-write
0
PB.0 wake-up function enabled
#0000
1
PB.1 wake-up function enabled
#0001
2
PB.2 wake-up function enabled
#0010
3
PB.3 wake-up function enabled
#0011
4
PB.4 wake-up function enabled
#0100
5
PB.5 wake-up function enabled
#0101
6
PB.6 wake-up function enabled
#0110
7
PB.7 wake-up function enabled
#0111
8
PB.8 wake-up function enabled
#1000
10
PB.10 wake-up function enabled
#1010
11
PB.11 wake-up function enabled
#1011
12
PB.12 wake-up function enabled
#1100
13
PB.13 wake-up function enabled
#1101
14
PB.14 wake-up function enabled
#1110
15
PB.15 wake-up function enabled
#1111
PCLKDIV
CLK_PCLKDIV
APB Clock Divider Register
0x34
-1
read-write
n
0x0
0x0
APB0DIV
APB0 Clock Divider
APB0 clock can be divided from HCLK
Note: When the clock frequency of HCLK greater than 75 MHz, the value of APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be greater than 0.
0
3
read-write
0
PCLK0 = HCLK
#000
1
PCLK0 = 1/2 HCLK
#001
2
PCLK0 = 1/4 HCLK
#010
3
PCLK0 = 1/8 HCLK
#011
4
PCLK0 = 1/16 HCLK
#100
APB1DIV
APB1 Clock Divider
APB1 clock can be divided from HCLK
Note: When the clock frequency of HCLK greater than 75 MHz, the value of APB1DIV (CLK_PCLKDIV[6:4]) and APB0DIV(CLK_PCLKDIV[2:0]) must be greater than 0.
4
3
read-write
0
PCLK1 = HCLK
#000
1
PCLK1 = 1/2 HCLK
#001
2
PCLK1 = 1/4 HCLK
#010
3
PCLK1 = 1/8 HCLK
#011
4
PCLK1 = 1/16 HCLK
#100
PCSWKCTL
CLK_PCSWKCTL
GPC Standby Power-down Wakeup Control Register
0xA8
-1
read-write
n
0x0
0x0
DBEN
PC Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
8
1
read-write
0
Standby power-down wake-up pin De-bounce function disable
#0
1
Standby power-down wake-up pin De-bounce function enable
#1
PFWKEN
Pin Falling Edge Wake-up Enable Bit
2
1
read-write
0
PC group pin falling edge wake-up function disabled
#0
1
PC group pin falling edge wake-up function enabled
#1
PRWKEN
Pin Rising Edge Wake-up Enable Bit
1
1
read-write
0
PC group pin rising edge wake-up function disabled
#0
1
PC group pin rising edge wake-up function enabled
#1
WKEN
Standby Power-down Pin Wake-up Enable Bit
0
1
read-write
0
PC group pin wake-up function disabled
#0
1
PC group pin wake-up function enabled
#1
WKPSEL
PC Standby Power-down Wake-up Pin Select
4
4
read-write
0
PC.0 wake-up function enabled
#0000
1
PC.1 wake-up function enabled
#0001
2
PC.2 wake-up function enabled
#0010
3
PC.3 wake-up function enabled
#0011
4
PC.4 wake-up function enabled
#0100
5
PC.5 wake-up function enabled
#0101
6
PC.6 wake-up function enabled
#0110
7
PC.7 wake-up function enabled
#0111
8
PC.8 wake-up function enabled
#1000
9
PC.9 wake-up function enabled
#1001
10
PC.10 wake-up function enabled
#1010
11
PC.11 wake-up function enabled
#1011
12
PC.12 wake-up function enabled
#1100
13
PC.13 wake-up function enabled
#1101
14
PC.14 wake-up function enabled
#1110
15
PC.15 wake-up function enabled
#1111
PDSWKCTL
CLK_PDSWKCTL
GPD Standby Power-down Wakeup Control Register
0xAC
-1
read-write
n
0x0
0x0
DBEN
PD Input Signal De-bounce Enable Bit
The DBEN bit is used to enable the de-bounce function for each corresponding I/O. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the internal low speed RC oscillator.
The de-bounce function is valid only for edge triggered.
8
1
read-write
0
Standby power-down wake-up pin De-bounce function disable
#0
1
Standby power-down wake-up pin De-bounce function enable
#1
PFWKEN
Pin Falling Edge Wake-up Enable Bit
2
1
read-write
0
PD group pin falling edge wake-up function disabled
#0
1
PD group pin falling edge wake-up function enabled
#1
PRWKEN
Pin Rising Edge Wake-up Enable Bit
1
1
read-write
0
PD group pin rising edge wake-up function disabled
#0
1
PD group pin rising edge wake-up function enabled
#1
WKEN
Standby Power-down Pin Wake-up Enable Bit
0
1
read-write
0
PD group pin wake-up function disabled
#0
1
PD group pin wake-up function enabled
#1
WKPSEL
PD Standby Power-down Wake-up Pin Select
4
4
read-write
0
PD.0 wake-up function enabled
#0000
1
PD.1 wake-up function enabled
#0001
2
PD.2 wake-up function enabled
#0010
3
PD.3 wake-up function enabled
#0011
4
PD.4 wake-up function enabled
#0100
5
PD.5 wake-up function enabled
#0101
6
PD.6 wake-up function enabled
#0110
7
PD.7 wake-up function enabled
#0111
8
PD.8 wake-up function enabled
#1000
9
PD.9 wake-up function enabled
#1001
10
PD.10 wake-up function enabled
#1010
11
PD.11 wake-up function enabled
#1011
12
PD.12 wake-up function enabled
#1100
13
PD.13 wake-up function enabled
#1101
14
PD.14 wake-up function enabled
#1110
15
PD.15 wake-up function enabled
#1111
PLLCTL
CLK_PLLCTL
PLL Control Register
0x40
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as PLL input clock FIN
#1
FBDIV
PLL Feedback Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
9
read-write
INDIV
PLL Input Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
5
read-write
LKSEL
PLL Lock Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
22
1
read-write
0
Refer to STBSEL
#0
1
Refer to PLL macro lock signal
#1
OE
PLL OE (FOUT Enable) Pin Control (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control (Write Protected)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
2
read-write
PD
Power-down Mode (Write Protected)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLSRC
PLL Source Clock Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
19
2
read-write
0
PLL source clock from external high-speed crystal oscillator (HXT)
#00
1
PLL source clock from internal high-speed oscillator (HIRC)
#01
2
PLL source clock from clock doubler output (XCLK)
#10
3
Reserved. Do not use
#11
STBSEL
PLL Stable Counter Selection (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#0
1
PLL stable time is 44000 PLL source clock (suitable for source clock is larger than 12 MHz)
#1
PMUCTL
CLK_PMUCTL
Power Manager Control Register
0x90
-1
read-write
n
0x0
0x0
HIRCPDEN
HIRC Enable Control in Power-down Mode (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
24
1
read-write
0
HIRC disable at Power-down mode
#0
1
HIRC enabled at Power-down mode except DPD mode
#1
PDMSEL
Power-down Mode Selection (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
3
read-write
0
Power-down mode is selected. (PD)
#000
1
Low leakage Power-down mode is selected (LLPD)
#001
2
Reserved. Do not use
#010
3
Reserved. Do not use
#011
4
Standby Power-down mode 0 is selected (SPD0) (SRAM retention)
#100
5
Standby Power-down mode 1 is selected (SPD1)
#101
6
Deep Power-down mode is selected (DPD)
#110
7
Reserved. Do not use
#111
RTCWKEN
RTC Wake-up Enable Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
RTC wake-up disable at Standby Power-down mode
#0
1
RTC wake-up enabled at Standby Power-down mode
#1
VADWKEN
VAD Standby Power-down Mode Wake-up Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
21
1
read-write
0
VAD wake-up disable at Standby Power-down mode
#0
1
VAD wake-up enabled at Standby Power-down mode
#1
WKPINEN
Wake-up Pin Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
16
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKTMREN
Wake-up Timer Enable (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
Wake-up timer disable at DPD/SPD mode
#0
1
Wake-up timer enabled at DPD/SPD mode
#1
WKTMRIS
Wake-up Timer Time-out Interval Select (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
These bits control wake-up timer time-out interval when chip at DPD/SPD mode.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
3
read-write
0
Time-out interval is 128 LIRC clocks (About 12.8 ms)
#000
1
Time-out interval is 256 LIRC clocks (About 25.6 ms)
#001
2
Time-out interval is 512 LIRC clocks (About 51.2 ms)
#010
3
Time-out interval is 1024 LIRC clocks (About 102.4ms)
#011
4
Time-out interval is 4096 LIRC clocks (About 409.6ms)
#100
5
Time-out interval is 8192 LIRC clocks (About 819.2ms)
#101
6
Time-out interval is 16384 LIRC clocks (About 1638.4ms)
#110
7
Time-out interval is 65536 LIRC clocks (About 6553.6ms)
#111
PMUSTS
CLK_PMUSTS
Power Manager Status Register
0x94
-1
read-write
n
0x0
0x0
BODWK
BOD Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a BOD happened. This flag is cleared when SPD mode is entered.
4
1
read-only
CLRWK
Clear Wake-up Flag
Note: This bit is auto cleared by hardware.
31
1
read-write
0
No clear
#0
1
Clear all wake-up flag
#1
DPD_RSTWK
DPD Mode Reset Wake-up Flag (Read Only)
This flag indicates that wakeup of device was requested with a reset. This flag is cleared when DPD mode is entered.
7
1
read-only
DPD_TMRWK
DPD Mode Wake-up Timer Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by wakeup timer time-out. This flag is cleared when DPD mode is entered.
2
1
read-only
GPAWK
GPA Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. This flag is cleared when SPD mode is entered.
8
1
read-only
GPBWK
GPB Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. This flag is cleared when SPD mode is entered.
9
1
read-only
GPCWK
GPC Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. This flag is cleared when SPD mode is entered.
10
1
read-only
GPDWK
GPD Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. This flag is cleared when SPD mode is entered.
11
1
read-only
LVRWK
LVR Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. This flag is cleared when SPD mode is entered.
3
1
read-only
PINWK
Pin Wake-up Flag (Read Only)
This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.15). This flag is cleared when DPD mode is entered.
1
1
read-only
PORWK
Power-on-reset Wake-up Flag (Read Only)
This flag indicates that wakeup of device was requested with a power-on reset. This flag is cleared when DPD mode is entered.
0
1
read-only
RTCWK
RTC Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a RTC alarm or tick time happened. This flag is cleared when SPD mode is entered.
5
1
read-only
SPD_TMRWK
SPD Mode Wake-up Timer Wake-up Flag (Read Only)
This flag indicates that wake-up of chip was requested by wakeup timer time-out. This flag is cleared when SPD mode is entered.
6
1
read-only
VADWK
VAD Wake-up Flag (Read Only)
This flag indicates that wakeup of device from Standby Power-down mode was requested with a VAD happened. This flag is cleared when SPD mode is entered.
13
1
read-only
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 1.
2
1
read-write
0
Internal high speed RC oscillator (HIRC) Disabled
#0
1
Internal high speed RC oscillator (HIRC) Enabled
#1
HXTEN
HXT Enable Bit (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
External high speed crystal (HXT) Disabled
#0
1
External high speed crystal (HXT) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
2
read-write
0
HXT frequency is lower than from 8 MHz
#00
1
HXT frequency is from 8 MHz to 12 MHz
#01
2
HXT frequency is from 12 MHz to 16 MHz
#10
3
HXT frequency is higher than 16 MHz
#11
HXTSELTYP
HXT Crystal Type Select Bit (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
Select INV type
#0
1
Select GM type
#1
HXTTBEN
HXT Crystal TURBO Mode (Write Protected)
This is a protected register. Please refer to open lock sequence to program it.
13
1
read-write
0
HXT Crystal TURBO mode disabled
#0
1
HXT Crystal TURBO mode enabled
#1
LIRCEN
LIRC Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 1.
Note 3: The value of this bit must be kept 1.
3
1
read-write
0
Internal low speed RC oscillator (LIRC) Disabled
#0
1
Internal low speed RC oscillator (LIRC) Enabled
#1
LXTEN
LXT Enable Bit (Write Protected)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: The reset value of this bit is 0.
1
1
read-write
0
External low speed crystal (LXT) Disabled
#0
1
External low speed crystal (LXT) Enabled
#1
PDEN
System Power-down Enable (Write Protected)
When this bit is set to 1, Power-down mode is enabled and chip
keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip will not enter Power-down mode after CPU sleep command WFI
#0
1
Chip enters Power-down mode after CPU sleep command WFI
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protected)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 128 clock cycles when chip works at internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protected)
Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
Set by 'Power-down wake-up event', it indicates that resume from Power-down mode'
The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
6
1
read-write
PDWTCPU
this Bit Control the Power-down Entry Condition (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
1
Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU runs WFI instruction
#1
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
-1
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source (CLK_CLKSEL0[2:0]). If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
HXTSTB
HXT Clock Source Stable Flag (Read Only)
0
1
read-only
0
External high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
External high speed crystal oscillator (HXT) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
LXTSTB
LXT Clock Source Stable Flag (Read Only)
1
1
read-only
0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
External low speed crystal oscillator (LXT) clock is stabled and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
XCLKSTB
XCLK Clock Source Stable Flag (Read Only)
5
1
read-only
0
Clcok doubler (XCLK) clock is not stable or disabled
#0
1
Clcok doubler (XCLK) clock is stable and enabled
#1
SWKDBCTL
CLK_SWKDBCTL
Standby Power-down Wake-up De-bounce Control Register
0x9C
-1
read-write
n
0x0
0x0
SWKDBCLKSEL
Standby Power-down Wake-up De-bounce Sampling Cycle Selection
Note: De-bounce counter clock source is the internal low speed RC oscillator (LIRC).
0
4
read-write
0
Sample wake-up input once per 1 clocks
#0000
1
Sample wake-up input once per 2 clocks
#0001
2
Sample wake-up input once per 4 clocks
#0010
3
Sample wake-up input once per 8 clocks
#0011
4
Sample wake-up input once per 16 clocks
#0100
5
Sample wake-up input once per 32 clocks
#0101
6
Sample wake-up input once per 64 clocks
#0110
7
Sample wake-up input once per 128 clocks
#0111
8
Sample wake-up input once per 256 clocks
#1000
9
Sample wake-up input once per 2*256 clocks
#1001
10
Sample wake-up input once per 4*256 clocks
#1010
11
Sample wake-up input once per 8*256 clocks
#1011
12
Sample wake-up input once per 16*256 clocks
#1100
13
Sample wake-up input once per 32*256 clocks
#1101
14
Sample wake-up input once per 64*256 clocks
#1110
15
Sample wake-up input once per 128*256 clocks.
#1111
XCLKCTL
CLK_XCLKCTL
Clock Doubler Output Control Register
0x64
-1
read-write
n
0x0
0x0
XCLKEN
XCLK Enable Bit
4
1
read-write
0
Clock doubler (XCLK) Disabled
#0
1
Clock doubler (XCLK) Enabled
#1
XCLKMUL
Clock doubler Output Frequency Multiplication
0
2
read-write
0
Output frequency multiply by 1 (Bypass)
#00
1
Output frequency multiply by 2
#01
2
Output frequency multiply by 4
#10
3
Output frequency multiply by 8
#11
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results
This field indicates the CRC checksum result.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHKSINIT
Checksum Initialization
Note: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value
#1
CHKSREV
Checksum Bit Order Reverse
This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CRCEN
CRC Channel Enable Bit
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
26
1
read-write
0
1's complement for CRC writes data in Disabled
#0
1
1's complement for CRC writes data in Enabled
#1
DATLEN
CPU Write Data Length
This field indicates the write data length.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.
Data length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse
This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC write data in Disabled
#0
1
Bit order reversed for CRC write data in Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
-1
read-write
n
0x0
0x0
DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Value
This field indicates the CRC seed value.
Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
0
32
read-write
CRYPTO
CRYPTO Register Map
CRYPTO
0x0
0x0
0x30
registers
n
0x100
0x4C
registers
n
0x300
0x28
registers
n
0x348
0x10
registers
n
0x50
0x10
registers
n
AES0_CNT
CRYPTO_AES0_CNT
AES Byte Count Register
0x148
-1
read-write
n
0x0
0x0
CNT
AES Byte Count
The CRYPTO_AES0_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES0_CNT is 32-bit and the maximum of byte count is 4G bytes.
CRYPTO_AES0_CNT can be read and written. Writing to CRYPTO_AES0_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AES0_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.
According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.
In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AES0_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES0_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
0
32
read-write
AES0_DADDR
CRYPTO_AES0_DADDR
AES DMA Destination Address Register
0x144
-1
read-write
n
0x0
0x0
DADDR
AES DMA Destination Address
The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.
DADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.
In DMA mode, software can update the next CRYPTO_AES0_DADDR before triggering START.
The value of CRYPTO_AES0_SADDR and CRYPTO_AES0_DADDR can be the same.
0
32
read-write
AES0_IV0
CRYPTO_AES0_IV0
AES Initial Vector Word 0 Register
0x130
-1
read-write
n
0x0
0x0
IV
AES Initial Vectors
Four initial vectors (CRYPTO_AES0_IV0, CRYPTO_AES0_IV1, CRYPTO_AES0_IV2, and CRYPTO_AES0_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AES0_IV0, CRYPTO_AES0_IV1, CRYPTO_AES0_IV2, and CRYPTO_AES0_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
0
32
read-write
AES0_IV1
CRYPTO_AES0_IV1
AES Initial Vector Word 1 Register
0x134
-1
read-write
n
0x0
0x0
AES0_IV2
CRYPTO_AES0_IV2
AES Initial Vector Word 2 Register
0x138
-1
read-write
n
0x0
0x0
AES0_IV3
CRYPTO_AES0_IV3
AES Initial Vector Word 3 Register
0x13C
-1
read-write
n
0x0
0x0
AES0_KEY0
CRYPTO_AES0_KEY0
AES Key Word 0 Register
0x110
-1
read-write
n
0x0
0x0
KEY
CRYPTO_AES0_KEYx
The KEY keeps the security key for AES operation.
{CRYPTO_AES0_KEY7, CRYPTO_AES0_KEY6, CRYPTO_AES0_KEY5, CRYPTO_AES0_KEY4, CRYPTO_AES0_KEY3, CRYPTO_AES0_KEY2, CRYPTO_AES0_KEY1, CRYPTO_AES0_KEY0} stores the 256-bit security key for AES operation.
0
32
read-write
AES0_KEY1
CRYPTO_AES0_KEY1
AES Key Word 1 Register
0x114
-1
read-write
n
0x0
0x0
AES0_KEY2
CRYPTO_AES0_KEY2
AES Key Word 2 Register
0x118
-1
read-write
n
0x0
0x0
AES0_KEY3
CRYPTO_AES0_KEY3
AES Key Word 3 Register
0x11C
-1
read-write
n
0x0
0x0
AES0_KEY4
CRYPTO_AES0_KEY4
AES Key Word 4 Register
0x120
-1
read-write
n
0x0
0x0
AES0_KEY5
CRYPTO_AES0_KEY5
AES Key Word 5 Register
0x124
-1
read-write
n
0x0
0x0
AES0_KEY6
CRYPTO_AES0_KEY6
AES Key Word 6 Register
0x128
-1
read-write
n
0x0
0x0
AES0_KEY7
CRYPTO_AES0_KEY7
AES Key Word 7 Register
0x12C
-1
read-write
n
0x0
0x0
AES0_SADDR
CRYPTO_AES0_SADDR
AES DMA Source Address Register
0x140
-1
read-write
n
0x0
0x0
SADDR
AES DMA Source Address
The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.
SADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.
In DMA mode, software can update the next CRYPTO_AES0_SADDR before triggering START.
The value of CRYPTO_AES0_SADDR and CRYPTO_AES0_DADDR can be the same.
0
32
read-write
AES_CTL
CRYPTO_AES_CTL
AES Control Register
0x100
-1
read-write
n
0x0
0x0
CHANNEL
AES Engine Working Channel
Keeps this field as 0x00.
24
2
read-write
DMACSCAD
AES Engine DMA with Cascade Mode
6
1
read-write
0
DMA cascade function Disabled
#0
1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
#1
DMAEN
AES Engine DMA Enable Bit
The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
AES DMA engine Disabled
#0
1
AES_DMA engine Enabled
#1
DMALAST
AES Last Block
In DMA mode, this bit must be set as beginning the last DMA cascade round.
In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
This bit is always 0 when it's read back. Must be written again once START is triggered.
5
1
read-write
ENCRYPTO
AES Encryption/Decryption
16
1
read-write
0
AES engine executes decryption operation
#0
1
AES engine executes encryption operation
#1
INSWAP
AES Engine Input Data Swap
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
KEYPRT
Protect Key
Read as a flag to reflect KEYPRT.
31
1
read-write
0
No effect
#0
1
Protect the content of the AES key from reading. The return value for reading CRYPTO_AES0_KEYx is not the content of the registers CRYPTO_AES0_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
#1
KEYSZ
AES Key Size
This bit defines three different key size for AES operation.
If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
2
2
read-write
2
256 bits key
2
KEYUNPRT
Unprotect Key
Writing 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is that AES key is unprotected.
The KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
26
5
read-write
OPMODE
AES Engine Operation Modes
8
8
read-write
0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x00
2
CFB (Cipher Feedback Mode)
0x02
3
OFB (Output Feedback Mode)
0x03
4
CTR (Counter Mode)
0x04
16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x10
17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x11
18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
0x12
OUTSWAP
AES Engine Output Data Swap
22
1
read-write
0
Keep the original order
#0
1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
START
AES Engine Start
Note: This bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start AES engine. BUSY flag will be set
#1
STOP
AES Engine Stop
Note: This bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop AES engine
#1
AES_DATIN
CRYPTO_AES_DATIN
AES Engine Data Input Port Register
0x108
-1
read-write
n
0x0
0x0
DATIN
AES Engine Input Port
CPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data when INBUFFULL is 0.
0
32
read-write
AES_DATOUT
CRYPTO_AES_DATOUT
AES Engine Data Output Port Register
0x10C
-1
read-only
n
0x0
0x0
DATOUT
AES Engine Output Port
CPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data when OUTBUFEMPTY is 0.
0
32
read-only
AES_FDBCK0
CRYPTO_AES_FDBCK0
AES Engine Output Feedback Data After Cryptographic Operation
0x50
-1
read-only
n
0x0
0x0
FDBCK
AES Feedback Information
The feedback value is 128 bits in size.
The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES0_IVx for the next block in DMA cascade mode.
The AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AES0_IVx in the same channel operation, and then continue the operation with the original setting.
0
32
read-only
AES_FDBCK1
CRYPTO_AES_FDBCK1
AES Engine Output Feedback Data After Cryptographic Operation
0x54
-1
read-write
n
0x0
0x0
AES_FDBCK2
CRYPTO_AES_FDBCK2
AES Engine Output Feedback Data After Cryptographic Operation
0x58
-1
read-write
n
0x0
0x0
AES_FDBCK3
CRYPTO_AES_FDBCK3
AES Engine Output Feedback Data After Cryptographic Operation
0x5C
-1
read-write
n
0x0
0x0
AES_STS
CRYPTO_AES_STS
AES Engine Flag
0x104
-1
read-only
n
0x0
0x0
BUSERR
AES DMA Access Bus Error Flag
20
1
read-only
0
No error
#0
1
Bus error will stop DMA operation and AES engine
#1
BUSY
AES Engine Busy
0
1
read-only
0
The AES engine is idle or finished
#0
1
The AES engine is under processing
#1
CNTERR
CRYPTO_AES0_CNT Setting Error
12
1
read-only
0
No error in CRYPTO_AES0_CNT setting
#0
1
CRYPTO_AES0_CNT is 0 if DMAEN(CRYPTO_AES_CTL[7]) is enabled
#1
INBUFEMPTY
AES Input Buffer Empty
8
1
read-only
0
There are some data in input buffer waiting for the AES engine to process
#0
1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
#1
INBUFERR
AES Input Buffer Error Flag
10
1
read-only
0
No error
#0
1
Error happens during feeding data to the AES engine
#1
INBUFFULL
AES Input Buffer Full Flag
9
1
read-only
0
AES input buffer is not full. Software can feed the data into the AES engine
#0
1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
#1
OUTBUFEMPTY
AES Out Buffer Empty
16
1
read-only
0
AES output buffer is not empty. There are some valid data kept in output buffer
#0
1
AES output buffer is empty. Software cannot get data from CRYPTO_AES_DATOUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
#1
OUTBUFERR
AES Out Buffer Error Flag
18
1
read-only
0
No error
#0
1
Error happens during getting the result from AES engine
#1
OUTBUFFULL
AES Out Buffer Full Flag
17
1
read-only
0
AES output buffer is not full
#0
1
AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT. Otherwise, the AES engine will be pending since the output buffer is full
#1
INTEN
CRYPTO_INTEN
Crypto Interrupt Enable Control Register
0x0
-1
read-write
n
0x0
0x0
AESEIEN
AES Error Flag Enable Bit
1
1
read-write
0
AES error interrupt flag Disabled
#0
1
AES error interrupt flag Enabled
#1
AESIEN
AES Interrupt Enable Bit
Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
0
1
read-write
0
AES interrupt Disabled
#0
1
AES interrupt Enabled
#1
PRNGIEN
PRNG Interrupt Enable Bit
16
1
read-write
0
PRNG interrupt Disabled
#0
1
PRNG interrupt Enabled
#1
SHAEIEN
SHA Error Interrupt Enable Bit
25
1
read-write
0
SHA error interrupt flag Disabled
#0
1
SHA error interrupt flag Enabled
#1
SHAIEN
SHA Interrupt Enable Bit
Note: In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
24
1
read-write
0
SHA interrupt Disabled
#0
1
SHA interrupt Enabled
#1
INTSTS
CRYPTO_INTSTS
Crypto Interrupt Flag
0x4
-1
read-write
n
0x0
0x0
AESEIF
AES Error Flag
This bit is cleared by writing 1, and it has no effect by writing 0.
1
1
read-write
0
No AES error
#0
1
AES encryption/decryption error interrupt
#1
AESIF
AES Finish Interrupt Flag
This bit is cleared by writing 1, and it has no effect by writing 0.
0
1
read-write
0
No AES interrupt
#0
1
AES encryption/decryption done interrupt
#1
PRNGIF
PRNG Finish Interrupt Flag
This bit is cleared by writing 1, and it has no effect by writing 0.
16
1
read-write
0
No PRNG interrupt
#0
1
PRNG key generation done interrupt
#1
SHAEIF
SHA Error Flag
This register includes operating and setting error. The detail flag is shown in CRYPTO_SHA_STS register.
This bit is cleared by writing 1, and it has no effect by writing 0.
25
1
read-write
0
No SHA error
#0
1
SHA error interrupt
#1
SHAIF
SHASHA Finish Interrupt Flag
This bit is cleared by writing 1, and it has no effect by writing 0.
24
1
read-write
0
No SHA interrupt
#0
1
SHA operation done interrupt
#1
PRNG_CTL
CRYPTO_PRNG_CTL
PRNG Control Register
0x8
-1
read-write
n
0x0
0x0
BUSY
PRNG Busy (Read Only)
8
1
read-only
0
PRNG engine is idle
#0
1
Indicate that the PRNG engine is generating CRYPTO_PRNG_KEYx
#1
KEYSZ
PRNG Generate Key Size
2
2
read-write
0
64 bits
#00
1
128 bits
#01
2
192 bits
#10
3
256 bits
#11
SEEDRLD
Reload New Seed for PRNG Engine
1
1
read-write
0
Generating key based on the current seed
#0
1
Reload new seed
#1
START
Start PRNG Engine
0
1
read-write
0
Stop PRNG engine
#0
1
Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated
#1
PRNG_KEY0
CRYPTO_PRNG_KEY0
PRNG Generated Key0
0x10
-1
read-only
n
0x0
0x0
KEY
Store PRNG Generated Key (Read Only)
The bits store the key that is generated by PRNG.
0
32
read-only
PRNG_KEY1
CRYPTO_PRNG_KEY1
PRNG Generated Key1
0x14
-1
read-write
n
0x0
0x0
PRNG_KEY2
CRYPTO_PRNG_KEY2
PRNG Generated Key2
0x18
-1
read-write
n
0x0
0x0
PRNG_KEY3
CRYPTO_PRNG_KEY3
PRNG Generated Key3
0x1C
-1
read-write
n
0x0
0x0
PRNG_KEY4
CRYPTO_PRNG_KEY4
PRNG Generated Key4
0x20
-1
read-write
n
0x0
0x0
PRNG_KEY5
CRYPTO_PRNG_KEY5
PRNG Generated Key5
0x24
-1
read-write
n
0x0
0x0
PRNG_KEY6
CRYPTO_PRNG_KEY6
PRNG Generated Key6
0x28
-1
read-write
n
0x0
0x0
PRNG_KEY7
CRYPTO_PRNG_KEY7
PRNG Generated Key7
0x2C
-1
read-write
n
0x0
0x0
PRNG_SEED
CRYPTO_PRNG_SEED
Seed for PRNG
0xC
-1
write-only
n
0x0
0x0
SEED
Seed for PRNG (Write Only)
The bits store the seed for PRNG engine.
0
32
write-only
SHA_CTL
CRYPTO_SHA_CTL
SHA Control Register
0x300
-1
read-write
n
0x0
0x0
DMACSCAD
SHA Engine DMA with Cascade Mode
6
1
read-write
0
DMA cascade function Disabled
#0
1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
#1
DMAEN
SHA Engine DMA Enable Bit
SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
SHA DMA engine Disabled
#0
1
SHA DMA engine Enabled
#1
DMAFIRST
SHA First Block in cascadefunction
This bit must be set as feeding in first byte of data.
4
1
read-write
DMALAST
SHA Last Block
This bit must be set as feeding in last byte of data.
5
1
read-write
INSWAP
SHA Engine Input Data Swap
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
OPMODE
SHA Engine Operation Modes
0x100: SHA256
Note: These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
8
3
read-write
OUTSWAP
SHA Engine Output Data Swap
22
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
SHAEN
SHA Engine Operating Mode
11
1
read-write
0
Execute SHA function
#0
1
Reserved.
#1
START
SHA Engine Start
Note: This bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start SHA engine. BUSY flag will be set
#1
STOP
SHA Engine Stop
Note: This bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop SHA engine
#1
SHA_DATIN
CRYPTO_SHA_DATIN
SHA Engine Non-dMA Mode Data Input Port Register
0x354
-1
read-write
n
0x0
0x0
DATIN
SHA Engine Input Port
CPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS. Feed data when DATINREQ is 1.
0
32
read-write
SHA_DGST0
CRYPTO_SHA_DGST0
SHA Digest Message 0
0x308
-1
read-only
n
0x0
0x0
DGST
SHA Digest Message Output Register
For SHA-256, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST7.
0
32
read-only
SHA_DGST1
CRYPTO_SHA_DGST1
SHA Digest Message 1
0x30C
-1
read-write
n
0x0
0x0
SHA_DGST2
CRYPTO_SHA_DGST2
SHA Digest Message 2
0x310
-1
read-write
n
0x0
0x0
SHA_DGST3
CRYPTO_SHA_DGST3
SHA Digest Message 3
0x314
-1
read-write
n
0x0
0x0
SHA_DGST4
CRYPTO_SHA_DGST4
SHA Digest Message 4
0x318
-1
read-write
n
0x0
0x0
SHA_DGST5
CRYPTO_SHA_DGST5
SHA Digest Message 5
0x31C
-1
read-write
n
0x0
0x0
SHA_DGST6
CRYPTO_SHA_DGST6
SHA Digest Message 6
0x320
-1
read-write
n
0x0
0x0
SHA_DGST7
CRYPTO_SHA_DGST7
SHA Digest Message 7
0x324
-1
read-write
n
0x0
0x0
SHA_DMACNT
CRYPTO_SHA_DMACNT
SHA Byte Count Register
0x350
-1
read-write
n
0x0
0x0
DMACNT
SHA Operation Byte Count
The CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRYPTO_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
CRYPTO_SHA_DMACNT can be read and written. Writing to CRYPTO_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation.
In Non-DMA mode, CRYPTO_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
0
32
read-write
SHA_KEYCNT
CRYPTO_SHA_KEYCNT
SHA Key Byte Count Register
0x348
-1
read-write
n
0x0
0x0
KEYCNT
SHA Key Byte Count
The CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written.
Writing to the register CRYPTO_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA _KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA operation.
0
32
read-write
SHA_SADDR
CRYPTO_SHA_SADDR
SHA DMA Source Address Register
0x34C
-1
read-write
n
0x0
0x0
SADDR
SHA DMA Source Address
The SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from SRAM memory space and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_SHA_SADDR are ignored.
CRYPTO_SHA_SADDR can be read and written. Writing to CRYPTO_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTOSHA_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation.
In DMA mode, software can update the next CRYPTO_SHA_SADDR before triggering START.
CRYPTO_SHA_SADDR and CRYPTO_SHA_DADDR can be the same in the value.
0
32
read-write
SHA_STS
CRYPTO_SHA_STS
SHA Status Flag
0x304
-1
read-only
n
0x0
0x0
BUSY
SHA Engine Busy
0
1
read-only
0
SHA engine is idle or finished
#0
1
SHA engine is busy
#1
DATINREQ
SHA Non-DMA Mode Data Input Request
16
1
read-only
0
No effect
#0
1
Request SHA Non-DMA mode data input
#1
DMABUSY
SHA Engine DMA Busy Flag
1
1
read-only
0
SHA DMA engine is idle or finished
#0
1
SHA DMA engine is busy
#1
DMAERR
SHA Engine DMA Error Flag
8
1
read-only
0
Show the SHA engine access normal
#0
1
Show the SHA engine access error
#1
DMIC
DMIC Register Map
DMIC
0x0
0x0
0x1C
registers
n
0x24
0x4
registers
n
0x30
0x4
registers
n
CTL
DMIC_CTL
DMIC Control Register
0x0
-1
read-write
n
0x0
0x0
CH01HPF
DMIC Channel 01 High Pass Filter Enable Bit
Set this bit to 1 to Enable DMIC channel 0 and channel 1 HPF filter for remove DC component.
20
1
read-write
0
DMIC Channel 01 HPF Disabled
#0
1
DMIC Channel 01 HPF Enabled
#1
CH0MUTE
DMIC Channel 0 Mute Enable Bit
Set this bit to 1 to mute DMIC channel 0.
12
1
read-write
0
DMIC Channel 0 Unmute
#0
1
DMIC Channel 0 Mute
#1
CH1MUTE
DMIC Channel 1 Mute Enable Bit
Set this bit to 1 to mute DMIC channel 1.
13
1
read-write
0
DMIC Channel 1 Unmute
#0
1
DMIC Channel 1 Mute
#1
CH23HPF
DMIC Channel 23 High Pass Filter Enable Bit
Set this bit to 1 to Enable DMIC channel 2 and channel 3 HPF filter for remove DC component.
21
1
read-write
0
DMIC Channel 23 HPF Disabled
#0
1
DMIC Channel 23 HPF Enabled
#1
CH2MUTE
DMIC Channel 2 Mute Enable Bit
Set this bit to 1 to mute DMIC channel 2.
14
1
read-write
0
DMIC Channel 2 Unmute
#0
1
DMIC Channel 2 Mute
#1
CH3MUTE
DMIC Channel 3 Mute Enable Bit
Set this bit to 1 to mute DMIC channel 3.
15
1
read-write
0
DMIC Channel 3 Unmute
#0
1
DMIC Channel 3 Mute
#1
CHEN0
DMIC Channel 0 Enable Bit
Set this bit to 1 to enable DMIC channel 0 operation.
0
1
read-write
0
DMIC Channel 0 Disabled
#0
1
DMIC Channel 0 Enabled
#1
CHEN1
DMIC Channel 1 Enable Bit
Set this bit to 1 to enable DMIC channel 1 operation.
1
1
read-write
0
DMIC Channel 1 Disabled
#0
1
DMIC Channel 1 Enabled
#1
CHEN2
DMIC Channel 2 Enable Bit
Set this bit to 1 to enable DMIC channel 2 operation.
2
1
read-write
0
DMIC Channel 2 Disabled
#0
1
DMIC Channel 2 Enabled
#1
CHEN3
DMIC Channel 3 Enable Bit
Set this bit to 1 to enable DMIC channel 3 operation.
3
1
read-write
0
DMIC Channel 3 Disabled
#0
1
DMIC Channel 3 Enabled
#1
DATWIDTH
Data Effective Bit in FIFO
31
1
read-write
0
The bit-width of data word is 16-bit, valid bits is DMIC_FIFO[15:0]
#0
1
The bit-width of data word is 24-bit, valid bits is DMIC _FIFO[23:0]
#1
GAINSTEP
Volume Control Gain Adjust Step for Decimal Point.
27
2
read-write
0
0.5dB (1/2)
#00
1
0.25dB (1/4)
#01
2
0.125dB (1/8)
#10
LEDGE01
DMIC Channel 01 Data Latch Edge
The data of DMIC channel 0 and channel 1 is latched on DMIC_DATA0 pin. This bit is used to select the data of DMIC channel 0 and channel 1 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
8
1
read-write
0
The data of channel 0 is latched on falling edge of DMIC_CLK. The data of channel 1 is latched on rising edge of DMIC_CLK
#0
1
The data of channel 0 is latched on rising edge of DMIC_CLK. The data of channel 1 is latched on falling edge of DMIC_CLK
#1
LEDGE23
DMIC Channel 23 Data Latch Edge
The data of DMIC channel 2 and channel 3 is latched on DMIC_DATA0 pin. This bit is used to select the data of DMIC channel 2 and channel 3 is latched on rising or falling edge of DMIC_CLK (DMIC bus clock).
9
1
read-write
0
The data of channel 2 is latched on falling edge of DMIC_CLK. The data of channel 3 is latched on rising edge of DMIC_CLK
#0
1
The data of channel 2 is latched on rising edge of DMIC_CLK. The data of channel 3 is latched on falling edge of DMIC_CLK
#1
SWRST
Internal State Software Reset.
Set this bit to 1 to Reset DMIC state machine, but all DMIC registers are kept unchanged.
24
1
read-write
0
Normal operation
#0
1
DMIC State Machine Reset
#1
DIV
DMIC_DIV
DMIC Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
CLKDIV
Divider to Generate the DMIC Bus Clock
The value in this field is the frequency divider for generating the DMIC bus clock. The frequency is obtained according to the following equation.
where F_DMIC_MCLK is the frequency of DMIC working main clock (DMIC_MCLK) and F_DMIC_CLK is the frequency of DMIC bus clock (DMIC_CLK).
8
8
read-write
DMTH
FIFO Threshold Level
If the valid data count of the FIFO data buffer is more than or equal to DMTH (DMIC_DIV[20:16]) setting, the DMTHIF (DMIC_STATUS[2]) bit will set to 1, else the DMTHIF (DMIC_STATUS[2]) bit will be cleared to 0.
16
5
read-write
DMTHIE
FIFO Threshold Interrupt
21
1
read-write
0
FIFO threshold interrupt Disabled
#0
1
FIFO threshold interrupt Enabled
#1
FCLR
FIFO Clear
Note 1: To clear the FIFO, need to write FCLR (DMIC_DIV[23:22]) to 11b, and can read the EMPTY (DMIC_STATUS[1]) bit to make sure that the FIFO has been cleared.
Note 2: This field is auto cleared by hardware.
22
2
read-write
3
Clear the FIFO
#11
HPFCUTF
High Pass Filter Cut Off Frequency Selection
28
3
read-write
0
(0.002% * Sample rate)
#000
1
(0.004% * Sample rate)
#001
2
(0.016% * Sample rate)
#010
3
(0.063% * Sample rate)
#011
4
(0.125% * Sample rate)
#100
5
(0.251% * Sample rate)
#101
6
(0.507% * Sample rate)
#110
7
(1.029% * Sample rate)
#111
MCLKDIV
Divider to Generate the DMIC Working Main Clock
The value in this field is the frequency divider for generating the DMIC working main clock. The frequency is obtained according to the following equation.
where F_DMIC_CLK_SRC is the frequency of DMIC module clock source, which is defined in the clock control register DMICSEL (CLK_CLKSEL2[11:9]) and F_DMIC_MCLK depends on the cycle of DMIC DSP processor needed, it is 49.152MHz in general.
0
8
read-write
OSR
DMIC OSR Setting
24
3
read-write
0
Down sample 64
#000
1
Down sample 128
#001
2
Down sample 256
#010
3
Down sample 100
#011
7
Down sample 50
#111
FIFO
DMIC_FIFO
DMIC FIFO Data Output Register
0x10
-1
write-only
n
0x0
0x0
FIFO
FIFO Data Output Register
DMIC contains 32 level (32x24 bit) data buffer for data receive. A read to this register pushes data out from FIFO data buffer and decrements the read pointer. This is the address that PDMA reads audio data from. The remaining data word number is indicated by FIFOPTR (DMIC_STATUS[8:4]).
0
24
write-only
GAIN0_1
DMIC_GAIN0_1
DMIC Channel 0 and 1 Volume Control Register
0x14
-1
read-write
n
0x0
0x0
CH0GAIN
Channel 0 Gain Control
A 16-bit signed 2's complement number, content is as following
Bit15: Sign bit
Bit14~Bit7: Integer Part
Bit6: Decimal Part,0.5dB
Bit5: Decimal Part, 0.25dB
Bit4: Decimal Part,0.125dB
Bit3~Bit0: Reserved
The mapping between real gain and programmed number is
For example,
if the desired gain is 0dB, the programmed value will be -128 (0xC000)
if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
0
16
read-write
CH1GAIN
Channel 1 Gain Control
A 16-bit signed 2's complement number, content is as following
Bit15: Sign bit
Bit14~Bit7: Integer Part
Bit6: Decimal Part,0.5dB
Bit5: Decimal Part, 0.25dB
Bit4: Decimal Part,0.125dB
Bit3~Bit0: Reserved
The mapping between real gain and programmed number is
For example,
if the desired gain is 0dB, the programmed value will be -128 (0xC000)
if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
16
16
read-write
GAIN2_3
DMIC_GAIN2_3
DMIC Channel 2 and 3 Volume Control Register
0x18
-1
read-write
n
0x0
0x0
CH2GAIN
Channel 2 Gain Control
A 16-bit signed 2's complement number, content is as following
Bit15: Sign bit
Bit14~Bit7: Integer Part
Bit6: Decimal Part,0.5dB
Bit5: Decimal Part, 0.25dB
Bit4: Decimal Part,0.125dB
Bit3~Bit0: Reserved
The mapping between real gain and programmed number is
For example,
if the desired gain is 0dB, the programmed value will be -128 (0xC000)
if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
0
16
read-write
CH3GAIN
Channel 3 Gain Control
A 16-bit signed 2's complement number, content is as following
Bit15: Sign bit
Bit14~Bit7: Integer Part
Bit6: Decimal Part,0.5dB
Bit5: Decimal Part, 0.25dB
Bit4: Decimal Part,0.125dB
Bit3~Bit0: Reserved
The mapping between real gain and programmed number is
For example,
if the desired gain is 0dB, the programmed value will be -128 (0xC000)
if the desired gain is -20.5dB, the programmed value will be -107.5(0xCA40)
16
16
read-write
PDMACTL
DMIC_PDMACTL
DMIC PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMAEN
PDMA Transfer Enable Bit
0
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer Enabled
#1
RAMCFG
DMIC_RAMCFG
DMIC DSP RAM Configuration Register
0x24
-1
read-write
n
0x0
0x0
D0RAMCLR
DSP0 RAM Data Clear
Note: This field is auto cleared by hardware.
24
1
read-write
0
No Effect
#0
1
Clear the DSP0 RAM Data
#1
D1RAMCLR
DSP1 RAM Data Clear
Note: This field is auto cleared by hardware.
25
1
read-write
0
No Effect
#0
1
Clear the DSP1 RAM Data
#1
STATUS
DMIC_STATUS
DMIC Status Register
0x8
-1
read-only
n
0x0
0x0
DMTHIF
FIFO Threshold Interrupt Status (Read Only)
2
1
read-only
0
The valid data count within the FIFO data buffer is less than the setting value of DMTH (DMIC_DIV[20:16])
#0
1
The valid data count within the FIFO data buffer is more than or equal to the setting value of TH (DMIC_DIV[20:16])
#1
EMPTY
FIFO Empty Indicator (Read Only)
1
1
read-only
0
FIFO is not empty
#0
1
FIFO is empty
#1
FIFOPTR
FIFO Pointer (Read Only)
The FULL (DMIC_STATUS[0]) and FIFOPTR (DMIC_STATUS[8:4]) indicates the field that the valid data count within the DMIC FIFO buffer.
The maximum value shown in FIFOPTR (DMIC_STATUS[8:4]) is 31. When the using level of DMIC FIFO buffer equal to 32, The FULL (DMIC_STATUS[0]) is set to 1.
4
5
read-only
FULL
FIFO Full Indicator (Read Only)
0
1
read-only
0
FIFO is not full
#0
1
FIFO is full
#1
ZCTH
DMIC_ZCTH
DMIC Zero Cross Threshold Register
0x30
-1
read-write
n
0x0
0x0
ZCTH
Zero Crossing Threshold for PCM Sample Amplitude Gain Adjustment.
DMIC_ZCTH[23] is sign bit, the range [-8388688~8388607]
0
24
read-write
DPWM
DPWM Register Map
DPWM
0x0
0x0
0x18
registers
n
CTL
DPWM_CTL
DPWM Control Register
0x0
-1
read-write
n
0x0
0x0
CLKSET
Working Clock Selection
31
1
read-write
0
512 fs working clock
#0
1
500 fs working clock
#1
DEADTIME
Driver Dead Time Control.
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
3
1
read-write
DPWMEN
Audio DPWM Modulator Enable
6
1
read-write
0
Audio DPWM modulator Disabled
#0
1
Audio DPWM modulator Enabled
#1
DRVEN
Driver Enable Bit
7
1
read-write
0
Audio DPWM driver Disabled
#0
1
Audio DPWM driver Enabled
#1
FCLR
FIFO Clear
Note 1: To clear the FIFO, need to write FCLR (DPWM_CTL[29:28]) to 11b, and can read the EMPTY (DPWM_STATUS[1]) bit to make sure that the FIFO has been cleared.
Note 2: This field is auto cleared by hardware.
28
2
read-write
3
Clear the FIFO
#11
FIFOWIDTH
FIFO Data Width
This bit field is used to define the bit-width of data word and valid bits in register DPWM_FIFO.
Note: When FLTEN is '0', FIFOWIDTH is for fixed point setting.
0
2
read-write
0
The bit-width of data word is 32-bit, valid bits is DPWM_FIFO[31:0]
#00
1
The bit-width of data word is 16-bit, valid bits is DPWM_FIFO[15:0]
#01
2
The bit-width of data word is 8-bit, valid bits is DPWM_FIFO[7:0]
#10
3
The bit-width of data word is 24-bit, valid bits is DPWM_FIFO[23:0]
#11
MODESEL
Data Control in FIFO
4
2
read-write
0
Data is stereo format
#00
1
Data is monaural format
#01
2
Data is 2.1 Channel
#10
3
Reserved.
#11
SWRST
State Machine Software Reset
30
1
read-write
0
State Machine normal operation
#0
1
State Machine Reset
#1
TH
FIFO Threshold Level
If the valid data count of the FIFO data buffer is less than or equal to TH (DPWM_CTL[16:12]) setting, the THIF (DPWM_STATUS[2]) will set to 1, else the THIF (DPWM_STATUS[2]) will be cleared to 0.
12
5
read-write
THIE
FIFO Threshold Interrupt
11
1
read-write
0
FIFO threshold interrupt Disabled
#0
1
FIFO threshold interrupt Enabled
#1
FIFO
DPWM_FIFO
DPWM FIFO Data Input Register
0xC
-1
write-only
n
0x0
0x0
FIFO
FIFO Data Input Register
DPWM contains 32 words (32x32 bit) data buffer for data transmit. A write to this register pushes data onto the FIFO data buffer and increments the write pointer. This is the address that PDMA writes audio data to. The remaining word number is indicated by FIFOPTR (DPWM_STATUS[8:4]).
0
32
write-only
FREQ
DPWM_FREQ
DPWM Output Signal Frequency Control Register
0x14
-1
read-write
n
0x0
0x0
FREQSEL
Output Signal FrequencySelection
0
2
read-write
0
Output signal frequency is 384 kHz
#00
1
Output signal frequency is 307 kHz.
Output signal frequency depends on STEPSEL (DPWM_FREQ[10:8])
#01
STEPSEL
Output Signal Frequency
8
3
read-write
0
Output signal frequency is 614 kHz
#000
1
Output signal frequency is 512 kHz
#001
2
Output signal frequency is 438 kHz
#010
3
Output signal frequency is 384 kHz
#011
4
Output signal frequency is 341 kHz
#100
5
Output signal frequency is 307 kHz
#101
PDMACTL
DPWM_PDMACTL
DPWM PDMA Control Register
0x8
-1
read-write
n
0x0
0x0
PDMAEN
PDMA Transfer Enable Bit
0
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer Enabled
#1
STATUS
DPWM_STATUS
DPWM Status Register
0x4
-1
read-only
n
0x0
0x0
EMPTY
FIFO Empty (Read Only)
1
1
read-only
0
FIFO is not empty
#0
1
FIFO is empty
#1
FIFOPTR
FIFO Pointer (Read Only)
The FULL (DPWM_STATUS[0]) and FIFOPTR (DPWM_STATUS[9:4]) indicates the field that the valid data count within the DPWM FIFO buffer.
The maximum value shown in FIFOPTR is 32. When the using level of DPWM FIFO buffer equal to 32, The FULL (DPWM_STATUS[0]) is set to 1.
4
6
read-only
FULL
FIFO Full (Read Only)
0
1
read-only
0
FIFO is not full
#0
1
FIFO is full
#1
THIF
FIFO Threshold Interrupt Status (Read Only)
2
1
read-only
0
The valid data count within the FIFO data buffer is more than the setting value of TH (DPWM_CTL[16:12])
#0
1
The valid data count within the FIFO data buffer is less than or equal to the setting value of TH (DPWM_CTL[16:12])
#1
ZOHDIV
DPWM_ZOHDIV
DPWM Zero Order Hold Division Register
0x10
-1
read-write
n
0x0
0x0
CLKDIV
Clock Divider
Divider to generate the DPWM_CLK
where F_ DPWM _CLK_SRC is the frequency of DPWM module clock source, which is defined in the clock control register DPWMSEL (CLK_CLKSEL2[13:12]) and F_DPWM_CLK is the frequency of DPWM module working clock (DPWM_CLK).
Note 1: If fs is 48 kHz, the frequency of DPWM_CLK must be 24.576 MHz or 24 MHz according to the value of CLKSET (DPWM_CTL[31]).
Note 2: If fs is 96 kHz, the frequency of DPWM_CLK must be 49.152 MHz or 48 MHz according to the value of CLKSET (DPWM_CTL[31]).
8
11
read-write
ZOHDIV
Zero Order Hold, Down-sampling Divisor
The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in this register by the following formula:
0
8
read-write
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x2C
registers
n
0x30
0x4
registers
n
0x40
0x2C
registers
n
0x440
0x8
registers
n
0x70
0x4
registers
n
0x80
0x2C
registers
n
0x800
0x100
registers
n
0xB0
0x4
registers
n
0xC0
0x2C
registers
n
0xF0
0x4
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC)
#1
ICLKON
Interrupt Clock on Mode
Note: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
INTSTS
GPIO_INTSTS
Interrupt Status Register
0x444
-1
read-write
n
0x0
0x0
PAINTSTS
Port A Interrupt Status (Read Only)
0
1
read-only
0
No interrupt at PA.n
#0
1
PA.n generates an interrupt
#1
PBINTSTS
Port B Interrupt Status (Read Only)
1
1
read-only
0
No interrupt at PB.n
#0
1
PB.n generates an interrupt
#1
PCINTSTS
Port C Interrupt Status (Read Only)
2
1
read-only
0
No interrupt at PC.n
#0
1
PC.n generates an interrupt
#1
PDINTSTS
Port D Interrupt Status (Read Only)
3
1
read-only
0
No interrupt at PD.n
#0
1
PD.n generates an interrupt
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.N Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
-1
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
-1
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output Register
0x830
-1
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output Register
0x834
-1
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output Register
0x838
-1
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output Register
0x83C
-1
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
-1
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
-1
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
-1
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
-1
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
-1
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
-1
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
-1
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
-1
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
-1
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK0
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A-D Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control Register
0x14
-1
read-write
n
0x0
0x0
DBEN0
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A-D Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
-1
read-write
n
0x0
0x0
DINOFF0
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A-D Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A-D Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC0
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
0
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC1
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
1
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC10
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
10
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC11
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
11
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC12
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
12
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC13
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
13
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC14
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
14
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC15
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
15
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC2
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
2
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC3
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
3
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC4
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
4
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC5
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
5
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC6
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
6
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC7
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
7
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC8
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
8
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC9
Port A-D Pin[n] Interrupt Source Flag
Write Operation :
9
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
-1
read-write
n
0x0
0x0
TYPE0
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A-D I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN0
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
0
1
read-only
PIN1
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
1
1
read-only
PIN10
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
10
1
read-only
PIN11
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
11
1
read-only
PIN12
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
12
1
read-only
PIN13
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
13
1
read-only
PIN14
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
14
1
read-only
PIN15
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
15
1
read-only
PIN2
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
2
1
read-only
PIN3
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
3
1
read-only
PIN4
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
4
1
read-only
PIN5
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
5
1
read-only
PIN6
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
6
1
read-only
PIN7
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
7
1
read-only
PIN8
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
8
1
read-only
PIN9
Port A-D Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
9
1
read-only
PA_PUSEL
PA_PUSEL
PA Pull-up and Pull-down Selection Register
0x30
-1
read-write
n
0x0
0x0
PUSEL0
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
0
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL1
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
2
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL10
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
20
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL11
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
22
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL12
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
24
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL13
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
26
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL14
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
28
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL15
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
30
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL2
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
4
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL3
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
6
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL4
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
8
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL5
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
10
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL6
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
12
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL7
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
14
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL8
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
16
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PUSEL9
Port A-D Pin[n] Pull-up and Pull-down Enable Register
Determine each I/O Pull-up/pull-down of Px.n pins.
18
2
read-write
0
Px.n pull-up and pull- down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull-down disable
#11
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control Register
0x28
-1
read-write
n
0x0
0x0
HSREN0
Port A-D Pin[n] High Slew Rate Control
0
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN1
Port A-D Pin[n] High Slew Rate Control
2
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN10
Port A-D Pin[n] High Slew Rate Control
20
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN11
Port A-D Pin[n] High Slew Rate Control
22
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN12
Port A-D Pin[n] High Slew Rate Control
24
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN13
Port A-D Pin[n] High Slew Rate Control
26
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN14
Port A-D Pin[n] High Slew Rate Control
28
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN15
Port A-D Pin[n] High Slew Rate Control
30
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN2
Port A-D Pin[n] High Slew Rate Control
4
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN3
Port A-D Pin[n] High Slew Rate Control
6
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN4
Port A-D Pin[n] High Slew Rate Control
8
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN5
Port A-D Pin[n] High Slew Rate Control
10
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN6
Port A-D Pin[n] High Slew Rate Control
12
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN7
Port A-D Pin[n] High Slew Rate Control
14
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN8
Port A-D Pin[n] High Slew Rate Control
16
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
HSREN9
Port A-D Pin[n] High Slew Rate Control
18
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Px.n output with fast slew rate mode
#10
3
Reserved. Do not use
#11
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable Register
0x24
-1
read-write
n
0x0
0x0
SMTEN0
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
0
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN1
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
1
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN10
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
10
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN11
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
11
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN12
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
12
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN13
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
13
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN14
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
14
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN15
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
15
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN2
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
2
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN3
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
3
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN4
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
4
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN5
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
5
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN6
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
6
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN7
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
7
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN8
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
8
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN9
Port A-D Pin[n] Input Schmitt Trigger Enable Bit
9
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
-1
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output Register
0x868
-1
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output Register
0x86C
-1
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output Register
0x870
-1
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output Register
0x874
-1
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output Register
0x878
-1
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output Register
0x87C
-1
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
-1
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
-1
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
-1
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
-1
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
-1
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output Register
0x858
-1
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output Register
0x85C
-1
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output Register
0x860
-1
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output Register
0x864
-1
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control Register
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
-1
read-write
n
0x0
0x0
PB_PUSEL
PB_PUSEL
PB Pull-up and Pull-down Selection Register
0x70
-1
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
PB High Slew Rate Control Register
0x68
-1
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
PB Input Schmitt Trigger Enable Register
0x64
-1
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output Register
0x880
-1
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A8
-1
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8AC
-1
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B0
-1
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B4
-1
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B8
-1
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8BC
-1
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output Register
0x884
-1
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output Register
0x888
-1
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output Register
0x88C
-1
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output Register
0x890
-1
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output Register
0x894
-1
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output Register
0x898
-1
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output Register
0x89C
-1
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A0
-1
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A4
-1
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
-1
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control Register
0x94
-1
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
-1
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
-1
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x9C
-1
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
-1
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
-1
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
-1
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
-1
read-write
n
0x0
0x0
PC_PUSEL
PC_PUSEL
PC Pull-up and Pull-down Selection Register
0xB0
-1
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
PC High Slew Rate Control Register
0xA8
-1
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
PC Input Schmitt Trigger Enable Register
0xA4
-1
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C0
-1
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E8
-1
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8EC
-1
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F0
-1
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F4
-1
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F8
-1
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8FC
-1
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C4
-1
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C8
-1
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8CC
-1
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D0
-1
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D4
-1
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D8
-1
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8DC
-1
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E0
-1
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E4
-1
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
PD Data Output Write Mask
0xCC
-1
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
PD De-bounce Enable Control Register
0xD4
-1
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
PD Digital Input Path Disable Control
0xC4
-1
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0xC8
-1
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable Control Register
0xDC
-1
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
PD Interrupt Source Flag
0xE0
-1
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
PD Interrupt Trigger Type Control
0xD8
-1
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0xC0
-1
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0xD0
-1
read-write
n
0x0
0x0
PD_PUSEL
PD_PUSEL
PD Pull-up and Pull-down Selection Register
0xF0
-1
read-write
n
0x0
0x0
PD_SLEWCTL
PD_SLEWCTL
PD High Slew Rate Control Register
0xE8
-1
read-write
n
0x0
0x0
PD_SMTEN
PD_SMTEN
PD Input Schmitt Trigger Enable Register
0xE4
-1
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address cannot be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL
I2C_CTL
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. This bit will be cleared by hardware automatically.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable
9
1
read-write
0
Address match 10-bit function is disabled
#0
1
Address match 10-bit function is enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status Register
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status Register
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected or arbitration lost condition occured.
Note: This bit is read only.
8
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control Register
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control Register
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame
Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
2
1
read-write
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 10'h000, the address cannot be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
Note: The wake-up function cannot use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL
I2C_CTL
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. This bit will be cleared by hardware automatically.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable
9
1
read-write
0
Address match 10-bit function is disabled
#0
1
Address match 10-bit function is enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status Register
When address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status Register
When address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status Register
When address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status Register
When address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy
Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected or arbitration lost condition occured.
Note: This bit is read only.
8
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control Register
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control Register
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame
Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
2
1
read-write
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2S0
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
0x20
0x8
registers
n
I2Sn_CLKDIV
I2Sn_CLKDIV
I2S Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency.
Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
8
10
read-write
MCLKDIV
Master Clock Divider
If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input.
Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
0
7
read-write
I2Sn_CTL0
I2Sn_CTL0
I2S Control Register 0
0x0
-1
read-write
n
0x0
0x0
CHWIDTH
Channel Width
This bit fields are used to define the length of audio channel. If CHWIDTH DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
28
2
read-write
0
The bit-width of each audio channel is 8-bit
#00
1
The bit-width of each audio channel is 16-bit
#01
2
The bit-width of each audio channel is 24-bit
#10
3
The bit-width of each audio channel is 32-bit
#11
DATWIDTH
Data Width
This bit field is used to define the bit-width of data word in each audio channel
4
2
read-write
0
The bit-width of data word is 8-bit
#00
1
The bit-width of data word is 16-bit
#01
2
The bit-width of data word is 24-bit
#10
3
The bit-width of data word is 32-bit
#11
FLZCDEN
Force Left Channel Zero Cross Data Option Bit
If this bit set to 1, when channel (Ch0,Ch2,Ch4,Ch6) data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
17
1
read-write
0
Keep channel (Ch0,Ch2,Ch4,Ch6) data , when zero crossing flag on
#0
1
Force channel (Ch0,Ch2,Ch4,Ch6) data to zero, when zero crossing flag on
#1
FORMAT
Data Format Selection
24
3
read-write
0
I2S standard data format
#000
1
I2S with MSB justified
#001
2
I2S with LSB justified
#010
3
Reserved. Do not use
#011
4
PCM standard data format
#100
5
PCM with MSB justified
#101
6
PCM with LSB justified
#110
7
Reserved. Do not use
#111
FRZCDEN
Force Right Channel Zero Cross Data Option Bit
If this bit set to 1, when channel (Ch1,Ch3,Ch5,Ch7) data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
16
1
read-write
0
Keep channel (Ch1,Ch3,Ch5,Ch7) data , when zero crossing flag on
#0
1
Force channel (Ch1,Ch3,Ch5,Ch7) data to zero, when zero crossing flag on
#1
I2SEN
I2S Controller Enable Control
0
1
read-write
0
I2S controller Disabled
#0
1
I2S controller Enabled
#1
MCLKEN
Master Clock Enable Control
If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data Control
Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Control
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Send zero on transmit channel
#1
ORDER
Stereo Data Order in FIFO
In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
7
1
read-write
0
Even channel data at high byte in 8-bit/16-bit data width
#0
1
Even channel data at low byte
#1
PCMSYNC
PCM Synchronization Pulse Length Selection
This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
Note: This bit is only available in master mode
27
1
read-write
0
One BCLK period
#0
1
One channel period
#1
RXEN
Receive Enable Control
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXFBCLR
Receive FIFO Buffer Clear
Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
Note2: This bit is cleared by hardware automatically, read it return zero.
19
1
read-write
0
No Effect
#0
1
Clear RX FIFO
#1
RXLCH
Receive Left Channel Enable Control
23
1
read-write
0
Receives channel1 data in MONO mode
#0
1
Receives channel0 data in MONO mode
#1
RXPDMAEN
Receive PDMA Enable Control
21
1
read-write
0
Receiver PDMA function Disabled
#0
1
Receiver PDMA function Enabled
#1
SLAVE
Slave Mode Enable Control
Note: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TDMCHNUM
TDM Channel Number
30
2
read-write
0
2 channels in audio frame
#00
1
4 channels in audio frame
#01
2
6 channels in audio frame
#10
3
8 channels in audio frame
#11
TXEN
Transmit Enable Control
1
1
read-write
0
Data transmission Disabled
#0
1
Data transmission Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
Note2: This bit is clear by hardware automatically, read it return zero.
18
1
read-write
0
No Effect
#0
1
Clear TX FIFO
#1
TXPDMAEN
Transmit PDMA Enable Control
20
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2Sn_CTL1
I2Sn_CTL1
I2S Control Register 1
0x20
-1
read-write
n
0x0
0x0
CH0ZCEN
Channel0 Zero-cross Detection Enable Control
Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
0
1
read-write
0
channel0 zero-cross detect Disabled
#0
1
channel0 zero-cross detect Enabled
#1
CH1ZCEN
Channel1 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
1
1
read-write
0
channel1 zero-cross detect Disabled
#0
1
channel1 zero-cross detect Enabled
#1
CH2ZCEN
Channel2 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
2
1
read-write
0
channel2 zero-cross detect Disabled
#0
1
channel2 zero-cross detect Enabled
#1
CH3ZCEN
Channel3 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
3
1
read-write
0
channel3 zero-cross detect Disabled
#0
1
channel3 zero-cross detect Enabled
#1
CH4ZCEN
Channel4 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
4
1
read-write
0
channel4 zero-cross detect Disabled
#0
1
channel4 zero-cross detect Enabled
#1
CH5ZCEN
Channel5 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
5
1
read-write
0
channel5 zero-cross detect Disabled
#0
1
channel5 zero-cross detect Enabled
#1
CH6ZCEN
Channel6 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
6
1
read-write
0
channel6 zero-cross detect Disabled
#0
1
channel6 zero-cross detect Enabled
#1
CH7ZCEN
Channel7 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
7
1
read-write
0
channel7 zero-cross detect Disabled
#0
1
channel7 zero-cross detect Enabled
#1
PB16ORD
FIFO Read/Write Order in 16-bit Width of Peripheral Bus
25
1
read-write
0
Low 16-bit read/write access first
#0
1
High 16-bit read/write access first
#1
PBWIDTH
Peripheral Bus Data Width Selection
This bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
24
1
read-write
0
32 bits data width
#0
1
16 bits data width
#1
RXTH
Receive FIFO Threshold Level
Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
16
4
read-write
0
1 data word in receive FIFO
#0000
1
2 data words in receive FIFO
#0001
2
3 data words in receive FIFO
#0010
14
15 data words in receive FIFO
#1110
15
16 data words in receive FIFO
#1111
TXTH
Transmit FIFO Threshold Level
Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
8
4
read-write
0
0 data word in transmit FIFO
#0000
1
1 data word in transmit FIFO
#0001
2
2 data words in transmit FIFO
#0010
14
14 data words in transmit FIFO
#1110
15
15 data words in transmit FIFO
#1111
I2Sn_IEN
I2Sn_IEN
I2S Interrupt Enable Register
0x8
-1
read-write
n
0x0
0x0
CH0ZCIEN
Channel0 Zero-cross Interrupt Enable Control
16
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH1ZCIEN
Channel1 Zero-cross Interrupt Enable Control
17
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH2ZCIEN
Channel2 Zero-cross Interrupt Enable Control
18
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH3ZCIEN
Channel3 Zero-cross Interrupt Enable Control
19
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH4ZCIEN
Channel4 Zero-cross Interrupt Enable Control
20
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH5ZCIEN
Channel5 Zero-cross Interrupt Enable Control
21
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH6ZCIEN
Channel6 Zero-cross Interrupt Enable Control
22
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH7ZCIEN
Channel7 Zero-cross Interrupt Enable Control
23
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVFIEN
Receive FIFO Overflow Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt Enable Control
Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1. If RXTHIEN bit is enabled, interrupt occur.
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDFIEN
Receive FIFO Underflow Interrupt E Enable Control
Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVFIEN
Transmit FIFO Overflow Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDFIEN
Transmit FIFO Underflow Interrupt Enable Control
Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
I2Sn_RXFIFO
I2Sn_RXFIFO
I2S Receive FIFO Register
0x14
-1
read-only
n
0x0
0x0
RXFIFO
Receive FIFO Bits
I2S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
0
32
read-only
I2Sn_STATUS0
I2Sn_STATUS0
I2S Status Register 0
0xC
-1
read-write
n
0x0
0x0
DATACH
Transmission Data Channel (Read Only)
This bit fields are used to indicate which audio channel is current transmit data belong.
3
3
read-only
0
channel0 (means left channel while 2-channel I2S/PCM mode)
#000
1
channel1 (means right channel while 2-channel I2S/PCM mode)
#001
2
channel2 (available while 4-channel TDM PCM mode)
#010
3
channel3 (available while 4-channel TDM PCM mode)
#011
4
channel4 (available while 6-channel TDM PCM mode)
#100
5
channel5 (available while 6-channel TDM PCM mode)
#101
6
channel6 (available while 8-channel TDM PCM mode)
#110
7
channel7 (available while 8-channel TDM PCM mode)
#111
I2SINT
I2S Interrupt Flag (Read Only)
Note: It is wire-OR of I2STXINT and I2SRXINT bits.
0
1
read-only
0
No I2S interrupt
#0
1
I2S interrupt
#1
I2SRXINT
I2S Receive Interrupt (Read Only)
1
1
read-only
0
No receive interrupt
#0
1
Receive interrupt
#1
I2STXINT
I2S Transmit Interrupt (Read Only)
2
1
read-only
0
No transmit interrupt
#0
1
Transmit interrupt
#1
RXEMPTY
Receive FIFO Empty (Read Only)
Note: This bit reflects data words number in receive FIFO is zero
12
1
read-only
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full (Read Only)
Note: This bit reflects data words number in receive FIFO is 12.
11
1
read-only
0
Not full
#0
1
Full
#1
RXOVIF
Receive FIFO Overflow Interrupt Flag
Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
Note2: Write 1 to clear this bit to 0.
9
1
read-write
0
No overflow occur
#0
1
Overflow occur
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
10
1
read-only
0
Data word(s) in FIFO is not higher than threshold level
#0
1
Data word(s) in FIFO is higher than threshold level
#1
RXUDIF
Receive FIFO Underflow Interrupt Flag
Note1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs.
Note2: Write 1 to clear this bit to zero
8
1
read-write
0
No underflow occur
#0
1
Underflow occur
#1
TXBUSY
Transmit Busy (Read Only)
Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
21
1
read-only
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit reflect data word number in transmit FIFO is zero
20
1
read-only
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full (Read Only)
This bit reflect data word number in transmit FIFO is 12
19
1
read-only
0
Not full
#0
1
Full
#1
TXOVIF
Transmit FIFO Overflow Interrupt Flag
Note1: Write data to transmit FIFO when it is full and this bit set to 1
Note2: Write 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
18
1
read-only
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal or lower than threshold level
#1
TXUDIF
Transmit FIFO Underflow Interrupt Flag
Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
Note2: Write 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
I2Sn_STATUS1
I2Sn_STATUS1
I2S Status Register 1
0x24
-1
read-write
n
0x0
0x0
CH0ZCIF
Channel0 Zero-cross Interrupt Flag
It indicates channel0 next sample data sign bit is changed or all data bits are zero.
0
1
read-write
0
No zero-cross in channel0
#0
1
Channel0 zero-cross is detected
#1
CH1ZCIF
Channel1 Zero-cross Interrupt Flag
It indicates channel1 next sample data sign bit is changed or all data bits are zero.
1
1
read-write
0
No zero-cross in channel1
#0
1
Channel1 zero-cross is detected
#1
CH2ZCIF
Channel2 Zero-cross Interrupt Flag
It indicates channel2 next sample data sign bit is changed or all data bits are zero.
2
1
read-write
0
No zero-cross in channel2
#0
1
Channel2 zero-cross is detected
#1
CH3ZCIF
Channel3 Zero-cross Interrupt Flag
It indicates channel3 next sample data sign bit is changed or all data bits are zero.
3
1
read-write
0
No zero-cross in channel3
#0
1
Channel3 zero-cross is detected
#1
CH4ZCIF
Channel4 Zero-cross Interrupt Flag
It indicates channel4 next sample data sign bit is changed or all data bits are zero.
4
1
read-write
0
No zero-cross in channel4
#0
1
Channel4 zero-cross is detected
#1
CH5ZCIF
Channel5 Zero-cross Interrupt Flag
It indicates channel5 next sample data sign bit is changed or all data bits are zero.
5
1
read-write
0
No zero-cross in channel5
#0
1
Channel5 zero-cross is detected
#1
CH6ZCIF
Channel6 Zero-cross Interrupt Flag
It indicates channel6 next sample data sign bit is changed or all data bits are zero.
6
1
read-write
0
No zero-cross in channel6
#0
1
Channel6 zero-cross is detected
#1
CH7ZCIF
Channel7 Zero-cross Interrupt Flag
It indicates channel7 next sample data sign bit is changed or all data bits are zero.
7
1
read-write
0
No zero-cross in channel7
#0
1
Channel7 zero-cross is detected
#1
RXCNT
Receive FIFO Level (Read Only)
These bits indicate the number of available entries in receive FIFO
Others are reserved. Do not use.
16
5
read-only
0
No data
#00000
1
1 word in receive FIFO
#00001
2
2 words in receive FIFO
#00010
14
14 words in receive FIFO
#01110
15
15 words in receive FIFO
#01111
16
16 words in receive FIFO
#10000
TXCNT
Transmit FIFO Level (Read Only)
These bits indicate the number of available entries in transmit FIFO
Others are reserved. Do not use.
8
5
read-only
0
No data
#00000
1
1 word in transmit FIFO
#00001
2
2 words in transmit FIFO
#00010
14
14 words in transmit FIFO
#01110
15
15 words in transmit FIFO
#01111
16
16 words in transmit FIFO
#10000
I2Sn_TXFIFO
I2Sn_TXFIFO
I2S Transmit FIFO Register
0x10
-1
write-only
n
0x0
0x0
TXFIFO
Transmit FIFO Bits
I2S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
0
32
write-only
I2S1
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
0x20
0x8
registers
n
I2Sn_CLKDIV
I2Sn_CLKDIV
I2S Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. Software can program these bit fields to generate sampling rate clock frequency.
Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
8
10
read-write
MCLKDIV
Master Clock Divider
If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input.
Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
0
7
read-write
I2Sn_CTL0
I2Sn_CTL0
I2S Control Register 0
0x0
-1
read-write
n
0x0
0x0
CHWIDTH
Channel Width
This bit fields are used to define the length of audio channel. If CHWIDTH DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
28
2
read-write
0
The bit-width of each audio channel is 8-bit
#00
1
The bit-width of each audio channel is 16-bit
#01
2
The bit-width of each audio channel is 24-bit
#10
3
The bit-width of each audio channel is 32-bit
#11
DATWIDTH
Data Width
This bit field is used to define the bit-width of data word in each audio channel
4
2
read-write
0
The bit-width of data word is 8-bit
#00
1
The bit-width of data word is 16-bit
#01
2
The bit-width of data word is 24-bit
#10
3
The bit-width of data word is 32-bit
#11
FLZCDEN
Force Left Channel Zero Cross Data Option Bit
If this bit set to 1, when channel (Ch0,Ch2,Ch4,Ch6) data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
17
1
read-write
0
Keep channel (Ch0,Ch2,Ch4,Ch6) data , when zero crossing flag on
#0
1
Force channel (Ch0,Ch2,Ch4,Ch6) data to zero, when zero crossing flag on
#1
FORMAT
Data Format Selection
24
3
read-write
0
I2S standard data format
#000
1
I2S with MSB justified
#001
2
I2S with LSB justified
#010
3
Reserved. Do not use
#011
4
PCM standard data format
#100
5
PCM with MSB justified
#101
6
PCM with LSB justified
#110
7
Reserved. Do not use
#111
FRZCDEN
Force Right Channel Zero Cross Data Option Bit
If this bit set to 1, when channel (Ch1,Ch3,Ch5,Ch7) data sign bit changes or next shift data bits are all 0 then the channel ZCIF flag in I2S_STATUS1 register is set to 1 and channel data will force zero. This function is only available in transmit operation.
16
1
read-write
0
Keep channel (Ch1,Ch3,Ch5,Ch7) data , when zero crossing flag on
#0
1
Force channel (Ch1,Ch3,Ch5,Ch7) data to zero, when zero crossing flag on
#1
I2SEN
I2S Controller Enable Control
0
1
read-write
0
I2S controller Disabled
#0
1
I2S controller Enabled
#1
MCLKEN
Master Clock Enable Control
If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data Control
Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Control
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Send zero on transmit channel
#1
ORDER
Stereo Data Order in FIFO
In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte. In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
7
1
read-write
0
Even channel data at high byte in 8-bit/16-bit data width
#0
1
Even channel data at low byte
#1
PCMSYNC
PCM Synchronization Pulse Length Selection
This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
Note: This bit is only available in master mode
27
1
read-write
0
One BCLK period
#0
1
One channel period
#1
RXEN
Receive Enable Control
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXFBCLR
Receive FIFO Buffer Clear
Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
Note2: This bit is cleared by hardware automatically, read it return zero.
19
1
read-write
0
No Effect
#0
1
Clear RX FIFO
#1
RXLCH
Receive Left Channel Enable Control
23
1
read-write
0
Receives channel1 data in MONO mode
#0
1
Receives channel0 data in MONO mode
#1
RXPDMAEN
Receive PDMA Enable Control
21
1
read-write
0
Receiver PDMA function Disabled
#0
1
Receiver PDMA function Enabled
#1
SLAVE
Slave Mode Enable Control
Note: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TDMCHNUM
TDM Channel Number
30
2
read-write
0
2 channels in audio frame
#00
1
4 channels in audio frame
#01
2
6 channels in audio frame
#10
3
8 channels in audio frame
#11
TXEN
Transmit Enable Control
1
1
read-write
0
Data transmission Disabled
#0
1
Data transmission Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
Note2: This bit is clear by hardware automatically, read it return zero.
18
1
read-write
0
No Effect
#0
1
Clear TX FIFO
#1
TXPDMAEN
Transmit PDMA Enable Control
20
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2Sn_CTL1
I2Sn_CTL1
I2S Control Register 1
0x20
-1
read-write
n
0x0
0x0
CH0ZCEN
Channel0 Zero-cross Detection Enable Control
Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
0
1
read-write
0
channel0 zero-cross detect Disabled
#0
1
channel0 zero-cross detect Enabled
#1
CH1ZCEN
Channel1 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
1
1
read-write
0
channel1 zero-cross detect Disabled
#0
1
channel1 zero-cross detect Enabled
#1
CH2ZCEN
Channel2 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
2
1
read-write
0
channel2 zero-cross detect Disabled
#0
1
channel2 zero-cross detect Enabled
#1
CH3ZCEN
Channel3 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
3
1
read-write
0
channel3 zero-cross detect Disabled
#0
1
channel3 zero-cross detect Enabled
#1
CH4ZCEN
Channel4 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
4
1
read-write
0
channel4 zero-cross detect Disabled
#0
1
channel4 zero-cross detect Enabled
#1
CH5ZCEN
Channel5 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
5
1
read-write
0
channel5 zero-cross detect Disabled
#0
1
channel5 zero-cross detect Enabled
#1
CH6ZCEN
Channel6 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
6
1
read-write
0
channel6 zero-cross detect Disabled
#0
1
channel6 zero-cross detect Enabled
#1
CH7ZCEN
Channel7 Zero-cross Detect Enable Control
Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
7
1
read-write
0
channel7 zero-cross detect Disabled
#0
1
channel7 zero-cross detect Enabled
#1
PB16ORD
FIFO Read/Write Order in 16-bit Width of Peripheral Bus
25
1
read-write
0
Low 16-bit read/write access first
#0
1
High 16-bit read/write access first
#1
PBWIDTH
Peripheral Bus Data Width Selection
This bit is used to choice the available data width of APB bus. It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
24
1
read-write
0
32 bits data width
#0
1
16 bits data width
#1
RXTH
Receive FIFO Threshold Level
Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
16
4
read-write
0
1 data word in receive FIFO
#0000
1
2 data words in receive FIFO
#0001
2
3 data words in receive FIFO
#0010
14
15 data words in receive FIFO
#1110
15
16 data words in receive FIFO
#1111
TXTH
Transmit FIFO Threshold Level
Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
8
4
read-write
0
0 data word in transmit FIFO
#0000
1
1 data word in transmit FIFO
#0001
2
2 data words in transmit FIFO
#0010
14
14 data words in transmit FIFO
#1110
15
15 data words in transmit FIFO
#1111
I2Sn_IEN
I2Sn_IEN
I2S Interrupt Enable Register
0x8
-1
read-write
n
0x0
0x0
CH0ZCIEN
Channel0 Zero-cross Interrupt Enable Control
16
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH1ZCIEN
Channel1 Zero-cross Interrupt Enable Control
17
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH2ZCIEN
Channel2 Zero-cross Interrupt Enable Control
18
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH3ZCIEN
Channel3 Zero-cross Interrupt Enable Control
19
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH4ZCIEN
Channel4 Zero-cross Interrupt Enable Control
20
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH5ZCIEN
Channel5 Zero-cross Interrupt Enable Control
21
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH6ZCIEN
Channel6 Zero-cross Interrupt Enable Control
22
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
CH7ZCIEN
Channel7 Zero-cross Interrupt Enable Control
23
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVFIEN
Receive FIFO Overflow Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt Enable Control
Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1. If RXTHIEN bit is enabled, interrupt occur.
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDFIEN
Receive FIFO Underflow Interrupt E Enable Control
Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVFIEN
Transmit FIFO Overflow Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable Control
Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDFIEN
Transmit FIFO Underflow Interrupt Enable Control
Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
I2Sn_RXFIFO
I2Sn_RXFIFO
I2S Receive FIFO Register
0x14
-1
read-only
n
0x0
0x0
RXFIFO
Receive FIFO Bits
I2S contains 16 words (16x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
0
32
read-only
I2Sn_STATUS0
I2Sn_STATUS0
I2S Status Register 0
0xC
-1
read-write
n
0x0
0x0
DATACH
Transmission Data Channel (Read Only)
This bit fields are used to indicate which audio channel is current transmit data belong.
3
3
read-only
0
channel0 (means left channel while 2-channel I2S/PCM mode)
#000
1
channel1 (means right channel while 2-channel I2S/PCM mode)
#001
2
channel2 (available while 4-channel TDM PCM mode)
#010
3
channel3 (available while 4-channel TDM PCM mode)
#011
4
channel4 (available while 6-channel TDM PCM mode)
#100
5
channel5 (available while 6-channel TDM PCM mode)
#101
6
channel6 (available while 8-channel TDM PCM mode)
#110
7
channel7 (available while 8-channel TDM PCM mode)
#111
I2SINT
I2S Interrupt Flag (Read Only)
Note: It is wire-OR of I2STXINT and I2SRXINT bits.
0
1
read-only
0
No I2S interrupt
#0
1
I2S interrupt
#1
I2SRXINT
I2S Receive Interrupt (Read Only)
1
1
read-only
0
No receive interrupt
#0
1
Receive interrupt
#1
I2STXINT
I2S Transmit Interrupt (Read Only)
2
1
read-only
0
No transmit interrupt
#0
1
Transmit interrupt
#1
RXEMPTY
Receive FIFO Empty (Read Only)
Note: This bit reflects data words number in receive FIFO is zero
12
1
read-only
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full (Read Only)
Note: This bit reflects data words number in receive FIFO is 12.
11
1
read-only
0
Not full
#0
1
Full
#1
RXOVIF
Receive FIFO Overflow Interrupt Flag
Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
Note2: Write 1 to clear this bit to 0.
9
1
read-write
0
No overflow occur
#0
1
Overflow occur
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
10
1
read-only
0
Data word(s) in FIFO is not higher than threshold level
#0
1
Data word(s) in FIFO is higher than threshold level
#1
RXUDIF
Receive FIFO Underflow Interrupt Flag
Note1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs.
Note2: Write 1 to clear this bit to zero
8
1
read-write
0
No underflow occur
#0
1
Underflow occur
#1
TXBUSY
Transmit Busy (Read Only)
Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
21
1
read-only
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit reflect data word number in transmit FIFO is zero
20
1
read-only
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full (Read Only)
This bit reflect data word number in transmit FIFO is 12
19
1
read-only
0
Not full
#0
1
Full
#1
TXOVIF
Transmit FIFO Overflow Interrupt Flag
Note1: Write data to transmit FIFO when it is full and this bit set to 1
Note2: Write 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
18
1
read-only
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal or lower than threshold level
#1
TXUDIF
Transmit FIFO Underflow Interrupt Flag
Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
Note2: Write 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
I2Sn_STATUS1
I2Sn_STATUS1
I2S Status Register 1
0x24
-1
read-write
n
0x0
0x0
CH0ZCIF
Channel0 Zero-cross Interrupt Flag
It indicates channel0 next sample data sign bit is changed or all data bits are zero.
0
1
read-write
0
No zero-cross in channel0
#0
1
Channel0 zero-cross is detected
#1
CH1ZCIF
Channel1 Zero-cross Interrupt Flag
It indicates channel1 next sample data sign bit is changed or all data bits are zero.
1
1
read-write
0
No zero-cross in channel1
#0
1
Channel1 zero-cross is detected
#1
CH2ZCIF
Channel2 Zero-cross Interrupt Flag
It indicates channel2 next sample data sign bit is changed or all data bits are zero.
2
1
read-write
0
No zero-cross in channel2
#0
1
Channel2 zero-cross is detected
#1
CH3ZCIF
Channel3 Zero-cross Interrupt Flag
It indicates channel3 next sample data sign bit is changed or all data bits are zero.
3
1
read-write
0
No zero-cross in channel3
#0
1
Channel3 zero-cross is detected
#1
CH4ZCIF
Channel4 Zero-cross Interrupt Flag
It indicates channel4 next sample data sign bit is changed or all data bits are zero.
4
1
read-write
0
No zero-cross in channel4
#0
1
Channel4 zero-cross is detected
#1
CH5ZCIF
Channel5 Zero-cross Interrupt Flag
It indicates channel5 next sample data sign bit is changed or all data bits are zero.
5
1
read-write
0
No zero-cross in channel5
#0
1
Channel5 zero-cross is detected
#1
CH6ZCIF
Channel6 Zero-cross Interrupt Flag
It indicates channel6 next sample data sign bit is changed or all data bits are zero.
6
1
read-write
0
No zero-cross in channel6
#0
1
Channel6 zero-cross is detected
#1
CH7ZCIF
Channel7 Zero-cross Interrupt Flag
It indicates channel7 next sample data sign bit is changed or all data bits are zero.
7
1
read-write
0
No zero-cross in channel7
#0
1
Channel7 zero-cross is detected
#1
RXCNT
Receive FIFO Level (Read Only)
These bits indicate the number of available entries in receive FIFO
Others are reserved. Do not use.
16
5
read-only
0
No data
#00000
1
1 word in receive FIFO
#00001
2
2 words in receive FIFO
#00010
14
14 words in receive FIFO
#01110
15
15 words in receive FIFO
#01111
16
16 words in receive FIFO
#10000
TXCNT
Transmit FIFO Level (Read Only)
These bits indicate the number of available entries in transmit FIFO
Others are reserved. Do not use.
8
5
read-only
0
No data
#00000
1
1 word in transmit FIFO
#00001
2
2 words in transmit FIFO
#00010
14
14 words in transmit FIFO
#01110
15
15 words in transmit FIFO
#01111
16
16 words in transmit FIFO
#10000
I2Sn_TXFIFO
I2Sn_TXFIFO
I2S Transmit FIFO Register
0x10
-1
write-only
n
0x0
0x0
TXFIFO
Transmit FIFO Bits
I2S contains 16 words (16x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0xC
registers
n
0x10
0xC
registers
n
0x84
0x8
registers
n
DINTEN
INT_DINTEN
DSP Interrupt Source Enable Register
0x18
-1
read-write
n
0x0
0x0
BODEN
BOD DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
BOD DSP Interrupt source Disabled
#0
1
BOD DSP Interrupt source Enabled
#1
CLKFEN
CLKFAIL DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CLKFAIL DSP Interrupt source Disabled
#0
1
CLKFAIL DSP Interrupt source Enabled
#1
DMICEN
DMIC DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
DMIC DSP Interrupt source Disabled
#0
1
DMIC DSP Interrupt source Enabled
#1
GPAEN
GPA DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
GPA DSP Interrupt source Disabled
#0
1
GPA DSP Interrupt source Enabled
#1
GPBEN
GPB DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
GPB DSP Interrupt source Disabled
#0
1
GPB DSP Interrupt source Enabled
#1
GPCEN
GPC DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
GPC DSP Interrupt source Disabled
#0
1
GPC DSP Interrupt source Enabled
#1
GPDEN
GPD DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
GPD DSP Interrupt source Disabled
#0
1
GPD DSP Interrupt source Enabled
#1
IRCEN
IRC DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
IRC DSP Interrupt source Disabled
#0
1
IRC DSP Interrupt source Enabled
#1
PWM0P0EN
PWM0_P0 DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
PWM0_P0 DSP Interrupt source Disabled
#0
1
PWM0_P0 DSP Interrupt source Enabled
#1
PWM0P1EN
PWM0_P1 DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
PWM0_P1 DSP Interrupt source Disabled
#0
1
PWM0_P1 DSP Interrupt source Enabled
#1
PWM0P2EN
PWM0_P2 DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
PWM0_P2 DSP Interrupt source Disabled
#0
1
PWM0_P2 DSP Interrupt source Enabled
#1
PWRWUEN
PWRWU DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
PWRWU DSP Interrupt source Disabled
#0
1
PWRWU DSP Interrupt source Enabled
#1
VADEN
VAD DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
VAD DSP Interrupt source Disabled
#0
1
VAD DSP Interrupt source Enabled
#1
WDTEN
WDT DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
WDT DSP Interrupt source Disabled
#0
1
WDT DSP Interrupt source Enabled
#1
WWDTEN
WWDT DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
WWDT DSP Interrupt source Disabled
#0
1
WWDT DSP Interrupt source Enabled
#1
XCLKFEN
XCLKFAIL DSP Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
XCLKFAIL DSP Interrupt source Disabled
#0
1
XCLKFAIL DSP Interrupt source Enabled
#1
DIRQ
INT_DIRQ
DSP Interrupt Request Source Register
0x88
-1
read-write
n
0x0
0x0
IRQ
DSP IRQ Source Register
The INT_DIRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to DSP.
0
26
read-write
DNMIEN
INT_DNMIEN
DSP NMI Source Interrupt Enable Register
0x10
-1
read-write
n
0x0
0x0
BODINT
BOD NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt 0 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt 0 NMI source Disabled
#0
1
External interrupt 0 NMI source Enabled
#1
EINT1
External Interrupt 1 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt 1 NMI source Disabled
#0
1
External interrupt 1 NMI source Enabled
#1
IRCINT
IRC TRIM NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWUINT
Power-down Mode Wake-up NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTCINT
RTC NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
UART0INT
UART0 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1INT
UART1 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
XCLKFAIL
MCLK Input Fail Detected NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
MCLK input fail detected interrupt NMI source Disabled
#0
1
MCLK input fail detected interrupt NMI source Enabled
#1
DNMISTS
INT_DNMISTS
DSP NMI Source Interrupt Status Register
0x14
-1
read-only
n
0x0
0x0
BODINT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt 0 Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt 0 interrupt is deasserted
#0
1
External Interrupt 0 interrupt is asserted
#1
EINT1
External Interrupt 1 Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt 1 interrupt is deasserted
#0
1
External Interrupt 1 interrupt is asserted
#1
IRCINT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWUINT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTCINT
RTC Interrupt Flag (Read Only)
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
UART0INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART0 interrupt is deasserted
#0
1
UART0 interrupt is asserted
#1
UART1INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
XCLKFAIL
XCLK Fail Detected Interrupt Flag (Read Only)
5
1
read-only
0
MCLK input fail detected interrupt is deasserted
#0
1
MCLK input fail detected interrupt is asserted
#1
MINTEN
INT_MINTEN
MCU Interrupt Source Enable Register
0x8
-1
read-write
n
0x0
0x0
BODEN
BOD MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
BOD MCU Interrupt source Disabled
#0
1
BOD MCU Interrupt source Enabled
#1
CLKFEN
CLKFAIL MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CLKFAIL MCU Interrupt source Disabled
#0
1
CLKFAIL MCU Interrupt source Enabled
#1
DMICEN
DMIC MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
DMIC MCU Interrupt source Disabled
#0
1
DMIC MCU Interrupt source Enabled
#1
IRCEN
IRC MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
IRC MCU Interrupt source Disabled
#0
1
IRC MCU Interrupt source Enabled
#1
PWM0P0EN
PWM0_P0 MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
PWM0_P0 MCU Interrupt source Disabled
#0
1
PWM0_P0 MCU Interrupt source Enabled
#1
PWM0P1EN
PWM0_P1 MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
PWM0_P1 MCU Interrupt source Disabled
#0
1
PWM0_P1 MCU Interrupt source Enabled
#1
PWM0P2EN
PWM0_P2 MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
PWM0_P2 MCU Interrupt source Disabled
#0
1
PWM0_P2 MCU Interrupt source Enabled
#1
PWRWUEN
PWRWU MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
PWRWU MCU Interrupt source Disabled
#0
1
PWRWU MCU Interrupt source Enabled
#1
VADEN
VAD MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
VAD MCU Interrupt source Disabled
#0
1
VAD MCU Interrupt source Enabled
#1
WDTEN
WDT MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
WDT MCU Interrupt source Disabled
#0
1
WDT MCU Interrupt source Enabled
#1
WWDTEN
WWDT MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
WWDT MCU Interrupt source Disabled
#0
1
WWDT MCU Interrupt source Enabled
#1
XCLKFEN
XCLKFAIL MCU Interrupt Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
XCLKFAIL MCU Interrupt source Disabled
#0
1
XCLKFAIL MCU Interrupt source Enabled
#1
MIRQ
INT_MIRQ
MCU Interrupt Request Source Register
0x84
-1
read-write
n
0x0
0x0
IRQ
MCU IRQ Source Register
The INT_MIRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU.
0
32
read-write
MNMIEN
INT_MNMIEN
MCU NMI Source Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BODINT
BOD NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt 0 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt 0 NMI source Disabled
#0
1
External interrupt 0 NMI source Enabled
#1
EINT1
External Interrupt 1 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt 1 NMI source Disabled
#0
1
External interrupt 1 NMI source Enabled
#1
IRCINT
IRC TRIM NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWUINT
Power-down Mode Wake-up NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTCINT
RTC NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
UART0INT
UART0 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1INT
UART1 NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
XCLKFAIL
MCLK Input Fail Detected NMI Source Enable (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
MCLK input fail detected interrupt NMI source Disabled
#0
1
MCLK input fail detected interrupt NMI source Enabled
#1
MNMISTS
INT_MNMISTS
MCU NMI Source Interrupt Status Register
0x4
-1
read-only
n
0x0
0x0
BODINT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt 0 Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt 0 interrupt is deasserted
#0
1
External Interrupt 0 interrupt is asserted
#1
EINT1
External Interrupt 1 Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt 1 interrupt is deasserted
#0
1
External Interrupt 1 interrupt is asserted
#1
IRCINT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWUINT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTCINT
RTC Interrupt Flag (Read Only)
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
UART0INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART0 interrupt is deasserted
#0
1
UART0 interrupt is asserted
#1
UART1INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
XCLKFAIL
XCLK Fail Detected Interrupt Flag (Read Only)
5
1
read-only
0
MCLK input fail detected interrupt is deasserted
#0
1
MCLK input fail detected interrupt is asserted
#1
OMC
OMC Register Map
OMC
0x0
0x0
0x14
registers
n
0x40
0x4
registers
n
ISPADDR
OMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address
ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
For CRC32 Checksum Calculation command, this field is the OTP starting address for checksum calculation, 32 bytes alignment is necessary for CRC32 checksum calculation.
For 32-bit Program, ISP address needs word alignment (4-byte).
0
32
read-write
ISPCMD
OMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP Command
ISP command table is shown below:
The other commands are invalid.
Note: The supply voltage of VDD must be higher than 2.5V for OTP programming.
0
7
read-write
0
32-Bit Read
0x00
4
Read Unique ID
0x04
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read Checksum
0x0d
33
32-bit Program
0x21
45
Run Checksum Calculation
0x2d
46
Vector Remap
0x2e
ISPCTL
OMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
ISPEN
ISP Enable Bit (Write Protected)
ISP function enable bit. Set this bit to enable ISP function.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protected)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) Destination address is illegal, such as over an available range.
(2) Invalid ISP commands.
(3) Program command at the address which is already programmed.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit needs to be cleared by writing 1 to it.
6
1
read-write
ISPDAT
OMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
0
32
read-write
ISPSTS
OMC_ISPSTS
ISP Status Register
0x40
-1
read-only
n
0x0
0x0
ISPBUSY
ISP Busy Flag (Read Only)
This bit is the mirror of ISPGO (OMC_ISPTRG[0]).
0
1
read-only
0
ISP operation is finished
#0
1
ISP is progressed
#1
ISPFF
ISP Fail Flag (Read Only)
This bit is the mirror of ISPFF(OMC_ISPCTL[6]), it needs to be cleared by writing 1 to OMC_ISPCTL[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) Destination address is illegal, such as over an available range.
(2) Invalid ISP commands.
(3) Program command at the address which is already programmed.
6
1
read-only
VECMAP
Vector Page Mapping Address (Read Only)
The current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}
9
21
read-only
ISPTRG
OMC_ISPTRG
ISP Trigger Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protected)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x140
registers
n
0x400
0x3C
registers
n
0x440
0x4
registers
n
0x450
0xC
registers
n
0x460
0x4
registers
n
0x480
0x10
registers
n
0x500
0x30
registers
n
0x540
0x40
registers
n
0x600
0x10
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
-1
read-write
n
0x0
0x0
ABTIF0
PDMA Channel 0 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 0 has target abort error User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel 0 transfer
#0
1
AHB bus ERROR response received when channel 0 transfer
#1
ABTIF1
PDMA Channel 1 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 1 has target abort error User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel 1 transfer
#0
1
AHB bus ERROR response received when channel 1 transfer
#1
ABTIF10
PDMA Channel 10 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 10 has target abort error User can write 1 to clear these bits.
10
1
read-write
0
No AHB bus ERROR response received when channel 10 transfer
#0
1
AHB bus ERROR response received when channel 10 transfer
#1
ABTIF11
PDMA Channel 11 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 11 has target abort error User can write 1 to clear these bits.
11
1
read-write
0
No AHB bus ERROR response received when channel 11 transfer
#0
1
AHB bus ERROR response received when channel 11 transfer
#1
ABTIF12
PDMA Channel 12 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 12 has target abort error User can write 1 to clear these bits.
12
1
read-write
0
No AHB bus ERROR response received when channel 12 transfer
#0
1
AHB bus ERROR response received when channel 12 transfer
#1
ABTIF13
PDMA Channel 13 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 13 has target abort error User can write 1 to clear these bits.
13
1
read-write
0
No AHB bus ERROR response received when channel 13 transfer
#0
1
AHB bus ERROR response received when channel 13 transfer
#1
ABTIF14
PDMA Channel 14 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 14 has target abort error User can write 1 to clear these bits.
14
1
read-write
0
No AHB bus ERROR response received when channel 14 transfer
#0
1
AHB bus ERROR response received when channel 14 transfer
#1
ABTIF15
PDMA Channel 15 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 15 has target abort error User can write 1 to clear these bits.
15
1
read-write
0
No AHB bus ERROR response received when channel 15 transfer
#0
1
AHB bus ERROR response received when channel 15 transfer
#1
ABTIF2
PDMA Channel 2 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 2 has target abort error User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel 2 transfer
#0
1
AHB bus ERROR response received when channel 2 transfer
#1
ABTIF3
PDMA Channel 3 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 3 has target abort error User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel 3 transfer
#0
1
AHB bus ERROR response received when channel 3 transfer
#1
ABTIF4
PDMA Channel 4 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 4 has target abort error User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel 4 transfer
#0
1
AHB bus ERROR response received when channel 4 transfer
#1
ABTIF5
PDMA Channel 5 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 5 has target abort error User can write 1 to clear these bits.
5
1
read-write
0
No AHB bus ERROR response received when channel 5 transfer
#0
1
AHB bus ERROR response received when channel 5 transfer
#1
ABTIF6
PDMA Channel 6 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 6 has target abort error User can write 1 to clear these bits.
6
1
read-write
0
No AHB bus ERROR response received when channel 6 transfer
#0
1
AHB bus ERROR response received when channel 6 transfer
#1
ABTIF7
PDMA Channel 7 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 7 has target abort error User can write 1 to clear these bits.
7
1
read-write
0
No AHB bus ERROR response received when channel 7 transfer
#0
1
AHB bus ERROR response received when channel 7 transfer
#1
ABTIF8
PDMA Channel 8 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 8 has target abort error User can write 1 to clear these bits.
8
1
read-write
0
No AHB bus ERROR response received when channel 8 transfer
#0
1
AHB bus ERROR response received when channel 8 transfer
#1
ABTIF9
PDMA Channel 9 Read/Write Target Abort Interrupt Status Flag
This bit indicates PDMA channel 9 has target abort error User can write 1 to clear these bits.
9
1
read-write
0
No AHB bus ERROR response received when channel 9 transfer
#0
1
AHB bus ERROR response received when channel 9 transfer
#1
AICTL0
PDMA_AICTL0
Address Interval Control Register of PDMA Channel 0
0x600
-1
read-write
n
0x0
0x0
DAICNT
PDMA Destination Address Interval Count
The 16-bit register defines the destination address interval count of each row.
16
16
read-write
SAICNT
PDMA Source Address Interval Count
The 16-bit register defines the source address interval count of each row.
0
16
read-write
AICTL1
PDMA_AICTL1
Address Interval Control Register of PDMA Channel 1
0x608
-1
read-write
n
0x0
0x0
ALIGN
PDMA_ALIGN
PDMA Transfer Alignment Status Register
0x428
-1
read-write
n
0x0
0x0
ALIGN0
PDMA Channel 0 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
0
1
read-write
0
PDMA channel 0 source address and destination address both follow transfer width setting
#0
1
PDMA channel 0 source address or destination address is not follow transfer width setting
#1
ALIGN1
PDMA Channel 1 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
1
1
read-write
0
PDMA channel 1 source address and destination address both follow transfer width setting
#0
1
PDMA channel 1 source address or destination address is not follow transfer width setting
#1
ALIGN10
PDMA Channel 10 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
10
1
read-write
0
PDMA channel 10 source address and destination address both follow transfer width setting
#0
1
PDMA channel 10 source address or destination address is not follow transfer width setting
#1
ALIGN11
PDMA Channel 11 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
11
1
read-write
0
PDMA channel 11 source address and destination address both follow transfer width setting
#0
1
PDMA channel 11 source address or destination address is not follow transfer width setting
#1
ALIGN12
PDMA Channel 12 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
12
1
read-write
0
PDMA channel 12 source address and destination address both follow transfer width setting
#0
1
PDMA channel 12 source address or destination address is not follow transfer width setting
#1
ALIGN13
PDMA Channel 13 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
13
1
read-write
0
PDMA channel 13 source address and destination address both follow transfer width setting
#0
1
PDMA channel 13 source address or destination address is not follow transfer width setting
#1
ALIGN14
PDMA Channel 14 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
14
1
read-write
0
PDMA channel 14 source address and destination address both follow transfer width setting
#0
1
PDMA channel 14 source address or destination address is not follow transfer width setting
#1
ALIGN15
PDMA Channel 15 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
15
1
read-write
0
PDMA channel 15 source address and destination address both follow transfer width setting
#0
1
PDMA channel 15 source address or destination address is not follow transfer width setting
#1
ALIGN2
PDMA Channel 2 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
2
1
read-write
0
PDMA channel 2 source address and destination address both follow transfer width setting
#0
1
PDMA channel 2 source address or destination address is not follow transfer width setting
#1
ALIGN3
PDMA Channel 3 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
3
1
read-write
0
PDMA channel 3 source address and destination address both follow transfer width setting
#0
1
PDMA channel 3 source address or destination address is not follow transfer width setting
#1
ALIGN4
PDMA Channel 4 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
4
1
read-write
0
PDMA channel 4 source address and destination address both follow transfer width setting
#0
1
PDMA channel 4 source address or destination address is not follow transfer width setting
#1
ALIGN5
PDMA Channel 5 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
5
1
read-write
0
PDMA channel 5 source address and destination address both follow transfer width setting
#0
1
PDMA channel 5 source address or destination address is not follow transfer width setting
#1
ALIGN6
PDMA Channel 6 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
6
1
read-write
0
PDMA channel 6 source address and destination address both follow transfer width setting
#0
1
PDMA channel 6 source address or destination address is not follow transfer width setting
#1
ALIGN7
PDMA Channel 7 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
7
1
read-write
0
PDMA channel 7 source address and destination address both follow transfer width setting
#0
1
PDMA channel 7 source address or destination address is not follow transfer width setting
#1
ALIGN8
PDMA Channel 8 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
8
1
read-write
0
PDMA channel 8 source address and destination address both follow transfer width setting
#0
1
PDMA channel 8 source address or destination address is not follow transfer width setting
#1
ALIGN9
PDMA Channel 9 Transfer Alignment Flag Register
Note: Software can write 1 to clear this bit.
9
1
read-write
0
PDMA channel 9 source address and destination address both follow transfer width setting
#0
1
PDMA channel 9 source address or destination address is not follow transfer width setting
#1
ASOCR0
PDMA_ASOCR0
Address Stride Offset Register of PDMA Channel 0
0x504
-1
read-write
n
0x0
0x0
DASOL
PDMA Destination Address Stride Offset Length
The 16-bit register defines the destination address stride transfer offset count of each row.
16
16
read-write
SASOL
PDMA Source Address Stride Offset Length
The 16-bit register defines the source address stride transfer offset count of each row.
0
16
read-write
ASOCR1
PDMA_ASOCR1
Address Stride Offset Register of PDMA Channel 1
0x50C
-1
read-write
n
0x0
0x0
ASOCR2
PDMA_ASOCR2
Address Stride Offset Register of PDMA Channel 2
0x514
-1
read-write
n
0x0
0x0
ASOCR3
PDMA_ASOCR3
Address Stride Offset Register of PDMA Channel 3
0x51C
-1
read-write
n
0x0
0x0
ASOCR4
PDMA_ASOCR4
Address Stride Offset Register of PDMA Channel 4
0x524
-1
read-write
n
0x0
0x0
ASOCR5
PDMA_ASOCR5
Address Stride Offset Register of PDMA Channel 5
0x52C
-1
read-write
n
0x0
0x0
CHCTL
PDMA_CHCTL
PDMA Channel Control 0 Register
0x400
-1
read-write
n
0x0
0x0
CHEN0
PDMA Channel 0 Enable Bit
Set this bit to 1 to enable PDMA channel 0 operation. Channel 0 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
0
1
read-write
0
PDMA Channel 0 Disabled
#0
1
PDMA Channel 0 Enabled
#1
CHEN1
PDMA Channel 1 Enable Bit
Set this bit to 1 to enable PDMA channel 1 operation. Channel 1 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
1
1
read-write
0
PDMA Channel 1 Disabled
#0
1
PDMA Channel 1 Enabled
#1
CHEN10
PDMA Channel 10 Enable Bit
Set this bit to 1 to enable PDMA channel 10 operation. Channel 10 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
10
1
read-write
0
PDMA Channel 10 Disabled
#0
1
PDMA Channel 10 Enabled
#1
CHEN11
PDMA Channel 11 Enable Bit
Set this bit to 1 to enable PDMA channel 11 operation. Channel 11 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
11
1
read-write
0
PDMA Channel 11 Disabled
#0
1
PDMA Channel 11 Enabled
#1
CHEN12
PDMA Channel 12 Enable Bit
Set this bit to 1 to enable PDMA channel 12 operation. Channel 12 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
12
1
read-write
0
PDMA Channel 12 Disabled
#0
1
PDMA Channel 12 Enabled
#1
CHEN13
PDMA Channel 13 Enable Bit
Set this bit to 1 to enable PDMA channel 13 operation. Channel 13 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
13
1
read-write
0
PDMA Channel 13 Disabled
#0
1
PDMA Channel 13 Enabled
#1
CHEN14
PDMA Channel 14 Enable Bit
Set this bit to 1 to enable PDMA channel 14 operation. Channel 14 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
14
1
read-write
0
PDMA Channel 14 Disabled
#0
1
PDMA Channel 14 Enabled
#1
CHEN15
PDMA Channel 15 Enable Bit
Set this bit to 1 to enable PDMA channel 15 operation. Channel 15 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
15
1
read-write
0
PDMA Channel 15 Disabled
#0
1
PDMA Channel 15 Enabled
#1
CHEN2
PDMA Channel 2 Enable Bit
Set this bit to 1 to enable PDMA channel 2 operation. Channel 2 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
2
1
read-write
0
PDMA Channel 2 Disabled
#0
1
PDMA Channel 2 Enabled
#1
CHEN3
PDMA Channel 3 Enable Bit
Set this bit to 1 to enable PDMA channel 3 operation. Channel 3 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
3
1
read-write
0
PDMA Channel 3 Disabled
#0
1
PDMA Channel 3 Enabled
#1
CHEN4
PDMA Channel 4 Enable Bit
Set this bit to 1 to enable PDMA channel 4 operation. Channel 4 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
4
1
read-write
0
PDMA Channel 4 Disabled
#0
1
PDMA Channel 4 Enabled
#1
CHEN5
PDMA Channel 5 Enable Bit
Set this bit to 1 to enable PDMA channel 5 operation. Channel 5 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
5
1
read-write
0
PDMA Channel 5 Disabled
#0
1
PDMA Channel 5 Enabled
#1
CHEN6
PDMA Channel 6 Enable Bit
Set this bit to 1 to enable PDMA channel 6 operation. Channel 6 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
6
1
read-write
0
PDMA Channel 6 Disabled
#0
1
PDMA Channel 6 Enabled
#1
CHEN7
PDMA Channel 7 Enable Bit
Set this bit to 1 to enable PDMA channel 7 operation. Channel 7 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
7
1
read-write
0
PDMA Channel 7 Disabled
#0
1
PDMA Channel 7 Enabled
#1
CHEN8
PDMA Channel 8 Enable Bit
Set this bit to 1 to enable PDMA channel 8 operation. Channel 8 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
8
1
read-write
0
PDMA Channel 8 Disabled
#0
1
PDMA Channel 8 Enabled
#1
CHEN9
PDMA Channel 9 Enable Bit
Set this bit to 1 to enable PDMA channel 9 operation. Channel 9 cannot be active if it is not set as enabled.
Note: Set corresponding bit of PDMA_STOP or PDMA_CHRST register will also clear this bit.
9
1
read-write
0
PDMA channel 9 Disabled
#0
1
PDMA channel 9 Enabled
#1
CHRST
PDMA_CHRST
PDMA Channel Reset Register
0x460
-1
read-write
n
0x0
0x0
CH0RST
Channel 0 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
0
1
read-write
0
corresponding channel 0 not reset
#0
1
corresponding channel 0 is reset
#1
CH10RST
Channel 10 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
10
1
read-write
0
corresponding channel 10 not reset
#0
1
corresponding channel 10 is reset
#1
CH11RST
Channel 11 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
11
1
read-write
0
corresponding channel 11 not reset
#0
1
corresponding channel 11 is reset
#1
CH12RST
Channel 12 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
12
1
read-write
0
corresponding channel 12 not reset
#0
1
corresponding channel 12 is reset
#1
CH13RST
Channel 13 Reset
Note 1 : This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
13
1
read-write
0
corresponding channel 13 not reset
#0
1
corresponding channel 13 is reset
#1
CH14RST
Channel 14 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
14
1
read-write
0
corresponding channel 14 not reset
#0
1
corresponding channel 14 is reset
#1
CH15RST
Channel 15 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
15
1
read-write
0
corresponding channel 15 not reset
#0
1
corresponding channel 15 is reset
#1
CH1RST
Channel 1 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
1
1
read-write
0
corresponding channel 1 not reset
#0
1
corresponding channel 1 is reset
#1
CH2RST
Channel 2 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
2
1
read-write
0
corresponding channel 2 not reset
#0
1
corresponding channel 2 is reset
#1
CH3RST
Channel 3 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
3
1
read-write
0
corresponding channel 3 not reset
#0
1
corresponding channel 3 is reset
#1
CH4RST
Channel 4 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
4
1
read-write
0
corresponding channel 4 not reset
#0
1
corresponding channel 4 is reset
#1
CH5RST
Channel 5 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
5
1
read-write
0
corresponding channel 5 not reset
#0
1
corresponding channel 5 is reset
#1
CH6RST
Channel 6 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
6
1
read-write
0
corresponding channel 6 not reset
#0
1
corresponding channel 6 is reset
#1
CH7RST
Channel 7 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
7
1
read-write
0
corresponding channel 7 not reset
#0
1
corresponding channel 7 is reset
#1
CH8RST
Channel 8 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
8
1
read-write
0
corresponding channel 8 not reset
#0
1
corresponding channel 8 is reset
#1
CH9RST
Channel 9 Reset
Note 1: This bit will be cleared automatically after finishing reset.
Note 2 : Set this bit to 1 will also clear corresponding bit of PDMA_CHCTL.
9
1
read-write
0
corresponding channel 9 not reset
#0
1
corresponding channel 9 is reset
#1
COMSCAT0
PDMA_COMSCAT0
Complete Scatter-gather Descriptor Table Address of PDMA Channel 0
0x540
-1
read-write
n
0x0
0x0
COMADDR
PDMA Complete Description Address Register
This field indicates a 32-bit complete external description address of PDMA controller.
Write Operation:
Write any value to this field will clear this field to 0
Read Operation:
Indicates a 32-bit complete external description address
Note: This field is only used for Scatter-Gather mode to indicate the complete external description address.
0
32
read-write
COMSCAT1
PDMA_COMSCAT1
Complete Scatter-gather Descriptor Table Address of PDMA Channel 1
0x544
-1
read-write
n
0x0
0x0
COMSCAT10
PDMA_COMSCAT10
Complete Scatter-gather Descriptor Table Address of PDMA Channel 10
0x568
-1
read-write
n
0x0
0x0
COMSCAT11
PDMA_COMSCAT11
Complete Scatter-gather Descriptor Table Address of PDMA Channel 11
0x56C
-1
read-write
n
0x0
0x0
COMSCAT12
PDMA_COMSCAT12
Complete Scatter-gather Descriptor Table Address of PDMA Channel 12
0x570
-1
read-write
n
0x0
0x0
COMSCAT13
PDMA_COMSCAT13
Complete Scatter-gather Descriptor Table Address of PDMA Channel 13
0x574
-1
read-write
n
0x0
0x0
COMSCAT14
PDMA_COMSCAT14
Complete Scatter-gather Descriptor Table Address of PDMA Channel 14
0x578
-1
read-write
n
0x0
0x0
COMSCAT15
PDMA_COMSCAT15
Complete Scatter-gather Descriptor Table Address of PDMA Channel 15
0x57C
-1
read-write
n
0x0
0x0
COMSCAT2
PDMA_COMSCAT2
Complete Scatter-gather Descriptor Table Address of PDMA Channel 2
0x548
-1
read-write
n
0x0
0x0
COMSCAT3
PDMA_COMSCAT3
Complete Scatter-gather Descriptor Table Address of PDMA Channel 3
0x54C
-1
read-write
n
0x0
0x0
COMSCAT4
PDMA_COMSCAT4
Complete Scatter-gather Descriptor Table Address of PDMA Channel 4
0x550
-1
read-write
n
0x0
0x0
COMSCAT5
PDMA_COMSCAT5
Complete Scatter-gather Descriptor Table Address of PDMA Channel 5
0x554
-1
read-write
n
0x0
0x0
COMSCAT6
PDMA_COMSCAT6
Complete Scatter-gather Descriptor Table Address of PDMA Channel 6
0x558
-1
read-write
n
0x0
0x0
COMSCAT7
PDMA_COMSCAT7
Complete Scatter-gather Descriptor Table Address of PDMA Channel 7
0x55C
-1
read-write
n
0x0
0x0
COMSCAT8
PDMA_COMSCAT8
Complete Scatter-gather Descriptor Table Address of PDMA Channel 8
0x560
-1
read-write
n
0x0
0x0
COMSCAT9
PDMA_COMSCAT9
Complete Scatter-gather Descriptor Table Address of PDMA Channel 9
0x564
-1
read-write
n
0x0
0x0
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel 0
0x100
-1
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address Register (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel 1
0x104
-1
read-write
n
0x0
0x0
CURSCAT10
PDMA_CURSCAT10
Current Scatter-gather Descriptor Table Address of PDMA Channel 10
0x128
-1
read-write
n
0x0
0x0
CURSCAT11
PDMA_CURSCAT11
Current Scatter-gather Descriptor Table Address of PDMA Channel 11
0x12C
-1
read-write
n
0x0
0x0
CURSCAT12
PDMA_CURSCAT12
Current Scatter-gather Descriptor Table Address of PDMA Channel 12
0x130
-1
read-write
n
0x0
0x0
CURSCAT13
PDMA_CURSCAT13
Current Scatter-gather Descriptor Table Address of PDMA Channel 13
0x134
-1
read-write
n
0x0
0x0
CURSCAT14
PDMA_CURSCAT14
Current Scatter-gather Descriptor Table Address of PDMA Channel 14
0x138
-1
read-write
n
0x0
0x0
CURSCAT15
PDMA_CURSCAT15
Current Scatter-gather Descriptor Table Address of PDMA Channel 15
0x13C
-1
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel 2
0x108
-1
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel 3
0x10C
-1
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel 4
0x110
-1
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel 5
0x114
-1
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel 6
0x118
-1
read-write
n
0x0
0x0
CURSCAT7
PDMA_CURSCAT7
Current Scatter-gather Descriptor Table Address of PDMA Channel 7
0x11C
-1
read-write
n
0x0
0x0
CURSCAT8
PDMA_CURSCAT8
Current Scatter-gather Descriptor Table Address of PDMA Channel 8
0x120
-1
read-write
n
0x0
0x0
CURSCAT9
PDMA_CURSCAT9
Current Scatter-gather Descriptor Table Address of PDMA Channel 9
0x124
-1
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel 0
0x0
-1
read-write
n
0x0
0x0
BURSIZE
Burst Size
This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
Note: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment
This field is used to set the destination address increment size.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection
Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted
#01
2
Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute
#10
3
Reserved. Do not use
#11
SAINC
Source Address Increment
This field is used to set the source address increment size.
8
2
read-write
3
No increment (fixed address)
#11
STRIDEEN
Stride Mode Enable Bit
15
1
read-write
0
Stride transfer mode Disabled
#0
1
Stride transfer mode Enabled
#1
TBINTDIS
Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. This bit is only used for scatter-gather mode. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finish each transfer data, this field will be decrease immediately.
16
16
read-write
TXTYPE
Transfer Type
Note: When transfer to/from DRAM and IRAM, recommend that using 64-byte address alignment in burst mode to improve access efficiency.
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved. Do not use
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel 0
0x8
-1
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address Register
This field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 0
0xC
-1
read-write
n
0x0
0x0
NEXT
PDMA Next Descriptor Table Offset
This field indicates the offset of the next descriptor table address in memory.
When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
Note 1: The first descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
32
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel 0
0x4
-1
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT10_CTL
PDMA_DSCT10_CTL
Descriptor Table Control Register of PDMA Channel 10
0xA0
-1
read-write
n
0x0
0x0
DSCT10_DA
PDMA_DSCT10_DA
Destination Address Register of PDMA Channel 10
0xA8
-1
read-write
n
0x0
0x0
DSCT10_NEXT
PDMA_DSCT10_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 10
0xAC
-1
read-write
n
0x0
0x0
DSCT10_SA
PDMA_DSCT10_SA
Source Address Register of PDMA Channel 10
0xA4
-1
read-write
n
0x0
0x0
DSCT11_CTL
PDMA_DSCT11_CTL
Descriptor Table Control Register of PDMA Channel 11
0xB0
-1
read-write
n
0x0
0x0
DSCT11_DA
PDMA_DSCT11_DA
Destination Address Register of PDMA Channel 11
0xB8
-1
read-write
n
0x0
0x0
DSCT11_NEXT
PDMA_DSCT11_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 11
0xBC
-1
read-write
n
0x0
0x0
DSCT11_SA
PDMA_DSCT11_SA
Source Address Register of PDMA Channel 11
0xB4
-1
read-write
n
0x0
0x0
DSCT12_CTL
PDMA_DSCT12_CTL
Descriptor Table Control Register of PDMA Channel 12
0xC0
-1
read-write
n
0x0
0x0
DSCT12_DA
PDMA_DSCT12_DA
Destination Address Register of PDMA Channel 12
0xC8
-1
read-write
n
0x0
0x0
DSCT12_NEXT
PDMA_DSCT12_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 12
0xCC
-1
read-write
n
0x0
0x0
DSCT12_SA
PDMA_DSCT12_SA
Source Address Register of PDMA Channel 12
0xC4
-1
read-write
n
0x0
0x0
DSCT13_CTL
PDMA_DSCT13_CTL
Descriptor Table Control Register of PDMA Channel 13
0xD0
-1
read-write
n
0x0
0x0
DSCT13_DA
PDMA_DSCT13_DA
Destination Address Register of PDMA Channel 13
0xD8
-1
read-write
n
0x0
0x0
DSCT13_NEXT
PDMA_DSCT13_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 13
0xDC
-1
read-write
n
0x0
0x0
DSCT13_SA
PDMA_DSCT13_SA
Source Address Register of PDMA Channel 13
0xD4
-1
read-write
n
0x0
0x0
DSCT14_CTL
PDMA_DSCT14_CTL
Descriptor Table Control Register of PDMA Channel 14
0xE0
-1
read-write
n
0x0
0x0
DSCT14_DA
PDMA_DSCT14_DA
Destination Address Register of PDMA Channel 14
0xE8
-1
read-write
n
0x0
0x0
DSCT14_NEXT
PDMA_DSCT14_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 14
0xEC
-1
read-write
n
0x0
0x0
DSCT14_SA
PDMA_DSCT14_SA
Source Address Register of PDMA Channel 14
0xE4
-1
read-write
n
0x0
0x0
DSCT15_CTL
PDMA_DSCT15_CTL
Descriptor Table Control Register of PDMA Channel 15
0xF0
-1
read-write
n
0x0
0x0
DSCT15_DA
PDMA_DSCT15_DA
Destination Address Register of PDMA Channel 15
0xF8
-1
read-write
n
0x0
0x0
DSCT15_NEXT
PDMA_DSCT15_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 15
0xFC
-1
read-write
n
0x0
0x0
DSCT15_SA
PDMA_DSCT15_SA
Source Address Register of PDMA Channel 15
0xF4
-1
read-write
n
0x0
0x0
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel 1
0x10
-1
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel 1
0x18
-1
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 1
0x1C
-1
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel 1
0x14
-1
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel 2
0x20
-1
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel 2
0x28
-1
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 2
0x2C
-1
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel 2
0x24
-1
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel 3
0x30
-1
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel 3
0x38
-1
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 3
0x3C
-1
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel 3
0x34
-1
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel 4
0x40
-1
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel 4
0x48
-1
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 4
0x4C
-1
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel 4
0x44
-1
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel 5
0x50
-1
read-write
n
0x0
0x0
DSCT5_DA
PDMA_DSCT5_DA
Destination Address Register of PDMA Channel 5
0x58
-1
read-write
n
0x0
0x0
DSCT5_NEXT
PDMA_DSCT5_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 5
0x5C
-1
read-write
n
0x0
0x0
DSCT5_SA
PDMA_DSCT5_SA
Source Address Register of PDMA Channel 5
0x54
-1
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel 6
0x60
-1
read-write
n
0x0
0x0
DSCT6_DA
PDMA_DSCT6_DA
Destination Address Register of PDMA Channel 6
0x68
-1
read-write
n
0x0
0x0
DSCT6_NEXT
PDMA_DSCT6_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 6
0x6C
-1
read-write
n
0x0
0x0
DSCT6_SA
PDMA_DSCT6_SA
Source Address Register of PDMA Channel 6
0x64
-1
read-write
n
0x0
0x0
DSCT7_CTL
PDMA_DSCT7_CTL
Descriptor Table Control Register of PDMA Channel 7
0x70
-1
read-write
n
0x0
0x0
DSCT7_DA
PDMA_DSCT7_DA
Destination Address Register of PDMA Channel 7
0x78
-1
read-write
n
0x0
0x0
DSCT7_NEXT
PDMA_DSCT7_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 7
0x7C
-1
read-write
n
0x0
0x0
DSCT7_SA
PDMA_DSCT7_SA
Source Address Register of PDMA Channel 7
0x74
-1
read-write
n
0x0
0x0
DSCT8_CTL
PDMA_DSCT8_CTL
Descriptor Table Control Register of PDMA Channel 8
0x80
-1
read-write
n
0x0
0x0
DSCT8_DA
PDMA_DSCT8_DA
Destination Address Register of PDMA Channel 8
0x88
-1
read-write
n
0x0
0x0
DSCT8_NEXT
PDMA_DSCT8_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 8
0x8C
-1
read-write
n
0x0
0x0
DSCT8_SA
PDMA_DSCT8_SA
Source Address Register of PDMA Channel 8
0x84
-1
read-write
n
0x0
0x0
DSCT9_CTL
PDMA_DSCT9_CTL
Descriptor Table Control Register of PDMA Channel 9
0x90
-1
read-write
n
0x0
0x0
DSCT9_DA
PDMA_DSCT9_DA
Destination Address Register of PDMA Channel 9
0x98
-1
read-write
n
0x0
0x0
DSCT9_NEXT
PDMA_DSCT9_NEXT
First Scatter-gather Descriptor Table Offset Address of PDMA Channel 9
0x9C
-1
read-write
n
0x0
0x0
DSCT9_SA
PDMA_DSCT9_SA
Source Address Register of PDMA Channel 9
0x94
-1
read-write
n
0x0
0x0
INT0EN
PDMA_INT0EN
PDMA Interrupt 0 Enable Register
0x418
-1
read-write
n
0x0
0x0
INTEN0
PDMA Channel 0 Interrupt Enable Register
This field is used for enabling PDMA channel 0 interrupt.
0
1
read-write
0
PDMA channel 0 interrupt Disabled
#0
1
PDMA channel 0 interrupt Enabled
#1
INTEN1
PDMA Channel 1 Interrupt Enable Register
This field is used for enabling PDMA channel 1 interrupt.
1
1
read-write
0
PDMA channel 1 interrupt Disabled
#0
1
PDMA channel 1 interrupt Enabled
#1
INTEN10
PDMA Channel 10 Interrupt Enable Register
This field is used for enabling PDMA channel 10 interrupt.
10
1
read-write
0
PDMA channel 10 interrupt Disabled
#0
1
PDMA channel 10 interrupt Enabled
#1
INTEN11
PDMA Channel 11 Interrupt Enable Register
This field is used for enabling PDMA channel 11 interrupt.
11
1
read-write
0
PDMA channel 11 interrupt Disabled
#0
1
PDMA channel 11 interrupt Enabled
#1
INTEN12
PDMA Channel 0 Interrupt Enable Register
This field is used for enabling PDMA channel 12 interrupt.
12
1
read-write
0
PDMA channel 12 interrupt Disabled
#0
1
PDMA channel 12 interrupt Enabled
#1
INTEN13
PDMA Channel 13 Interrupt Enable Register
This field is used for enabling PDMA channel 13 interrupt.
13
1
read-write
0
PDMA channel 13 interrupt Disabled
#0
1
PDMA channel 13 interrupt Enabled
#1
INTEN14
PDMA Channel 14 Interrupt Enable Register
This field is used for enabling PDMA channel 14 interrupt.
14
1
read-write
0
PDMA channel 14 interrupt Disabled
#0
1
PDMA channel 14 interrupt Enabled
#1
INTEN15
PDMA Channel 15 Interrupt Enable Register
This field is used for enabling PDMA channel 15 interrupt.
15
1
read-write
0
PDMA channel 15 interrupt Disabled
#0
1
PDMA channel 15 interrupt Enabled
#1
INTEN2
PDMA Channel 2 Interrupt Enable Register
This field is used for enabling PDMA channel 2 interrupt.
2
1
read-write
0
PDMA channel 2 interrupt Disabled
#0
1
PDMA channel 2 interrupt Enabled
#1
INTEN3
PDMA Channel 3 Interrupt Enable Register
This field is used for enabling PDMA channel 3 interrupt.
3
1
read-write
0
PDMA channel 3 interrupt Disabled
#0
1
PDMA channel 3 interrupt Enabled
#1
INTEN4
PDMA Channel 4 Interrupt Enable Register
This field is used for enabling PDMA channel 4 interrupt.
4
1
read-write
0
PDMA channel 4 interrupt Disabled
#0
1
PDMA channel 4 interrupt Enabled
#1
INTEN5
PDMA Channel 5 Interrupt Enable Register
This field is used for enabling PDMA channel 5 interrupt.
5
1
read-write
0
PDMA channel 5 interrupt Disabled
#0
1
PDMA channel 5 interrupt Enabled
#1
INTEN6
PDMA Channel 6 Interrupt Enable Register
This field is used for enabling PDMA channel 6 interrupt.
6
1
read-write
0
PDMA channel 6 interrupt Disabled
#0
1
PDMA channel 6 interrupt Enabled
#1
INTEN7
PDMA Channel 7 Interrupt Enable Register
This field is used for enabling PDMA channel 7 interrupt.
7
1
read-write
0
PDMA channel 7 interrupt Disabled
#0
1
PDMA channel 7 interrupt Enabled
#1
INTEN8
PDMA Channel 8 Interrupt Enable Register
This field is used for enabling PDMA channel 8 interrupt.
8
1
read-write
0
PDMA channel 8 interrupt Disabled
#0
1
PDMA channel 8 interrupt Enabled
#1
INTEN9
PDMA Channel 9 Interrupt Enable Register
This field is used for enabling PDMA channel 9 interrupt.
9
1
read-write
0
PDMA channel 9 interrupt Disabled
#0
1
PDMA channel 9 interrupt Enabled
#1
INT0STS
PDMA_INT0STS
PDMA Interrupt 0 Status Register
0x41C
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read-only)
This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-write
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
2
1
read-only
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
REQTOF0
Request Time-out Flag for Channel 0
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
Request Time-out Flag for Channel 1
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
INT1EN
PDMA_INT1EN
PDMA Interrupt 1 Enable Register
0x450
-1
read-write
n
0x0
0x0
INT1STS
PDMA_INT1STS
PDMA Interrupt 1 Status Register
0x454
-1
read-write
n
0x0
0x0
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
-1
write-only
n
0x0
0x0
FPRICLR0
PDMA Channel 0 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel 0 fixed priority setting
#1
FPRICLR1
PDMA Channel 1 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel 1 fixed priority setting
#1
FPRICLR10
PDMA Channel 10 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
10
1
write-only
0
No effect
#0
1
Clear PDMA channel 10 fixed priority setting
#1
FPRICLR11
PDMA Channel 11 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
11
1
write-only
0
No effect
#0
1
Clear PDMA channel 11 fixed priority setting
#1
FPRICLR12
PDMA Channel 12 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
12
1
write-only
0
No effect
#0
1
Clear PDMA channel 12 fixed priority setting
#1
FPRICLR13
PDMA Channel 13 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
13
1
write-only
0
No effect
#0
1
Clear PDMA channel 13 fixed priority setting
#1
FPRICLR14
PDMA Channel 14 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
14
1
write-only
0
No effect
#0
1
Clear PDMA channel 14 fixed priority setting
#1
FPRICLR15
PDMA Channel 15 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
15
1
write-only
0
No effect
#0
1
Clear PDMA channel 15 fixed priority setting
#1
FPRICLR2
PDMA Channel 2 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel 2 fixed priority setting
#1
FPRICLR3
PDMA Channel 3 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel 3 fixed priority setting
#1
FPRICLR4
PDMA Channel 4 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel 4 fixed priority setting
#1
FPRICLR5
PDMA Channel 5 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
5
1
write-only
0
No effect
#0
1
Clear PDMA channel 5 fixed priority setting
#1
FPRICLR6
PDMA Channel 6 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
6
1
write-only
0
No effect
#0
1
Clear PDMA channel 6 fixed priority setting
#1
FPRICLR7
PDMA Channel 7 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
7
1
write-only
0
No effect
#0
1
Clear PDMA channel 7 fixed priority setting
#1
FPRICLR8
PDMA Channel 8 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
8
1
write-only
0
No effect
#0
1
Clear PDMA channel 8 fixed priority setting
#1
FPRICLR9
PDMA Channel 9 Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
9
1
write-only
0
No effect
#0
1
Clear PDMA channel 9 fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
-1
read-write
n
0x0
0x0
FPRISET0
PDMA Channel 0 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.
Corresponding PDMA channel 0 is round-robin priority
#0
1
Set PDMA channel 0 to fixed priority channel.
Corresponding PDMA channel 0 is fixed priority
#1
FPRISET1
PDMA Channel 1 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.
Corresponding PDMA channel 1 is round-robin priority
#0
1
Set PDMA channel 1 to fixed priority channel.
Corresponding PDMA channel 1 is fixed priority
#1
FPRISET10
PDMA Channel 10 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
10
1
read-write
0
No effect.
Corresponding PDMA channel 10 is round-robin priority
#0
1
Set PDMA channel 10 to fixed priority channel.
Corresponding PDMA channel 10 is fixed priority
#1
FPRISET11
PDMA Channel 10 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
11
1
read-write
0
No effect.
Corresponding PDMA channel 11 is round-robin priority
#0
1
Set PDMA channel 11 to fixed priority channel.
Corresponding PDMA channel 11 is fixed priority
#1
FPRISET12
PDMA Channel 12 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
12
1
read-write
0
No effect.
Corresponding PDMA channel 12 is round-robin priority
#0
1
Set PDMA channel 12 to fixed priority channel.
Corresponding PDMA channel 12 is fixed priority
#1
FPRISET13
PDMA Channel 13 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
13
1
read-write
0
No effect.
Corresponding PDMA channel 13 is round-robin priority
#0
1
Set PDMA channel 13 to fixed priority channel.
Corresponding PDMA channel 13 is fixed priority
#1
FPRISET14
PDMA Channel 14 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
14
1
read-write
0
No effect.
Corresponding PDMA channel 14 is round-robin priority
#0
1
Set PDMA channel 14 to fixed priority channel.
Corresponding PDMA channel 14 is fixed priority
#1
FPRISET15
PDMA Channel 15 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
15
1
read-write
0
No effect.
Corresponding PDMA channel 15 is round-robin priority
#0
1
Set PDMA channel 15 to fixed priority channel.
Corresponding PDMA channel 15 is fixed priority
#1
FPRISET2
PDMA Channel 2 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.
Corresponding PDMA channel 2 is round-robin priority
#0
1
Set PDMA channel 2 to fixed priority channel.
Corresponding PDMA channel 2 is fixed priority
#1
FPRISET3
PDMA Channel 3 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.
Corresponding PDMA channel 3 is round-robin priority
#0
1
Set PDMA channel 3 to fixed priority channel.
Corresponding PDMA channel 3 is fixed priority
#1
FPRISET4
PDMA Channel 4 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.
Corresponding PDMA channel 4 is round-robin priority
#0
1
Set PDMA channel 4 to fixed priority channel.
Corresponding PDMA channel 4 is fixed priority
#1
FPRISET5
PDMA Channel 5 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
5
1
read-write
0
No effect.
Corresponding PDMA channel 5 is round-robin priority
#0
1
Set PDMA channel 5 to fixed priority channel.
Corresponding PDMA channel 5 is fixed priority
#1
FPRISET6
PDMA Channel 6 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
6
1
read-write
0
No effect.
Corresponding PDMA channel 6 is round-robin priority
#0
1
Set PDMA channel 6 to fixed priority channel.
Corresponding PDMA channel 6 is fixed priority
#1
FPRISET7
PDMA Channel 7 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
7
1
read-write
0
No effect.
Corresponding PDMA channel 7 is round-robin priority
#0
1
Set PDMA channel 7 to fixed priority channel.
Corresponding PDMA channel 7 is fixed priority
#1
FPRISET8
PDMA Channel 8 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
8
1
read-write
0
No effect.
Corresponding PDMA channel 8 is round-robin priority
#0
1
Set PDMA channel 8 to fixed priority channel.
Corresponding PDMA channel 8 is fixed priority
#1
FPRISET9
PDMA Channel 9 Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
9
1
read-write
0
No effect.
Corresponding PDMA channel 9 is round-robin priority
#0
1
Set PDMA channel 9 to fixed priority channel.
Corresponding PDMA channel 9 is fixed priority
#1
RCNT0
PDMA_RCNT0
Repeat Count Register of PDMA Channel 0
0x604
-1
read-write
n
0x0
0x0
RCNT
PDMA Repeat Count
The 16-bit register defines the repeat times of block transfer.
0
16
read-write
RCNT1
PDMA_RCNT1
Repeat Count Register of PDMA Channel 1
0x60C
-1
read-write
n
0x0
0x0
REQSEL0_3
PDMA_REQSEL0_3
PDMA Request Source Select Register 0
0x480
-1
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A peripheral can't assign to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
0
6
read-write
0
Disable PDMA peripheral request
0
20
Channel connects to SPI0_TX
20
21
Channel connects to SPI0_RX
21
24
Channel connects to SPI2_TX
24
25
Channel connects to SPI2_RX
25
27
Channel connects to DMIC_RX
27
28
Channel connects to DPWM_TX
28
30
Channel connects to I2S1_TX
30
31
Channel connects to I2S1_RX
31
32
Channel connects to PWM0_P1_RX
32
33
Channel connects to PWM0_P2_RX
33
34
Channel connects to PWM0_P3_RX
34
4
Channel connects to UART0_TX
4
44
Channel connects to I2S0_TX
44
45
Channel connects to I2S0_RX
45
46
Channel connects to TMR0
46
47
Channel connects to TMR1
47
48
Channel connects to TMR2
48
49
Channel connects to TMR3
49
5
Channel connects to UART0_RX
5
6
Channel connects to UART1_TX
6
7
Channel connects to UART1_RX
7
REQSRC1
Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC2
Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC3
Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL12_15
PDMA_REQSEL12_15
PDMA Request Source Select Register 3
0x48C
-1
read-write
n
0x0
0x0
REQSRC12
Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC13
Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC14
Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC15
Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL4_7
PDMA_REQSEL4_7
PDMA Request Source Select Register 1
0x484
-1
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC5
Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC6
Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC7
Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL8_11
PDMA_REQSEL8_11
PDMA Request Source Select Register 2
0x488
-1
read-write
n
0x0
0x0
REQSRC10
Channel 10 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC11
Channel 11 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 11. User can configure 1the peripheral setting by REQSRC11.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSRC8
Channel 8 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8.
Note: The channel configuration is the same as REQSRC.0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC9
Channel 9 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
STCR0
PDMA_STCR0
Stride Transfer Count Register of PDMA Channel 0
0x500
-1
read-write
n
0x0
0x0
STC
PDMA Stride Transfer Count
0
16
read-write
STCR1
PDMA_STCR1
Stride Transfer Count Register of PDMA Channel 1
0x508
-1
read-write
n
0x0
0x0
STCR2
PDMA_STCR2
Stride Transfer Count Register of PDMA Channel 2
0x510
-1
read-write
n
0x0
0x0
STCR3
PDMA_STCR3
Stride Transfer Count Register of PDMA Channel 3
0x518
-1
read-write
n
0x0
0x0
STCR4
PDMA_STCR4
Stride Transfer Count Register of PDMA Channel 4
0x520
-1
read-write
n
0x0
0x0
STCR5
PDMA_STCR5
Stride Transfer Count Register of PDMA Channel 5
0x528
-1
read-write
n
0x0
0x0
STOP
PDMA_STOP
PDMA Transfer Stop Control Register
0x404
-1
write-only
n
0x0
0x0
STOP0
PDMA Channel 0 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 0 transfer. When user sets STOP0 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN0 (PDMA_CHCTL [0]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
0
1
write-only
0
No effect
#0
1
Stop PDMA channel 0 transfer
#1
STOP1
PDMA Channel 1 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 1 transfer. When user sets STOP1 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN1 (PDMA_CHCTL [1]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
1
1
write-only
0
No effect
#0
1
Stop PDMA channel 1 transfer
#1
STOP10
PDMA Channel 10 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 10 transfer. When user sets STOP10 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN10 (PDMA_CHCTL [10]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
10
1
write-only
0
No effect
#0
1
Stop PDMA channel 10 transfer
#1
STOP11
PDMA Channel 11 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 11 transfer. When user sets STOP11 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN11 (PDMA_CHCTL [11]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
11
1
write-only
0
No effect
#0
1
Stop PDMA channel 11 transfer
#1
STOP12
PDMA Channel 12 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 12 transfer. When user sets STOP12 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN12 (PDMA_CHCTL [12]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
12
1
write-only
0
No effect
#0
1
Stop PDMA channel 12 transfer
#1
STOP13
PDMA Channel 13 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 13 transfer. When user sets STOP13 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN13 (PDMA_CHCTL [13]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
13
1
write-only
0
No effect
#0
1
Stop PDMA channel 13 transfer
#1
STOP14
PDMA Channel 14 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 14 transfer. When user sets STOP14 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN14 (PDMA_CHCTL [14]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
14
1
write-only
0
No effect
#0
1
Stop PDMA channel 14 transfer
#1
STOP15
PDMA Channel 15 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 15 transfer. When user sets STOP15 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN15 (PDMA_CHCTL [15]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
15
1
write-only
0
No effect
#0
1
Stop PDMA channel 15 transfer
#1
STOP2
PDMA Channel 2 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 2 transfer. When user sets STOP2 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN2 (PDMA_CHCTL [2]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
2
1
write-only
0
No effect
#0
1
Stop PDMA channel 2 transfer
#1
STOP3
PDMA Channel 3 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 3 transfer. When user sets STOP3 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN3 (PDMA_CHCTL [3]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
3
1
write-only
0
No effect
#0
1
Stop PDMA channel 3 transfer
#1
STOP4
PDMA Channel 4 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 4 transfer. When user sets STOP4 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN4 (PDMA_CHCTL [4]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
4
1
write-only
0
No effect
#0
1
Stop PDMA channel 4 transfer
#1
STOP5
PDMA Channel 5 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 5 transfer. When user sets STOP5 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN5 (PDMA_CHCTL [5]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
5
1
write-only
0
No effect
#0
1
Stop PDMA channel 5 transfer
#1
STOP6
PDMA Channel 6 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 6 transfer. When user sets STOP6 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN6 (PDMA_CHCTL [6]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
6
1
write-only
0
No effect
#0
1
Stop PDMA channel 6 transfer
#1
STOP7
PDMA Channel 7 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 7 transfer. When user sets STOP7 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN7 (PDMA_CHCTL [7]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
7
1
write-only
0
No effect
#0
1
Stop PDMA channel 7 transfer
#1
STOP8
PDMA Channel 8 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 8 transfer. When user sets STOP8 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN8 (PDMA_CHCTL [8]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
8
1
write-only
0
No effect
#0
1
Stop PDMA channel 8 transfer
#1
STOP9
PDMA Channel 9 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 9 transfer. When user sets STOP9 bit, the PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN9 (PDMA_CHCTL [9]) and clear request active flag. If re-enable the stopped channel again, the remaining transfers will be processed.
9
1
write-only
0
No effect
#0
1
Stop PDMA channel 9 transfer
#1
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
-1
write-only
n
0x0
0x0
SWREQ0
PDMA Channel 0 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 0.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
PDMA Channel 0 no effect
#0
1
PDMA Channel 0 generate a software request
#1
SWREQ1
PDMA Channel 1 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 1.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
PDMA Channel 1 no effect
#0
1
PDMA Channel 1 generate a software request
#1
SWREQ10
PDMA Channel 10 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 10.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
10
1
write-only
0
PDMA Channel 10 no effect
#0
1
PDMA Channel 10 generate a software request
#1
SWREQ11
PDMA Channel 11 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 11.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
11
1
write-only
0
PDMA Channel 11 no effect
#0
1
PDMA Channel 11 generate a software request
#1
SWREQ12
PDMA Channel 12 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 12.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
12
1
write-only
0
PDMA Channel 12 no effect
#0
1
PDMA Channel 12 generate a software request
#1
SWREQ13
PDMA Channel 13 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 13.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
13
1
write-only
0
PDMA Channel 13 no effect
#0
1
PDMA Channel 13 generate a software request
#1
SWREQ14
PDMA Channel 14 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 14.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
14
1
write-only
0
PDMA Channel 14 no effect
#0
1
PDMA Channel 14 generate a software request
#1
SWREQ15
PDMA Channel 15 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 15.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
15
1
write-only
0
PDMA Channel 15 no effect
#0
1
PDMA Channel 15 generate a software request
#1
SWREQ2
PDMA Channel 2 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 2.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
PDMA Channel 2 no effect
#0
1
PDMA Channel 2 generate a software request
#1
SWREQ3
PDMA Channel 3 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 3.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
PDMA Channel 3 no effect
#0
1
PDMA Channel 3 generate a software request
#1
SWREQ4
PDMA Channel 4 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 4.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
PDMA Channel 4 no effect
#0
1
PDMA Channel 4 generate a software request
#1
SWREQ5
PDMA Channel 5 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 5.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
5
1
write-only
0
PDMA Channel 5 no effect
#0
1
PDMA Channel 5 generate a software request
#1
SWREQ6
PDMA Channel 6 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 6.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
6
1
write-only
0
PDMA Channel 6 no effect
#0
1
PDMA Channel 6 generate a software request
#1
SWREQ7
PDMA Channel 7 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 7.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
7
1
write-only
0
PDMA Channel 7 no effect
#0
1
PDMA Channel 7 generate a software request
#1
SWREQ8
PDMA Channel 8 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 8.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
8
1
write-only
0
PDMA Channel 8 no effect
#0
1
PDMA Channel 8 generate a software request
#1
SWREQ9
PDMA Channel 9 Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA Channel 9.
Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
9
1
write-only
0
PDMA Channel 9 no effect
#0
1
PDMA Channel 9 generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
-1
read-only
n
0x0
0x0
TXACTF0
PDMA Channel 0 Transfer on Active Flag Register (Read Only)
0
1
read-only
0
PDMA channel 0 is not finished
#0
1
PDMA channel 0 is in active
#1
TXACTF1
PDMA Channel 1 Transfer on Active Flag Register (Read Only)
1
1
read-only
0
PDMA channel 1 is not finished
#0
1
PDMA channel 1 is in active
#1
TXACTF10
PDMA Channel 10 Transfer on Active Flag Register (Read Only)
10
1
read-only
0
PDMA channel 10 is not finished
#0
1
PDMA channel 10 is in active
#1
TXACTF11
PDMA Channel 11 Transfer on Active Flag Register (Read Only)
11
1
read-only
0
PDMA channel 11 is not finished
#0
1
PDMA channel 11 is in active
#1
TXACTF12
PDMA Channel 12 Transfer on Active Flag Register (Read Only)
12
1
read-only
0
PDMA channel 12 is not finished
#0
1
PDMA channel 12 is in active
#1
TXACTF13
PDMA Channel 13 Transfer on Active Flag Register (Read Only)
13
1
read-only
0
PDMA channel 13 is not finished
#0
1
PDMA channel 13 is in active
#1
TXACTF14
PDMA Channel 14 Transfer on Active Flag Register (Read Only)
14
1
read-only
0
PDMA channel 14 is not finished
#0
1
PDMA channel 14 is in active
#1
TXACTF15
PDMA Channel 15 Transfer on Active Flag Register (Read Only)
15
1
read-only
0
PDMA channel 15 is not finished
#0
1
PDMA channel 15 is in active
#1
TXACTF2
PDMA Channel 2 Transfer on Active Flag Register (Read Only)
2
1
read-only
0
PDMA channel 2 is not finished
#0
1
PDMA channel 2 is in active
#1
TXACTF3
PDMA Channel 3 Transfer on Active Flag Register (Read Only)
3
1
read-only
0
PDMA channel 3 is not finished
#0
1
PDMA channel 3 is in active
#1
TXACTF4
PDMA Channel 4 Transfer on Active Flag Register (Read Only)
4
1
read-only
0
PDMA channel 4 is not finished
#0
1
PDMA channel 4 is in active
#1
TXACTF5
PDMA Channel 5 Transfer on Active Flag Register (Read Only)
5
1
read-only
0
PDMA channel 5 is not finished
#0
1
PDMA channel 5 is in active
#1
TXACTF6
PDMA Channel 6 Transfer on Active Flag Register (Read Only)
6
1
read-only
0
PDMA channel 6 is not finished
#0
1
PDMA channel 6 is in active
#1
TXACTF7
PDMA Channel 7 Transfer on Active Flag Register (Read Only)
7
1
read-only
0
PDMA channel 7 is not finished
#0
1
PDMA channel 7 is in active
#1
TXACTF8
PDMA Channel 8 Transfer on Active Flag Register (Read Only)
8
1
read-only
0
PDMA channel 8 is not finished
#0
1
PDMA channel 8 is in active
#1
TXACTF9
PDMA Channel 9 Transfer on Active Flag Register (Read Only)
9
1
read-only
0
PDMA channel 9 is not finished
#0
1
PDMA channel 9 is in active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
-1
read-write
n
0x0
0x0
TDIF0
PDMA Channel 0 Transfer Done Flag Register
This bit indicates PDMA channel 0 transfer has been finished or not, user can write 1 to clear this bits.
0
1
read-write
0
PDMA channel 0 transfer has not finished
#0
1
PDMA channel 0 has finished transmission
#1
TDIF1
PDMA Channel 1 Transfer Done Flag Register
This bit indicates PDMA channel 1 transfer has been finished or not, user can write 1 to clear this bits.
1
1
read-write
0
PDMA channel 1 transfer has not finished
#0
1
PDMA channel 1 has finished transmission
#1
TDIF10
PDMA Channel 10 Transfer Done Flag Register
This bit indicates PDMA channel 10 transfer has been finished or not, user can write 1 to clear this bits.
10
1
read-write
0
PDMA channel 10 transfer has not finished
#0
1
PDMA channel 10 has finished transmission
#1
TDIF11
PDMA Channel 11 Transfer Done Flag Register
This bit indicates PDMA channel 11 transfer has been finished or not, user can write 1 to clear this bits.
11
1
read-write
0
PDMA channel 11 transfer has not finished
#0
1
PDMA channel 11 has finished transmission
#1
TDIF12
PDMA Channel 12 Transfer Done Flag Register
This bit indicates PDMA channel 12 transfer has been finished or not, user can write 1 to clear this bits.
12
1
read-write
0
PDMA channel 12 transfer has not finished
#0
1
PDMA channel 12 has finished transmission
#1
TDIF13
PDMA Channel 13 Transfer Done Flag Register
This bit indicates PDMA channel 13 transfer has been finished or not, user can write 1 to clear this bits.
13
1
read-write
0
PDMA channel 13 transfer has not finished
#0
1
PDMA channel 13 has finished transmission
#1
TDIF14
PDMA Channel 14 Transfer Done Flag Register
This bit indicates PDMA channel 14 transfer has been finished or not, user can write 1 to clear this bits.
14
1
read-write
0
PDMA channel 14 transfer has not finished
#0
1
PDMA channel 14 has finished transmission
#1
TDIF15
PDMA Channel 15 Transfer Done Flag Register
This bit indicates PDMA channel 15 transfer has been finished or not, user can write 1 to clear this bits.
15
1
read-write
0
PDMA channel 15 transfer has not finished
#0
1
PDMA channel 15 has finished transmission
#1
TDIF2
PDMA Channel 2 Transfer Done Flag Register
This bit indicates PDMA channel 2 transfer has been finished or not, user can write 1 to clear this bits.
2
1
read-write
0
PDMA channel 2 transfer has not finished
#0
1
PDMA channel 2 has finished transmission
#1
TDIF3
PDMA Channel 3 Transfer Done Flag Register
This bit indicates PDMA channel 3 transfer has been finished or not, user can write 1 to clear this bits.
3
1
read-write
0
PDMA channel 3 transfer has not finished
#0
1
PDMA channel 3 has finished transmission
#1
TDIF4
PDMA Channel 4 Transfer Done Flag Register
This bit indicates PDMA channel 4 transfer has been finished or not, user can write 1 to clear this bits.
4
1
read-write
0
PDMA channel 4 transfer has not finished
#0
1
PDMA channel 4 has finished transmission
#1
TDIF5
PDMA Channel 5 Transfer Done Flag Register
This bit indicates PDMA channel 5 transfer has been finished or not, user can write 1 to clear this bits.
5
1
read-write
0
PDMA channel 5 transfer has not finished
#0
1
PDMA channel 5 has finished transmission
#1
TDIF6
PDMA Channel 6 Transfer Done Flag Register
This bit indicates PDMA channel 6 transfer has been finished or not, user can write 1 to clear this bits.
6
1
read-write
0
PDMA channel 6 transfer has not finished
#0
1
PDMA channel 6 has finished transmission
#1
TDIF7
PDMA Channel 7 Transfer Done Flag Register
This bit indicates PDMA channel 7 transfer has been finished or not, user can write 1 to clear this bits.
7
1
read-write
0
PDMA channel 7 transfer has not finished
#0
1
PDMA channel 7 has finished transmission
#1
TDIF8
PDMA Channel 8 Transfer Done Flag Register
This bit indicates PDMA channel 8 transfer has been finished or not, user can write 1 to clear this bits.
8
1
read-write
0
PDMA channel 8 transfer has not finished
#0
1
PDMA channel 8 has finished transmission
#1
TDIF9
PDMA Channel 9 Transfer Done Flag Register
This bit indicates PDMA channel 9 transfer has been finished or not, user can write 1 to clear this bits.
9
1
read-write
0
PDMA channel 9 transfer has not finished
#0
1
PDMA channel 9 has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Time-out Counter Ch1 and Ch0 Register
0x440
-1
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on the setting of TOUTPSC0.
0
16
read-write
TOC1
Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on the setting of TOUTPSC1.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
-1
read-write
n
0x0
0x0
TOUTEN0
PDMA Channel 0 Time-out Enable Bit
0
1
read-write
0
PDMA Channel 0 time-out function Disable
#0
1
PDMA Channel 0 time-out function Enable
#1
TOUTEN1
PDMA Channel 1 Time-out Enable Bit
1
1
read-write
0
PDMA Channel 1 time-out function Disable
#0
1
PDMA Channel 1 time-out function Enable
#1
TOUTI0EN
PDMA_TOUTI0EN
PDMA Time-out Interrupt 0 Enable Register
0x438
-1
read-write
n
0x0
0x0
TOUTIEN0
PDMA Channel 0 Time-out Interrupt Enable Bit
0
1
read-write
0
PDMA Channel 0 time-out interrupt Disable
#0
1
PDMA Channel 0 time-out interrupt Enable
#1
TOUTIEN1
PDMA Channel 1 Time-out Interrupt Enable Bit
1
1
read-write
0
PDMA Channel 1 time-out interrupt Disable
#0
1
PDMA Channel 1 time-out interrupt Enable
#1
TOUTI1EN
PDMA_TOUTI1EN
PDMA Time-out Interrupt 1 Enable Register
0x458
-1
read-write
n
0x0
0x0
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
-1
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
-1
read-only
n
0x0
0x0
REQSTS0
PDMA Channel 0 Request Status (Read Only)
This flag indicates whether channel 0 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
0
1
read-only
0
PDMA Channel 0 has no request
#0
1
PDMA Channel 0 has a request
#1
REQSTS1
PDMA Channel 1 Request Status (Read Only)
This flag indicates whether channel 1 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
1
1
read-only
0
PDMA Channel 1 has no request
#0
1
PDMA Channel 1 has a request
#1
REQSTS10
PDMA Channel 10 Request Status (Read Only)
This flag indicates whether channel 10 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
10
1
read-only
0
PDMA Channel 10 has no request
#0
1
PDMA Channel 10 has a request
#1
REQSTS11
PDMA Channel 11 Request Status (Read Only)
This flag indicates whether channel 11 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
11
1
read-only
0
PDMA Channel 11 has no request
#0
1
PDMA Channel 11 has a request
#1
REQSTS12
PDMA Channel 12 Request Status (Read Only)
This flag indicates whether channel 12 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
12
1
read-only
0
PDMA Channel 12 has no request
#0
1
PDMA Channel 12 has a request
#1
REQSTS13
PDMA Channel 13 Request Status (Read Only)
This flag indicates whether channel 13 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
13
1
read-only
0
PDMA Channel 13 has no request
#0
1
PDMA Channel 13 has a request
#1
REQSTS14
PDMA Channel 14 Request Status (Read Only)
This flag indicates whether channel 14 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
14
1
read-only
0
PDMA Channel 14 has no request
#0
1
PDMA Channel 14 has a request
#1
REQSTS15
PDMA Channel 15 Request Status (Read Only)
This flag indicates whether channel 15 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
15
1
read-only
0
PDMA Channel 15 has no request
#0
1
PDMA Channel 15 has a request
#1
REQSTS2
PDMA Channel 2 Request Status (Read Only)
This flag indicates whether channel 2 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
2
1
read-only
0
PDMA Channel 2 has no request
#0
1
PDMA Channel 2 has a request
#1
REQSTS3
PDMA Channel 3 Request Status (Read Only)
This flag indicates whether channel 3 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
3
1
read-only
0
PDMA Channel 3 has no request
#0
1
PDMA Channel 3 has a request
#1
REQSTS4
PDMA Channel 4 Request Status (Read Only)
This flag indicates whether channel 4 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
4
1
read-only
0
PDMA Channel 4 has no request
#0
1
PDMA Channel 4 has a request
#1
REQSTS5
PDMA Channel 5 Request Status (Read Only)
This flag indicates whether channel 5 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
5
1
read-only
0
PDMA Channel 5 has no request
#0
1
PDMA Channel 5 has a request
#1
REQSTS6
PDMA Channel 6 Request Status (Read Only)
This flag indicates whether channel 6 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
6
1
read-only
0
PDMA Channel 6 has no request
#0
1
PDMA Channel 6 has a request
#1
REQSTS7
PDMA Channel 7 Request Status (Read Only)
This flag indicates whether channel 7 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
7
1
read-only
0
PDMA Channel 7 has no request
#0
1
PDMA Channel 7 has a request
#1
REQSTS8
PDMA Channel 8 Request Status (Read Only)
This flag indicates whether channel 8 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
8
1
read-only
0
PDMA Channel 8 has no request
#0
1
PDMA Channel 8 has a request
#1
REQSTS9
PDMA Channel 9 Request Status (Read Only)
This flag indicates whether channel 9 have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note1: If user stops or resets each PDMA transfer by setting PDMA_STOP or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
9
1
read-only
0
PDMA Channel 9 has no request
#0
1
PDMA Channel 9 has a request
#1
PWM0
PWM Register Map
PWM
0x0
0x0
0x2C
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x200
0x4C
registers
n
0x250
0x8
registers
n
0x30
0x18
registers
n
0x304
0x3C
registers
n
0x50
0x18
registers
n
0x70
0xC
registers
n
0x80
0xC
registers
n
0x90
0x18
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
PWM Channel 0 Capture Function Enable Bits
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
PWM Channel 1 Capture Function Enable Bits
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
PWM Channel 2 Capture Function Enable Bits
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
PWM Channel 3 Capture Function Enable Bits
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
PWM Channel 4 Capture Function Enable Bits
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
PWM Channel 5 Capture Function Enable Bits
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
PWM Channel 0 Capture Inverter Enable Bits
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
PWM Channel 1 Capture Inverter Enable Bits
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
PWM Channel 2 Capture Inverter Enable Bits
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
PWM Channel 3 Capture Inverter Enable Bits
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
PWM Channel 4 Capture Inverter Enable Bits
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
PWM Channel 5 Capture Inverter Enable Bits
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
PWM Channel 0 Falling Capture Reload Enable Bits
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
PWM Channel 1 Falling Capture Reload Enable Bits
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
PWM Channel 2 Falling Capture Reload Enable Bits
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
PWM Channel 3 Falling Capture Reload Enable Bits
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
PWM Channel 4 Falling Capture Reload Enable Bits
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
PWM Channel 5 Falling Capture Reload Enable Bits
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
PWM Channel 0 Rising Capture Reload Enable Bits
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
PWM Channel 1 Rising Capture Reload Enable Bits
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
PWM Channel 2 Rising Capture Reload Enable Bits
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
PWM Channel 3 Rising Capture Reload Enable Bits
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
PWM Channel 4 Rising Capture Reload Enable Bits
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
PWM Channel 5 Rising Capture Reload Enable Bits
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
PWM_CAPIEN
PWM_CAPIEN
PWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIEN0
PWM Channel 0 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
8
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN1
PWM Channel 1 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
9
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN2
PWM Channel 2 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
10
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN3
PWM Channel 3 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
11
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN4
PWM Channel 4 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
12
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN5
PWM Channel 5 Capture Falling Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
13
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPRIEN0
PWM Channel 0 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
0
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN1
PWM Channel 1 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
1
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN2
PWM Channel 2 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
2
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN3
PWM Channel 3 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
3
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN4
PWM Channel 4 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
4
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN5
PWM Channel 5 Capture Rising Latch Interrupt Enable Bits
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
5
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
PWM_CAPIF
PWM_CAPIF
PWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CFLIF0
PWM Channel 0 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF1
PWM Channel 1 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF2
PWM Channel 2 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
PWM Channel 3 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF4
PWM Channel 4 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF5
PWM Channel 5 Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIF0
PWM Channel 0 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF1
PWM Channel 1 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF2
PWM Channel 2 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
PWM Channel 3 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF4
PWM Channel 4 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF5
PWM Channel 5 Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear.
Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
PWM Channel 0 Capture Input Enable Bits
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
PWM Channel 1 Capture Input Enable Bits
1
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
PWM Channel 2 Capture Input Enable Bits
2
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
PWM Channel 3 Capture Input Enable Bits
3
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
PWM Channel 4 Capture Input Enable Bits
4
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
PWM Channel 5 Capture Input Enable Bits
5
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFLIFOV0
PWM Channel 0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
8
1
read-only
CFLIFOV1
PWM Channel 1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
9
1
read-only
CFLIFOV2
PWM Channel 2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
10
1
read-only
CFLIFOV3
PWM Channel 3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
11
1
read-only
CFLIFOV4
PWM Channel 4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
12
1
read-only
CFLIFOV5
PWM Channel 5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
13
1
read-only
CRLIFOV0
PWM Channel 0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
0
1
read-only
CRLIFOV1
PWM Channel 1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
1
1
read-only
CRLIFOV2
PWM Channel 2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
2
1
read-only
CRLIFOV3
PWM Channel 3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
3
1
read-only
CRLIFOV4
PWM Channel 4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
4
1
read-only
CRLIFOV5
PWM Channel 5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
5
1
read-only
PWM_CLKPSC0_1
PWM_CLKPSC0_1
PWM Clock Pre-scale Register 0/1
0x14
-1
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Pre-scale
The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
0
12
read-write
PWM_CLKPSC2_3
PWM_CLKPSC2_3
PWM Clock Pre-scale Register 2/3
0x18
-1
read-write
n
0x0
0x0
PWM_CLKPSC4_5
PWM_CLKPSC4_5
PWM Clock Pre-scale Register 4/5
0x1C
-1
read-write
n
0x0
0x0
PWM_CLKSRC
PWM_CLKSRC
PWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
PWM_CH01 External Clock Source Select
0
3
read-write
0
PWM0_CLK
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC2
PWM_CH23 External Clock Source Select
8
3
read-write
0
PWM0_CLK
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC4
PWM_CH45 External Clock Source Select
16
3
read-write
0
PWM0_CLK
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
PWM_CMPBUF0
PWM_CMPBUF0
PWM CMPDAT0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Register Buffer (Read Only)
Used as CMP active register.
0
16
read-only
PWM_CMPBUF1
PWM_CMPBUF1
PWM CMPDAT1 Buffer
0x320
-1
read-write
n
0x0
0x0
PWM_CMPBUF2
PWM_CMPBUF2
PWM CMPDAT2 Buffer
0x324
-1
read-write
n
0x0
0x0
PWM_CMPBUF3
PWM_CMPBUF3
PWM CMPDAT3 Buffer
0x328
-1
read-write
n
0x0
0x0
PWM_CMPBUF4
PWM_CMPBUF4
PWM CMPDAT4 Buffer
0x32C
-1
read-write
n
0x0
0x0
PWM_CMPBUF5
PWM_CMPBUF5
PWM CMPDAT5 Buffer
0x330
-1
read-write
n
0x0
0x0
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP use to compare with CNTR to generate PWM waveform.
In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Counter Register 0
0x90
-1
read-only
n
0x0
0x0
CNT
PWM Data Register (Read Only)
User can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
PWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down count
#0
1
Counter is UP count
#1
PWM_CNT1
PWM_CNT1
PWM Counter Register 1
0x94
-1
read-write
n
0x0
0x0
PWM_CNT2
PWM_CNT2
PWM Counter Register 2
0x98
-1
read-write
n
0x0
0x0
PWM_CNT3
PWM_CNT3
PWM Counter Register 3
0x9C
-1
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Counter Register 4
0xA0
-1
read-write
n
0x0
0x0
PWM_CNT5
PWM_CNT5
PWM Counter Register 5
0xA4
-1
read-write
n
0x0
0x0
PWM_CNTCLR
PWM_CNTCLR
PWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
PWM Channel 0 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR1
PWM Channel 1 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
1
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR2
PWM Channel 2 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
2
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR3
PWM Channel 3 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
3
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR4
PWM Channel 4 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
4
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR5
PWM Channel 5 Clear PWM Counter Control Bit
It is automatically cleared by hardware.
5
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
PWM Channel 0 Counter Enable Bits
0
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN1
PWM Channel 1 Counter Enable Bits
1
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN2
PWM Channel 2 Counter Enable Bits
2
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN3
PWM Channel 3 Counter Enable Bits
3
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN4
PWM Channel 4 Counter Enable Bits
4
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN5
PWM Channel 5 Counter Enable Bits
5
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
PWM_CPSCBUF0_1
PWM_CPSCBUF0_1
PWM CLKPSC0_1 Buffer
0x334
-1
read-only
n
0x0
0x0
CPSCBUF
PWM Counter Clock Pre-scale Buffer
Use as PWM counter clock pre-scare active register.
0
12
read-only
PWM_CPSCBUF2_3
PWM_CPSCBUF2_3
PWM CLKPSC2_3 Buffer
0x338
-1
read-write
n
0x0
0x0
PWM_CPSCBUF4_5
PWM_CPSCBUF4_5
PWM CLKPSC4_5 Buffer
0x33C
-1
read-write
n
0x0
0x0
PWM_CTL0
PWM_CTL0
PWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
PWM Channel 0 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
PWM Channel 1 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
PWM Channel 2 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
PWM Channel 3 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
PWM Channel 4 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
PWM Channel 5 Center Re-load
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protected)
If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
Note: This register is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt disable
#0
1
ICE debug mode counter halt enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protected)
PWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
GROUPEN
Group Function Enable Bit(S)
24
1
read-write
0
The output waveform of each PWM channel are independent
#0
1
Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1
#1
IMMLDEN0
PWM Channel 0 Immediately Load Enable Bits
Note: If IMMLDEN0 is enabled, WINLDEN0 and CTRLD0 will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
PWM Channel 1 Immediately Load Enable Bits
Note: If IMMLDEN1 is enabled, WINLDEN1 and CTRLD1 will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
PWM Channel 2 Immediately Load Enable Bits
Note: If IMMLDEN2 is enabled, WINLDEN2 and CTRLD2 will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
PWM Channel 3 Immediately Load Enable Bits
Note: If IMMLDEN3 is enabled, WINLDEN3 and CTRLD3 will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
PWM Channel 4 Immediately Load Enable Bits
Note: If IMMLDEN4 is enabled, WINLDEN4 and CTRLD4 will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
PWM Channel 5 Immediately Load Enable Bits
Note: If IMMLDEN5 is enabled, WINLDEN5 and CTRLD5 will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
WINLDEN0
PWM Channel 0 Window Load Enable Bits
8
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
WINLDEN1
PWM Channel 1 Window Load Enable Bits
9
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
WINLDEN2
PWM Channel 2 Window Load Enable Bits
10
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
WINLDEN3
PWM Channel 3 Window Load Enable Bits
11
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
WINLDEN4
PWM Channel 4 Window Load Enable Bits
12
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
WINLDEN5
PWM Channel 5 Window Load Enable Bits
13
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success
#1
PWM_CTL1
PWM_CTL1
PWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTMODE0
PWM Channel 0 Counter Mode
16
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTMODE1
PWM Channel 1 Counter Mode
17
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTMODE2
PWM Channel 2 Counter Mode
18
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTMODE3
PWM Channel 3 Counter Mode
19
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTMODE4
PWM Channel 4 Counter Mode
20
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTMODE5
PWM Channel 5 Counter Mode
21
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTTYPE0
PWM Channel 0 Counter Behavior Type
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
CNTTYPE1
PWM Channel 1 Counter Behavior Type
2
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
CNTTYPE2
PWM Channel 2 Counter Behavior Type
4
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
CNTTYPE3
PWM Channel 3 Counter Behavior Type
6
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
CNTTYPE4
PWM Channel 4 Counter Behavior Type
8
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
CNTTYPE5
PWM Channel 5 Counter Behavior Type
10
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved. Do not use
#11
OUTMODE0
PWM Channel 0 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
24
1
read-write
0
PWM independent mode
#0
1
PWM complementary mode
#1
OUTMODE2
PWM Channel 2 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
25
1
read-write
0
PWM independent mode
#0
1
PWM complementary mode
#1
OUTMODE4
PWM Channel 4 Output Mode
Note: When operating in group function, these bits must all set to the same mode.
26
1
read-write
0
PWM independent mode
#0
1
PWM complementary mode
#1
PWM_DTCTL0_1
PWM_DTCTL0_1
PWM Dead-time Control Register 0/1
0x70
-1
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
24
1
read-write
0
Dead-time clock source from PWM_CLK
#0
1
Dead-time clock source from prescaler output
#1
DTCNT
Dead-time Counter (Write Protected)
The dead-time can be calculated from the following formula:
Note: This register is write protected. Refer toSYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protected)
Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
Note: This register is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
PWM_DTCTL2_3
PWM_DTCTL2_3
PWM Dead-time Control Register 2/3
0x74
-1
read-write
n
0x0
0x0
PWM_DTCTL4_5
PWM_DTCTL4_5
PWM Dead-time Control Register 4/5
0x78
-1
read-write
n
0x0
0x0
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
PWM_INTEN0
PWM_INTEN0
PWM Interrupt Enable Register 0
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
PWM Channel 0 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
PWM Channel 1 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
PWM Channel 2 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
PWM Channel 3 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
PWM Channel 4 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
PWM Channel 5 Compare Down Count Interrupt Enable Bits
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
PWM Channel 0 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
PWM Channel 1 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
PWM Channel 2 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
PWM Channel 3 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
PWM Channel 4 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
PWM Channel 5 Compare Up Count Interrupt Enable Bits
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
PWM Channel 0 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN1
PWM Channel 1 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
9
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN2
PWM Channel 2 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
10
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN3
PWM Channel 3 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
11
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN4
PWM Channel 4 Period Point Interrupt Enable Bits
Note: When up-down counter type period point means center point.
12
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN5
PWM Channel 5 Period Point Interrupt Enable Bits
Note1: When up-down counter type period point means center point.
Note2: This channels will read always 0 at complementary mode.
13
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
PWM Channel 0 Zero Point Interrupt Enable Bits
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN1
PWM Channel 1 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
1
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN2
PWM Channel 2 Zero Point Interrupt Enable Bits
2
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN3
PWM Channel 3 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
3
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN4
PWM Channel 4 Zero Point Interrupt Enable Bits
4
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN5
PWM Channel 5 Zero Point Interrupt Enable Bits
Note: This channel will read always 0 at complementary mode.
5
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
PWM_INTSTS0
PWM_INTSTS0
PWM Interrupt Flag Register 0
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
PWM Channel 0 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT0, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
24
1
read-write
CMPDIF1
PWM Channel 1 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT1, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
25
1
read-write
CMPDIF2
PWM Channel 2 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT2, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
26
1
read-write
CMPDIF3
PWM Channel 3 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT3, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
27
1
read-write
CMPDIF4
PWM Channel 4 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT4, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
28
1
read-write
CMPDIF5
PWM Channel 4 Compare Down Count Interrupt Flag
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDAT5, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
29
1
read-write
CMPUIF0
PWM Channel 0 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT0, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
16
1
read-write
CMPUIF1
PWM Channel 1 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT1, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
17
1
read-write
CMPUIF2
PWM Channel 2 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT2, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
18
1
read-write
CMPUIF3
PWM Channel 3 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT3, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
19
1
read-write
CMPUIF4
PWM Channel 4 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT4, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
20
1
read-write
CMPUIF5
PWM Channel 5 Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDAT5, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
21
1
read-write
PIF0
PWM Channel 0 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero..
8
1
read-write
PIF1
PWM Channel 1 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD1, software can write 1 to clear this bit to zero.
9
1
read-write
PIF2
PWM Channel 2 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero.
10
1
read-write
PIF3
PWM Channel 3 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD3, software can write 1 to clear this bit to zero.
11
1
read-write
PIF4
PWM Channel 4 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero.
12
1
read-write
PIF5
PWM Channel 5 Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIOD5, software can write 1 to clear this bit to zero.
13
1
read-write
ZIF0
PWM Channel 0 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
0
1
read-write
ZIF1
PWM Channel 1 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
1
1
read-write
ZIF2
PWM Channel 2 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
2
1
read-write
ZIF3
PWM Channel 3 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
3
1
read-write
ZIF4
PWM Channel 4 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
4
1
read-write
ZIF5
PWM Channel 5 Zero Point Interrupt Flag
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
5
1
read-write
PWM_LOAD
PWM_LOAD
PWM Load Register
0x28
-1
read-write
n
0x0
0x0
LOAD0
PWM Channel 0 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
0
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
LOAD1
PWM Channel 1 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
1
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
LOAD2
PWM Channel 2 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
2
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
LOAD3
PWM Channel 3 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
3
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
LOAD4
PWM Channel 4 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
4
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
LOAD5
PWM Channel 5 Re-load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Write Operation:
5
1
read-write
0
No effect.
No load window is set
#0
1
Set load window of window loading mode.
Load window is set
#1
PWM_MSK
PWM_MSK
PWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
PWM Channel 0 Mask Data Bit
This bit control the state of output pin, if MSKEN0 (PWM_MSKEN[0]) is enabled.
0
1
read-write
0
Output logic low to PWM0
#0
1
Output logic high to PWM0
#1
MSKDAT1
PWM Channel 1 Mask Data Bit
This bit control the state of output pin, if MSKEN1 (PWM_MSKEN[1]) is enabled.
1
1
read-write
0
Output logic low to PWM1
#0
1
Output logic high to PWM1
#1
MSKDAT2
PWM Channel 2 Mask Data Bit
This bit control the state of output pin, if MSKEN2 (PWM_MSKEN[2]) is enabled.
2
1
read-write
0
Output logic low to PWM2
#0
1
Output logic high to PWM2
#1
MSKDAT3
PWM Channel 3 Mask Data Bit
This bit control the state of output pin, if MSKEN3 (PWM_MSKEN[3]) is enabled.
3
1
read-write
0
Output logic low to PWM3
#0
1
Output logic high to PWM3
#1
MSKDAT4
PWM Channel 4 Mask Data Bit
This bit control the state of output pin, if MSKEN4 (PWM_MSKEN[4]) is enabled.
4
1
read-write
0
Output logic low to PWM4
#0
1
Output logic high to PWM4
#1
MSKDAT5
PWM Channel 5 Mask Data Bit
This bit control the state of output pin, if MSKEN5 (PWM_MSKEN[5]) is enabled.
5
1
read-write
0
Output logic low to PWM5
#0
1
Output logic high to PWM5
#1
PWM_MSKEN
PWM_MSKEN
PWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
PWM Channel 0 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled.
0
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT0 (PWM_MSK[0]) data
#1
MSKEN1
PWM Channel 1 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT1 (PWM_MSK[1]) data.
1
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT1 (PWM_MSK[1]) data
#1
MSKEN2
PWM Channel 2 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT2 (PWM_MSK[2]) data.
2
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT2 (PWM_MSK[2]) data
#1
MSKEN3
PWM Channel 3 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT3 (PWM_MSK[3]) data.
3
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT3 (PWM_MSK[3]) data
#1
MSKEN4
PWM Channel 4 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT4 (PWM_MSK[4]) data.
4
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT4 (PWM_MSK[4]) data
#1
MSKEN5
PWM Channel 5 Mask Enable Bits
The PWM output signal will be masked when this bit is enabled and output MSKDAT5 (PWM_MSK[5]) data.
5
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDAT5 (PWM_MSK[5]) data
#1
PWM_PBUF0
PWM_PBUF0
PWM PERIOD0 Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
PWM Period Register Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
PWM_PBUF1
PWM_PBUF1
PWM PERIOD1 Buffer
0x308
-1
read-write
n
0x0
0x0
PWM_PBUF2
PWM_PBUF2
PWM PERIOD2 Buffer
0x30C
-1
read-write
n
0x0
0x0
PWM_PBUF3
PWM_PBUF3
PWM PERIOD3 Buffer
0x310
-1
read-write
n
0x0
0x0
PWM_PBUF4
PWM_PBUF4
PWM PERIOD4 Buffer
0x314
-1
read-write
n
0x0
0x0
PWM_PBUF5
PWM_PBUF5
PWM PERIOD5 Buffer
0x318
-1
read-write
n
0x0
0x0
PWM_PDMACAP0_1
PWM_PDMACAP0_1
PWM Capture Channel 01 PDMA Register
0x240
-1
read-only
n
0x0
0x0
CAPBUF
PWM Capture PDMA Register (Read Only)
This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
0
16
read-only
PWM_PDMACAP2_3
PWM_PDMACAP2_3
PWM Capture Channel 23 PDMA Register
0x244
-1
read-write
n
0x0
0x0
PWM_PDMACAP4_5
PWM_PDMACAP4_5
PWM Capture Channel 45 PDMA Register
0x248
-1
read-write
n
0x0
0x0
PWM_PDMACTL
PWM_PDMACTL
PWM PDMA Control Register
0x23C
-1
read-write
n
0x0
0x0
CAPMOD0_1
Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
1
2
read-write
0
Reserved. Do not use
#00
1
PWM_RCAPDAT0/1
#01
2
PWM_FCAPDAT0/1
#10
3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
#11
CAPMOD2_3
Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
9
2
read-write
0
Reserved. Do not use
#00
1
PWM_RCAPDAT2/3
#01
2
PWM_FCAPDAT2/3
#10
3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
#11
CAPMOD4_5
Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
17
2
read-write
0
Reserved. Do not use
#00
1
PWM_RCAPDAT4/5
#01
2
PWM_FCAPDAT4/5
#10
3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
#11
CAPORD0_1
Capture Channel 0/1 Rising/Falling Order
3
1
read-write
0
PWM_FCAPDAT0/1 is the first captured data to memory
#0
1
PWM_RCAPDAT0/1 is the first captured data to memory
#1
CAPORD2_3
Capture Channel 2/3 Rising/Falling Order
11
1
read-write
0
PWM_FCAPDAT2/3 is the first captured data to memory
#0
1
PWM_RCAPDAT2/3 is the first captured data to memory
#1
CAPORD4_5
Capture Channel 4/5 Rising/Falling Order
19
1
read-write
0
PWM_FCAPDAT4/5 is the first captured data to memory
#0
1
PWM_RCAPDAT4/5 is the first captured data to memory
#1
CHEN0_1
Channel 0/1 PDMA Enable
0
1
read-write
0
Channel 0/1 PDMA function Disabled
#0
1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
#1
CHEN2_3
Channel 2/3 PDMA Enable
8
1
read-write
0
Channel 2/3 PDMA function Disabled
#0
1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
#1
CHEN4_5
Channel 4/5 PDMA Enable
16
1
read-write
0
Channel 4/5 PDMA function Disabled
#0
1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
#1
CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer
4
1
read-write
0
Channel0
#0
1
Channel1
#1
CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer
12
1
read-write
0
Channel2
#0
1
Channel3
#1
CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer
20
1
read-write
0
Channel4
#0
1
Channel5
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x30
-1
read-write
n
0x0
0x0
PERIOD
PWM Period Register
Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
PWM_PERIOD1
PWM_PERIOD1
PWM Period Register 1
0x34
-1
read-write
n
0x0
0x0
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x38
-1
read-write
n
0x0
0x0
PWM_PERIOD3
PWM_PERIOD3
PWM Period Register 3
0x3C
-1
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x40
-1
read-write
n
0x0
0x0
PWM_PERIOD5
PWM_PERIOD5
PWM Period Register 5
0x44
-1
read-write
n
0x0
0x0
PWM_PHS0_1
PWM_PHS0_1
PWM Counter Phase Register 0/1
0x80
-1
read-write
n
0x0
0x0
PHS
PWM Synchronous Start Phase Bits
PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
0
16
read-write
PWM_PHS2_3
PWM_PHS2_3
PWM Counter Phase Register 2/3
0x84
-1
read-write
n
0x0
0x0
PWM_PHS4_5
PWM_PHS4_5
PWM Counter Phase Register 4/5
0x88
-1
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
PWM Channel 0 Pin Output Enable Bits
0
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN1
PWM Channel 1 Pin Output Enable Bits
1
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN2
PWM Channel 2 Pin Output Enable Bits
2
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN3
PWM Channel 3 Pin Output Enable Bits
3
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN4
PWM Channel 4 Pin Output Enable Bits
4
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN5
PWM Channel 5 Pin Output Enable Bits
5
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
PWM_POLCTL
PWM_POLCTL
PWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
PWM Channel 0 PIN Polar Inverse Control
The register controls polarity state of PWM output.
0
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV1
PWM Channel 1 PIN Polar Inverse Control
The register controls polarity state of PWM output.
1
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV2
PWM Channel 2 PIN Polar Inverse Control
The register controls polarity state of PWM output.
2
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV3
PWM Channel 3 PIN Polar Inverse Control
The register controls polarity state of PWM output.
3
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV4
PWM Channel 4 PIN Polar Inverse Control
The register controls polarity state of PWM output.
4
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV5
PWM Channel 5 PIN Polar Inverse Control
The register controls polarity state of PWM output.
5
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
PWM_SSCTL
PWM_SSCTL
PWM Synchronous Start Control Register
0x110
-1
read-write
n
0x0
0x0
SSEN0
PWM Channel 0 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN1
PWM Channel 1 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
1
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN2
PWM Channel 2 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
2
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN3
PWM Channel 3 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
3
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN4
PWM Channel 4 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
4
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN5
PWM Channel 5 Synchronous Start Function Enable Bits
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
5
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSRC
PWM Synchronous Start Source Select Bits
8
2
read-write
0
Synchronous start source come from PWM0
#00
PWM_SSTRG
PWM_SSTRG
PWM Synchronous Start Trigger Register
0x114
-1
write-only
n
0x0
0x0
CNTSEN
PWM Counter Synchronous Start Enable (Write Only)
PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx) start counting at the same time.
Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
0
1
write-only
PWM_STATUS
PWM_STATUS
PWM Status Register
0x120
-1
read-write
n
0x0
0x0
CNTMAXF0
PWM Channel 0 Time-base Counter Equal to 0xFFFF Latched Flag
0
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
CNTMAXF1
PWM Channel 1 Time-base Counter Equal to 0xFFFF Latched Flag
1
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
CNTMAXF2
PWM Channel 2 Time-base Counter Equal to 0xFFFF Latched Flag
2
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
CNTMAXF3
PWM Channel 3 Time-base Counter Equal to 0xFFFF Latched Flag
3
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
CNTMAXF4
PWM Channel 4 Time-base Counter Equal to 0xFFFF Latched Flag
4
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
CNTMAXF5
PWM Channel 5 Time-base Counter Equal to 0xFFFF Latched Flag
5
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value, software can write 1 to clear this bit
#1
SYNCINF0
PWM Channel 0 Input Synchronization Latched Flag
8
1
read-write
0
Indicates no SYNC_IN event has occurred
#0
1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
#1
SYNCINF2
PWM Channel 2 Input Synchronization Latched Flag
9
1
read-write
0
Indicates no SYNC_IN event has occurred
#0
1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
#1
SYNCINF4
PWM Channel 4 Input Synchronization Latched Flag
10
1
read-write
0
Indicates no SYNC_IN event has occurred
#0
1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
#1
PWM_SWSYNC
PWM_SWSYNC
PWM Software Control Synchronization Register
0xC
-1
read-write
n
0x0
0x0
SWSYNC0
PWM Channel 0 Software SYNC Function
When SINSRC0 (PWM_SYNC[9:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
0
1
read-write
SWSYNC2
PWM Channel 2 Software SYNC Function
When SINSRC2 (PWM_SYNC[11:10]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
1
1
read-write
SWSYNC4
PWM Channel 4 Software SYNC Function
When SINSRC4 (PWM_SYNC[13:12]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
2
1
read-write
PWM_SYNC
PWM_SYNC
PWM Synchronization Register
0x8
-1
read-write
n
0x0
0x0
PHSDIR0
PWM Channel 0 Phase Direction Control
24
1
read-write
0
Control PWM counter count decrement after synchronizing
#0
1
Control PWM counter count increment after synchronizing
#1
PHSDIR2
PWM Channel 2 Phase Direction Control
25
1
read-write
0
Control PWM counter count decrement after synchronizing
#0
1
Control PWM counter count increment after synchronizing
#1
PHSDIR4
PWM Channel 4 Phase Direction Control
26
1
read-write
0
Control PWM counter count decrement after synchronizing
#0
1
Control PWM counter count increment after synchronizing
#1
PHSEN0
PWM Channel 0 SYNC Phase Enable Bits
0
1
read-write
0
PWM counter disable to load PHS value
#0
1
PWM counter enable to load PHS value
#1
PHSEN2
PWM Channel 2 SYNC Phase Enable Bits
1
1
read-write
0
PWM counter disable to load PHS value
#0
1
PWM counter enable to load PHS value
#1
PHSEN4
PWM Channel 4 SYNC Phase Enable Bits
2
1
read-write
0
PWM counter disable to load PHS value
#0
1
PWM counter enable to load PHS value
#1
SFLTCNT
SYNC Edge Detector Filter Count
The register bits control the counter number of edge detector.
20
3
read-write
SFLTCSEL
SYNC Edge Detector Filter Clock Selection
17
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
SINPINV
SYNC Input Pin Inverse
23
1
read-write
0
The state of pin SYNC is passed to the negative edge detector
#0
1
The inversed state of pin SYNC is passed to the negative edge detector
#1
SINSRC0
PWM Channel 0 PWM0_SYNC_IN Source Selection
8
2
read-write
0
Synchronize source from SYNC_IN or SWSYNC
#00
1
Counter equal to 0
#01
2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#10
3
SYNC_OUT will not be generated
#11
SINSRC2
PWM Channel 2 PWM0_SYNC_IN Source Selection
10
2
read-write
0
Synchronize source from SYNC_IN or SWSYNC
#00
1
Counter equal to 0
#01
2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#10
3
SYNC_OUT will not be generated
#11
SINSRC4
PWM Channel 4 PWM0_SYNC_IN Source Selection
12
2
read-write
0
Synchronize source from SYNC_IN or SWSYNC
#00
1
Counter equal to 0
#01
2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#10
3
SYNC_OUT will not be generated
#11
SNFLTEN
PWM0_SYNC_IN Noise Filter Enable Bits
16
1
read-write
0
Noise filter of input pin PWM0_SYNC_IN is Disabled
#0
1
Noise filter of input pin PWM0_SYNC_IN is Enabled
#1
PWM_WGCTL0
PWM_WGCTL0
PWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
PWM Channel 0 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL1
PWM Channel 1 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL2
PWM Channel 2 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL3
PWM Channel 3 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL4
PWM Channel 4 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL5
PWM Channel 5 Period (Center) Point Control
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
ZPCTL0
PWM Channel 0 Zero Point Control
PWM can control output level when PWM counter count to zero.
0
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL1
PWM Channel 1 Zero Point Control
PWM can control output level when PWM counter count to zero.
2
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL2
PWM Channel 2 Zero Point Control
PWM can control output level when PWM counter count to zero.
4
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL3
PWM Channel 3 Zero Point Control
PWM can control output level when PWM counter count to zero.
6
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL4
PWM Channel 4 Zero Point Control
PWM can control output level when PWM counter count to zero.
8
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL5
PWM Channel 5 Zero Point Control
PWM can control output level when PWM counter count to zero.
10
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
PWM_WGCTL1
PWM_WGCTL1
PWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
PWM Channel 0 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
16
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL1
PWM Channel 1 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
18
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL2
PWM Channel 2 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
20
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL3
PWM Channel 3 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
22
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL4
PWM Channel 4 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
24
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL5
PWM Channel 5 Compare Down Point Control
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
26
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPUCTL0
PWM Channel 0 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
0
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL1
PWM Channel 1 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
2
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL2
PWM Channel 2 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
4
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL3
PWM Channel 3 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
6
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL4
PWM Channel 4 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
8
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL5
PWM Channel 5 Compare Up Point Control
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
10
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
RTC
RTC Register Map
RTC
0x0
0x0
0x3C
registers
n
0x100
0x4
registers
n
CAL
RTC_CAL
RTC Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
RTC Calendar Alarm Register
0x20
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CAMSK
RTC_CAMSK
RTC Calendar Alarm Mask Register
0x38
-1
read-write
n
0x0
0x0
MDAY
Mask 1-Day Calendar Digit of Alarm Setting (0~9)
0
1
read-write
MMON
Mask 1-Month Calendar Digit of Alarm Setting (0~9)
2
1
read-write
MTENDAY
Mask 10-Day Calendar Digit of Alarm Setting (0~3)
1
1
read-write
MTENMON
Mask 10-Month Calendar Digit of Alarm Setting (0~1)
3
1
read-write
MTENYEAR
Mask 10-Year Calendar Digit of Alarm Setting (0~9)
5
1
read-write
MYEAR
Mask 1-Year Calendar Digit of Alarm Setting (0~9)
4
1
read-write
CLKFMT
RTC_CLKFMT
RTC Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-hour / 12-hour Time Scale Selection
Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FREQADJ
Frequency Compensation Register
User must to get actual LXT frequency for RTC application.
Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
0
22
read-write
INIT
RTC_INIT
RTC Initiation Register
0x0
-1
read-write
n
0x0
0x0
INIT
RTC Initiation (Write Only)
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0.
1
31
write-only
INIT_ACTIVE
RTC Active Status (Read Only)
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
-1
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Bit
Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
0
1
read-write
0
RTC Alarm interrupt Disabled
#0
1
RTC Alarm interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Bit
Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
1
1
read-write
0
RTC Time Tick interrupt Disabled
#0
1
RTC Time Tick interrupt Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Status Register
0x2C
-1
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag
Note: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
TICKIF
RTC Time Tick Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
Tick condition does not occur
#0
1
Tick condition occur
#1
LEAPYEAR
RTC_LEAPYEAR
RTC Leap Year Indicator Register
0x24
-1
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication Register (Read Only)
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
LXTCTL
RTC_LXTCTL
RTC 32.768 KHz Oscillator Control Register
0x100
-1
read-write
n
0x0
0x0
GAIN
Oscillator Gain Option
User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
1
2
read-write
0
L0 mode
#00
1
L1 mode
#01
2
L2 mode
#10
3
L3 mode
#11
RWEN
RTC_RWEN
RTC Access Enable Register
0x4
-1
read-write
n
0x0
0x0
RTCBUSY
RTC Write Busy Flag
This bit indicates RTC registers are writable or not.
0: RTC registers are writable.
1: RTC registers can't write, RTC under Busy Status.
Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
24
1
read-write
RWENF
RTC Register Access Enable Flag (Read Only)
Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
16
1
read-only
0
RTC register read/write Disabled
#0
1
RTC register read/write Enabled
#1
TALM
RTC_TALM
RTC Time Alarm Register
0x1C
-1
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TAMSK
RTC_TAMSK
RTC Time Alarm Mask Register
0x34
-1
read-write
n
0x0
0x0
MHR
Mask 1-Hour Time Digit of Alarm Setting (0~9)
4
1
read-write
MMIN
Mask 1-Min Time Digit of Alarm Setting (0~9)
2
1
read-write
MSEC
Mask 1-Sec Time Digit of Alarm Setting (0~9)
0
1
read-write
MTENHR
Mask 10-Hour Time Digit of Alarm Setting (0~2)
5
1
read-write
MTENMIN
Mask 10-Min Time Digit of Alarm Setting (0~5)
3
1
read-write
MTENSEC
Mask 10-Sec Time Digit of Alarm Setting (0~5)
1
1
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
-1
read-write
n
0x0
0x0
TICK
Time Tick Register
These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
Note: This register can be read back and written after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/128 second
#111
TIME
RTC_TIME
RTC Time Loading Register
0xC
-1
read-write
n
0x0
0x0
HR
1-Hour Time Digit (0~9)
16
4
read-write
MIN
1-Min Time Digit (0~9)
8
4
read-write
SEC
1-Sec Time Digit (0~9)
0
4
read-write
TENHR
10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
RTC Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register
0
3
read-write
0
Sunday
#000
1
Monday
#001
2
Tuesday
#010
3
Wednesday
#011
4
Thursday
#100
5
Friday
#101
6
Saturday
#110
7
Reserved. Do not use
#111
SCS
SYST_SCR Register Map
SYST_SCR
0x0
0x10
0xC
registers
n
0xD04
0x4
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
System Reset Request
Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested
This bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit
Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions
This bit is write only and can only be written when the core is halted.
Note: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
Register Access Key
When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
ICSR
ICSR
Interrupt Control and State Register
0xD04
-1
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-pending Bit
Write Operation:
Note: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.
NMI exception is not pending
#0
1
Changes NMI exception state to pending.
NMI exception is pending
#1
PENDSTRTC_CAL
SysTick Exception Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit
Write Operation:
26
1
read-write
0
No effect.
SysTick exception is not pending
#0
1
Changes SysTick exception state to pending.
SysTick exception is pending
#1
PENDSVRTC_CAL
PendSV Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit
Write Operation:
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.
PendSV exception is not pending
#0
1
Changes PendSV exception state to pending.
PendSV exception is pending
#1
VECTACTIVE
Number of the Current Active Exception
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception
Indicates the exception number of the highest priority pending enabled exception:
12
6
read-write
0
no pending exceptions
0
SCR
SCR
System Control Register
0xD10
-1
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection
Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control
This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enters sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
-1
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
'0' denotes the highest priority and '0x3' denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
-1
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
'0' denotes the highest priority and '0x3' denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
'0' denotes the highest priority and '0x3' denotes the lowest priority.
30
2
read-write
SYST_CTRL
SYST_CTRL
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register was read.
COUNTFLAG is set by a count transition from 1 to 0.
COUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_LOAD
SYST_LOAD
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYST_VAL
SYST_VAL
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
CURRENT
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
CLKDIV
SPI0_CLKDIV
SPI0 Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note: User should set DIVIDER carefully because the peripheral clock frequency must be slower than or equal to system frequency.
0
9
read-write
CTL
SPI0_CTL
SPI0 Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DUALIOEN
Dual I/O Mode Enable Bit (Only Supported in SPI0)
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPI0_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI0_RX)
#1
QUADIOEN
Quad I/O Mode Enable Bit (Only Supported in SPI0)
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPI0_CTL, SPI0_CLKDIV, SPI0_SSCTL and SPI0_FIFOCTL registers, user shall clear the SPIEN (SPI0_CTL[0]) and confirm the SPIENSTS (SPI0_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
4
4
read-write
TWOBIT
2-bit Transfer Mode Enable Bit (Only Supported in SPI0)
Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-Bit Transfer mode Disabled
#0
1
2-Bit Transfer mode Enabled
#1
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
FIFOCTL
SPI0_FIFOCTL
SPI0 FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI0_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI0_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
When TX underflow event occurs in Slave mode, TXUFIF (SPI0_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
Note2: When TX underflow event occurs, SPI0_MISO0 pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPI0_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
PDMACTL
SPI0_PDMACTL
SPI0 PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
SPI0_RX
SPI0 Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
There are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI0_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SSCTL
SPI0_SSCTL
SPI0 Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI0_SSCTL[0]) and SS1 (SPI0_SSCTL[1])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-wire Mode Enable Bit (Only Supported in SPI0)
Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins.
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-out Period (Only Supported in SPI0)
In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out Reset Control (Only Supported in SPI0)
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)
If AUTOSS bit is cleared to 0,
Note: SPI0_SS0 is defined as the slave select input in Slave mode.
0
1
read-write
0
Set the SPI0_SS0 line to inactive state.
Keep the SPI0_SS0 line at inactive state
#0
1
Set the SPI0_SS0 line to active state.
SPI0_SS0 line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of slave select line is specified in SSACTPOL (SPI0_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal.
2
1
read-write
0
The slave selection signal is active low
#0
1
The slave selection signal is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
SPI0_STATUS
SPI0 Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVTOIF
Slave Time-out Interrupt Flag (Only Supported in SPI0)
When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI0_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
Note: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPI0_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
TX
SPI0_TX
SPI0 Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPI0_CTL[12:8]).
If DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPI2
SPI Register Map
SPI
0x0
0x0
0x1C
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
CLKDIV
SPI2_CLKDIV
SPI2 Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note1: Not supported in I2S mode.
Note2: User should set DIVIDER carefully because the peripheral clock frequency must be slower than or equal to system frequency.
0
9
read-write
CTL
SPI2_CTL
SPI2 Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
Note: For SPI2, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI2.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPI2_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI2_RX)
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPI2_CTL, SPI2_CLKDIV, SPI2_SSCTL and SPI2_FIFOCTL registers, user shall clear the SPIEN (SPI2_CTL[0]) and confirm the SPIENSTS (SPI2_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
FIFOCTL
SPI2_FIFOCTL
SPI2 FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI2_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. For SPI2, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
24
4
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI2_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. For SPI2, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
28
4
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
When TX underflow event occurs in Slave mode, TXUFIF (SPI2_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
Note2: This bit should be set as 0 in I2S mode.
Note3: When TX underflow event occurs, SPI2_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPI2_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
I2SCLK
SPI2_I2SCLK
SPI2 I2S Clock Divider Control Register
0x64
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
Note: User should set BCLKDIV carefully because the peripheral clock frequency must be slower than or equal to system frequency
8
10
read-write
MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:
where
is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
7
read-write
I2SCTL
SPI2_I2SCTL
SPI2 I2S Control Register
0x60
-1
read-write
n
0x0
0x0
FLZCDEN
Force Left Channel Zero Cross Data Option Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI2_I2SSTS register is set to 1 and left channel data will force zero. This function is only available in transmit operation.
17
1
read-write
0
Keep Left channel data, when zero crossing flag on
#0
1
Force Left channel data to zero, when zero crossing flag on
#1
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
FRZCDEN
Force Right Channel Zero Cross Data Option Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI2_I2SSTS register is set to 1 and right channel data will force zero. This function is only available in transmit operation.
16
1
read-write
0
Keep Right channel data, when zero crossing flag on
#0
1
Force Right channel data to zero, when zero crossing flag on
#1
I2SEN
I2S Controller Enable Bit
Note:
1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
2. Before changing the configurations of SPI2_I2SCTL, SPI2_I2SCLK, and SPI2_FIFOCTL registers, user shall clear the I2SEN (SPI2_I2SCTL[0]) and confirm the I2SENSTS (SPI2_I2SSTS[15]) is 0.
0
1
read-write
0
Disabled I2S mode
#0
1
Enabled I2S mode
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode
I2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from I94100 series to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
data size is 8-bit
#00
1
data size is 16-bit
#01
2
data size is 24-bit
#10
3
data size is 32-bit
#11
I2SSTS
SPI2_I2SSTS
SPI2 I2S Status Register
0x68
-1
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
The SPI/I2S control logic is disabled
#0
1
The SPI/I2S control logic is enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
19
1
read-write
PDMACTL
SPI2_PDMACTL
SPI2 PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
SPI2_RX
SPI2 Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
There are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI2_STATUS[8] or SPI2_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
0
32
read-only
SSCTL
SPI2_SSCTL
SPI2 Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI2_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)
If AUTOSS bit is cleared to 0,
0
1
read-write
0
Set the SPI2_SS line to inactive state.
Keep the SPI2_SS line at inactive state
#0
1
Set the SPI2_SS line to active state.
SPI2_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of slave select line is specified in SSACTPOL (SPI2_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal.
2
1
read-write
0
The slave selection signal is active low
#0
1
The slave selection signal is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
SPI2_STATUS
SPI2 Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurs
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurs
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
The SPI controller is disabled
#0
1
The SPI controller is enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPI2_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
STATUS2
SPI2_STATUS2
SPI2 Status Register 2
0x18
-1
read-only
n
0x0
0x0
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
0
6
read-only
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
8
5
read-only
TX
SPI2_TX
SPI2 Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPI2_CTL[12:8]) in SPI mode or WDWIDTH (SPI2_I2SCTL[5:4]) in I2S mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
In I2S mode, if WDWIDTH (SPI2_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SPIM
SPIM Register Map
SPIM
0x0
0x0
0x8
registers
n
0xC
0x40
registers
n
CTL0
SPIM_CTL0
Control and Status Register 0
0x0
-1
read-write
n
0x0
0x0
B4ADDREN
4-byte Address Mode Enable Bit
Note: Used for DMA write mode, DMA read mode, and DMM mode.
5
1
read-write
0
4-byte address mode Disabled, and 3-byte address mode Enabled
#0
1
4-byte address mode Enabled
#1
BALEN
Balance the AHB Control Time Between Cipher Enable and Disable Control
When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.
Note: Only useful when cipher is disabled.
2
1
read-write
BITMODE
SPI Interface Bit Mode
Note: Only used for normal I/O mode.
20
2
read-write
0
Standard mode
0x0
1
Dual mode
0x1
2
Quad mode
0x2
3
Reserved.
0x3
BURSTNUM
Transmit/Receive Burst Number
This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
Note: Only used for normal I/O Mode.
13
2
read-write
0
Only one transmit/receive transaction will be executed in one transfer
0x0
1
Two successive transmit/receive transactions will be executed in one transfer
0x1
2
Three successive transmit/receive transactions will be executed in one transfer
0x2
3
Four successive transmit/receive transactions will be executed in one transfer
0x3
CIPHOFF
Cipher Disable Bit
0
1
read-write
0
Cipher function Enabled
#0
1
Cipher function Disabled
#1
CMDCODE
Page Program Command Code (Note4)
The Others command codes are Reserved.
The DTR/DDR read commands '0x0D,0xBD,0xED' improves throughput by transferring address and data on both the falling and rising edge of SPI Flash clock (SPIM_CLK). It is similar to those commands '0x0B, 0xBB, 0xEB' but allows transfer of address and data on rising edge and falling edge of SPI Flash output clock. (Note2)
Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands.
Note2: See SPI Flash specifications for support items.
Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 6.173, Figure 6.174, and Figure 6.175.
Note4: Please disable 'continuous read mode' and 'burst wrap mode' before DMA write mode of SPI Flash controller is used to program data of external SPI Flash. After using DMA write mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
24
8
read-write
2
Page program (Used for DMA Write mode)
0x02
3
Standard Read (Used for DMA Read/DMM mode)
0x03
11
Fast Read (Used for DMA Read/DMM mode)
0x0b
13
DTR/DDR Fast read (Used for DMA Read/DMM mode)
0x0d
50
Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3)
0x32
56
Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3)
0x38
59
Fast Read Dual Output (Used for DMA Read/DMM mode)
0x3b
64
Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3)
0x40
187
Fast Read Dual I/O (Used for DMA Read/DMM mode)
0xbb
189
DTR/DDR dual read (Used for DMA Read/DMM mode)
0xbd
231
Word quad read (Used for DMA Read/DMM mode)
0xe7
235
Fast quad read (Used for DMA Read/DMM mode)
0xeb
237
DTR/DDR quad read (Used for DMA Read/DMM mode)
0xed
DWIDTH
Transmit/Receive Bit Length
This specifies how many bits are transmitted/received in one transmit/receive transaction.
Note1: Only used for normal I/O mode.
Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
8
5
read-write
23
24 bits
0x17
31
32 bits
0x1f
7
8 bits
0x7
15
16 bits
0xf
IEN
Interrupt Enable Bit
6
1
read-write
0
SPIM Interrupt Disabled
#0
1
SPIM Interrupt Enabled
#1
IF
Interrupt Flag
Write Operation:
7
1
read-write
0
No effect.
The transfer has not finished yet
#0
1
Write 1 to clear.
The transfer has done
#1
OPMODE
SPI Function Operation Mode
Note1: After using Normal I/O mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
Note2: In DMA write mode, hardware will send just one page program command per operation. Users must take care of cross-page cases. After using DMA write mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
Note3: For external SPI Flash with 32 MB, access address range of external SPI Flash address is from 0x00000000 to 0x01FFFFFF when using Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash.
Note4: For external SPI Flash with 32 MB, access address range of external SPI Flash address is from 0x08000000 to 0x09FFFFFF when using Direct Memory mapping mode (DMM mode) to read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash.
22
2
read-write
0
Normal I/O mode. (Note1) (Note3)
0x0
1
DMA write mode. (Note2) (Note3)
0x1
2
DMA read mode. (Note3)
0x2
3
Direct Memory Mapping mode (DMM mode) (Default). (Note4)
0x3
QDIODIR
SPI Interface Direction Select for Quad/Dual Mode
Note: Only used for normal I/O mode.
15
1
read-write
0
Interface signals are input
#0
1
Interface signals are output
#1
SUSPITV
Suspend Interval
Note: Only used for normal I/O mode.
16
4
read-write
0
2 AHB clock cycles
0x0
1
3 AHB clock cycles
0x1
14
16 AHB clock cycles
0xe
15
17 AHB clock cycles
0xf
CTL1
SPIM_CTL1
Control Register 1
0x4
-1
read-write
n
0x0
0x0
CACHEOFF
Cache Memory Function Disable Bit
Note: When CCM mode is enabled, the cache function will be disable by hardware automatically. When CCM mode is disabled, the cache function can be enable or disable by user.
1
1
read-write
0
Cache memory function Enabled. (Default)
#0
1
Cache memory function Disabled
#1
CCMEN
CCM (Core Coupled Memory) Mode Enable Bit
Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically. When CCM mode is disabled, the cache function can be enabled or disabled by user.
Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master. In this case, the SPI Flash controller will send error response via HRESP bus signal to bus master.
Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status. When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
2
1
read-write
0
CCM mode Disabled. (Default)
#0
1
CCM mode Enabled
#1
CDINVAL
Cache Data Invalid Enable Bit
Write Operation:
Read Operation: No effect
Note: When SPI Flash memory is page erasing or whole Flash erasing, please set CDINVAL to 0x1. After using normal I/O mode or DMA write mode of SPI Flash controller to program or erase the content of external SPI Flash, please set CDINVAL to 0x1.
3
1
read-write
0
No effect
#0
1
Set all cache data to be invalid. This bit is cleared by hardware automatically
#1
DIVIDER
Clock Divider Register
The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock 'SCLK' on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:
Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK.
Note2: SCLK is serial SPI output clock.
Note3: Please check the specification of the used SPI Flash component to decide the frequency of SPI Flash clock.
Note4: For DTR/DDR read commands '0x0D, 0xBD, 0xED', the setting values of DIVIDER are only all multiples of 2. For example, 1,2,4,8,16,32,...
16
16
read-write
SPIMEN
Go and Busy Status
Write Operation:
Note: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, user should not write to any register of this peripheral.
0
1
read-write
0
No effect.
The transfer has done
#0
1
Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.
The transfer has not finished yet
#1
SS
Slave Select Active Enable Bit
Note: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer. Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 6.172.
4
1
read-write
0
SPIM_SS is in active level
#0
1
SPIM_SS is in inactive level (Default)
#1
SSACTPOL
Slave Select Active Level
It defines the active level of device/slave select signal (SPIM_SS), as shown in Table 6.172.
5
1
read-write
0
The SPIM_SS slave select signal is active low
#0
1
The SPIM_SS slave select signal is active high
#1
CTL2
SPIM_CTL2
Control Register 2
0x48
-1
read-write
n
0x0
0x0
DCNUM
Dummy Cycle Number (Only for Direct Memory Mapping Mode and DMA Read Mode)
Set number of dummy cycles
(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7:
For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI Flash specification.
(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED:
user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI Flash specification.
Note: Number of dummy cycles depends on the frequency of SPI output clock, SPI Flash vendor, and read command types. Please check the used SPI Flash specification to know the setting value of this number of dummy cycles.
24
5
read-write
DTRMPOFF
Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED (Only for Direct Memory Mapping Mode and DMA Read Mode)
Note: Please check the used SPI Flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
20
1
read-write
0
Mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED
#0
1
mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED
#1
USETEN
User Set Value Enable Bit (Only for Direct Memory Mapping Mode and DMA Read Mode with Read Commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7)
For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
16
1
read-write
0
Hardware circuit of SPI Flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI Flash operations automatically
#0
1
If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI Flash operations manually
#1
DMACNT
SPIM_DMACNT
DMA Transfer Byte Count Register
0x34
-1
read-write
n
0x0
0x0
DMACNT
DMA Transfer Byte Count Register
It indicates the transfer length for DMA process.
Note1: The unit for counting is byte.
Note2: The number must be the multiple of 4.
Note3: Please check specification of used SPI Flash to know maximum byte length of page program.
0
24
read-write
DMMCTL
SPIM_DMMCTL
Direct Memory Mapping Mode Control Register
0x44
-1
read-write
n
0x0
0x0
ACTSCLKT
SPI Flash Active SCLK Time (Only for Direct Memory Mapping Mode, DMA Write Mode, and DMA Read Mode)
The bits set time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, as shown in Figure 6.1711.
Note2: SCLK is SPI output clock
Note3: Please check the used SPI Flash specification to know the setting value of this register, and different SPI Flash vendor may use different setting values.
28
4
read-write
BWEN
16 Bytes Burst Wrap Mode Enable Bit (Only for Direct Memory Mapping Mode, Cache Enable, and Read Command Code '0xEB, and 0xE7')
In direct memory mapping mode, both of quad read commands '0xEB' and '0xE7' support burst wrap mode for cache application and performance enhance. For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI Flash controller, use cache data line with 16 bytes size). For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI Flash data quickly.
24
1
read-write
0
Burst Wrap Mode Disabled. (Default)
#0
1
Burst Wrap Mode Enabled
#1
CREN
Continuous Read Mode Enable Bit (Only for Direct Memory Mapping Mode, Read Command Codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED)
For read operations of SPI Flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the 'continuous read mode' bits (8 bits) after the input address data.
Note: When using function of continuous read mode and setting USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI Flash specifications. When using function of continuous read mode and setting USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set to value 0x20.
25
1
read-write
0
Continuous Read Mode Disabled. (Default)
#0
1
Continuous Read Mode Enabled
#1
CRMDAT
Mode Bits Data for Continuous Read Mode (or Performance Enhance Mode) (Only for Direct Memory Mapping Mode)
Set the mode bits data for continuous read mode (or performance enhance mode).
When setting this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active. (Note1)
Note1: Please check the used SPI Flash specification to know the setting value of this mode bits data, and different SPI Flash vendor may use different setting values.
Note2: CRMDAT needs to be used with CREN(SPIM_DMMCTL[25]).
8
8
read-write
DESELTIM
SPI Flash Deselect Time (Only for Direct Memory Mapping Mode)
Set the minimum time width of SPI Flash deselect time (i.e. Minimum SPIM_SS deselect time), as shown in Figure 6.1711.
(1) Cache function disable:
Note3: Please check the used SPI Flash specification to know the setting value of this register, and different SPI Flash vendor may use different setting values.
16
5
read-write
UACTSCLK
User Sets SPI Flash Active SCLK Time (Only for Direct Memory Mapping Mode, DMA Write Mode, and DMA Read Mode)
Note: When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
26
1
read-write
0
According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically. (Default)
#0
1
Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually
#1
FADDR
SPIM_FADDR
SPI Flash Address Register
0x38
-1
read-write
n
0x0
0x0
ADDR
SPI Flash Address Register
For DMA Read mode, this is the source address for DMA transfer.
For DMA Write mode, this is the destination address for DMA transfer.
Note1: This address must be word-aligned.
Note2: For external SPI Flash with 32 MB, the value of this SPI Flash address register 'ADDR' is from 0x00000000 to 0x01FFFFFF when using DMA write mode and DMA read mode to write/read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash.
0
32
read-write
KEY1
SPIM_KEY1
Cipher Key1 Register
0x3C
-1
write-only
n
0x0
0x0
KEY1
Cipher Key1 Register
This is the KEY1 data for cipher function.
Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. KEY1 0x0000_0000 and KEY20x0000_0000), cipher encryption/decryption is enabled.
0
32
write-only
KEY2
SPIM_KEY2
Cipher Key2 Register
0x40
-1
write-only
n
0x0
0x0
KEY2
Cipher Key2 Register
This is the KEY2 data for cipher function.
Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically.
Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. KEY1 0x0000_0000 and KEY20x0000_0000), cipher encryption/decryption is enabled.
0
32
write-only
RX0
SPIM_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RXDAT
Data Receive Register
The Data Receive Registers hold the received data of the last executed transfer.
Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RXDAT register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first.
In a byte, received data are held in the most significant bit of RXDAT register first.
0
32
read-only
RX1
SPIM_RX1
Data Receive Register 1
0x14
-1
read-write
n
0x0
0x0
RX2
SPIM_RX2
Data Receive Register 2
0x18
-1
read-write
n
0x0
0x0
RX3
SPIM_RX3
Data Receive Register 3
0x1C
-1
read-write
n
0x0
0x0
RXCLKDLY
SPIM_RXCLKDLY
RX Clock Delay Control Register
0xC
-1
read-write
n
0x0
0x0
DWDELSEL
SPI Flash Deselect Time Interval of DMA Write Mode (for DMA Write Mode Only)
The bits set the deselect time interval of SPI Flash (i.e. time interval of inactive level of SPIM_SS) when SPI Flash controller operates on DMA write mode. (Note1)
0
8
read-write
PHDELSEL
SPI Flash Phase Delay Time (for DMA Write Mode, DMA Read Mode)
The bits set phase delay time between command data phase, address data phase, and dummy cycle phase, where SPI Flash controller will send those phase data to external SPI Flash.
8
8
read-write
RDDLYSEL
Sampling Clock Delay Selection for Received Data (for Normal I/O Mode, DMA Rread Mode, DMA Write Mode, and Direct Memory Mapping Mode)
Determine the number of inserted delay cycles. Used to adjust the sampling clock of received data to latch the correct data.
0x0: No delay. (Default)
0x1: Delay 1 SPI Flash clock.
0x2: Delay 2 SPI Flash clocks.
0x3: Delay 3 SPI Flash clocks.
...
0x7: Delay 7 SPI Flash clocks
Note: The manufacturer or device ID of external SPI Flash component can be used to determine the correct setting value of RDDLYSEL. An example is given as follows.
For example, the manufacturer ID and device ID of external SPI Flash for some vendor are 0xEF and 0x1234 separately. First, set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI Flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).
If the manufacturer ID which reads from external SPI Flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1. According to manufacturer id reads from external SPI Flash, RDDLYSEL needs to be set to 0x1 to receive SPI Flash data correctly.
16
3
read-write
RDEDGE
Sampling Clock Edge Selection for Received Data (for Normal I/O Mode, DMA Read Mode, DMA Write Mode, and Direct Memory Mapping Mode)
20
1
read-write
0
Use SPI input clock rising edge to sample received data. (Default)
#0
1
Use SPI input clock falling edge to sample received data
#1
SRAMADDR
SPIM_SRAMADDR
SRAM Memory Address Register
0x30
-1
read-write
n
0x0
0x0
ADDR
SRAM Memory Address
For DMA Read mode, this is the destination address for DMA transfer.
For DMA Write mode, this is the source address for DMA transfer.
Note: This address must be word-aligned.
0
32
read-write
TX0
SPIM_TX0
Data Transmit Register 0
0x20
-1
read-write
n
0x0
0x0
TXDAT
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in next transfer.
Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TXDAT register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first.
In a byte, data are transmitted in the most significant bit of TXDAT register first.
0
32
read-write
TX1
SPIM_TX1
Data Transmit Register 1
0x24
-1
read-write
n
0x0
0x0
TX2
SPIM_TX2
Data Transmit Register 2
0x28
-1
read-write
n
0x0
0x0
TX3
SPIM_TX3
Data Transmit Register 3
0x2C
-1
read-write
n
0x0
0x0
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x110
0x4
registers
n
0x18
0x4
registers
n
0x2C
0x24
registers
n
0x400
0x4
registers
n
0x70
0x10
registers
n
0xA4
0x4
registers
n
0xE0
0x1C
registers
n
AHBMCTL
SYS_AHBMCTL
AHB Bus Matrix Priority Control Register
0x400
-1
read-write
n
0x0
0x0
INTACTEN
Highest AHB Bus Priority of Cortex M0 Core Enable Bit (Write Protected)
Enable Cortex-M0 Core With Highest AHB Bus Priority In AHB Bus Matrix
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Round-robin mode
#0
1
Cortex-M0 CPU with highest bus priority when interrupt occur
#1
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protected)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
Without de-glitch function
#000
1
3 system clock (HCLK)
#001
2
7 system clock (HCLK)
#010
3
15 system clock (HCLK)
#011
4
31 system clock (HCLK)
#100
5
63 system clock (HCLK)
#101
6
127 system clock (HCLK)
#110
7
255 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protected)
The default value is set by user configuration block register CBODEN (CONFIG0 [19]).
Note 1: The reset value of SYS_BODCTL[0] is determined by user configuration block.
Note 2: Brown-out detector can only work when both BODEN(SYS_BODCTL[0]) and LVREN(SYS_BODCTL[7]) are set to 1.
Note 3: LIRC must be enabled.
Note 4: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector has not detected a BOD event on VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects that VDD crosses BODLVL setting from either direction, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protected)
Note1: The low power mode can reduce the current to about 1/10 but slow the BOD response.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status
The detected voltage is lower than BODVL setting.
If the BODEN is 0, BOD function is disabled and this bit will be 0.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protected)
The default value is set by user configuration block register CBORST(CONFIG0[20]) bit .
Note 1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will latch until BODEN is set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note 2: The reset value of SYS_BODCTL[3] is determined by user configuration block.
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protected)
The default value is set by user configuration block register CBOV (CONFIG0 [23:21]).
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
16
3
read-write
0
Brown-Out Detector threshold voltage is 1.6V
#000
1
Brown-Out Detector threshold voltage is 1.8V
#001
2
Brown-Out Detector threshold voltage is 2.0V
#010
3
Brown-Out Detector threshold voltage is 2.2V
#011
4
Brown-Out Detector threshold voltage is 2.4V
#100
5
Brown-Out Detector threshold voltage is 2.6V
#101
6
Brown-Out Detector threshold voltage is 2.8V
#110
7
Brown-Out Detector threshold voltage is 3.0V
#111
LVRDGSEL
LVR Output De-glitch Time Select (Write Protected)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
12
3
read-write
0
Without de-glitch function
#000
1
3 system clock (HCLK)
#001
2
7 system clock (HCLK)
#010
3
15 system clock (HCLK)
#011
4
31 system clock (HCLK)
#100
5
63 system clock (HCLK)
#101
6
127 system clock (HCLK)
#110
7
255 system clock (HCLK)
#111
LVREN
Low Voltage Reset Enable Bit (Write Protected)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
DSPCTL
SYS_DSPCTL
DSP Control Register
0xA4
-1
read-write
n
0x0
0x0
DSPRST
DSP Reset Control (Write Protected)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
DSP Reset is asserted
#0
1
DSP Normal Run
#1
MCUHALTEN
MCU Halt Control (Write Protected)
Enable DSP halt MCU when DSP at break status MCU should also at debugging status
Note : This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
DSP halt MCU Disabled
#0
1
DSP halt MCU Enabled
#1
OCDRESET
DSP OCDHaltOnReset Control (Write Protected)
Note : This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
DSP OCDHaltOnReset is asserted
#0
1
DSP Normal Run
#1
RUNSTALL
DSP RunStall Control (Write Protected)
1
1
read-write
0
DSP Stall
#0
1
DSP Run
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
-1
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
-1
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
-1
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multiple Function Control Register
0x44
-1
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
4
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
4
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
4
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
4
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
4
read-write
PC15MFP
PC.15 Multi-function Pin Selection
28
4
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
4
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
-1
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPD_MFPH
SYS_GPD_MFPH
GPIOD High Byte Multiple Function Control Register
0x4C
-1
read-write
n
0x0
0x0
PD10MFP
PD.10 Multi-function Pin Selection
8
4
read-write
PD11MFP
PD.11 Multi-function Pin Selection
12
4
read-write
PD12MFP
PD.12 Multi-function Pin Selection
16
4
read-write
PD13MFP
PD.13 Multi-function Pin Selection
20
4
read-write
PD14MFP
PD.14 Multi-function Pin Selection
24
4
read-write
PD15MFP
PD.15 Multi-function Pin Selection
28
4
read-write
PD8MFP
PD.8 Multi-function Pin Selection
0
4
read-write
PD9MFP
PD.9 Multi-function Pin Selection
4
4
read-write
GPD_MFPL
SYS_GPD_MFPL
GPIOD Low Byte Multiple Function Control Register
0x48
-1
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
4
read-write
PD4MFP
PD.4 Multi-function Pin Selection
16
4
read-write
PD5MFP
PD.5 Multi-function Pin Selection
20
4
read-write
PD6MFP
PD.6 Multi-function Pin Selection
24
4
read-write
PD7MFP
PD.7 Multi-function Pin Selection
28
4
read-write
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protected)
Setting this bit will reset the whole chip, including Processor core and all peripherals this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers are reset and the chip settings from user configuration block are also reloaded.
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protected)
Setting this bit will only reset the processor core and OTP Memory Controller(OMC) this bit will automatically return to 0 after the 2 clock cycles.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protected)
Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
CRPTRST
CRYPTO Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
CRYPTO controller normal operation
#0
1
CRYPTO controller reset
#1
PDMARST
PDMA Controller Reset (Write Protected)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
SPIMRST
SPIM Controller Reset (Write Protected)
Setting this bit to 1 will generate a reset signal to the SPIM controller. User needs to set this bit to 0 to release from the reset sate.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
SPIM controller normal operation
#0
1
SPIM controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
-1
read-write
n
0x0
0x0
DMICRST
DMIC Controller Reset
15
1
read-write
0
DMIC controller normal operation
#0
1
DMIC controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
HIRCCKF
HIRC Clock Filter Enable Bit
31
1
read-write
0
HIRC clock filter Enabled
#0
1
HIRC clock filter Disabled
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2S0RST
I2S0 Controller Reset
29
1
read-write
0
I2S0 controller normal operation
#0
1
I2S0 controller reset
#1
I2S1RST
I2S1 Controller Reset
30
1
read-write
0
I2S1 controller normal operation
#0
1
I2S1 controller reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI2RST
SPI2 Controller Reset
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
USBDRST
USBD Controller Reset
27
1
read-write
0
USBD controller normal operation
#0
1
USBD controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
-1
read-write
n
0x0
0x0
DPWMRST
DPWM Controller Reset
6
1
read-write
0
Audio DPWM controller normal operation
#0
1
Audio DPWM controller reset
#1
PWM0RST
PWM0 Controller Reset
16
1
read-write
0
PWM0 controller normal operation
#0
1
PWM0 controller reset
#1
IRCTCTL
SYS_IRCTCTL
HIRC Trim Control Register
0xF0
-1
read-write
n
0x0
0x0
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation is keep going if clock is inaccuracy
#0
1
The trim operation is stopped if clock is inaccuracy
#1
FREQSEL
Trim Frequency Selection
This field indicates the target frequency of 48 MHz and 49.152 MHz internal high speed RC oscillator (HIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#01
3
Enable HIRC auto trim function and trim HIRC to 49.152 MHz
#11
LOOPSEL
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks.
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks of reference clock
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
HIRC trim reference clock is from LXT (32.768 kHz)
#0
1
HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet
#1
RETRYCNT
Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
IRCTIEN
SYS_IRCTIEN
HIRC Trim Interrupt Enable Register
0xF4
-1
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
2
1
read-write
0
Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
#1
TFAILIEN
Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
1
1
read-write
0
Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
#1
IRCTISTS
SYS_IRCTISTS
HIRC Trim Interrupt Status Register
0xF8
-1
read-write
n
0x0
0x0
CLKERRIF
Clock Error Interrupt Status
When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status
This bit indicates the HIRC frequency is locked.
This is a status bit and doesn't trigger any interrupt
Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
0
1
read-write
0
The internal high-speed oscillator frequency doesn't lock at 48 MHz or 49.152 MHz
#0
1
The internal high-speed oscillator frequency locked at 48 MHz or 49.152 MHz.
#1
TFAILIF
Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
P2PNTFY0
SYS_P2PNTFY0
Processor to Processor Notification 0 Register
0xE0
-1
read-write
n
0x0
0x0
P2PNTFY
Processor to Proccessor Notification Flag (Write Protect)
Each bit in this field represent a notification flag a Sending Processor can set in order to generate a P2P0_INT at the Receiving Processor.
Write operation:
Engineering note: When reading this register the value will be a mirrored value of SYS_P2PSTS0.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
32
read-write
0
No effect.
Notification flag inactive
0
1
Set the corresponding bit in SYS_P2PSTS0 register.
Notification flag active
1
P2PNTFY1
SYS_P2PNTFY1
Processor to Processor Notification 1 Register
0xE8
-1
read-write
n
0x0
0x0
P2PNTFY
Processor to Proccessor Notification Flag (Write Protect)
Each bit in this field represent a notification flag a Sending Processor can set in order to generate a P2P1_INT at the Receiving Processor.
Write operation:
Engineering note: When reading this register the value will be a mirrored value of SYS_P2PSTS1.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
32
read-write
0
No effect.
Notification flag inactive
0
1
Set the corresponding bit in SYS_P2PSTS1 register.
Notification flag active
1
P2PSTS0
SYS_P2PSTS0
Processor to Processor Notification Status 0 Register
0xE4
-1
read-write
n
0x0
0x0
P2PSTS
Processor to Proccessor Notification Status (Write Protect)
A Receiving Processor SW can read this register in order to determin which notification flag was set by the Sending Processor. Each bit in this register reflects a notification.
Writing operation
If any bit in this register is 1, P2P0_INT will be asserted.
0
32
read-write
0
No affect
Notification flag is not active
0
1
Clear notification flag
Notification flag is active
1
P2PSTS1
SYS_P2PSTS1
Processor to Processor Notification Status 1 Register
0xEC
-1
read-write
n
0x0
0x0
P2PSTS
Processor to Proccessor Notification Status (Write Protect)
A Receiving Processor SW can read this register in order to determin which notification flag was set by the Sending Processor. Each bit in this register reflects a notification.
Writing operation
If any bit in this register is 1, P2P1_INT will be asserted.
0
32
read-write
0
No affect
Notification flag is not active
0
1
Clear notification flag
Notification flag is active
1
PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)
This register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
RCADJ
SYS_RCADJ
HIRC Trim Value Register
0x110
-1
read-write
n
0x0
0x0
RCADJ
RC48M Trim Value (Write Protect)
This bit is the protected bit, which means programming it needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
This field reflects the HIRC trim value.
Software can update HIRC trim value by writing this field.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
10
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code (Write Only)
Some registers have a write-protection function. To write to these registers, this write protection must be by writing the sequence value '59h', '16h', '88h' to this address. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protected registers can be write accessed.
Register Lock Control Disable Index (Read Only)
The Protected registers are:
SYS_IPRST0: address 0x4000_0008
SYS_BODCTL: address 0x4000_0018
SYS_PORCTL: address 0x4000_0024
SYS_USBPHY: address 0x4000_002C
SYS_DSPCTL: address 0x4000_00A4
SYS_PTPNTFY0: address 0x4000_00E0
SYS_PTPNTFY1: address 0x4000_00E8
CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power-down wake-up interrupt clear)
CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
CLK_CLKDSTS: address 0x4000_0274
NMIEN: address 0x4000_0300
OMC_ISPCTL: address 0x4000_C000 (ISP Control register)
OMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
OMC_ISPSTS: address 0x4000_C040
WDT_CTL: address 0x4004_0000
AHBMCTL: address 0x4000_0400
CLK_PLLCTL: address 0x4000_0240
PWM_CTL0: address 0x4005_8000
PWM_DTCTL0_1: address 0x4005_8070
PWM_DTCTL2_3: address 0x4005_8074
PWM_DTCTL4_5: address 0x4005_8078
0
8
write-only
0
Write-protection Enabled for write protected registers. Any write to the protected registers is ignored
0
1
Write-protection Disabled for write protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag
Note: Write 1 to clear this bit to 0.
Note: when ICE is connected, CPU lockup event sets this flag to 1 but will not reset chip.
8
1
read-write
0
No reset from CPU lockup occurred
#0
1
The Cortex-M0 lockup occurred and chip is reset
#1
CPURF
CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and OTP Memory Controller (OMC).
Note: Write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 Core and OMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET issued the reset signal to reset the system
#1
PMURF
PMU Reset Flag
Note: Write 1 to clear this bit to 0.
6
1
read-write
0
No reset from POR, PINR, WDTR, LVR, BODR, SYSR and CPULKR
#0
1
When POR, PINR, WDTR, LVR, BODR, SYSR and CPULKR occurred
#1
PORF
POR Reset Flag
The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer issued the reset signal to reset the system
#1
UCID0
SYS_UCID0
Unique Customer ID 0 Register
0x70
-1
read-only
n
0x0
0x0
UCID
Unique Customer ID 0 (Read Only)
This register reflects unique customer ID 0.
0
32
read-only
UCID1
SYS_UCID1
Unique Customer ID 1 Register
0x74
-1
read-only
n
0x0
0x0
UCID
Unique Customer ID 1 (Read Only)
This register reflects unique customer ID 1.
0
32
read-only
UCID2
SYS_UCID2
Unique Customer ID 2 Register
0x78
-1
read-only
n
0x0
0x0
UCID
Unique Customer ID 2 (Read Only)
This register reflects unique customer ID 2.
0
32
read-only
UCID3
SYS_UCID3
Unique Customer ID 3 Register
0x7C
-1
read-only
n
0x0
0x0
UCID
Unique Customer ID 3 (Read Only)
This register reflects unique customer ID 3.
0
32
read-only
USBPHY
SYS_USBPHY
USB PHY Control Register
0x2C
-1
read-write
n
0x0
0x0
USBEN
USB PHY Enable (Write Protect)
This bit is used to enable/disable USB PHY function.
8
1
read-write
0
USB PHY function Disabled (default)
#0
1
USB PHY function Enabled
#1
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x28
registers
n
0x174
0x8
registers
n
0x180
0x4
registers
n
0x188
0x4
registers
n
0x194
0x4
registers
n
0x19C
0xC
registers
n
0x40
0x28
registers
n
0x74
0x8
registers
n
0x80
0x4
registers
n
0x88
0x4
registers
n
0x94
0x14
registers
n
TIMER0_ALTCTL
TIMER0_ALTCTL
Timer0 Alternative Control Register
0x20
-1
read-write
n
0x0
0x0
FUNCSEL
Function Selection
Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
0
1
read-write
0
Timer controller is used as timer function
#0
1
Timer controller is used as PWM function
#1
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register (Read Only)
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
Read operation.
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
Write operation.
Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)
This bit indicates if the counter reset operation active.
When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
Note: This bit is read only.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTEN
Timer Counting Enable Bit
Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protected)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Control
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ignored and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit
If updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter
Note: Overwriting prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer External Capture Pin Enable Bit
This bit enables the TMx_EXT capture pin input function.
3
1
read-write
0
TMx_EXT (x= 0~3) pin Disabled
#0
1
TMx_EXT (x= 0~3) pin Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Reserved Event Counter input source is from USB internal SOF output signal
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Power-down mode if timer time-out interrupt signal generated
#1
TIMER0_PWMCLKPSC
TIMER0_PWMCLKPSC
Timer0 PWM Counter Clock Pre-scale Register
0x48
-1
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Pre-scale
The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
0
12
read-write
TIMER0_PWMCLKSRC
TIMER0_PWMCLKSRC
Timer0 PWM Counter Clock Source Register
0x44
-1
read-write
n
0x0
0x0
CLKSRC
PWM Counter Clock Source Select
The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
0
3
read-write
0
TMRx_CLK
#000
1
Internal TIMER0 time-out or capture event
#001
2
Internal TIMER1 time-out or capture event
#010
3
Internal TIMER2 time-out or capture event
#011
4
Internal TIMER3 time-out or capture event
#100
TIMER0_PWMCMPBUF
TIMER0_PWMCMPBUF
Timer0 PWM Comparator Buffer Register
0xA4
-1
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Buffer Register (Read Only)
Used as CMP active register.
0
16
read-only
TIMER0_PWMCMPDAT
TIMER0_PWMCMPDAT
Timer0 PWM Comparator Register
0x54
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events.
0
16
read-write
TIMER0_PWMCNT
TIMER0_PWMCNT
Timer0 PWM Counter Register
0x5C
-1
read-only
n
0x0
0x0
CNT
PWM Counter Value Register (Read Only)
User can monitor CNT to know the current counter value in 16-bit period counter.
0
16
read-only
DIRF
PWM Counter Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is active in down count
#0
1
Counter is active up count
#1
TIMER0_PWMCNTCLR
TIMER0_PWMCNTCLR
Timer0 PWM Clear Counter Register
0x4C
-1
read-write
n
0x0
0x0
CNTCLR
Clear PWM Counter Control Bit
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type
#1
TIMER0_PWMCTL
TIMER0_PWMCTL
Timer0 PWM Control Register
0x40
-1
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit
0
1
read-write
0
PWM counter and clock prescale Stop Running
#0
1
PWM counter and clock prescale Start Running
#1
CNTMODE
PWM Counter Mode
3
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTTYPE
PWM Counter Behavior Type
1
2
read-write
0
Up count type
#00
1
Down count type
#01
2
Up-down count type
#10
3
Reserved. Do not use
#11
CTRLD
Center Re-load
In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
8
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protected)
If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
Note: This register is write protected. Refer toSYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt disable
#0
1
ICE debug mode counter halt enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protected)
PWM output pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer toSYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDEN
Immediately Load Enable Bit
Note: If IMMLDEN is enabled, CTRLD will be invalid.
9
1
read-write
0
PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period
#0
1
PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP
#1
OUTMODE
PWM Output Mode
This bit controls the output mode of corresponding PWM channel.
16
1
read-write
0
PWM independent mode
#0
1
PWM complementary mode
#1
TIMER0_PWMDTCTL
TIMER0_PWMDTCTL
Timer0 PWM Dead-time Control Register
0x58
-1
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
24
1
read-write
0
Dead-time clock source from TMRx_PWMCLK without counter clock prescale
#0
1
Dead-time clock source from TMRx_PWMCLK with counter clock prescale
#1
DTCNT
Dead-time Counter (Write Protected)
The dead-time can be calculated from the following two formulas:
Note: This register is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protected)
Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
Note: This register is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
TIMER0_PWMINTEN0
TIMER0_PWMINTEN0
Timer0 PWM Interrupt Enable Register 0
0x80
-1
read-write
n
0x0
0x0
CMPDIEN
PWM Compare Down Count Interrupt Enable Bit
3
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN
PWM Compare Up Count Interrupt Enable Bit
2
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN
PWM Period Point Interrupt Enable Bit
Note: When in up-down count type, period point means the center point of current PWM period.
1
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN
PWM Zero Point Interrupt Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
TIMER0_PWMINTSTS0
TIMER0_PWMINTSTS0
Timer0 PWM Interrupt Status Register 0
0x88
-1
read-write
n
0x0
0x0
CMPDIF
PWM Compare Down Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
Note2: This bit is cleared by writing 1 to it.
3
1
read-write
CMPUIF
PWM Compare Up Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..
Note2: This bit is cleared by writing 1 to it.
2
1
read-write
PIF
PWM Period Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
Note2: This bit is cleared by writing 1 to it.
1
1
read-write
ZIF
PWM Zero Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches zero.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
TIMER0_PWMMSK
TIMER0_PWMMSK
Timer0 PWM Output Mask Data Control Register
0x64
-1
read-write
n
0x0
0x0
MSKDAT0
PWMx_CH0 Output Mask Data Control Bit
0
1
read-write
0
Output logic Low to PWMx_CH0
#0
1
Output logic High to PWMx_CH0
#1
MSKDAT1
PWMx_CH1 Output Mask Data Control Bit
1
1
read-write
0
Output logic Low to PWMx_CH1
#0
1
Output logic High to PWMx_CH1
#1
TIMER0_PWMMSKEN
TIMER0_PWMMSKEN
Timer0 PWM Output Mask Enable Register
0x60
-1
read-write
n
0x0
0x0
MSKEN0
PWMx_CH0 Output Mask Enable Bit
The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
0
1
read-write
0
PWMx_CH0 output signal is non-masked
#0
1
PWMx_CH0 output signal is masked and output MSKDAT0 data
#1
MSKEN1
PWMx_CH1 Output Mask Enable Bit
The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
1
1
read-write
0
PWMx_CH1 output signal is non-masked
#0
1
PWMx_CH1 output signal is masked and output MSKDAT1 data
#1
TIMER0_PWMPBUF
TIMER0_PWMPBUF
Timer0 PWM Period Buffer Register
0xA0
-1
read-only
n
0x0
0x0
PBUF
PWM Period Buffer Register (Read Only)
Used as PERIOD active register.
0
16
read-only
TIMER0_PWMPERIOD
TIMER0_PWMPERIOD
Timer0 PWM Period Register
0x50
-1
read-write
n
0x0
0x0
PERIOD
PWM Period Register
In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
In up and down count type:
Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
0
16
read-write
TIMER0_PWMPOEN
TIMER0_PWMPOEN
Timer0 PWM Pin Output Enable Register
0x78
-1
read-write
n
0x0
0x0
POEN0
PWMx_CH0 Output Pin Enable Bit
0
1
read-write
0
PWMx_CH0 pin at tri-state mode
#0
1
PWMx_CH0 pin in output mode
#1
POEN1
PWMx_CH1 Output Pin Enable Bit
1
1
read-write
0
PWMx_CH1 pin at tri-state mode
#0
1
PWMx_CH1 pin in output mode
#1
TIMER0_PWMPOLCTL
TIMER0_PWMPOLCTL
Timer0 PWM Pin Output Polar Control Register
0x74
-1
read-write
n
0x0
0x0
PINV0
PWMx_CH0 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH0 output pin.
0
1
read-write
0
PWMx_CH0 output pin polar inverse Disabled
#0
1
PWMx_CH0 output pin polar inverse Enabled
#1
PINV1
PWMx_CH1 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH1 output pin.
1
1
read-write
0
PWMx_CH1 output pin polar inverse Disabled
#0
1
PWMx_CH1 output pin polar inverse Enabled
#1
TIMER0_PWMSCTL
TIMER0_PWMSCTL
Timer0 PWM Synchronous Control Register
0x94
-1
read-write
n
0x0
0x0
SYNCMODE
PWM Synchronous Mode Enable Select
0
2
read-write
0
PWM synchronous function Disabled
#00
1
PWM synchronous counter start function Enabled
#01
2
Reserved. Do not use
#10
3
PWM synchronous counter clear function Enabled
#11
SYNCSRC
PWM Synchronous Counter Start/Clear Source Select
Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
8
1
read-write
0
Counter synchronous start/clear by trigger STRGEN (TIMER0_PWMSTRG[0])
#0
1
Counter synchronous start/clear by trigger STRGEN (TIMER2_PWMSTRG[0])
#1
TIMER0_PWMSTATUS
TIMER0_PWMSTATUS
Timer0 PWM Status Register
0x9C
-1
read-write
n
0x0
0x0
CNTMAXF
PWM Counter Equal to 0xFFFF Flag
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
Indicates the PWM counter value never reached its maximum value 0xFFFF
#0
1
Indicates the PWM counter value has reached its maximum value
#1
TIMER0_PWMSTRG
TIMER0_PWMSTRG
Timer0 PWM Synchronous Trigger Register
0x98
-1
write-only
n
0x0
0x0
STRGEN
PWM Counter Synchronous Trigger Enable Bit (Write Only)
PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
Note: This bit is only available in TIMER0 and TIMER2.
0
1
write-only
TIMER0_TRGCTL
TIMER0_TRGCTL
Timer0 Trigger Control Register
0x1C
-1
read-write
n
0x0
0x0
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
1
1
read-write
0
Timer interrupt trigger PWM Disabled
#0
1
Timer interrupt trigger PWM Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger PWM, PDMA
#0
1
Capture interrupt signal is used to internal trigger PWM, PDMA
#1
TIMER1_ALTCTL
TIMER1_ALTCTL
Timer1 Alternative Control Register
0x120
-1
read-write
n
0x0
0x0
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x110
-1
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x104
-1
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x10C
-1
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x100
-1
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x118
-1
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x114
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x108
-1
read-write
n
0x0
0x0
TIMER1_PWMCLKPSC
TIMER1_PWMCLKPSC
Timer1 PWM Counter Clock Pre-scale Register
0x148
-1
read-write
n
0x0
0x0
TIMER1_PWMCLKSRC
TIMER1_PWMCLKSRC
Timer1 PWM Counter Clock Source Register
0x144
-1
read-write
n
0x0
0x0
TIMER1_PWMCMPBUF
TIMER1_PWMCMPBUF
Timer1 PWM Comparator Buffer Register
0x1A4
-1
read-write
n
0x0
0x0
TIMER1_PWMCMPDAT
TIMER1_PWMCMPDAT
Timer1 PWM Comparator Register
0x154
-1
read-write
n
0x0
0x0
TIMER1_PWMCNT
TIMER1_PWMCNT
Timer1 PWM Counter Register
0x15C
-1
read-write
n
0x0
0x0
TIMER1_PWMCNTCLR
TIMER1_PWMCNTCLR
Timer1 PWM Clear Counter Register
0x14C
-1
read-write
n
0x0
0x0
TIMER1_PWMCTL
TIMER1_PWMCTL
Timer1 PWM Control Register
0x140
-1
read-write
n
0x0
0x0
TIMER1_PWMDTCTL
TIMER1_PWMDTCTL
Timer1 PWM Dead-time Control Register
0x158
-1
read-write
n
0x0
0x0
TIMER1_PWMINTEN0
TIMER1_PWMINTEN0
Timer1 PWM Interrupt Enable Register 0
0x180
-1
read-write
n
0x0
0x0
TIMER1_PWMINTSTS0
TIMER1_PWMINTSTS0
Timer1 PWM Interrupt Status Register 0
0x188
-1
read-write
n
0x0
0x0
TIMER1_PWMMSK
TIMER1_PWMMSK
Timer1 PWM Output Mask Data Control Register
0x164
-1
read-write
n
0x0
0x0
TIMER1_PWMMSKEN
TIMER1_PWMMSKEN
Timer1 PWM Output Mask Enable Register
0x160
-1
read-write
n
0x0
0x0
TIMER1_PWMPBUF
TIMER1_PWMPBUF
Timer1 PWM Period Buffer Register
0x1A0
-1
read-write
n
0x0
0x0
TIMER1_PWMPERIOD
TIMER1_PWMPERIOD
Timer1 PWM Period Register
0x150
-1
read-write
n
0x0
0x0
TIMER1_PWMPOEN
TIMER1_PWMPOEN
Timer1 PWM Pin Output Enable Register
0x178
-1
read-write
n
0x0
0x0
TIMER1_PWMPOLCTL
TIMER1_PWMPOLCTL
Timer1 PWM Pin Output Polar Control Register
0x174
-1
read-write
n
0x0
0x0
TIMER1_PWMSCTL
TIMER1_PWMSCTL
Timer1 PWM Synchronous Control Register
0x194
-1
read-write
n
0x0
0x0
TIMER1_PWMSTATUS
TIMER1_PWMSTATUS
Timer1 PWM Status Register
0x19C
-1
read-write
n
0x0
0x0
TIMER1_TRGCTL
TIMER1_TRGCTL
Timer1 Trigger Control Register
0x11C
-1
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x28
registers
n
0x174
0x8
registers
n
0x180
0x4
registers
n
0x188
0x4
registers
n
0x194
0x4
registers
n
0x19C
0xC
registers
n
0x40
0x28
registers
n
0x74
0x8
registers
n
0x80
0x4
registers
n
0x88
0x4
registers
n
0x94
0x14
registers
n
TIMER2_ALTCTL
TIMER2_ALTCTL
Timer2 Alternative Control Register
0x20
-1
read-write
n
0x0
0x0
FUNCSEL
Function Selection
Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
0
1
read-write
0
Timer controller is used as timer function
#0
1
Timer controller is used as PWM function
#1
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register (Read Only)
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
Read operation.
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
Write operation.
Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)
This bit indicates if the counter reset operation active.
When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
Note: This bit is read only.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTEN
Timer Counting Enable Bit
Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protected)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Control
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.
Note: For Timer1/3, this bit is ignored and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The Timer controller is operated in One-shot mode
#00
1
The Timer controller is operated in Periodic mode
#01
2
The Timer controller is operated in Toggle-output mode
#10
3
The Timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit
If updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter
Note: Overwriting prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer External Capture Pin Enable Bit
This bit enables the TMx_EXT capture pin input function.
3
1
read-write
0
TMx_EXT (x= 0~3) pin Disabled
#0
1
TMx_EXT (x= 0~3) pin Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Reserved Event Counter input source is from USB internal SOF output signal
#1
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Power-down mode if timer time-out interrupt signal generated
#1
TIMER2_PWMCLKPSC
TIMER2_PWMCLKPSC
Timer2 PWM Counter Clock Pre-scale Register
0x48
-1
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Pre-scale
The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
0
12
read-write
TIMER2_PWMCLKSRC
TIMER2_PWMCLKSRC
Timer2 PWM Counter Clock Source Register
0x44
-1
read-write
n
0x0
0x0
CLKSRC
PWM Counter Clock Source Select
The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
0
3
read-write
0
TMRx_CLK
#000
1
Internal TIMER0 time-out or capture event
#001
2
Internal TIMER1 time-out or capture event
#010
3
Internal TIMER2 time-out or capture event
#011
4
Internal TIMER3 time-out or capture event
#100
TIMER2_PWMCMPBUF
TIMER2_PWMCMPBUF
Timer2 PWM Comparator Buffer Register
0xA4
-1
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Buffer Register (Read Only)
Used as CMP active register.
0
16
read-only
TIMER2_PWMCMPDAT
TIMER2_PWMCMPDAT
Timer2 PWM Comparator Register
0x54
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events.
0
16
read-write
TIMER2_PWMCNT
TIMER2_PWMCNT
Timer2 PWM Counter Register
0x5C
-1
read-only
n
0x0
0x0
CNT
PWM Counter Value Register (Read Only)
User can monitor CNT to know the current counter value in 16-bit period counter.
0
16
read-only
DIRF
PWM Counter Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is active in down count
#0
1
Counter is active up count
#1
TIMER2_PWMCNTCLR
TIMER2_PWMCNTCLR
Timer2 PWM Clear Counter Register
0x4C
-1
read-write
n
0x0
0x0
CNTCLR
Clear PWM Counter Control Bit
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type
#1
TIMER2_PWMCTL
TIMER2_PWMCTL
Timer2 PWM Control Register
0x40
-1
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit
0
1
read-write
0
PWM counter and clock prescale Stop Running
#0
1
PWM counter and clock prescale Start Running
#1
CNTMODE
PWM Counter Mode
3
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
CNTTYPE
PWM Counter Behavior Type
1
2
read-write
0
Up count type
#00
1
Down count type
#01
2
Up-down count type
#10
3
Reserved. Do not use
#11
CTRLD
Center Re-load
In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
8
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protected)
If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
Note: This register is write protected. Refer toSYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt disable
#0
1
ICE debug mode counter halt enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protected)
PWM output pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer toSYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDEN
Immediately Load Enable Bit
Note: If IMMLDEN is enabled, CTRLD will be invalid.
9
1
read-write
0
PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period
#0
1
PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP
#1
OUTMODE
PWM Output Mode
This bit controls the output mode of corresponding PWM channel.
16
1
read-write
0
PWM independent mode
#0
1
PWM complementary mode
#1
TIMER2_PWMDTCTL
TIMER2_PWMDTCTL
Timer2 PWM Dead-time Control Register
0x58
-1
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protected)
Note: This register is write protected. Refer to SYS_REGLCTL register.
24
1
read-write
0
Dead-time clock source from TMRx_PWMCLK without counter clock prescale
#0
1
Dead-time clock source from TMRx_PWMCLK with counter clock prescale
#1
DTCNT
Dead-time Counter (Write Protected)
The dead-time can be calculated from the following two formulas:
Note: This register is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protected)
Dead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
Note: This register is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
TIMER2_PWMINTEN0
TIMER2_PWMINTEN0
Timer2 PWM Interrupt Enable Register 0
0x80
-1
read-write
n
0x0
0x0
CMPDIEN
PWM Compare Down Count Interrupt Enable Bit
3
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN
PWM Compare Up Count Interrupt Enable Bit
2
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN
PWM Period Point Interrupt Enable Bit
Note: When in up-down count type, period point means the center point of current PWM period.
1
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN
PWM Zero Point Interrupt Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
TIMER2_PWMINTSTS0
TIMER2_PWMINTSTS0
Timer2 PWM Interrupt Status Register 0
0x88
-1
read-write
n
0x0
0x0
CMPDIF
PWM Compare Down Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
Note2: This bit is cleared by writing 1 to it.
3
1
read-write
CMPUIF
PWM Compare Up Count Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..
Note2: This bit is cleared by writing 1 to it.
2
1
read-write
PIF
PWM Period Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
Note2: This bit is cleared by writing 1 to it.
1
1
read-write
ZIF
PWM Zero Point Interrupt Flag
This bit is set by hardware when TIMERx_PWM counter reaches zero.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
TIMER2_PWMMSK
TIMER2_PWMMSK
Timer2 PWM Output Mask Data Control Register
0x64
-1
read-write
n
0x0
0x0
MSKDAT0
PWMx_CH0 Output Mask Data Control Bit
0
1
read-write
0
Output logic Low to PWMx_CH0
#0
1
Output logic High to PWMx_CH0
#1
MSKDAT1
PWMx_CH1 Output Mask Data Control Bit
1
1
read-write
0
Output logic Low to PWMx_CH1
#0
1
Output logic High to PWMx_CH1
#1
TIMER2_PWMMSKEN
TIMER2_PWMMSKEN
Timer2 PWM Output Mask Enable Register
0x60
-1
read-write
n
0x0
0x0
MSKEN0
PWMx_CH0 Output Mask Enable Bit
The PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
0
1
read-write
0
PWMx_CH0 output signal is non-masked
#0
1
PWMx_CH0 output signal is masked and output MSKDAT0 data
#1
MSKEN1
PWMx_CH1 Output Mask Enable Bit
The PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
1
1
read-write
0
PWMx_CH1 output signal is non-masked
#0
1
PWMx_CH1 output signal is masked and output MSKDAT1 data
#1
TIMER2_PWMPBUF
TIMER2_PWMPBUF
Timer2 PWM Period Buffer Register
0xA0
-1
read-only
n
0x0
0x0
PBUF
PWM Period Buffer Register (Read Only)
Used as PERIOD active register.
0
16
read-only
TIMER2_PWMPERIOD
TIMER2_PWMPERIOD
Timer2 PWM Period Register
0x50
-1
read-write
n
0x0
0x0
PERIOD
PWM Period Register
In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
In up and down count type:
Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
0
16
read-write
TIMER2_PWMPOEN
TIMER2_PWMPOEN
Timer2 PWM Pin Output Enable Register
0x78
-1
read-write
n
0x0
0x0
POEN0
PWMx_CH0 Output Pin Enable Bit
0
1
read-write
0
PWMx_CH0 pin at tri-state mode
#0
1
PWMx_CH0 pin in output mode
#1
POEN1
PWMx_CH1 Output Pin Enable Bit
1
1
read-write
0
PWMx_CH1 pin at tri-state mode
#0
1
PWMx_CH1 pin in output mode
#1
TIMER2_PWMPOLCTL
TIMER2_PWMPOLCTL
Timer2 PWM Pin Output Polar Control Register
0x74
-1
read-write
n
0x0
0x0
PINV0
PWMx_CH0 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH0 output pin.
0
1
read-write
0
PWMx_CH0 output pin polar inverse Disabled
#0
1
PWMx_CH0 output pin polar inverse Enabled
#1
PINV1
PWMx_CH1 Output Pin Polar Control Bit
The bit is used to control polarity state of PWMx_CH1 output pin.
1
1
read-write
0
PWMx_CH1 output pin polar inverse Disabled
#0
1
PWMx_CH1 output pin polar inverse Enabled
#1
TIMER2_PWMSCTL
TIMER2_PWMSCTL
Timer2 PWM Synchronous Control Register
0x94
-1
read-write
n
0x0
0x0
SYNCMODE
PWM Synchronous Mode Enable Select
0
2
read-write
0
PWM synchronous function Disabled
#00
1
PWM synchronous counter start function Enabled
#01
2
Reserved. Do not use
#10
3
PWM synchronous counter clear function Enabled
#11
SYNCSRC
PWM Synchronous Counter Start/Clear Source Select
Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
8
1
read-write
0
Counter synchronous start/clear by trigger STRGEN (TIMER0_PWMSTRG[0])
#0
1
Counter synchronous start/clear by trigger STRGEN (TIMER2_PWMSTRG[0])
#1
TIMER2_PWMSTATUS
TIMER2_PWMSTATUS
Timer2 PWM Status Register
0x9C
-1
read-write
n
0x0
0x0
CNTMAXF
PWM Counter Equal to 0xFFFF Flag
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
Indicates the PWM counter value never reached its maximum value 0xFFFF
#0
1
Indicates the PWM counter value has reached its maximum value
#1
TIMER2_PWMSTRG
TIMER2_PWMSTRG
Timer2 PWM Synchronous Trigger Register
0x98
-1
write-only
n
0x0
0x0
STRGEN
PWM Counter Synchronous Trigger Enable Bit (Write Only)
PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
Note: This bit is only available in TIMER0 and TIMER2.
0
1
write-only
TIMER2_TRGCTL
TIMER2_TRGCTL
Timer2 Trigger Control Register
0x1C
-1
read-write
n
0x0
0x0
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM Enable Bit
If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
1
1
read-write
0
Timer interrupt trigger PWM Disabled
#0
1
Timer interrupt trigger PWM Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger PWM, PDMA
#0
1
Capture interrupt signal is used to internal trigger PWM, PDMA
#1
TIMER3_ALTCTL
TIMER3_ALTCTL
Timer3 Alternative Control Register
0x120
-1
read-write
n
0x0
0x0
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x110
-1
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x104
-1
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x10C
-1
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x100
-1
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x118
-1
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x114
-1
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x108
-1
read-write
n
0x0
0x0
TIMER3_PWMCLKPSC
TIMER3_PWMCLKPSC
Timer3 PWM Counter Clock Pre-scale Register
0x148
-1
read-write
n
0x0
0x0
TIMER3_PWMCLKSRC
TIMER3_PWMCLKSRC
Timer3 PWM Counter Clock Source Register
0x144
-1
read-write
n
0x0
0x0
TIMER3_PWMCMPBUF
TIMER3_PWMCMPBUF
Timer3 PWM Comparator Buffer Register
0x1A4
-1
read-write
n
0x0
0x0
TIMER3_PWMCMPDAT
TIMER3_PWMCMPDAT
Timer3 PWM Comparator Register
0x154
-1
read-write
n
0x0
0x0
TIMER3_PWMCNT
TIMER3_PWMCNT
Timer3 PWM Counter Register
0x15C
-1
read-write
n
0x0
0x0
TIMER3_PWMCNTCLR
TIMER3_PWMCNTCLR
Timer3 PWM Clear Counter Register
0x14C
-1
read-write
n
0x0
0x0
TIMER3_PWMCTL
TIMER3_PWMCTL
Timer3 PWM Control Register
0x140
-1
read-write
n
0x0
0x0
TIMER3_PWMDTCTL
TIMER3_PWMDTCTL
Timer3 PWM Dead-time Control Register
0x158
-1
read-write
n
0x0
0x0
TIMER3_PWMINTEN0
TIMER3_PWMINTEN0
Timer3 PWM Interrupt Enable Register 0
0x180
-1
read-write
n
0x0
0x0
TIMER3_PWMINTSTS0
TIMER3_PWMINTSTS0
Timer3 PWM Interrupt Status Register 0
0x188
-1
read-write
n
0x0
0x0
TIMER3_PWMMSK
TIMER3_PWMMSK
Timer3 PWM Output Mask Data Control Register
0x164
-1
read-write
n
0x0
0x0
TIMER3_PWMMSKEN
TIMER3_PWMMSKEN
Timer3 PWM Output Mask Enable Register
0x160
-1
read-write
n
0x0
0x0
TIMER3_PWMPBUF
TIMER3_PWMPBUF
Timer3 PWM Period Buffer Register
0x1A0
-1
read-write
n
0x0
0x0
TIMER3_PWMPERIOD
TIMER3_PWMPERIOD
Timer3 PWM Period Register
0x150
-1
read-write
n
0x0
0x0
TIMER3_PWMPOEN
TIMER3_PWMPOEN
Timer3 PWM Pin Output Enable Register
0x178
-1
read-write
n
0x0
0x0
TIMER3_PWMPOLCTL
TIMER3_PWMPOLCTL
Timer3 PWM Pin Output Polar Control Register
0x174
-1
read-write
n
0x0
0x0
TIMER3_PWMSCTL
TIMER3_PWMSCTL
Timer3 PWM Synchronous Control Register
0x194
-1
read-write
n
0x0
0x0
TIMER3_PWMSTATUS
TIMER3_PWMSTATUS
Timer3 PWM Status Register
0x19C
-1
read-write
n
0x0
0x0
TIMER3_TRGCTL
TIMER3_TRGCTL
Timer3 Trigger Control Register
0x11C
-1
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x28
registers
n
0x2C
0x8
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD)
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM)
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.14.51.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.14.51.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.14.51.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.14.51.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UARTn_TXD pin.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UARTn_TXD pin.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value
These bits field indicate how many clock cycle selected by UARTn_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
4
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
4
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
2
read-write
0
UART function
#00
3
RS-485 function
#11
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not disable immediately when this bit is set. The TX and RX completed current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
This bit can enable or disable TX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit
Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically or by software.
Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control
This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode.
Note2: Refer to Figure 6.1415 and Figure 6.1416 for RS-485 function mode.
Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
nCTS change will wake-up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external
#1
WKDATEN
Incoming Data Wake-up Enable Bit
incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled, when the system is in Power-down mode,
#1
WKRFRTEN
RX FIFO Reached Threshold Wake-up Enable Bit
2
1
read-write
0
RX FIFO reached threshold wake-up system function Disabled
#0
1
RX FIFO reached threshold wake-up system function Enabled: RX FIFO reaching threshold wakes up the system from power down mode
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit
Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in
#1
WKTOUTEN
RX FIFO Time-out Wake-up Enable Bit
Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
RX FIFO time-out wake-up system function Disabled
#0
1
RX FIFO time-out wake-up system function Enabled: a time-out event for RX FIFO not reaching threshold wakes up the system from power down mode
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
This bit is set if chip wake-up from power-down state by RX FIFO reached threshold
wake-up .
Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the RX FIFO Reached Threshold wake-up cause this bit is set to '1'.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RX FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
RX FIFO Threshold Time-out Wake-up Flag
This bit is set indicating system wake-up from a RX FIFO Threshold Time-out event
wake-up.
Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the RX FIFO threshold time-out wake-up will set TOUTWKF bit to '1'.
Note2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from RX FIFO Threshold Time-out event
#1
UART1
UART Register Map
UART
0x0
0x0
0x28
registers
n
0x2C
0x8
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD)
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM)
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.14.51.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.14.51.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.14.51.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.14.51.
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
-1
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten
These 9-bits are used to define the relative bit is compensated or not.
BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UARTn_TXD pin.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UARTn_TXD pin.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value
These bits field indicate how many clock cycle selected by UARTn_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
4
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
4
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
2
read-write
0
UART function
#00
3
RS-485 function
#11
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not disable immediately when this bit is set. The TX and RX completed current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
This bit can enable or disable TX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated .
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit
Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically or by software.
Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control
This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note1: Refer to Figure 6.1413 and Figure 6.1414 for UART function mode.
Note2: Refer to Figure 6.1415 and Figure 6.1416 for RS-485 function mode.
Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
nCTS change will wake-up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external
#1
WKDATEN
Incoming Data Wake-up Enable Bit
incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled, when the system is in Power-down mode,
#1
WKRFRTEN
RX FIFO Reached Threshold Wake-up Enable Bit
2
1
read-write
0
RX FIFO reached threshold wake-up system function Disabled
#0
1
RX FIFO reached threshold wake-up system function Enabled: RX FIFO reaching threshold wakes up the system from power down mode
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit
Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode
and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in
#1
WKTOUTEN
RX FIFO Time-out Wake-up Enable Bit
Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
RX FIFO time-out wake-up system function Disabled
#0
1
RX FIFO time-out wake-up system function Enabled: a time-out event for RX FIFO not reaching threshold wakes up the system from power down mode
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
This bit is set if chip wake-up from power-down state by RX FIFO reached threshold
wake-up .
Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the RX FIFO Reached Threshold wake-up cause this bit is set to '1'.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RX FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag
This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.
Note2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
RX FIFO Threshold Time-out Wake-up Flag
This bit is set indicating system wake-up from a RX FIFO Threshold Time-out event
wake-up.
Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the RX FIFO threshold time-out wake-up will set TOUTWKF bit to '1'.
Note2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from RX FIFO Threshold Time-out event
#1
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x20
0x8
registers
n
0x500
0xC0
registers
n
0x8C
0x8
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-up Resistor on USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
RESUME
Resume Status
Note: This bit is read only.
2
1
read-write
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status
Note: This bit is read only.
1
1
read-write
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TOUT
Time-out Status
Note: This bit is read only.
3
1
read-write
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status
Note: This bit is read only.
0
1
read-write
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
-1
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
USBD_SRAM address + { BUFSEG, 3'b000}
Refer to the section 6.21.5.7 for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USBD_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
-1
read-write
n
0x0
0x0
BUFSEG10
USBD_BUFSEG10
Endpoint 10 Buffer Segmentation Register
0x5A0
-1
read-write
n
0x0
0x0
BUFSEG11
USBD_BUFSEG11
Endpoint 11 Buffer Segmentation Register
0x5B0
-1
read-write
n
0x0
0x0
BUFSEG2
USBD_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
-1
read-write
n
0x0
0x0
BUFSEG3
USBD_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
-1
read-write
n
0x0
0x0
BUFSEG4
USBD_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
-1
read-write
n
0x0
0x0
BUFSEG5
USBD_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
-1
read-write
n
0x0
0x0
BUFSEG6
USBD_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
-1
read-write
n
0x0
0x0
BUFSEG7
USBD_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
-1
read-write
n
0x0
0x0
BUFSEG8
USBD_BUFSEG8
Endpoint 8 Buffer Segmentation Register
0x580
-1
read-write
n
0x0
0x0
BUFSEG9
USBD_BUFSEG9
Endpoint 9 Buffer Segmentation Register
0x590
-1
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x508
-1
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number
These bits are used to define the endpoint number of the current endpoint
0
4
read-write
ISOCH
Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USBD_CFG1
Endpoint 1 Configuration Register
0x518
-1
read-write
n
0x0
0x0
CFG10
USBD_CFG10
Endpoint 10 Configuration Register
0x5A8
-1
read-write
n
0x0
0x0
CFG11
USBD_CFG11
Endpoint 11 Configuration Register
0x5B8
-1
read-write
n
0x0
0x0
CFG2
USBD_CFG2
Endpoint 2 Configuration Register
0x528
-1
read-write
n
0x0
0x0
CFG3
USBD_CFG3
Endpoint 3 Configuration Register
0x538
-1
read-write
n
0x0
0x0
CFG4
USBD_CFG4
Endpoint 4 Configuration Register
0x548
-1
read-write
n
0x0
0x0
CFG5
USBD_CFG5
Endpoint 5 Configuration Register
0x558
-1
read-write
n
0x0
0x0
CFG6
USBD_CFG6
Endpoint 6 Configuration Register
0x568
-1
read-write
n
0x0
0x0
CFG7
USBD_CFG7
Endpoint 7 Configuration Register
0x578
-1
read-write
n
0x0
0x0
CFG8
USBD_CFG8
Endpoint 8 Configuration Register
0x588
-1
read-write
n
0x0
0x0
CFG9
USBD_CFG9
Endpoint 9 Configuration Register
0x598
-1
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
-1
read-write
n
0x0
0x0
CLRRDY
Clear Ready
When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
This bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USBD_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
-1
read-write
n
0x0
0x0
CFGP10
USBD_CFGP10
Endpoint 10 Set Stall and Clear In/Out Ready Control Register
0x5AC
-1
read-write
n
0x0
0x0
CFGP11
USBD_CFGP11
Endpoint 11 Set Stall and Clear In/Out Ready Control Register
0x5BC
-1
read-write
n
0x0
0x0
CFGP2
USBD_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
-1
read-write
n
0x0
0x0
CFGP3
USBD_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
-1
read-write
n
0x0
0x0
CFGP4
USBD_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
-1
read-write
n
0x0
0x0
CFGP5
USBD_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
-1
read-write
n
0x0
0x0
CFGP6
USBD_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
-1
read-write
n
0x0
0x0
CFGP7
USBD_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
-1
read-write
n
0x0
0x0
CFGP8
USBD_CFGP8
Endpoint 8 Set Stall and Clear In/Out Ready Control Register
0x58C
-1
read-write
n
0x0
0x0
CFGP9
USBD_CFGP9
Endpoint 9 Set Stall and Clear In/Out Ready Control Register
0x59C
-1
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
-1
read-only
n
0x0
0x0
OV
Overrun
It indicates that the received data is over the maximum payload number or not.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
EPSTS0
USBD_EPSTS0
USB Device Endpoint Status Register 0
0x20
-1
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Status
These bits are used to indicate the current status of this endpoint
0
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS1
Endpoint 1 Status
These bits are used to indicate the current status of this endpoint
4
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS2
Endpoint 2 Status
These bits are used to indicate the current status of this endpoint
8
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS3
Endpoint 3 Status
These bits are used to indicate the current status of this endpoint
12
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS4
Endpoint 4 Status
These bits are used to indicate the current status of this endpoint
16
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS5
Endpoint 5 Status
These bits are used to indicate the current status of this endpoint
20
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS6
Endpoint 6 Status
These bits are used to indicate the current status of this endpoint
24
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS7
Endpoint 7 Status
These bits are used to indicate the current status of this endpoint
28
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS1
USBD_EPSTS1
USB Device Endpoint Status Register 1
0x24
-1
read-only
n
0x0
0x0
EPSTS10
Endpoint 10 Status
These bits are used to indicate the current status of this endpoint
8
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS11
Endpoint 11 Status
These bits are used to indicate the current status of this endpoint
12
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS8
Endpoint 8 Status
These bits are used to indicate the current status of this endpoint
0
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS9
Endpoint 9 Status
These bits are used to indicate the current status of this endpoint
4
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
-1
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FN
USBD_FN
USB Frame Number Register
0x8C
-1
read-only
n
0x0
0x0
FN
Frame Number
These bits contain the 11-bits frame number in the last received SOF packet.
0
11
read-only
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function and Its Status in IN Token
15
1
read-write
0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-event-wake-up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
SOFIEN
Start of Frame Interrupt Enable Bit
4
1
read-write
0
SOF Interrupt Disabled
#0
1
SOF Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-up Function Enable Bit
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
-1
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status
The BUS event means that there is one of the suspend or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT10
Endpoint 10's USB Event Status
26
1
read-write
0
No event occurred in endpoint 10
#0
1
USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1]
#1
EPEVT11
Endpoint 11's USB Event Status
27
1
read-write
0
No event occurred in endpoint 11
#0
1
USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status
22
1
read-write
0
No event occurred in endpoint 6
#0
1
USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status
23
1
read-write
0
No event occurred in endpoint 7
#0
1
USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
#1
EPEVT8
Endpoint 8's USB Event Status
24
1
read-write
0
No event occurred in endpoint 8
#0
1
USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1]
#1
EPEVT9
Endpoint 9's USB Event Status
25
1
read-write
0
No event occurred in endpoint 9
#0
1
USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1]
#1
NEVWKIF
No-event-wake-up Interrupt Status
3
1
read-write
0
NEVWK event does not occur
#0
1
No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by writing 1 to USBD_INTSTS[31]
#1
SOFIF
Start of Frame Interrupt Status
4
1
read-write
0
SOF event does not occur
#0
1
SOF event occurred, cleared by write 1 to USBD_INTSTS[4]
#1
USBIF
USB Event Interrupt Status
The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS (USBD_EPSTS0 and USBD_EPSTS1) to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPEVT11~0 (USBD_INTSTS[27:16] and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]
#1
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
-1
read-write
n
0x0
0x0
MXPLD
Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USBD_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
-1
read-write
n
0x0
0x0
MXPLD10
USBD_MXPLD10
Endpoint 10 Maximal Payload Register
0x5A4
-1
read-write
n
0x0
0x0
MXPLD11
USBD_MXPLD11
Endpoint 11 Maximal Payload Register
0x5B4
-1
read-write
n
0x0
0x0
MXPLD2
USBD_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
-1
read-write
n
0x0
0x0
MXPLD3
USBD_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
-1
read-write
n
0x0
0x0
MXPLD4
USBD_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
-1
read-write
n
0x0
0x0
MXPLD5
USBD_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
-1
read-write
n
0x0
0x0
MXPLD6
USBD_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
-1
read-write
n
0x0
0x0
MXPLD7
USBD_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
-1
read-write
n
0x0
0x0
MXPLD8
USBD_MXPLD8
Endpoint 8 Maximal Payload Register
0x584
-1
read-write
n
0x0
0x0
MXPLD9
USBD_MXPLD9
Endpoint 9 Maximal Payload Register
0x594
-1
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero in USB Bus
The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
-1
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation
It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
USBD_SRAM address + {STBUFSEG, 3'b000}
Note: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
-1
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
VAD
DMIC Register Map
DMIC
0x0
0x0
0x30
registers
n
BIQCTL0
VAD_BIQCTL0
VAD Biquad Filter Control Register 0
0x4
-1
read-write
n
0x0
0x0
BIQA1
VAD Biquad Filter Coefficient
Biquad Filter Coefficient a1, in 3 intergers + 13 fractional bits
0
16
read-write
BIQA2
VAD Biquad Filter Coefficient
Biquad Filter Coefficient a2, in 3 intergers + 13 fractional bits.
16
16
read-write
BIQCTL1
VAD_BIQCTL1
VAD Biquad Filter Control Register 1
0x8
-1
read-write
n
0x0
0x0
BIQB0
VAD Biquad Filter Coefficient
Biquad Filter Coefficient b0, in 3 intergers + 13 fractional bits.
0
16
read-write
BIQB1
VAD Biquad Filter Coefficient
Biquad Filter Coefficient b1, in 3 intergers + 13 fractional bits.
16
16
read-write
BIQCTL2
VAD_BIQCTL2
VAD Biquad Filter Control Register 2
0xC
-1
read-write
n
0x0
0x0
BIQB2
VAD Biquad Filter Coefficient
Biquad Filter Coefficient b2, in 3 intergers + 13 fractional bits.
0
16
read-write
BIQEN
VAD Biquad Filter Enable Bit
31
1
read-write
0
VAD Biquad Filter Disabled
#0
1
VAD Biquad Filter Enabled
#1
CTL0
VAD_CTL0
VAD Control Register 0
0x10
-1
read-write
n
0x0
0x0
LTAT
Long Term Power Attack Time
Slow attack (e.g., 0x5): less sensitive to environment change.
Fast attack (e.g., 0x8): more sensitive to environment change.
16
4
read-write
STAT
Short Term Power Attack Time
Slow attack (e.g., 0x99): slow responding to voice, but more stable.
Fast attack (e.g., 0xCC): fast responding to voice, but more sensitive to other sounds.
Suggested default attack time setting: Long term power attack time (0x5), Short term power attack time (0xAA).
The 'Short Term Power', in order to detect the instant power of the voices, requires faster attack time, while 'Long Term Power', in order to get the averaged power of the background environment, requires slower attack time to maintain its stability. So the Short term power attack time should be always bigger than the Long term power attack time.
0
8
read-write
CTL1
VAD_CTL1
VAD Control Register 1
0x14
-1
read-write
n
0x0
0x0
STPTHL
Short Term Power Threshold Lower Limit
To check if the incoming signal is small enough so that VAD status can be terminated.
16
16
read-write
STPTHU
Short Term Power Threshold Upper Limit
To check if the incoming signal is big enough to be ready for VAD activation.
0
16
read-write
CTL2
VAD_CTL2
VAD Control Register 2
0x18
-1
read-write
n
0x0
0x0
LTTHRE
Long Term Power Threshold
To check the background energy, also serve as the lower limit of long term power. When the long term power value is lower than the threshold, it will be set to the threshold value for VAD decision.
16
16
read-write
CTL3
VAD_CTL3
VAD Control Register 3
0x1C
-1
read-write
n
0x0
0x0
DEVTHRE
Deviation Threshold
To check if the incoming signal is substantially bigger than its background. This may work to exclude breath sound as it is slowly varying, but not other sounds (e.g., footsteps, hand claps) with sudden amplitude increase.
Small: easy to trigger, good for far-field pick-up, but requiring quiet environment.
Large: good for handheld applications, but requiring louder voice to trigger.
0
16
read-write
HOT
Hang Over time
Hang Over time setting, means how many clocks (CLKSD) of the ACTIVE (VAD_STATUS0[31]) staying high when the calculation is no longer bigger than the threshold
16
16
read-write
PDMED_CTL
PDMED_CTL
PDMED Control Register
0x28
-1
read-write
n
0x0
0x0
DMCH
DMIC Channel Selection
2
1
read-write
0
Left
#0
1
Right
#1
OSCEN
PDMED 512K Oscillator Enable Control
1
1
read-write
0
Oscillator Disable
#0
1
Oscillator Enable
#1
PDMEDEN
PDMED Enable Control
0
1
read-write
0
PDMED Disable
#0
1
PDMED Enable
#1
PDMEDTH
PDMED Threshold Limit
To check if the incoming signal is big enough to be ready for PED activation.
8
6
read-write
PDMED_STATUS
PDMED_STATUS
PDMED Status Read-back Register
0x2C
-1
read-only
n
0x0
0x0
ACTIVE
Pulse Density Modulation Energy Dection Output to Decision Logic
When the voice active event occurs, this bit will be set to 1.
31
1
read-only
0
No effect
#0
1
Voice detected
#1
SINCCTL
VAD_SINCCTL
VAD SINC Filter Control Register
0x0
-1
read-write
n
0x0
0x0
ACTCL
VAD Active Flag Clear
Note: ACTIVE(VAD_STATUS0[31]) STP(VAD_STATUS0[15:0] LTP(VAD_STATUS1[31:16] DEV(VAD_STATUS1[15:0]) are cleared.
30
1
read-write
0
No effect
#0
1
Clear ACTIVE(VAD_STATUS0[31])
#1
DATAOFF
VAD Sending Data to SRAM Control
When the ACTIVE (VAD_STATUS0[31]) goes high, the data will be transferred to SRAM to store which can be used for keyword detection later. After some time, if user needs to stop sending data to SRAM, write this bit to 1.
28
1
read-write
MCLKDIV
Divider to generate the VAD Working Main Clock
The value in this field is the frequency divider for generating the VAD working main clock. The frequency is obtained according to the following equation.
where HIRC is the frequency of VAD module clock source, which enable HIRC in the System power down control register PWRCTL (CLK_PWRCTL[2])
16
8
read-write
SINCOSR
VAD SINC Filter OSR Setting
8
4
read-write
0
Down sample 48
000
1
Down sample 64
001
10
Down sample 96
010
SW
VAD Path Switch Control
After the ACTIVE(VAD_STATUS0[31]) goes high, it will automatically switch to the DMIC path. When the CPU is entering idle mode, write 1 to switch back to the VAD path.
29
1
read-write
0
No effect
#0
1
Switched back to VAD path(DMIC_CTL[0]=0)
#1
VADEN
VAD Enable Control
Note: When set this bit to 1, DMIC_CLK is generated by VAD module.
31
1
read-write
0
VAD Disabled
#0
1
VAD Enabled
#1
STATUS0
VAD_STATUS0
VAD Status Read-back Register 0
0x20
-1
read-only
n
0x0
0x0
ACTIVE
VAD Activation Flag (Read Only)
When the voice active event occurs, this bit will be set to 1.
31
1
read-only
0
No effect
#0
1
Voice detected
#1
STP
Short Term Signal Power (Read Only)
This field shows the short term signal power value.
0
16
read-only
STATUS1
VAD_STATUS1
VAD Status Read-back Register 1
0x24
-1
read-only
n
0x0
0x0
DEV
Deviation (Read Only)
This field shows deviation of the Long Term Signal Power and Short Term Signal Power.
0
16
read-only
LTP
Long Term Signal Power (Read Only)
This field shows the long term signal power value.
16
16
read-only
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
-1
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protected)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protected)
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag
This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Control (Write Protected)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: The reset value of this bit is 0.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTCNT
Reset WDT Up Counter (Write Protected)
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT up counter value
#1
RSTEN
WDT Time-out Reset Enable Control (Write Protected)
Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protected)
These three bits select the time-out interval period for the WDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
24 * WDT_CLK
#000
1
26 * WDT_CLK
#001
2
28 * WDT_CLK
#010
3
210 * WDT_CLK
#011
4
212 * WDT_CLK
#100
5
214 * WDT_CLK
#101
6
216 * WDT_CLK
#110
7
218 * WDT_CLK
#111
WDTEN
WDT Enable Control (Write Protected)
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protected)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
Note3: The reset value of this bit is 0.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protected)
This bit indicates the interrupt wake-up flag status of WDT
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit is cleared by writing 1 to it.
Note3: The reset value of this bit is 0.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value
CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Register
Set this register to adjust the valid reload window.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control
WWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Control Bit
If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Control Bit
Set this bit to enable WWDT counter counting.
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter is starting counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
-1
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register
Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
-1
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag
This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag
This bit indicates the system has been reset by WWDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1