nuvoTon
ISD91200B_v1
2024.05.02
ISD91200B_v1 SVD file
8
32
ALC
ALC Register Map
ALC
0x0
0x0
0x10
registers
n
CTL
ALC_CTL
ALC Control Register
0x0
-1
read-write
n
0x0
0x0
ALCEN
ALC Select
28
1
read-write
0
ALC disabled (default)
#0
1
ALC enabled
#1
ALCRANGESEL
ALC Target range selection
21
1
read-write
0
ALC target range -28.5~ -6dB
#0
1
ALC target range -22.5 ~-1.5dB
#1
ATKSEL
ALC Attack Time
(Value: 0~10)
4
4
read-write
DECAYSEL
ALC Decay Time
(Value: 0~10)
8
4
read-write
HOLDTIME
ALC Hold Time
17
4
read-write
MAXGAIN
ALC Maximum Gain
25
3
read-write
0
-6.75 dB
0
1
-0.75 dB
1
2
+5.25 dB
2
3
+11.25 dB
3
4
+17.25 dB
4
5
+23.25 dB
5
6
+29.25 dB
6
7
+35.25 dB
7
MINGAIN
ALC Minimum Gain
22
3
read-write
0
-12 dB
0
1
-6 dB
1
2
0 dB
2
3
6 dB
3
4
12 dB
4
5
18 dB
5
6
24 dB
6
7
30 dB
7
MODESEL
ALC Mode
12
1
read-write
0
ALC normal operation mode
#0
1
ALC limiter mode
#1
NGEN
Noise Gate Enable
3
1
read-write
0
Noise gate disabled
#0
1
Noise gate enabled
#1
NGPKSEL
ALC Noise Gate Peak Detector Select
29
1
read-write
0
use peak-to-peak value for noise gate threshold determination (default)
#0
1
use absolute peak value for noise gate threshold determination
#1
NGTHBST
Noise Gate Threshold
000 --- -39dB
001--- -45dB
010---- -51dB
011 --- -57dB
100 --- -63dB
101 --- -69dB
110 --- -75dB
111 --- -81dB
0
3
read-write
PKLIMEN
ALC Peak Limiter Enable
Default is 0 ,
Please set as 1
31
1
read-write
PKSEL
ALC Gain Peak Detector Select
30
1
read-write
0
use absolute peak value for ALC training (default)
#0
1
use peak-to-peak value for ALC training
#1
TARGETLV
ALC Target Level
13
4
read-write
0
-28.5 dB
0
1
-27 dB
1
10
-13.5 dB
10
11
-12 dB
11
12
-10.5 dB
12
13
-9 dB
13
14
-7.5 dB
14
15
-6 dB
15
2
-25.5 dB
2
3
-24 dB
3
4
-22.5 dB
4
5
-21 dB
5
6
-19.5 dB
6
7
-18 dB
7
8
-16.5 dB
8
9
-15 dB
9
GAIN
ALC_GAIN
ALC GAIN Control Register
0x4
-1
read-write
n
0x0
0x0
INITGAIN
ALC Initial Gain
Set ALC initial gain.
Selects the PGA gain setting from -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB
0
6
read-write
INITGAINEN
ALC Update Initial Gain
7
1
read-write
0
ALC PGA GAIN load automatic calculating gain
#0
1
ALC PGA GAIN load ALCINIT_GAIN
#1
PKLIMIT
ALC Peak Limiter Threshold
Full scale - 0x7fff
Default value is 0x6fdc - 87.5% of full scale
16
16
read-write
ZCEN
ALC Zero Crossing Enable
6
1
read-write
0
zero crossing disabled
#0
1
zero crossing enabled when update gain
#1
INTCTL
ALC_INTCTL
ALC Interrupt Control Register
0xC
-1
read-write
n
0x0
0x0
ALCIF
ALC Interrupt flag
This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated, either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled.
Write a 1 to this register to clear.
31
1
read-write
GDECIE
GAIN Decrease interrupt enable control
3
1
read-write
GDECIF
GAIN Decrease interrupt flag
11
1
read-write
GINCIE
GAIN Increase interrupt enable control
2
1
read-write
GINCIF
GAIN Increase interrupt flag
10
1
read-write
GMAXIE
GAIN more than maximum GAIN interrupt enable control
4
1
read-write
GMAXIF
GAIN more than maximum GAIN interrupt flag.
12
1
read-write
GMINIE
GAIN less than minimum GAIN interrupt enable control
5
1
read-write
GMINIF
GAIN less than minimum GAIN interrupt flag.
13
1
read-write
NGIE
ALC noise gating interrupt enable control
1
1
read-write
NGIF
ALC noise gating interrupt flag
9
1
read-write
PLMTIE
ALC Peak limiting Interrupt enable control
0
1
read-write
PLMTIF
ALC Peak limiting Interrupt flag
8
1
read-write
STS
ALC_STS
ALC Status Register
0x8
-1
read-write
n
0x0
0x0
ALCGAIN
ALC GAIN
Current ADC gain setting
20
6
read-write
CLIPF
Clipping Flag
Asserted when signal level is detected to be above 87.5% of full scale
0
1
read-write
NOISEF
Noise Flag
Asserted when signal level is detected to be below NGTHBST
1
1
read-write
P2PVAL
Peak-to-peak Value
9 MSBs of measured peak-to-peak value
2
9
read-write
PEAKVAL
Peak Value
9 MSBs of measured absolute peak value
11
9
read-write
ANA
ANA Register Map
ANA
0x0
0x0
0x4
registers
n
0x20
0x10
registers
n
0x84
0x4
registers
n
0x94
0xC
registers
n
FQMMCNT
ANA_FQMMCNT
Frequency Measurement Count Register
0x98
-1
read-write
n
0x0
0x0
FQMMCTL
ANA_FQMMCTL
Frequency Measurement Control Register
0x94
-1
read-write
n
0x0
0x0
FQMMCNT
Frequency Measurement Count
Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz
0
16
read-write
FQMMCYC
ANA_FQMMCYC
Frequency Measurement Cycle Register
0x9C
-1
read-write
n
0x0
0x0
FQMMCYC
Frequency Measurement Cycles
0
24
read-write
LDOPD
ANA_LDOPD
LDO Power Down Register
0x24
-1
read-write
n
0x0
0x0
DISCHAR
Discharge
1
1
read-write
0
Don't discharge VD33
#0
1
Switch discharge resistor to VD33
#1
PD
Power Down LDO
When powered down no current delivered to VD33.
0
1
read-write
0
Enable LDO
#0
1
Power Down
#1
LDOSEL
ANA_LDOSEL
LDO Voltage Select Register
0x20
-1
read-write
n
0x0
0x0
LDOSEL
Select LDO Output Voltage
Note that maximum I/O pad operation speed only specified for voltage >2.4V.
0
3
read-write
0
1.8V
0
1
2.4V
1
2
2.5V
2
3
2.7V
3
4
3.0V
4
5
3.3V
5
6
1.5V
6
7
1.7V
7
MICBEN
ANA_MICBEN
Microphone Bias Enable
0x2C
-1
read-write
n
0x0
0x0
MICBSEL
ANA_MICBSEL
Microphone Bias Voltage Level Selection
0x28
-1
read-write
n
0x0
0x0
TRIM
ANA_TRIM
Oscillator Trim Register
0x84
-1
read-write
n
0x0
0x0
COARSE
COARSE
Current COARSE range setting of the oscillator. Read Only
8
8
read-write
OSCTRIM
Oscillator Trim
Reads current oscillator trim setting. Read Only.
0
8
read-write
VMID
ANA_VMID
VMID Reference Control Register
0x0
-1
read-write
n
0x0
0x0
PDHIRES
Power Down High (360kΩ) Resistance Reference
2
1
read-write
0
Connect the High Resistance reference to VMID. Use this setting for minimum power consumption
#0
1
The High Resistance reference is disconnected from VMID. Default power down and reset condition
#1
PDLORES
Power Down Low (4.8kΩ) Resistance Reference
1
1
read-write
0
Connect the Low Resistance reference to VMID. Use this setting for fast power up of VMID. Can be turned off after 50ms to save power
#0
1
The Low Resistance reference is disconnected from VMID. Default power down and reset condition
#1
PULLDOWN
VMID Pulldown
0
1
read-write
0
Release VMID pin for reference operation
#0
1
Pull VMID pin to ground. Default power down and reset condition
#1
BIQ
BIQ Register Map
BIQ
0x0
0x0
0x78
registers
n
0x80
0x8
registers
n
COEFF0
BIQ_COEFF0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
0x0
-1
read-write
n
0x0
0x0
COEFFDAT
Coefficient Data
0
32
read-write
COEFF1
BIQ_COEFF1
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
0x4
-1
read-write
n
0x0
0x0
COEFF10
BIQ_COEFF10
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
0x28
-1
read-write
n
0x0
0x0
COEFF11
BIQ_COEFF11
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
0x2C
-1
read-write
n
0x0
0x0
COEFF12
BIQ_COEFF12
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
0x30
-1
read-write
n
0x0
0x0
COEFF13
BIQ_COEFF13
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
0x34
-1
read-write
n
0x0
0x0
COEFF14
BIQ_COEFF14
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
0x38
-1
read-write
n
0x0
0x0
COEFF15
BIQ_COEFF15
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
0x3C
-1
read-write
n
0x0
0x0
COEFF16
BIQ_COEFF16
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
0x40
-1
read-write
n
0x0
0x0
COEFF17
BIQ_COEFF17
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
0x44
-1
read-write
n
0x0
0x0
COEFF18
BIQ_COEFF18
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
0x48
-1
read-write
n
0x0
0x0
COEFF19
BIQ_COEFF19
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
0x4C
-1
read-write
n
0x0
0x0
COEFF2
BIQ_COEFF2
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
0x8
-1
read-write
n
0x0
0x0
COEFF20
BIQ_COEFF20
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
0x50
-1
read-write
n
0x0
0x0
COEFF21
BIQ_COEFF21
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
0x54
-1
read-write
n
0x0
0x0
COEFF22
BIQ_COEFF22
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
0x58
-1
read-write
n
0x0
0x0
COEFF23
BIQ_COEFF23
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
0x5C
-1
read-write
n
0x0
0x0
COEFF24
BIQ_COEFF24
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
0x60
-1
read-write
n
0x0
0x0
COEFF25
BIQ_COEFF25
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
0x64
-1
read-write
n
0x0
0x0
COEFF26
BIQ_COEFF26
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
0x68
-1
read-write
n
0x0
0x0
COEFF27
BIQ_COEFF27
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
0x6C
-1
read-write
n
0x0
0x0
COEFF28
BIQ_COEFF28
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
0x70
-1
read-write
n
0x0
0x0
COEFF29
BIQ_COEFF29
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
0x74
-1
read-write
n
0x0
0x0
COEFF3
BIQ_COEFF3
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
0xC
-1
read-write
n
0x0
0x0
COEFF4
BIQ_COEFF4
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
0x10
-1
read-write
n
0x0
0x0
COEFF5
BIQ_COEFF5
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
0x14
-1
read-write
n
0x0
0x0
COEFF6
BIQ_COEFF6
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
0x18
-1
read-write
n
0x0
0x0
COEFF7
BIQ_COEFF7
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
0x1C
-1
read-write
n
0x0
0x0
COEFF8
BIQ_COEFF8
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
0x20
-1
read-write
n
0x0
0x0
COEFF9
BIQ_COEFF9
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
0x24
-1
read-write
n
0x0
0x0
CTL
BIQ_CTL
BIQ Control Register
0x80
-1
read-write
n
0x0
0x0
BIQEN
BIQ Filter Start to Run
0
1
read-write
0
BIQ filter is not processing
#0
1
BIQ filter is on
#1
DLCOEFF
Move BIQ Out of Reset State
3
1
read-write
0
BIQ filter is in reset state
#0
1
When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on
#1
DPWMPUSR
DPWM Path Up Sample Rate (From SRDIV Result)
0001 --- up 1x ( no up sample)
0010 --- up 2x
0011 --- up 3x
0100 --- up 4x
0110 --- up 6x
Others reserved
8
3
read-write
HPFON
High Pass Filter On
Note :
If this register is on, BIQ only 5 stage left.for user.
SDADC path sixth stage coefficient is for HPF filter coefficient.
DPWM path first stage coefficient is for HPF filter coefficient.
1
1
read-write
0
disable high pass filter
#0
1
enable high pass filter
#1
PATHSEL
AC Path Selection for BIQ
2
1
read-write
0
used in SDADC path
#0
1
used in DPWM path
#1
PRGCOEFF
Programming Mode Coefficient Control Bit
This bit must be turned off when BIQEN is on.
7
1
read-write
0
Coefficient RAM is in normal mode
#0
1
coefficient RAM is under programming mode
#1
SDADCWNSR
SDADC Down Sample
001--- 1x (no down sample)
010 --- 2x
011 --- 3x
100 --- 4x
11 0--- 6x
Others reserved
4
3
read-write
SRDIV
SR Divider
16
13
read-write
STAGE
BIQ Stage Number Control
11
1
read-write
0
6 stage
#0
1
5 stage
#1
STS
BIQ_STS
BIQ Status Register
0x84
-1
read-write
n
0x0
0x0
BISTDONE
RAM BIST testing DONE flag for internal use
2
1
read-write
BISTEN
RAM BIST testing Enable for internal use
0
1
read-write
BISTFAILED
RAM BIST testing FAILED indicator for internal use
1
1
read-write
RAMINITF
Coefficient Ram Initial Default Done Flag
31
1
read-write
0
initial default value done
#0
1
still working on
#1
BOD
BOD Register Map
BOD
0x0
0x0
0x8
registers
n
0x10
0x4
registers
n
BODCTL
BOD_BODCTL
Brown Out Detector Enable Register
0x4
-1
read-write
n
0x0
0x0
BODEN
BOD Enable
0
2
read-write
BODIF
Current Status of Interrupt
3
1
read-write
BODINTEN
BOD Interrupt Enable
2
1
read-write
0
Disable BOD Interrupt
#0
1
Enable BOD Interrupt
#1
BODOUT
Output of BOD Detection Block
4
1
read-write
BODRST
BOD Reset
1: Reset device when BOD is triggered.
5
1
read-write
LVR_EN
Low Voltage Reset (LVR) Enable (Initialized and Protected Bit)
The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config0[27].
16
1
read-write
0
Disable LVR function
#0
1
Enable LVR function
#1
LVR_FILTER
Default value is 00.
17
2
read-write
0
LVR output will be filtered by 1 HCLK
#00
1
LVR output will be filtered by 2 HCLK
#01
2
LVR output will be filtered by 8 HCLK
#10
3
LVR output will be filtered by 15 HCLK
#11
BODDTMR
BOD_BODDTMR
Brown Out Detector Timer Register
0x10
-1
read-write
n
0x0
0x0
DURTOFF
Time BOD Detector Is Off
(DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)
0
16
read-write
DURTON
Time BOD Detector Is Active
(DURTON+1) * 100us. Minimum value is 1. (default is 400us)
16
4
read-write
BODSEL
BOD_BODSEL
Brown Out Detector Select Register
0x0
-1
read-write
n
0x0
0x0
BODHYS
BOD Hysteresis
4
1
read-write
0
Hysteresis Disabled
#0
1
Enable Hysteresis of BOD detection
#1
BODVL
BOD Voltage Level
0
4
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x30
registers
n
AHBCLK
CLK_AHBCLK
AHB Device Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
HCLKEN
CPU Clock Enable (HCLK)
Must be left as 1 for normal operation.
0
1
read-write
ISPCKEN
Flash ISP Controller Clock Enable Control
2
1
read-write
0
To disable the Flash ISP engine clock
#0
1
To enable the Flash ISP engine clock
#1
PDMACKEN
PDMA Controller Clock Enable Control
1
1
read-write
0
To disable the PDMA engine clock
#0
1
To enable the PDMA engine clock
#1
APBCLK0
CLK_APBCLK0
APB Device Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ANACKEN
Analog Block Clock Enable Control
30
1
read-write
0
Disable
#0
1
Enable
#1
BIQALCKEN
BIQ and ALC Clock Enable Control
18
1
read-write
0
Disable
#0
1
Enable
#1
DPWMCKEN
Differential PWM Speaker Driver Clock Enable Control
13
1
read-write
0
Disable
#0
1
Enable
#1
I2C0CKEN
I2C0 Clock Enable Control
8
1
read-write
0
Disable
#0
1
Enable
#1
I2S0CKEN
I2S Clock Enable Control
29
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH01CKEN
PWM0CH0 and PWM0CH1 Block Clock Enable Control
20
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH23CKEN
PWM0CH2 and PWM0CH3 Block Clock Enable Control
21
1
read-write
0
Disable
#0
1
Enable
#1
RTCCKEN
Real-time-clock APB Interface Clock Control
5
1
read-write
0
Disable
#0
1
Enable
#1
SARADCKEN
SAR Analog-digital-converter (ADC) Clock Enable Control
17
1
read-write
0
Disable
#0
1
Enable
#1
SDADCCKEN
Delta-Sigma Analog-digital-converter (ADC) Enable Control
28
1
read-write
0
Disable
#0
1
Enable
#1
SPI0CKEN
SPI0 Clock Enable Control
12
1
read-write
0
Disable
#0
1
Enable
#1
SPI1CKEN
SPI1 Clock Enable Control
11
1
read-write
0
Disable
#0
1
Enable
#1
TMR0CKEN
Timer0 Clock Enable Control
6
1
read-write
0
Disable
#0
1
Enable
#1
TMR1CKEN
Timer1 Clock Enable Control
7
1
read-write
0
Disable
#0
1
Enable
#1
UART0CKEN
UART0 Clock Enable Control
16
1
read-write
0
Disable
#0
1
Enable
#1
UART1CKEN
UART1 Clock Enable Control
15
1
read-write
0
Disable
#0
1
Enable
#1
WDTCKEN
Watchdog Clock Enable Control
0
1
read-write
0
Disable
#0
1
Enable
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register
0x18
-1
read-write
n
0x0
0x0
BIQDIV
BIQ Clock Divide Number From HCLK Clock Source
4
4
read-write
DPWMDIV
DPWM Clock Divide Number From HCLK Clock Source
12
4
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
SARADCDIV
SARADC Clock Divide Number From ADC Clock Source
24
8
read-write
SDADCDIV
SDADC Clock Divide Number From ADC Clock Source
16
8
read-write
UARTDIV
UART Clock Divide Number From UART Clock Source
8
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Select
Ensure that related clock sources (pre-select and new-select) are enabled before updating register.
These bits are protected, to write to bits first perform the unlock sequence.
0
3
read-write
0
clock source from HIRC. (deafult)
#000
1
clock source from LXT
#001
2
clock source from LIRC
#010
3
clock source from HXT
#011
HIRCFSEL
High Frequency RC Oscilltor Frequency Select Register.
These bits are protected, to write to bits first perform the unlock sequence.
6
2
read-write
0
Trim for 49.152MHz selected
#00
1
Trim for 32.768MHz selected
#01
2
Trim for reserved
#10
STCLKSEL
MCU Cortex_M0 SYST Clock Source Select
These bits are protected, to write to bits first perform the unlock sequence.
Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR must be set to 0.
3
3
read-write
0
clock source from LIRC
#000
1
clock source from LXT.
clock source from HCLK÷2 (Default)
#001
2
clock source from LIRC divided by 2
#010
3
clock source from HIRC divided by 2
#011
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
DPWMSEL
Differential Speaker Driver PWM Clock Source Select
4
2
read-write
0
clock source from HCLK/(DPWMDIV+1). (default)
#00
1
clock source from HXT
Reserved
#01
PWM0CH01SEL
PWM0CH01 Clock Source Select
PWM0 CH0 and CH1 uses the same clock source, and pre-scaler
28
2
read-write
0
clock source from LIRC
#00
1
clock source from LXT
#01
2
clock source from HCLK
#10
3
clock source from HIRC.(default)
#11
PWM0CH23SEL
PWM0CH23 Clock Source Select
PWM0 CH2 and CH3 uses the same clock source, and pre-scaler
30
2
read-write
0
clock source from LIRC
#00
1
clock source from LXT
#01
2
clock source from HCLK
#10
3
clock source from HIRC.(default)
#11
SARADCSEL
SAR ADC Clock Source Select
24
2
read-write
0
clock source from HCLK (default)
#00
1
clock source from LIRC
#01
2
clock source from HIRC
#10
3
clock source from LXT
#11
SDADCSEL
SD ADC Clock Source Select (output is MCLK after clock enable)
2
2
read-write
0
clock source from HCLK/(SDADCDIV+1). (default)
#00
1
clock source from HXT
Reserved
#01
TMR0SEL
TIMER0 Clock Source Select
8
3
read-write
0
clock source from LIRC
#000
1
clock source from LXT.
clock source from internal HCLK.(default)
#001
2
clock source from HXT
#010
3
clock source from external pin (GPIOA[10])
#011
TMR1SEL
TIMER1 Clock Source Select
12
3
read-write
0
clock source from LIRC
#000
1
clock source from LXT.
clock source from HCLK.(default)
#001
2
clock source from HXT
#010
3
clock source from external pin (GPIOA[11])
#011
WDTSEL
WDT Clock Source Select
0
2
read-write
0
clock source from HIRC
#00
1
clock source from LXT
#01
2
clock source from HCLK/2048 clock
#10
3
clock source from LIRC.(default)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
I2S0SEL
I2S0 Clock Source Select
0
2
read-write
0
clock source from internal 10kHz oscillator.(default)
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK
#10
3
clock source from HIRC
#11
UART1DIV
UART1 Clock Divide Number From UART Clock Source
8
4
read-write
DBGPD
CLK_DBGPD
Debug Port Power Down Disable Register
0x28
-1
read-write
n
0x0
0x0
DISPDREQ
Disable Power Down
0
1
read-write
0
Enable power down requests
#0
1
Disable power down requests
#1
ICECLKST
ICECLKST Pin State
Read Only. Current state of ICE_CLK pin.
6
1
read-write
ICEDATST
ICEDATST Pin State
Read Only. Current state of ICE_DAT pin.
7
1
read-write
DPDSTATE
CLK_DPDSTATE
Deep Power Down State Register
0xC
-1
read-write
n
0x0
0x0
DPDSTSRD
DPD State Read Back
Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
8
8
read-write
DPDSTSWR
DPD State Write Register
Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
0
8
read-write
PWRCTL
CLK_PWRCTL
System Power Control Register
0x0
-1
read-write
n
0x0
0x0
DPDEN
Deep Power Down (DPD) Bit
Set to '1' and issue WFI/WFE instruction to enter DPD mode.
11
1
read-write
FLASHEN
Flash ROM Control Enable/Disable
Bit [19]: for Stop mode operation
Bit [18]: for Sleep mode operation
1: Turn off flash
0: Normal
Note: It takes 10us to turn on the flash to normal
18
2
read-write
HIRCEN
HIRC Oscillator Enable Bit
2
1
read-write
0
disable
#0
1
enable (default)
#1
HOLDIO
When entering SPD mode, IO state is automatically held If this bit is set to '1' then this sate upon resuming full power mode will be hold until the RELEASE_IO bit is written '1'
12
1
read-write
HXTEN
HXT Oscillator Enable Bit
4
1
read-write
0
disable (default)
#0
1
enable
#1
IOSTATE
'1': IO held from SPD '0': IO released.
14
1
read-write
LIRCDPDEN
OSC10k Enabled Control
Determines whether OSC10k is enabled in DPD mode. If OSC10k is disabled, device cannot wake from DPD with SELWKTMR delay.
17
1
read-write
0
enabled
#0
1
disabled
#1
LIRCEN
LIRC Oscillator Enable Bit
3
1
read-write
0
disable
#0
1
enable (default)
#1
LXTEN
External 32.768 KHz Crystal Enable Bit
1
1
read-write
0
disable (default)
#0
1
enable
#1
PORWKF
POR Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.
26
1
read-write
RELEASEIO
Write '1' to this bit to release IO state after exiting SPD if hold request was made with the HOLD_IO bit.
13
1
read-write
SPDEN
Standby Power Down (SPD) Bit
Set to '1' and issue WFI/WFE instruction to enter SPD mode.
10
1
read-write
STOPEN
Stop
Set to '1' and issue WFI/WFE instruction to enter STOP mode.
9
1
read-write
TMRWKF
Timer Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10khz oscillator. Flag is cleared when DPD mode is entered.
25
1
read-write
WKPINEN
Wakeup Pin Enabled Control
Determines whether WAKEUP pin is enabled in DPD mode.
16
1
read-write
0
enabled
#0
1
disabled
#1
WKPINWKF
Pin Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
24
1
read-write
WKPUEN
Wakeup Pin Pull-up Control
This signal is latched in deep power down and preserved.
27
1
read-write
0
pull-up enable
#0
1
tri-state (default)
#1
PWRSTSF
CLK_PWRSTSF
Power State Flag Register
0x24
-1
read-write
n
0x0
0x0
DSF
Deep Sleep Flag
This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
0
1
read-write
SPDF
Powered Down Flag
This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag.
2
1
read-write
STOPF
Stop Flag
This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
1
1
read-write
SLEEPCTL
CLK_SLEEPCTL
Sleep Clock Source Select Register
0x20
-1
read-write
n
0x0
0x0
ANACKEN
Analog Block Sleep Clock Enable Control
30
1
read-write
0
Disable
#0
1
Enable
#1
BIQALCKEN
BIQ and ALCSleep Clock Enable Control
18
1
read-write
0
Disable
#0
1
Enable
#1
DPWMCKEN
Differential PWM Speaker Driver Sleep Clock Enable Control
13
1
read-write
0
Disable
#0
1
Enable
#1
HCLKCKEN
CPU Clock Sleep Enable (HCLK)
Must be left as '1' for normal operation.
0
1
read-write
0
Disable
#0
1
Enable
#1
I2C0CKEN
I2C0 Sleep Clock Enable Control
8
1
read-write
0
Disable
#0
1
Enable
#1
I2SCKEN
I2S Sleep Clock Enable Control
29
1
read-write
0
Disable
#0
1
Enable
#1
ISPCKEN
Flash ISP Controller Sleep Clock Enable Control
2
1
read-write
0
Disable
#0
1
Enable
#1
PDMACKEN
PDMA Controller Sleep Clock Enable Control
1
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH01CKEN
PWM0CH0 and PWM0CH1 Block Sleep Clock Enable Control
20
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH23CKEN
PWM0CH2 and PWM0CH3 Block Sleep Clock Enable Control
21
1
read-write
0
Disable
#0
1
Enable
#1
RTCCKEN
Real-time- Sleep Clock APB Interface Clock Control
5
1
read-write
0
Disable
#0
1
Enable
#1
SARADCCKEN
SARADC Sleep Clock Enable Control
17
1
read-write
0
Disable
#0
1
Enable
#1
SDADCCKEN
Delta-Sigma Analog-digital-converter (ADC) Sleep Clock Enable Control
28
1
read-write
0
Disable
#0
1
Enable
#1
SPI0CKEN
SPI0 Sleep Clock Enable Control
12
1
read-write
0
Disable
#0
1
Enable
#1
SPI1CHEN
SPI1 Sleep Clock Enable Control
11
1
read-write
0
Disable
#0
1
Enable
#1
TMR0CKEN
Timer0 Sleep Clock Enable Control
6
1
read-write
0
Disable
#0
1
Enable
#1
TMR1CKEN
Timer1 Sleep Clock Enable Control
7
1
read-write
0
Disable
#0
1
Enable
#1
UART0CKEN
UART0 Sleep Clock Enable Control
16
1
read-write
0
Disable
#0
1
Enable
#1
UART1CKEN
UART1 Sleep Clock Enable Control
15
1
read-write
0
Disable
#0
1
Enable
#1
WDTCKEN
Watchdog Sleep Clock Enable Control
4
1
read-write
0
Disable
#0
1
Enable
#1
WAKE10K
CLK_WAKE10K
Deep Power Down 10K Wakeup Timer
0x2C
-1
read-write
n
0x0
0x0
SELWKTMR
Select Wakeup Timer
WAKEUP after 64* (SELWKTMR+1) OSC10k clocks (6.4 * (SELWKTMR+1) ms)
0
14
read-write
WAKE10KEN
Enable WAKE from DPD on 10kHz timer
31
1
read-write
WKTMRSTS
Current Wakeup Timer Setting
Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.
16
14
read-write
CSCAN
CSCAN Register Map
CSCAN
0x0
0x0
0x1C
registers
n
AGPIO
CSCAN_AGPIO
CSCAN Analog GPIO Function Register
0x10
-1
read-write
n
0x0
0x0
AGPIO
CSCAN AGPIO
If bit set to 1 then corresponding GPIOB[n] is forced to an analog mode where digital input, output and pullup is disabled. Can be used to set pad into analog mode for CapSensing, SAR ADC and OPAMP functions.
0
16
read-write
CMPCTL
CSCAN_CMPCTL
Comparator Control Register
0x18
-1
read-write
n
0x0
0x0
C1INTEN
Comparator 1 interrupt control
3
1
read-write
0
disable
#0
1
enable
#1
C1NSEL
Comparator 1 inverting input control
1
1
read-write
0
from VH0
#0
1
from C1N pin
#1
C1OUT
Comparator 1 Output.
Real time readback of comparator 1.
16
1
read-write
C1OUTEN
Comparator 1 output pin control bit
2
1
read-write
0
disable
#0
1
enable
#1
C2INTEN
Comparator 2 interrupt control
11
1
read-write
0
disable
#0
1
enable
#1
C2OUT
Comparator 2 Output.
Real time readback of comparator 2.
17
1
read-write
C2OUTEN
Comparator 2 output pin control bit
10
1
read-write
0
disable
#0
1
enable
#1
C2PSEL
Comparator 2 inverting input control
9
1
read-write
0
from VL0
#0
1
from C2P pin
#1
CMP1EN
Comparator 1 enable or disable control
0
1
read-write
0
disable
#0
1
enable
#1
CMP2EN
Comparator 2 enable or disable control
8
1
read-write
0
disable
#0
1
enable
#1
CMPES
Interrupt edge control bits
14
2
read-write
0
disable
#00
1
rising edge trigger
#01
2
falling edge trigger
#10
3
dual edge trigger
#11
CMP_INT
Comparator Interrupt.
Set by harddware.
Write 1 to clear.
4
1
read-write
CNPSEL
Comparator non-inverting input control
7
1
read-write
0
from OPA output
#0
1
from CNP pin
#1
LPWREN
Comparator Low power mode enable
If '1' comparator will remain enabled in STOP/SPD power modes.
24
1
read-write
COUNT
CSCAN_COUNT
CSCAN Count Status Register
0x8
-1
read-write
n
0x0
0x0
COUNT
CSCAN Count
Count result of single scan.
0
16
read-write
CTRL
CSCAN_CTRL
CSCAN Control Register
0x0
-1
read-write
n
0x0
0x0
CURRENT
CSCAN Oscillator current
Controls the analog bais current of the capacitive relaxation oscillator.
0:300nA 1:450nA 2:600nA 3:1200nA
16
2
read-write
DUR_CNT
CSCAN Duration Count
This counter is used to set a wakeup time after a capacitive sensing scan is complete. It is in units of low frewquency clock period (either LXT or LIRC clock) and gives delay of 160, 320, 480,640, 800, 960, 1120, 1280, 1440,1600, 1920, 2240, 2560, 2880,3200 3840 periods for settings 0,..,15.
24
4
read-write
EN
CSCAN Enable
Write 1 to start. Reset by hardware when operation finished.
30
1
read-write
INT_EN
CSCAN Enable Interrupt
20
1
read-write
0
Interrupt disabled
#0
1
Interrupt enabled
#1
MODE0
CSCAN Mode0
22
1
read-write
0
Single shot Capacitive sense
#0
1
Scans each channel set in SCAN_MASK and stores in RAM
#1
MODE1
CSCAN Mode1
23
1
read-write
0
Interrupt when scan finished
#0
1
Interrupt when DUR_CNT delay occurs
#1
PD
Power Down
0: Enable analog circuit
1: Power down analog circuit and block.
31
1
read-write
ReservedBIAS
CSCAN Comparator bias current
Controls the bais current of relaxation comparators. Suggest default 0. Can select lower for marginal power savings and less accuracy.
0:Normal 1:Half 3:Quarter
Keep with 0
18
2
read-write
SEL
CSCAN Select
In single mode selects the channel (GPIOB[15:0]) to perform measurement on.
0
16
read-write
SLOW_CLK
CSCAN Slow Clock
**Notes:
In low speed mode, for CYCLE_CNT <5, the minimum frequency of oscillation of a CAPSENSE GPIO must be > Fclk/2. Where Fclk is the frequency of LXT or LIRC depending which is selected as reference.
21
1
read-write
0
Timebase clock is HIRC
#0
1
Timebase clock is LIRC (XTAL32K_EN = 0) or XTAL (XTAL32K_EN = 1)
#1
CYCCNT
CSCAN_CYCCNT
CSCAN Cycle Count Control Register
0x4
-1
read-write
n
0x0
0x0
CYCLE_CNT
CSCAN Cycle Count
0
4
read-write
MASK
Scan Mask Register
If MASK[n] is set then GPIOB[n] is included in scan of capacitive sensing.
16
16
read-write
INT
CSCAN_INT
CSCAN Interrupt Register
0xC
-1
read-write
n
0x0
0x0
INT
CSCAN Interrupt active
Write '1' to clear.
0
1
read-write
OPACTL
CSCAN_OPACTL
Operational Amplifier Control Register
0x14
-1
read-write
n
0x0
0x0
A0EN
OPA0 Enable or Disable Control Bit
0
1
read-write
0
disable
#0
1
enable
#1
A0NS
A0N Pin to OPA0 Inverting Input Control Bit
2
1
read-write
0
no connection
#0
1
from A0N pin
#1
A0O2A1N
OPA0 Output to OPA0 Inverting Input Control Bit
23
1
read-write
0
disable
#0
1
enable
#1
A0O2A1P
OPA0 Output to OPA1 Non-inverting Input Control Bit
22
1
read-write
0
disable
#0
1
enable
#1
A0O2CIN
OPA0 output to comparator input control bit
25
1
read-write
0
disable
#0
1
enable
#1
A0O2N
OPA0 Output to OPA0 Inverting Input Control Bit
6
1
read-write
0
disable
#0
1
enable
#1
A0OEN
OPA0 Output Enable or Disable Control Bit
1
1
read-write
0
disable
#0
1
enable
#1
A0PS
A0P Pin to OPA0 Non-inverting Input Control Bit
3
1
read-write
0
no connection
#0
1
from A0P pin
#1
A0PSEL
OPA0 Non-inverting Input Selection Bit
4
2
read-write
0
no connection
#00
1
from VH1 (0.9×VDDA)
#01
2
from VM (0.5×VDDA)
#10
3
: from VL1 (0.1×VDDA)
#11
A0X
Operational amplifier 0 output positive logic This bit is read only
7
1
read-write
A102N
OPA1 Output to OPA1 Inverting Input Control Bit
14
1
read-write
0
disable
#0
1
enable
#1
A1EN
OPA1 Enable or Disable Control Bit
8
1
read-write
0
disable
#0
1
enable
#1
A1NS
A1N Pin to OPA1 Inverting Input Control Bit
10
1
read-write
0
no connection
#0
1
from A0N pin
#1
A1O2CIN
OPA1 output to comparator input control bit
26
1
read-write
0
disable
#0
1
enable
#1
A1OEN
OPA1 Output Enable or Disable Control Bit
9
1
read-write
0
disable
#0
1
enable
#1
A1PS
A1P Pin to OPA1 Non-inverting Input Control Bit
11
1
read-write
0
no connection
#0
1
from A0P pin
#1
A1PSEL
OPA1 Non-inverting Input Selection Bit
12
2
read-write
0
no connection
#00
1
from VH1 (0.9×VDDA)
#01
2
from VM (0.5×VDDA )
#10
3
: from VL1 (0.1×VDDA)
#11
A1X
Operational amplifier 1 output positive logic This bit is read only
15
1
read-write
LPWREN
Enable Opamps in STOP/SPD modes
24
1
read-write
0
disable
#0
1
enable
#1
PGA
OPA1 Gain Control Bits
16
3
read-write
0
1
#000
1
8
#001
2
16
#010
3
24
#011
4
32
#100
5
40
#101
6
48
#110
7
56
#111
PGAEN
OPA1 PGA Gain Enable Control Bits
19
1
read-write
0
disable
#0
1
Enable
#1
VREFEN
Enable OPA and Comparator Reference Voltage Generator
20
1
read-write
0
disable
#0
1
enable
#1
DPWM
DPWM Register Map
DPWM
0x0
0x0
0x14
registers
n
CTL
DPWM_CTL
DPWM Control Register
0x0
-1
read-write
n
0x0
0x0
DEADTIME
DPWM Driver DEADTIME Control.
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
3
1
read-write
DPWMEN
DPWM Enable
6
1
read-write
0
Disable DPWM
#0
1
Enable DPWM
#1
DWPMDRVEN
DPWM Driver Enable
7
1
read-write
0
Disable DPWM Driver
#0
1
Enable DPWM Diver
#1
FIFOWIDTH
DPWM FIFO DATA WIDTH SELETION From PDMA
0
2
read-write
0
PDMA MSB 24bits PWDATA[31:8]
#00
1
PDMA 16 bits PWDATA[15:0]
#01
2
PDMA 8bits PWDATA[7:0]
#10
3
PDMA 24bits PWDATA[23:0]
#11
ReservedMUTEEN
ReservedDPWM NOSIE REMOVER Enable (rev C still has problem)
10
1
read-write
0
turn off noise remover function
#0
1
turn on remover function
#1
ReservedMUTETM
ReservedDPWM MUTE Waite Time
8
2
read-write
0
mute afer 2^13 DPWM CLOCK cycle at MUTEEN = 1
#00
1
mute afer 2^14 DPWM CLOCK cycle at MUTEEN = 1
#01
2
mute afer 2^15 DPWM CLOCK cycle at MUTEEN = 1
#10
3
mute afer 2^16 DPWM CLOCK cycle at MUTEEN = 1
#11
RXTH
DPWM FIFO Threshold
If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHIF bit will set to 1, else the RXTHIF bit will be cleared to 0.
12
4
read-write
RXTHIE
DPWM FIFO Threshold Interrupt
11
1
read-write
0
DPWM FIFO threshold interrupt Disabled
#0
1
DPWM FIFO threshold interrupt Enabled
#1
DATA
DPWM_DATA
DPWM DATA FIFO Input
0xC
-1
write-only
n
0x0
0x0
INDATA
DPWM FIFO Audio Data Input
A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
0
32
write-only
DMACTL
DPWM_DMACTL
DPWM PDMA Control Register
0x8
-1
read-write
n
0x0
0x0
DMAEN
Enable DPWM DMA Interface
0
1
read-write
0
Disable PDMA. No requests will be made to PDMA controller
#0
1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
#1
STS
DPWM_STS
DPWM DATA FIFO Status Register
0x4
-1
read-only
n
0x0
0x0
BISTEN
BIST Enable
DPWM FIFO can be testing by Cortex-M0
Internal use
31
1
read-only
0
disable DPWM FIFO BIST testing
#0
1
enable DPWM FIFO BIST testing
#1
EMPTY
FIFO Empty
1
1
read-only
0
FIFO is not empty
#0
1
FIFO is empty
#1
FIFOPTR
DPWM FIFO Pointer (Read Only)
The FULL bit and FIFOPOINTER indicates the field that the valid data count within the DPWM FIFO buffer.
The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
4
4
read-only
FULL
FIFO Full
0
1
read-only
0
FIFO is not full
#0
1
FIFO is full
#1
RXTHIF
DPWM FIFO Threshold Interrupt Status (Read Only)
2
1
read-only
0
The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH
#1
ZOHDIV
DPWM_ZOHDIV
DPWM Zero Order Hold Division Register
0x10
-1
read-write
n
0x0
0x0
LVL
LVL controls the voltage output of the MICBIAS generator, voltages are encoded as following: 0 - 1.5V1 - 1.8V2 - 1.95V3 - 2.1V4 - 2.25V5 - 2.4V6 - 2.55V 7 - 2.7
Note: MICBIAS voltage should be at least 300mV lower than VCCA.
0
3
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x18
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address
This register reports the data flash starting address. It is a read only register.
Data flash size is defined by user configuration register content is loaded from Config1 when chip is reset.
0
32
read-only
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPADDR [1:0] must be 00b for correct ISP operation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP Command
Operation Mode : CMD
Standby : 0x3X
Read : 0x00
Program : 0x21
Page Erase : 0x22
Read CID : 0x0B
Read DID : 0x0C
0
6
read-write
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
APUWEN
APU Write Enable
3
1
read-write
0
APROM can't write itself. ISPFF with 1
#0
1
APROM write to itself
#1
BS
Boot Select
Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event.
1
1
read-write
0
APROM
#0
1
LDROM
#1
CACHEDIS
Cache Disable
When set to 1, caching of flash memory reads is disabled.
21
1
read-write
CFGUEN
CONFIG Update Enable
When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
4
1
read-write
0
Disable
#0
1
Enable
#1
ISPEN
ISP Enable
0
1
read-write
0
Disable ISP function
#0
1
Enable ISP function
#1
ISPFF
ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) Destination address is illegal, such as over an available range.
Write 1 to clear.
6
1
read-write
LDUEN
LDROM Update Enable
LDROM update enable bit.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data Register
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
0
32
read-write
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.
After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity.
This is a protected register, user must first follow the unlock sequence to gain access.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is on going
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x180
0x4
registers
n
0x40
0x24
registers
n
DBCTL
DBCTL
Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
DBCLKSRC
De-bounce Counter Clock Source Select
4
1
read-write
0
De-bounce counter clock source is HCLK
#0
1
De-bounce counter clock source is the internal 16 kHz clock
#1
ICLKON
Interrupt Clock on Mode
Set this bit 0 will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.
5
1
read-write
0
disable the clock if the GPIOx[n] interrupt is disabled
#0
1
Interrupt generation clock always active
#1
PA_DATMSK
PA_DATMSK
GPIO Port A Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK
Port [A/B] Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is writing protected.
0
16
read-write
0
The corresponding Px_DOUT[n] bit can be updated
0
1
The corresponding Px_DOUT[n] bit is read only
1
PA_DBEN
PA_DBEN
GPIO Port A De-bounce Enable
0x14
-1
read-write
n
0x0
0x0
DBEN
Port [A/B] De-bounce Enable Control
DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register.
The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
0
16
read-write
0
The bit[n] de-bounce function is disabled
0
1
The bit[n] de-bounce function is enabled
1
PA_DINOFF
PA_DINOFF
GPIO Port A Pin Input Disable
0x4
-1
read-write
n
0x0
0x0
DINOFF
GPIOx Pin[n] OFF Digital Input Path Enable
16
16
read-write
0
Enable IO digital input path (Default)
0
1
Disable IO digital input path (low leakage mode)
1
PA_DOUT
PA_DOUT
GPIO Port A Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Px Pin[n] Output Value
Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
0
16
read-write
0
GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set
0
1
GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set
1
PA_INTEN
PA_INTEN
GPIO Port A Interrupt Enable
0x1C
-1
read-write
n
0x0
0x0
FLIEN
Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low
FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level low will generate an interrupt.
If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt.
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
0
16
read-write
0
Disable GPIOx[n] for low-level or high-to-low interrupt
0
1
Enable GPIOx[n] for low-level or high-to-low interrupt
1
RHIEN
Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High
RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level high will generate an interrupt.
If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt.
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
16
16
read-write
0
Disable GPIOx[n] for level-high or low-to-high interrupt
0
1
Enable GPIOx[n] for level-high or low-to-high interrupt
1
PA_INTSRC
PA_INTSRC
GPIO Port A Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC
Port [A/B] Interrupt Source Flag
Read :
0
16
read-write
0
No interrupt from GPIOx[n].
No action
0
1
Indicates GPIOx[n] generated an interrupt.
Clear the corresponding pending interrupt
1
PA_INTTYPE
PA_INTTYPE
GPIO Port A Interrupt Trigger Type
0x18
-1
read-write
n
0x0
0x0
TYPE
Port [A/B] Edge or Level Detection Interrupt Trigger Type
TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt
If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur
0
16
read-write
0
Edge triggered interrupt
0
1
Level triggered interrupt
1
PA_MODE
PA_MODE
GPIO Port A Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
0
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE1
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
2
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE10
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
20
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE11
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
22
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE12
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
24
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE13
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
26
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE14
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
28
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE15
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
30
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE2
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
4
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE3
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
6
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE4
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
8
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE5
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
10
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE6
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
12
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE7
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
14
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE8
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
16
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE9
Px I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins
18
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
GPIO Port A Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN
Port [A/B] Pin Values
The value read from each of these bit reflects the actual status of the respective GPIO pin
0
16
read-only
PB_DATMSK
PB_DATMSK
GPIO Port B Data Output Write Mask
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
GPIO Port B De-bounce Enable
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
GPIO Port B Pin Input Disable
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
GPIO Port B Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
GPIO Port B Interrupt Enable
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
GPIO Port B Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
GPIO Port B Interrupt Trigger Type
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
GPIO Port B Pin I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
GPIO Port B Pin Value
0x50
-1
read-write
n
0x0
0x0
I2C
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address Register
The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched.
1
7
read-write
GC
General Call Function
0
1
read-write
0
Disable General Call Function
#0
1
Enable General Call Function
#1
ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
1
7
read-write
0
Mask disable
0
1
Mask enable (the received corresponding address bit is don't care.)
1
ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Register
0
8
read-write
CTL
I2C_CTL
I2C Control Register
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
2
1
read-write
I2CEN
I2C Controller Enable Bit
Set to enable I2C serial function block.
6
1
read-write
0
Disable
#0
1
Enable
#1
INTEN
Enable Interrupt
7
1
read-write
0
Disable interrupt
#0
1
Enable interrupt CPU
#1
SI
I2C Interrupt Flag
When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
3
1
read-write
STA
I2C START Control Bit
Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device.
4
1
read-write
DAT
I2C_DAT
I2C DATA Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data Register
During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
0
8
read-write
STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Register
The status register of I2C:
0
8
read-only
TOCTL
I2C_TOCTL
I2C Time Out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divide by 4
When enabled, the time-out clock is PCLK/4.
1
1
read-write
0
Disable
#0
1
Enable
#1
TOCEN
Time-out Counter Control Bit
When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disable
#0
1
Enable
#1
TOIF
Time-out Flag
0
1
read-write
0
No time-out
#0
1
Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear.
#1
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
CLKDIV
I2S_CLKDIV
I2S Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
If I2S operates in master mode, bit clock is provided by I91200. Software can program these bits to generate bit clock frequency for the desired sample rate.
For sample rate Fs, the desired bit clock frequency is:
8
8
read-write
MCLKDIV
Master Clock Divider
I91200can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLKDIV clock input, otherwise MCLK frequency is given by:
0
3
read-write
CTL
I2S_CTL
I2S Control Register
0x0
-1
read-write
n
0x0
0x0
FORMAT
Data Format
7
1
read-write
0
I2S data format
#0
1
MSB justified data format
#1
I2SEN
Enable I2S Controller
0
1
read-write
0
Disable
#0
1
Enable
#1
LZCEN
Left Channel Zero Cross Detect Enable
If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCIF flag in I2S_STATUS register will be set to 1.
17
1
read-write
0
Disable left channel zero cross detect
#0
1
Enable left channel zero cross detect
#1
MCLKEN
Master Clock Enable
The I91200can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the I2S_CLKDIV.MCLKDIV[2:0] register.
15
1
read-write
0
Disable master clock
#0
1
Enable master clock
#1
MONO
Monaural Data
This parameter sets whether mono or stereo data is processed. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable
3
1
read-write
0
Transmit data is shifted from FIFO
#0
1
Transmit channel zero
#1
RXCLR
Clear Receive FIFO
Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically when clear operation complete.
19
1
read-write
RXEN
Receive Enable
2
1
read-write
0
Disable data receive
#0
1
Enable data receive
#1
RXPDMAEN
Enable Receive DMA
When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
21
1
read-write
0
Disable RX DMA
#0
1
Enable RX DMA
#1
RXTH
Receive FIFO Threshold Level
When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set.
12
3
read-write
RZCEN
Right Channel Zero Cross Detect Enable
If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
16
1
read-write
0
Disable right channel zero cross detect
#0
1
Enable right channel zero cross detect
#1
SLAVE
Slave Mode
I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from I91200. In slave mode, I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXCLR
Clear Transmit FIFO
Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed.
This bit is cleared by hardware automatically when clear operation complete.
18
1
read-write
TXEN
Transmit Enable
1
1
read-write
0
Disable data transmit
#0
1
Enable data transmit
#1
TXPDMAEN
Enable Transmit DMA
When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
20
1
read-write
0
Disable TX DMA
#0
1
Enable TX DMA
#1
TXTH
Transmit FIFO Threshold Level
If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.
9
3
read-write
WDWIDTH
Word Width
This parameter sets the word width of audio data. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.
4
2
read-write
0
data is 8 bit
#00
1
data is 16 bit
#01
2
data is 24 bit
#10
3
data is 32 bit
#11
IEN
I2S_IEN
I2S Interrupt Enable Register
0x8
-1
read-write
n
0x0
0x0
LZCIEN
Left Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and left channel has zero cross event
12
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXOVIEN
Receive FIFO Overflow Interrupt Enable
1
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt
Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].
2
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXUDIEN
Receive FIFO Underflow Interrupt Enable
If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1.
0
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and right channel has zero cross event
11
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXOVIEN
Transmit FIFO Overflow Interrupt Enable
Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
9
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable
Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].
10
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXUDIEN
Transmit FIFO Underflow Interrupt Enable
Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
8
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RX
I2S_RX
I2S Receive FIFO Register
0x14
-1
read-only
n
0x0
0x0
RX
Receive FIFO Register (Read Only)
A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT.
0
32
read-only
STATUS
I2S_STATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SIF
I2S Interrupt (Read Only)
This bit is set if any enabled I2S interrupt is active.
0
1
read-only
0
No I2S interrupt
#0
1
I2S interrupt active
#1
LZCIF
Left Channel Zero Cross Flag (Write '1' to Clear, or Clear LZCEN)
23
1
read-write
0
No zero cross detected
#0
1
Left channel zero cross is detected
#1
RIGHT
Right Channel Active (Read Only)
This bit indicates current data being transmitted/received belongs to right channel
3
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Level (Read Only)
24
4
read-only
RXEMPTY
Receive FIFO Empty (Read Only)
This is set when receive FIFO is empty.
12
1
read-only
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full (Read Only)
This bit is set when receive FIFO is full.
11
1
read-only
0
Not full
#0
1
Full
#1
RXIF
I2S Receive Interrupt (Read Only)
This indicates that there is an active receive interrupt source. This could be RXOVIF, RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
1
1
read-only
0
No receive interrupt
#0
1
Receive interrupt occurred
#1
RXOVIF
Receive FIFO Overflow Flag (Write '1' to Clear)
This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.
9
1
read-write
0
No overflow
#0
1
Overflow
#1
RXTHIF
Receive FIFO Threshold Flag (Read Only)
When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.
10
1
read-only
0
Data word(s) in FIFO is less than threshold level
#0
1
Data word(s) in FIFO is greater than or equal to threshold level
#1
RXUDIF
Receive FIFO Underflow Flag (Write '1' to Clear)
This flag is set if attempt is made to read receive FIFO while it is empty.
8
1
read-write
0
No underflow
#0
1
Underflow
#1
RZCIF
Right Channel Zero Cross Flag (Write '1' to Clear, or Clear RZCEN)
22
1
read-write
0
No zero cross
#0
1
Right channel zero cross is detected
#1
TXBUSY
Transmit Busy (Read Only)
This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register.
21
1
read-only
0
Transmit shift register is empty
#0
1
Transmit shift register is busy
#1
TXCNT
Transmit FIFO Level (Read Only)
28
4
read-only
TXEMPTY
Transmit FIFO Empty (Read Only)
This is set when transmit FIFO is empty.
20
1
read-only
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full (Read Only)
This bit is set when transmit FIFO is full.
19
1
read-only
0
Not full
#0
1
Full
#1
TXIF
I2S Transmit Interrupt (Read Only)
This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
2
1
read-only
0
No transmit interrupt
#0
1
Transmit interrupt occurred
#1
TXOVIF
Transmit FIFO Overflow Flag (Write '1' to Clear)
This flag is set if data is written to transmit FIFO when it is full.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Flag (Read Only)
When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold exceeded.
18
1
read-only
0
Data word(s) in FIFO is greater than threshold level
#0
1
Data word(s) in FIFO is less than or equal to threshold level
#1
TXUDIF
Transmit FIFO Underflow Flag (Write '1' to Clear)
This flag is set if I2S controller requests data when transmit FIFO is empty.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX
I2S_TX
I2S Transmit FIFO Register
0x10
-1
write-only
n
0x0
0x0
TX
Transmit FIFO Register (Write Only)
A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT.
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity Register
0x0
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (Reserved) Interrupt Source Identity Register
0x28
-1
read-only
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
IRQ11 (UART1) Interrupt Source Identity Register
0x2C
-1
read-only
n
0x0
0x0
INTSRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART1 INT
0
3
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) Interrupt Source Identity Register
0x30
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART0_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (SPI1) Interrupt Source Identity Register
0x34
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI1 INT
0
3
read-only
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) Interrupt Source Identity Register
0x38
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
0
3
read-only
IRQ15_SRC
IRQ15_SRC
IRQ15 (DPWM) Interrupt Source Identity Register
0x3C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1:
Bit0: DPWM INT
0
3
read-only
IRQ16_SRC
IRQ16_SRC
IRQ16 (Reserved) Interrupt Source Identity Register
0x40
-1
read-only
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (Reserved) Interrupt Source Identity Register
0x44
-1
read-only
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity Register
0x48
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2C0_INT
0
3
read-only
IRQ19_SRC
IRQ19_SRC
IRQ19 (Reserved) Interrupt Source Identity Register
0x4C
-1
read-only
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity Register
0x4
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
0
3
read-only
IRQ20_SRC
IRQ20_SRC
IRQ20 (Reserved) Interrupt Source Identity Register
0x50
-1
read-only
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
IRQ21 (CMP) Interrupt Source Identity Register
0x54
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: CMP INT
0
3
read-only
IRQ22_SRC
IRQ22_SRC
IRQ22 (MAC ) Interrupt Source Identity Register
0x58
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: MAC INT
0
3
read-only
IRQ23_SRC
IRQ23_SRC
IRQ23 (Reserved) Interrupt Source Identity Register
0x5C
-1
read-only
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
IRQ24 (Reserved) Interrupt Source Identity Register
0x60
-1
read-only
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (SARADC) Interrupt Source Identity Register
0x64
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SARADC INT
0
3
read-only
IRQ26_SRC
IRQ26_SRC
IRQ26 (PDMA) Interrupt Source Identity Register
0x68
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
0
3
read-only
IRQ27_SRC
IRQ27_SRC
IRQ27 (I2S0) Interrupt Source Identity Register
0x6C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2S_INT
0
3
read-only
IRQ28_SRC
IRQ28_SRC
IRQ28 (CAPS) Interrupt Source Identity Register
0x70
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: CAPS_INT
0
3
read-only
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity Register
0x74
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity Register
0x8
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
0
3
read-only
IRQ30_SRC
IRQ30_SRC
IRQ30 (Reserved) Interrupt Source Identity Register
0x78
-1
read-only
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
IRQ31 (RTC) Interrupt Source Identity Register
0x7C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
0
3
read-only
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity Register
0xC
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
0
3
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (GPA/B) Interrupt Source Identity Register
0x10
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (ALC) Interrupt Source Identity Register
0x14
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ALC_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWM0) Interrupt Source Identity Register
0x18
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM_INT
0
3
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (Reserved) Interrupt Source Identity Register
0x1C
-1
read-only
n
0x0
0x0
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity Register
0x20
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR0_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity Register
0x24
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR1_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identify Register
0x84
-1
read-write
n
0x0
0x0
ALC
IRQ5 (ALC) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
5
1
read-write
BOD
IRQ0 (BOD) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
0
1
read-write
CAPS
IRQ28 (CAPS) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
28
1
read-write
CMP
IRQ21 (CMP) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
21
1
read-write
DPWM
IRQ15 (DPWM) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
15
1
read-write
EINT0
IRQ2 (EINT0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
2
1
read-write
EINT1
IRQ3 (EINT1) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
3
1
read-write
GPAB
IRQ4 (GPA/B) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
4
1
read-write
I2C
IRQ18 (I2C0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
18
1
read-write
I2S
IRQ27 (I2S0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
27
1
read-write
MAC
IRQ22 (MAC ) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
22
1
read-write
PDMA
IRQ26 (PDMA) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
26
1
read-write
PWM
IRQ6 (PWM0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
6
1
read-write
RTC
IRQ31 (RTC) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
31
1
read-write
SARADC
IRQ25 (SARADC) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
25
1
read-write
SDADC
IRQ29 (SDADC) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
29
1
read-write
SPI0
IRQ14 (SPI0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
14
1
read-write
SPI1
IRQ13 (SPI1) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
13
1
read-write
TMR0
IRQ8 (TMR0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
8
1
read-write
TMR1
RQ9 (TMR1) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
9
1
read-write
UART0
IRQ12 (UART0) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
12
1
read-write
UART1
IRQ11 (UART1) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
11
1
read-write
WDT
IRQ1 (WDT) Interrupt Source Identity Register
0: No effect.
1: clear the interrupt
1
1
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
-1
read-write
n
0x0
0x0
IRQ_TM
IRQ Test Mode
If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence.
7
1
read-write
NMI_SEL
NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
The NMI_SEL bit[4:0] used to select the NMI interrupt source
0
5
read-write
PDMA0
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x34
0x8
registers
n
PDMA_CTLn
PDMA_CTLn
PDMA Control Register of Channel n
0x0
-1
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
0
1
read-write
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped
#11
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped
#11
SWRST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TXEN
Trigger Enable - Start a PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
TXWIDTH
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
WAINTSEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_CURDADDRn
PDMA_CURDADDRn
PDMA Current Destination Address Register of Channel n
0x18
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring.
This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSADDRn
PDMA_CURSADDRn
PDMA Current Source Address Register of Channel n
0x14
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring.
This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSPANn
PDMA_CURSPANn
PDMA Current Span Increment Register of Channel n
0x38
-1
read-write
n
0x0
0x0
SPAN
Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode.
0
8
read-write
PDMA_CURTXCNTn
PDMA_CURTXCNTn
PDMA Current Transfer Byte Count Register of Channel n
0x1C
-1
read-only
n
0x0
0x0
CNT
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_DADDRn
PDMA_DADDRn
PDMA Transfer Destination Address Register of Channel n
0x8
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_INTENn
PDMA_INTENn
PDMA Interrupt Enable Control Register of Channel n
0x20
-1
read-write
n
0x0
0x0
ABTIEN
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
TXIEN
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
WRAPIEN
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_INTPNTn
PDMA_INTPNTn
PDMA Internal Buffer Pointer Register of Channel n
0x10
-1
read-only
n
0x0
0x0
POINTER
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_INTSTSn
PDMA_INTSTSn
PDMA Interrupt Status Register of Channel n
0x24
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TXIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
WRAPIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (PDMA_CURTXCNT == 0)
#0001
4
Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT /2)
#0100
PDMA_SADDRn
PDMA_SADDRn
PDMA Transfer Source Address Register of Channel n
0x4
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_SPANn
PDMA_SPANn
PDMA Span Increment Register of Channel n
0x34
-1
read-only
n
0x0
0x0
SPAN
Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPAN may be a negative number.
0
8
read-only
PDMA_TXCNTn
PDMA_TXCNTn
PDMA Transfer Byte Count Register of Channel n
0xC
-1
read-write
n
0x0
0x0
CNT
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA1
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x34
0x8
registers
n
PDMA_CTLn
PDMA_CTLn
PDMA Control Register of Channel n
0x0
-1
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
0
1
read-write
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped
#11
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped
#11
SWRST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TXEN
Trigger Enable - Start a PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
TXWIDTH
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
WAINTSEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_CURDADDRn
PDMA_CURDADDRn
PDMA Current Destination Address Register of Channel n
0x18
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring.
This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSADDRn
PDMA_CURSADDRn
PDMA Current Source Address Register of Channel n
0x14
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring.
This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSPANn
PDMA_CURSPANn
PDMA Current Span Increment Register of Channel n
0x38
-1
read-write
n
0x0
0x0
SPAN
Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode.
0
8
read-write
PDMA_CURTXCNTn
PDMA_CURTXCNTn
PDMA Current Transfer Byte Count Register of Channel n
0x1C
-1
read-only
n
0x0
0x0
CNT
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_DADDRn
PDMA_DADDRn
PDMA Transfer Destination Address Register of Channel n
0x8
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_INTENn
PDMA_INTENn
PDMA Interrupt Enable Control Register of Channel n
0x20
-1
read-write
n
0x0
0x0
ABTIEN
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
TXIEN
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
WRAPIEN
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_INTPNTn
PDMA_INTPNTn
PDMA Internal Buffer Pointer Register of Channel n
0x10
-1
read-only
n
0x0
0x0
POINTER
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_INTSTSn
PDMA_INTSTSn
PDMA Interrupt Status Register of Channel n
0x24
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TXIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
WRAPIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (PDMA_CURTXCNT == 0)
#0001
4
Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT /2)
#0100
PDMA_SADDRn
PDMA_SADDRn
PDMA Transfer Source Address Register of Channel n
0x4
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_SPANn
PDMA_SPANn
PDMA Span Increment Register of Channel n
0x34
-1
read-only
n
0x0
0x0
SPAN
Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPAN may be a negative number.
0
8
read-only
PDMA_TXCNTn
PDMA_TXCNTn
PDMA Transfer Byte Count Register of Channel n
0xC
-1
read-write
n
0x0
0x0
CNT
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA2
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x34
0x8
registers
n
PDMA_CTLn
PDMA_CTLn
PDMA Control Register of Channel n
0x0
-1
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
0
1
read-write
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped
#11
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped
#11
SWRST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TXEN
Trigger Enable - Start a PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
TXWIDTH
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
WAINTSEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_CURDADDRn
PDMA_CURDADDRn
PDMA Current Destination Address Register of Channel n
0x18
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring.
This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSADDRn
PDMA_CURSADDRn
PDMA Current Source Address Register of Channel n
0x14
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring.
This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSPANn
PDMA_CURSPANn
PDMA Current Span Increment Register of Channel n
0x38
-1
read-write
n
0x0
0x0
SPAN
Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode.
0
8
read-write
PDMA_CURTXCNTn
PDMA_CURTXCNTn
PDMA Current Transfer Byte Count Register of Channel n
0x1C
-1
read-only
n
0x0
0x0
CNT
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_DADDRn
PDMA_DADDRn
PDMA Transfer Destination Address Register of Channel n
0x8
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_INTENn
PDMA_INTENn
PDMA Interrupt Enable Control Register of Channel n
0x20
-1
read-write
n
0x0
0x0
ABTIEN
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
TXIEN
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
WRAPIEN
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_INTPNTn
PDMA_INTPNTn
PDMA Internal Buffer Pointer Register of Channel n
0x10
-1
read-only
n
0x0
0x0
POINTER
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_INTSTSn
PDMA_INTSTSn
PDMA Interrupt Status Register of Channel n
0x24
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TXIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
WRAPIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (PDMA_CURTXCNT == 0)
#0001
4
Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT /2)
#0100
PDMA_SADDRn
PDMA_SADDRn
PDMA Transfer Source Address Register of Channel n
0x4
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_SPANn
PDMA_SPANn
PDMA Span Increment Register of Channel n
0x34
-1
read-only
n
0x0
0x0
SPAN
Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPAN may be a negative number.
0
8
read-only
PDMA_TXCNTn
PDMA_TXCNTn
PDMA Transfer Byte Count Register of Channel n
0xC
-1
read-write
n
0x0
0x0
CNT
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA3
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x34
0x8
registers
n
PDMA_CTLn
PDMA_CTLn
PDMA Control Register of Channel n
0x0
-1
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
0
1
read-write
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
Reserved
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped
#11
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.
4
2
read-write
0
Transfer Source address is incremented
#00
1
Reserved
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped
#11
SWRST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TXEN
Trigger Enable - Start a PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
TXWIDTH
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
Reserved
#11
WAINTSEL
Wrap Interrupt Select
x1x1: Both half and w interrupts generated.
12
4
read-write
PDMA_CURDADDRn
PDMA_CURDADDRn
PDMA Current Destination Address Register of Channel n
0x18
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring.
This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSADDRn
PDMA_CURSADDRn
PDMA Current Source Address Register of Channel n
0x14
-1
read-only
n
0x0
0x0
ADDR
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring.
This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs.
0
32
read-only
PDMA_CURSPANn
PDMA_CURSPANn
PDMA Current Span Increment Register of Channel n
0x38
-1
read-write
n
0x0
0x0
SPAN
Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode.
0
8
read-write
PDMA_CURTXCNTn
PDMA_CURTXCNTn
PDMA Current Transfer Byte Count Register of Channel n
0x1C
-1
read-only
n
0x0
0x0
CNT
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs
0
16
read-only
PDMA_DADDRn
PDMA_DADDRn
PDMA Transfer Destination Address Register of Channel n
0x8
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
PDMA_INTENn
PDMA_INTENn
PDMA Interrupt Enable Control Register of Channel n
0x20
-1
read-write
n
0x0
0x0
ABTIEN
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
TXIEN
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
WRAPIEN
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
PDMA_INTPNTn
PDMA_INTPNTn
PDMA Internal Buffer Pointer Register of Channel n
0x10
-1
read-only
n
0x0
0x0
POINTER
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
PDMA_INTSTSn
PDMA_INTSTSn
PDMA Interrupt Status Register of Channel n
0x24
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TXIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
WRAPIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
8
4
read-write
1
Current transfer finished flag (PDMA_CURTXCNT == 0)
#0001
4
Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT /2)
#0100
PDMA_SADDRn
PDMA_SADDRn
PDMA Transfer Source Address Register of Channel n
0x4
-1
read-write
n
0x0
0x0
ADDR
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
PDMA_SPANn
PDMA_SPANn
PDMA Span Increment Register of Channel n
0x34
-1
read-only
n
0x0
0x0
SPAN
Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPAN may be a negative number.
0
8
read-only
PDMA_TXCNTn
PDMA_TXCNTn
PDMA Transfer Byte Count Register of Channel n
0xC
-1
read-write
n
0x0
0x0
CNT
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
0
16
read-write
PDMA_GCR
PDMA Register Map
PDMA
0x0
0x0
0x10
registers
n
PDMA_GCTL
PDMA_GCTL
PDMA Global Control Register
0x0
-1
read-write
n
0x0
0x0
CH0CKEN
PDMA Controller Channel 0 Clock Enable Control
1: Enable Channel 0 clock.
0: Disable Channel 0 clock.
8
1
read-write
CH1CKEN
PDMA Controller Channel 1 Clock Enable Control
1: Enable Channel 1 clock.
0: Disable Channel 1 clock.
9
1
read-write
CH2CKEN
PDMA Controller Channel 2 Clock Enable Control
1: Enable Channel 2 clock.
0: Disable Channel 2 clock.
10
1
read-write
CH3CKEN
PDMA Controller Channel 3 Clock Enable Control
1: Enable Channel 3 clock.
0: Disable Channel 3 clock.
11
1
read-write
SWRST
PDMA Software Reset
Note: This bit can reset all channels (global reset).
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles
#1
PDMA_GINTSTS
PDMA_GINTSTS
PDMA Global Interrupt Status Register
0xC
-1
read-only
n
0x0
0x0
CH0INTSTS
Interrupt Pin Status of Channel 0 (Read Only)
This bit is the interrupt pin status of PDMA channel 0.
0
1
read-only
CH1INTSTS
Interrupt Pin Status of Channel 1 (Read Only)
This bit is the interrupt pin status of PDMA channel 1.
1
1
read-only
CH2INTSTS
Interrupt Pin Status of Channel 2 (Read Only)
This bit is the interrupt pin status of PDMA channel 2.
2
1
read-only
CH3INTSTS
Interrupt Pin Status of Channel 3 (Read Only)
This bit is the interrupt pin status of PDMA channel 3.
3
1
read-only
PDMA_SVCSEL0
PDMA_SVCSEL0
PDMA Service Selection Control Register 0
0x4
-1
read-write
n
0x0
0x0
DPWMTXSEL
PDMA DPWM Transmit Selection
This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
12
4
read-write
I2SRXSEL
PDMA I2S Receive Selection
This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request.
24
4
read-write
I2STXSEL
PDMA I2S Transmit Selection
This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request.
28
4
read-write
SDADCRXSEL
PDMA SDADC Receive Selection
This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request.
8
4
read-write
SPI0RXSEL
PDMA SPI0 Receive Selection
This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
0
4
read-write
SPI0TXSEL
PDMA SPI0 Transmit Selection
This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
4
4
read-write
UART0RXSEL
PDMA UART0 Receive Selection
This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request.
16
4
read-write
UART0XSEL
PDMA UART0 Transmit Selection
This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request.
20
4
read-write
PDMA_SVCSEL1
PDMA_SVCSEL1
PDMA Service Selection Control Register 1
0x8
-1
read-write
n
0x0
0x0
SARADCRXSEL
PDMA SARADC Receive Selection
This field defines which PDMA channel is connected to SARADC peripheral receive (PDMA source) request.
16
4
read-write
SPI1RXSEL
PDMA SPI1 Receive Selection
This field defines which PDMA channel is connected to SPI1 peripheral receive (PDMA source) request.
8
4
read-write
SPI1TXSEL
PDMA SPI1 Transmit Selection
This field defines which PDMA channel is connected to SPI1 peripheral transmit (PDMA destination) request.
12
4
read-write
UART1RXSEL
PDMA UART1 Receive Selection
This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request.
0
4
read-write
UART1XSEL
PDMA UART1 Transmit Selection
This field defines which PDMA channel is connected to UART1 peripheral transmit (PDMA destination) request.
4
4
read-write
PWM
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x30
registers
n
CAPCTL01
PWM_CAPCTL01
Capture Control Register for Pair of PWM0CH0 and PWM0CH1
0x50
-1
read-write
n
0x0
0x0
CAPEN0
Capture Channel 0 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function on channel 0
#0
1
Enable capture function on channel 0
#1
CAPEN1
Capture Channel 1 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
19
1
read-write
0
Disable capture function on channel 1
#0
1
Enable capture function on channel 1
#1
CAPIF0
Capture0 Interrupt Indication Flag
4
1
read-write
CAPIF1
Capture1 Interrupt Indication Flag
20
1
read-write
CAPINV0
Channel 0 Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CAPINV1
Channel 1 Inverter ON/OFF
16
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CFLIEN0
Channel 0 Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIEN1
Channel 1 Falling Latch Interrupt Enable
When enabled, capture block generates an interrupt on falling edge of input.
18
1
read-write
0
Disable falling edge latch interrupt
#0
1
Enable falling edge latch interrupt
#1
CFLIF0
PWM_FCAPDAT0 Latched Indicator Bit
When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CFLIF1
PWM_FCAPDAT1 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
23
1
read-write
CRLIEN0
Channel 0 Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIEN1
Channel 1 Rising Latch Interrupt Enable
When enabled, capture block generates an interrupt on rising edge of input.
17
1
read-write
0
Disable rising edge latch interrupt
#0
1
Enable rising edge latch interrupt
#1
CRLIF0
PWM_RCAPDAT0 Latched Indicator Bit
When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CRLIF1
PWM_RCAPDAT1 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
22
1
read-write
CAPCTL23
PWM_CAPCTL23
Capture Control Register for Pair of PWM0CH2 and PWM0CH3
0x54
-1
read-write
n
0x0
0x0
CAPEN2
Capture Channel 2 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function on channel 0
#0
1
Enable capture function on channel 0
#1
CAPEN3
Capture Channel 3 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
19
1
read-write
0
Disable capture function on channel 1
#0
1
Enable capture function on channel 1
#1
CAPIF2
Capture2 Interrupt Indication Flag
4
1
read-write
CAPIF3
Capture3 Interrupt Indication Flag
20
1
read-write
CAPINV2
Channel 2 Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CAPINV3
Channel 3 Inverter ON/OFF
16
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CFLIEN2
Channel 2 Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIEN3
Channel 3 Falling Latch Interrupt Enable
When enabled, capture block generates an interrupt on falling edge of input.
18
1
read-write
0
Disable falling edge latch interrupt
#0
1
Enable falling edge latch interrupt
#1
CFLIF2
PWM_FCAPDAT2 Latched Indicator Bit
When input channel 2 has a falling transition, PWM_FCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CFLIF3
PWM_FCAPDAT3 Latched Indicator Bit
When input channel 3 has a falling transition, PWM_FCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
23
1
read-write
CRLIEN2
Channel 2 Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIEN3
Channel 3 Rising Latch Interrupt Enable
When enabled, capture block generates an interrupt on rising edge of input.
17
1
read-write
0
Disable rising edge latch interrupt
#0
1
Enable rising edge latch interrupt
#1
CRLIF2
PWM_RCAPDAT2 Latched Indicator Bit
When input channel 2 has a rising transition, PWM_RCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CRLIF3
PWM_RCAPDAT3 Latched Indicator Bit
When input channel 3 has a rising transition, PWM_RCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
22
1
read-write
CAPINEN
PWM_CAPINEN
Capture Input Enable Register
0x78
-1
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Register
0 : OFF (GPA[13:12], GPB[15:14] pin input disconnected from Capture block)
1 : ON (GPA[13:12] , GPB[15:14] pin, if in PWM alternative function, will be configured as an input and fed to capture function)
CAPINEN[3:0]
Bit [3][2][1][0]
Bit xxx1 : Capture channel 0 is from GPA [12]
Bit xx1x : Capture channel 1 is from GPA [13]
Bit x1xx : Capture channel 2 is from GPB [14]
Bit 1xxx : Capture channel 3 is from GPB [15]
0
4
read-write
CLKDIV
PWM_CLKDIV
PWM Clock Select Register
0x4
-1
read-write
n
0x0
0x0
CLKDIV0
Timer 0 Clock Source Selection
Value : Input clock divided by
0 : 2
1 : 4
2 : 8
3 : 16
4 : 1
0
3
read-write
CLKDIV1
Timer 1 Clock Source Selection
(Table is as CLKDIV0)
4
3
read-write
CLKDIV2
Timer 2 Clock Source Selection
(Table is as CLKDIV0)
8
3
read-write
CLKDIV3
Timer 3 Clock Source Selection
(Table is as CLKDIV0)
12
3
read-write
CLKPSC
PWM_CLKPSC
PWM Prescaler Register
0x0
-1
read-write
n
0x0
0x0
CLKPSC01
Clock Pre-scaler Pair of PWM0CH0 and PWM0CH1
Clock input is divided by (CLKPSC01 + 1)
This implies PWM counter 0 and 1 will also be stopped.
0
8
read-write
CLKPSC23
Clock Pre-scaler for Pair of PWM0CH2 and PWM0CH3
Clock input is divided by (CLKPSC23 + 1)
This implies PWM counter 2 and 3 will also be stopped.
8
8
read-write
DTCNT01
Dead Zone Interval Register for Pair of PWM0CH0 and PWM0CH1
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector 0.
16
8
read-write
DTCNT23
Dead Zone Interval Register for Pair of PWM0CH2 and PWM0CH3
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector 0.
24
8
read-write
CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x10
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP determines the PWM duty cycle.
Note: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x1C
-1
read-write
n
0x0
0x0
CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x28
-1
read-write
n
0x0
0x0
CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x34
-1
read-write
n
0x0
0x0
CNT0
PWM_CNT0
PWM Data Register 0
0x14
-1
read-only
n
0x0
0x0
CNT
PWM Data Register
Reports the current value of the 16-bit down counter.
0
16
read-only
CNT1
PWM_CNT1
PWM Data Register 1
0x20
-1
read-write
n
0x0
0x0
CNT2
PWM_CNT2
PWM Data Register 2
0x2C
-1
read-write
n
0x0
0x0
CNT3
PWM_CNT3
PWM Data Register 3
0x38
-1
read-write
n
0x0
0x0
CTL
PWM_CTL
PWM Control Register
0x8
-1
read-write
n
0x0
0x0
CNTEN0
PWM-timer 0 Enable/Disable Start Run
0
1
read-write
0
Stop PWM-Timer 0 Running
#0
1
Enable PWM-Timer 0 Start/Run
#1
CNTEN1
PWM-timer 1 Enable/Disable Start Run
8
1
read-write
0
Stop PWM-Timer 1
#0
1
Enable PWM-Timer 1 Start/Run
#1
CNTEN2
PWM-timer 2 Enable/Disable Start Run
16
1
read-write
0
Stop PWM-Timer 2
#0
1
Enable PWM-Timer 2 Start/Run
#1
CNTEN3
PWM-timer 3 Enable/Disable Start Run
24
1
read-write
0
Stop PWM-Timer 3
#0
1
Enable PWM-Timer 3 Start/Run
#1
CNTMODE0
PWM-timer 0 Auto-reload/One-shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared.
3
1
read-write
0
One-Shot Mode
#0
1
Auto-reload Mode
#1
CNTMODE1
PWM-timer 1 Auto-reload/One-shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared.
11
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
CNTMODE2
PWM-timer 2 Auto-reload/One-shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD2 and PWM_CMPDAT2 to be cleared.
19
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
CNTMODE3
PWM-timer 3 Auto-reload/One-shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared.
27
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
DTEN01
Dead-zone 01 Generator Enable/Disable Pair of PWM0CH0 and PWM0CH1
Note: When Dead-Zone Generator is enabled, the pair of PWM0CH0 and PWM0CH1 become a complementary pair.
4
1
read-write
0
Disable
#0
1
Enable
#1
DTEN23
Dead-zone 23 Generator Enable/Disable Pair of PWM0CH2 and PWM0CH3
Note: When Dead-Zone Generator is enabled, the pair of PWM0CH2 and PWM0CH3 become a complementary pair.
5
1
read-write
0
Disable
#0
1
Enable
#1
PINV0
PWM-timer 0 Output Inverter ON/OFF
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV1
PWM-timer 1 Output Inverter ON/OFF
10
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV2
PWM-timer 2 Output Inverter ON/OFF
18
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV3
PWM-timer 3 Output Inverter ON/OFF
26
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
FCAPDAT0
PWM_FCAPDAT0
Capture Falling Latch Register (Channel 0)
0x5C
-1
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
0
16
read-only
FCAPDAT1
PWM_FCAPDAT1
Capture Falling Latch Register (Channel 1)
0x64
-1
read-write
n
0x0
0x0
FCAPDAT2
PWM_FCAPDAT2
Capture Falling Latch Register (Channel 2)
0x6C
-1
read-write
n
0x0
0x0
FCAPDAT3
PWM_FCAPDAT3
Capture Falling Latch Register (Channel 3)
0x74
-1
read-write
n
0x0
0x0
INTEN
PWM_INTEN
PWM Interrupt Enable Register
0x40
-1
read-write
n
0x0
0x0
PIEN0
PWM Timer 0 Interrupt Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
PIEN1
PWM Timer 1 Interrupt Enable
1
1
read-write
0
Disable
#0
1
Enable
#1
PIEN2
PWM Timer 2 Interrupt Enable
2
1
read-write
0
Disable
#0
1
Enable
#1
PIEN3
PWM Timer 3 Interrupt Enable
3
1
read-write
0
Disable
#0
1
Enable
#1
INTSTS
PWM_INTSTS
PWM Interrupt Flag Register
0x44
-1
read-write
n
0x0
0x0
PIF0
PWM Timer 0 Interrupt Flag
Flag is set by hardware when PWM0CH0 down counter reaches zero, software can clear this bit by writing '1' to it.
0
1
read-write
PIF1
PWM Timer 1 Interrupt Flag
Flag is set by hardware when PWM0CH1 down counter reaches zero, software can clear this bit by writing '1' to it.
1
1
read-write
PIF2
PWM Timer 2 Interrupt Flag
Flag is set by hardware when PWM0CH2 down counter reaches zero, software can clear this bit by writing '1' to it.
2
1
read-write
PIF3
PWM Timer 3 Interrupt Flag
Flag is set by hardware when PWM0CH3 down counter reaches zero, software can clear this bit by writing '1' to it.
3
1
read-write
PERIOD0
PWM_PERIOD0
PWM Counter Register 0
0xC
-1
read-write
n
0x0
0x0
PERIOD
PWM Counter/Timer Reload Value
PERIOD determines the PWM period.
Note:
Any write to PERIOD will take effect in next PWM cycle.
0
16
read-write
PERIOD1
PWM_PERIOD1
PWM Counter Register 1
0x18
-1
read-write
n
0x0
0x0
PERIOD2
PWM_PERIOD2
PWM Counter Register 2
0x24
-1
read-write
n
0x0
0x0
PERIOD3
PWM_PERIOD3
PWM Counter Register 3
0x30
-1
read-write
n
0x0
0x0
POEN
PWM_POEN
PWM0 Output Enable Register for CH0~CH3
0x7C
-1
read-write
n
0x0
0x0
POEN0
PWM0CH0 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
0
1
read-write
0
Disable PWM0CH0 output to pin
#0
1
Enable PWM0CH 0 output to pin
#1
POEN1
PWM0CH1 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
1
1
read-write
0
Disable PWM0CH1 output to pin
#0
1
Enable PWM0CH1 output to pin
#1
POEN2
PWM0CH2 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
2
1
read-write
0
Disable PWM0CH2 output to pin
#0
1
Enable PWM0CH2 output to pin
#1
POEN3
PWM0CH3 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
3
1
read-write
0
Disable PWM0CH3 output to pin
#0
1
Enable PWM0CH3 output to pin
#1
RCAPDAT0
PWM_RCAPDAT0
Capture Rising Latch Register (Channel 0)
0x58
-1
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
0
16
read-only
RCAPDAT1
PWM_RCAPDAT1
Capture Rising Latch Register (Channel 1)
0x60
-1
read-write
n
0x0
0x0
RCAPDAT2
PWM_RCAPDAT2
Capture Rising Latch Register (Channel 2)
0x68
-1
read-write
n
0x0
0x0
RCAPDAT3
PWM_RCAPDAT3
Capture Rising Latch Register (Channel 3)
0x70
-1
read-write
n
0x0
0x0
RTC
RTC Register Map
RTC
0x0
0x0
0x34
registers
n
CAL
RTC_CAL
Calendar Load Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
Calendar Alarm Register
0x20
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CLKFMT
RTC_CLKFMT
Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-hour / 12-hour Mode Selection
Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode
The range of 24-hour time scale is between 0 and 23.
12-hour time scale:
01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06)
07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12)
21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06)
27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12)
0
1
read-write
0
select 12-hour time scale with AM and PM indication
#0
1
select 24-hour time scale
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fractional Part
Refer to Table 576 RTC Frequency Compensation Example for the examples.
0
6
read-write
INTEGER
Integer Part
Register should contain the value (INT(Factual) - 32761)
The range between 32761 and 32776
8
4
read-write
INIT
RTC_INIT
RTC Initialization Register
0x0
-1
read-write
n
0x0
0x0
ATVSTS
RTC Active Status (Read Only)
0: RTC is in reset state
1: RTC is in normal active state.
0
1
read-only
INIT
RTC Initialization
After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIT. This will force a hardware reset then release all logic and counters.
1
31
read-write
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
-1
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable
0
1
read-write
0
RTC Alarm Interrupt is disabled
#0
1
RTC Alarm Interrupt is enabled
#1
TICKIEN
Time-tick Interrupt and Wakeup-by-tick Enable
1
1
read-write
0
RTC Time-Tick Interrupt is disabled
#0
1
RTC Time-Tick Interrupt is enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Indicator Register
0x2C
-1
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag
0
1
read-write
0
Indicates no Alarm Interrupt condition
#0
1
Indicates RTC Alarm Interrupt generated
#1
TICKIF
RTC Time-tick Interrupt Flag
1
1
read-write
0
Indicates no Time-Tick Interrupt condition
#0
1
Indicates RTC Time-Tick Interrupt generated
#1
LEAPYEAR
RTC_LEAPYEAR
Leap Year Indicator Register
0x24
-1
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication Register (Read Only)
0
1
read-only
0
Current year is not a leap year
#0
1
Current year is leap year
#1
RWEN
RTC_RWEN
RTC Access Enable Register
0x4
-1
read-write
n
0x0
0x0
RWEN
RTC Register Access Enable Password (Write Only)
0
16
write-only
43365
Enable RTC acces..s
0xa965
RWENF
RTC Register Access Enable Flag (Read Only)
RTC_INIT : R/W : R/W
RTC_FREQADJ : R/W : -
RTC_TIME : R/W : R
RTC_CAL : R/W : R
RTC_CLKFMT : R/W : R/W
RTC_WEEKDAY : R/W : R
RTC_TALM : R/W : -
RTC_CALM : R/W : -
RTC_LEAPYEAR : R : R
RTC_INTEN : R/W : R/W
RTC_INTSTS : R/W : R/W
RTC_TICK : R/W : -
16
1
read-only
0
RTC register read/write disable
#0
1
RTC register read/write enable
#1
TALM
RTC_TALM
Time Alarm Register
0x1C
-1
read-write
n
0x0
0x0
HR
1 Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1 Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1 Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10 Hour Time Digit of Alarm Setting (0~3)2
20
2
read-write
TENMIN
10 Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10 Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
-1
read-write
n
0x0
0x0
TICKSEL
Time Tick Period Select
The RTC time tick period for Periodic Time-Tick Interrupt request.
Time Tick (second) : 1 / (2^TTR)
Note: This register can be read back after the RTC is active.
0
3
read-write
TWKEN
RTC Timer Wakeup CPU Function Enable Bit
If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up.
3
1
read-write
0
Disable Wakeup CPU function
#0
1
Enable the Wakeup function
#1
TIME
RTC_TIME
Time Load Register
0xC
-1
read-write
n
0x0
0x0
HR
1 Hour Time Digit (0~9)
16
4
read-write
MIN
1 Min Time Digit (0~9)
8
4
read-write
SEC
1 Sec Time Digit (0~9)
0
4
read-write
TENHR
10 Hour Time Digit (0~3)
20
2
read-write
TENMIN
10 Min Time Digit (0~5)
12
3
read-write
TENSEC
10 Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register
0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday)
4 (Thursday), 5 (Friday), 6 (Saturday)
0
3
read-write
SARADC
SARADC Register Map
SARADC
0x0
0x0
0x30
registers
n
0x40
0x4
registers
n
0x50
0x4
registers
n
0x5C
0x14
registers
n
ACTL
SARADC_ACTL
SAR ADC Analog Control Register
0x5C
-1
read-write
n
0x0
0x0
ReservedSAR_cur
ReservedSAR current
0 --- low bias current for comparator
1 --- high bias current for comparator
17
1
read-write
ReservedSAR_VCMsel
ReservedSAR VCM voltage
0---- select internal VCM
1 --- select external VCM
16
1
read-write
SAR_SE_MODE
SE mode selection
0
1
read-write
1
SARADC in single ended mode
#1
SAR_VREF
VREF selection
0 -- select VCCA as VREF
1 -- select MICBIAS as VREF
18
1
read-write
CHEN
SARADC_CHEN
SAR ADC Channel Enable Register
0x64
-1
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable Bit
Set CHEN[11:0] to enable the corresponding analog input channel 11 ~ 0.
Note: Keep 0 for [15:12]
0
16
read-write
0
SARADC input channel Disabled
0
1
SARADC input channel Enabled
1
ReservedDIFFCHEN
ReservedDifferencial channel mask enable
20
4
read-write
ReservedSAR_Vref_sel
ReservedAnalog reference voltage
0 --- use input [15] Note: no MUX selection to input[15] for user
1 ---- measure voltage on vref_bandgap instead of voltage on input [15]
16
1
read-write
CMP0
SARADC_CMP0
SAR ADC Compare Register 0
0x68
-1
read-write
n
0x0
0x0
ADCMPEN
Compare Enable Bit
Note: Set this bit to 1 to enable SARADC controller to compare CMPDAT[11:0] with specified channel conversion result when converted data is loaded into DAT register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
ADCMPIE
Compare Interrupt Enable Bit
Note: If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPF bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPCH
Compare Channel Selection
3
4
read-write
0
Channel 0 conversion result is selected to be compared
#0000
1
Channel 1 conversion result is selected to be compared
#0001
2
Channel 2 conversion result is selected to be compared
#0010
3
Channel 3 conversion result is selected to be compared
#0011
4
Channel 4 conversion result is selected to be compared
#0100
5
Channel 5 conversion result is selected to be compared
#0101
6
Channel 6 conversion result is selected to be compared
#0110
7
Channel 7 conversion result is selected to be compared
#0111
8
Channel 8 conversion result is selected to be compared
#1000
9
Channel 9 conversion result is selected to be compared
#1001
10
Channel 10 conversion result is selected to be compared
#1010
11
Channel 11 conversion result is selected to be compared
#1011
12
Reserved
#1100
13
Reserved
#1101
14
Reserved
#1110
15
Reserved
#1111
CMPCOND
Compare Condition
Note: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (CMPx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (CMPx[27:16]), the internal match counter will increase one
#1
CMPDAT
Comparison Data
The 12-bit data is used to compare with conversion result of specified channel.
When ADCFMbit is set to 0, SARADC comparator compares CMPDAT with conversion result with unsigned format. CMPDAT should be filled in unsigned format.
When ADCFMbit is set to 1, SARADC comparator compares CMPDAT with conversion result with 2'complement format. CMPDAT should be filled in 2'complement format.
16
12
read-write
CMPMCNT
Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
8
4
read-write
CMP1
SARADC_CMP1
SAR ADC Compare Register 1
0x6C
-1
read-write
n
0x0
0x0
CTL
SARADC_CTL
SAR ADC Control Register
0x60
-1
read-write
n
0x0
0x0
ADCEN
A/D Converter Enable Bit
Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADCIE
A/D Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
HWTRGCOND
External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
HWTRGEN
Hardware Trigger Enable Bit
Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).
SARADC hardware trigger function is only supported in single-cycle scan mode.
If hardware trigger mode, the SWTRG bit can be set to 1 by the selected hardware trigger source.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
HWTRGSEL
Hardware Trigger Source Selection
Software should disable TRGEN and SWTRG before change HWTRGSEL.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
OPMODE
A/D Converter Operation Mode
When changing the operation mode, software should disable SWTRG bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
PDMAEN
PDMA Transfer Enable Bit
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in DAT 0~11 Enabled
#1
SWTRG
A/D Conversion Start
SWTRG bit can be set to 1 from three sources: software, external pin STADC. SWTRG will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
11
1
read-write
0
Conversion stops and A/D converter enter idle state
#0
1
Conversion starts
#1
DAT0
SARADC_DAT0
SAR ADC Data Register 0
0x0
-1
read-only
n
0x0
0x0
OV
Overrun Flag (Read Only)
Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read.
16
1
read-only
0
Data in RESULT[11:0] is recent conversion result
#0
1
Data in RESULT[11:0] is overwritten
#1
RESULT
A/D Conversion Result
This field contains conversion result of SARADC.
12-bit SARADC conversion result with unsigned format.
0
12
read-only
VALID
Valid Flag (Read Only)
Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read.
17
1
read-only
0
Data in RESULT[11:0] bits is not valid
#0
1
Data in RESULT[11:0] bits is valid
#1
DAT1
SARADC_DAT1
SAR ADC Data Register 1
0x4
-1
read-write
n
0x0
0x0
DAT10
SARADC_DAT10
SAR ADC Data Register 10
0x28
-1
read-write
n
0x0
0x0
DAT11
SARADC_DAT11
SAR ADC Data Register 11
0x2C
-1
read-write
n
0x0
0x0
DAT2
SARADC_DAT2
SAR ADC Data Register 2
0x8
-1
read-write
n
0x0
0x0
DAT3
SARADC_DAT3
SAR ADC Data Register 3
0xC
-1
read-write
n
0x0
0x0
DAT4
SARADC_DAT4
SAR ADC Data Register 4
0x10
-1
read-write
n
0x0
0x0
DAT5
SARADC_DAT5
SAR ADC Data Register 5
0x14
-1
read-write
n
0x0
0x0
DAT6
SARADC_DAT6
SAR ADC Data Register 6
0x18
-1
read-write
n
0x0
0x0
DAT7
SARADC_DAT7
SAR ADC Data Register 7
0x1C
-1
read-write
n
0x0
0x0
DAT8
SARADC_DAT8
SAR ADC Data Register 8
0x20
-1
read-write
n
0x0
0x0
DAT9
SARADC_DAT9
SAR ADC Data Register 9
0x24
-1
read-write
n
0x0
0x0
PDMADAT
SARADC_PDMADAT
SAR ADC PDMA Current Transfer Data
0x50
-1
read-only
n
0x0
0x0
DATA
SAR ADC PDMA Current Transfer Data Register (Read Only)
When PDMA transferring, read this register can monitor current PDMA transfer data.
Current PDMA transfer data is the content of DAT0 ~ DAT11.
0
18
read-only
STATUS
SARADC_STATUS
SAR ADC Status Register
0x40
-1
read-write
n
0x0
0x0
ADCMPF0
Compare Flag
When the selected channel A/D conversion result meets setting condition in SARADC_CMP0 then this bit is set to 1. And it is cleared by writing 1 to self.
1
1
read-write
0
Conversion result in DAT register does not meet CMP0 register
#0
1
Conversion result in DAT register meets CMP0 register
#1
ADCMPF1
Compare Flag
When the selected channel A/D conversion result meets setting condition in SARADC_CMP1 then this bit is set to 1. And it is cleared by writing 1 to self.
2
1
read-write
0
Conversion result in DAT register does not meet CMP1 register
#0
1
Conversion result in DAT register meets CMP1 register
#1
ADEF
A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADEF is set to 1 at these two conditions:
1. When A/D conversion ends in Single mode.
2. When A/D conversion ends on all specified channels in Scan mode.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)
This bit is mirror of as SWTRG bit in CTL.
3
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
4
4
read-only
VALID
Data Valid Flag (Read Only)
It is a mirror of VALID bit in DATx.
8
16
read-only
SCS
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x300
0x20
registers
n
0x80
0x4
registers
n
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
-1
read-write
n
0x0
0x0
CLRENA
Clear-enable Control
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will disable the associated interrupt.
Writing 0 has no effect.
The register reads back with the current enable state.
0
32
read-write
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
-1
read-write
n
0x0
0x0
CLRPEND
Clear-pending Control
Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 0 has no effect.
The register reads back with the current pending state.
0
32
read-write
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x300
-1
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_1
Priority of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_2
Priority of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_3
Priority of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x304
-1
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_5
Priority of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_6
Priority of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_7
Priority of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x308
-1
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_11
Priority of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
PRI_8
Priority of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_9
Priority of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x30C
-1
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x310
-1
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_17
Priority of IRQ17
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_18
Priority of IRQ18
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_19
Priority of IRQ19
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x314
-1
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_21
Priority of IRQ21
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_22
Priority of IRQ22
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_23
Priority of IRQ23
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x318
-1
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_25
Priority of IRQ25
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_26
Priority of IRQ26
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_27
Priority of IRQ27
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x31C
-1
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_29
Priority of IRQ29
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_30
Priority of IRQ30
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_31
Priority of IRQ31
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
-1
read-write
n
0x0
0x0
SETENA
Set-enable Control
Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will enable the associated interrupt.
Writing 0 has no effect.
The register reads back the current enable state.
0
32
read-write
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
-1
read-write
n
0x0
0x0
SETPEND
Set-pending Control
Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 0 has no effect.
The register reads back with the current pending state.
0
32
read-write
SDADC
SDADC Register Map
SDADC
0x0
0x0
0x2C
registers
n
BS_BANDGPLDO
BS_BANDGPLDO
Bridge Sense Bandgap and LDO Control Register
0x24
-1
read-write
n
0x0
0x0
BCHOPEN
BS Bandgap chopper enable
2
1
read-write
0
disable
#0
1
enable
#1
BCHOPLFEN
BS Bandgap low frequency chopper enable
3
1
read-write
0
disable
#0
1
enable
#1
BCHOPPH
BS Bandgap chopper phase
When chopper is off
8
1
read-write
0
chopper switches in default state
#0
1
invert chopper switches
#1
BFLTCHRG
BS Bandgap filter charge
1
1
read-write
0
high impedance mode (low noise)
#0
1
quick charge external capacitor
#1
BGCCDIVF
BS Bandgap Lf chopper frequency selection
9
2
read-write
0
1024
#00
1
512
#01
2
256
#10
3
128
#11
BGEN
BS Bandgap enable
0
1
read-write
0
disable
#0
1
enable
#1
BTRIM
BS Bandgap TRIM
4
4
read-write
0
bandgap +0
#0000
1
bandgap+(1*12)mV
#0001
2
bandgap+(2*12)mV
#0010
3
bandgap+(3*12)mV
#0011
4
bandgap+(4*12)mV
#0100
5
bandgap+(5*12)mV
#0101
6
bandgap+(6*12)mV
#0110
7
bandgap+(7*12)mV
#0111
8
bandgap-(8*12)mV
#1000
9
bandgap-(7*12)mV
#1001
10
bandgap-(6*12)mV
#1010
11
bandgap-(5*12)mV
#1011
12
bandgap-(4*12)mV
#1100
13
bandgap-(3*12)mV
#1101
14
bandgap-(2*12)mV
#1110
15
bandgap-(1*12)mV
#1111
CLKDIV
Bridge Sense clock divider for 400KHz
ADC_CLK /(2*400K)
24
7
read-write
CLKEN
Bridge Sense clock enable for 400KHz, 200KHz and 160Hz
31
1
read-write
0
disable
#0
1
enable
#1
DISCHRG
BS LDO Discharge
13
1
read-write
0
disable
#0
1
enable
#1
DIVEN
BS LDO Voltage Divider Enable
14
1
read-write
0
disable
#0
1
enable
#1
LDOEN
BS LDO(Bridge Bias) Enable
12
1
read-write
0
disable
#0
1
enable
#1
LDOSET
BS set LDO output voltage
16
4
read-write
0
1.5
#0000
1
1.8
#0001
2
2.1
#0010
3
2.4
#0011
4
2.7
#0100
5
3.0
#0101
6
3.3
#0110
7
3.6
#0111
8
3.9
#1000
9
4.2
#1001
10
4.5
#1010
BS_INSTRAMP
BS_INSTRAMP
Bridge Sense Instrumentation Amplifer Control Register
0x28
-1
read-write
n
0x0
0x0
CHOPEN
BS Instrumentation Amplifer chopper enable
18
1
read-write
0
disable choppers in the three opamps
#0
1
enable choppers in the three opamps
#1
CHOPF
BS Instrumentation Amplifer chopper frequency selection
26
2
read-write
0
100kHz
#00
1
200kHz
#01
2
50kHz
#10
3
25kHz
#11
CHOPNDIS
BS Instrumentation Amplifer chopper negative disable
When OFFSETTRIM bit is high
21
1
read-write
0
Enable chopper in negative input opamp
#0
1
disable chopper in negative input opamp
#1
CHOPNPH
BS Instrumentation Amplifer chopper phase negative input opamp
When chopper is off or when OFFSETTRIM bit is high
23
1
read-write
0
chopper switches in negative input opamp in default state
#0
1
invert chopper switches in negative input opamp
#1
CHOPOPH
BS Instrumentation Amplifer chopper phase output opamp
When chopper is off
25
1
read-write
0
chopper switches in output opamp in default state
#0
1
invert chopper switches in output opamp
#1
CHOPPDIS
BS Instrumentation Amplifer chopper positive disable
When OFFSETTRIM bit is high
22
1
read-write
0
Enable chopper in positive input opamp
#0
1
disable chopper in positive input opamp
#1
CHOPPPH
BS Instrumentation Amplifer chopper phase positive input opamp
When chopper is off or when OFFSETTRIM bit is high
24
1
read-write
0
chopper switches in positive input opamp in default state
#0
1
invert chopper switches in positive input opamp
#1
EN
BS Instrumentation Amplifer enable
0
1
read-write
0
Disable
#0
1
Enable
#1
GAIN
BS Instrumentation Amplifer GAIN
1
3
read-write
0
1
#000
1
2
#001
2
4
#010
3
8
#011
4
16
#100
5
32
#101
6
64
#110
7
128
#111
OFFSETN
BS Instrumentation Amplifer offset negetive input opamp
4
6
read-write
OFFSETNEN
BS Instrumentation Amplifer offset negetvie input opamp enable
10
1
read-write
0
don't use bits [9:4]
#0
1
use value of bits [9:4] to change offset of positive input opamp
#1
OFFSETP
BS Instrumentation Amplifer offset positive input opamp
12
6
read-write
OFFSETPEN
BS Instrumentation Amplifer offset positive input opamp enable
11
1
read-write
0
don't use bits [17:12]
#0
1
use value of bits [17:12] to change offset of positive input opamp
#1
OFFSETTRIM
BS Instrumentation Amplifer offset trim mode
20
1
read-write
0
disable offset trim mode
#0
1
enable offset trim mode
#1
SCHOPF
BS Instrumentation Amplifer System chopper frequency
28
2
read-write
0
40Hz
#00
1
80Hz
#01
2
20Hz
#10
3
10Hz
#11
SCHOPPH
BS Instrumentation Amplifer System chopper phase
When system chopper is off
30
1
read-write
0
system chopper switches in default state
#0
1
invert system chopper switches
#1
SYSCHOPEN
BS Instrumentation Amplifer system chopper enable
19
1
read-write
0
disable system chopper
#0
1
enable system chopper
#1
CLKDIV
SDADC_CLKDIV
SD ADC Clock Divider Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
SD_CLK Clock Divider
SDADC internal clock divider. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. (Refer to 7.1.4.2.)
CLKDIV must be greater than and equal 2.
0
8
read-write
CMPR0
SDADC_CMPR0
SD ADC Comparator 0 Control Register
0x18
-1
read-write
n
0x0
0x0
CMPCOND
Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
2
1
read-write
0
Set the compare condition that result is less than CMPD
#0
1
Set the compare condition that result is greater or equal to CMPD
#1
CMPD
Comparison Data
23 bit value to compare to FIFO output word.
8
23
read-write
CMPF
Compare Flag
When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.
3
1
read-write
CMPIE
Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable compare function interrupt
#0
1
Enable compare function interrupt
#1
CMPMATCNT
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
4
4
read-write
CMPOEN
Compare Match output FIFO zero
31
1
read-write
0
FIFO data keep original one
#0
1
compare match then FIFO out zero
#1
CMPR1
SDADC_CMPR1
SD ADC Comparator 1 Control Register
0x1C
-1
read-write
n
0x0
0x0
CMPCOND
Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
2
1
read-write
0
Set the compare condition that result is less than CMPD
#0
1
Set the compare condition that result is greater or equal to CMPD
#1
CMPD
Comparison Data
23 bit value to compare to FIFO output word.
8
23
read-write
CMPF
Compare Flag
When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.
3
1
read-write
CMPIE
Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable compare function interrupt
#0
1
Enable compare function interrupt
#1
CMPMATCNT
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
4
4
read-write
CMPOEN
Compare Match output FIFO zero
31
1
read-write
0
FIFO data keep original one
#0
1
compare match then FIFO out zero
#1
CTL
SDADC_CTL
SD ADC Control Register
0xC
-1
read-write
n
0x0
0x0
DMICEN
Digital MIC Enable
8
1
read-write
0
keep SDADC function
#0
1
turn digital MIC function input from GPIO
#1
DSRATE
Down Sampling Ratio
0
2
read-write
0
reserved
0
1
down sample X 16
1
2
down sample X 32
2
3
down sample X 64
3
FIFOBITS
FIFO Data Bits Selection
2
2
read-write
0
32 bits
0
1
16 bits
1
2
8 bits
2
3
24 bits
3
FIFOTH
FIFO Threshold:
Determines at what level the ADC FIFO will generate a interrupt.
Interrupt will be generated when number of words present in ADC FIFO is >
FIFOTH.
4
3
read-write
FIFOTHIE
FIFO Threshold Interrupt Enable
7
1
read-write
0
disable interrupt whenever FIFO level exceeds that set in FIFOTH
#0
1
enable interrupt whenever FIFO level exceeds that set in FIFOTH
#1
RATESEL
Sample Rate Selection
11
1
read-write
0
choose DSRATE for SDADC
#0
1
choose BSRATE for BS
#1
ReservedBSRATE
Down Sampling for BS
9
2
read-write
0
down sample 2000 for SPS384
#00
1
down sampel 4000(reserved)
#01
2
down sample 8000(reserved)
#10
3
down sample 16000 for SPS9.6,SPS19.2,SPS38.4 and SPS76.8Reserved
#11
DAT
SDADC_DAT
SD ADC FIFO Data Read Register
0x0
-1
read-only
n
0x0
0x0
RESULT
Delta-Sigma ADC DATA FIFO Read
A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with SDADC_FIFOSTS.THIF to determine if valid data is present in FIFO.
0
16
read-only
EN
SDADC_EN
SD ADC Enable Register
0x4
-1
read-write
n
0x0
0x0
DINBYPS
ADC data input bypass (internal debug)
2
1
read-write
0
normal mode
#0
1
analog 5bits to FIFO for testing
#1
DINEDGE
ADC data input clock edge selection
1
1
read-write
0
ADC clock negetive edge latch
#0
1
ADC clock positive edge latch
#1
SDADCEN
SDADC Enable
0
1
read-write
0
Conversion stopped and ADC is reset including FIFO pointers
#0
1
ADC Conversion enabled
#1
FIFOSTS
SDADC_FIFOSTS
SD ADC FIFO Status Register
0x10
-1
read-write
n
0x0
0x0
BISTEN
BIST Enable
Internal use
31
1
read-write
0
Disable SDADC FIFO BIST testing
#0
1
Enable SDADC FIFO BIST testing SDADC FIFO can be testing by Cortex-M0
#1
EMPTY
FIFO Empty
1
1
read-write
0
FIFO is not empty
#0
1
FIFO is empty
#1
FULL
FIFO Full
0
1
read-write
0
FIFO is not full
#0
1
FIFO is full
#1
POINTER
SDADC FIFO Pointer (Read Only)
The FULL bit and POINTER[3:0] indicates the field that the valid data count within the SDADC FIFO buffer.
The Maximum value shown in POINTER is 15. When the using level of SDADC FIFO Buffer equal to 16, The FULL bit is set to 1.
4
4
read-only
THIF
ADC FIFO Threshold Interrupt Status (Read Only)
2
1
read-only
0
The valid data count within the transmit FIFO buffer is less than to the setting value of FIFOTH
#0
1
The valid data count within the SDADC FIFO buffer is larger than or equal the setting value of FIFOTH
#1
PDMACTL
SDADC_PDMACTL
SD ADC PDMA Control Register
0x14
-1
read-write
n
0x0
0x0
PDMAEN
Enable SDADC PDMA Receive Channel
0
1
read-write
0
Disable SDADC PDMA
#0
1
Enable SDADC PDMA
#1
SDCHOP
SDADC_SDCHOP
Sigma Delta Analog Block Control Register
0x20
-1
read-write
n
0x0
0x0
AUDIOPATHSEL
Audio Path Selection, Connect SDADC input to
30
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Bridge Sense
#10
3
Reserved
#11
BIAS
SDADC Bias Current Selection
1
2
read-write
0
1
#00
1
0.75
#01
2
0.5
#10
3
1.25
#11
CHOPCLKPH
SDADC Chopper Clock phase selection
25
1
read-write
0
chopper transition after falling edge of ADC_CLK (default)
#0
1
chopper transition after rising edge of ADC_CLK
#1
CHOPEN
SDADC chopper enable
29
1
read-write
0
disable (default)
#0
1
enable
#1
CHOPF
SDADC Chopper Frequency in fixed chop mode
23
2
read-write
0
Fs/2 (default)
#00
1
Fs/4
#01
2
Fs/8
#10
3
Fs/16
#11
CHOPFIX
SDADC Chopper Fixed Frequency
26
1
read-write
0
dither chopper frequency (default)
#0
1
choose fixed frequency
#1
CHOPORD
SDADC Chopper Order
27
1
read-write
0
1st order dithering of chopper frequency (default)
#0
1
2nd order dithering of chopper frequency
#1
CHOPPH
SDADC chopper phase
When chopper is off:
28
1
read-write
0
chopper switches in default state
#0
1
invert chopper switches
#1
PD
SDADC Power Down
0
1
read-write
0
SDADC power on
#0
1
SDADC power off
#1
PGA_ADCDC
21
2
read-write
0
Default
#00
PGA_CLASSA
Enable Class A mode of operation
18
1
read-write
0
Class AB
#0
1
Class A (default)
#1
PGA_CMLCK
Common mode Threshold lock adjust enable
15
1
read-write
0
Enable
#0
1
Disable
#1
PGA_CMLCKADJ
16
2
read-write
PGA_DISCH
Charge inputs selected by PGA_ACDC[1:0] to VREF
14
1
read-write
0
Disable
#0
1
Enable
#1
PGA_GAIN
13
1
read-write
PGA_HZMODE
Select input impedance
20
1
read-write
0
12k Ohm input impedance
#0
1
500k Ohm input impedance (default)
#1
PGA_IBCTR
Trim PGA Current
9
3
read-write
0
default
0
PGA_IBLOOP
Trim PGA current
12
1
read-write
1
default
#1
PGA_MODE
PGA mode selection
6
3
read-write
0
Disable
0
1
Enable
1
PGA_MUTE
Mute control signal
0—disable
1—enable
5
1
read-write
PGA_PU
Power up PGA
0—disable
1—enable
4
1
read-write
PGA_TRIMOBC
Trim current in output driver
19
1
read-write
0
disable
#0
1
enable (default)
#1
VREF
SDADC Chopper in Reference Buffer
3
1
read-write
0
chopper off
#0
1
chopper on
#1
SPI0
SPI Register Map
SPI
0x0
0x0
0x1C
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x50
0x4
registers
n
CLKDIV
SPI0_CLKDIV
Clock Divider Register (Master Only)
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation.
where
Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control, CLKSEL1 register.
0
8
read-write
CTL
SPI0_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SCLK idle low
#0
1
SCLK idle high
#1
DUALIOEN
Dual I/O Mode Enable
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
DWIDTH - Data Word Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
8
5
read-write
LSB
LSB First
Note:
For DUAL and QUAD transactions with LSB must be set to 0.
13
1
read-write
0
The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field)
#0
1
The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX)
#1
QDIODIR
Quad or Dual I/O Mode Direction Control
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable
Note:
Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
REORDER is only available for Receive mode in DUAL and QUAD transactions.
For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXMODEEN
FIFO Receive Mode Enable
24
1
read-write
0
Disable function
#0
1
Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0
#1
RXNEG
Receive at Negative Edge
1
1
read-write
0
The received data input signal is latched at the rising edge of SCLK
#0
1
The received data input signal is latched at the falling edge of SCLK
#1
RXTCNTEN
DMA Receive Transaction Count Enable
23
1
read-write
0
Disable function
#0
1
Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI0_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller
#1
SLAVE
Master Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Enable
In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to 1.
Note:
All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG, RXNEG, DWIDTH, LSB, CLKP, and so on).
0
1
read-write
0
Disable SPI Transfer
#0
1
Enable SPI Transfer
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and QUAD mode transactions.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
Note:
For DUAL and QUAD transactions with SUSPITV must be set to 0.
4
4
read-write
TWOBIT
Two Bits Transfer Mode
When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
Disable two-bit transfer mode
#0
1
Enable two-bit transfer mode
#1
TXNEG
Transmit at Negative Edge
2
1
read-write
0
The transmitted data output signal is changed at the rising edge of SCLK
#0
1
The transmitted data output signal is changed at the falling edge of SCLK
#1
UNITIEN
Unit Transfer Interrupt Enable
17
1
read-write
0
Disable SPI Unit Transfer Interrupt
#0
1
Enable SPI Unit Transfer Interrupt to CPU
#1
FIFOCTL
SPI0_FIFOCTL
FIFO Control/Status Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Clear Receive FIFO Buffer
Note: If there is slave receive time out event, the RXRST will be set 1 when the SPI0_SSCTL.SLVTORST, is enabled.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
00: 1 word will transmit
01: 2 word will transmit
10: 3 word will transmit
11: 4 word will transmit
24
2
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Clear Transmit FIFO Buffer
Note: If there is slave receive time out event, the TXRST will be set 1 when the SPI0_SSCTL.SLVTORST, is enabled.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
00: 1 word will transmit
01: 2 word will transmit
10: 3 word will transmit
11: 4 word will transmit
28
2
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUDFIEN
Slave Transmit Under Run Interrupt Enable
7
1
read-write
0
Slave Transmit FIFO under-run interrupt Disabled
#0
1
Slave Transmit FIFO under-run interrupt Enabled
#1
TXUDFPOL
Transmit Under-run Data Out
Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.
Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time to report the transmit under-run data out.
6
1
read-write
0
The SPI data out is 0 if there is transmit under-run event in Slave mode
#0
1
The SPI data out is 1 if there is transmit under-run event in Slave mode
#1
PDMACTL
SPI0_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RXPDMAEN
Receive PDMA Enable
Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
1
1
read-write
TXPDMAEN
Transmit DMA Enable
Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.
0
1
read-write
RX
SPI0_RX
FIFO Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI0_STATUS. RXEMPTY bit is not set to 1. This is a read-only register.
0
32
read-only
RXTSNCNT
SPI0_RXTSNCNT
Receive Transaction Count Register
0x18
-1
read-write
n
0x0
0x0
RXTSNCNT
DMA Receive Transaction Count
When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI0_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate.
0
17
read-write
SSCTL
SPI0_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI0_SSCTL[1:0]
#0
1
If this bit is set, SPI0_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI0_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
SLV3WIRE
Slave 3-wire Mode Enable
This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
4
1
read-write
0
4-wire bi-directional interface
#0
1
3-wire bi-directional interface
#1
SLVBCEIEN
Slave Mode Error 0 Interrupt Enable
8
1
read-write
0
Slave mode error 0 interrupt Disable
#0
1
Slave mode error 0 interrupt Enable
#1
SLVTOCNT
Slave Mode Time-out Period
In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out FIFO Clear
6
1
read-write
0
Function disabled
#0
1
Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event
#1
SLVUDRIEN
Slave Mode Error 1 Interrupt Enable
9
1
read-write
0
Slave mode error 1 interrupt Disable
#0
1
Slave mode error 1 interrupt Enable
#1
SS
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI0_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPI0_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI0_SS0/1 is specified in SSACTPOL.
Note: SPI0_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SSACTIEN
Slave Select Active Interrupt Enable
12
1
read-write
0
Slave select active interrupt Disable
#0
1
Slave select active interrupt Enable
#1
SSACTPOL
Slave Select Active Level
This bit defines the active status of slave select signal (SPI0_SS0/1).
2
1
read-write
0
The slave select signal SPI0_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI0_SS0/1 is active on high-level/rising-edge
#1
SSINAIEN
Slave Select Inactive Interrupt Enable
13
1
read-write
0
Slave select inactive interrupt Disable
#0
1
Slave select inactive interrupt Enable
#1
STATUS
SPI0_STATUS
Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
SPI Unit Bus Status (Read Only)
0
1
read-only
0
No transaction in the SPI bus
#0
1
SPI controller unit is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to itself.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)
10
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Error 0 Interrupt Status (Read Only)
In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.
6
1
read-only
0
No Slave mode error 0 event
#0
1
Slave mode error 0 occurs
#1
SLVTOIF
Slave Time-out Interrupt Status (Read Only)
When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI0_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active.
Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period.
5
1
read-only
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode Error 1 Interrupt Status (Read Only)
In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
7
1
read-only
0
No Slave mode error 1 event
#0
1
Slave mode error 1 occurs
#1
SPIENSTS
SPI Enable Bit Status (Read Only)
Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
15
1
read-only
0
Indicate the transmit control bit is disabled
#0
1
Indicate the transfer control bit is active
#1
SSACTIF
Slave Select Active Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
Slave select active interrupt is clear or not occur
#0
1
Slave select active interrupt event has occur
#1
SSINAIF
Slave Select Inactive Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
3
1
read-write
0
Slave select inactive interrupt is clear or not occur
#0
1
Slave select inactive interrupt event has occur
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: If SPI0_SSCTL.SSACTPOL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
Indicates the slave select line bus status is 0
#0
1
Indicates the slave select line bus status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
FIFO CLR Status (Read Only)
Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done.
23
1
read-only
0
Done the FIFO buffer clear function of TXRST and RXRST
#0
1
Doing the FIFO buffer clear function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Status (Read Only)
18
1
read-only
0
The valid data count of the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Slave Transmit FIFO Under-run Interrupt Status (Read Only)
When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set.
Note: This bit will be cleared by writing 1 to itself.
19
1
read-only
UNITIF
Unit Transfer Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
TX
SPI0_TX
FIFO Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI0_CTL register.
For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer.
0
32
write-only
VERNUM
SPI0_VERNUM
IP Version Number Register
0x50
-1
read-only
n
0x0
0x0
SPI1
SPI1 Register Map
SPI1
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x8
registers
n
CLKDIV
SPI1_CLKDIV
Clock Divider Register (Master Only)
0x4
-1
read-write
n
0x0
0x0
CLKDIV0
Clock Divider Register (master only)
The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
In slave mode, the period of SPI clock driven by a master shall satisfy
In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock.
0
16
read-write
CLKDIV1
Clock Divider 2 Register (master only)
The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
16
16
read-write
CTL
SPI1_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
BYTEENDIAN
Byte Endian Reorder Function
This function changes the order of bytes sent/received to be least significant physical byte first.
20
1
read-write
BYTESLEEP
Insert Sleep interval between Bytes
19
1
read-write
CLKP
Clock Polarity
11
1
read-write
0
SCLK idle low
#0
1
SCLK idle high
#1
DMABURST
Enable DMA Automatic SS function.
When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.
28
1
read-write
EN
Go and Busy Status
NOTE: All registers should be set before writing 1 to this EN bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished
#1
FIFO
FIFO Mode
21
1
read-write
0
No FIFO present on transmit and receive buffer
#0
1
Enable FIFO on transmit and receive buffer
#1
IE
Interrupt Enable
17
1
read-write
0
Disable SPI Interrupt
#0
1
Enable SPI Interrupt to CPU
#1
IF
Interrupt Flag
NOTE: This bit is cleared by writing 1 to itself.
16
1
read-write
0
Indicates the transfer is not finished yet
#0
1
Indicates that the transfer is complete. Interrupt is generated to CPU if enabled
#1
LSB
LSB First
10
1
read-write
0
The MSB is transmitted/received first (which bit in SPI1_TX0/1 and SPI1_RX0/1 register that is depends on the TXBITLEN field)
#0
1
The LSB is sent first on the line (bit 0 of SPI1_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI1_RX0/1)
#1
RXEMPTY
Receive FIFO EMPTY STATUS
24
1
read-write
0
The receive data FIFO is not empty
#0
1
The receive data FIFO is empty
#1
RXFULL
Receive FIFO FULL STATUS
25
1
read-write
0
The receive data FIFO is not full
#0
1
The receive data FIFO is full
#1
RXNEG
Receive At Negative Edge
1
1
read-write
0
The received data input signal is latched at the rising edge of SCLK
#0
1
The received data input signal is latched at the falling edge of SCLK
#1
SLAVE
Master Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLEEP
Suspend Interval (Master Only)
(SLEEP[3:0] + 2) * period of SCLK
12
4
read-write
TWOB
Two Bits Transfer Mode
Note that when enabled in master mode, MOSI data comes from SPI1_TX0 and MOSI data from SPI1_TX1. Likewise SPI1_RX0 receives bit stream from MISO0 and SPI1_RX1 from MISO1. Note that when enabled, the setting of TXNUM must be programmed as 0x00
22
1
read-write
0
Disable two-bit transfer mode
#0
1
Enable two-bit transfer mode
#1
TXBITLEN
Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
3
5
read-write
0
32 bit
#00000
1
1 bit
#00001
2
2 bit
#00010
3
3 bit
#00011
4
4 bit
#00100
5
5 bit
#00101
6
6 bit
#00110
7
7 bit
#00111
8
8 bit
#01000
9
9 bit
#01001
10
10 bit
#01010
11
11 bit
#01011
12
12 bit
#01100
13
13 bit
#01101
14
14 bit
#01110
15
15 bit
#01111
16
16 bit
#10000
17
17 bit
#10001
18
18 bit
#10010
19
19 bit
#10011
20
20 bit
#10100
21
21 bit
#10101
22
22 bit
#10110
23
23 bit
#10111
24
24 bit
#11000
25
25 bit
#11001
26
26 bit
#11010
27
27 bit
#11011
28
28 bit
#11100
29
29 bit
#11101
30
30 bit
#11110
31
31 bit
#11111
TXEMPTY
Transmit FIFO EMPTY STATUS
26
1
read-write
0
The transmit data FIFO is not empty
#0
1
The transmit data FIFO is empty
#1
TXFULL
Transmit FIFO FULL STATUS
27
1
read-write
0
The transmit data FIFO is not full
#0
1
The transmit data FIFO is full
#1
TXNEG
Transmit At Negative Edge
2
1
read-write
0
The transmitted data output signal is changed at the rising edge of SCLK
#0
1
The transmitted data output signal is changed at the falling edge of SCLK
#1
TXNUM
Transmit/Receive Word Numbers
This field specifies how many transmit/receive word numbers should be executed in one transfer.
8
2
read-write
0
Only one transmit/receive word will be executed in one transfer
#00
1
Two successive transmit/receive word will be executed in one transfer
#01
2
Reserved
#10
3
Reserved
#11
VARCLKEN
Variable Clock Enable (Master Only)
Note that when enabled, the setting of TXBITLEN must be programmed as 0x10 (16 bits mode)
23
1
read-write
0
The serial clock output frequency is fixed and determined only by the value of DIVIDER
#0
1
SCLK output frequency is variable. The output frequency is determined by the value of VARCLK, DIVIDER, and DIVIDER2
#1
PDMACTL
SPI1_PDMACTL
SPI PDMA Control Register
0x38
-1
read-write
n
0x0
0x0
RXMDAEN
Receive DMA Start
Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
1
1
read-write
0
Disable
#0
1
Enable
#1
TXMDAEN
Transmit DMA Start
Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically.
If using DMA mode to transfer data, remember not to set EN bit of SPI_CTL register. The DMA controller inside SPI module will set it automatically whenever necessary.
0
1
read-write
0
Disable
#0
1
Enable
#1
RX0
SPI1_RX0
Data Receive Register 0
0x10
-1
read-only
n
0x0
0x0
RX
Data Receive Register
The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and TXNUM is set to 0x0, bit SPI1_RX0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers.
0
32
read-only
RX1
SPI1_RX1
Data Receive Register 1
0x14
-1
read-only
n
0x0
0x0
RX
Data Receive Register
The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and TXNUM is set to 0x0, bit SPI1_RX0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers.
0
32
read-only
SSCTL
SPI1_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
ASS
Automatic Slave Select (Master only)
3
1
read-write
0
If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SSCTL register
#0
1
If this bit is set, SPISS signals are generated automatically. It means that device/slave select signal, which is set in SSCTL register is asserted by the SPI controller when transmit/receive is started by setting EN, and is de-asserted after each transmit/receive is finished
#1
LTRIGFLAG
Level Trigger Flag
When the SSLTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
Note: This bit is READ only
5
1
read-write
0
One of the received number and the received bit length doesn't meet the requirement in one transfer
#0
1
The received number and received bits met the requirement which defines in TXNUM and TXBITLEN among one transfer
#1
SSLTRIG
Slave Select Level Trigger (Slave only)
4
1
read-write
0
The input slave select signal is edge-trigger. This is the default value
#0
1
The slave select signal will be level-trigger. It depends on SSLVL to decide the signal is active low or active high
#1
SSLVL
Slave Select Active Level
It defines the active level of device/slave select signal (SPISSx0/1).
2
1
read-write
0
The slave select signal SPISSx0/1 is active at low-level/falling-edge
#0
1
The slave select signal SPISSx0/1 is active at high-level/rising-edge
#1
SSR
Slave Select Register (Master only)
If ASS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If ASS bit is set, writing 1 to any bit location of this field will select appropriate SPISS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSLVL).
Note: SPISS is always defined as device/slave select input signal in slave mode.
0
1
read-write
TX0
SPI1_TX0
Data Transmit Register 0
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and the TXNUM is set to 0x0, the bit SPI1_TX0[7:0] will be transmitted in next transfer. If TXBITLEN is set to 0x00 and TXNUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is SPI1_TX0[31:0], SPI1_TX1[31:0]).
0
32
write-only
TX1
SPI1_TX1
Data Transmit Register 1
0x24
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and the TXNUM is set to 0x0, the bit SPI1_TX0[7:0] will be transmitted in next transfer. If TXBITLEN is set to 0x00 and TXNUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is SPI1_TX0[31:0], SPI1_TX1[31:0]).
0
32
write-only
VARCLK
SPI1_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of CLKDIV1. Refer to register CLKDIV0.
Refer to Figure 562 Variable Serial Clock Frequency paragraph for detailed description.
0
32
read-write
SYS
SYS Register Map
SYS
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x110
0x1C
registers
n
0x30
0x4
registers
n
0x38
0x8
registers
n
0x54
0x4
registers
n
GPA_MFP
SYS_GPA_MFP
GPIOA Multiple Alternate Functions Control Register
0x38
-1
read-write
n
0x0
0x0
PA0MFP
Alternate Function Setting for PA0MFP
0
2
read-write
0
GPIO
#00
1
SPI0_MISO1
#01
3
I2S0_FS
#11
PA10MFP
Alternate Function Setting for PA10MFP
20
2
read-write
0
GPIO
#00
1
PWM0CH0
#01
2
TM0
#10
3
DPWM_P
#11
PA11MFP
Alternate Function Setting for PA11MFP
22
2
read-write
0
GPIO
#00
1
PWM0CH1
#01
2
TM1
#10
3
DPWM_M
#11
PA12MFP
Alternate Function Setting for PA12MFP
24
2
read-write
0
GPIO
#00
1
PWM0CH2
#01
2
X12MI
#10
3
I2C0_SDA
#11
PA13MFP
Alternate Function Setting for PA13MFP
26
2
read-write
0
GPIO
#00
1
PWM0CH3
#01
2
X12MO
#10
3
I2C0_SCL
#11
PA14MFP
Alternate Function Setting for PA14MFP
28
2
read-write
0
GPIO
#00
1
UART1_TX
#01
2
DMIC_CLK
#10
3
X32KI
#11
PA15MFP
Alternate Function Setting for PA15MFP
30
2
read-write
0
GPIO
#00
1
UART1_RX
#01
2
MCLK
#10
3
X32KO
#11
PA1MFP
Alternate Function Setting for PA1MFP
2
2
read-write
0
GPIO
#00
1
SPI0_MOSI0
#01
3
I2S0_BCLK
#11
PA2MFP
Alternate Function Setting for PA2MFP
4
2
read-write
0
GPIO
#00
1
SPI0_SCLK0
#01
2
DMIC_DAT
#10
3
I2S0_SDI
#11
PA3MFP
Alternate Function Setting for PA3MFP
6
2
read-write
0
GPIO
#00
1
SPI0_SSB0
#01
2
SARADC_TRIG
#10
3
I2S0_SDO
#11
PA4MFP
Alternate Function Setting for PA4MFP
8
2
read-write
0
GPIO
#00
1
SPI0_MISO0
#01
2
UART0_TX
#10
3
SPI1_MOSI
#11
PA5MFP
Alternate Function Setting for PA5MFP
10
2
read-write
0
GPIO
#00
1
SPI0_MOSI1
#01
2
UART0_RX
#10
3
SPI1_SCLK
#11
PA6MFP
Alternate Function Setting for PA6MFP
12
2
read-write
0
GPIO
#00
1
UART0_TX
#01
2
I2C0_SDA
#10
3
SPI1_SSB
#11
PA7MFP
Alternate Function Setting for PA7MFP
14
2
read-write
0
GPIO
#00
1
UART0_RX
#01
2
I2C0_SCL
#10
3
SPI1_MISO
#11
PA8MFP
Alternate Function Setting for PA8MFP
16
2
read-write
0
GPIO
#00
1
I2C0_SDA
#01
2
UART1_TX
#10
3
UART0_RTSn
#11
PA9MFP
Alternate Function Setting for PA9MFP
18
2
read-write
0
GPIO
#00
1
I2C0_SCL
#01
2
UART1_RX
#10
3
UART0_CTSn
#11
GPB_MFP
SYS_GPB_MFP
GPIOB Multiple Alternate Functions Control Register
0x3C
-1
read-write
n
0x0
0x0
PB0MFP
Alternate Function Setting for PB0MFP
0
2
read-write
0
GPIO
#00
1
SPI1_MOSI
#01
PB10MFP
Alternate Function Setting for PB10MFP
20
2
read-write
0
GPIO
#00
2
I2S0_SDI
#10
3
UART1_TX
#11
PB11MFP
Alternate Function Setting for PB11MFP
22
2
read-write
0
GPIO
#00
2
I2S0_SDO
#10
3
UART1_RX
#11
PB12MFP
Alternate Function Setting for PB12MFP
24
2
read-write
0
GPIO
#00
1
SP0_MISO1
#01
2
SPI1_MOSI
#10
3
DMIC_DAT
#11
PB13MFP
Alternate Function Setting for PB13MFP
26
2
read-write
0
GPIO
#00
1
SPI0_MOSI0
#01
2
SPI1_SCLK
#10
3
SARADC_TRIG
#11
PB14MFP
Alternate Function Setting for PB14MFP
28
2
read-write
0
GPIO
#00
1
SPI0_SCLK0
#01
2
SPI1_SSB
#10
3
DMIC_CLK
#11
PB15MFP
Alternate Function Setting for PB15MFP
30
2
read-write
0
GPIO
#00
1
SPI0_SSB0
#01
2
SPI1_MISO
#10
3
MCLK
#11
PB1MFP
Alternate Function Setting for PB1MFP
2
2
read-write
0
GPIO
#00
1
SPI1_SCLK
#01
PB2MFP
Alternate Function Setting for PB2MFP
4
2
read-write
0
GPIO
#00
1
SPI1_SSB
#01
PB3MFP
Alternate Function Setting for PB3MFP
6
2
read-write
0
GPIO
#00
1
SPI1_MISO
#01
PB4MFP
Alternate Function Setting for PB4MFP
8
2
read-write
0
GPIO
#00
1
I2S0_FS
#01
PB5MFP
Alternate Function Setting for PB5MFP
10
2
read-write
0
GPIO
#00
1
I2S0_BCLK
#01
PB6MFP
Alternate Function Setting for PB6MFP
12
2
read-write
0
GPIO
#00
1
I2S0_SDI
#01
PB7MFP
Alternate Function Setting for PB7MFP
14
2
read-write
0
GPIO
#00
1
I2S0_SDO
#01
PB8MFP
Alternate Function Setting for PB8MFP
16
2
read-write
0
GPIO
#00
1
I2C0_SDA
#01
2
I2S0_FS
#10
3
UART1_RSTn
#11
PB9MFP
Alternate Function Setting for PB9MFP
18
2
read-write
0
GPIO
#00
1
I2C0_SCL
#01
2
I2S0_BCLK
#10
3
UART1_CTsn
#11
GPSMTEN
SYS_GPSMTEN
GPIOA/B Input Type Control Register
0x30
-1
read-write
n
0x0
0x0
HSSGPAG0
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
17
1
read-write
0
GPIOA 3/2/1/0 Output low slew rate
#0
1
GPIOA 3/2/1/0 Output high slew rate
#1
HSSGPAG1
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
19
1
read-write
0
GPIOA 7/6/5/4 Output low slew rate
#0
1
GPIOA 7/6/5/4 Output high slew rate
#1
HSSGPAG2
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
21
1
read-write
0
GPIOA 11/10/9/8 Output low slew rate
#0
1
GPIOA 11/10/9/8 Output high slew rate
#1
HSSGPAG3
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
23
1
read-write
0
GPIOA 15/14/13/12 Output low slew rate
#0
1
GPIOA 15/14/13/12 Output high slew rate
#1
HSSGPBG0
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
25
1
read-write
0
GPIOB 3/2/1/0 Output low slew rate
#0
1
GPIOB 3/2/1/0 Output high slew rate
#1
HSSGPBG1
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
27
1
read-write
0
GPIOB 7/6/5/4 Output low slew rate
#0
1
GPIOB 7/6/5/4 Output high slew rate
#1
HSSGPBG2
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
29
1
read-write
0
GPIOB 11/10/9/8 Output low slew rate
#0
1
GPIOB 11/10/9/8 Output high slew rate
#1
HSSGPBG3
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
31
1
read-write
0
GPIOB 15/14/13/12 Output low slew rate
#0
1
GPIOB 15/14/13/12 Output high slew rate
#1
SSGPAG0
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
16
1
read-write
0
GPIOA 3/2/1/0 input CMOS enabled
#0
1
GPIOA 3/2/1/0 input Schmitt Trigger enabled
#1
SSGPAG1
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
18
1
read-write
0
GPIOA 7/6/5/4 input CMOS enabled
#0
1
GPIOA 7/6/5/4 input Schmitt Trigger enabled
#1
SSGPAG2
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
20
1
read-write
0
GPIOA 11/10/9/8 input CMOS enabled
#0
1
GPIOA 11/10/9/8 input Schmitt Trigger enabled
#1
SSGPAG3
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
22
1
read-write
0
GPIOA 15/14/13/12 input CMOS enabled
#0
1
GPIOA 15/14/13/12 input Schmitt Trigger enabled
#1
SSGPBG0
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
24
1
read-write
0
GPIOB 3/2/1/0 input CMOS enabled
#0
1
GPIOB 3/2/1/0 input Schmitt Trigger enabled
#1
SSGPBG1
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
26
1
read-write
0
GPIOB 7/6/5/4 input CMOS enabled
#0
1
GPIOB 7/6/5/4 input Schmitt Trigger enabled
#1
SSGPBG2
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
28
1
read-write
0
GPIOB 11/10/9/8 input CMOS enabled
#0
1
GPIOB 11/10/9/8 input Schmitt Trigger enabled
#1
SSGPBG3
this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.
Each bit controls a group of four GPIO pins
30
1
read-write
0
GPIOB 15/14/13/12 input CMOS enabled
#0
1
GPIOB 15/14/13/12 input Schmitt Trigger enabled
#1
IPRST0
SYS_IPRST0
IP Reset Control Resister0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles.
CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded.
This bit is a protected bit, to program first issue the unlock sequence
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPURST
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
This bit is a protected bit, to program first issue the unlock sequence
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
PDMARST
PDMA Controller Reset
Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state
2
1
read-write
0
Normal operation
#0
1
PDMA IP reset
#1
IPRST1
SYS_IPRST1
IP Reset Control Resister1
0xC
-1
read-write
n
0x0
0x0
ANARST
Analog Block Control Reset
30
1
read-write
0
Normal Operation
#0
1
Reset
#1
BIQRST
Biquad Filter Block Reset
18
1
read-write
0
Normal Operation
#0
1
Reset
#1
DPWMRST
DPWM Speaker Driver Reset
13
1
read-write
0
Normal Operation
#0
1
Reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
Normal Operation
#0
1
Reset
#1
I2S0RST
I2S Controller Reset
29
1
read-write
0
Normal Operation
#0
1
Reset
#1
PWM0RST
PWM0 Controller Reset
20
1
read-write
0
Normal Operation
#0
1
Reset
#1
SARADCRST
SAR ADC Controller Reset,
27
1
read-write
0
Normal Operation
#0
1
Reset,
#1
SDADCRST
SDADC Controller Reset
28
1
read-write
0
Normal Operation
#0
1
Reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
Normal Operation
#0
1
Reset
#1
SPI1RST
SPI1 Controller Reset
11
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR0RST
Timer0 Controller Reset
6
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR1RST
Timer1 Controller Reset
7
1
read-write
0
Normal Operation
#0
1
Reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
Normal Operation
#0
1
Reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
Normal Operation
#0
1
Reset
#1
IRCTCTL
SYS_IRCTCTL
Oscillator Frequency Adjustment Control Register
0x110
-1
read-write
n
0x0
0x0
FREQ
Current oscillator frequency trim value. (based on CLK_CLKSEL0.HIRCFSEL)
0
10
read-write
RANGE
1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
15
1
read-write
OSC10KTRIM
SYS_OSC10KTRIM
10kHz Oscillator (LIRC) Trim Register
0x114
-1
read-write
n
0x0
0x0
TRIM
23bit trim for LIRC.
0
23
read-write
TRMCLK
31
1
read-write
OSCTRIM0
SYS_OSCTRIM0
Internal Oscillator Trim Register 0
0x118
-1
read-write
n
0x0
0x0
EN2MHZ
1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
31
1
read-write
TRIM
16bit sign extended representation of 10bit trim.
0
16
read-write
OSCTRIM1
SYS_OSCTRIM1
Internal Oscillator Trim Register 1
0x11C
-1
read-write
n
0x0
0x0
EN2MHZ
1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
31
1
read-write
TRIM
16bit sign extended representation of 10bit trim.
0
16
read-write
OSCTRIM2
SYS_OSCTRIM2
Internal Oscillator Trim Register 2
0x120
-1
read-write
n
0x0
0x0
EN2MHZ
1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
31
1
read-write
TRIM
16bit sign extended representation of 10bit trim.
0
16
read-write
PDID
SYS_PDID
Product ID
0x0
-1
read-only
n
0x0
0x0
PDID
Product Identifier
Chip identifier for I91200 series.
0
32
read-only
REGLCTL
SYS_REGLCTL
Register Lock Control
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Protected Register Unlock Register
0
1
read-write
0
Protected registers are locked. Any write to the target register is ignored
#0
1
Protected registers are unlocked
#1
Reserved
Reserved
System Reserved, Keep POR Value
0x128
-1
read-write
n
0x0
0x0
RSTSTS
SYS_RSTSTS
System Reset Source Register
0x4
-1
read-write
n
0x0
0x0
CORERSTF
Reset Source From CORE
The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset.
This bit is cleared by writing 1 to itself.
0
1
read-write
0
No reset from CORE
#0
1
Core was reset by hardware block
#1
CPURF
Reset Source From CPU
The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).
This bit is cleared by writing 1 to itself.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 CPU kernel and FMC has been reset by software setting CPURST to 1
#1
DPDRSTF
Deep Power Down Reset Flag
The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
9
1
read-write
0
No detected
#0
1
A power on was triggered by DPD timer
#1
LVRF
Low Voltage Reset Flag
The LVRF flag is set if pervious reset source originates from the LVR module.
This bit is cleared by writing 1 to itself.
3
1
read-write
0
No reset from LVR
#0
1
The LVR module issued the reset signal to reset the system
#1
PADRF
The RSTS_PAD Flag Is If Pervious Reset Source Originates From the /RESET Pin
This bit is cleared by writing 1 to itself.
1
1
read-write
0
No reset from Pin /RESET
#0
1
Pin /RESET had issued the reset signal to reset the system
#1
PMURSTF
Reset Source From PMU
The PMURSTF flag is set if the PMU.
This bit is cleared by writing 1 to itself.
6
1
read-write
0
No reset from PMU
#0
1
PMU reset the system from a power down/standby event
#1
PORF
Power on Reset Flag
The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
10
1
read-write
0
No detected
#0
1
A power on Reset has occurred
#1
SYSRF
Reset Source From MCU
The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel.
This bit is cleared by writing 1 to itself.
5
1
read-write
0
No reset from MCU
#0
1
The Cortex_M0 MCU issued a reset signal to reset the system by software writing 1 to bit SYSRESTREQ(SYSINFO_AIRCTL[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel
#1
WDTRF
Reset Source From WDT
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
This bit is cleared by writing 1 to itself.
2
1
read-write
0
No reset from Watch-Dog
#0
1
The Watch-Dog module issued the reset signal to reset the system
#1
WKRSTF
Wakeup Pin Reset Flag
The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
8
1
read-write
0
No detected
#0
1
A power on was triggered by WAKEUP pin
#1
WKCTL
SYS_WKCTL
WAKEUP pin control register
0x54
-1
read-write
n
0x0
0x0
XTALTRIM
SYS_XTALTRIM
External Crystal Oscillator Trim Register
0x124
-1
read-write
n
0x0
0x0
LOWPWR
1: low power mode. 0: normal mode.
9
1
read-write
SELXT
HXT select external clock
0: Disable
1: Enable
16
1
read-write
XGS
HXT Gain Select
24
2
read-write
SYSINFO
SYSINFO Register Map
SYSINFO
0x0
0x0
0x8
registers
n
0x1C
0x8
registers
n
0xC
0x8
registers
n
AIRCTL
SYSINFO_AIRCTL
Application Interrupt and Reset Control Register
0xC
-1
read-write
n
0x0
0x0
CLRACTVT
Clear All Active Vector
Clears all active state information for fixed and configurable exceptions.
The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE.
1
1
read-write
0
do not clear state information
#0
1
clear state information
#1
ENDIANES
Endianness
Read Only. Reads 0 indicating little endian machine.
15
1
read-write
SRSTREQ
System Reset Request
Writing 1 to this bit asserts a signal to request a reset by the external system.
2
1
read-write
0
do not request a reset
#0
1
request reset
#1
VTKEY
Vector Key
The value 0x05FA must be written to this register, otherwise
a write to register is UNPREDICTABLE.
16
16
read-write
CPUID
SYSINFO_CPUID
CPUID Base Register
0x0
-1
read-only
n
0x0
0x0
IMPCODE
Implementer Code Assigned by ARM
24
8
read-only
PART
ARMv6-m Parts
Reads as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Part Number
Reads as 0xC20.
4
12
read-only
REVISION
Revision
Reads as 0x0
0
4
read-only
ICSR
SYSINFO_ICSR
Interrupt Control State Register
0x4
-1
read-write
n
0x0
0x0
ISRPEND
ISR Pending
Indicates if an external configurable (NVIC generated) interrupt is pending.
22
1
read-write
ISRPREEM
ISR Preemptive
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-write
NMIPNSET
NMI Pending Set Control
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
31
1
read-write
PPSVICLR
Clear a Pending PendSV Interrupt
Write 1 to clear a pending PendSV interrupt.
27
1
read-write
PPSVISET
Set a Pending PendSV Interrupt
This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
28
1
read-write
PSTKICLR
Clear a Pending SYST
Write 1 to clear a pending SYST.
25
1
read-write
PSTKISET
Set a Pending SYST
Reads back with current state (1 if Pending, 0 if not).
26
1
read-write
VTACT
Vector Active
0: Thread mode
Value > 1: the exception number for the current executing exception.
0
9
read-write
VTPEND
Vector Pending
Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
12
9
read-write
SCR
SYSINFO_SCR
System Control Register
0x10
-1
read-write
n
0x0
0x0
SEVNONPN
Send Event on Pending Bit
When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
4
1
read-write
0
only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLPDEEP
Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode
The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states.
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLPONEXC
Sleep on Exception
When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
SHPR2
SYSINFO_SHPR2
System Handler Priority Register 2
0x1C
-1
read-write
n
0x0
0x0
PRI11
Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SHPR3
SYSINFO_SHPR3
System Handler Priority Register 3
0x20
-1
read-write
n
0x0
0x0
PRI14
Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI15
Priority of System Handler 15 - SYST
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SYSTICK
SYSTICK Register Map
SYSTICK
0x0
0x10
0xC
registers
n
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
CLKSRC
Clock Source
2
1
read-write
0
Core clock unused
#0
1
Core clock used for SysTick, this bit will read as 1 and ignore writes
#1
COUNTFLAG
Count Flag
Returns 1 if timer counted to 0 since last time this register was read.
16
1
read-write
0
Cleared on read or by a write to the Current Value register
#0
1
Set by a count transition from 1 to 0
#1
ENABLE
ENABLE
0
1
read-write
0
The counter is disabled
#0
1
The counter will operate in a multi-shot manner
#1
TICKINT
Enables SysTick Exception Request
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
CURRENT
Current Counter Value
This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit.
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
RELOAD
SysTick Reload
Value to load into the Current Value register when the counter reaches 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 200 clock pulses, set RELOAD to 199.
0
24
read-write
TMR0
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
TMRn_CMP
TMRn_CMP
Timer Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count.
0
25
read-write
TMRn_CNT
TMRn_CNT
Timer Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value.
0
24
read-write
TMRn_CTL
TMRn_CTL
Timer Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTDATEN
Data Latch Enable
When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
CNTEN
Counter Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware
0
1
The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)
1
2
Reserved
2
3
The timer is operating in continuous counting mode. The associated interrupt signal is generated when CNT = TIMERx_CMP (if INTEN is enabled) however, the 24-bit up-counter counts continuously without reset
3
PSC
Pre-scale Counter
0
8
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 24-bit up-counter and CNTEN bit
#1
TMRn_INTSTS
TMRn_INTSTS
Timer Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1.
0
1
read-write
TMR1
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
TMRn_CMP
TMRn_CMP
Timer Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count.
0
25
read-write
TMRn_CNT
TMRn_CNT
Timer Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value.
0
24
read-write
TMRn_CTL
TMRn_CTL
Timer Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTDATEN
Data Latch Enable
When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
CNTEN
Counter Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware
0
1
The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)
1
2
Reserved
2
3
The timer is operating in continuous counting mode. The associated interrupt signal is generated when CNT = TIMERx_CMP (if INTEN is enabled) however, the 24-bit up-counter counts continuously without reset
3
PSC
Pre-scale Counter
0
8
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 24-bit up-counter and CNTEN bit
#1
TMRn_INTSTS
TMRn_INTSTS
Timer Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1.
0
1
read-write
UART0
UART Register Map
UART
0x0
0x0
0x34
registers
n
UARTn_ALTCTL
UARTn_ALTCTL
UART LIN Control Register.
0x2C
-1
read-write
n
0x0
0x0
BRKFL
UART LIN Break Field Length Count
This field indicates a 4-bit LIN Tx break field count.
NOTE: This break field length is BRKFL + 2
0
4
read-write
LINRXEN
LIN RX Enable
6
1
read-write
0
Disable LIN Rx mode
#0
1
Enable LIN Rx mode
#1
LINTXEN
LIN TX Break Mode Enable
NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Disable LIN Tx Break Mode
#0
1
Enable LIN Tx Break Mode
#1
UARTn_BAUD
UARTn_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal 1
Refer to Table 5116 UART Baud Rate Setting Table for more information.
28
1
read-write
BAUDM1
Divider X Enable
Refer to Table 5116 UART Baud Rate Setting Table for more information.
NOTE: When in IrDA mode, this bit must disabled.
29
1
read-write
0
Disable divider X ( M = 16)
#0
1
Enable divider X (M = EDIVM1+1, with EDIVM1 ≥ 8)
#1
BRD
Baud Rate Divider
Refer to Table 5116 UART Baud Rate Setting Table for more information.
0
16
read-write
EDIVM1
Divider x
24
4
read-write
UARTn_DAT
UARTn_DAT
UART Receive/Transfer FIFO Register.
0x0
-1
read-write
n
0x0
0x0
DAT
Receive FIFO Register
Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
0
8
read-write
UARTn_FIFO
UARTn_FIFO
UART FIFO Control Register.
0x8
-1
read-write
n
0x0
0x0
RFITL
Receive FIFO Interrupt (RDAINT) Trigger Level
When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and, if enabled, an RDAINT interrupt will generated.
Value : INTR_RDA Trigger Level (Bytes)
0 : 1
1 : 4
4
4
read-write
RTSTRGLV
RTS Trigger Level for Auto-flow Control
Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).
Value : Trigger Level (Bytes)
0 : 1
1 : 4
2 : 8
16
4
read-write
RXRST
Receive FIFO Reset
When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the receiving internal state machine and pointers
#1
TXRST
Transmit FIFO Reset
When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
2
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the transmit internal state machine and pointers
#1
UARTn_FIFOSTS
UARTn_FIFOSTS
UART FIFO Status Register.
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
6
1
read-write
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
5
1
read-write
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
4
1
read-write
RXEMPTY
Receive FIFO Empty (Read Only)
This bit indicates whether the Rx FIFO is empty or not.
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receive FIFO Full (Read Only)
This bit indicates whether the Rx FIFO is full or not.
This bit is set when Rx FIFO is full otherwise it is cleared by hardware.
15
1
read-only
RXOVIF
Rx Overflow Error Interrupt Flag
If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
RXPTR
Rx FIFO Pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
8
6
read-only
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit indicates whether the Tx FIFO is empty or not.
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
NOTE: This bit is read only.
28
1
read-only
TXFULL
Transmit FIFO Full (Read Only)
This bit indicates whether the Tx FIFO is full or not.
23
1
read-only
TXOVIF
Tx Overflow Error Interrupt Flag
If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
24
1
read-write
TXPTR
Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented.
16
6
read-only
UARTn_FUNCSEL
UARTn_FUNCSEL
UART Function Select Register.
0x30
-1
read-write
n
0x0
0x0
IRDAEN
Enable IrDA Function
1
1
read-write
0
UART Function
#0
1
Enable IrDA Function
#1
LINEN
Enable LIN Function
Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.
0
1
read-write
0
UART Function
#0
1
Enable LIN Function
#1
UARTn_INTEN
UARTn_INTEN
UART Interrupt Enable Register.
0x4
-1
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable
When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted).
13
1
read-write
0
Disable CTS auto flow control
#0
1
Enable
#1
ATORTSEN
RTS Auto Flow Control Enable
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.
12
1
read-write
0
Disable RTS auto flow control
#0
1
Enable
#1
BUFERRIEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off BUFERRINT
#0
1
Enable IBUFERRINT
#1
DMARXEN
Receive DMA Enable
If enabled, the UART will request DMA service when data is available in receive FIFO.
15
1
read-write
DMATXEN
Transmit DMA Enable
If enabled, the UART will request DMA service when space is available in transmit FIFO.
14
1
read-write
LINIEN
LIN RX Break Field Detected Interrupt Enable
8
1
read-write
0
Mask off Lin bus Rx break field interrupt
#0
1
Enable Lin bus Rx break field interrupt
#1
MODEMIEN
Modem Status Interrupt Enable
3
1
read-write
0
Mask off MODEMINT
#0
1
Enable MODEMINT
#1
RDAIEN
Receive Data Available Interrupt Enable
0
1
read-write
0
Mask off RDAINT
#0
1
Enable RDAINT
#1
RLSIEN
Receive Line Status Interrupt Enable
2
1
read-write
0
Mask off RLSINT
#0
1
Enable RLSINT
#1
RXTOIEN
Receive Time Out Interrupt Enable
4
1
read-write
0
Mask off RXTOINT
#0
1
Enable RXTOINT
#1
THREIEN
Transmit FIFO Register Empty Interrupt Enable
1
1
read-write
0
Mask off THERINT
#0
1
Enable THERINT
#1
TOCNTEN
Time-out Counter Enable
11
1
read-write
0
Disable Time-out counter
#0
1
Enable
#1
UARTn_INTSTS
UARTn_INTSTS
UART Interrupt Status Register.
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.
13
1
read-write
DBERRIF
DMA MODE Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
21
1
read-only
DBERRINT
DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF.
29
1
read-write
DLINIF
DMA MODE LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
23
1
read-write
DLININT
DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF.
31
1
read-write
DMODEMI
DMA MODE MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF.
27
1
read-write
DMODEMIF
DMA MODE MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
19
1
read-only
DRLSIF
DMA MODE Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
DRLSINT
DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.
26
1
read-write
DRXTOIF
DMA MODE Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
20
1
read-only
DRXTOINT
DMA MODE Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF.
28
1
read-write
LINIF
LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
7
1
read-write
LININT
LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.LINIEN and LINIF.
15
1
read-write
MODEMINT
MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.MODEMIEN and MODENIF.
11
1
read-write
MODENIF
MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.
NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RDAIEN and RDAIF.
8
1
read-write
RLSIF
Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RLSIEN and RLSIF.
10
1
read-write
RXTOIF
Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
4
1
read-only
RXTOINT
Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RXTOIEN and RXTOIF.
12
1
read-write
THERINT
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.THREIEN and THREIF.
9
1
read-write
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.
NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
1
1
read-only
UARTn_IRDA
UARTn_IRDA
UART IrDA Control Register.
0x28
-1
read-write
n
0x0
0x0
LOOPBACK
IrDA Loopback Test Mode
Loopback Tx to Rx.
2
1
read-write
RXINV
Receive Inversion Enable
6
1
read-write
0
No inversion
#0
1
Invert Rx input signal
#1
TXEN
Transmit/Receive Selection
1
1
read-write
0
Enable IrDA receiver
#0
1
Enable IrDA transmitter
#1
TXINV
Transmit Inversion Enable
5
1
read-write
0
No inversion
#0
1
Invert Tx output signal
#1
UARTn_LINE
UARTn_LINE
UART Line Control Register.
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable
This bit has effect only when PBE (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1's are transmitted or checked in the data word and parity bits
#1
NSB
Number of STOP Bits
2
1
read-write
0
One STOP bit is generated after the transmitted data
#0
1
Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable
3
1
read-write
0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Disable stick parity
#0
1
When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared
#1
WLS
Word Length Select
0 (5bits), 1(6bits), 2(7bits), 3(8bits)
0
2
read-write
UARTn_MODEM
UARTn_MODEM
UART Modem Control Register.
0x10
-1
read-write
n
0x0
0x0
LBMEN
Loopback Mode Enable
4
1
read-write
0
Disable
#0
1
Enable
#1
RTS
RTS (Request-to-send) Signal
1
1
read-write
0
Drive RTS inactive ( = ~RTSACTLV)
#0
1
Drive RTS active ( = RTSACTLV)
#1
RTSACTLV
Request-to-send (RTS) Active Trigger Level
This bit can change the RTS trigger level.
9
1
read-write
0
RTS is active low level
#0
1
RTS is active high level
#1
RTSSTS
RTS Pin State (Read Only)
This bit is the pin status of RTS.
13
1
read-only
UARTn_MODEMSTS
UARTn_MODEMSTS
UART Modem Status Register.
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
Clear-to-send (CTS) Active Trigger Level
This bit can change the CTS trigger level.
8
1
read-write
0
CTS is active low level
#0
1
CTS is active high level
#1
CTSDETF
Detect CTS State Change Flag
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
CTSSTS
CTS Pin Status (Read Only)
This bit is the pin status of CTS.
4
1
read-only
UARTn_TOUT
UARTn_TOUT
UART Time Out Register
0x20
-1
read-write
n
0x0
0x0
TOIC
Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate.
0
7
read-write
UART1
UART Register Map
UART
0x0
0x0
0x34
registers
n
UARTn_ALTCTL
UARTn_ALTCTL
UART LIN Control Register.
0x2C
-1
read-write
n
0x0
0x0
BRKFL
UART LIN Break Field Length Count
This field indicates a 4-bit LIN Tx break field count.
NOTE: This break field length is BRKFL + 2
0
4
read-write
LINRXEN
LIN RX Enable
6
1
read-write
0
Disable LIN Rx mode
#0
1
Enable LIN Rx mode
#1
LINTXEN
LIN TX Break Mode Enable
NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Disable LIN Tx Break Mode
#0
1
Enable LIN Tx Break Mode
#1
UARTn_BAUD
UARTn_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal 1
Refer to Table 5116 UART Baud Rate Setting Table for more information.
28
1
read-write
BAUDM1
Divider X Enable
Refer to Table 5116 UART Baud Rate Setting Table for more information.
NOTE: When in IrDA mode, this bit must disabled.
29
1
read-write
0
Disable divider X ( M = 16)
#0
1
Enable divider X (M = EDIVM1+1, with EDIVM1 ≥ 8)
#1
BRD
Baud Rate Divider
Refer to Table 5116 UART Baud Rate Setting Table for more information.
0
16
read-write
EDIVM1
Divider x
24
4
read-write
UARTn_DAT
UARTn_DAT
UART Receive/Transfer FIFO Register.
0x0
-1
read-write
n
0x0
0x0
DAT
Receive FIFO Register
Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
0
8
read-write
UARTn_FIFO
UARTn_FIFO
UART FIFO Control Register.
0x8
-1
read-write
n
0x0
0x0
RFITL
Receive FIFO Interrupt (RDAINT) Trigger Level
When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and, if enabled, an RDAINT interrupt will generated.
Value : INTR_RDA Trigger Level (Bytes)
0 : 1
1 : 4
4
4
read-write
RTSTRGLV
RTS Trigger Level for Auto-flow Control
Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).
Value : Trigger Level (Bytes)
0 : 1
1 : 4
2 : 8
16
4
read-write
RXRST
Receive FIFO Reset
When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the receiving internal state machine and pointers
#1
TXRST
Transmit FIFO Reset
When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
2
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the transmit internal state machine and pointers
#1
UARTn_FIFOSTS
UARTn_FIFOSTS
UART FIFO Status Register.
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
6
1
read-write
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
5
1
read-write
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
4
1
read-write
RXEMPTY
Receive FIFO Empty (Read Only)
This bit indicates whether the Rx FIFO is empty or not.
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receive FIFO Full (Read Only)
This bit indicates whether the Rx FIFO is full or not.
This bit is set when Rx FIFO is full otherwise it is cleared by hardware.
15
1
read-only
RXOVIF
Rx Overflow Error Interrupt Flag
If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
RXPTR
Rx FIFO Pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
8
6
read-only
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit indicates whether the Tx FIFO is empty or not.
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
NOTE: This bit is read only.
28
1
read-only
TXFULL
Transmit FIFO Full (Read Only)
This bit indicates whether the Tx FIFO is full or not.
23
1
read-only
TXOVIF
Tx Overflow Error Interrupt Flag
If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
24
1
read-write
TXPTR
Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented.
16
6
read-only
UARTn_FUNCSEL
UARTn_FUNCSEL
UART Function Select Register.
0x30
-1
read-write
n
0x0
0x0
IRDAEN
Enable IrDA Function
1
1
read-write
0
UART Function
#0
1
Enable IrDA Function
#1
LINEN
Enable LIN Function
Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.
0
1
read-write
0
UART Function
#0
1
Enable LIN Function
#1
UARTn_INTEN
UARTn_INTEN
UART Interrupt Enable Register.
0x4
-1
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable
When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted).
13
1
read-write
0
Disable CTS auto flow control
#0
1
Enable
#1
ATORTSEN
RTS Auto Flow Control Enable
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.
12
1
read-write
0
Disable RTS auto flow control
#0
1
Enable
#1
BUFERRIEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off BUFERRINT
#0
1
Enable IBUFERRINT
#1
DMARXEN
Receive DMA Enable
If enabled, the UART will request DMA service when data is available in receive FIFO.
15
1
read-write
DMATXEN
Transmit DMA Enable
If enabled, the UART will request DMA service when space is available in transmit FIFO.
14
1
read-write
LINIEN
LIN RX Break Field Detected Interrupt Enable
8
1
read-write
0
Mask off Lin bus Rx break field interrupt
#0
1
Enable Lin bus Rx break field interrupt
#1
MODEMIEN
Modem Status Interrupt Enable
3
1
read-write
0
Mask off MODEMINT
#0
1
Enable MODEMINT
#1
RDAIEN
Receive Data Available Interrupt Enable
0
1
read-write
0
Mask off RDAINT
#0
1
Enable RDAINT
#1
RLSIEN
Receive Line Status Interrupt Enable
2
1
read-write
0
Mask off RLSINT
#0
1
Enable RLSINT
#1
RXTOIEN
Receive Time Out Interrupt Enable
4
1
read-write
0
Mask off RXTOINT
#0
1
Enable RXTOINT
#1
THREIEN
Transmit FIFO Register Empty Interrupt Enable
1
1
read-write
0
Mask off THERINT
#0
1
Enable THERINT
#1
TOCNTEN
Time-out Counter Enable
11
1
read-write
0
Disable Time-out counter
#0
1
Enable
#1
UARTn_INTSTS
UARTn_INTSTS
UART Interrupt Status Register.
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.
13
1
read-write
DBERRIF
DMA MODE Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
21
1
read-only
DBERRINT
DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF.
29
1
read-write
DLINIF
DMA MODE LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
23
1
read-write
DLININT
DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF.
31
1
read-write
DMODEMI
DMA MODE MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF.
27
1
read-write
DMODEMIF
DMA MODE MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
19
1
read-only
DRLSIF
DMA MODE Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
DRLSINT
DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.
26
1
read-write
DRXTOIF
DMA MODE Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
20
1
read-only
DRXTOINT
DMA MODE Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF.
28
1
read-write
LINIF
LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
7
1
read-write
LININT
LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.LINIEN and LINIF.
15
1
read-write
MODEMINT
MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.MODEMIEN and MODENIF.
11
1
read-write
MODENIF
MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.
NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RDAIEN and RDAIF.
8
1
read-write
RLSIF
Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RLSIEN and RLSIF.
10
1
read-write
RXTOIF
Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
4
1
read-only
RXTOINT
Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RXTOIEN and RXTOIF.
12
1
read-write
THERINT
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.THREIEN and THREIF.
9
1
read-write
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.
NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
1
1
read-only
UARTn_IRDA
UARTn_IRDA
UART IrDA Control Register.
0x28
-1
read-write
n
0x0
0x0
LOOPBACK
IrDA Loopback Test Mode
Loopback Tx to Rx.
2
1
read-write
RXINV
Receive Inversion Enable
6
1
read-write
0
No inversion
#0
1
Invert Rx input signal
#1
TXEN
Transmit/Receive Selection
1
1
read-write
0
Enable IrDA receiver
#0
1
Enable IrDA transmitter
#1
TXINV
Transmit Inversion Enable
5
1
read-write
0
No inversion
#0
1
Invert Tx output signal
#1
UARTn_LINE
UARTn_LINE
UART Line Control Register.
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable
This bit has effect only when PBE (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1's are transmitted or checked in the data word and parity bits
#1
NSB
Number of STOP Bits
2
1
read-write
0
One STOP bit is generated after the transmitted data
#0
1
Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable
3
1
read-write
0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Disable stick parity
#0
1
When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared
#1
WLS
Word Length Select
0 (5bits), 1(6bits), 2(7bits), 3(8bits)
0
2
read-write
UARTn_MODEM
UARTn_MODEM
UART Modem Control Register.
0x10
-1
read-write
n
0x0
0x0
LBMEN
Loopback Mode Enable
4
1
read-write
0
Disable
#0
1
Enable
#1
RTS
RTS (Request-to-send) Signal
1
1
read-write
0
Drive RTS inactive ( = ~RTSACTLV)
#0
1
Drive RTS active ( = RTSACTLV)
#1
RTSACTLV
Request-to-send (RTS) Active Trigger Level
This bit can change the RTS trigger level.
9
1
read-write
0
RTS is active low level
#0
1
RTS is active high level
#1
RTSSTS
RTS Pin State (Read Only)
This bit is the pin status of RTS.
13
1
read-only
UARTn_MODEMSTS
UARTn_MODEMSTS
UART Modem Status Register.
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
Clear-to-send (CTS) Active Trigger Level
This bit can change the CTS trigger level.
8
1
read-write
0
CTS is active low level
#0
1
CTS is active high level
#1
CTSDETF
Detect CTS State Change Flag
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
CTSSTS
CTS Pin Status (Read Only)
This bit is the pin status of CTS.
4
1
read-only
UARTn_TOUT
UARTn_TOUT
UART Time Out Register
0x20
-1
read-write
n
0x0
0x0
TOIC
Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate.
0
7
read-write
VOLCTRL
VOLCTRL Register Map
VOLCTRL
0x0
0x0
0xC
registers
n
ADCVAL
VOLCTRL_ADCVAL
ADC Volume Control Value
0x4
-1
read-write
n
0x0
0x0
VALUE
Delta-Sigma ADC Signal Volume Control Value
0
24
read-write
DPWMVAL
VOLCTRL_DPWMVAL
DPWM Volume Control Value
0x8
-1
read-write
n
0x0
0x0
VALUE
DPWM Audio Signal Volume Control Value
0
24
read-write
EN
VOLCTRL_EN
Volume Control Enable Register
0x0
-1
read-write
n
0x0
0x0
DPWMVOLEN
DPWM Audio Signal Volume Control Enable
1
1
read-write
0
bypass the volume control function
#0
1
enable the volume control function
#1
DPWMZCEN
DPWM Audio Signal Volume Zero Crossing Enable
3
1
read-write
0
disable zero crossing update gain
#0
1
enable Zero crossing update gain
#1
SDADCVOLEN
Delta-Sigma ADC Signal Volume Control Enable
0
1
read-write
0
bypass the volume control function
#0
1
enable the volume control function
#1
SDADCZCEN
Delta-Sigma ADC Signal Volume Zero Crossing Enable
2
1
read-write
0
disable zero crossing update gain
#0
1
enable Zero crossing update gain
#1
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
IF
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
NOTE: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt has not occurred
#0
1
Watchdog timer interrupt has occurred
#1
INTEN
Watchdog Timer Interrupt Enable
6
1
read-write
0
Disable the Watchdog timer interrupt
#0
1
Enable the Watchdog timer interrupt
#1
RSTCNT
Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
NOTE: This bit will auto clear after few clock cycle
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Reset the contents of the Watchdog timer
#1
RSTEN
Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
1
1
read-write
0
Disable Watchdog timer reset function
#0
1
Enable Watchdog timer reset function
#1
RSTF
Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
NOTE: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog timer reset has not occurred
#0
1
Watchdog timer reset has occurred
#1
TOUTSEL
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:
Where WDT_CLK is the period of the Watchdog Timer clock source.
8
3
read-write
WDTEN
Watchdog Timer Enable
7
1
read-write
0
Disable the Watchdog timer (This action will reset the internal counter)
#0
1
Enable the Watchdog timer
#1