nuvoTon
ISD9300_v3
2024.05.05
ISD9300_v3 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x10
registers
n
CTL0
ACMP_CTL0
Analog Comparator 0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACMPEN
Comparator Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
ACMPIE
CMP0 Interrupt Enable
1
1
read-write
0
Disable CMP0 interrupt function
#0
1
Enable CMP0 interrupt function
#1
NEGSEL
Comparator0 Negative Input Select
4
1
read-write
0
VBG, Bandgap reference voltage aaa 1.2V
#0
1
VMID reference voltage aaa VCCA/2
#1
CTL1
ACMP_CTL1
Analog Comparator 1 Control Register
0x4
-1
read-write
n
0x0
0x0
ACMPEN
Comparator Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
ACMPIE
CMP1 Interrupt Enable
1
1
read-write
0
Disable CMP1interrupt function
#0
1
Enable CMP1 interrupt function
#1
NEGSEL
Comparator1 Negative Input Select
4
1
read-write
0
GPIOB[7]
#0
1
VBG, Bandgap reference voltage aaa 1.2V
#1
POSSEL
ACMP_POSSEL
Comparator Select Register
0xC
-1
read-write
n
0x0
0x0
POSSEL
Comparator0 GPIO Selection
GPIOB[POSSEL] is the active analog GPIO input selected to Comparator 0 positive input.
0
3
read-write
STATUS
ACMP_STATUS
Comparator Status Register
0x8
-1
read-write
n
0x0
0x0
ACMPIF0
Compare 0 Flag
This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
0
1
read-write
ACMPIF1
Compare 1 Flag
This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
1
1
read-write
ACMPO0
Comparator0 Output
Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP0EN aaa 0).
2
1
read-write
ACMPO1
Comparator1 Output
Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN aaa 0).
3
1
read-write
ADC
ADC Register Map
ADC
0x0
0x0
0x20
registers
n
CHEN
ADC_CHEN
ADC Enable Register
0x4
-1
read-write
n
0x0
0x0
CHEN
ADC Enable
0
1
read-write
0
Conversion stopped and ADC is reset including FIFO pointers
#0
1
ADC Conversion enabled
#1
CLKDIV
ADC_CLKDIV
ADC Clock Divider Register
0x8
-1
read-write
n
0x0
0x0
CLKDIV
ADC Clock Divider
This register determines the clock division ration between the incoming ADC_CLK ( aaa HCLK by default) and the Delta-Sigma sampling clock of the ADC. This together with the over-sampling ratio (OVSPLRAT) determines the audio sample rate of the converter. CLKDIV should be set to give a SDCLK frequency in the range of 1.024-6.144MHz.
CLKDIV must be greater than 2.
SDCLK frequency aaa HCLK ÷ CLKDIV
0
8
read-write
CMP0
ADC_CMP0
ADC Comparator 0 Control Register
0x18
-1
read-write
n
0x0
0x0
ADCMPEN
Compare Enable
Set this bit to 1 to enable compare CMPDAT with FIFO data output.
0
1
read-write
0
Disable compare
#0
1
Enable compare
#1
ADCMPIE
Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, CMPFLAG bit will be asserted, if ADCMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Disable compare function interrupt
#0
1
Enable compare function interrupt
#1
CMPCOND
Compare Condition
Note: When the internal counter reaches the value (CMPMCNT +1), the CMPFLAG bit will be set.
2
1
read-write
0
Set the compare condition that result is less than CMPDAT
#0
1
Set the compare condition that result is greater or equal to CMPDAT
#1
CMPDAT
Comparison Data
16 bit value to compare to FIFO output word.
16
16
read-write
CMPFLAG
Compare Flag
When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self.
7
1
read-write
CMPMCNT
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMCNT +1), the CMPFLAG bit will be set.
8
4
read-write
CMP1
0x1C
-1
read-write
n
0x0
0x0
DAT
ADC_DAT
ADC FIFO Data Out
0x0
-1
read-only
n
0x0
0x0
RESULT
ADC Audio Data FIFO Read
A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with FIFOINTLV interrupt to determine if valid data is present in FIFO.
0
16
read-only
DCICTL
ADC_DCICTL
ADC Decimation Control Register
0xC
-1
read-write
n
0x0
0x0
GAIN
CIC Filter Additional Gain
This should normally remain default 0. Can be set to non-zero values to provide additional digital gain from the decimation filter. An additional gain is applied to signal of GAIN÷2.
16
4
read-write
OVSPLRAT
Decimation Over-Sampling Ratio
This term determines the over-sampling ratio of the decimation filter. Valid values are:
0: OVSPLRAT aaa 64
1: OVSPLRAT aaa 128
2: OVSPLRAT aaa 192
3: OVSPLRAT aaa 384
0
4
read-write
INTCTL
ADC_INTCTL
ADC Interrupt Control Register
0x10
-1
read-write
n
0x0
0x0
FIFOINTLV
FIFO Interrupt Level
Determines at what level the ADC FIFO will generate a servicing interrupt to the CPU. Interrupt will be generated when number of words present in ADC FIFO is > FIFOINTLV.
0
3
read-write
INTEN
Interrupt Enable
If set to '1' an interrupt is generated whenever FIFO level exceeds that set in FIFOINTLV.
31
1
read-write
PDMACTL
ADC_PDMACTL
ADC PDMA Control Register
0x14
-1
read-write
n
0x0
0x0
RXDMAEN
Enable ADC PDMA Receive Channel
Enable ADC PDMA. If set, then ADC will request PDMA service when data is available.
0
1
read-write
ALC
ALC Register Map
ALC
0x0
0x0
0x10
registers
n
CTL
ALC_CTL
ALC Control Register
0x0
-1
read-write
n
0x0
0x0
ALCEN
ALC Select
28
1
read-write
0
ALC disabled (default)
#0
1
ALC enabled
#1
ATKSEL
ALC Attack Time
(Value: 0~10)
When MODESEL aaa 0, Range: 500us to 512ms
When MODESEL aaa 1,Range: 125us to 128ms (Both ALC time doubles with every step)
4
4
read-write
DECAYSEL
ALC Decay Time
(Value: 0~10)
When MODESEL aaa 0, Range: 125us to 128ms
When MODESEL aaa 1, Range: 31us to 32ms (time doubles with every step)
8
4
read-write
HOLDTIME
ALC Hold Time
(Value: 0~10). Hold Time aaa (2^HOLDTIME) ms
17
4
read-write
MAXGAIN
ALC Maximum Gain
25
3
read-write
0
-6.75 dB
0
1
-0.75 dB
1
2
+5.25 dB
2
3
+11.25 dB
3
4
+17.25 dB
4
5
+23.25 dB
5
6
+29.25 dB
6
7
+35.25 dB
7
MINGAIN
ALC Minimum Gain
22
3
read-write
0
-12 dB
0
1
-6 dB
1
2
0 dB
2
3
6 dB
3
4
12 dB
4
5
18 dB
5
6
24 dB
6
7
30 dB
7
MODESEL
ALC Mode
12
1
read-write
0
ALC normal operation mode
#0
1
ALC limiter mode
#1
NGEN
Noise Gate Enable
3
1
read-write
0
Noise gate disabled
#0
1
Noise gate enabled
#1
NGPKSEL
ALC Noise Gate Peak Detector Select
29
1
read-write
0
use peak-to-peak value for noise gate threshold determination (default)
#0
1
use absolute peak value for noise gate threshold determination
#1
NGTHBST
Noise Gate Threshold
Boost disabled: Threshold aaa (-81+6xNGTHBST) dB
Boost enabled: Threshold aaa (-87+6xNGTHBST) dB
0
3
read-write
PKLIMEN
ALC Peak Limiter Enable
31
1
read-write
0
enable fast decrement when signal exceeds 87.5% of full scale (default)
#0
1
disable fast decrement when signal exceeds 87.5% of full scale
#1
PKSEL
ALC Gain Peak Detector Select
30
1
read-write
0
use absolute peak value for ALC training (default)
#0
1
use peak-to-peak value for ALC training
#1
TARGETLV
ALC Target Level
13
4
read-write
0
-28.5 dB
0
1
-27 dB
1
10
-13.5 dB
10
11
-12 dB
11
12
-10.5 dB
12
13
-9 dB
13
14
-7.5 dB
14
15
-6 dB
15
2
-25.5 dB
2
3
-24 dB
3
4
-22.5 dB
4
5
-21 dB
5
6
-19.5 dB
6
7
-18 dB
7
8
-16.5 dB
8
9
-15 dB
9
ZCEN
ALC Zero Crossing
21
1
read-write
0
zero crossing disabled
#0
1
zero crossing enabled
#1
INTCTL
ALC_INTCTL
ALC interrupt enable register
0xC
-1
read-write
n
0x0
0x0
INTEN
ALC Interrupt Enable
0
1
read-write
0
INTEN disabled
#0
1
INTEN enabled
#1
INTSTS
ALC_INTSTS
ALC interrupt register
0x8
-1
read-write
n
0x0
0x0
INTFLAG
ALC Interrupt
This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated, either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled.
Write a 1 to this register to clear.
0
1
read-write
STS
ALC_STS
ALC status register
0x4
-1
read-only
n
0x0
0x0
CLIPFLAG
Clipping Flag
Asserted when signal level is detected to be above 87.5% of full scale
0
1
read-only
NOISEF
Noise Flag
Asserted when signal level is detected to be below NGTH
1
1
read-only
P2PVAL
Peak-To-Peak Value
9 MSBs of measured peak-to-peak value
2
9
read-only
PEAKVAL
Peak Value
9 MSBs of measured absolute peak value
11
8
read-only
ANA
ANA Register Map
ANA
0x0
0x0
0x4
registers
n
0x20
0x10
registers
n
0x50
0x4
registers
n
0x60
0xC
registers
n
0x8
0x8
registers
n
0x84
0x4
registers
n
0x8C
0x14
registers
n
CAPSCNT
ANA_CAPSCNT
Capacitive Touch Sensing Count Register
0x90
-1
read-only
n
0x0
0x0
CAPSCNT
Counter Read Back Value Of Capacitive Touch Sensing Block
0
24
read-only
CAPSCTL
ANA_CAPSCTL
Capacitive Touch Sensing Control Register
0x8C
-1
read-write
n
0x0
0x0
CAPSEN
Enable
31
1
read-write
0
Disable/Reset block
#0
1
Enable Block
#1
CLKDIV
Reference Clock Divider
Circuit can be used to generate a reference clock output of SDCLK/2/(CLKDIV+1) instead of a Capacitive Touch Sensing reset signal.
8
8
read-write
CLKMODE
Reference Clock Mode
5
1
read-write
0
Capacitive Touch Sensing Mode
#0
1
Circuit is in Reference clock generation mode
#1
CYCLECNT
Number Of Relaxation Cycles
Peripheral performs 2^(CYCLECNT) relaxation cycles before generating interrupt.
2
3
read-write
INTEN
Interrupt Enable
30
1
read-write
0
Disable/Reset CAPS_IRQ interrupt
#0
1
Enable CAPS_IRQ interrupt
#1
LOWTIME
Output Low Time
Number of PCLK cycles to discharge external capacitor.
0
2
read-write
0
1cycle
0
1
2cycles
1
2
8cycles
2
3
16cycles
3
RSTCNT
Reset Count
0: Release/Activate CAP_CNT
1: Set high to reset CAP_CNT.
29
1
read-write
CURCTL0
ANA_CURCTL0
Current Source Control Register
0x8
-1
read-write
n
0x0
0x0
CURSRCEN
Enable Current Source To GPIOB[X]
Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source.
0
8
read-write
0
Disable
0
1
Enable current source to pin GPIOB[x]
1
VALSEL
Current Source Value
Select master current for source generation
8
2
read-write
0
0.5 uA
0
1
1 uA
1
2
2.5 uA
2
3
5 uA
3
CURCTL1
ANA_CURCTL1
Current Source Control Register 1
0xC
-1
read-write
n
0x0
0x0
CURSRCEN
Enable Current Source To GPIOB[X], GPIOA[X-4]
Individually enable current source to GPIO pins. Each GPIOB[11:0] and GPIOA[11:8] pin has a separate current source.
0
16
read-write
0
Disable
0
1
Enable current source to pin GPIOB[x] , x aaa 11~0 GPIOA[x-4] , x aaa 15~12
1
FQMMCNT
ANA_FQMMCNT
Frequency Measurement Count Register
0x98
-1
read-only
n
0x0
0x0
FQMMCNT
Frequency Measurement Count
When MMSTS aaa 1 and FQMMEN aaa 1, this is number of PCLK periods counted for frequency measurement.
The frequency will be PCLK aaa FQMMCNT * Fref /(CYCLESEL+1) Hz
Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz
0
16
read-only
FQMMCTL
ANA_FQMMCTL
Frequency Measurement Control Register
0x94
-1
read-write
n
0x0
0x0
CLKSEL
Reference Clock Source
00b: OSC16K,
01b: OSC32K (default),
1xb: I2S_WS - can be GPIOA[4,8,12] according to SYS_GPA_MFP register, configure I2S in SLAVE mode to enable.
0
2
read-write
CYCLESEL
Frequency Measurement Cycles
Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us), set CYCLESEL to 7, then measurement period would be 30.5175*(7+1), 244.1us.
16
8
read-write
FQMMEN
FQMMEN
31
1
read-write
0
Disable/Reset block
#0
1
Start Frequency Measurement
#1
MMSTS
Measurement Done
2
1
read-write
0
Measurement Ongoing
#0
1
Measurement Complete
#1
FQMMCYC
ANA_FQMMCYC
Frequency Measurement Cycle Register
0x9C
-1
read-write
n
0x0
0x0
FQMMCYC
Frequency Measurement Cycles
Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T aaa 30.5175µs), FQMMCYC aaa 7, then measurement period would be 30.5175*(7+1) aaa 244.1µs. This address access same register as ANA_FQMMCTL but allows access to more bits of register.
0
24
read-write
LDOPD
ANA_LDOPD
LDO Power Down Register
0x24
-1
read-write
n
0x0
0x0
DISCHAR
Discharge
1
1
read-write
0
No load on VD33
#0
1
Switch discharge resistor to VD33
#1
PD
Power Down LDO
When powered down no current delivered to VD33.
0
1
read-write
0
Enable LDO
#0
1
Power Down
#1
LDOSEL
ANA_LDOSEL
LDO Voltage Select Register
0x20
-1
read-write
n
0x0
0x0
LDOSEL
Select LDO Output Voltage
Note that maximum I/O pad operation speed only specified for voltage >2.4V.
0
2
read-write
0
3.0V
0
1
1.8V
1
2
2.4V
2
3
3.3V
3
MICBEN
ANA_MICBEN
Microphone Bias Enable Register
0x2C
-1
read-write
n
0x0
0x0
MICBEN
Enable Microphone Bias Generator
0
1
read-write
0
Powered Down
#0
1
Enabled
#1
MICBSEL
ANA_MICBSEL
Microphone Bias Select Register
0x28
-1
read-write
n
0x0
0x0
REFSEL
Select Reference Source For MICBIAS Generator
VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used as reference.
2
1
read-write
0
VMID aaa VCCA/2 is reference source
#0
1
VBG (bandgap voltage reference) is reference source
#1
VOLSEL
Select Microphone Bias Voltage
MICBMODE aaa 0
0: 90% VCCA
1: 65% VCCA
2: 75% VCCA
3: 50% VCCA
MICBMODE aaa 1
0: 2.4V
1: 1.7V
2: 2.0V
3: 1.3V
0
2
read-write
MUXCTL
ANA_MUXCTL
Analog Multiplexer Control Register
0x50
-1
read-write
n
0x0
0x0
MUXEN
Enable The Analog Multiplexer
14
1
read-write
0
All channels disabled
#0
1
Selection determined by register setting
#1
NEGINSEL
Selects Connection Of GPIOB[7:0] To PGA_INN, Negative Input Of PGA
If NEGINSEL[n] aaa 1 then GPIOB[n] is connected to PGA_INN.
0
8
read-write
PGAINSEL
Select MICP/MICN To PGA Inputs
13
1
read-write
POSINSEL
Selects Connection Of GPIOB[7,5,3,1] To PGA_INP, Positive Input Of PGA
1000b: GPIOB[7] connected to PGA_INP
0100b: GPIOB[5] connected to PGA_INP
0010b: GPIOB[3] connected to PGA_INP
0001b: GPIOB[1] connected to PGA_INP
8
4
read-write
PTATCUR
Select PTAT Current
I_PTAT, to PGA_INN, negative input to PGA, for temperature measurement.
12
1
read-write
PGACTL
ANA_PGACTL
PGA Enable Register
0x60
-1
read-write
n
0x0
0x0
BSTGAIN
Boost Stage Gain Setting
3
1
read-write
0
Gain aaa 0dB
#0
1
Gain aaa 26dB
#1
PUBOOST
Power Up Control For Boost Stage Amplifier
This amplifier must be powered up for signal path operation.
2
1
read-write
0
Power Down
#0
1
Power up
#1
PUPGA
Power Up Control For PGA Amplifier
This amplifier must be powered up for signal path operation.
1
1
read-write
0
Power Down
#0
1
Power up
#1
REFSEL
Select Reference For Analog Path
Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to VBG aaa 1.2V.
0
1
read-write
0
Select VMID voltage as analog ground reference
#0
1
Select Bandgap voltage as analog ground reference
#1
PGAGAIN
ANA_PGAGAIN
PGA Gain Select Register
0x68
-1
read-write
n
0x0
0x0
GAINREAD
Current PGA Gain Value
Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA gain.
8
6
read-write
GAINSET
Select The PGA Gain Setting
From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB.
0
6
read-write
SIGCTL
ANA_SIGCTL
Signal Path Control Register
0x64
-1
read-write
n
0x0
0x0
MUTEBST
Boost Stage Mute Control
6
1
read-write
0
Normal
#0
1
Signal Muted
#1
MUTEPGA
PGA Mute Control
5
1
read-write
0
Normal
#0
1
Signal Muted
#1
PUADCOP
Power Up ADC ΣΔ Modulator
This block must be powered up for ADC operation.
4
1
read-write
0
Power down
#0
1
Power up
#1
PUBUFADC
Power Up Control For ADC Reference Buffer
This block must be powered up for signal path operation.
2
1
read-write
0
Power down
#0
1
Power up
#1
PUBUFPGA
Power Up Control For PGA Reference Buffer
This block must be powered up for signal path operation.
1
1
read-write
0
Power down
#0
1
Power up
#1
PUCURB
Power Up Control For Current Bias Generation
This block must be powered up for signal path operation.
3
1
read-write
0
Power down
#0
1
Power up
#1
PUZCDCMP
Power Up And Enable Control For Zero Cross Detect Comparator
When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal threshold. To operate ZCD the ALC peripheral clock (CLK_APBCLK0.BQALCKEN) must also be enabled and BIQ_CTL.DLCOEFF aaa 1 to allow ZCD clocks to be generated.
0
1
read-write
0
Power down
#0
1
Power up and enable zero cross detection
#1
TRIM
ANA_TRIM
Oscillator Trim Register
0x84
-1
read-write
n
0x0
0x0
COARSE
COARSE
Current COARSE range setting of the oscillator. Read Only
8
8
read-write
OSCTRIM
Oscillator Trim
Reads current oscillator trim setting. Read Only.
0
8
read-write
SUPERFINE
Superfine
The SUPERFINE trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE trim setting between the current setting and one setting above (values 1,127) or below (values -1, -128) the current trim setting. Each step effectively moves the frequency 1/128th of the full FINE trim step size.
16
8
read-write
VMID
ANA_VMID
VMID Reference Control Register
0x0
-1
read-write
n
0x0
0x0
PDHIRES
Power Down High (360kΩ) Resistance Reference
2
1
read-write
0
Connect the High Resistance reference to VMID. Use this setting for minimum power consumption
#0
1
The High Resistance reference is disconnected from VMID. Default power down and reset condition
#1
PDLORES
Power Down Low (4.8kΩ) Resistance Reference
1
1
read-write
0
Connect the Low Resistance reference to VMID. Use this setting for fast power up of VMID. Can be turned off after 50ms to save power
#0
1
The Low Resistance reference is disconnected from VMID. Default power down and reset condition
#1
PULLDOWN
VMID Pulldown
0
1
read-write
0
Release VMID pin for reference operation
#0
1
Pull VMID pin to ground. Default power down and reset condition
#1
BIQ
BIQ Register Map
BIQ
0x0
0x0
0x3C
registers
n
0x40
0x4
registers
n
COEFF0
BIQ_COEFF0
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0
-1
read-write
n
0x0
0x0
COEFFDAT
Coefficient Data
0
32
read-write
COEFF1
0x4
-1
read-write
n
0x0
0x0
COEFF10
0x28
-1
read-write
n
0x0
0x0
COEFF11
0x2C
-1
read-write
n
0x0
0x0
COEFF12
0x30
-1
read-write
n
0x0
0x0
COEFF13
0x34
-1
read-write
n
0x0
0x0
COEFF14
0x38
-1
read-write
n
0x0
0x0
COEFF2
0x8
-1
read-write
n
0x0
0x0
COEFF3
0xC
-1
read-write
n
0x0
0x0
COEFF4
0x10
-1
read-write
n
0x0
0x0
COEFF5
0x14
-1
read-write
n
0x0
0x0
COEFF6
0x18
-1
read-write
n
0x0
0x0
COEFF7
0x1C
-1
read-write
n
0x0
0x0
COEFF8
0x20
-1
read-write
n
0x0
0x0
COEFF9
0x24
-1
read-write
n
0x0
0x0
CTL
BIQ_CTL
BIQ Control Register
0x40
-1
read-write
n
0x0
0x0
BIQEN
BIQ Filter Start To Run
0
1
read-write
0
BIQ filter is not processing
#0
1
BIQ filter is on
#1
DLCOEFF
Move BIQ Out Of Reset State
3
1
read-write
0
BIQ filter is in reset state
#0
1
When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on
#1
DPWMPUSR
DPWM Path Up Sample Rate (From SRDIV Result)
This register is only used when PATHSEL is set to 1. The operating sample rate for the biquad filter will be
(DPWMPUSR+1)*HCLK/(SRDIV+1).
Default value for this register is 3.
4
3
read-write
PATHSEL
AC Path Selection For BIQ
1
1
read-write
0
used in ADC path
#0
1
used in DPWM path
#1
PRGCOEFF
Programming Mode Coefficient Control Bit
This bit must be turned off when BIQEN in on.
2
1
read-write
0
Coefficient RAM is in normal mode
#0
1
coefficient RAM is under programming mode
#1
SRDIV
Sample Rate Divider
This register is used to program the operating sampling rate of the biquad filter. The sample rate is defined as
HCLK/(SRDIV+1).
Default to 3071 so the sampling rate is 16K when HCLK is 49.152MHz.
16
13
read-write
BODTALM
BOD Register Map
BOD
0x0
0x0
0x14
registers
n
BODCTL
BODTALM_BODCTL
Brown Out Detector Enable Register
0x4
-1
read-write
n
0x0
0x0
BODEN
BOD Enable
1xb aaa Enable continuous BOD detection.
01b aaa Enable time multiplexed BOD detection. See BODTALM_BODDTMR register.
00b aaa Disable BOD Detection.
0
2
read-write
BODIF
Current Status Of Interrupt
3
1
read-write
BODINTEN
BOD Interrupt Enable
2
1
read-write
0
Disable BOD Interrupt
#0
1
Enable BOD Interrupt
#1
BODOUT
Output Of BOD Detection Block
This signal can be monitored to determine the current state of the BOD comparator. BODOUT aaa 1 implies that VCC is less than BODVL.
4
1
read-write
BODDTMR
BODTALM_BODDTMR
Brown Out Detector Timer Register
0x10
-1
read-write
n
0x0
0x0
DURTOFF
Time BOD Detector Is Off
(DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)
0
16
read-write
DURTON
Time BOD Detector Is Active
(DURTON+1) * 100us. Minimum value is 1. (default is 400us)
16
4
read-write
BODSEL
BODTALM_BODSEL
Brown Out Detector Select Register
0x0
-1
read-write
n
0x0
0x0
BODHYS
BOD Hysteresis
3
1
read-write
0
Hysteresis Disabled
#0
1
Enable Hysteresis of BOD detection
#1
BODRANGE
Range
Range setting for BODVL
4
1
read-write
BODVL
BOD Voltage Level
RANGE aaa 0
111b aaa 4.6V
110b aaa 3.0V
101b aaa 2.8V
100b aaa 2.65V
011b aaa 2.5V
010b aaa 2.4V
001b aaa 2.2V
000b aaa 2.1V
RANGE aaa 1
111b aaa 4.2V
110b aaa 3.9V
101b aaa 3.8V
100b aaa 3.7V
011b aaa 3.6V
010b aaa 3.4V
001b aaa 3.2V
00 000b aaa 3.1V
0
3
read-write
TALMCTL
BODTALM_TALMCTL
Temperature Alarm Enable Register
0xC
-1
read-write
n
0x0
0x0
TALMEN
TALARM Enable
0
1
read-write
0
Disable TALARM Detection
#0
1
Enable TALARM Detection
#1
TALMIEN
TALARM Interrupt Enable
2
1
read-write
0
Disable TALARM Interrupt
#0
1
Enable TALARM Interrupt
#1
TALMIF
Current Status Of Interrupt
Latched whenever a Temperature Sense event occurs and IE aaa 1. Write '1' to clear.
3
1
read-write
TALMOUT
Output Of TALARM Block
Can be polled to determine whether TALARM active (be 1).
1
1
read-write
TALMSEL
BODTALM_TALMSEL
Temperature Alarm Select Register
0x8
-1
read-write
n
0x0
0x0
TALMVL
Temperature Alarm Sense Level
0000:105C
0001:115C
0010:125C
0100:135C
1000:145C
0
4
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x2C
registers
n
AHBCLK
CLK_AHBCLK
AHB Device Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
HCLKEN
CPU Clock Enable (HCLK)
Must be left as '1' for normal operation.
0
1
read-write
ISPCKEN
Flash ISP Controller Clock Enable Control
2
1
read-write
0
To disable the Flash ISP engine clock
#0
1
To enable the Flash ISP engine clock
#1
PDMACKEN
PDMA Controller Clock Enable Control
1
1
read-write
0
To disable the PDMA engine clock
#0
1
To enable the PDMA engine clock
#1
APBCLK0
CLK_APBCLK0
APB Device Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ACMPCKEN
Analog Comparator Clock Enable Control
22
1
read-write
0
Disable
#0
1
Enable
#1
ADCCKEN
Audio Analog-Digital-Converter (ADC) Clock Enable Control
28
1
read-write
0
Disable
#0
1
Enable
#1
ANACKEN
Analog Block Clock Enable Control
30
1
read-write
0
Disable
#0
1
Enable
#1
BFALCKEN
Biquad Filter And Automatic Level Control Block Clock Enable Control
18
1
read-write
0
Disable
#0
1
Enable
#1
CRCCKEN
Cyclic Redundancy Check Block Clock Enable Control
19
1
read-write
0
Disable
#0
1
Enable
#1
DPWMCKEN
Differential PWM Speaker Driver Clock Enable Control
13
1
read-write
0
Disable
#0
1
Enable
#1
I2C0CKEN
I2C0 Clock Enable Control
8
1
read-write
0
Disable
#0
1
Enable
#1
I2S0CKEN
I2S Clock Enable Control
29
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH01CKEN
PWM0CH0 And PWM0CH1 Block Clock Enable Control
20
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH23CKEN
PWM0CH2 And PWM0CH3 Block Clock Enable Control
21
1
read-write
0
Disable
#0
1
Enable
#1
PWM1CH01CKEN
PWM1CH0 And PWM1CH1 Clock Enable Control
31
1
read-write
0
Disable
#0
1
Enable
#1
RTCCKEN
Real-Time-Clock APB Interface Clock Control
5
1
read-write
0
Disable
#0
1
Enable
#1
SBRAMCKEN
Standby RAM Clock Enable Control
26
1
read-write
0
Disable
#0
1
Enable
#1
SPI0CKEN
SPI0 Clock Enable Control
12
1
read-write
0
Disable
#0
1
Enable
#1
TMR0CKEN
Timer0 Clock Enable Control
6
1
read-write
0
Disable
#0
1
Enable
#1
TMR1CKEN
Timer1 Clock Enable Control
7
1
read-write
0
Disable
#0
1
Enable
#1
UARTCKEN
UART Clock Enable Control
16
1
read-write
0
Disable
#0
1
Enable
#1
WDTCKEN
Watchdog Clock Enable Control
4
1
read-write
0
Disable
#0
1
Enable
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register
0x18
-1
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source
The ADC clock frequency aaa (ADC clock source frequency ) / (ADC_N + 1)
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
The HCLK clock frequency aaa (HCLK clock source frequency) / (HCLK_N + 1)
0
4
read-write
UARTDIV
UART Clock Divide Number From UART Clock Source
The UART clock frequency aaa (UART clock source frequency ) / (UART_N + 1)
8
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Select
Ensure that related clock sources (pre-select and new-select) are enabled before updating register.
These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
000 aaa clock source from internal OSC48M oscillator.
001 aaa clock source from external 32kHz crystal clock
010 aaa clock source from internal 16kHz oscillator clock
100 aaa CLK2X a frequency doubled output of OSC48M, only available on M and H speed grade devices.
Others aaa RESERVED
0
3
read-write
HIRCFSEL
OSC48M Frequency Select
Determines which trim setting to use for OSC48M internal oscillator. Oscillator is factory trimmed within 1% to:
0: 49.152MHz (Default)
1: 32.768MHz
2: 36.864MHz
6
2
read-write
STCLKSEL
MCU Cortex_M0 SYST Clock Source Select
These bits are protected, to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
000 aaa clock source from 16kHz internal clock
001 aaa clock source from external 32kHz crystal clock
010 aaa clock source from 16kHz internal oscillator divided by 2
011 aaa clock source from OSC49M internal oscillator divided by 2
1xx aaa clock source from HCLK÷2 (Default)
Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR must be set to 0.
3
3
read-write
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
DPWMCKSEL
Differential Speaker Driver PWM Clock Source Select
4
1
read-write
0
OSC48M clock
#0
1
2x OSC48M clock
#1
PWM0CH01CKSEL
PWM0CH0 And PWM0CH1 Clock Source Select
PWM0CH0 and PWM0CH1 uses the same clock source, and pre-scaler
28
2
read-write
0
clock source from internal 16kHz oscillator
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK
#10
3
clock source from internal OSC48M oscillator clock
#11
PWM0CH23CKSEL
PWM0CH2 And PWM0CH3 Clock Source Select
PWM0CH2 and PWM0CH3 uses the same clock source, and pre-scaler
30
2
read-write
0
clock source from internal 16kHz oscillator
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK
#10
3
clock source from internal OSC48M oscillator clock
#11
TMR0SEL
TIMER0 Clock Source Select
000 aaa clock source from internal 16kHz oscillator
001 aaa clock source from external 32kHz crystal clock
010 aaa clock source from HCLK
011 aaa clock source from external pin (GPIOA[14])
1xx aaa clock source from internal OSC48M oscillator clock
8
3
read-write
TMR1SEL
TIMER1 Clock Source Select
000 aaa clock source from internal 16kHz oscillator
001 aaa clock source from external 32kHz crystal clock
010 aaa clock source from HCLK
011 aaa clock source from external pin (GPIOA[15])
1xx aaa clock source from internal OSC48M oscillator clock
12
3
read-write
WDTSEL
WDT Clock Source Select
0
2
read-write
0
clock source from internal OSC48M oscillator clock
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK/2048 clock
#10
3
clock source from internal 16kHz oscillator clock
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
I2S0SEL
I2S0 Clock Source Select
0
2
read-write
0
clock source from internal 16kHz oscillator
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK
#10
3
clock source from internal OSC48M oscillator clock
#11
PWM1CH01CKSEL
PWM1CH0 And PWM1CH1 Clock Source Select
PWM1CH0 and PWM1CH1 uses the same clock source, and pre-scaler
4
2
read-write
0
clock source from internal 16kHz oscillator
#00
1
clock source from external 32kHz crystal clock
#01
2
clock source from HCLK
#10
3
clock source from internal OSC48M oscillator clock
#11
DBGPD
CLK_DBGPD
Debug Port Power Down Disable Register
0x28
-1
read-write
n
0x0
0x0
DISPDREQ
Disable Power Down
0
1
read-write
0
Enable power down requests
#0
1
Disable power down requests
#1
ICECLKST
ICECLKST Pin State
Read Only. Current state of ICE_CLK pin.
6
1
read-write
ICEDATST
ICEDATST Pin State
Read Only. Current state of ICE_DAT pin.
7
1
read-write
DPDSTATE
CLK_DPDSTATE
Deep Power Down State Register
0xC
-1
read-write
n
0x0
0x0
DPDSTSRD
DPD State Read Back
Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
8
8
read-write
DPDSTSWR
DPD State Write
To set the CLK_DPDSTATE register, write value to this register. Data is latched on next DPD event.
0
8
read-write
PWRCTL
CLK_PWRCTL
System Power Control Register
0x0
-1
read-write
n
0x0
0x0
DPDEN
Deep Power Down (DPD) Bit
Set to '1' and issue WFI/WFE instruction to enter DPD mode.
11
1
read-write
HIRCEN
OSC49M Oscillator Enable Bit
2
1
read-write
0
disable
#0
1
enable (default)
#1
LIRCDPDEN
OSC16K Enabled Control
Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled, device cannot wake from DPD with SELWKTMR delay.
17
1
read-write
0
enabled
#0
1
disabled
#1
LIRCEN
OSC16K Oscillator Enable Bit
3
1
read-write
0
disable
#0
1
enable (default)
#1
LXTEN
External 32.768 KHz Crystal Enable Bit
1
1
read-write
0
disable (default)
#0
1
enable
#1
PORWKF
POR Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.
26
1
read-write
SELWKTMR
Select Wakeup Timer
SELWKTMR[0] aaa 1: WAKEUP after 128 OSC16K clocks (12.8 ms)
SELWKTMR[1] aaa 1: WAKEUP after 256 OSC16K clocks (25.6 ms)
SELWKTMR[2] aaa 1: WAKEUP after 512 OSC16K clocks (51.2 ms)
SELWKTMR[3] aaa 1: WAKEUP after 1024 OSC16K clocks (102.4ms)
20
4
read-write
SPDEN
Standby Power Down (SPD) Bit
Set to '1' and issue WFI/WFE instruction to enter SPD mode.
10
1
read-write
STOP
Stop
RESERVED - do not set to '1'
9
1
read-write
TMRWKF
Timer Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 16Khz oscillator. Flag is cleared when DPD mode is entered.
25
1
read-write
WKPINEN
Wakeup Pin Enabled Control
Determines whether WAKEUP pin is enabled in DPD mode.
16
1
read-write
0
enabled
#0
1
disabled
#1
WKPINWKF
Pin Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
24
1
read-write
WKTMRSTS
Current Wakeup Timer Setting
Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.
28
4
read-write
PWRSTSF
CLK_PWRSTSF
Power State Flag Register
0x24
-1
read-write
n
0x0
0x0
DSF
Deep Sleep Flag
This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
0
1
read-write
SPDF
Powered Down Flag
This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag.
2
1
read-write
STOPF
Stop Flag
This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
1
1
read-write
SLEEPCTL
CLK_SLEEPCTL
Sleep Clock Source Select Register
0x20
-1
read-write
n
0x0
0x0
ACMPCKEN
Analog Comparator Sleep Clock Enable Control
22
1
read-write
0
Disable
#0
1
Enable
#1
ADCCKEN
Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control
28
1
read-write
0
Disable
#0
1
Enable
#1
ANACKEN
Analog Block Sleep Clock Enable Control
30
1
read-write
0
Disable
#0
1
Enable
#1
BQALCKEN
Biquad Filter/ALC Block Sleep Clock Enable Control
18
1
read-write
0
Disable
#0
1
Enable
#1
CRCCKEN
Cyclic Redundancy Check Sleep Block Clock Enable Control
19
1
read-write
0
Disable
#0
1
Enable
#1
DPWMCKEN
Differential PWM Speaker Driver Sleep Clock Enable Control
13
1
read-write
0
Disable
#0
1
Enable
#1
HCLKCKEN
CPU Clock Sleep Enable (HCLK)
Must be left as '1' for normal operation.
0
1
read-write
0
Disable
#0
1
Enable
#1
I2C0CKEN
I2C0 Sleep Clock Enable Control
8
1
read-write
0
Disable
#0
1
Enable
#1
I2SCKEN
I2S Sleep Clock Enable Control
29
1
read-write
0
Disable
#0
1
Enable
#1
ISPCKEN
Flash ISP Controller Sleep Clock Enable Control
2
1
read-write
0
Disable
#0
1
Enable
#1
PDMACKEN
PDMA Controller Sleep Clock Enable Control
1
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH01CKEN
PWM0CH0 And PWM0CH1 Block Sleep Clock Enable Control
20
1
read-write
0
Disable
#0
1
Enable
#1
PWM0CH23CKEN
PWM0CH2 And PWM0CH3 Block Sleep Clock Enable Control
21
1
read-write
0
Disable
#0
1
Enable
#1
PWM1CH01CKEN
PWM1CH0 And PWM1CH1 Block Sleep Clock Enable Control
31
1
read-write
0
Disable
#0
1
Enable
#1
RTCCKEN
Real-Time- Sleep Clock APB Interface Clock Control
5
1
read-write
0
Disable
#0
1
Enable
#1
SBRAMCKEN
Standby RAM Sleep Clock Enable Control
26
1
read-write
0
Disable
#0
1
Enable
#1
SPI0CKEN
SPI0 Sleep Clock Enable Control
12
1
read-write
0
Disable
#0
1
Enable
#1
TMR0CKEN
Timer0 Sleep Clock Enable Control
6
1
read-write
0
Disable
#0
1
Enable
#1
TMR1CKEN
Timer1 Sleep Clock Enable Control
7
1
read-write
0
Disable
#0
1
Enable
#1
UARTCKEN
UART Sleep Clock Enable Control
16
1
read-write
0
Disable
#0
1
Enable
#1
WDTCKEN
Watchdog Sleep Clock Enable Control
4
1
read-write
0
Disable
#0
1
Enable
#1
DPWM
DPWM Register Map
DPWM
0x0
0x0
0x14
registers
n
CTL
DPWM_CTL
DPWM Control Register
0x0
-1
read-write
n
0x0
0x0
DEADTIME
DPWM Driver Deadtime Control
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
3
1
read-write
DITHEREN
DPWM Signal Dither Control
To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither:
4
2
read-write
0
No dither
0
1
+/- 1 bit dither
1
3
+/- 2 bit dither
3
DPWMEN
DPWM Enable
6
1
read-write
0
Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset)
#0
1
Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO
#1
MODUFRQ
DPWM Modulation Frequency
This parameter controls the carrier modulation frequency of the PWM signal as a proportion of DPWM_CLK.
MODUFRQ : DPWM_CLK Division : Frequency for DPWM_CLK aaa 98.304MHZ
0 : 228 : 431158
1 : 156 : 630154
2 : 76 : 1293474
3 : 52 : 1890462
4 : 780 : 126031
5 : 524 : 187603
6 : 396 : 248242
7 : 268 : 366806
0
3
read-write
DATA
DPWM_DATA
DPWM DATA FIFO Input
0xC
-1
write-only
n
0x0
0x0
INDATA
DPWM FIFO Audio Data Input
A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
0
16
write-only
DMACTL
DPWM_DMACTL
DPWM PDMA Control Register
0x8
-1
read-write
n
0x0
0x0
DMAEN
Enable DPWM DMA Interface
0
1
read-write
0
Disable PDMA. No requests will be made to PDMA controller
#0
1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
#1
STS
DPWM_STS
DPWM DATA FIFO Status Register
0x4
-1
read-only
n
0x0
0x0
EMPTY
FIFO Empty
1
1
read-only
0
FIFO is not empty
#0
1
FIFO is empty
#1
FULL
FIFO Full
0
1
read-only
0
FIFO is not full
#0
1
FIFO is full
#1
ZOHDIV
DPWM_ZOHDIV
DPWM Zero Order Hold Division Register
0x10
-1
read-write
n
0x0
0x0
ZOHDIV
DPWM Zero Order Hold, Down-Sampling Divisor
The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula:
Fs aaa HCLK/ZOHDIV/64
Valid range is 1 to 255. Default is 48, which gives a sample rate of 16kHz for a 49.152MHz (default) HCLK.
0
8
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x18
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address
This register reports the data flash starting address. It is a read only register.
Data flash size is defined by user configuration register content is loaded from Config1 when chip is reset.
0
32
read-only
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPADDR [1:0] must be 00b for correct ISP operation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP Command
Operation Mode : CMD
Standby : 0x3X
Read : 0x00
Program : 0x21
Page Erase : 0x22
Read CID : 0x0B
Read DID : 0x0C
0
6
read-write
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
BS
Boot Select
Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event.
1
1
read-write
0
APROM
#0
1
LDROM
#1
CACHEDIS
Cache Disable
When set to 1, caching of flash memory reads is disabled.
21
1
read-write
CFGUEN
CONFIG Update Enable
When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
4
1
read-write
0
Disable
#0
1
Enable
#1
ISPEN
ISP Enable
0
1
read-write
0
Disable ISP function
#0
1
Enable ISP function
#1
ISPFF
ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) Destination address is illegal, such as over an available range.
Write 1 to clear.
6
1
read-write
LDUEN
LDROM Update Enable
LDROM update enable bit.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
SWRST
Software Reset
Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset.
7
1
read-write
WAITCFG
Flash Access Wait State Configuration
For M and H speed grade parts this sets the access speed to the flash memory.
0x00: Three wait states. HCLK > 72MHz
0x01: Two wait states. 72MHz > HCLK > 50MHz
0x02: One wait state. HCLK
16
3
read-write
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data Register
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
0
32
read-write
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.
After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity.
This is a protected register, user must first follow the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)) to gain access.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is on going
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x180
0x4
registers
n
0x40
0x24
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-Bounce Sampling Cycle Selection
For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce clocks. For example if DBCLKSRC aaa 6, then interrupt is sampled every 2^6 aaa 64 de-bounce clocks. If DBCLKSRC is 16KHz oscillator this would be a 64ms de-bounce.
0
4
read-write
DBCLKSRC
De-Bounce Counter Clock Source Select
4
1
read-write
0
De-bounce counter clock source is HCLK
#0
1
De-bounce counter clock source is the internal 16 kHz clock
#1
ICLKON
Interrupt Clock On Mode
Set this bit 0 will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.
5
1
read-write
0
disable the clock if the GPIOx[n] interrupt is disabled
#0
1
Interrupt generation clock always active
#1
PA_DATMSK
PA_DATMSK
GPIO Port A Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK
Port [A/B] Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is writing protected.
0
16
read-write
0
The corresponding Px_DOUT[n] bit can be updated
0
1
The corresponding Px_DOUT[n] bit is read only
1
PA_DBEN
PA_DBEN
GPIO Port A De-bounce Enable
0x14
-1
read-write
n
0x0
0x0
DBEN
Port [A/B] De-Bounce Enable Control
DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register.
The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
0
16
read-write
0
The bit[n] de-bounce function is disabled
0
1
The bit[n] de-bounce function is enabled
1
PA_DINOFF
PA_DINOFF
GPIO Port A Pin Input Disable
0x4
-1
read-write
n
0x0
0x0
DINOFF
GPIOx Pin[N] OFF Digital Input Path Enable
16
16
read-write
0
Enable IO digital input path (Default)
0
1
Disable IO digital input path (low leakage mode)
1
PA_DOUT
PA_DOUT
GPIO Port A Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Px Pin[N] Output Value
Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
0
16
read-write
0
GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set
0
1
GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set
1
PA_INTEN
PA_INTEN
GPIO Port A Interrupt Enable
0x1C
-1
read-write
n
0x0
0x0
FLIEN
Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low
FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level low will generate an interrupt.
If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt.
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
0
16
read-write
0
Disable GPIOx[n] for low-level or high-to-low interrupt
0
1
Enable GPIOx[n] for low-level or high-to-low interrupt
1
RHIEN
Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High
RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level high will generate an interrupt.
If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt.
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
16
16
read-write
0
Disable GPIOx[n] for level-high or low-to-high interrupt
0
1
Enable GPIOx[n] for level-high or low-to-high interrupt
1
PA_INTSRC
PA_INTSRC
GPIO Port A Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC
Port [A/B] Interrupt Source Flag
Read :
1 aaa Indicates GPIOx[n] generated an interrupt
0 aaa No interrupt from GPIOx[n]
Write :
1 aaa Clear the corresponding pending interrupt.
0 aaa No action
0
16
read-write
PA_INTTYPE
PA_INTTYPE
GPIO Port A Interrupt Trigger Type
0x18
-1
read-write
n
0x0
0x0
TYPE
Port [A/B] Edge Or Level Detection Interrupt Trigger Type
TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt
If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur
0
16
read-write
0
Edge triggered interrupt
0
1
Level triggered interrupt
1
PA_MODE
PA_MODE
GPIO Port A Pin I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
0
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE1
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
2
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE10
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
20
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE11
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
22
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE12
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
24
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE13
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
26
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE14
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
28
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE15
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
30
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE2
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
4
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE3
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
6
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE4
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
8
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE5
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
10
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE6
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
12
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE7
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
14
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE8
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
16
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
MODE9
Px I/O Pin[N] Mode Control
Determine each I/O type of GPIOx pins
18
2
read-write
0
GPIO port [n] pin is in INPUT mode
#00
1
GPIO port [n] pin is in OUTPUT mode
#01
2
GPIO port [n] pin is in Open-Drain mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
GPIO Port A Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN
Port [A/B] Pin Values
The value read from each of these bit reflects the actual status of the respective GPIO pin
0
16
read-only
PB_DATMSK
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
0x58
-1
read-write
n
0x0
0x0
PB_MODE
0x40
-1
read-write
n
0x0
0x0
PB_PIN
0x50
-1
read-write
n
0x0
0x0
I2C
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
ADDR0
I2C_ADDR0
I2C Slave address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address Register
The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched.
1
7
read-write
GC
General Call Function
0
1
read-write
0
Disable General Call Function
#0
1
Enable General Call Function
#1
ADDR1
0x18
-1
read-write
n
0x0
0x0
ADDR2
0x1C
-1
read-write
n
0x0
0x0
ADDR3
0x20
-1
read-write
n
0x0
0x0
ADDRMSK0
I2C_ADDRMSK0
I2C Slave address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSKx1
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
1
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx2
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
2
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx3
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
3
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx4
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
4
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx5
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
5
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx6
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
6
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSKx7
I2C Address Mask Register
I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.
7
1
read-write
0
Mask disable
#0
1
Mask enable (the received corresponding address bit is don't care.)
#1
ADDRMSK1
0x28
-1
read-write
n
0x0
0x0
ADDRMSK2
0x2C
-1
read-write
n
0x0
0x0
ADDRMSK3
0x30
-1
read-write
n
0x0
0x0
CLKDIV
I2C_CLKDIV
I2C clock divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Register
The I2C clock rate bits: Data Baud Rate of I2C aaa PCLK /(4x(I2C_CLKDIV+1)).
0
8
read-write
CTL
I2C_CTL
I2C Control Register
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
1. A slave is acknowledging the address sent from master,
2. The receiver devices are acknowledging the data sent by transmitter.
When AA aaa 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
2
1
read-write
I2CEN
I2C Controller Enable Bit
Set to enable I2C serial function block.
6
1
read-write
0
Disable
#0
1
Enable
#1
INTEN
Enable Interrupt
7
1
read-write
0
Disable interrupt
#0
1
Enable interrupt CPU
#1
SI
I2C Interrupt Flag
When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit EI (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.
3
1
read-write
STA
I2C START Control Bit
Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device.
4
1
read-write
DAT
I2C_DAT
I2C DATA Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data Register
During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
0
8
read-write
STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Register
The status register of I2C:
The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2C_STATUS contains F8H, no serial interrupt is requested. All other I2C_STATUS values correspond to defined I2C states. When each of these states is entered, a status interrupt is requested (SI aaa 1). A valid status code is present in I2C_STATUS one PCLK cycle after SI is set by hardware and is still present one PCLK cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
0
8
read-only
TOCTL
I2C_TOCTL
I2C Time out control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-Out Counter Input Clock Divide By 4
When enabled, the time-out clock is PCLK/4.
1
1
read-write
0
Disable
#0
1
Enable
#1
TOCEN
Time-Out Counter Control Bit
When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disable
#0
1
Enable
#1
TOIF
Time-Out Flag
0
1
read-write
0
No time-out
#0
1
Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear.
#1
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
CLKDIV
I2S_CLKDIV
I2S Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider
If I2S operates in master mode, bit clock is provided by ISD9160. Software can program these bits to generate bit clock frequency for the desired sample rate.
For sample rate Fs, the desired bit clock frequency is:
F(BCLK) aaa Fs x Word_width_in_bytes x 16
For example if Fs aaa 16kHz, and word width is 2-bytes (16bit) then desired bit clock frequency is 512kHz.
The bit clock frequency is given by:
F(BCLK) aaa F(I2S_CLKDIV) / 2x(BCLKDIV+1)
Or,
BCLKDIV aaa F(I2S_CLKDIV) / (2 x F(BCLK)) -1
So if F(I2S_CLKDIV) aaa HCLK aaa 49.152MHz , desired F(BCLK) aaa 512kHz then BCLKDIV aaa 47
8
8
read-write
MCLKDIV
Master Clock Divider
ISD9160 can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLKDIV clock input, otherwise MCLK frequency is given by:
F(MCLK) aaa F(I2S_CLKDIV) / (2xMCLKDIV)
Or,
MCLKDIV aaa F(I2S_CLKDIV) / (2 x F(MCLK))
If the desired MCLK frequency is 254Fs and Fs aaa 16kHz then MCLKDIV aaa 6
0
3
read-write
CTL
I2S_CTL
I2S Control Register
0x0
-1
read-write
n
0x0
0x0
FORMAT
Data Format
See Figure 561 and Figure 562 for timing differences.
7
1
read-write
0
I2S data format
#0
1
MSB justified data format
#1
I2SEN
Enable I2S Controller
0
1
read-write
0
Disable
#0
1
Enable
#1
LZCEN
Left Channel Zero Cross Detect Enable
If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCIF flag in I2S_STATUS register will be set to 1.
17
1
read-write
0
Disable left channel zero cross detect
#0
1
Enable left channel zero cross detect
#1
MCLKEN
Master Clock Enable
The ISD9160 can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the I2S_CLKDIV.MCLKDIV[2:0] register.
15
1
read-write
0
Disable master clock
#0
1
Enable master clock
#1
MONO
Monaural Data
This parameter sets whether mono or stereo data is processed. See Figure 563 for details of how data is formatted in transmit and receive FIFO.
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable
3
1
read-write
0
Transmit data is shifted from FIFO
#0
1
Transmit channel zero
#1
RXCLR
Clear Receive FIFO
Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically when clear operation complete.
19
1
read-write
RXEN
Receive Enable
2
1
read-write
0
Disable data receive
#0
1
Enable data receive
#1
RXPDMAEN
Enable Receive DMA
When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
21
1
read-write
0
Disable RX DMA
#0
1
Enable RX DMA
#1
RXTH
Receive FIFO Threshold Level
When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set.
12
3
read-write
RZCEN
Right Channel Zero Cross Detect Enable
If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
16
1
read-write
0
Disable right channel zero cross detect
#0
1
Enable right channel zero cross detect
#1
SLAVE
Slave Mode
I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from ISD9160. In slave mode, I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXCLR
Clear Transmit FIFO
Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed.
This bit is cleared by hardware automatically when clear operation complete.
18
1
read-write
TXEN
Transmit Enable
1
1
read-write
0
Disable data transmit
#0
1
Enable data transmit
#1
TXPDMAEN
Enable Transmit DMA
When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
20
1
read-write
0
Disable TX DMA
#0
1
Enable TX DMA
#1
TXTH
Transmit FIFO Threshold Level
If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.
9
3
read-write
WDWIDTH
Word Width
This parameter sets the word width of audio data. See Figure 563 for details of how data is formatted in transmit and receive FIFO.
4
2
read-write
0
data is 8 bit
#00
1
data is 16 bit
#01
2
data is 24 bit
#10
3
data is 32 bit
#11
IEN
I2S_IEN
I2S Interrupt Enable Register
0x8
-1
read-write
n
0x0
0x0
LZCIEN
Left Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and left channel has zero cross event
12
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXOVIEN
Receive FIFO Overflow Interrupt Enable
1
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt
Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].
2
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RXUDIEN
Receive FIFO Underflow Interrupt Enable
If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1.
0
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and right channel has zero cross event
11
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXOVIEN
Transmit FIFO Overflow Interrupt Enable
Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
9
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable
Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].
10
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
TXUDIEN
Transmit FIFO Underflow Interrupt Enable
Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
8
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
RX
I2S_RX
I2S Receive FIFO Register
0x14
-1
read-only
n
0x0
0x0
RX
Receive FIFO Register (Read Only)
A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT.
0
32
read-only
STATUS
I2S_STATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SIF
I2S Interrupt (Read Only)
This bit is set if any enabled I2S interrupt is active.
0
1
read-only
0
No I2S interrupt
#0
1
I2S interrupt active
#1
LZCIF
Left Channel Zero Cross Flag (Write '1' To Clear, Or Clear LZCEN)
23
1
read-write
0
No zero cross detected
#0
1
Left channel zero cross is detected
#1
RIGHT
Right Channel Active (Read Only)
This bit indicates current data being transmitted/received belongs to right channel
3
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Level (Read Only)
24
4
read-only
RXEMPTY
Receive FIFO Empty (Read Only)
This is set when receive FIFO is empty.
12
1
read-only
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full (Read Only)
This bit is set when receive FIFO is full.
11
1
read-only
0
Not full
#0
1
Full
#1
RXIF
I2S Receive Interrupt (Read Only)
This indicates that there is an active receive interrupt source. This could be RXOVIF, RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
1
1
read-only
0
No receive interrupt
#0
1
Receive interrupt occurred
#1
RXOVIF
Receive FIFO Overflow Flag (Write '1' To Clear)
This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.
9
1
read-write
0
No overflow
#0
1
Overflow
#1
RXTHIF
Receive FIFO Threshold Flag (Read Only)
When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.
10
1
read-only
0
Data word(s) in FIFO is less than threshold level
#0
1
Data word(s) in FIFO is greater than or equal to threshold level
#1
RXUDIF
Receive FIFO Underflow Flag (Write '1' To Clear)
This flag is set if attempt is made to read receive FIFO while it is empty.
8
1
read-write
0
No underflow
#0
1
Underflow
#1
RZCIF
Right Channel Zero Cross Flag (Write '1' To Clear, Or Clear RZCEN)
22
1
read-write
0
No zero cross
#0
1
Right channel zero cross is detected
#1
TXBUSY
Transmit Busy (Read Only)
This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register.
21
1
read-only
0
Transmit shift register is empty
#0
1
Transmit shift register is busy
#1
TXCNT
Transmit FIFO Level (Read Only)
28
4
read-only
TXEMPTY
Transmit FIFO Empty (Read Only)
This is set when transmit FIFO is empty.
20
1
read-only
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full (Read Only)
This bit is set when transmit FIFO is full.
19
1
read-only
0
Not full
#0
1
Full
#1
TXIF
I2S Transmit Interrupt (Read Only)
This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
2
1
read-only
0
No transmit interrupt
#0
1
Transmit interrupt occurred
#1
TXOVIF
Transmit FIFO Overflow Flag (Write '1' To Clear)
This flag is set if data is written to transmit FIFO when it is full.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Flag (Read Only)
When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold exceeded.
18
1
read-only
0
Data word(s) in FIFO is greater than threshold level
#0
1
Data word(s) in FIFO is less than or equal to threshold level
#1
TXUDIF
Transmit FIFO Underflow Flag (Write '1' To Clear)
This flag is set if I2S controller requests data when transmit FIFO is empty.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX
I2S_TX
I2S Transmit FIFO Register
0x10
-1
write-only
n
0x0
0x0
TX
Transmit FIFO Register (Write Only)
A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT.
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity Register
0x0
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (RESERVED) Interrupt Source Identity Register
0x28
-1
read-only
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
IRQ11 (RESERVED) Interrupt Source Identity Register
0x2C
-1
read-only
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) Interrupt Source Identity Register
0x30
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART0_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (RESERVED) Interrupt Source Identity Register
0x34
-1
read-only
n
0x0
0x0
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) Interrupt Source Identity Register
0x38
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
0
3
read-only
IRQ15_SRC
IRQ15_SRC
IRQ15 (RESERVED) Interrupt Source Identity Register
0x3C
-1
read-only
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (RESERVED) Interrupt Source Identity Register
0x40
-1
read-only
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (RESERVED) Interrupt Source Identity Register
0x44
-1
read-only
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity Register
0x48
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2C0_INT
0
3
read-only
IRQ19_SRC
IRQ19_SRC
IRQ19 (RESERVED) Interrupt Source Identity Register
0x4C
-1
read-only
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity Register
0x4
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
0
3
read-only
IRQ20_SRC
IRQ20_SRC
IRQ20 (RESERVED) Interrupt Source Identity Register
0x50
-1
read-only
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
IRQ21 (TALARM) Interrupt Source Identity Register
0x54
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TALARM_INT
0
3
read-only
IRQ22_SRC
IRQ22_SRC
IRQ22 (RESERVED ) Interrupt Source Identity Register
0x58
-1
read-only
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
IRQ23 (RESERVED) Interrupt Source Identity Register
0x5C
-1
read-only
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
IRQ24 (RESERVED) Interrupt Source Identity Register
0x60
-1
read-only
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity Register
0x64
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TALARM_INT
0
3
read-only
IRQ26_SRC
IRQ26_SRC
IRQ26 (PDMA) Interrupt Source Identity Register
0x68
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
0
3
read-only
IRQ27_SRC
IRQ27_SRC
IRQ27 (I2S) Interrupt Source Identity Register
0x6C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: I2S_INT
0
3
read-only
IRQ28_SRC
IRQ28_SRC
IRQ28 (CAPS) Interrupt Source Identity Register
0x70
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: CAPS_INT
0
3
read-only
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity Register
0x74
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity Register
0x8
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
0
3
read-only
IRQ30_SRC
IRQ30_SRC
IRQ30 (RESERVED) Interrupt Source Identity Register
0x78
-1
read-only
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
IRQ31 (RTC) Interrupt Source Identity Register
0x7C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
0
3
read-only
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity Register
0xC
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: INT0_INT
0
3
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (GPA/B) Interrupt Source Identity Register
0x10
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (ALC) Interrupt Source Identity Register
0x14
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ALC_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWM0) Interrupt Source Identity Register
0x18
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM0_INT
0
3
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (PWM1) Interrupt Source Identity Register
0x1C
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM1_INT
0
3
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity Register
0x20
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR0_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity Register
0x24
-1
read-only
n
0x0
0x0
INT_SRC
Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TMR1_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identify Register
0x84
-1
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Test Mode
In Normal mode (NMI_SEL register bit [7] aaa 0) The device collects interrupts from each peripheral and synchronizes them to interrupt the Cortex-M0.
In Test mode (NMI_SEL register bit [7] aaa 1), the interrupts from peripherals are blocked, and the interrupts are replaces by MCU_IRQ[31:0].
When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].
When MCU_IRQ[n] is 1 (meaning an interrupt is asserted) writing MCU_bit[n] '1' will clear the interrupt
Writing MCU_IRQ[n] 0 : has no effect.
0
32
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
-1
read-write
n
0x0
0x0
IRQ_TM
IRQ Test Mode
If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
7
1
read-write
NMI_SEL
NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
The NMI_SEL bit[4:0] used to select the NMI interrupt source
0
5
read-write
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x100
0x28
registers
n
0x134
0x8
registers
n
0x200
0x28
registers
n
0x234
0x8
registers
n
0x300
0x28
registers
n
0x334
0x8
registers
n
0x34
0x8
registers
n
0xE00
0x8
registers
n
0xE0C
0x4
registers
n
0xE14
0x4
registers
n
0xE1C
0xC
registers
n
0xE80
0xC
registers
n
0xF00
0x8
registers
n
0xF0C
0x4
registers
n
CH0IF
PDMA_CH0IF
PDMA Interrupt Status Register of Channel 0
0x24
-1
read-write
n
0x0
0x0
INTSTS
Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
31
1
read-only
TXABTIF
PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
TXOKIF
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
1
1
read-write
0
Transfer ongoing or Idle
#0
1
Transfer Complete
#1
WAIF
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
0001 aaa Current transfer finished flag (CURBC aaaaaa 0).
0100 aaa Current transfer half complete flag (CURBC aaaaaa BYTECNT/2).
8
4
read-write
CH1IF
0x124
-1
read-write
n
0x0
0x0
CH2IF
0x224
-1
read-write
n
0x0
0x0
CH3IF
0x324
-1
read-write
n
0x0
0x0
CRCBC
PDMA_CRCBC
CRC DMA Transfer Byte Count Register
0xE0C
-1
read-write
n
0x0
0x0
BYTECNT
CRC DMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of CRC DMA.
0
16
read-write
CRCCBC
PDMA_CRCCBC
CRC DMA Current Transfer Byte Count Register
0xE1C
-1
read-only
n
0x0
0x0
CURBC
CRC DMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of CRC_DMA.
Note: CRCRST will clear this register value.
0
16
read-only
CRCCHKS
PDMA_CRCCHKS
CRC Checksum Register
0xE88
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Register
This field indicates the CRC checksum.
0
32
read-only
CRCCSA
PDMA_CRCCSA
CRC DMA Current Source Address Register
0xE14
-1
read-only
n
0x0
0x0
CURSA
CRC DMA Current Source Address Register (Read Only)
This field indicates the source address where the CRC DMA transfer just occurs.
0
32
read-only
CRCCTL
PDMA_CRCCTL
CRC Control Register
0xE00
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum Complement
27
1
read-write
0
No 1's complement for CRC checksum
#0
1
1's complement for CRC checksum
#1
CHKSREV
Checksum Reverse
Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
No bit order reverse for CRC checksum
#0
1
Bit order reverse for CRC checksum
#1
CRCEN
CRC Channel Enable
Setting this bit to 1 enables CRC's operation.
When operation in CRC DMA mode (TRGEN aaa 1), if user clears this bit, the DMA operation will be continuous until all CRC DMA operation is done, and the TRGEN bit will asserted until all CRC DMA operation done. But in this case, the PDMA_CRCINTF [TXOKIF] flag will inactive, user can read CRC result by reading PDMA_CRCCHKS register when TRGEN aaa 0
When operation in CRC DMA mode (TRGEN aaa 1), if user wants to stop the transfer immediately, user can write 1 to CRCRST bit to stop the transmission.
0
1
read-write
CRCMODE
CRC Polynomial Mode
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
CRCRST
CRC Engine Reset
Note: When operated in CPU PIO mode, setting this bit will reload the initial seed value.
1
1
read-write
0
No effect
#0
1
Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles
#1
DATFMT
Write Data Complement
26
1
read-write
0
No 1's complement for CRC write data in
#0
1
1's complement for CRC write data in
#1
DATLEN
CPU Write Data Length
When operation in CPU PIO mode (CRCEN aaa 1, TRGEN aaa 0), this field indicates the write data length.
00 aaa Data length is 8-bit mode
01 aaa Data length is 16-bit mode
1x aaa Data length is 32-bit mode
Note1: This field is used for CPU PIO mode.
Note2: When the data length is 8-bit mode, the valid data is PDMA_CRCDAT [7:0] if the data length is 16-bit mode, the valid data is PDMA_CRCDAT [15:0].
28
2
read-write
DATREV
Write Data Order Reverse
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
24
1
read-write
0
No bit order reversed for CRC write data in
#0
1
Bit order reversed for CRC write data in (per byte)
#1
TRGEN
TRGEN
Note1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in PDMA_CRCDAT register.
Note2: When CRC DMA transfer is completed, this bit will be cleared automatically.
Note3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
CRC DMA data read or write transfer Enabled
#1
CRCDAT
PDMA_CRCDAT
CRC Write Data Register
0xE80
-1
read-write
n
0x0
0x0
DATA
CRC Write Data Register
When operated in CPU PIO (PDMA_CRCCTL.CRCEN aaa 1, PDMA_CRCCTL.TRGEN aaa 0) mode, software can write data to this field to perform CRC operation
When operated in CRC DMA mode (PDMA_CRCCTL.CRCEN aaa 1, PDMA_CRCCTL.TRGEN aaa 0), this field will be used for DMA internal buffer.
Note1: When operated in CRC DMA mode, so don't filled any data in this field.
Note2: The PDMA_CRCCTL.DATFMT and PDMA_CRCCTL.DATREV bit setting will affect this field for example, if DATREV aaa 1, if the write data in PDMA_CRCDAT register is 0xAABBCCDD, the read data from PDMA_CRCDAT register will be 0x55DD33BB.
0
32
read-write
CRCINTEN
PDMA_CRCINTEN
CRC DMA Interrupt Enable Register
0xE20
-1
read-write
n
0x0
0x0
TXABTIEN
CRC DMA Read/Write Target Abort Interrupt Enable
0
1
read-write
0
Target abort interrupt generation Disabled during CRC DMA transfer
#0
1
Target abort interrupt generation Enabled during CRC DMA transfer
#1
TXOKIEN
CRC DMA Transfer Done Interrupt Enable
1
1
read-write
0
Interrupt generator Disabled when CRC DMA transfer is done
#0
1
Interrupt generator Enabled when CRC DMA transfer is done
#1
CRCINTF
PDMA_CRCINTF
CRC DMA Interrupt Status Register
0xE24
-1
read-write
n
0x0
0x0
TXABTIF
CRC DMA Read/Write Target Abort Interrupt Flag
Software can write 1 to clear this bit to zero.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
TXOKIF
Block Transfer Done Interrupt Flag
This bit indicates that CRC DMA has finished all transfer.
Software can write 1 to clear this bit to zero.
1
1
read-write
0
Not finished
#0
1
Done
#1
CRCSA
PDMA_CRCSA
CRC DMA Source Address Register
0xE04
-1
read-write
n
0x0
0x0
SRCADDR
CRC DMA Transfer Source Address Register
This field indicates a 32-bit source address of CRC DMA.
Note: The source address must be word alignment.
0
32
read-write
CRCSEED
PDMA_CRCSEED
CRC Seed Register
0xE84
-1
read-write
n
0x0
0x0
SEED
CRC Seed Register
This field indicates the CRC seed value.
0
32
read-write
CURBCCH0
PDMA_CURBCCH0
PDMA Current Byte Count Register of Channel 0
0x1C
-1
read-only
n
0x0
0x0
CURBC
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs
0
16
read-only
CURBCCH1
0x11C
-1
read-write
n
0x0
0x0
CURBCCH2
0x21C
-1
read-write
n
0x0
0x0
CURBCCH3
0x31C
-1
read-write
n
0x0
0x0
CURDACH0
PDMA_CURDACH0
PDMA Current Destination Address Register of Channel 0
0x18
-1
read-only
n
0x0
0x0
CURDA
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs.
0
32
read-only
CURDACH1
0x118
-1
read-write
n
0x0
0x0
CURDACH2
0x218
-1
read-write
n
0x0
0x0
CURDACH3
0x318
-1
read-write
n
0x0
0x0
CURSACH0
PDMA_CURSACH0
PDMA Current Source Address Register of Channel 0
0x14
-1
read-only
n
0x0
0x0
CURSA
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs.
0
32
read-only
CURSACH1
0x114
-1
read-write
n
0x0
0x0
CURSACH2
0x214
-1
read-write
n
0x0
0x0
CURSACH3
0x314
-1
read-write
n
0x0
0x0
CURSRCH0
PDMA_CURSRCH0
PDMA Current Span Increment Register of Channel 0
0x38
-1
read-write
n
0x0
0x0
CSPANREG
Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode.
0
16
read-write
CURSRCH1
0x138
-1
read-write
n
0x0
0x0
CURSRCH2
0x238
-1
read-write
n
0x0
0x0
CURSRCH3
0x338
-1
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
PDMA Control Register of Channel 0
0x0
-1
read-write
n
0x0
0x0
CHEN
PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
0
1
read-write
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
6
2
read-write
0
Transfer Destination Address is incremented
#00
1
RESERVED
#01
2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#10
3
Transfer Destination Address is wrapped. When PDMA_CURBCCH (Current Byte Count) equals zero, the PDMA_CURDACH (Current Destination Address) and PDMA_CURBCCH registers will be reloaded from the PDMA_DSCTn_ENDDA (Destination Address) and PDMA_TXBCCHn (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
2
2
read-write
0
Memory to Memory mode (SRAM-to-SRAM)
#00
1
IP to Memory mode (APB-to-SRAM)
#01
2
Memory to IP mode (SRAM-to-APB)
#10
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
4
2
read-write
0
Transfer Source address is incremented
#00
1
RESERVED
#01
2
Transfer Source address is fixed
#10
3
Transfer Source address is wrapped. When PDMA_CURBCCH (Current Byte Count) equals zero, the PDMA_CURSACH (Current Source Address) and PDMA_CURBCCH registers will be reloaded from the SAR (Source Address) and PDMA_TXBCCH (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN aaa 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
#11
SWRST
Software Engine Reset
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
#1
TXEN
Trigger Enable - Start A PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
23
1
read-write
0
Write: no effect. Read: Idle/Finished
#0
1
Enable PDMA data read or write transfer
#1
TXWIDTH
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
19
2
read-write
0
One word (32 bits) is transferred for every PDMA operation
#00
1
One byte (8 bits) is transferred for every PDMA operation
#01
2
One half-word (16 bits) is transferred for every PDMA operation
#10
3
RESERVED
#11
WAINTSEL
Wrap Interrupt Select
x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes were sent.
xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BYTECNT aaa 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around.
x1x1: Both half and w interrupts generated.
12
4
read-write
DSCT0_ENDDA
PDMA_DSCT0_ENDDA
PDMA Transfer Destination Address Register of Channel 0
0x8
-1
read-write
n
0x0
0x0
ENDDA
PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
0
32
read-write
DSCT0_ENDSA
PDMA_DSCT0_ENDSA
PDMA Transfer Source Address Register of Channel 0
0x4
-1
read-write
n
0x0
0x0
ENDSA
PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
0
32
read-write
DSCT1_CTL
0x100
-1
read-write
n
0x0
0x0
DSCT1_ENDDA
0x108
-1
read-write
n
0x0
0x0
DSCT1_ENDSA
0x104
-1
read-write
n
0x0
0x0
DSCT2_CTL
0x200
-1
read-write
n
0x0
0x0
DSCT2_ENDDA
0x208
-1
read-write
n
0x0
0x0
DSCT2_ENDSA
0x204
-1
read-write
n
0x0
0x0
DSCT3_CTL
0x300
-1
read-write
n
0x0
0x0
DSCT3_ENDDA
0x308
-1
read-write
n
0x0
0x0
DSCT3_ENDSA
0x304
-1
read-write
n
0x0
0x0
GLOBALIF
PDMA_GLOBALIF
PDMA Global Interrupt Status Register
0xF0C
-1
read-only
n
0x0
0x0
GLOBALIF
Interrupt Pin Status (Read Only)
GLOBALIF[n] is the interrupt status of PDMA channel n.
0
4
read-only
GLOCTL
PDMA_GLOCTL
PDMA Global Control Register
0xF00
-1
read-write
n
0x0
0x0
CHCKEN
PDMA Controller Channel Clock Enable Control
To enable clock for channel n CHCKEN[n] must be set.
CHCKEN[n] aaa 1: Enable Channel n clock
CHCKEN[n] aaa 0: Disable Channel n clock
8
4
read-write
SWRST
PDMA Software Reset
Note: This bit can reset all channels (global reset).
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles
#1
INLBPCH0
PDMA_INLBPCH0
PDMA Internal Buffer Pointer Register of Channel 0
0x10
-1
read-only
n
0x0
0x0
BURPTR
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
0
4
read-only
INLBPCH1
0x110
-1
read-write
n
0x0
0x0
INLBPCH2
0x210
-1
read-write
n
0x0
0x0
INLBPCH3
0x310
-1
read-write
n
0x0
0x0
INTENCH0
PDMA_INTENCH0
PDMA Interrupt Enable Control Register of Channel 0
0x20
-1
read-write
n
0x0
0x0
TXABTIEN
PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
0
1
read-write
0
Disable PDMA transfer target abort interrupt generation
#0
1
Enable PDMA transfer target abort interrupt generation
#1
TXOKIEN
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
1
1
read-write
0
Disable PDMA transfer done interrupt generation
#0
1
Enable PDMA transfer done interrupt generation
#1
WAINTEN
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
2
1
read-write
0
Disable Wraparound PDMA interrupt generation
#0
1
Enable Wraparound interrupt generation
#1
INTENCH1
0x120
-1
read-write
n
0x0
0x0
INTENCH2
0x220
-1
read-write
n
0x0
0x0
INTENCH3
0x320
-1
read-write
n
0x0
0x0
SPANRCH0
PDMA_SPANRCH0
PDMA Span Increment Register of Channel 0
0x34
-1
read-only
n
0x0
0x0
SPANREG
Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPANREG may be a negative number.
0
9
read-only
SPANRCH1
0x134
-1
read-write
n
0x0
0x0
SPANRCH2
0x234
-1
read-write
n
0x0
0x0
SPANRCH3
0x334
-1
read-write
n
0x0
0x0
SVCSEL
PDMA_SVCSEL
PDMA Service Selection Control Register
0xF04
-1
read-write
n
0x0
0x0
ADCRXSEL
PDMA ADC Receive Selection
This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request.
8
4
read-write
DPWMTXSEL
PDMA DPWM Transmit Selection
This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
12
4
read-write
I2SRXSEL
PDMA I2S Receive Selection
This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request.
24
4
read-write
I2STXSEL
PDMA I2S Transmit Selection
This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request.
28
4
read-write
SPIRXSEL
PDMA SPI0 Receive Selection
This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
0
4
read-write
SPITXSEL
PDMA SPI0 Transmit Selection
This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
4
4
read-write
UARTRXSEL
PDMA UART0 Receive Selection
This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request.
16
4
read-write
UARTXSEL
PDMA UART0 Transmit Selection
This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request.
20
4
read-write
TXBCCH0
PDMA_TXBCCH0
PDMA Transfer Byte Count Register of Channel 0
0xC
-1
read-write
n
0x0
0x0
BYTECNT
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes.
0
16
read-write
TXBCCH1
0x10C
-1
read-write
n
0x0
0x0
TXBCCH2
0x20C
-1
read-write
n
0x0
0x0
TXBCCH3
0x30C
-1
read-write
n
0x0
0x0
PWM
PWM0_PWM1 Register Map
PWM0_PWM1
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x54
registers
n
0xC0
0x8
registers
n
0xD0
0x4
registers
n
0xD8
0x10
registers
n
0xF8
0x8
registers
n
PWM0_CAPCTL01
PWM0_CAPCTL01
Capture Control Register For Pair Of PWM0CH0 And PWM0CH1
0x50
-1
read-write
n
0x0
0x0
CAPEN0
Capture Channel 0 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function on channel 0
#0
1
Enable capture function on channel 0
#1
CAPEN1
Capture Channel 1 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
19
1
read-write
0
Disable capture function on channel 1
#0
1
Enable capture function on channel 1
#1
CAPIF0
Capture0 Interrupt Indication Flag
If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1), a rising transition at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFLIEN0 aaa 1). This flag is cleared by software writing a '1' to it.
4
1
read-write
CAPIF1
Capture1 Interrupt Indication Flag
If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1), a rising transition at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN1 aaa 1). This flag is cleared by software writing a '1' to it.
20
1
read-write
CAPINV0
Channel 0 Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CAPINV1
Channel 1 Inverter ON/OFF
16
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CFLIEN0
Channel 0 Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIEN1
Channel 1 Falling Latch Interrupt Enable
When enabled, capture block generates an interrupt on falling edge of input.
18
1
read-write
0
Disable falling edge latch interrupt
#0
1
Enable falling edge latch interrupt
#1
CFLIF0
PWM_FCAPDAT0 Latched Indicator Bit
When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CFLIF1
PWM_FCAPDAT1 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
23
1
read-write
CRLIEN0
Channel 0 Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIEN1
Channel 1 Rising Latch Interrupt Enable
When enabled, capture block generates an interrupt on rising edge of input.
17
1
read-write
0
Disable rising edge latch interrupt
#0
1
Enable rising edge latch interrupt
#1
CRLIF0
PWM_RCAPDAT0 Latched Indicator Bit
When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CRLIF1
PWM_RCAPDAT1 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
22
1
read-write
PWM0_CAPCTL23
PWM0_CAPCTL23
Capture Control Register For Pair Of PWM0CH2 And PWM0CH3
0x54
-1
read-write
n
0x0
0x0
CAPEN2
Capture Channel 2 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function on channel 0
#0
1
Enable capture function on channel 0
#1
CAPEN3
Capture Channel 3 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
19
1
read-write
0
Disable capture function on channel 1
#0
1
Enable capture function on channel 1
#1
CAPIF2
Capture2 Interrupt Indication Flag
If channel 0 rising latch interrupt is enabled (CRLIEN2 aaa 1), a rising transition at input channel 0 will result in CAPIF2 to high Similarly, a falling transition will cause CAPIF2 to be set high if channel 0 falling latch interrupt is enabled (CFLIEN2 aaa 1). This flag is cleared by software writing a '1' to it.
4
1
read-write
CAPIF3
Capture3 Interrupt Indication Flag
If channel 1 rising latch interrupt is enabled (CRLIEN3 aaa 1), a rising transition at input channel 1 will result in CAPIF3 to high Similarly, a falling transition will cause CAPIF3 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN3 aaa 1). This flag is cleared by software writing a '1' to it.
20
1
read-write
CAPINV2
Channel 2 Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CAPINV3
Channel 3 Inverter ON/OFF
16
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CFLIEN2
Channel 2 Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIEN3
Channel 3 Falling Latch Interrupt Enable
When enabled, capture block generates an interrupt on falling edge of input.
18
1
read-write
0
Disable falling edge latch interrupt
#0
1
Enable falling edge latch interrupt
#1
CFLIF2
PWM_FCAPDAT2 Latched Indicator Bit
When input channel 0 has a falling transition, PWM_FCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CFLIF3
PWM_FCAPDAT3 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_FCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
23
1
read-write
CRLIEN2
Channel 2 Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIEN3
Channel 3 Rising Latch Interrupt Enable
When enabled, capture block generates an interrupt on rising edge of input.
17
1
read-write
0
Disable rising edge latch interrupt
#0
1
Enable rising edge latch interrupt
#1
CRLIF2
PWM_RCAPDAT2 Latched Indicator Bit
When input channel 0 has a rising transition, PWM_RCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CRLIF3
PWM_RCAPDAT3 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_RCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
22
1
read-write
PWM0_CAPINEN
PWM0_CAPINEN
Capture Input Enable Register
0x78
-1
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Register
0 : OFF (GPA[13:12], GPB[15:14] pin input disconnected from Capture block)
1 : ON (GPA[13:12] , GPB[15:14] pin, if in PWM alternative function, will be configured as an input and fed to capture function)
CAPINEN[3:0]
Bit [3][2][1][0]
Bit xxx1 : Capture channel 0 is from GPA [12]
Bit xx1x : Capture channel 1 is from GPA [13]
Bit x1xx : Capture channel 2 is from GPB [14]
Bit 1xxx : Capture channel 3 is from GPB [15]
0
4
read-write
PWM0_CLKDIV
PWM0_CLKDIV
PWM Clock Select Register
0x4
-1
read-write
n
0x0
0x0
CLKDIV0
Timer 0 Clock Source Selection
Value : Input clock divided by
0 : 2
1 : 4
2 : 8
3 : 16
4 : 1
0
3
read-write
CLKDIV1
Timer 1 Clock Source Selection
(Table is as CLKDIV0)
4
3
read-write
CLKDIV2
Timer 2 Clock Source Selection
(Table is as CLKDIV0)
8
3
read-write
CLKDIV3
Timer 3 Clock Source Selection
(Table is as CLKDIV0)
12
3
read-write
PWM0_CLKPSC
PWM0_CLKPSC
PWM Prescaler Register
0x0
-1
read-write
n
0x0
0x0
CLKPSC01
Clock Pre-Scaler Pair Of PWM0CH0 And PWM0CH1
Clock input is divided by (CLKPSC01 + 1)
If CLKPSC01 aaa 0, then the pre-scaler output clock will be stopped.
This implies PWM counter 0 and 1 will also be stopped.
0
8
read-write
CLKPSC23
Clock Pre-Scaler For Pair Of PWM0CH2 And PWM0CH3
Clock input is divided by (CLKPSC23 + 1)
If CLKPSC23 aaa 0, then the pre-scaler output clock will be stopped.
This implies PWM counter 2 and 3 will also be stopped.
8
8
read-write
DTCNT01
Dead Zone Interval Register For Pair Of PWM0CH0 And PWM0CH1
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector 0.
16
8
read-write
DTCNT23
Dead Zone Interval Register For Pair Of PWM0CH2 And PWM0CH3
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector 0.
24
8
read-write
PWM0_CMPDAT0
PWM0_CMPDAT0
PWM Comparator Register 0
0x10
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP determines the PWM duty cycle.
PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1)
Duty Cycle aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
PWM0_CMPDAT1
0x1C
-1
read-write
n
0x0
0x0
PWM0_CMPDAT2
0x28
-1
read-write
n
0x0
0x0
PWM0_CMPDAT3
0x34
-1
read-write
n
0x0
0x0
PWM0_CNT0
PWM0_CNT0
PWM Data Register 0
0x14
-1
read-only
n
0x0
0x0
CNT
PWM Data Register
Reports the current value of the 16-bit down counter.
0
16
read-only
PWM0_CNT1
0x20
-1
read-write
n
0x0
0x0
PWM0_CNT2
0x2C
-1
read-write
n
0x0
0x0
PWM0_CNT3
0x38
-1
read-write
n
0x0
0x0
PWM0_CTL
PWM0_CTL
PWM Control Register
0x8
-1
read-write
n
0x0
0x0
CNTEN0
PWM-Timer 0 Enable/Disable Start Run
0
1
read-write
0
Stop PWM-Timer 0 Running
#0
1
Enable PWM-Timer 0 Start/Run
#1
CNTEN1
PWM-Timer 1 Enable/Disable Start Run
8
1
read-write
0
Stop PWM-Timer 1
#0
1
Enable PWM-Timer 1 Start/Run
#1
CNTEN2
PWM-Timer 2 Enable/Disable Start Run
16
1
read-write
0
Stop PWM-Timer 2
#0
1
Enable PWM-Timer 2 Start/Run
#1
CNTEN3
PWM-Timer 3 Enable/Disable Start Run
24
1
read-write
0
Stop PWM-Timer 3
#0
1
Enable PWM-Timer 3 Start/Run
#1
CNTMODE0
PWM-Timer 0 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared.
3
1
read-write
0
One-Shot Mode
#0
1
Auto-reload Mode
#1
CNTMODE1
PWM-Timer 1 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared.
11
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
CNTMODE2
PWM-Timer 2 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD2 and PWM_CMPDAT2 to be cleared.
19
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
CNTMODE3
PWM-Timer 3 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared.
27
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
DTEN01
Dead-Zone 01 Generator Enable/Disable Pair Of PWM0CH0 And PWM0CH1
Note: When Dead-Zone Generator is enabled, the pair of PWM0CH0 and PWM0CH1 become a complementary pair.
4
1
read-write
0
Disable
#0
1
Enable
#1
DTEN23
Dead-Zone 23 Generator Enable/Disable Pair Of PWM0CH2 And PWM0CH3
Note: When Dead-Zone Generator is enabled, the pair of PWM0CH2 and PWM0CH3 become a complementary pair.
5
1
read-write
0
Disable
#0
1
Enable
#1
PINV0
PWM-Timer 0 Output Inverter ON/OFF
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV1
PWM-Timer 1 Output Inverter ON/OFF
10
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV2
PWM-Timer 2 Output Inverter ON/OFF
18
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV3
PWM-Timer 3 Output Inverter ON/OFF
26
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PWM0_FCAPDAT0
PWM0_FCAPDAT0
Capture Falling Latch Register (Channel 0)
0x5C
-1
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
0
16
read-only
PWM0_FCAPDAT1
0x64
-1
read-write
n
0x0
0x0
PWM0_FCAPDAT2
0x6C
-1
read-write
n
0x0
0x0
PWM0_FCAPDAT3
0x74
-1
read-write
n
0x0
0x0
PWM0_INTEN
PWM0_INTEN
PWM Interrupt Enable Register
0x40
-1
read-write
n
0x0
0x0
PIEN0
PWM Timer 0 Interrupt Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
PIEN1
PWM Timer 1 Interrupt Enable
1
1
read-write
0
Disable
#0
1
Enable
#1
PIEN2
PWM Timer 2 Interrupt Enable
2
1
read-write
0
Disable
#0
1
Enable
#1
PIEN3
PWM Timer 3 Interrupt Enable
3
1
read-write
0
Disable
#0
1
Enable
#1
PWM0_INTSTS
PWM0_INTSTS
PWM Interrupt Flag Register
0x44
-1
read-write
n
0x0
0x0
PIF0
PWM Timer 0 Interrupt Flag
Flag is set by hardware when PWM0CH0 down counter reaches zero, software can clear this bit by writing '1' to it.
0
1
read-write
PIF1
PWM Timer 1 Interrupt Flag
Flag is set by hardware when PWM0CH1 down counter reaches zero, software can clear this bit by writing '1' to it.
1
1
read-write
PIF2
PWM Timer 2 Interrupt Flag
Flag is set by hardware when PWM0CH2 down counter reaches zero, software can clear this bit by writing '1' to it.
2
1
read-write
PIF3
PWM Timer 3 Interrupt Flag
Flag is set by hardware when PWM0CH3 down counter reaches zero, software can clear this bit by writing '1' to it.
3
1
read-write
PWM0_PERIOD0
PWM0_PERIOD0
PWM Counter Register 0
0xC
-1
read-write
n
0x0
0x0
PERIOD
PWM Counter/Timer Reload Value
PERIOD determines the PWM period.
PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1)
Duty ratio aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note:
Any write to PERIOD will take effect in next PWM cycle.
0
16
read-write
PWM0_PERIOD1
0x18
-1
read-write
n
0x0
0x0
PWM0_PERIOD2
0x24
-1
read-write
n
0x0
0x0
PWM0_PERIOD3
0x30
-1
read-write
n
0x0
0x0
PWM0_POEN
PWM0_POEN
PWM0 Output Enable Register for CH0~CH3
0x7C
-1
read-write
n
0x0
0x0
POEN0
PWM0CH0 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
0
1
read-write
0
Disable PWM0CH0 output to pin
#0
1
Enable PWM0CH 0 output to pin
#1
POEN1
PWM0CH1 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
1
1
read-write
0
Disable PWM0CH1 output to pin
#0
1
Enable PWM0CH1 output to pin
#1
POEN2
PWM0CH2 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
2
1
read-write
0
Disable PWM0CH2 output to pin
#0
1
Enable PWM0CH2 output to pin
#1
POEN3
PWM0CH3 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
3
1
read-write
0
Disable PWM0CH3 output to pin
#0
1
Enable PWM0CH3 output to pin
#1
PWM0_RCAPDAT0
PWM0_RCAPDAT0
Capture Rising Latch Register (Channel 0)
0x58
-1
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
0
16
read-only
PWM0_RCAPDAT1
0x60
-1
read-write
n
0x0
0x0
PWM0_RCAPDAT2
0x68
-1
read-write
n
0x0
0x0
PWM0_RCAPDAT3
0x70
-1
read-write
n
0x0
0x0
PWM1_CAPCTL01
PWM1_CAPCTL01
Capture Control Register For Pair Of PWM1CH0 And PWM1CH1
0xD0
-1
read-write
n
0x0
0x0
CAPEN0
Capture Channel 0 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
3
1
read-write
0
Disable capture function on channel 0
#0
1
Enable capture function on channel 0
#1
CAPEN1
Capture Channel 1 Transition Enable/Disable
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
19
1
read-write
0
Disable capture function on channel 1
#0
1
Enable capture function on channel 1
#1
CAPIF0
Capture0 Interrupt Indication Flag
If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1), a rising transition at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFLIEN0 aaa 1). This flag is cleared by software writing a '1' to it.
4
1
read-write
CAPIF1
Capture1 Interrupt Indication Flag
If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1), a rising transition at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN1 aaa 1). This flag is cleared by software writing a '1' to it.
20
1
read-write
CAPINV0
Channel 0 Inverter ON/OFF
0
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CAPINV1
Channel 1 Inverter ON/OFF
16
1
read-write
0
Inverter OFF
#0
1
Inverter ON. Reverse the input signal from GPIO before Capture timer
#1
CFLIEN0
Channel 0 Falling Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on falling edge of input.
2
1
read-write
0
Disable falling latch interrupt
#0
1
Enable falling latch interrupt
#1
CFLIEN1
Channel 1 Falling Latch Interrupt Enable
When enabled, capture block generates an interrupt on falling edge of input.
18
1
read-write
0
Disable falling edge latch interrupt
#0
1
Enable falling edge latch interrupt
#1
CFLIF0
PWM_FCAPDAT0 Latched Indicator Bit
When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
7
1
read-write
CFLIF1
PWM_FCAPDAT1 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
23
1
read-write
CRLIEN0
Channel 0 Rising Latch Interrupt Enable ON/OFF
When enabled, capture block generates an interrupt on rising edge of input.
1
1
read-write
0
Disable rising latch interrupt
#0
1
Enable rising latch interrupt
#1
CRLIEN1
Channel 1 Rising Latch Interrupt Enable
When enabled, capture block generates an interrupt on rising edge of input.
17
1
read-write
0
Disable rising edge latch interrupt
#0
1
Enable rising edge latch interrupt
#1
CRLIF0
PWM_RCAPDAT0 Latched Indicator Bit
When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
6
1
read-write
CRLIF1
PWM_RCAPDAT1 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
22
1
read-write
PWM1_CAPINEN
PWM1_CAPINEN
Capture Input Enable Register
0xF8
-1
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Register
0 : OFF (GPA[15:14] pin input disconnected from Capture block)
1 : ON (GPA[15:14] pin, if in PWM alternative function, will be configured as an input and fed to capture function)
CAPINEN[1:0]
Bit [1][0]
Bit x1 : Capture channel 0 is from GPA [14]
Bit 1x : Capture channel 1 is from GPA [15]
0
2
read-write
PWM1_CLKDIV
PWM1_CLKDIV
PWM Clock Select Register
0x84
-1
read-write
n
0x0
0x0
CLKDIV0
Timer 0 Clock Source Selection
Value : Input clock divided by
0 : 2
1 : 4
2 : 8
3 : 16
4 : 1
0
3
read-write
CLKDIV1
Timer 1 Clock Source Selection
(Table is as CLKDIV0)
4
3
read-write
PWM1_CLKPSC
PWM1_CLKPSC
PWM Prescaler Register
0x80
-1
read-write
n
0x0
0x0
CLKPSC01
Clock Pre-Scaler For Pair Of PWM1CH0 And PWM1CH1
Clock input is divided by (CLKPSC01 + 1)
If CLKPSC01 aaa 0, then the pre-scaler output clock will be stopped.
This implies PWM counter 4 and 5 will also be stopped.
0
8
read-write
DTCNT01
Dead Zone Interval Register For Pair Of PWM1CH0 And PWM1CH1
These 8 bits determine dead zone length.
The unit time of dead zone length is that from clock selector 0.
16
8
read-write
PWM1_CMPDAT0
PWM1_CMPDAT0
PWM Comparator Register 0
0x90
-1
read-write
n
0x0
0x0
CMP
PWM Comparator Register
CMP determines the PWM duty cycle.
PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1)
Duty Cycle aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note: Any write to CMP will take effect in next PWM cycle.
0
16
read-write
PWM1_CMPDAT1
0x9C
-1
read-write
n
0x0
0x0
PWM1_CNT0
PWM1_CNT0
PWM Data Register 0
0x94
-1
read-only
n
0x0
0x0
CNT
PWM Data Register
Reports the current value of the 16-bit down counter.
0
16
read-only
PWM1_CNT1
0xA0
-1
read-write
n
0x0
0x0
PWM1_CTL
PWM1_CTL
PWM Control Register
0x88
-1
read-write
n
0x0
0x0
CNTEN0
PWM-Timer 0 Enable/Disable Start Run
0
1
read-write
0
Stop PWM-Timer 0 Running
#0
1
Enable PWM-Timer 0 Start/Run
#1
CNTEN1
PWM-Timer 1 Enable/Disable Start Run
8
1
read-write
0
Stop PWM-Timer 1
#0
1
Enable PWM-Timer 1 Start/Run
#1
CNTMODE0
PWM-Timer 0 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared.
3
1
read-write
0
One-Shot Mode
#0
1
Auto-reload Mode
#1
CNTMODE1
PWM-Timer 1 Auto-Reload/One-Shot Mode
Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared.
11
1
read-write
0
One-Shot Mode
#0
1
Auto-load Mode
#1
DTEN01
Dead-Zone 01 Generator Enable/Disable For Pair Of PWM1CH0 And PWM1CH1
Note: When Dead-Zone Generator is enabled, the pair of PWM1CH0 and PWM1CH1 become a complementary pair.
4
1
read-write
0
Disable
#0
1
Enable
#1
PINV0
PWM-Timer 0 Output Inverter ON/OFF
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV1
PWM-Timer 1 Output Inverter ON/OFF
10
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PWM1_FCAPDAT0
PWM1_FCAPDAT0
Capture Falling Latch Register (Channel 0)
0xDC
-1
read-only
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
0
16
read-only
PWM1_FCAPDAT1
0xE4
-1
read-write
n
0x0
0x0
PWM1_INTEN
PWM1_INTEN
PWM Interrupt Enable Register
0xC0
-1
read-write
n
0x0
0x0
PIEN0
PWM Timer 0 Interrupt Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
PIEN1
PWM Timer 1 Interrupt Enable
1
1
read-write
0
Disable
#0
1
Enable
#1
PWM1_INTSTS
PWM1_INTSTS
PWM Interrupt Flag Register
0xC4
-1
read-write
n
0x0
0x0
PIF0
PWM Timer 0 Interrupt Flag
Flag is set by hardware when PWM1CH0 down counter reaches zero, software can clear this bit by writing '1' to it.
0
1
read-write
PIF1
PWM Timer 1 Interrupt Flag
Flag is set by hardware when PWM1CH1 down counter reaches zero, software can clear this bit by writing '1' to it.
1
1
read-write
PWM1_PERIOD0
PWM1_PERIOD0
PWM Counter Register 0
0x8C
-1
read-write
n
0x0
0x0
PERIOD
PWM Counter/Timer Reload Value
PERIOD determines the PWM period.
PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1)
Duty ratio aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note:
Any write to PERIOD will take effect in next PWM cycle.
0
16
read-write
PWM1_PERIOD1
0x98
-1
read-write
n
0x0
0x0
PWM1_POEN
PWM1_POEN
PWM1 Output Enable Register for CH0~CH1
0xFC
-1
read-write
n
0x0
0x0
POEN0
PWM1CH0 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
0
1
read-write
0
Disable PWM1CH0 output to pin
#0
1
Enable PWM1CH0 output to pin
#1
POEN1
PWM1CH1 Output Enable Register
Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
1
1
read-write
0
Disable PWM1CH1 output to pin
#0
1
Enable PWM1CH1 output to pin
#1
PWM1_RCAPDAT0
PWM1_RCAPDAT0
Capture Rising Latch Register (Channel 0)
0xD8
-1
read-only
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register
In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
0
16
read-only
PWM1_RCAPDAT1
0xE0
-1
read-write
n
0x0
0x0
RTC
RTC Register Map
RTC
0x0
0x0
0x34
registers
n
CAL
RTC_CAL
Calendar Load Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
Calendar Alarm Register
0x20
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CLKFMT
RTC_CLKFMT
Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-Hour / 12-Hour Mode Selection
Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode
The range of 24-hour time scale is between 0 and 23.
12-hour time scale:
01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06)
07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12)
21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06)
27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12)
0
1
read-write
0
select 12-hour time scale with AM and PM indication
#0
1
select 24-hour time scale
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fractional Part
Formula aaa (fraction part of detected value) x 60
Refer to 5.8.4.4 for the examples.
0
6
read-write
INTEGER
Integer Part
Register should contain the value (INT(Factual) - 32761)
Ex: Integer part of detected value aaa 32772,
RTC_FREQADJ.INTEGER aaa 32772-32761 aaa 11 (1011b)
The range between 32761 and 32776
8
4
read-write
INIT
RTC_INIT
RTC Initialization Register
0x0
-1
read-write
n
0x0
0x0
ATVSTS
RTC Active Status (Read Only)
0: RTC is in reset state
1: RTC is in normal active state.
0
1
read-only
INIT
RTC Initialization
After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIT. This will force a hardware reset then release all logic and counters.
1
31
read-write
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
-1
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable
0
1
read-write
0
RTC Alarm Interrupt is disabled
#0
1
RTC Alarm Interrupt is enabled
#1
TICKIEN
Time-Tick Interrupt And Wakeup-By-Tick Enable
1
1
read-write
0
RTC Time-Tick Interrupt is disabled
#0
1
RTC Time-Tick Interrupt is enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Indicator Register
0x2C
-1
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag
0
1
read-write
0
Indicates no Alarm Interrupt condition
#0
1
Indicates RTC Alarm Interrupt generated
#1
TICKIF
RTC Time-Tick Interrupt Flag
1
1
read-write
0
Indicates no Time-Tick Interrupt condition
#0
1
Indicates RTC Time-Tick Interrupt generated
#1
LEAPYEAR
RTC_LEAPYEAR
Leap year Indicator Register
0x24
-1
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication Register (Read Only)
0
1
read-only
0
Current year is not a leap year
#0
1
Current year is leap year
#1
RWEN
RTC_RWEN
RTC Access Enable Register
0x4
-1
read-write
n
0x0
0x0
RWEN
RTC Register Access Enable Password (Write Only)
0xA965 aaa Enable RTC access
Others aaa Disable RTC access
0
16
write-only
RWENF
RTC Register Access Enable Flag (Read Only)
This bit will be set after RWEN[15:0] register is set to 0xA965, it will clear automatically in 512 RTC clock cycles or RWEN[15:0] ! aaa 0xA965. The effect of RTC_RWEN.RWENF on access to each register is given Table 572.
Table 572 RTC_RWEN.RWENF Register Access Effect.
Register : RWENF aaa 1 : RWENF aaa 0
RTC_INIT : R/W : R/W
RTC_FREQADJ : R/W : -
RTC_TIME : R/W : R
RTC_CAL : R/W : R
RTC_CLKFMT : R/W : R/W
RTC_WEEKDAY : R/W : R
RTC_TALM : R/W : -
RTC_CALM : R/W : -
RTC_LEAPYEAR : R : R
RTC_INTEN : R/W : R/W
RTC_INTSTS : R/W : R/W
RTC_TICK : R/W : -
16
1
read-only
0
RTC register read/write disable
#0
1
RTC register read/write enable
#1
TALM
RTC_TALM
Time Alarm Register
0x1C
-1
read-write
n
0x0
0x0
HR
1 Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1 Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1 Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10 Hour Time Digit of Alarm Setting (0~3)2
20
2
read-write
TENMIN
10 Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10 Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
-1
read-write
n
0x0
0x0
TICKSEL
Time Tick Period Select
The RTC time tick period for Periodic Time-Tick Interrupt request.
Time Tick (second) : 1 / (2^TTR)
Note: This register can be read back after the RTC is active.
0
3
read-write
TWKEN
RTC Timer Wakeup CPU Function Enable Bit
If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm Match occurs, CPU will wake up.
3
1
read-write
0
Disable Wakeup CPU function
#0
1
Enable the Wakeup function
#1
TIME
RTC_TIME
Time Load Register
0xC
-1
read-write
n
0x0
0x0
HR
1 Hour Time Digit (0~9)
16
4
read-write
MIN
1 Min Time Digit (0~9)
8
4
read-write
SEC
1 Sec Time Digit (0~9)
0
4
read-write
TENHR
10 Hour Time Digit (0~3)
20
2
read-write
TENMIN
10 Min Time Digit (0~5)
12
3
read-write
TENSEC
10 Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day Of The Week Register
0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday)
4 (Thursday), 5 (Friday), 6 (Saturday)
0
3
read-write
SCS
SCS Register Map
SCS
0x0
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x180
-1
read-write
n
0x0
0x0
CLRENA
Clear-Enable Control
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will disable the associated interrupt.
Writing 0 has no effect.
The register reads back with the current enable state.
0
32
read-write
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x280
-1
read-write
n
0x0
0x0
CLRPEND
Clear-Pending Control
Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 0 has no effect.
The register reads back with the current pending state.
0
32
read-write
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
-1
read-write
n
0x0
0x0
PRI_0
Priority Of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_1
Priority Of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_2
Priority Of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_3
Priority Of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
-1
read-write
n
0x0
0x0
PRI_4
Priority Of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_5
Priority Of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_6
Priority Of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_7
Priority Of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
-1
read-write
n
0x0
0x0
PRI_10
Priority Of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_11
Priority Of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
PRI_8
Priority Of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_9
Priority Of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
-1
read-write
n
0x0
0x0
PRI_12
Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_13
Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_14
Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_15
Priority Of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x410
-1
read-write
n
0x0
0x0
PRI_16
Priority Of IRQ16
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_17
Priority Of IRQ17
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_18
Priority Of IRQ18
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_19
Priority Of IRQ19
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x414
-1
read-write
n
0x0
0x0
PRI_20
Priority Of IRQ20
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_21
Priority Of IRQ21
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_22
Priority Of IRQ22
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_23
Priority Of IRQ23
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x418
-1
read-write
n
0x0
0x0
PRI_24
Priority Of IRQ24
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_25
Priority Of IRQ25
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_26
Priority Of IRQ26
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_27
Priority Of IRQ27
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x41C
-1
read-write
n
0x0
0x0
PRI_28
Priority Of IRQ28
0 denotes the highest priority and 3 denotes lowest priority
6
2
read-write
PRI_29
Priority Of IRQ29
0 denotes the highest priority and 3 denotes lowest priority
14
2
read-write
PRI_30
Priority Of IRQ30
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI_31
Priority Of IRQ31
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-Enable Control Register
0x100
-1
read-write
n
0x0
0x0
SETENA
Set-Enable Control
Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will enable the associated interrupt.
Writing 0 has no effect.
The register reads back the current enable state.
0
32
read-write
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-Pending Control Register
0x200
-1
read-write
n
0x0
0x0
SETPEND
Set-Pending Control
Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 0 has no effect.
The register reads back with the current pending state.
0
32
read-write
SPI0
SPI0 Register Map
SPI0
0x0
0x0
0x1C
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
Clock Divider Register (Master Only)
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register
The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation.
Fspi_sclk aaa Fspi_clock_src / (DIVIDER+1)
where
Fspi_clock_src is the SPI engine clock source, which is defined in the clock control, CLK_SEL1 register.
0
8
read-write
SPI_CTL
SPI_CTL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SCLK idle low
#0
1
SCLK idle high
#1
DUALIOEN
Dual I/O Mode Enable
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
DWIDTH - Data Word Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
DWIDTH aaa 0x01 ... 1 bit
DWIDTH aaa 0x02 ... 2 bits
......
DWIDTH aaa 0x1f ... 31 bits
DWIDTH aaa 0x00 ... 32 bits
8
5
read-write
LSB
LSB First
Note:
For DUAL and QUAD transactions with LSB must be set to 0.
13
1
read-write
0
The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field)
#0
1
The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX)
#1
QDIODIR
Quad Or Dual I/O Mode Direction Control
20
1
read-write
0
Quad or Dual Input mode
#0
1
Quad or Dual Output mode
#1
QUADIOEN
Quad I/O Mode Enable
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable
Note:
Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
REORDER is only available for Receive mode in DUAL and QUAD transactions.
For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXMODEEN
FIFO Receive Mode Enable
24
1
read-write
0
Disable function
#0
1
Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0
#1
RXNEG
Receive At Negative Edge
1
1
read-write
0
The received data input signal is latched at the rising edge of SCLK
#0
1
The received data input signal is latched at the falling edge of SCLK
#1
RXTCNTEN
DMA Receive Transaction Count Enable
23
1
read-write
0
Disable function
#0
1
Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller
#1
SLAVE
Master Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Enable
In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to 1.
Note:
All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG, RXNEG, DWIDTH, LSB, CLKP, and so on).
0
1
read-write
0
Disable SPI Transfer
#0
1
Enable SPI Transfer
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation. SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and QUAD mode transactions.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
SUSPITV aaa 0x0 ... 0.5 SPICLK clock cycle
SUSPITV aaa 0x1 ... 1.5 SPICLK clock cycle
......
SUSPITV aaa 0xE ... 14.5 SPICLK clock cycle
SUSPITV aaa 0xF ... 15.5 SPICLK clock cycle
Note:
For DUAL and QUAD transactions with SUSPITV must be set to 0.
4
4
read-write
TWOBIT
Two Bits Transfer Mode
When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
Disable two-bit transfer mode
#0
1
Enable two-bit transfer mode
#1
TXNEG
Transmit At Negative Edge
2
1
read-write
0
The transmitted data output signal is changed at the rising edge of SCLK
#0
1
The transmitted data output signal is changed at the falling edge of SCLK
#1
UNITIEN
Unit Transfer Interrupt Enable
17
1
read-write
0
Disable SPI Unit Transfer Interrupt
#0
1
Enable SPI Unit Transfer Interrupt to CPU
#1
SPI_FIFOCTL
SPI_FIFOCTL
FIFO Control/Status Register
0x10
-1
read-write
n
0x0
0x0
RXOVIEN
Receive FIFO Overrun Interrupt Enable
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Clear Receive FIFO Buffer
Note: If there is slave receive time out event, the RXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-Out Interrupt Enable
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXRST
Clear Transmit FIFO Buffer
Note: If there is slave receive time out event, the TXRST will be set 1 when the SPI_SSCTL.SLVTORST, is enabled.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUDFIEN
Slave Transmit Under Run Interrupt Enable
7
1
read-write
0
Slave Transmit FIFO under-run interrupt Disabled
#0
1
Slave Transmit FIFO under-run interrupt Enabled
#1
TXUDFPOL
Transmit Under-Run Data Out
Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.
Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time to report the transmit under-run data out.
6
1
read-write
0
The SPI data out is 0 if there is transmit under-run event in Slave mode
#0
1
The SPI data out is 1 if there is transmit under-run event in Slave mode
#1
SPI_PDMACTL
SPI_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RXPDMAEN
Receive PDMA Enable
Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
1
1
read-write
TXPDMAEN
Transmit DMA Enable
Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.
0
1
read-write
SPI_RX
SPI_RX
FIFO Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register
A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register.
0
32
read-only
SPI_RXTSNCNT
SPI_RXTSNCNT
Receive Transaction Count Register
0x18
-1
read-write
n
0x0
0x0
RXTSNCNT
DMA Receive Transaction Count
When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate.
0
17
read-write
SPI_SSCTL
SPI_SSCTL
Slave Select Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI_SSCTL[1:0]
#0
1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
SLV3WIRE
Slave 3-Wire Mode Enable
This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK, SPI_MISO, and SPI_MOSI.
4
1
read-write
0
4-wire bi-directional interface
#0
1
3-wire bi-directional interface
#1
SLVBCEIEN
Slave Mode Error 0 Interrupt Enable
8
1
read-write
0
Slave mode error 0 interrupt Disable
#0
1
Slave mode error 0 interrupt Enable
#1
SLVTOCNT
Slave Mode Time-Out Period
In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-Out Interrupt Enable
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-Out FIFO Clear
6
1
read-write
0
Function disabled
#0
1
Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event
#1
SLVUDRIEN
Slave Mode Error 1 Interrupt Enable
9
1
read-write
0
Slave mode error 1 interrupt Disable
#0
1
Slave mode error 1 interrupt Enable
#1
SS
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SSACTPOL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SSACTIEN
Slave Select Active Interrupt Enable
12
1
read-write
0
Slave select active interrupt Disable
#0
1
Slave select active interrupt Enable
#1
SSACTPOL
Slave Select Active Level
This bit defines the active status of slave select signal (SPI_SS0/1).
2
1
read-write
0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
#1
SSINAIEN
Slave Select Inactive Interrupt Enable
13
1
read-write
0
Slave select inactive interrupt Disable
#0
1
Slave select inactive interrupt Enable
#1
SPI_STATUS
SPI_STATUS
Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
SPI Unit Bus Status (Read Only)
The following listing are the bus busy conditions:
SPIEN aaa 1 and the TXEMPTY aaa 0.
For SPI Master, the TXEMPTY aaa 1 but the current transaction is not finished yet.
For SPI Slave receive mode, the SPIEN aaa 1 and there is serial clock input into the SPI core logic when slave select is active.
For SPI Slave transmit mode, the SPIEN aaa 1 and the transmit buffer is not empty in SPI core logic event if the slave select is inactive.
0
1
read-only
0
No transaction in the SPI bus
#0
1
SPI controller unit is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Status
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to itself.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)
Note: If RXTHIEN aaa 1 and RXTHIF aaa 1, the SPI controller will generate a SPI interrupt request.
10
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-Out Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Error 0 Interrupt Status (Read Only)
In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.
6
1
read-only
0
No Slave mode error 0 event
#0
1
Slave mode error 0 occurs
#1
SLVTOIF
Slave Time-Out Interrupt Status (Read Only)
When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active.
Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period.
5
1
read-only
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode Error 1 Interrupt Status (Read Only)
In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
7
1
read-only
0
No Slave mode error 1 event
#0
1
Slave mode error 1 occurs
#1
SPIENSTS
SPI Enable Bit Status (Read Only)
Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
15
1
read-only
0
Indicate the transmit control bit is disabled
#0
1
Indicate the transfer control bit is active
#1
SSACTIF
Slave Select Active Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
Slave select active interrupt is clear or not occur
#0
1
Slave select active interrupt event has occur
#1
SSINAIF
Slave Select Inactive Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
3
1
read-write
0
Slave select inactive interrupt is clear or not occur
#0
1
Slave select inactive interrupt event has occur
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: If SPI_SSCTL.SSACTPOL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
Indicates the slave select line bus status is 0
#0
1
Indicates the slave select line bus status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
FIFO CLR Status (Read Only)
Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done.
23
1
read-only
0
Done the FIFO buffer clear function of TXRST and RXRST
#0
1
Doing the FIFO buffer clear function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Status (Read Only)
Note: If TXTHIEN aaa 1 and TXTHIF aaa 1, the SPI controller will generate a SPI interrupt request.
18
1
read-only
0
The valid data count of the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Slave Transmit FIFO Under-Run Interrupt Status (Read Only)
When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set.
Note: This bit will be cleared by writing 1 to itself.
19
1
read-only
UNITIF
Unit Transfer Interrupt Status
Note: This bit will be cleared by writing 1 to itself.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
FIFO Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x110
0x4
registers
n
0x30
0x10
registers
n
0x54
0x4
registers
n
GPA_MFP
SYS_GPA_MFP
GPIOA multiple alternate functions control register
0x38
-1
read-write
n
0x0
0x0
PA0MFP
Alternate Function Setting For PA0MFP
0
2
read-write
0
GPIO
#00
1
SPI_MOSI0
#01
2
MCLK
#10
PA10MFP
Alternate Function Setting For PA10MFP
20
2
read-write
0
GPIO
#00
1
I2C_SDA
#01
2
CMP14
#10
3
UART_RTSn
#11
PA11MFP
Alternate Function Setting For PA11MFP
22
2
read-write
0
GPIO
#00
1
I2C_SCL
#01
2
CMP15
#10
3
UART_CTSn
#11
PA12MFP
Alternate Function Setting For PA12MFP
24
2
read-write
0
GPIO
#00
1
PWM0CH0
#01
2
SPKP
#10
3
I2S_FS
#11
PA13MFP
Alternate Function Setting For PA13MFP
26
2
read-write
0
GPIO
#00
1
PWM0CH1
#01
2
SPKM
#10
3
I2S_BCLK
#11
PA14MFP
Alternate Function Setting For PA14MFP
28
2
read-write
0
GPIO
#00
1
TM0
#01
2
SDCLK
#10
3
PWM1CH0
#11
PA15MFP
Alternate Function Setting For PA15MFP
30
2
read-write
0
GPIO
#00
1
TM1
#01
2
SDIN
#10
3
PWM1CH1
#11
PA1MFP
Alternate Function Setting For PA1MFP
2
2
read-write
0
GPIO
#00
1
SPI_SCLK
#01
2
I2C_SCL
#10
PA2MFP
Alternate Function Setting For PA2MFP
4
2
read-write
0
GPIO
#00
1
SPI_SSB0
#01
PA3MFP
Alternate Function Setting For PA3MFP
6
2
read-write
0
GPIO
#00
1
SPI_MISO0
#01
2
I2C_SDA
#10
PA4MFP
Alternate Function Setting For PA4MFP
8
2
read-write
0
GPIO
#00
1
I2S_FS
#01
PA5MFP
Alternate Function Setting For PA5MFP
10
2
read-write
0
GPIO
#00
1
I2S_BCLK
#01
3
SPI_SSB1
#11
PA6MFP
Alternate Function Setting For PA6MFP
12
2
read-write
0
GPIO
#00
1
I2S_SDI
#01
2
UART_TX
#10
PA7MFP
Alternate Function Setting For PA7MFP
14
2
read-write
0
GPIO
#00
1
I2S_SDO
#01
PA8MFP
Alternate Function Setting For PA8MFP
16
2
read-write
0
GPIO
#00
1
UART_TX
#01
2
CMP12
#10
3
PWM0CH2
#11
PA9MFP
Alternate Function Setting For PA9MFP
18
2
read-write
0
GPIO
#00
1
UART_RX
#01
2
CMP13
#10
3
PWM0CH3
#11
GPB_MFP
SYS_GPB_MFP
GPIOB multiple alternate functions control register
0x3C
-1
read-write
n
0x0
0x0
PB0MFP
Alternate Function Setting For PB0MFP
0
2
read-write
0
GPIO
#00
1
SPI_SSB1
#01
2
CMP0
#10
3
SPI_SSB0
#11
PB10MFP
Alternate Function Setting For PB10MFP
20
2
read-write
0
GPIO
#00
2
CMP10
#10
PB11MFP
Alternate Function Setting For PB11MFP
22
2
read-write
0
GPIO
#00
1
I2S_SDO
#01
2
CMP11
#10
PB12MFP
Alternate Function Setting For PB12MFP
24
2
read-write
0
GPIO
#00
1
SPI_MISO1
#01
2
PWM1CH0
#10
3
PWM1CH1B
#11
PB13MFP
Alternate Function Setting For PB13MFP
26
2
read-write
0
GPIO
#00
1
SPI_MOSI1
#01
2
PWM1CH1
#10
3
PWM1CH0B
#11
PB14MFP
Alternate Function Setting For PB14MFP
28
2
read-write
0
GPIO
#00
1
PWM0CH2
#01
2
UART_TX
#10
3
PWM0CH3B
#11
PB15MFP
Alternate Function Setting For PB15MFP
30
2
read-write
0
GPIO
#00
1
PWM0CH3
#01
3
PWM0CH2B
#11
PB1MFP
Alternate Function Setting For PB1MFP
2
2
read-write
0
GPIO
#00
1
MCLK
#01
2
CMP1
#10
3
SPI_SSB1
#11
PB2MFP
Alternate Function Setting For PB2MFP
4
2
read-write
0
GPIO
#00
1
I2C_SCL
#01
2
CMP2
#10
3
SPI_SCLK
#11
PB3MFP
Alternate Function Setting For PB3MFP
6
2
read-write
0
GPIO
#00
1
I2C_SDA
#01
2
CMP3
#10
3
SPI_MISO0
#11
PB4MFP
Alternate Function Setting For PB4MFP
8
2
read-write
0
GPIO
#00
1
PWM0CH0B
#01
2
CMP4
#10
3
SPI_MOSI0
#11
PB5MFP
Alternate Function Setting For PB5MFP
10
2
read-write
0
GPIO
#00
1
PWM0CH1B
#01
2
CMP5
#10
3
SPI_MISO1
#11
PB6MFP
Alternate Function Setting For PB6MFP
12
2
read-write
0
GPIO
#00
1
I2S_SDI
#01
2
CMP6
#10
3
SPI_MOSI1
#11
PB7MFP
Alternate Function Setting For PB7MFP
14
2
read-write
0
GPIO
#00
1
I2S_SDO
#01
2
CMP7
#10
PB8MFP
Alternate Function Setting For PB8MFP
16
2
read-write
0
GPIO
#00
1
I2S_FS(master)
#01
2
CMP8
#10
PB9MFP
Alternate Function Setting For PB9MFP
18
2
read-write
0
GPIO
#00
1
I2S_BCLK(master)
#01
2
CMP9
#10
IPRST0
SYS_IPRST0
IP Reset Control Resister0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles.
CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded.
This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPURST
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
PDMARST
PDMA Controller Reset
Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state
2
1
read-write
0
Normal operation
#0
1
PDMA IP reset
#1
IPRST1
SYS_IPRST1
IP Reset Control Resister1
0xC
-1
read-write
n
0x0
0x0
ACMPRST
Analog Comparator Reset
22
1
read-write
0
Normal Operation
#0
1
Reset
#1
ANARST
Analog Block Control Reset
30
1
read-write
0
Normal Operation
#0
1
Reset
#1
BIQRST
Biquad Filter Block Reset
18
1
read-write
0
Normal Operation
#0
1
Reset
#1
CRCRST
CRC Generation Block Reset
19
1
read-write
0
Normal Operation
#0
1
Reset
#1
DPWMRST
DPWM Speaker Driver Reset
13
1
read-write
0
Normal Operation
#0
1
Reset
#1
EADCRST
ADC Controller Reset
28
1
read-write
0
Normal Operation
#0
1
Reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
Normal Operation
#0
1
Reset
#1
I2S0RST
I2S Controller Reset
29
1
read-write
0
Normal Operation
#0
1
Reset
#1
PWM0RST
PWM0 Controller Reset
20
1
read-write
0
Normal Operation
#0
1
Reset
#1
PWM1RST
PWM1 Controller Reset
21
1
read-write
0
Normal Operation
#0
1
Reset
#1
SPI0RST
SPI0 Controller Reset
12
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR0RST
Timer0 Controller Reset
6
1
read-write
0
Normal Operation
#0
1
Reset
#1
TMR1RST
Timer1 Controller Reset
7
1
read-write
0
Normal Operation
#0
1
Reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
Normal Operation
#0
1
Reset
#1
IRCTCTL
SYS_IRCTCTL
Oscillator Frequency Adjustment control register
0x110
-1
read-write
n
0x0
0x0
FREQ0SEL
Frequency Select
8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
0
8
read-write
FREQ1SEL
Frequency Select
8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
16
8
read-write
RGE0SEL
Range Bit For Oscillator
8
1
read-write
0
high range
#0
1
low range
#1
RGE1SEL
Range Bit For Oscillator
24
1
read-write
0
high range
#0
1
low range
#1
PASMTEN
SYS_PASMTEN
GPIOA input type control register
0x30
-1
read-write
n
0x0
0x0
SMTEN16
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
16
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN17
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
17
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN18
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
18
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN19
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
19
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN20
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
20
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN21
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
21
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN22
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
22
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN23
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
23
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN24
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
24
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN25
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
25
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN26
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
26
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN27
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
27
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN28
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
28
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN29
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
29
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN30
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
30
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
SMTEN31
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
31
1
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger disabled
#0
1
GPIOA[15:0] I/O input Schmitt Trigger enabled
#1
PBSMTEN
SYS_PBSMTEN
GPIOB input type control register
0x34
-1
read-write
n
0x0
0x0
SMTEN16
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
16
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN17
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
17
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN18
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
18
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN19
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
19
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN20
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
20
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN21
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
21
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN22
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
22
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
SMTEN23
Schmitt Trigger
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
23
1
read-write
0
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
#0
1
GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
#1
PDID
SYS_PDID
Product ID
0x0
-1
read-only
n
0x0
0x0
PDID
Product Identifier
Chip identifier for ISD9300 series.
0
32
read-only
REGLCTL
SYS_REGLCTL
Register Lock Control
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Protected Register Unlock Register
0
1
read-write
0
Protected registers are locked. Any write to the target register is ignored
#0
1
Protected registers are unlocked
#1
RSTSTS
SYS_RSTSTS
System Reset Source Register
0x4
-1
read-write
n
0x0
0x0
CORERSTF
Reset Source From CORE
The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset.
This bit is cleared by writing 1 to itself.
0
1
read-write
0
No reset from CORE
#0
1
Core was reset by hardware block
#1
CPURF
Reset Source From CPU
The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).
This bit is cleared by writing 1 to itself.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 CPU kernel and FMC has been reset by software setting CPURST to 1
#1
DPDRSTF
Deep Power Down Reset Flag
The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
9
1
read-write
0
No detected
#0
1
A power on was triggered by DPD timer
#1
PMURSTF
Reset Source From PMU
The PMURSTF flag is set if the PMU.
This bit is cleared by writing 1 to itself.
6
1
read-write
0
No reset from PMU
#0
1
PMU reset the system from a power down/standby event
#1
PORF
Power On Reset Flag
The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
10
1
read-write
0
No detected
#0
1
A power on Reset has occurred
#1
SYSRF
Reset Source From MCU
The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel.
This bit is cleared by writing 1 to itself.
5
1
read-write
0
No reset from MCU
#0
1
The Cortex_M0 MCU issued a reset signal to reset the system by software writing 1 to bit SYSRESTREQ(SYSCTL_AIRCTL[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel
#1
WDTRF
Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
This bit is cleared by writing 1 to itself.
2
1
read-write
0
No reset from Watch-Dog
#0
1
The Watch-Dog module issued the reset signal to reset the system
#1
WKRSTF
Wakeup Pin Reset Flag
The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin.
This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
8
1
read-write
0
No detected
#0
1
A power on was triggered by WAKEUP pin
#1
WKCTL
SYS_WKCTL
WAKEUP pin control register
0x54
-1
read-write
n
0x0
0x0
WKDIN
State Of Wakeup Pin
Read only.
0
1
read-write
WKDOUT
Wakeup Output State
Default set 0
3
1
read-write
WKOENB
Wakeup Pin Output Enable Bar
2
1
read-write
0
drive WKDOUT to pin
#0
1
tri-state (default)
#1
WKPUEN
Wakeup Pin Pull-Up Control
This signal is latched in deep power down and preserved.
1
1
read-write
0
pull-up enable
#0
1
tri-state (default)
#1
SYSINFO
SYSINFO Register Map
SYSINFO
0x0
0x0
0x8
registers
n
0x1C
0x8
registers
n
0xC
0x8
registers
n
SYSCTL_AIRCTL
SYSCTL_AIRCTL
Application Interrupt and Reset Control Register
0xC
-1
read-write
n
0x0
0x0
CLRACTVT
Clear All Active Vector
Clears all active state information for fixed and configurable exceptions.
The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE.
1
1
read-write
0
do not clear state information
#0
1
clear state information
#1
ENDIANES
Endianness
Read Only. Reads 0 indicating little endian machine.
15
1
read-write
SRSTREQ
System Reset Request
Writing 1 to this bit asserts a signal to request a reset by the external system.
2
1
read-write
0
do not request a reset
#0
1
request reset
#1
VTKEY
Vector Key
The value 0x05FA must be written to this register, otherwise
a write to register is UNPREDICTABLE.
16
16
read-write
SYSCTL_CPUID
SYSCTL_CPUID
CPUID Base Register
0x0
-1
read-only
n
0x0
0x0
IMPCODE
Implementer Code Assigned By ARM
ARM aaa 0x41.
24
8
read-only
PART
ARMv6-M Parts
Reads as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Part Number
Reads as 0xC20.
4
12
read-only
REVISION
Revision
Reads as 0x0
0
4
read-only
SYSCTL_ICSR
SYSCTL_ICSR
Interrupt Control State Register
0x4
-1
read-write
n
0x0
0x0
ISRPEND
ISR Pending
Indicates if an external configurable (NVIC generated) interrupt is pending.
22
1
read-write
ISRPREEM
ISR Preemptive
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-write
NMIPNSET
NMI Pending Set Control
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
31
1
read-write
PPSVICLR
Clear A Pending PendSV Interrupt
Write 1 to clear a pending PendSV interrupt.
27
1
read-write
PPSVISET
Set A Pending PendSV Interrupt
This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
28
1
read-write
PSTKICLR
Clear A Pending SYST
Write 1 to clear a pending SYST.
25
1
read-write
PSTKISET
Set A Pending SYST
Reads back with current state (1 if Pending, 0 if not).
26
1
read-write
VTACT
Vector Active
0: Thread mode
Value > 1: the exception number for the current executing exception.
0
9
read-write
VTPEND
Vector Pending
Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
12
9
read-write
SYSCTL_SCR
SYSCTL_SCR
System Control Register
0x10
-1
read-write
n
0x0
0x0
SEVNONPN
Send Event On Pending Bit
When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
4
1
read-write
0
only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLPDEEP
Controls Whether The Processor Uses Sleep Or Deep Sleep As Its Low Power Mode
The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states.
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLPONEXC
Sleep On Exception
When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
SYSCTL_SHPR2
SYSCTL_SHPR2
System Handler Priority Register 2
0x1C
-1
read-write
n
0x0
0x0
PRI11
Priority Of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SYSCTL_SHPR3
SYSCTL_SHPR3
System Handler Priority Register 3
0x20
-1
read-write
n
0x0
0x0
PRI14
Priority Of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes lowest priority
22
2
read-write
PRI15
Priority Of System Handler 15 - SYST
0 denotes the highest priority and 3 denotes lowest priority
30
2
read-write
SYSTICK
SYSTICK Register Map
SYSTICK
0x0
0x0
0xC
registers
n
SYST_CSR
SYST_CSR
SYST Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKSRC
Clock Source
2
1
read-write
0
Clock selected from CLK_CLKSEL0.STCLKSEL is used as clock source
#0
1
Core clock used for SYST
#1
COUNTFLAG
Count Flag
Returns 1 if timer counted to 0 since last time this register was read.
16
1
read-write
0
Cleared on read or by a write to the Current Value register
#0
1
Set by a count transition from 1 to 0
#1
ENABLE
ENABLE
0
1
read-write
0
The counter is disabled
#0
1
The counter will operate in a multi-shot manner
#1
TICKINT
Enables SYST Exception Request
1
1
read-write
0
Counting down to 0 does not cause the SYST exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause SYST exception to be pended. Clearing the SYST Current Value register by a register write in software will not cause SYST to be pended
#1
SYST_CVR
SYST_CVR
SYST Current Value Register
0x8
-1
read-write
n
0x0
0x0
CURRENT
Current Counter Value
This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit.
0
24
read-write
SYST_RVR
SYST_RVR
SYST Reload Value Register
0x4
-1
read-write
n
0x0
0x0
RELOAD
SYST Reload
Value to load into the Current Value register when the counter reaches 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SYST interrupt is required every 200 clock pulses, set RELOAD to 199.
0
24
read-write
TMR0
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
TIMERx_CMP
TIMERx_CMP
Timer Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN aaa 1. The CMPDAT value defines the timer cycle time.
Time out period aaa (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT)
NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count.
0
25
read-write
TIMERx_CNT
TIMERx_CNT
Timer Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value.
0
24
read-write
TIMERx_CTL
TIMERx_CTL
Timer Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTDATEN
Data Latch Enable
When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
CNTEN
Counter Enable Bit
Note1: Setting CNTEN aaa 1 enables 24-bit counter. It continues count from last value.
Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE aaa 00b) when the timer interrupt is generated (INTEN aaa 1b).
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware
0
1
The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)
1
2
RESERVED
2
3
The timer is operating in continuous counting mode. The associated interrupt signal is generated when CNT = TIMERx_CMP (if INTEN is enabled) however, the 24-bit up-counter counts continuously without reset
3
PSC
Pre-Scale Counter
Clock input is divided by PSC+1 before it is fed to the counter. If PSC aaa 0, then there is no scaling.
0
8
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 24-bit up-counter and CNTEN bit
#1
TIMERx_INTSTS
TIMERx_INTSTS
Timer Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1.
0
1
read-write
TMR1
TMR Register Map
TMR
0x0
0x0
0x10
registers
n
TIMERx_CMP
TIMERx_CMP
Timer Compare Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparison Value
CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN aaa 1. The CMPDAT value defines the timer cycle time.
Time out period aaa (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT)
NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CEN state, whenever a new value is written to this register, TIMER will restart counting using this new value and abort previous count.
0
25
read-write
TIMERx_CNT
TIMERx_CNT
Timer Data Register
0xC
-1
read-write
n
0x0
0x0
CNT
Timer Data Register
When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value.
0
24
read-write
TIMERx_CTL
TIMERx_CTL
Timer Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the counter status of timer.
25
1
read-only
0
Timer is not active
#0
1
Timer is active
#1
CNTDATEN
Data Latch Enable
When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.
16
1
read-write
0
Timer Data Register update disable
#0
1
Timer Data Register update enable
#1
CNTEN
Counter Enable Bit
Note1: Setting CNTEN aaa 1 enables 24-bit counter. It continues count from last value.
Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE aaa 00b) when the timer interrupt is generated (INTEN aaa 1b).
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
INTEN
Interrupt Enable Bit
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TIMERx_CMP.
29
1
read-write
0
Disable TIMER Interrupt
#0
1
Enable TIMER Interrupt
#1
OPMODE
Timer Operating Mode
27
2
read-write
0
The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware
0
1
The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled)
1
2
RESERVED
2
3
The timer is operating in continuous counting mode. The associated interrupt signal is generated when CNT = TIMERx_CMP (if INTEN is enabled) however, the 24-bit up-counter counts continuously without reset
3
PSC
Pre-Scale Counter
Clock input is divided by PSC+1 before it is fed to the counter. If PSC aaa 0, then there is no scaling.
0
8
read-write
RSTCNT
Counter Reset Bit
Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.
26
1
read-write
0
No effect
#0
1
Reset Timer's pre-scale counter, internal 24-bit up-counter and CNTEN bit
#1
TIMERx_INTSTS
TIMERx_INTSTS
Timer Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1.
0
1
read-write
UART0
UART0 Register Map
UART0
0x0
0x0
0x34
registers
n
UART_ALTCTL
UART_ALTCTL
UART0 LIN Control Register.
0x2C
-1
read-write
n
0x0
0x0
BRKFL
UART LIN Break Field Length Count
This field indicates a 4-bit LIN Tx break field count.
NOTE: This break field length is BRKFL + 2
0
4
read-write
LINRXEN
LIN RX Enable
6
1
read-write
0
Disable LIN Rx mode
#0
1
Enable LIN Rx mode
#1
LINTXEN
LIN TX Break Mode Enable
NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
Disable LIN Tx Break Mode
#0
1
Enable LIN Tx Break Mode
#1
UART_BAUD
UART_BAUD
UART0 Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
Divider X Equal 1
0: M aaa EDIVM1+1, with restriction EDIVM1 ≥ 8.
1: M aaa 1, with restriction BRD[15:0] ≥ 3.
Refer to Table 5111 for more information.
28
1
read-write
BAUDM1
Divider X Enable
The baud rate equation is: Baud Rate aaa UART_CLK / [ M * (BRD + 2) ] The default value of M is 16.
Refer to Table 5111 for more information.
NOTE: When in IrDA mode, this bit must disabled.
29
1
read-write
0
Disable divider X ( M aaa 16)
#0
1
Enable divider X (M aaa EDIVM1+1, with EDIVM1 ≥ 8)
#1
BRD
Baud Rate Divider
Refer to Table 5111 for more information.
0
16
read-write
EDIVM1
Divider X
The baud rate divider M aaa EDIVM1+1.
24
4
read-write
UART_DAT
UART_DAT
UART0 Receive/Transfer FIFO Register.
0x0
-1
read-write
n
0x0
0x0
DAT
Receive FIFO Register
Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).
0
8
read-write
UART_FIFO
UART_FIFO
UART0 FIFO Control Register.
0x8
-1
read-write
n
0x0
0x0
RFITL
Receive FIFO Interrupt (RDAINT) Trigger Level
When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and, if enabled, an RDAINT interrupt will generated.
Value : INTR_RDA Trigger Level (Bytes)
0 : 1
1 : 4
2 : 8
4
4
read-write
RTSTRGLV
RTS Trigger Level For Auto-Flow Control
Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).
Value : Trigger Level (Bytes)
0 : 1
1 : 4
2 : 8
16
4
read-write
RXRST
Receive FIFO Reset
When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
1
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the receiving internal state machine and pointers
#1
TXRST
Transmit FIFO Reset
When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
2
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Writing 1 to this bit will reset the transmit internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART0 FIFO Status Register.
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
6
1
read-write
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
5
1
read-write
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
4
1
read-write
RXEMPTY
Receive FIFO Empty (Read Only)
This bit indicates whether the Rx FIFO is empty or not.
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RXFULL
Receive FIFO Full (Read Only)
This bit indicates whether the Rx FIFO is full or not.
This bit is set when Rx FIFO is full otherwise it is cleared by hardware.
15
1
read-only
RXOVIF
Rx Overflow Error Interrupt Flag
If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
RXPTR
Rx FIFO Pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
8
6
read-only
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit indicates whether the Tx FIFO is empty or not.
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
22
1
read-only
TXEMPTYF
Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
NOTE: This bit is read only.
28
1
read-only
TXFULL
Transmit FIFO Full (Read Only)
This bit indicates whether the Tx FIFO is full or not.
23
1
read-only
TXOVIF
Tx Overflow Error Interrupt Flag
If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
24
1
read-write
TXPTR
Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UART0 Function Select Register.
0x30
-1
read-write
n
0x0
0x0
IRDAEN
Enable IrDA Function
1
1
read-write
0
UART Function
#0
1
Enable IrDA Function
#1
LINEN
Enable LIN Function
Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.
0
1
read-write
0
UART Function
#0
1
Enable LIN Function
#1
UART_INTEN
UART_INTEN
UART0 Interrupt Enable Register.
0x4
-1
read-write
n
0x0
0x0
ATOCTSEN
CTS Auto Flow Control Enable
When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted).
13
1
read-write
0
Disable CTS auto flow control
#0
1
Enable
#1
ATORTSEN
RTS Auto Flow Control Enable
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.
12
1
read-write
0
Disable RTS auto flow control
#0
1
Enable
#1
BUFERRIEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off BUFERRINT
#0
1
Enable IBUFERRINT
#1
DMARXEN
Receive DMA Enable
If enabled, the UART will request DMA service when data is available in receive FIFO.
15
1
read-write
DMATXEN
Transmit DMA Enable
If enabled, the UART will request DMA service when space is available in transmit FIFO.
14
1
read-write
LINIEN
LIN RX Break Field Detected Interrupt Enable
8
1
read-write
0
Mask off Lin bus Rx break field interrupt
#0
1
Enable Lin bus Rx break field interrupt
#1
MODEMIEN
Modem Status Interrupt Enable
3
1
read-write
0
Mask off MODEMINT
#0
1
Enable MODEMINT
#1
RDAIEN
Receive Data Available Interrupt Enable
0
1
read-write
0
Mask off RDAINT
#0
1
Enable RDAINT
#1
RLSIEN
Receive Line Status Interrupt Enable
2
1
read-write
0
Mask off RLSINT
#0
1
Enable RLSINT
#1
RXTOIEN
Receive Time Out Interrupt Enable
4
1
read-write
0
Mask off RXTOINT
#0
1
Enable RXTOINT
#1
THREIEN
Transmit FIFO Register Empty Interrupt Enable
1
1
read-write
0
Mask off THERINT
#0
1
Enable THERINT
#1
TOCNTEN
Time-Out Counter Enable
11
1
read-write
0
Disable Time-out counter
#0
1
Enable
#1
UART_INTSTS
UART_INTSTS
UART0 Interrupt Status Register.
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
5
1
read-only
BUFERRINT
Buffer Error Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.
13
1
read-write
DBERRIF
DMA MODE Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
21
1
read-only
DBERRINT
DMA MODE Buffer Error Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF.
29
1
read-write
DLINIF
DMA MODE LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
23
1
read-write
DLININT
DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF.
31
1
read-write
DMODEMI
DMA MODE MODEM Status Interrupt Indicator To Interrupt
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF.
27
1
read-write
DMODEMIF
DMA MODE MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
19
1
read-only
DRLSIF
DMA MODE Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
DRLSINT
DMA MODE Receive Line Status Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.
26
1
read-write
DRXTOIF
DMA MODE Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
20
1
read-only
DRXTOINT
DMA MODE Time Out Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF.
28
1
read-write
LINIF
LIN Bus Rx Break Field Detected Flag
This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.
7
1
read-write
LININT
LIN Bus Rx Break Field Detected Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.LINIEN and LINIF.
15
1
read-write
MODEMINT
MODEM Status Interrupt Indicator To Interrupt
Logical AND of UART_INTEN.MODEMIEN and MODENIF.
11
1
read-write
MODENIF
MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
3
1
read-only
RDAIF
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.
NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
0
1
read-only
RDAINT
Receive Data Available Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.RDAIEN and RDAIF.
8
1
read-write
RLSIF
Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLSINT
Receive Line Status Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.RLSIEN and RLSIF.
10
1
read-write
RXTOIF
Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
4
1
read-only
RXTOINT
Time Out Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.RXTOIEN and RXTOIF.
12
1
read-write
THERINT
Transmit Holding Register Empty Interrupt Indicator To Interrupt Controller
Logical AND of UART_INTEN.THREIEN and THREIF.
9
1
read-write
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.
NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
1
1
read-only
UART_IRDA
UART_IRDA
UART0 IrDA Control Register.
0x28
-1
read-write
n
0x0
0x0
LOOPBACK
IrDA Loopback Test Mode
Loopback Tx to Rx.
2
1
read-write
RXINV
Receive Inversion Enable
6
1
read-write
0
No inversion
#0
1
Invert Rx input signal
#1
TXEN
Transmit/Receive Selection
1
1
read-write
0
Enable IrDA receiver
#0
1
Enable IrDA transmitter
#1
TXINV
Transmit Inversion Enable
5
1
read-write
0
No inversion
#0
1
Invert Tx output signal
#1
UART_LINE
UART_LINE
UART0 Line Control Register.
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable
This bit has effect only when PBE (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1's are transmitted or checked in the data word and parity bits
#1
NSB
Number Of STOP Bits
2
1
read-write
0
One STOP bit is generated after the transmitted data
#0
1
Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected
#1
PBE
Parity Bit Enable
3
1
read-write
0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Disable stick parity
#0
1
When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared
#1
WLS
Word Length Select
0 (5bits), 1(6bits), 2(7bits), 3(8bits)
0
2
read-write
UART_MODEM
UART_MODEM
UART0 Modem Control Register.
0x10
-1
read-write
n
0x0
0x0
LBMEN
Loopback Mode Enable
4
1
read-write
0
Disable
#0
1
Enable
#1
RTS
RTS (Request-To-Send) Signal
If UART_INTEN.ATORTSEN aaa 0, this bit controls whether RTS pin is active or not.
1
1
read-write
0
Drive RTS inactive ( aaa ~RTSACTLV)
#0
1
Drive RTS active ( aaa RTSACTLV)
#1
RTSACTLV
Request-To-Send (RTS) Active Trigger Level
This bit can change the RTS trigger level.
9
1
read-write
0
RTS is active low level
#0
1
RTS is active high level
#1
RTSSTS
RTS Pin State (Read Only)
This bit is the pin status of RTS.
13
1
read-only
UART_MODEMSTS
UART_MODEMSTS
UART0 Modem Status Register.
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
Clear-To-Send (CTS) Active Trigger Level
This bit can change the CTS trigger level.
8
1
read-write
0
CTS is active low level
#0
1
CTS is active high level
#1
CTSDETF
Detect CTS State Change Flag
This bit is set whenever CTS input has state change. It will generate Modem interrupt to CPU when UART_INTEN.MODEMIEN aaa 1
NOTE: This bit is cleared by writing 1 to itself.
0
1
read-write
CTSSTS
CTS Pin Status (Read Only)
This bit is the pin status of CTS.
4
1
read-only
UART_TOUT
UART_TOUT
UART0 Time Out Register
0x20
-1
read-write
n
0x0
0x0
TOIC
Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears RXTOIF. The period of the time out counter is the baud rate.
0
7
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
IF
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
NOTE: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog timer interrupt has not occurred
#0
1
Watchdog timer interrupt has occurred
#1
INTEN
Watchdog Timer Interrupt Enable
6
1
read-write
0
Disable the Watchdog timer interrupt
#0
1
Enable the Watchdog timer interrupt
#1
RSTCNT
Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
NOTE: This bit will auto clear after few clock cycle
0
1
read-write
0
Writing 0 to this bit has no effect
#0
1
Reset the contents of the Watchdog timer
#1
RSTEN
Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
1
1
read-write
0
Disable Watchdog timer reset function
#0
1
Enable Watchdog timer reset function
#1
RSTF
Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
NOTE: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog timer reset has not occurred
#0
1
Watchdog timer reset has occurred
#1
TOUTSEL
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:
Interrupt Timeout aaa 2^(2xTOUTSEL+4) x WDT_CLK
Reset Timeout aaa (2^(2xTOUTSEL+4) +1024) x WDT_CLK
Where WDT_CLK is the period of the Watchdog Timer clock source.
8
3
read-write
WDTEN
Watchdog Timer Enable
7
1
read-write
0
Disable the Watchdog timer (This action will reset the internal counter)
#0
1
Enable the Watchdog timer
#1