nuvoTon KM1M7AF52x 2024.04.28 KM1M7AF is a 32-bit microcontroller CM7 r1p1 little true true 4 false 8 32 ADC A/D Converter ADC 0x0 0x0 0x2B4 registers n G35 35 G36 36 G37 37 G38 38 G39 39 G40 40 G41 41 ADC0BUF00 A/D0 Conversion Data Buffer 00 Register 0x60 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF01 A/D0 Conversion Data Buffer 01 Register 0x64 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF02 A/D0 Conversion Data Buffer 02 Register 0x68 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF03 A/D0 Conversion Data Buffer 03 Register 0x6C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF04 A/D0 Conversion Data Buffer 04 Register 0x70 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF05 A/D0 Conversion Data Buffer 05 Register 0x74 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF06 A/D0 Conversion Data Buffer 06 Register 0x78 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF07 A/D0 Conversion Data Buffer 07 Register 0x7C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF08 A/D0 Conversion Data Buffer 08 Register 0x80 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF09 A/D0 Conversion Data Buffer 09 Register 0x84 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF10 A/D0 Conversion Data Buffer 10 Register 0x88 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF11 A/D0 Conversion Data Buffer 11 Register 0x8C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF12 A/D0 Conversion Data Buffer 12 Register 0x90 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF13 A/D0 Conversion Data Buffer 13 Register 0x94 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF14 A/D0 Conversion Data Buffer 14 Register 0x98 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUF15 A/D0 Conversion Data Buffer 15 Register 0x9C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC0CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUFB0 A/D0 Conversion Data Buffer B0 Register 0xA0 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC0CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUFB1 A/D0 Conversion Data Buffer B1 Register 0xA4 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC0CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUFB2 A/D0 Conversion Data Buffer B2 Register 0xA8 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC0CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0BUFB3 A/D0 Conversion Data Buffer B3 Register 0xAC 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC0CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC0CHECK A/D0 Fault Check Co0trol Register 0xB0 8 read-write n CHKEN Fault diagnosis function select 0 1 read-write CHKSEL Conversion Potential select 1 3 read-write __reserve0 0 is always read out. 3 8 read ADC0CHSEL00 A/D0 Conversion Channel 00 Selection Register 0x20 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL01 A/D0 Conversion Channel 01 Selection Register 0x22 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL02 A/D0 Conversion Channel 02 Selection Register 0x24 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL03 A/D0 Conversion Channel 03 Selection Register 0x26 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL04 A/D0 Conversion Channel 04 Selection Register 0x28 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL05 A/D0 Conversion Channel 05 Selection Register 0x2A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL06 A/D0 Conversion Channel 06 Selection Register 0x2C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL07 A/D0 Conversion Channel 07 Selection Register 0x2E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL08 A/D0 Conversion Channel 08 Selection Register 0x30 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL09 A/D0 Conversion Channel 09 Selection Register 0x32 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL10 A/D0 Conversion Channel 10 Selection Register 0x34 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL11 A/D0 Conversion Channel 11 Selection Register 0x36 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL12 A/D0 Conversion Channel 12 Selection Register 0x38 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL13 A/D0 Conversion Channel 13 Selection Register 0x3A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL14 A/D0 Conversion Channel 14 Selection Register 0x3C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSEL15 A/D0 Conversion Channel 15 Selection Register 0x3E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSELB0 A/D0 Conversion Channel B0 Selection Register 0x40 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSELB1 A/D0 Conversion Channel B1 Selection Register 0x42 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSELB2 A/D0 Conversion Channel B2 Selection Register 0x44 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CHSELB3 A/D0 Conversion Channel B3 Selection Register 0x46 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC0CTR0 A/D0 Co0versio0 Co0trol Register 0 0x0 16 read-write n CK ADCK select 1 4 read-write ON A/Dn operation mode 0 1 read-write __reserve0 0 is always read out. 4 16 read ADC0CTR1A A/D0 Co0versio0 Co0trol Register 1A 0x4 16 read-write n AECH Conversion end channel setting 4 8 read-write AEN A/D conversion start 0 1 read-write AMD A/D conversion mode select 2 3 read-write ATRG A/D conversion start by using trigger A 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read ADC0CTR1B A/D0 Co0versio0 Co0trol Register 1B 0x8 16 read-write n BECH Conversion end channel setting 4 6 read-write BEN A/D conversion start 0 1 read-write BMD A/D conversion mode select 2 3 read-write BTRG A/D conversion start by using trigger B 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 6 16 read ADC0CTREGA A/D0 Co0versio0 Start Trigger A Cou0t Register 0x14 8 read-write n ACNT The number for reducing start trigger A (at the second or later A/D conversion) 0 4 read-write ACNTI The number for reducing start trigger A (at the first A/D conversion) 4 8 read-write ADC0CTREGB A/D0 Co0versio0 Start Trigger B Cou0t Register 0x18 8 read-write n BCNT The number for reducing start trigger B (at the second or later A/D conversion) 0 4 read-write BCNTI The number for reducing start trigger B (at the first A/D conversion) 4 8 read-write ADC0ERCA A/D0 Co0versio0 Error Detectio0 Cha00el Setti0g Register A 0x48 16 read-write n ERCACH0 Error detection setting (the channel selected by setting ANnCHSEL00). 0 1 read-write ERCACH1 Error detection setting (the channel selected by setting ANnCHSEL01). 1 2 read-write ERCACH10 Error detection setting (the channel selected by setting ANnCHSEL10). 10 11 read-write ERCACH11 Error detection setting (the channel selected by setting ANnCHSEL11). 11 12 read-write ERCACH12 Error detection setting (the channel selected by setting ANnCHSEL12). 12 13 read-write ERCACH13 Error detection setting (the channel selected by setting ANnCHSEL13). 13 14 read-write ERCACH14 Error detection setting (the channel selected by setting ANnCHSEL14). 14 15 read-write ERCACH15 Error detection setting (the channel selected by setting ANnCHSEL15). 15 16 read-write ERCACH2 Error detection setting (the channel selected by setting ANnCHSEL02). 2 3 read-write ERCACH3 Error detection setting (the channel selected by setting ANnCHSEL03). 3 4 read-write ERCACH4 Error detection setting (the channel selected by setting ANnCHSEL04). 4 5 read-write ERCACH5 Error detection setting (the channel selected by setting ANnCHSEL05). 5 6 read-write ERCACH6 Error detection setting (the channel selected by setting ANnCHSEL06). 6 7 read-write ERCACH7 Error detection setting (the channel selected by setting ANnCHSEL07). 7 8 read-write ERCACH8 Error detection setting (the channel selected by setting ANnCHSEL08). 8 9 read-write ERCACH9 Error detection setting (the channel selected by setting ANnCHSEL09). 9 10 read-write ADC0ERCB A/D0 Co0versio0 Error Detectio0 Cha00el Setti0g Register B 0x4C 16 read-write n ERCBCH0 Error detection setting (the channel selected by setting ANnCHSELB0). 0 1 read-write ERCBCH1 Error detection setting (the channel selected by setting ANnCHSELB1). 1 2 read-write ERCBCH2 Error detection setting (the channel selected by setting ANnCHSELB2). 2 3 read-write ERCBCH3 Error detection setting (the channel selected by setting ANnCHSELB3). 3 4 read-write __reserve0 0 is always read out. 4 16 read ADC0LOWA A/D0 Co0versio0 Error Detectio0 Lower Limit Setti0g Register A 0x50 16 read-write n LOWA Set the lower limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC0LOWB A/D0 Co0versio0 Error Detectio0 Lower Limit Setti0g Register B 0x58 16 read-write n LOWB Set the lower limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC0ST A/D0 Co0versio0 Start Trigger Selectio0 Register 0x10 16 read-write n AST Start trigger A for A/Dn conversion 0 5 read-write BST Start trigger B for A/Dn conversion 8 13 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 13 16 read ADC0UPA A/D0 Co0versio0 Error Detectio0 Upper Limit Setti0g Register A 0x54 16 read-write n UPA Set the upper limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC0UPB A/D0 Co0versio0 Error Detectio0 Upper Limit Setti0g Register B 0x5C 16 read-write n UPB Set the upper limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC1BUF00 A/D1 Conversion Data Buffer 00 Register 0x160 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF01 A/D1 Conversion Data Buffer 01 Register 0x164 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF02 A/D1 Conversion Data Buffer 02 Register 0x168 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF03 A/D1 Conversion Data Buffer 03 Register 0x16C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF04 A/D1 Conversion Data Buffer 04 Register 0x170 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF05 A/D1 Conversion Data Buffer 05 Register 0x174 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF06 A/D1 Conversion Data Buffer 06 Register 0x178 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF07 A/D1 Conversion Data Buffer 07 Register 0x17C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF08 A/D1 Conversion Data Buffer 08 Register 0x180 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF09 A/D1 Conversion Data Buffer 09 Register 0x184 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF10 A/D1 Conversion Data Buffer 10 Register 0x188 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF11 A/D1 Conversion Data Buffer 11 Register 0x18C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF12 A/D1 Conversion Data Buffer 12 Register 0x190 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF13 A/D1 Conversion Data Buffer 13 Register 0x194 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF14 A/D1 Conversion Data Buffer 14 Register 0x198 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUF15 A/D1 Conversion Data Buffer 15 Register 0x19C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC1CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUFB0 A/D1 Conversion Data Buffer B0 Register 0x1A0 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC1CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUFB1 A/D1 Conversion Data Buffer B1 Register 0x1A4 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC1CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUFB2 A/D1 Conversion Data Buffer B2 Register 0x1A8 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC1CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1BUFB3 A/D1 Conversion Data Buffer B3 Register 0x1AC 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC1CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC1CHECK A/D1 Fault Check Co1trol Register 0x1B0 8 read-write n CHKEN Fault diagnosis function select 0 1 read-write CHKSEL Conversion Potential select 1 3 read-write __reserve0 0 is always read out. 3 8 read ADC1CHSEL00 A/D1 Conversion Channel 00 Selection Register 0x120 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL01 A/D1 Conversion Channel 01 Selection Register 0x122 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL02 A/D1 Conversion Channel 02 Selection Register 0x124 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL03 A/D1 Conversion Channel 03 Selection Register 0x126 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL04 A/D1 Conversion Channel 04 Selection Register 0x128 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL05 A/D1 Conversion Channel 05 Selection Register 0x12A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL06 A/D1 Conversion Channel 06 Selection Register 0x12C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL07 A/D1 Conversion Channel 07 Selection Register 0x12E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL08 A/D1 Conversion Channel 08 Selection Register 0x130 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL09 A/D1 Conversion Channel 09 Selection Register 0x132 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL10 A/D1 Conversion Channel 10 Selection Register 0x134 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL11 A/D1 Conversion Channel 11 Selection Register 0x136 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL12 A/D1 Conversion Channel 12 Selection Register 0x138 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL13 A/D1 Conversion Channel 13 Selection Register 0x13A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL14 A/D1 Conversion Channel 14 Selection Register 0x13C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSEL15 A/D1 Conversion Channel 15 Selection Register 0x13E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSELB0 A/D1 Conversion Channel B0 Selection Register 0x140 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSELB1 A/D1 Conversion Channel B1 Selection Register 0x142 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSELB2 A/D1 Conversion Channel B2 Selection Register 0x144 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CHSELB3 A/D1 Conversion Channel B3 Selection Register 0x146 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC1CTR0 A/D1 Co1versio1 Co1trol Register 0 0x100 16 read-write n CK ADCK select 1 4 read-write ON A/Dn operation mode 0 1 read-write __reserve0 0 is always read out. 4 16 read ADC1CTR1A A/D1 Co1versio1 Co1trol Register 1A 0x104 16 read-write n AECH Conversion end channel setting 4 8 read-write AEN A/D conversion start 0 1 read-write AMD A/D conversion mode select 2 3 read-write ATRG A/D conversion start by using trigger A 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read ADC1CTR1B A/D1 Co1versio1 Co1trol Register 1B 0x108 16 read-write n BECH Conversion end channel setting 4 6 read-write BEN A/D conversion start 0 1 read-write BMD A/D conversion mode select 2 3 read-write BTRG A/D conversion start by using trigger B 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 6 16 read ADC1CTREGA A/D1 Co1versio1 Start Trigger A Cou1t Register 0x114 8 read-write n ACNT The number for reducing start trigger A (at the second or later A/D conversion) 0 4 read-write ACNTI The number for reducing start trigger A (at the first A/D conversion) 4 8 read-write ADC1CTREGB A/D1 Co1versio1 Start Trigger B Cou1t Register 0x118 8 read-write n BCNT The number for reducing start trigger B (at the second or later A/D conversion) 0 4 read-write BCNTI The number for reducing start trigger B (at the first A/D conversion) 4 8 read-write ADC1ERCA A/D1 Co1versio1 Error Detectio1 Cha11el Setti1g Register A 0x148 16 read-write n ERCACH0 Error detection setting (the channel selected by setting ANnCHSEL00). 0 1 read-write ERCACH1 Error detection setting (the channel selected by setting ANnCHSEL01). 1 2 read-write ERCACH10 Error detection setting (the channel selected by setting ANnCHSEL10). 10 11 read-write ERCACH11 Error detection setting (the channel selected by setting ANnCHSEL11). 11 12 read-write ERCACH12 Error detection setting (the channel selected by setting ANnCHSEL12). 12 13 read-write ERCACH13 Error detection setting (the channel selected by setting ANnCHSEL13). 13 14 read-write ERCACH14 Error detection setting (the channel selected by setting ANnCHSEL14). 14 15 read-write ERCACH15 Error detection setting (the channel selected by setting ANnCHSEL15). 15 16 read-write ERCACH2 Error detection setting (the channel selected by setting ANnCHSEL02). 2 3 read-write ERCACH3 Error detection setting (the channel selected by setting ANnCHSEL03). 3 4 read-write ERCACH4 Error detection setting (the channel selected by setting ANnCHSEL04). 4 5 read-write ERCACH5 Error detection setting (the channel selected by setting ANnCHSEL05). 5 6 read-write ERCACH6 Error detection setting (the channel selected by setting ANnCHSEL06). 6 7 read-write ERCACH7 Error detection setting (the channel selected by setting ANnCHSEL07). 7 8 read-write ERCACH8 Error detection setting (the channel selected by setting ANnCHSEL08). 8 9 read-write ERCACH9 Error detection setting (the channel selected by setting ANnCHSEL09). 9 10 read-write ADC1ERCB A/D1 Co1versio1 Error Detectio1 Cha11el Setti1g Register B 0x14C 16 read-write n ERCBCH0 Error detection setting (the channel selected by setting ANnCHSELB0). 0 1 read-write ERCBCH1 Error detection setting (the channel selected by setting ANnCHSELB1). 1 2 read-write ERCBCH2 Error detection setting (the channel selected by setting ANnCHSELB2). 2 3 read-write ERCBCH3 Error detection setting (the channel selected by setting ANnCHSELB3). 3 4 read-write __reserve0 0 is always read out. 4 16 read ADC1LOWA A/D1 Co1versio1 Error Detectio1 Lower Limit Setti1g Register A 0x150 16 read-write n LOWA Set the lower limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC1LOWB A/D1 Co1versio1 Error Detectio1 Lower Limit Setti1g Register B 0x158 16 read-write n LOWB Set the lower limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC1ST A/D1 Co1versio1 Start Trigger Selectio1 Register 0x110 16 read-write n AST Start trigger A for A/Dn conversion 0 5 read-write BST Start trigger B for A/Dn conversion 8 13 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 13 16 read ADC1UPA A/D1 Co1versio1 Error Detectio1 Upper Limit Setti1g Register A 0x154 16 read-write n UPA Set the upper limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC1UPB A/D1 Co1versio1 Error Detectio1 Upper Limit Setti1g Register B 0x15C 16 read-write n UPB Set the upper limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC2BUF00 A/D2 Conversion Data Buffer 00 Register 0x260 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF01 A/D2 Conversion Data Buffer 01 Register 0x264 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF02 A/D2 Conversion Data Buffer 02 Register 0x268 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF03 A/D2 Conversion Data Buffer 03 Register 0x26C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF04 A/D2 Conversion Data Buffer 04 Register 0x270 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF05 A/D2 Conversion Data Buffer 05 Register 0x274 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF06 A/D2 Conversion Data Buffer 06 Register 0x278 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF07 A/D2 Conversion Data Buffer 07 Register 0x27C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF08 A/D2 Conversion Data Buffer 08 Register 0x280 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF09 A/D2 Conversion Data Buffer 09 Register 0x284 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF10 A/D2 Conversion Data Buffer 10 Register 0x288 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF11 A/D2 Conversion Data Buffer 11 Register 0x28C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF12 A/D2 Conversion Data Buffer 12 Register 0x290 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF13 A/D2 Conversion Data Buffer 13 Register 0x294 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF14 A/D2 Conversion Data Buffer 14 Register 0x298 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUF15 A/D2 Conversion Data Buffer 15 Register 0x29C 16 read-write n BUF A/D conversion results of the channel selected by setting ADC2CHSELm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUFB0 A/D2 Conversion Data Buffer B0 Register 0x2A0 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC2CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUFB1 A/D2 Conversion Data Buffer B1 Register 0x2A4 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC2CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUFB2 A/D2 Conversion Data Buffer B2 Register 0x2A8 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC2CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2BUFB3 A/D2 Conversion Data Buffer B3 Register 0x2AC 16 read-write n BUFB A/D conversion results of the channel selected by setting ADC2CHSELBm. 0 12 read __reserve0 0 is always read out. 12 16 read ADC2CHECK A/D2 Fault Check Co2trol Register 0x2B0 8 read-write n CHKEN Fault diagnosis function select 0 1 read-write CHKSEL Conversion Potential select 1 3 read-write __reserve0 0 is always read out. 3 8 read ADC2CHSEL00 A/D2 Conversion Channel 00 Selection Register 0x220 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL01 A/D2 Conversion Channel 01 Selection Register 0x222 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL02 A/D2 Conversion Channel 02 Selection Register 0x224 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL03 A/D2 Conversion Channel 03 Selection Register 0x226 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL04 A/D2 Conversion Channel 04 Selection Register 0x228 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL05 A/D2 Conversion Channel 05 Selection Register 0x22A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL06 A/D2 Conversion Channel 06 Selection Register 0x22C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL07 A/D2 Conversion Channel 07 Selection Register 0x22E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL08 A/D2 Conversion Channel 08 Selection Register 0x230 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL09 A/D2 Conversion Channel 09 Selection Register 0x232 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL10 A/D2 Conversion Channel 10 Selection Register 0x234 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL11 A/D2 Conversion Channel 11 Selection Register 0x236 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL12 A/D2 Conversion Channel 12 Selection Register 0x238 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL13 A/D2 Conversion Channel 13 Selection Register 0x23A 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL14 A/D2 Conversion Channel 14 Selection Register 0x23C 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSEL15 A/D2 Conversion Channel 15 Selection Register 0x23E 16 read-write n ACHSEL Conversion channel select 0 4 read-write ASHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSELB0 A/D2 Conversion Channel B0 Selection Register 0x240 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSELB1 A/D2 Conversion Channel B1 Selection Register 0x242 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSELB2 A/D2 Conversion Channel B2 Selection Register 0x244 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CHSELB3 A/D2 Conversion Channel B3 Selection Register 0x246 16 read-write n BCHSEL Conversion channel select 0 4 read-write BSHC Sampling/Hold cycles 8 14 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 14 16 read ADC2CTR0 A/D2 Co2versio2 Co2trol Register 0 0x200 16 read-write n CK ADCK select 1 4 read-write ON A/Dn operation mode 0 1 read-write __reserve0 0 is always read out. 4 16 read ADC2CTR1A A/D2 Co2versio2 Co2trol Register 1A 0x204 16 read-write n AECH Conversion end channel setting 4 8 read-write AEN A/D conversion start 0 1 read-write AMD A/D conversion mode select 2 3 read-write ATRG A/D conversion start by using trigger A 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read ADC2CTR1B A/D2 Co2versio2 Co2trol Register 1B 0x208 16 read-write n BECH Conversion end channel setting 4 6 read-write BEN A/D conversion start 0 1 read-write BMD A/D conversion mode select 2 3 read-write BTRG A/D conversion start by using trigger B 1 2 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 6 16 read ADC2CTREGA A/D2 Co2versio2 Start Trigger A Cou2t Register 0x214 8 read-write n ACNT The number for reducing start trigger A (at the second or later A/D conversion) 0 4 read-write ACNTI The number for reducing start trigger A (at the first A/D conversion) 4 8 read-write ADC2CTREGB A/D2 Co2versio2 Start Trigger B Cou2t Register 0x218 8 read-write n BCNT The number for reducing start trigger B (at the second or later A/D conversion) 0 4 read-write BCNTI The number for reducing start trigger B (at the first A/D conversion) 4 8 read-write ADC2ERCA A/D2 Co2versio2 Error Detectio2 Cha22el Setti2g Register A 0x248 16 read-write n ERCACH0 Error detection setting (the channel selected by setting ANnCHSEL00). 0 1 read-write ERCACH1 Error detection setting (the channel selected by setting ANnCHSEL01). 1 2 read-write ERCACH10 Error detection setting (the channel selected by setting ANnCHSEL10). 10 11 read-write ERCACH11 Error detection setting (the channel selected by setting ANnCHSEL11). 11 12 read-write ERCACH12 Error detection setting (the channel selected by setting ANnCHSEL12). 12 13 read-write ERCACH13 Error detection setting (the channel selected by setting ANnCHSEL13). 13 14 read-write ERCACH14 Error detection setting (the channel selected by setting ANnCHSEL14). 14 15 read-write ERCACH15 Error detection setting (the channel selected by setting ANnCHSEL15). 15 16 read-write ERCACH2 Error detection setting (the channel selected by setting ANnCHSEL02). 2 3 read-write ERCACH3 Error detection setting (the channel selected by setting ANnCHSEL03). 3 4 read-write ERCACH4 Error detection setting (the channel selected by setting ANnCHSEL04). 4 5 read-write ERCACH5 Error detection setting (the channel selected by setting ANnCHSEL05). 5 6 read-write ERCACH6 Error detection setting (the channel selected by setting ANnCHSEL06). 6 7 read-write ERCACH7 Error detection setting (the channel selected by setting ANnCHSEL07). 7 8 read-write ERCACH8 Error detection setting (the channel selected by setting ANnCHSEL08). 8 9 read-write ERCACH9 Error detection setting (the channel selected by setting ANnCHSEL09). 9 10 read-write ADC2ERCB A/D2 Co2versio2 Error Detectio2 Cha22el Setti2g Register B 0x24C 16 read-write n ERCBCH0 Error detection setting (the channel selected by setting ANnCHSELB0). 0 1 read-write ERCBCH1 Error detection setting (the channel selected by setting ANnCHSELB1). 1 2 read-write ERCBCH2 Error detection setting (the channel selected by setting ANnCHSELB2). 2 3 read-write ERCBCH3 Error detection setting (the channel selected by setting ANnCHSELB3). 3 4 read-write __reserve0 0 is always read out. 4 16 read ADC2LOWA A/D2 Co2versio2 Error Detectio2 Lower Limit Setti2g Register A 0x250 16 read-write n LOWA Set the lower limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC2LOWB A/D2 Co2versio2 Error Detectio2 Lower Limit Setti2g Register B 0x258 16 read-write n LOWB Set the lower limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC2ST A/D2 Co2versio2 Start Trigger Selectio2 Register 0x210 16 read-write n AST Start trigger A for A/Dn conversion 0 5 read-write BST Start trigger B for A/Dn conversion 8 13 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 13 16 read ADC2UPA A/D2 Co2versio2 Error Detectio2 Upper Limit Setti2g Register A 0x254 16 read-write n UPA Set the upper limit of A/Dn conversion result (trigger A) 0 12 read-write __reserve0 0 is always read out. 12 16 read ADC2UPB A/D2 Co2versio2 Error Detectio2 Upper Limit Setti2g Register B 0x25C 16 read-write n UPB Set the upper limit of A/Dn conversion result (trigger B) 0 12 read-write __reserve0 0 is always read out. 12 16 read CAN CAN FD Cotroller CAN 0x0 0x0 0x960 registers n G136 136 G137 137 G138 138 G139 139 G140 140 CAN0_CCCR CAN0 CC Co0trol Register 0x18 32 read-write n ASM Restricted Operation Mode (*2) 2 3 read-write BRSE Bit Rate Switch Enable (*1) 9 10 read-write CCE Configuration Change Enable (*1)(*4) 1 2 read-write CSA Clock Stop Acknowledge 3 4 read CSR Clock Stop Request (*3) 4 5 read-write DAR Disable Automatic Retransmission (*1) 6 7 read-write EFBI Edge Filtering during Bus Integration (*1) 13 14 read-write FDOE CAN FD Operation Enable (*1) 8 9 read-write INIT Initialization (*5) 0 1 read-write MON Bus Monitoring Mode (*2) 5 6 read-write NISO Non ISO Operation (*1) 15 16 read-write PXHD Protocol Exception Handling Disable (*1) 12 13 read-write TEST Test Mode Enable (*2) 7 8 read-write TXP Transmit Pause 14 15 read-write __reserve0 0 is always read out. 10 12 read __reserve1 0 is always read out. 16 32 read CAN0_CREL CAN0 Core Release Register 0x0 32 read-write n DAY Time Stamp Day 0 8 read MON Time Stamp Month 8 16 read REL Core Release Version 28 32 read STEP Step of Core Release 24 28 read SUBSTEP Sub-step of Core Release 20 24 read YEAR Time Stamp Year 16 20 read CAN0_DBTP CAN0 Data Bit Timi0g and Prescaler Register 0xC 32 read-write n DBRP Data Bit Rate Prescaler (*1) 16 21 read-write DSJW Data (Re)Synchronization Jump Width 0 4 read-write DTSEG1 Data time segment before sample point 8 13 read-write DTSEG2 Data time segment after sample point 4 8 read-write TDC Transmitter Delay Compensation 23 24 read-write __reserve0 0 is always read out. 13 16 read __reserve1 0 is always read out. 21 23 read __reserve2 0 is always read out. 24 32 read CAN0_ECR CAN0 Error Cou0ter Register 0x40 32 read-write n CEL CAN Error Logging (*1) 16 24 read REC Receive Error Counter 8 15 read RP Receive Error Passive 15 16 read TEC Transmit Error Counter 0 8 read __reserve0 0 is always read out. 24 32 read CAN0_GFC CAN0 Global Filter Co0figuratio0 Register 0x80 32 read-write n ANFE Accept Non-matching Frames Extended Message ID (29-bit) 2 4 read-write ANFS Accept Non-matching Frames Standard Message ID (11-bit) 4 6 read-write RRFE Reject Remote Frames Extended Message ID (29-bit) 0 1 read-write RRFS Reject Remote Frames Standard Message ID (11-bit) 1 2 read-write __reserve0 0 is always read out. 6 32 read CAN0_HPMS CAN0 High Priority Message Status Register 0x94 32 read-write n BIDX Buffer Index 0 6 read FIDX Filter Index 8 15 read FLST Filter List 15 16 read MSI Message Storage Indicator 6 8 read __reserve0 0 is always read out. 16 32 read CAN0_IE CAN0 I0terrupt Factor E0able Register 0x54 32 read-write n ARAE Access to Reserved Address Interrupt Factor Enable 29 30 read-write BECE Bit Error Corrected Interrupt Factor Enable 20 21 read-write BEUE Bit Error Uncorrected Interrupt Factor Enable 21 22 read-write BOE Bus_Off Status Interrupt Factor Enable 25 26 read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Factor Enable 19 20 read-write ELOE Error Logging Overflow Interrupt Factor Enable 22 23 read-write EPE Error Passive Interrupt Factor Enable 23 24 read-write EWE Warning Status Interrupt Factor Enable 24 25 read-write HPME High Priority Message Interrupt Factor Enable 8 9 read-write MRAFE Message RAM Access Failure Interrupt Factor Enable 17 18 read-write PEAE Protocol Error in Arbitration Phase Interrupt Factor Enable 27 28 read-write PEDE Protocol Error in Data Phase Interrupt Factor Enable 28 29 read-write RF0FE Rx FIFO 0 Full Interrupt Factor Enable 2 3 read-write RF0LE Rx FIFO 0 Message Lost Interrupt Factor Enable 3 4 read-write RF0NE Rx FIFO 0 New Message Interrupt Factor Enable 0 1 read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Factor Enable 1 2 read-write RF1FE Rx FIFO 1 Full Interrupt Factor Enable 6 7 read-write RF1LE Rx FIFO 1 Message Lost Interrupt Factor Enable 7 8 read-write RF1NE Rx FIFO 1 New Message Interrupt Factor Enable 4 5 read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Factor Enable 5 6 read-write TCE Transmission Completed Interrupt Factor Enable 9 10 read-write TCFE Transmission Cancellation Finished Interrupt Factor Enable 10 11 read-write TEFFE Tx Event FIFO Full Interrupt Factor Enable 14 15 read-write TEFLE Tx Event FIFO Event Lost Interrupt Factor Enable 15 16 read-write TEFNE Tx Event FIFO New Entry Interrupt Factor Enable 12 13 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Factor Enable 13 14 read-write TFEE Tx FIFO Empty Interrupt Factor Enable 11 12 read-write TOOE Timeout Occurred Interrupt Factor Enable 18 19 read-write TSWE Timestamp Wraparound Interrupt Factor Enable 16 17 read-write WDIE Watchdog Interrupt Factor Enable 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN0_ILE CAN0 I0terrupt Li0e E0able Register 0x5C 32 read-write n EINT0 Enable CANn-0 Interrupt 0 1 read-write EINT1 Enable CANn-1 Interrupt 1 2 read-write __reserve0 0 is always read out. 2 32 read CAN0_ILS CAN0 I0terrupt Li0e Select Register 0x58 32 read-write n ARAL Access to Reserved Address Line 29 30 read-write BECL Bit Error Corrected Interrupt Line 20 21 read-write BEUL Bit Error Uncorrected Interrupt Line 21 22 read-write BOL Bus_Off Status Interrupt Line 25 26 read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 20 read-write ELOL Error Logging Overflow Interrupt Line 22 23 read-write EPL Error Passive Interrupt Line 23 24 read-write EWL Warning Status Interrupt Line 24 25 read-write HPML High Priority Message Interrupt Line 8 9 read-write MRAFL Message RAM Access Failure Interrupt Line 17 18 read-write PEAL Protocol Error in Arbitration Phase Line 27 28 read-write PEDL Protocol Error in Data Phase Line 28 29 read-write RF0FL Rx FIFO 0 Full Interrupt Line 2 3 read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 4 read-write RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 2 read-write RF1FL Rx FIFO 1 Full Interrupt Line 6 7 read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 8 read-write RF1NL Rx FIFO 1 New Message Interrupt Line 4 5 read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 6 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 11 read-write TCL Transmission Completed Interrupt Line 9 10 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 15 read-write TEFLL Tx Event FIFO Event Lost Interrupt Line 15 16 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 13 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 14 read-write TFEL Tx FIFO Empty Interrupt Line 11 12 read-write TOOL Timeout Occurred Interrupt Line 18 19 read-write TSWL Timestamp Wraparound Interrupt Line 16 17 read-write WDIL Watchdog Interrupt Line 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN0_IR CAN0 I0terrupt Factor Register 0x50 32 read-write n ARA Access to Reserved Address Interrupt factor 29 30 read-write BEC Bit Error Corrected Interrupt factor 20 21 read-write BEU Bit Error Uncorrected Interrupt factor 21 22 read-write BO Bus_Off Status Interrupt factor 25 26 read-write DRX Message stored to Dedicated Rx Buffer Interrupt factor 19 20 read-write ELO Error Logging Overflow Interrupt factor 22 23 read-write EP Error Passive Interrupt factor 23 24 read-write EW Warning Status Interrupt factor 24 25 read-write HPM High Priority Message Interrupt factor 8 9 read-write MRAF Message RAM Access Failure Interrupt factor 17 18 read-write PEA Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used) 27 28 read-write PED Protocol Error in Data Phase Interrupt factor (Data Bit Time is used) 28 29 read-write RF0F Rx FIFO 0 Full Interrupt factor 2 3 read-write RF0L Rx FIFO 0 Message Lost Interrupt factor 3 4 read-write RF0N Rx FIFO 0 New Message Interrupt factor 0 1 read-write RF0W Rx FIFO 0 Watermark Reached Interrupt factor 1 2 read-write RF1F Rx FIFO 1 Full Interrupt factor 6 7 read-write RF1L Rx FIFO 1 Message Lost Interrupt factor 7 8 read-write RF1N Rx FIFO 1 New Message Interrupt factor 4 5 read-write RF1W Rx FIFO 1 Watermark Reached Interrupt factor 5 6 read-write TC Transmission Completed Interrupt factor 9 10 read-write TCF Transmission Cancellation Finished Interrupt factor 10 11 read-write TEFF Tx Event FIFO Full Interrupt factor 14 15 read-write TEFL Tx Event FIFO Element Lost Interrupt factor 15 16 read-write TEFN Tx Event FIFO New Entry Interrupt factor 12 13 read-write TEFW Tx Event FIFO Watermark Reached Interrupt factor 13 14 read-write TFE Tx FIFO Empty Interrupt factor 11 12 read-write TOO Timeout Occurred Interrupt factor 18 19 read-write TSW Timestamp Wraparound Interrupt factor 16 17 read-write WDI Watchdog Interrupt factor 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN0_NBTP CAN0 Nomi0al Bit Timi0g and Prescaler Register 0x1C 32 read-write n NBRP Nominal Bit Rate Prescaler 16 25 read-write NSJW Nominal (Re)Synchronization Jump Width 25 32 read-write NTSEG1 Nominal Time segment (TSEG1) before sample point 8 16 read-write NTSEG2 Nominal Time segment (TSEG2) after sample point 0 7 read-write __reserve0 0 is always read out. 7 8 read CAN0_NDAT1 CAN0 New Data 1 Register 0x98 32 read-write n ND1 New Data flags of Rx Buffers 0 to 31 (bp0 to 31) 0 32 read-write CAN0_NDAT2 CAN0 New Data 2 Register 0x9C 32 read-write n ND2 New Data flags of Rx Buffers 32 to 63 (bp0 to 31) 0 32 read-write CAN0_PSR CAN0 Protocol Status Register 0x44 32 read-write n ACT Activity 3 5 read BO Bus_Off Status 7 8 read DLEC Data Phase Last Error Code 8 11 read EP CANn Error Passive 5 6 read EW Warning Status 6 7 read LEC Last error code to occur on the CAN bus.(*4)(*5) 0 3 read PXE Protocol Exception Event (*1) 14 15 read RBRS BRS flag of last received CAN FD Message (*1) 12 13 read RESI ESI flag of last received CAN FD Message (*1) 11 12 read RFDF Received a CAN FD Message (*1) 13 14 read TDCV Transmitter Delay Compensation Value (Position of the secondary sample point) 16 23 read __reserve0 0 is always read out. 15 16 read __reserve1 0 is always read out. 23 32 read CAN0_RWD CAN0 RAM Watchdog Register 0x14 32 read-write n WDC Watchdog Configuration 0 8 read-write WDV Watchdog Value 8 16 read __reserve0 0 is always read out. 16 32 read CAN0_RXBC CAN0 Rx Buffer Co0figuratio0 Register 0xAC 32 read-write n RBSA Start address of Rx Buffers in Message RAM (*1)(*2) 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN0_RXESC CAN0 Rx Buffer/ FIFO Eleme0t Size Co0figuratio0 Register 0xBC 32 read-write n F0DS Rx FIFO 0 Data Field Size (*1) 0 3 read-write F1DS Rx FIFO 1 Data Field Size (*1) 4 7 read-write RBDS Rx Buffer Data Field Size (*1) 8 11 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read __reserve2 0 is always read out. 11 32 read CAN0_RXF0A CAN0 Rx FIFO 0 Ack0owledge Register 0xA8 32 read-write n F0AI Rx FIFO 0 Acknowledge Index (*1) 0 6 read-write __reserve0 0 is always read out. 6 32 read CAN0_RXF0C CAN0 Rx FIFO 0 Co0figuratio0 Register 0xA0 32 read-write n F0OM FIFO 0 Operation Mode 31 32 read-write F0S Rx FIFO 0 Size 16 23 read-write F0SA Start address of Rx FIFO 0 in Message RAM (*1) 0 16 read-write F0WM Rx FIFO 0 Watermark 24 31 read-write __reserve0 0 is always read out. 23 24 read CAN0_RXF0S CAN0 Rx FIFO 0 Status Register 0xA4 32 read-write n F0F Rx FIFO 0 Full 24 25 read F0FL Rx FIFO 0 Fill Level 0 7 read F0GI Rx FIFO 0 Get Index 8 14 read F0PI Rx FIFO 0 Put Index 16 22 read RF0L Rx FIFO 0 Message Lost (*1)(*2) 25 26 read __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 14 16 read __reserve2 0 is always read out. 22 24 read __reserve3 0 is always read out. 26 32 read CAN0_RXF1A CAN0 Rx FIFO 1 Ack0owledge Register 0xB8 32 read-write n F1AI Rx FIFO 1 Acknowledge Index 0 6 read-write __reserve0 0 is always read out. 6 32 read CAN0_RXF1C CAN0 Rx FIFO 1 Co0figuratio0 Register 0xB0 32 read-write n F1OM Rx FIFO 1 Operation Mode 31 32 read-write F1S Rx FIFO 1 Size 16 23 read-write F1SA Start address of Rx FIFO 1 in Message RAM (*1) 0 16 read-write F1WM Rx FIFO 1 Watermark 24 31 read-write __reserve0 0 is always read out. 23 24 read CAN0_RXF1S CAN0 Rx FIFO 1 Status Register 0xB4 32 read-write n DMS Debug Message Status 30 32 read F1F Rx FIFO 1 Full 24 25 read F1FL Rx FIFO 1 Fill Level 0 7 read F1GI Rx FIFO 1 Get Index 8 14 read F1PI Rx FIFO 1 Put Index 16 22 read RF1L Rx FIFO 1 Message Lost (*1)(*2) 25 26 read __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 14 16 read __reserve2 0 is always read out. 22 24 read __reserve3 0 is always read out. 26 30 read CAN0_SIDFC CAN0 Sta0dard ID Filter Co0figuratio0 Register 0x84 32 read-write n FLSSA Start address of Standard Message ID (11-bit) filter list (*1) 0 16 read-write LSS List Size Standard Message ID (11-bit) 16 24 read-write __reserve0 0 is always read out. 24 32 read CAN0_TDCR CAN0 Tra0smitter Delay Compe0satio0 Register 0x48 32 read-write n TDCF Transmitter Delay Compensation Filter Window Length (*1) 0 7 read-write TDCO Transmitter Delay Compensation Offset 8 15 read-write __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 15 32 read CAN0_TEST CAN0 Test Register 0x10 32 read-write n LBCK Loop Back Mode 4 5 read-write RX Monitors the actual value of CRX pin 7 8 read TX Control of Transmit Pin CTX (*1) 5 7 read-write __reserve0 0 is always read out. 0 4 read __reserve1 0 is always read out. 8 32 read CAN0_TOCC CAN0 Timeout Cou0ter Co0figuratio0 Register 0x28 32 read-write n ETOC Enable Timeout Counter 0 1 read-write TOP Start value of the Timeout Counter (down-counter). Configures the Timeout Period. 16 32 read-write TOS Timeout Counter Operation mode Selection 1 3 read-write __reserve0 0 is always read out. 3 16 read CAN0_TOCV CAN0 Timeout Cou0ter Value Register 0x2C 32 read-write n TOC Timeout Counter Value 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN0_TSCC CAN0 Timestamp Cou0ter Co0figuratio0 Register 0x20 32 read-write n TCP Timestamp Counter Prescaler 16 20 read-write TSS Timestamp Selection 0 2 read-write __reserve0 0 is always read out. 2 16 read __reserve1 0 is always read out. 20 32 read CAN0_TSCV CAN0 Timestamp Cou0ter Value Register 0x24 32 read-write n TSC Timestamp Counter 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN0_TXBAR CAN0 Tx Buffer Add Request Register 0xD0 32 read-write n AR Add Request 0 32 read-write CAN0_TXBC CAN0 Tx Buffer Co0figuratio0 Register 0xC0 32 read-write n NDTB Number of Dedicated Tx Buffers (*1) 16 22 read-write TBSA Start address of Tx Buffers in Message RAM (*2)(*3) 0 16 read-write TFQM Tx FIFO/Queue Mode 30 31 read-write TFQS Tx FIFO/Queue Size (*1) 24 30 read-write __reserve0 0 is always read out. 22 24 read __reserve1 0 is always read out. 31 32 read CAN0_TXBCF CAN0 Tx Buffer Ca0cellatio0 Fi0ished Register 0xDC 32 read-write n CF Transmit Buffer Cancellation Finished 0 32 read CAN0_TXBCIE CAN0 Tx Buffer Ca0cellatio0 Fi0ished I0terrupt E0able Register 0xE4 32 read-write n CFIE Tx Buffer Cancellation Finished Interrupt Enable 0 32 read-write CAN0_TXBCR CAN0 Tx Buffer Ca0cellatio0 Request Register 0xD4 32 read-write n CR Cancellation Request 0 32 read-write CAN0_TXBRP CAN0 Tx Buffer Request Pe0di0g Register 0xCC 32 read-write n TRP Transmission Request Pending 0 32 read CAN0_TXBTIE CAN0 Tx Buffer Tra0smissio0 I0terrupt E0able Register 0xE0 32 read-write n TIE Tx Buffer Transmission Interrupt Enable 0 32 read-write CAN0_TXBTO CAN0 Tx Buffer Tra0smissio0 Occurred Register 0xD8 32 read-write n TO Transmission Occurred 0 32 read CAN0_TXEFA CAN0 Tx Eve0t FIFO Ack0owledge Register 0xF8 32 read-write n EFAI Event FIFO Acknowledge Index 0 5 read-write __reserve0 0 is always read out. 5 32 read CAN0_TXEFC CAN0 Tx Eve0t FIFO Co0figuratio0 Register 0xF0 32 read-write n EFS Event FIFO Size 16 22 read-write EFSA Start address of Tx Event FIFO in Message RAM (*1) 0 16 read-write EFWM Event FIFO Watermark 24 30 read-write __reserve0 0 is always read out. 22 24 read __reserve1 0 is always read out. 30 32 read CAN0_TXEFS CAN0 Tx Eve0t FIFO Status Register 0xF4 32 read-write n EFF Event FIFO Full 24 25 read EFFL Event FIFO Fill Level 0 6 read EFGI Event FIFO Get Index 8 13 read EFPI Event FIFO Put Index 16 21 read TEFL Tx Event FIFO Element Lost (*1) 25 26 read __reserve0 0 is always read out. 6 8 read __reserve1 0 is always read out. 13 16 read __reserve2 0 is always read out. 21 24 read __reserve3 0 is always read out. 26 32 read CAN0_TXESC CAN0 Tx Buffer Eleme0t Size Co0figuratio0 Register 0xC8 32 read-write n TBDS Tx Buffer Data Field Size (*1) 0 3 read-write __reserve0 0 is always read out. 3 32 read CAN0_TXFQS CAN0 Tx FIFO/Queue Status Register 0xC4 32 read-write n TFFL Tx FIFO Free Level 0 6 read TFGI Tx FIFO Get Index (*1) 8 13 read TFQF Tx FIFO/Queue Full 21 22 read TFQPI Tx FIFO/Queue Put Index 16 21 read __reserve0 0 is always read out. 6 8 read __reserve1 0 is always read out. 13 16 read __reserve2 0 is always read out. 22 32 read CAN0_XIDAM CAN0 Exte0ded ID AND Mask Register 0x90 32 read-write n EIDM Extended Message ID Mask (*1) 0 29 read-write __reserve0 0 is always read out. 29 32 read CAN0_XIDFC CAN0 Exte0ded ID Filter Co0figuratio0 Register 0x88 32 read-write n FLESA Start address of Extended Message ID (29-bit) filter list (*1) 0 16 read-write LSE List Size Extended Message ID (29-bit) 16 23 read-write __reserve0 0 is always read out. 23 32 read CAN1_CCCR CAN1 CC Co1trol Register 0x218 32 read-write n ASM Restricted Operation Mode (*2) 2 3 read-write BRSE Bit Rate Switch Enable (*1) 9 10 read-write CCE Configuration Change Enable (*1)(*4) 1 2 read-write CSA Clock Stop Acknowledge 3 4 read CSR Clock Stop Request (*3) 4 5 read-write DAR Disable Automatic Retransmission (*1) 6 7 read-write EFBI Edge Filtering during Bus Integration (*1) 13 14 read-write FDOE CAN FD Operation Enable (*1) 8 9 read-write INIT Initialization (*5) 0 1 read-write MON Bus Monitoring Mode (*2) 5 6 read-write NISO Non ISO Operation (*1) 15 16 read-write PXHD Protocol Exception Handling Disable (*1) 12 13 read-write TEST Test Mode Enable (*2) 7 8 read-write TXP Transmit Pause 14 15 read-write __reserve0 0 is always read out. 10 12 read __reserve1 0 is always read out. 16 32 read CAN1_CREL CAN1 Core Release Register 0x200 32 read-write n DAY Time Stamp Day 0 8 read MON Time Stamp Month 8 16 read REL Core Release Version 28 32 read STEP Step of Core Release 24 28 read SUBSTEP Sub-step of Core Release 20 24 read YEAR Time Stamp Year 16 20 read CAN1_DBTP CAN1 Data Bit Timi1g and Prescaler Register 0x20C 32 read-write n DBRP Data Bit Rate Prescaler (*1) 16 21 read-write DSJW Data (Re)Synchronization Jump Width 0 4 read-write DTSEG1 Data time segment before sample point 8 13 read-write DTSEG2 Data time segment after sample point 4 8 read-write TDC Transmitter Delay Compensation 23 24 read-write __reserve0 0 is always read out. 13 16 read __reserve1 0 is always read out. 21 23 read __reserve2 0 is always read out. 24 32 read CAN1_ECR CAN1 Error Cou1ter Register 0x240 32 read-write n CEL CAN Error Logging (*1) 16 24 read REC Receive Error Counter 8 15 read RP Receive Error Passive 15 16 read TEC Transmit Error Counter 0 8 read __reserve0 0 is always read out. 24 32 read CAN1_GFC CAN1 Global Filter Co1figuratio1 Register 0x280 32 read-write n ANFE Accept Non-matching Frames Extended Message ID (29-bit) 2 4 read-write ANFS Accept Non-matching Frames Standard Message ID (11-bit) 4 6 read-write RRFE Reject Remote Frames Extended Message ID (29-bit) 0 1 read-write RRFS Reject Remote Frames Standard Message ID (11-bit) 1 2 read-write __reserve0 0 is always read out. 6 32 read CAN1_HPMS CAN1 High Priority Message Status Register 0x294 32 read-write n BIDX Buffer Index 0 6 read FIDX Filter Index 8 15 read FLST Filter List 15 16 read MSI Message Storage Indicator 6 8 read __reserve0 0 is always read out. 16 32 read CAN1_IE CAN1 I1terrupt Factor E1able Register 0x254 32 read-write n ARAE Access to Reserved Address Interrupt Factor Enable 29 30 read-write BECE Bit Error Corrected Interrupt Factor Enable 20 21 read-write BEUE Bit Error Uncorrected Interrupt Factor Enable 21 22 read-write BOE Bus_Off Status Interrupt Factor Enable 25 26 read-write DRXE Message stored to Dedicated Rx Buffer Interrupt Factor Enable 19 20 read-write ELOE Error Logging Overflow Interrupt Factor Enable 22 23 read-write EPE Error Passive Interrupt Factor Enable 23 24 read-write EWE Warning Status Interrupt Factor Enable 24 25 read-write HPME High Priority Message Interrupt Factor Enable 8 9 read-write MRAFE Message RAM Access Failure Interrupt Factor Enable 17 18 read-write PEAE Protocol Error in Arbitration Phase Interrupt Factor Enable 27 28 read-write PEDE Protocol Error in Data Phase Interrupt Factor Enable 28 29 read-write RF0FE Rx FIFO 0 Full Interrupt Factor Enable 2 3 read-write RF0LE Rx FIFO 0 Message Lost Interrupt Factor Enable 3 4 read-write RF0NE Rx FIFO 0 New Message Interrupt Factor Enable 0 1 read-write RF0WE Rx FIFO 0 Watermark Reached Interrupt Factor Enable 1 2 read-write RF1FE Rx FIFO 1 Full Interrupt Factor Enable 6 7 read-write RF1LE Rx FIFO 1 Message Lost Interrupt Factor Enable 7 8 read-write RF1NE Rx FIFO 1 New Message Interrupt Factor Enable 4 5 read-write RF1WE Rx FIFO 1 Watermark Reached Interrupt Factor Enable 5 6 read-write TCE Transmission Completed Interrupt Factor Enable 9 10 read-write TCFE Transmission Cancellation Finished Interrupt Factor Enable 10 11 read-write TEFFE Tx Event FIFO Full Interrupt Factor Enable 14 15 read-write TEFLE Tx Event FIFO Event Lost Interrupt Factor Enable 15 16 read-write TEFNE Tx Event FIFO New Entry Interrupt Factor Enable 12 13 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Factor Enable 13 14 read-write TFEE Tx FIFO Empty Interrupt Factor Enable 11 12 read-write TOOE Timeout Occurred Interrupt Factor Enable 18 19 read-write TSWE Timestamp Wraparound Interrupt Factor Enable 16 17 read-write WDIE Watchdog Interrupt Factor Enable 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN1_ILE CAN1 I1terrupt Li1e E1able Register 0x25C 32 read-write n EINT0 Enable CANn-0 Interrupt 0 1 read-write EINT1 Enable CANn-1 Interrupt 1 2 read-write __reserve0 0 is always read out. 2 32 read CAN1_ILS CAN1 I1terrupt Li1e Select Register 0x258 32 read-write n ARAL Access to Reserved Address Line 29 30 read-write BECL Bit Error Corrected Interrupt Line 20 21 read-write BEUL Bit Error Uncorrected Interrupt Line 21 22 read-write BOL Bus_Off Status Interrupt Line 25 26 read-write DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 20 read-write ELOL Error Logging Overflow Interrupt Line 22 23 read-write EPL Error Passive Interrupt Line 23 24 read-write EWL Warning Status Interrupt Line 24 25 read-write HPML High Priority Message Interrupt Line 8 9 read-write MRAFL Message RAM Access Failure Interrupt Line 17 18 read-write PEAL Protocol Error in Arbitration Phase Line 27 28 read-write PEDL Protocol Error in Data Phase Line 28 29 read-write RF0FL Rx FIFO 0 Full Interrupt Line 2 3 read-write RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 4 read-write RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 read-write RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 2 read-write RF1FL Rx FIFO 1 Full Interrupt Line 6 7 read-write RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 8 read-write RF1NL Rx FIFO 1 New Message Interrupt Line 4 5 read-write RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 6 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 11 read-write TCL Transmission Completed Interrupt Line 9 10 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 15 read-write TEFLL Tx Event FIFO Event Lost Interrupt Line 15 16 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 13 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 14 read-write TFEL Tx FIFO Empty Interrupt Line 11 12 read-write TOOL Timeout Occurred Interrupt Line 18 19 read-write TSWL Timestamp Wraparound Interrupt Line 16 17 read-write WDIL Watchdog Interrupt Line 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN1_IR CAN1 I1terrupt Factor Register 0x250 32 read-write n ARA Access to Reserved Address Interrupt factor 29 30 read-write BEC Bit Error Corrected Interrupt factor 20 21 read-write BEU Bit Error Uncorrected Interrupt factor 21 22 read-write BO Bus_Off Status Interrupt factor 25 26 read-write DRX Message stored to Dedicated Rx Buffer Interrupt factor 19 20 read-write ELO Error Logging Overflow Interrupt factor 22 23 read-write EP Error Passive Interrupt factor 23 24 read-write EW Warning Status Interrupt factor 24 25 read-write HPM High Priority Message Interrupt factor 8 9 read-write MRAF Message RAM Access Failure Interrupt factor 17 18 read-write PEA Protocol Error in Arbitration Phase Interrupt factor (Nominal Bit Time is used) 27 28 read-write PED Protocol Error in Data Phase Interrupt factor (Data Bit Time is used) 28 29 read-write RF0F Rx FIFO 0 Full Interrupt factor 2 3 read-write RF0L Rx FIFO 0 Message Lost Interrupt factor 3 4 read-write RF0N Rx FIFO 0 New Message Interrupt factor 0 1 read-write RF0W Rx FIFO 0 Watermark Reached Interrupt factor 1 2 read-write RF1F Rx FIFO 1 Full Interrupt factor 6 7 read-write RF1L Rx FIFO 1 Message Lost Interrupt factor 7 8 read-write RF1N Rx FIFO 1 New Message Interrupt factor 4 5 read-write RF1W Rx FIFO 1 Watermark Reached Interrupt factor 5 6 read-write TC Transmission Completed Interrupt factor 9 10 read-write TCF Transmission Cancellation Finished Interrupt factor 10 11 read-write TEFF Tx Event FIFO Full Interrupt factor 14 15 read-write TEFL Tx Event FIFO Element Lost Interrupt factor 15 16 read-write TEFN Tx Event FIFO New Entry Interrupt factor 12 13 read-write TEFW Tx Event FIFO Watermark Reached Interrupt factor 13 14 read-write TFE Tx FIFO Empty Interrupt factor 11 12 read-write TOO Timeout Occurred Interrupt factor 18 19 read-write TSW Timestamp Wraparound Interrupt factor 16 17 read-write WDI Watchdog Interrupt factor 26 27 read-write __reserve0 0 is always read out. 30 32 read CAN1_NBTP CAN1 Nomi1al Bit Timi1g and Prescaler Register 0x21C 32 read-write n NBRP Nominal Bit Rate Prescaler 16 25 read-write NSJW Nominal (Re)Synchronization Jump Width 25 32 read-write NTSEG1 Nominal Time segment (TSEG1) before sample point 8 16 read-write NTSEG2 Nominal Time segment (TSEG2) after sample point 0 7 read-write __reserve0 0 is always read out. 7 8 read CAN1_NDAT1 CAN1 New Data 1 Register 0x298 32 read-write n ND1 New Data flags of Rx Buffers 0 to 31 (bp0 to 31) 0 32 read-write CAN1_NDAT2 CAN1 New Data 2 Register 0x29C 32 read-write n ND2 New Data flags of Rx Buffers 32 to 63 (bp0 to 31) 0 32 read-write CAN1_PSR CAN1 Protocol Status Register 0x244 32 read-write n ACT Activity 3 5 read BO Bus_Off Status 7 8 read DLEC Data Phase Last Error Code 8 11 read EP CANn Error Passive 5 6 read EW Warning Status 6 7 read LEC Last error code to occur on the CAN bus.(*4)(*5) 0 3 read PXE Protocol Exception Event (*1) 14 15 read RBRS BRS flag of last received CAN FD Message (*1) 12 13 read RESI ESI flag of last received CAN FD Message (*1) 11 12 read RFDF Received a CAN FD Message (*1) 13 14 read TDCV Transmitter Delay Compensation Value (Position of the secondary sample point) 16 23 read __reserve0 0 is always read out. 15 16 read __reserve1 0 is always read out. 23 32 read CAN1_RWD CAN1 RAM Watchdog Register 0x214 32 read-write n WDC Watchdog Configuration 0 8 read-write WDV Watchdog Value 8 16 read __reserve0 0 is always read out. 16 32 read CAN1_RXBC CAN1 Rx Buffer Co1figuratio1 Register 0x2AC 32 read-write n RBSA Start address of Rx Buffers in Message RAM (*1)(*2) 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN1_RXESC CAN1 Rx Buffer/ FIFO Eleme1t Size Co1figuratio1 Register 0x2BC 32 read-write n F0DS Rx FIFO 0 Data Field Size (*1) 0 3 read-write F1DS Rx FIFO 1 Data Field Size (*1) 4 7 read-write RBDS Rx Buffer Data Field Size (*1) 8 11 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read __reserve2 0 is always read out. 11 32 read CAN1_RXF0A CAN1 Rx FIFO 0 Ack1owledge Register 0x2A8 32 read-write n F0AI Rx FIFO 0 Acknowledge Index (*1) 0 6 read-write __reserve0 0 is always read out. 6 32 read CAN1_RXF0C CAN1 Rx FIFO 0 Co1figuratio1 Register 0x2A0 32 read-write n F0OM FIFO 0 Operation Mode 31 32 read-write F0S Rx FIFO 0 Size 16 23 read-write F0SA Start address of Rx FIFO 0 in Message RAM (*1) 0 16 read-write F0WM Rx FIFO 0 Watermark 24 31 read-write __reserve0 0 is always read out. 23 24 read CAN1_RXF0S CAN1 Rx FIFO 0 Status Register 0x2A4 32 read-write n F0F Rx FIFO 0 Full 24 25 read F0FL Rx FIFO 0 Fill Level 0 7 read F0GI Rx FIFO 0 Get Index 8 14 read F0PI Rx FIFO 0 Put Index 16 22 read RF0L Rx FIFO 0 Message Lost (*1)(*2) 25 26 read __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 14 16 read __reserve2 0 is always read out. 22 24 read __reserve3 0 is always read out. 26 32 read CAN1_RXF1A CAN1 Rx FIFO 1 Ack1owledge Register 0x2B8 32 read-write n F1AI Rx FIFO 1 Acknowledge Index 0 6 read-write __reserve0 0 is always read out. 6 32 read CAN1_RXF1C CAN1 Rx FIFO 1 Co1figuratio1 Register 0x2B0 32 read-write n F1OM Rx FIFO 1 Operation Mode 31 32 read-write F1S Rx FIFO 1 Size 16 23 read-write F1SA Start address of Rx FIFO 1 in Message RAM (*1) 0 16 read-write F1WM Rx FIFO 1 Watermark 24 31 read-write __reserve0 0 is always read out. 23 24 read CAN1_RXF1S CAN1 Rx FIFO 1 Status Register 0x2B4 32 read-write n DMS Debug Message Status 30 32 read F1F Rx FIFO 1 Full 24 25 read F1FL Rx FIFO 1 Fill Level 0 7 read F1GI Rx FIFO 1 Get Index 8 14 read F1PI Rx FIFO 1 Put Index 16 22 read RF1L Rx FIFO 1 Message Lost (*1)(*2) 25 26 read __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 14 16 read __reserve2 0 is always read out. 22 24 read __reserve3 0 is always read out. 26 30 read CAN1_SIDFC CAN1 Sta1dard ID Filter Co1figuratio1 Register 0x284 32 read-write n FLSSA Start address of Standard Message ID (11-bit) filter list (*1) 0 16 read-write LSS List Size Standard Message ID (11-bit) 16 24 read-write __reserve0 0 is always read out. 24 32 read CAN1_TDCR CAN1 Tra1smitter Delay Compe1satio1 Register 0x248 32 read-write n TDCF Transmitter Delay Compensation Filter Window Length (*1) 0 7 read-write TDCO Transmitter Delay Compensation Offset 8 15 read-write __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 15 32 read CAN1_TEST CAN1 Test Register 0x210 32 read-write n LBCK Loop Back Mode 4 5 read-write RX Monitors the actual value of CRX pin 7 8 read TX Control of Transmit Pin CTX (*1) 5 7 read-write __reserve0 0 is always read out. 0 4 read __reserve1 0 is always read out. 8 32 read CAN1_TOCC CAN1 Timeout Cou1ter Co1figuratio1 Register 0x228 32 read-write n ETOC Enable Timeout Counter 0 1 read-write TOP Start value of the Timeout Counter (down-counter). Configures the Timeout Period. 16 32 read-write TOS Timeout Counter Operation mode Selection 1 3 read-write __reserve0 0 is always read out. 3 16 read CAN1_TOCV CAN1 Timeout Cou1ter Value Register 0x22C 32 read-write n TOC Timeout Counter Value 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN1_TSCC CAN1 Timestamp Cou1ter Co1figuratio1 Register 0x220 32 read-write n TCP Timestamp Counter Prescaler 16 20 read-write TSS Timestamp Selection 0 2 read-write __reserve0 0 is always read out. 2 16 read __reserve1 0 is always read out. 20 32 read CAN1_TSCV CAN1 Timestamp Cou1ter Value Register 0x224 32 read-write n TSC Timestamp Counter 0 16 read-write __reserve0 0 is always read out. 16 32 read CAN1_TXBAR CAN1 Tx Buffer Add Request Register 0x2D0 32 read-write n AR Add Request 0 32 read-write CAN1_TXBC CAN1 Tx Buffer Co1figuratio1 Register 0x2C0 32 read-write n NDTB Number of Dedicated Tx Buffers (*1) 16 22 read-write TBSA Start address of Tx Buffers in Message RAM (*2)(*3) 0 16 read-write TFQM Tx FIFO/Queue Mode 30 31 read-write TFQS Tx FIFO/Queue Size (*1) 24 30 read-write __reserve0 0 is always read out. 22 24 read __reserve1 0 is always read out. 31 32 read CAN1_TXBCF CAN1 Tx Buffer Ca1cellatio1 Fi1ished Register 0x2DC 32 read-write n CF Transmit Buffer Cancellation Finished 0 32 read CAN1_TXBCIE CAN1 Tx Buffer Ca1cellatio1 Fi1ished I1terrupt E1able Register 0x2E4 32 read-write n CFIE Tx Buffer Cancellation Finished Interrupt Enable 0 32 read-write CAN1_TXBCR CAN1 Tx Buffer Ca1cellatio1 Request Register 0x2D4 32 read-write n CR Cancellation Request 0 32 read-write CAN1_TXBRP CAN1 Tx Buffer Request Pe1di1g Register 0x2CC 32 read-write n TRP Transmission Request Pending 0 32 read CAN1_TXBTIE CAN1 Tx Buffer Tra1smissio1 I1terrupt E1able Register 0x2E0 32 read-write n TIE Tx Buffer Transmission Interrupt Enable 0 32 read-write CAN1_TXBTO CAN1 Tx Buffer Tra1smissio1 Occurred Register 0x2D8 32 read-write n TO Transmission Occurred 0 32 read CAN1_TXEFA CAN1 Tx Eve1t FIFO Ack1owledge Register 0x2F8 32 read-write n EFAI Event FIFO Acknowledge Index 0 5 read-write __reserve0 0 is always read out. 5 32 read CAN1_TXEFC CAN1 Tx Eve1t FIFO Co1figuratio1 Register 0x2F0 32 read-write n EFS Event FIFO Size 16 22 read-write EFSA Start address of Tx Event FIFO in Message RAM (*1) 0 16 read-write EFWM Event FIFO Watermark 24 30 read-write __reserve0 0 is always read out. 22 24 read __reserve1 0 is always read out. 30 32 read CAN1_TXEFS CAN1 Tx Eve1t FIFO Status Register 0x2F4 32 read-write n EFF Event FIFO Full 24 25 read EFFL Event FIFO Fill Level 0 6 read EFGI Event FIFO Get Index 8 13 read EFPI Event FIFO Put Index 16 21 read TEFL Tx Event FIFO Element Lost (*1) 25 26 read __reserve0 0 is always read out. 6 8 read __reserve1 0 is always read out. 13 16 read __reserve2 0 is always read out. 21 24 read __reserve3 0 is always read out. 26 32 read CAN1_TXESC CAN1 Tx Buffer Eleme1t Size Co1figuratio1 Register 0x2C8 32 read-write n TBDS Tx Buffer Data Field Size (*1) 0 3 read-write __reserve0 0 is always read out. 3 32 read CAN1_TXFQS CAN1 Tx FIFO/Queue Status Register 0x2C4 32 read-write n TFFL Tx FIFO Free Level 0 6 read TFGI Tx FIFO Get Index (*1) 8 13 read TFQF Tx FIFO/Queue Full 21 22 read TFQPI Tx FIFO/Queue Put Index 16 21 read __reserve0 0 is always read out. 6 8 read __reserve1 0 is always read out. 13 16 read __reserve2 0 is always read out. 22 32 read CAN1_XIDAM CAN1 Exte1ded ID AND Mask Register 0x290 32 read-write n EIDM Extended Message ID Mask (*1) 0 29 read-write __reserve0 0 is always read out. 29 32 read CAN1_XIDFC CAN1 Exte1ded ID Filter Co1figuratio1 Register 0x288 32 read-write n FLESA Start address of Extended Message ID (29-bit) filter list (*1) 0 16 read-write LSE List Size Extended Message ID (29-bit) 16 23 read-write __reserve0 0 is always read out. 23 32 read CANC_DBGMSG_CNT Debug Message Control Register 0x820 32 read-write n DBGMSG0 Debug Message Request of CAN0 0 1 read-write DBGMSG1 Debug Message Request of CAN1 1 2 read-write __reserve0 0 is always read out. 2 32 read CANC_ECCCTRL ECC Function Setting Register 0x900 32 read-write n CLR_DETECT Clear each status information detected when ECC error (1 bit or more) occurs (*1) 25 26 read-write CLR_MULTPL Clear each status information detected when ECC error (2 bits) occurs (*1) 17 18 read-write DETECT_EN Enable each status information detection function when ECC error (1 bit or more) occurs 24 25 read-write ECC_OFF ECC function ON/OFF 0 1 read-write IRQ_SEL Interrupt factor selection when ECC error occurs 8 9 read-write MULTPL_EN Enable each status information detection function when ECC error (2 bits) occurs 16 17 read-write __reserve0 0 is always read out. 1 8 read __reserve1 This bit must be set to 0 . 9 10 read-write __reserve2 0 is always read out. 10 16 read __reserve3 0 is always read out. 18 24 read __reserve4 0 is always read out. 26 32 read CANC_ECCRAM_DBG ECCRAM Debug Register 0x90C 32 read-write n ECCRAM_DBG_KEY Switching access route to ECC part of message RAM 0 32 read-write CANC_ECCRAM_DBGSEL ECCRAM Debug Area Selection Register 0x908 32 read-write n SEL Switching access surface to ECC part in Message RAM 0 2 read-write __reserve0 0 is always read out. 2 32 read CANC_ECCST ECC Error Detection Flag Register 0x904 32 read-write n DETECT_FLG_0 ECC error (1 bit or more) occurrence (*1) 1 2 read DETECT_FLG_1 ECC error (1 bit or more) occurrence (*1) 2 3 read DETECT_FLG_2 ECC error (1 bit or more) occurrence (*1) 3 4 read DETECT_FLG_3 ECC error (1 bit or more) occurrence (*1) 4 5 read MULTIPL_FLG ECC error (2 bits) occurrence detection (*2) 0 1 read __reserve0 0 is always read out. 5 32 read CANC_ERR_DETECT_ADDR_0 ECC Error (1 bit or more) Detection Address Register0 0x920 32 read-write n ERR_DETECT_ADDR_0 Detect and display address at the time of ECC error (1 bit or more) occurrence. 0 32 read CANC_ERR_DETECT_ADDR_1 ECC Error (1 bit or more) Detection Address Register1 0x930 32 read-write n ERR_DETECT_ADDR_1 Detect and display address at the time of ECC error (1 bit or more) occurrence. 0 32 read CANC_ERR_DETECT_ADDR_2 ECC Error (1 bit or more) Detection Address Register2 0x940 32 read-write n ERR_DETECT_ADDR_2 Detect and display address at the time of ECC error (1 bit or more) occurrence. 0 32 read CANC_ERR_DETECT_ADDR_3 ECC Error (1 bit or more) Detection Address Register3 0x950 32 read-write n ERR_DETECT_ADDR_3 Detect and display address at the time of ECC error (1 bit or more) occurrence. 0 32 read CANC_ERR_DETECT_DATA_0 ECC Error (1 bit or more) Detection Data Register0 0x924 32 read-write n ERR_DETECT_DATA_0 Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction. 0 32 read CANC_ERR_DETECT_DATA_1 ECC Error (1 bit or more) Detection Data Register1 0x934 32 read-write n ERR_DETECT_DATA_1 Detect data at the time of ECC error (1 bit or more) occurrence, and display the value before correction. 0 32 read CANC_ERR_DETECT_DATA_2 ECC Error (1 bit or more) Detection Data Register2 0x944 32 read-write n ERR_DETECT_DATA_2 Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction. 0 32 read CANC_ERR_DETECT_DATA_3 ECC Error (1 bit or more) Detection Data Register3 0x954 32 read-write n ERR_DETECT_DATA_3 Detect data at the time of ECC error (1bit or more) occurrence, and display the value before correction. 0 32 read CANC_ERR_DETECT_EBIT_0 ECC Error (1 bit or more) Target Bit Register0 0x92C 32 read-write n ERR_DETECT_EBIT_0 Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_EBIT_1 ECC Error (1 bit or more) Target Bit Register1 0x93C 32 read-write n ERR_DETECT_EBIT_1 Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (2nd stage FIFO) 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_EBIT_2 ECC Error (1 bit or more) Target Bit Register2 0x94C 32 read-write n ERR_DETECT_EBIT_2 Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (3rd stage FIFO) 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_EBIT_3 ECC Error (1 bit or more) Target Bit Register3 0x95C 32 read-write n ERR_DETECT_EBIT_3 Detect and display the target bit at the time of ECC error (1 bit or more) occurrence. (4th stage FIFO) 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_SYND_0 ECC Error (1 bit or more) Detection ECC Data Register0 0x928 32 read-write n ERR_DETECT_SYND_0 Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_SYND_1 ECC Error (1 bit or more) Detection ECC Data Register1 0x938 32 read-write n ERR_DETECT_SYND_1 Detect ECC data at the time of ECC error (1 bit or more) occurrence, and display the value before correction. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_SYND_2 ECC Error (1 bit or more) Detection ECC Data Register2 0x948 32 read-write n ERR_DETECT_SYND_2 Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_DETECT_SYND_3 ECC Error (1 bit or more) Detection ECC Data Register3 0x958 32 read-write n ERR_DETECT_SYND_3 Detect ECC data at the time of ECC error (1bit or more) occurrence, and display the value before correction. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_ERR_MULTPL_ADDR ECC Error (2 bits) Detection Address Register 0x910 32 read-write n ERR_MULTPL_ADDR Detect and display address at the time of ECC error (2 bits) occurrence. 0 32 read CANC_ERR_MULTPL_DATA ECC Error (2 bits) Detection Data Register 0x914 32 read-write n ERR_MULTPL_DATA Detect and display data at the time of ECC error (2 bits) occurrence. 0 32 read CANC_ERR_MULTPL_SYND ECC Error (2 bits) Detection ECC Data Register 0x918 32 read-write n ERR_MULTPL_SYND Detect and display ECC data at the time of ECC error (2 bits) occurrence. 0 7 read __reserve0 0 is always read out. 7 32 read CANC_EXTS_CMP External Timestamp Counter Compare Clear Register 0x810 32 read-write n CMP Set the compare value of External timestamp counter. 0 16 read-write __reserve0 0 is always read out. 16 32 read CANC_EXTS_CNTCLR External Timestamp Counter Clear Register 0x808 32 read-write n CNTCLR Clear the value of External timestamp counter (*1) 0 1 write __reserve0 0 is always read out. 1 32 read CANC_EXTS_CNTDT External Timestamp Counter Display Register 0x804 32 read-write n CNTDT Display the value of External timestamp counter. 0 16 read WRAPAROUND Status of External timestamp counter 16 17 read __reserve0 0 is always read out. 17 32 read CANC_EXTS_CNTEN External Timestamp Counter Control Register 0x800 32 read-write n CNTEN Operation control of External timestamp counter 0 1 read-write __reserve0 0 is always read out. 1 32 read CANC_EXTS_DIV External Timestamp Counter Dividing Register 0x80C 32 read-write n DIV Clock dividing ratio of External timestamp counter (*1) 0 16 read-write __reserve0 0 is always read out. 16 32 read CKM Clock Monitor CKM 0x0 0x0 0x184 registers n CKMCNT Clock Monitoring Enable Register 0x4 32 read-write n DETIRQ Action at clock error detection 1 2 read-write KEY_CODE Register Key 16 32 read-write MONEN Clock monitoring function enable 0 1 read-write MVCLK Selection of condition to enter clock transition mode 2 3 read-write __reserve0 0 is always read out. 3 16 read CKMSETL Clock Monitoring Frequency Lower Setting Register 0x14 32 read-write n KEY_CODE Register Key 16 32 read-write MNLSET Lower frequency limit setting for clock monitoring 0 14 read-write __reserve0 0 is always read out. 14 16 read CKMSETU Clock Monitoring Frequency Upper Setting Register 0x18 32 read-write n KEY_CODE Register Key 16 32 read-write MNUSET Upper frequency limit setting for clock monitoring 0 14 read-write __reserve0 0 is always read out. 14 16 read CKMSTAT Clock Monitoring Status Register 0xC 8 read-write n LOWDET Clock error factor (lower frequency error) 1 2 read MONRUN Clock monitoring function running status 7 8 read REFSTOP Clock error factor (reference clock stop) 3 4 read UPDET Clock error factor (upper frequency error) 2 3 read ZERODET Clock error factor (target clock stop) 0 1 read __reserve0 0 is always read out. 4 7 read CKMSTATC Clock Monitoring Status Clear Register 0x10 32 read-write n CKMDETC Clear CKMSTAT 0 4 write KEY_CODE Register Key 16 32 read-write __reserve0 0 is always read out. 4 16 read CKMTRMD Clock Transition Mode Register 0x0 32 read-write n KEY_CODE Register Key 16 32 read-write TRMD Status and control of the clock transition mode 0 1 read-write __reserve0 0 is always read out. 1 16 read CMP Comparator CMP 0x0 0x0 0x48 registers n G20 20 G21 21 G22 22 G23 23 G24 24 G25 25 G26 26 G27 27 G28 28 G29 29 CMP0CTR Comparator 0 Co0trol Register 0x0 16 read-write n EN Start of the comparator comparison 0 1 read-write HYS0 CMPn0 hysteresis setting 6 7 read-write HYS1 CMPn1 hysteresis setting 7 8 read-write INV0 Selection of CMPn0 comparator detection polarity 4 5 read-write INV1 Selection of CMPn1 comparator detection polarity 5 6 read-write MD Operation mode setting 1 2 read-write NF Selection of comparator output noise filter 8 12 read-write PW0 Operation of the CMPn0 comparator 2 3 read-write PW1 Operation of the CMPn1 comparator 3 4 read-write __reserve0 0 is always read out. 12 16 read CMP0STR Comparator 0 Status Register 0x4 16 read-write n STR0 Detection state of CMPn0 0 1 read STR1 Detection state of CMPn1 1 2 read __reserve0 0 is always read out. 2 16 read CMP1CTR Comparator 1 Co1trol Register 0x10 16 read-write n EN Start of the comparator comparison 0 1 read-write HYS0 CMPn0 hysteresis setting 6 7 read-write HYS1 CMPn1 hysteresis setting 7 8 read-write INV0 Selection of CMPn0 comparator detection polarity 4 5 read-write INV1 Selection of CMPn1 comparator detection polarity 5 6 read-write MD Operation mode setting 1 2 read-write NF Selection of comparator output noise filter 8 12 read-write PW0 Operation of the CMPn0 comparator 2 3 read-write PW1 Operation of the CMPn1 comparator 3 4 read-write __reserve0 0 is always read out. 12 16 read CMP1STR Comparator 1 Status Register 0x14 16 read-write n STR0 Detection state of CMPn0 0 1 read STR1 Detection state of CMPn1 1 2 read __reserve0 0 is always read out. 2 16 read CMP2CTR Comparator 2 Co2trol Register 0x20 16 read-write n EN Start of the comparator comparison 0 1 read-write HYS0 CMPn0 hysteresis setting 6 7 read-write HYS1 CMPn1 hysteresis setting 7 8 read-write INV0 Selection of CMPn0 comparator detection polarity 4 5 read-write INV1 Selection of CMPn1 comparator detection polarity 5 6 read-write MD Operation mode setting 1 2 read-write NF Selection of comparator output noise filter 8 12 read-write PW0 Operation of the CMPn0 comparator 2 3 read-write PW1 Operation of the CMPn1 comparator 3 4 read-write __reserve0 0 is always read out. 12 16 read CMP2STR Comparator 2 Status Register 0x24 16 read-write n STR0 Detection state of CMPn0 0 1 read STR1 Detection state of CMPn1 1 2 read __reserve0 0 is always read out. 2 16 read CMP3CTR Comparator 3 Co3trol Register 0x30 16 read-write n EN Start of the comparator comparison 0 1 read-write HYS0 CMPn0 hysteresis setting 6 7 read-write HYS1 CMPn1 hysteresis setting 7 8 read-write INV0 Selection of CMPn0 comparator detection polarity 4 5 read-write INV1 Selection of CMPn1 comparator detection polarity 5 6 read-write MD Operation mode setting 1 2 read-write NF Selection of comparator output noise filter 8 12 read-write PW0 Operation of the CMPn0 comparator 2 3 read-write PW1 Operation of the CMPn1 comparator 3 4 read-write __reserve0 0 is always read out. 12 16 read CMP3STR Comparator 3 Status Register 0x34 16 read-write n STR0 Detection state of CMPn0 0 1 read STR1 Detection state of CMPn1 1 2 read __reserve0 0 is always read out. 2 16 read CMP4CTR Comparator 4 Co4trol Register 0x40 16 read-write n EN Start of the comparator comparison 0 1 read-write HYS0 CMPn0 hysteresis setting 6 7 read-write HYS1 CMPn1 hysteresis setting 7 8 read-write INV0 Selection of CMPn0 comparator detection polarity 4 5 read-write INV1 Selection of CMPn1 comparator detection polarity 5 6 read-write MD Operation mode setting 1 2 read-write NF Selection of comparator output noise filter 8 12 read-write PW0 Operation of the CMPn0 comparator 2 3 read-write PW1 Operation of the CMPn1 comparator 3 4 read-write __reserve0 0 is always read out. 12 16 read CMP4STR Comparator 4 Status Register 0x44 16 read-write n STR0 Detection state of CMPn0 0 1 read STR1 Detection state of CMPn1 1 2 read __reserve0 0 is always read out. 2 16 read CRC CRC Calculation Circuit CRC 0x0 0x0 0x74 registers n CRC0CLR CRC0 Clear Register 0x10 8 read-write n CLR Set CRC0 seed value. 0 1 write __reserve0 0 is always read out. 1 8 read CRC0DATA_LSB CRC0 Data Register LSB 1st 0x4 32 read-write n DATA_LSB Data written to this register will be taken to perform CRC calculation with Least Significant Bit (LSB) First. 0 32 write CRC0DATA_MSB CRC0 Data Register MSB 1st 0x0 32 read-write n DATA_MSB Data written to this register will be taken to perform CRC calculation with Most Significant Bit (MSB) First. 0 32 write CRC0RES_LSB CRC0 Checksum Register LSB 1st 0xC 32 read-write n RES_LSB A read access to this register read out CRC0 checksum value with LSB First. 0 32 read CRC0RES_MSB CRC0 Checksum Register MSB 1st 0x8 32 read-write n RES_MSB A write access to this register will load CRC0 seed value to CRC0RES_MSB register. 0 32 read-write CRC1CLR CRC1 Clear Register 0x30 8 read-write n CLR Set CRC1 seed value. 0 1 write __reserve0 0 is always read out. 1 8 read CRC1DATA_LSB CRC1 Data Register LSB 1st 0x24 8 read-write n DATA_LSB Data written to this register will be taken to perform CRC calculation with Least Significant Bit (LSB) First. 0 8 write CRC1DATA_MSB CRC1 Data Register MSB 1st 0x20 8 read-write n DATA_MSB Data written to this register will be taken to perform CRC calculation with Most Significant Bit (MSB) First. 0 8 write CRC1RES_LSB CRC1 Checksum Register LSB 1st 0x2C 16 read-write n RES_LSB A read access to this register read out CRC1 checksum value with LSB First. 0 16 read CRC1RES_MSB CRC1 Checksum Register MSB 1st 0x28 16 read-write n RES_MSB A write access to this register will load CRC1 seed value to CRC1RES_MSB register. 0 16 read-write CRC2CLR CRC2 Clear Register 0x50 8 read-write n CLR Set CRC2 seed value. 0 1 write __reserve0 0 is always read out. 1 8 read CRC2DATA_LSB CRC2 Data Register LSB 1st 0x44 8 read-write n DATA_LSB Data written to this register will be taken to perform CRC calculation with Least Significant Bit (LSB) First. 0 8 write CRC2DATA_MSB CRC2 Data Register MSB 1st 0x40 8 read-write n DATA_MSB Data written to this register will be taken to perform CRC calculation with Most Significant Bit (MSB) First. 0 8 write CRC2RES_LSB CRC2 Checksum Register LSB 1st 0x4C 16 read-write n RES_LSB A read access to this register read out CRC2 checksum value with LSB First. 0 16 read CRC2RES_MSB CRC2 Checksum Register MSB 1st 0x48 16 read-write n RES_MSB A write access to this register will load CRC2 seed value to CRC1RES_MSB register. 0 16 read-write CRC3CLR CRC3 Clear Register 0x70 8 read-write n CLR Set CRC3 seed value. 0 1 write __reserve0 0 is always read out. 1 8 read CRC3DATA_LSB CRC3 Data Register LSB 1st 0x64 8 read-write n DATA_LSB Data written to this register will be taken to perform CRC calculation with Least Significant Bit (LSB) First. 0 8 write CRC3DATA_MSB CRC3Data Register MSB 1st 0x60 8 read-write n DATA_MSB Data written to this register will be taken to perform CRC calculation with Most Significant Bit (MSB) First. 0 8 write CRC3RES_LSB CRC3 Checksum Register LSB 1st 0x6C 8 read-write n RES_LSB A read access to this register read out CRC3 checksum value with LSB First. 0 8 read CRC3RES_MSB CRC3 Checksum Register MSB 1st 0x68 8 read-write n RES_MSB A write access to this register will load CRC3 seed value to CRC1RES_MSB register. 0 8 read-write DAC D/A Converter DAC 0x0 0x0 0x108 registers n DAC00CTR DAC00 Co00trol Register 0x0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC00DR DAC00 I00put Data Register 0x4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC00SLPCNT DAC00 Slope Compe00satio00 Co00trol Register 0x8 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC00SLPCYC DAC00 Slope Compe00satio00 Cycle Register 0xE 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC00SLPSET DAC00 Slope Compe00satio00 Setti00g Register 0xC 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC01CTR DAC01 Co01trol Register 0x10 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC01DR DAC01 I01put Data Register 0x14 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC01SLPCNT DAC01 Slope Compe01satio01 Co01trol Register 0x18 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC01SLPCYC DAC01 Slope Compe01satio01 Cycle Register 0x1E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC01SLPSET DAC01 Slope Compe01satio01 Setti01g Register 0x1C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC10CTR DAC10 Co10trol Register 0x20 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC10DR DAC10 I10put Data Register 0x24 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC10SLPCNT DAC10 Slope Compe10satio10 Co10trol Register 0x28 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC10SLPCYC DAC10 Slope Compe10satio10 Cycle Register 0x2E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC10SLPSET DAC10 Slope Compe10satio10 Setti10g Register 0x2C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC11CTR DAC11 Co11trol Register 0x30 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC11DR DAC11 I11put Data Register 0x34 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC11SLPCNT DAC11 Slope Compe11satio11 Co11trol Register 0x38 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC11SLPCYC DAC11 Slope Compe11satio11 Cycle Register 0x3E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC11SLPSET DAC11 Slope Compe11satio11 Setti11g Register 0x3C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC20CTR DAC20 Co20trol Register 0x40 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC20DR DAC20 I20put Data Register 0x44 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC20SLPCNT DAC20 Slope Compe20satio20 Co20trol Register 0x48 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC20SLPCYC DAC20 Slope Compe20satio20 Cycle Register 0x4E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC20SLPSET DAC20 Slope Compe20satio20 Setti20g Register 0x4C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC21CTR DAC21 Co21trol Register 0x50 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC21DR DAC21 I21put Data Register 0x54 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC21SLPCNT DAC21 Slope Compe21satio21 Co21trol Register 0x58 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC21SLPCYC DAC21 Slope Compe21satio21 Cycle Register 0x5E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC21SLPSET DAC21 Slope Compe21satio21 Setti21g Register 0x5C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC30CTR DAC30 Co30trol Register 0x60 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC30DR DAC30 I30put Data Register 0x64 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC30SLPCNT DAC30 Slope Compe30satio30 Co30trol Register 0x68 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC30SLPCYC DAC30 Slope Compe30satio30 Cycle Register 0x6E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC30SLPSET DAC30 Slope Compe30satio30 Setti30g Register 0x6C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC31CTR DAC31 Co31trol Register 0x70 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC31DR DAC31 I31put Data Register 0x74 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC31SLPCNT DAC31 Slope Compe31satio31 Co31trol Register 0x78 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC31SLPCYC DAC31 Slope Compe31satio31 Cycle Register 0x7E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC31SLPSET DAC31 Slope Compe31satio31 Setti31g Register 0x7C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC40CTR DAC40 Co40trol Register 0x80 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC40DR DAC40 I40put Data Register 0x84 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC40SLPCNT DAC40 Slope Compe40satio40 Co40trol Register 0x88 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC40SLPCYC DAC40 Slope Compe40satio40 Cycle Register 0x8E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC40SLPSET DAC40 Slope Compe40satio40 Setti40g Register 0x8C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DAC41CTR DAC41 Co41trol Register 0x90 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DAC41DR DAC41 I41put Data Register 0x94 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DAC41SLPCNT DAC41 Slope Compe41satio41 Co41trol Register 0x98 16 read-write n EDGESEL Slope compensation pin edge select 1 2 read-write SLPEN D/An slope compensation enable 0 1 read-write TGTSEL Slope compensation pin selection 8 13 read-write __reserve0 0 is always read out. 2 8 read __reserve1 0 is always read out. 13 16 read DAC41SLPCYC DAC41 Slope Compe41satio41 Cycle Register 0x9E 16 read-write n CYCLE Set slope compensation subtraction cycle. 0 8 read-write OFFSET Set slope compensation subtraction start offset value. 8 16 read-write DAC41SLPSET DAC41 Slope Compe41satio41 Setti41g Register 0x9C 8 read-write n SLPSET Set of slope compensation subtraction value. 0 5 read-write __reserve0 0 is always read out. 5 8 read DACP0CTR DACP0 Co0trol Register 0xF0 8 read-write n OE Output control to DAOTn pin 1 2 read-write ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 2 8 read DACP0DR DACP0 I0put Data Register 0xF4 16 read-write n BUF Set the input data which performs D/A conversion by DACPn. 0 10 read-write __reserve0 0 is always read out. 10 16 read DACP1CTR DACP1 Co1trol Register 0x100 8 read-write n OE Output control to DAOTn pin 1 2 read-write ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 2 8 read DACP1DR DACP1 I1put Data Register 0x104 16 read-write n BUF Set the input data which performs D/A conversion by DACPn. 0 10 read-write __reserve0 0 is always read out. 10 16 read DACV00CTR DACV00 CoV00trol Register 0xA0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DACV00DR DACV00 IV00put Data Register 0xA4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DACV01CTR DACV01 CoV01trol Register 0xB0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DACV01DR DACV01 IV01put Data Register 0xB4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DACV02CTR DACV02 CoV02trol Register 0xC0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DACV02DR DACV02 IV02put Data Register 0xC4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DACV1CTR DACV1 CoV1trol Register 0xD0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DACV1DR DACV1 IV1put Data Register 0xD4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DACV2CTR DACV2 CoV2trol Register 0xE0 8 read-write n ON Operation control of D/A converter 0 1 read-write __reserve0 0 is always read out. 1 8 read DACV2DR DACV2 IV2put Data Register 0xE4 8 read-write n BUF Set the input data which performs D/A conversion by DACn. 0 8 read-write DMAC DMA Controller DMAC 0x0 0x0 0x1F0C registers n G144 144 G145 145 G146 146 G147 147 G148 148 G149 149 G150 150 G151 151 G152 152 G153 153 G154 154 DMA0CNT DMA0 Tra0sfer Word Cou0t Register 0x8 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA0CTR DMA Co0trol Register 0x1C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA0DST DMA0 Desti0atio0 Address Register 0x4 32 read-write n DST DMA transfer destination address 0 32 read-write DMA0EXCNT Executio0 Tra0sfer Word Cou0t Register 0x14 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA0EXDST DMA0 Executio0 Desti0atio0 Address Register 0x10 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA0EXSRC DMA0 Executio0 Source Address Register 0xC 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA0RLCNT DMA0 Reload Cou0ter 0x18 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA0SFTRQ DMA0 Software Request Register 0x20 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA0SRC DMA0 Source Address Register 0x0 32 read-write n SRC DMA transfer source address 0 32 read-write DMA0STAT DMA Status Read Register 0x24 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA0STATW DMA Status Clear Register 0x28 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA10CNT DMA10 Tra10sfer Word Cou10t Register 0x1088 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA10CTR DMA Co10trol Register 0x109C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA10DST DMA10 Desti10atio10 Address Register 0x1084 32 read-write n DST DMA transfer destination address 0 32 read-write DMA10EXCNT Executio10 Tra10sfer Word Cou10t Register 0x1094 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA10EXDST DMA10 Executio10 Desti10atio10 Address Register 0x1090 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA10EXSRC DMA10 Executio10 Source Address Register 0x108C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA10RLCNT DMA10 Reload Cou10ter 0x1098 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA10SFTRQ DMA10 Software Request Register 0x10A0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA10SRC DMA10 Source Address Register 0x1080 32 read-write n SRC DMA transfer source address 0 32 read-write DMA10STAT DMA Status Read Register 0x10A4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA10STATW DMA Status Clear Register 0x10A8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA11CNT DMA11 Tra11sfer Word Cou11t Register 0x10C8 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA11CTR DMA Co11trol Register 0x10DC 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA11DST DMA11 Desti11atio11 Address Register 0x10C4 32 read-write n DST DMA transfer destination address 0 32 read-write DMA11EXCNT Executio11 Tra11sfer Word Cou11t Register 0x10D4 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA11EXDST DMA11 Executio11 Desti11atio11 Address Register 0x10D0 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA11EXSRC DMA11 Executio11 Source Address Register 0x10CC 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA11RLCNT DMA11 Reload Cou11ter 0x10D8 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA11SFTRQ DMA11 Software Request Register 0x10E0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA11SRC DMA11 Source Address Register 0x10C0 32 read-write n SRC DMA transfer source address 0 32 read-write DMA11STAT DMA Status Read Register 0x10E4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA11STATW DMA Status Clear Register 0x10E8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA12CNT DMA12 Tra12sfer Word Cou12t Register 0x1108 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA12CTR DMA Co12trol Register 0x111C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA12DST DMA12 Desti12atio12 Address Register 0x1104 32 read-write n DST DMA transfer destination address 0 32 read-write DMA12EXCNT Executio12 Tra12sfer Word Cou12t Register 0x1114 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA12EXDST DMA12 Executio12 Desti12atio12 Address Register 0x1110 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA12EXSRC DMA12 Executio12 Source Address Register 0x110C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA12RLCNT DMA12 Reload Cou12ter 0x1118 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA12SFTRQ DMA12 Software Request Register 0x1120 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA12SRC DMA12 Source Address Register 0x1100 32 read-write n SRC DMA transfer source address 0 32 read-write DMA12STAT DMA Status Read Register 0x1124 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA12STATW DMA Status Clear Register 0x1128 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA13CNT DMA13 Tra13sfer Word Cou13t Register 0x1148 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA13CTR DMA Co13trol Register 0x115C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA13DST DMA13 Desti13atio13 Address Register 0x1144 32 read-write n DST DMA transfer destination address 0 32 read-write DMA13EXCNT Executio13 Tra13sfer Word Cou13t Register 0x1154 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA13EXDST DMA13 Executio13 Desti13atio13 Address Register 0x1150 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA13EXSRC DMA13 Executio13 Source Address Register 0x114C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA13RLCNT DMA13 Reload Cou13ter 0x1158 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA13SFTRQ DMA13 Software Request Register 0x1160 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA13SRC DMA13 Source Address Register 0x1140 32 read-write n SRC DMA transfer source address 0 32 read-write DMA13STAT DMA Status Read Register 0x1164 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA13STATW DMA Status Clear Register 0x1168 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA14CNT DMA14 Tra14sfer Word Cou14t Register 0x1188 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA14CTR DMA Co14trol Register 0x119C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA14DST DMA14 Desti14atio14 Address Register 0x1184 32 read-write n DST DMA transfer destination address 0 32 read-write DMA14EXCNT Executio14 Tra14sfer Word Cou14t Register 0x1194 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA14EXDST DMA14 Executio14 Desti14atio14 Address Register 0x1190 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA14EXSRC DMA14 Executio14 Source Address Register 0x118C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA14RLCNT DMA14 Reload Cou14ter 0x1198 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA14SFTRQ DMA14 Software Request Register 0x11A0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA14SRC DMA14 Source Address Register 0x1180 32 read-write n SRC DMA transfer source address 0 32 read-write DMA14STAT DMA Status Read Register 0x11A4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA14STATW DMA Status Clear Register 0x11A8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA15CNT DMA15 Tra15sfer Word Cou15t Register 0x11C8 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA15CTR DMA Co15trol Register 0x11DC 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA15DST DMA15 Desti15atio15 Address Register 0x11C4 32 read-write n DST DMA transfer destination address 0 32 read-write DMA15EXCNT Executio15 Tra15sfer Word Cou15t Register 0x11D4 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA15EXDST DMA15 Executio15 Desti15atio15 Address Register 0x11D0 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA15EXSRC DMA15 Executio15 Source Address Register 0x11CC 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA15RLCNT DMA15 Reload Cou15ter 0x11D8 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA15SFTRQ DMA15 Software Request Register 0x11E0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA15SRC DMA15 Source Address Register 0x11C0 32 read-write n SRC DMA transfer source address 0 32 read-write DMA15STAT DMA Status Read Register 0x11E4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA15STATW DMA Status Clear Register 0x11E8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA1CNT DMA1 Tra1sfer Word Cou1t Register 0x48 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA1CTR DMA Co1trol Register 0x5C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA1DST DMA1 Desti1atio1 Address Register 0x44 32 read-write n DST DMA transfer destination address 0 32 read-write DMA1EXCNT Executio1 Tra1sfer Word Cou1t Register 0x54 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA1EXDST DMA1 Executio1 Desti1atio1 Address Register 0x50 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA1EXSRC DMA1 Executio1 Source Address Register 0x4C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA1RLCNT DMA1 Reload Cou1ter 0x58 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA1SFTRQ DMA1 Software Request Register 0x60 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA1SRC DMA1 Source Address Register 0x40 32 read-write n SRC DMA transfer source address 0 32 read-write DMA1STAT DMA Status Read Register 0x64 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA1STATW DMA Status Clear Register 0x68 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA2CNT DMA2 Tra2sfer Word Cou2t Register 0x88 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA2CTR DMA Co2trol Register 0x9C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA2DST DMA2 Desti2atio2 Address Register 0x84 32 read-write n DST DMA transfer destination address 0 32 read-write DMA2EXCNT Executio2 Tra2sfer Word Cou2t Register 0x94 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA2EXDST DMA2 Executio2 Desti2atio2 Address Register 0x90 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA2EXSRC DMA2 Executio2 Source Address Register 0x8C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA2RLCNT DMA2 Reload Cou2ter 0x98 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA2SFTRQ DMA2 Software Request Register 0xA0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA2SRC DMA2 Source Address Register 0x80 32 read-write n SRC DMA transfer source address 0 32 read-write DMA2STAT DMA Status Read Register 0xA4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA2STATW DMA Status Clear Register 0xA8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA3CNT DMA3 Tra3sfer Word Cou3t Register 0xC8 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA3CTR DMA Co3trol Register 0xDC 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA3DST DMA3 Desti3atio3 Address Register 0xC4 32 read-write n DST DMA transfer destination address 0 32 read-write DMA3EXCNT Executio3 Tra3sfer Word Cou3t Register 0xD4 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA3EXDST DMA3 Executio3 Desti3atio3 Address Register 0xD0 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA3EXSRC DMA3 Executio3 Source Address Register 0xCC 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA3RLCNT DMA3 Reload Cou3ter 0xD8 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA3SFTRQ DMA3 Software Request Register 0xE0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA3SRC DMA3 Source Address Register 0xC0 32 read-write n SRC DMA transfer source address 0 32 read-write DMA3STAT DMA Status Read Register 0xE4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA3STATW DMA Status Clear Register 0xE8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA4CNT DMA4 Tra4sfer Word Cou4t Register 0x108 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA4CTR DMA Co4trol Register 0x11C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA4DST DMA4 Desti4atio4 Address Register 0x104 32 read-write n DST DMA transfer destination address 0 32 read-write DMA4EXCNT Executio4 Tra4sfer Word Cou4t Register 0x114 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA4EXDST DMA4 Executio4 Desti4atio4 Address Register 0x110 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA4EXSRC DMA4 Executio4 Source Address Register 0x10C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA4RLCNT DMA4 Reload Cou4ter 0x118 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA4SFTRQ DMA4 Software Request Register 0x120 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA4SRC DMA4 Source Address Register 0x100 32 read-write n SRC DMA transfer source address 0 32 read-write DMA4STAT DMA Status Read Register 0x124 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA4STATW DMA Status Clear Register 0x128 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA5CNT DMA5 Tra5sfer Word Cou5t Register 0x148 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA5CTR DMA Co5trol Register 0x15C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA5DST DMA5 Desti5atio5 Address Register 0x144 32 read-write n DST DMA transfer destination address 0 32 read-write DMA5EXCNT Executio5 Tra5sfer Word Cou5t Register 0x154 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA5EXDST DMA5 Executio5 Desti5atio5 Address Register 0x150 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA5EXSRC DMA5 Executio5 Source Address Register 0x14C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA5RLCNT DMA5 Reload Cou5ter 0x158 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA5SFTRQ DMA5 Software Request Register 0x160 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA5SRC DMA5 Source Address Register 0x140 32 read-write n SRC DMA transfer source address 0 32 read-write DMA5STAT DMA Status Read Register 0x164 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA5STATW DMA Status Clear Register 0x168 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA6CNT DMA6 Tra6sfer Word Cou6t Register 0x188 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA6CTR DMA Co6trol Register 0x19C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA6DST DMA6 Desti6atio6 Address Register 0x184 32 read-write n DST DMA transfer destination address 0 32 read-write DMA6EXCNT Executio6 Tra6sfer Word Cou6t Register 0x194 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA6EXDST DMA6 Executio6 Desti6atio6 Address Register 0x190 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA6EXSRC DMA6 Executio6 Source Address Register 0x18C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA6RLCNT DMA6 Reload Cou6ter 0x198 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA6SFTRQ DMA6 Software Request Register 0x1A0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA6SRC DMA6 Source Address Register 0x180 32 read-write n SRC DMA transfer source address 0 32 read-write DMA6STAT DMA Status Read Register 0x1A4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA6STATW DMA Status Clear Register 0x1A8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA7CNT DMA7 Tra7sfer Word Cou7t Register 0x1C8 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA7CTR DMA Co7trol Register 0x1DC 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA7DST DMA7 Desti7atio7 Address Register 0x1C4 32 read-write n DST DMA transfer destination address 0 32 read-write DMA7EXCNT Executio7 Tra7sfer Word Cou7t Register 0x1D4 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA7EXDST DMA7 Executio7 Desti7atio7 Address Register 0x1D0 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA7EXSRC DMA7 Executio7 Source Address Register 0x1CC 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA7RLCNT DMA7 Reload Cou7ter 0x1D8 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA7SFTRQ DMA7 Software Request Register 0x1E0 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA7SRC DMA7 Source Address Register 0x1C0 32 read-write n SRC DMA transfer source address 0 32 read-write DMA7STAT DMA Status Read Register 0x1E4 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA7STATW DMA Status Clear Register 0x1E8 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA8CNT DMA8 Tra8sfer Word Cou8t Register 0x1008 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA8CTR DMA Co8trol Register 0x101C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA8DST DMA8 Desti8atio8 Address Register 0x1004 32 read-write n DST DMA transfer destination address 0 32 read-write DMA8EXCNT Executio8 Tra8sfer Word Cou8t Register 0x1014 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA8EXDST DMA8 Executio8 Desti8atio8 Address Register 0x1010 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA8EXSRC DMA8 Executio8 Source Address Register 0x100C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA8RLCNT DMA8 Reload Cou8ter 0x1018 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA8SFTRQ DMA8 Software Request Register 0x1020 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA8SRC DMA8 Source Address Register 0x1000 32 read-write n SRC DMA transfer source address 0 32 read-write DMA8STAT DMA Status Read Register 0x1024 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA8STATW DMA Status Clear Register 0x1028 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMA9CNT DMA9 Tra9sfer Word Cou9t Register 0x1048 32 read-write n CNT DMA transfer word count 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA9CTR DMA Co9trol Register 0x105C 32 read-write n DMAEN DMA transfer enable 31 32 read-write DSTMD DMA transfer addressing mode on destination address 28 29 read-write FACTOR DMA transfer request 0 7 read-write SIZE DMA transfer unit 24 26 read-write SRCMD DMA transfer addressing mode on source address 26 27 read-write __reserve0 0 is always read out. 7 24 read __reserve1 0 is always read out. 27 28 read __reserve2 0 is always read out. 29 31 read DMA9DST DMA9 Desti9atio9 Address Register 0x1044 32 read-write n DST DMA transfer destination address 0 32 read-write DMA9EXCNT Executio9 Tra9sfer Word Cou9t Register 0x1054 32 read-write n EXCNT During DMA transfer, the DMA transfer word count is held. 0 16 read-write __reserve0 0 is always read out. 16 32 read DMA9EXDST DMA9 Executio9 Desti9atio9 Address Register 0x1050 32 read-write n EXDST During DMA transfer, the transfer destination address is held. 0 32 read-write DMA9EXSRC DMA9 Executio9 Source Address Register 0x104C 32 read-write n EXSRC During DMA transfer, the transfer source address is held. 0 32 read-write DMA9RLCNT DMA9 Reload Cou9ter 0x1058 32 read-write n DSTRLD Load enable(during reload operation) 31 32 read-write RLDCNT The number of times of reloading 0 16 read-write SRCRLD Load enable(during reload operation) 30 31 read-write __reserve0 0 is always read out. 16 30 read DMA9SFTRQ DMA9 Software Request Register 0x1060 32 read-write n SFTRQ DMA request by software 0 1 write __reserve0 0 is always read out. 1 32 read DMA9SRC DMA9 Source Address Register 0x1040 32 read-write n SRC DMA transfer source address 0 32 read-write DMA9STAT DMA Status Read Register 0x1064 32 read-write n DMAREQ DMA transfer status 0 1 read OVFERR DMA transfer request overflow bit 2 3 read REQERR Disabled DMA transfer request error bit 1 2 read SYSERR System error bit 3 4 read __reserve0 0 is always read out. 4 32 read DMA9STATW DMA Status Clear Register 0x1068 32 read-write n OVFERR Clear the DMA transfer request overflow bit 2 3 write REQERR Clear the DMA transfer request error bit 1 2 write SYSERR Clear the system error bit 3 4 write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 32 read DMAC0NMI DMA0NMI Status Read Register 0xF00 32 read-write n NMI NMI detection bit (module m) 0 1 read __reserve0 0 is always read out. 1 32 read DMAC0NMIEN DMA0NMI Enable Register 0xF08 32 read-write n NMIEN DMA transfer discontinuity (module m) when NMI is detected 0 1 read-write __reserve0 0 is always read out. 1 32 read DMAC0NMIW DMA0NMI Status Clear Register 0xF04 32 read-write n NMIW Clear the NMI detection bit (module m) 0 1 write __reserve0 0 is always read out. 1 32 read DMAC1NMI DMA1NMI Status Read Register 0x1F00 32 read-write n NMI NMI detection bit (module m) 0 1 read __reserve0 0 is always read out. 1 32 read DMAC1NMIEN DMA1NMI Enable Register 0x1F08 32 read-write n NMIEN DMA transfer discontinuity (module m) when NMI is detected 0 1 read-write __reserve0 0 is always read out. 1 32 read DMAC1NMIW DMA1NMI Status Clear Register 0x1F04 32 read-write n NMIW Clear the NMI detection bit (module m) 0 1 write __reserve0 0 is always read out. 1 32 read FL Flash Memory FL 0x0 0x0 0xE4 registers n G32 32 G33 33 G34 34 G155 155 FIDBGCLRD D-Flash Debug Access Error Detection Clear Register 0xDC 8 read-write n DBGMCLR D-Flash 2-bit or more error detection at debugger access clear 1 2 read-write DBGSCLR D-Flash 1-bit error detection at debugger access clear 0 1 read-write __reserve0 0 is always read out. 2 8 read FIDBGCLRI I-Flash Debug Access Error Detection Clear Register 0xAC 8 read-write n DBGMCLR I-Flash 2-bit or more error detection at debugger access clear 1 2 read-write DBGSCLR I-Flash 1-bit error detection at debugger access clear 0 1 read-write __reserve0 0 is always read out. 2 8 read FIDBGDETD D-Flash Debug Access Error Detection Register 0xD8 8 read-write n DBGMDET D-Flash 2-bit or more error detection at debugger access 1 2 read DBGSDET D-Flash 1-bit error detection at debugger access 0 1 read __reserve0 0 is always read out. 2 8 read FIDBGDETI I-Flash Debug Access Error Detection Register 0xA8 8 read-write n DBGMDET I-Flash 2-bit or more error detection at debugger access 1 2 read DBGSDET I-Flash 1-bit error detection at debugger access 0 1 read __reserve0 0 is always read out. 2 8 read FIFDIECNT D-Flash ECC Control Register 0xB0 32 read-write n ECCMOD D-Flash ECC enable 0 1 read-write KEY_CODE Register Key 8 16 read-write __reserve0 This bit must be set to 0 . 1 2 read-write __reserve1 0 is always read out. 2 8 read __reserve2 0 is always read out. 16 32 read FIFDMBCLR D-Flash 2-bit or more Error Interrupt Clear Register 0xCC 32 read-write n MBECLRI [Write] 0 1 read-write __reserve0 0 is always read out. 1 32 read FIFDMBDET D-Flash 2-bit or more Error Detection Register 0xC8 32 read-write n MBDET D-Flash ECC 2-bit error interrupt target address 0 1 read MBMASTER D-Flash ECC 2-bit error interrupt generation master information 8 12 read __reserve0 0 is always read out. 1 8 read __reserve1 0 is always read out. 12 32 read FIFDMBEA D-Flash 2-bit or more Error Address 0xC4 32 read-write n MBEA D-Flash ECC 2-bit error interrupt target address 0 32 read FIFDSBCLR D-Flash 1-bit Error Interrupt Clear Register 0xC0 32 read-write n SBECLRI [Write] 0 1 read-write __reserve0 0 is always read out. 1 32 read FIFDSBDET D-Flash 1-bit Error Detection Register 0xBC 32 read-write n SBDET D-Flash ECC 1-bit error interrupt target address 0 1 read SBMASTER D-Flash ECC 1-bit error interrupt generation master information 8 12 read __reserve0 0 is always read out. 1 8 read __reserve1 0 is always read out. 12 32 read FIFDSBEA D-Flash 1-bit Error Address 0xB8 32 read-write n SBEA D-Flash ECC 1-bit error interrupt target address 0 32 read FIFDWAIT D-Flash Access Wait Control Register 0xD0 32 read-write n KEY_CODE Register Key 8 16 read-write WAITREG D-Flash Read access wait setting 0 4 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 16 32 read FIFEWEN Rewriting Enable Register 0x0 32 read-write n FEWEN Setup enable/disable the flash memory to be rewritten 0 8 read-write KEY_CODE Register Key 8 16 write __reserve0 0 is always read out. 16 32 read FIFIIECNT I-Flash ECC Control Register 0x80 32 read-write n ECCMOD I-Flash ECC enable 0 1 read-write KEY_CODE Register Key 8 16 read-write __reserve0 This bit must be set to 0 . 1 2 read-write __reserve1 0 is always read out. 2 8 read __reserve2 0 is always read out. 16 32 read FIFIMBCLR I-Flash 2-bit or more Error Interrupt Clear Register 0x9C 32 read-write n MBECLRI [Write] 0 1 read-write __reserve0 0 is always read out. 1 32 read FIFIMBDET I-Flash 2-bit or more Error Detection Register 0x98 32 read-write n MBDET I-Flash ECC 2-bit error interrupt target address 0 1 read MBMASTER I-Flash ECC 2-bit error interrupt generation master information 8 12 read __reserve0 0 is always read out. 1 8 read __reserve1 0 is always read out. 12 32 read FIFIMBEA I-Flash 2-bit or more Error Address 0x94 32 read-write n MBEA I-Flash ECC 2-bit error interrupt target address 0 32 read FIFISBCLR I-Flash 1-bit Error Interrupt Clear Register 0x90 32 read-write n SBECLRI [Write] 0 1 read-write __reserve0 0 is always read out. 1 32 read FIFISBDET I-Flash 1-bit Error Detection Register 0x8C 32 read-write n SBDET I-Flash ECC 1-bit error interrupt target address 0 1 read SBMASTER I-Flash ECC 1-bit error interrupt generation master information 8 12 read __reserve0 0 is always read out. 1 8 read __reserve1 0 is always read out. 12 32 read FIFISBEA I-Flash 1-bit Error Address 0x88 32 read-write n SBEA I-Flash ECC 1-bit error interrupt target address 0 32 read FIFIWAIT I-Flash Access Wait Control Register 0xA0 32 read-write n KEY_CODE Register Key 8 16 read-write WAITREG I-Flash Read access wait setting 0 4 read-write __reserve0 0 is always read out. 4 8 read __reserve1 0 is always read out. 16 32 read FIFMON Rewriting Status Register 0x8 32 read-write n HPROD0 D-Flash HW protect 0 error flag 13 14 read HPROD1 D-Flash HW protect 1 error flag 14 15 read HPROI0 I-Flash HW protect 0 error flag 11 12 read HPROI1 I-Flash HW protect 1 error flag 12 13 read NBRANK Writing blank error flag 8 9 read OUTADR Rewriting address error flag 9 10 read SPRO Rewriting SW protect error flag 10 11 read WBUSY Rewriting execution flag 0 1 read __reserve0 Undefined value will be read 1 3 read __reserve1 0 is always read out. 3 8 read __reserve2 0 is always read out. 15 16 read __reserve3 0 is always read out. 16 32 read FIFWCNT Rewriting Start Register 0x4 32 read-write n ERASEMD Select Program/Erase function 1 2 read-write START Start Program/Erase function 0 1 read-write __reserve0 0 is always read out. 2 32 read FIHPRO0ENDD D-Flash HW Protect 0 End Address 0x34 32 read-write n HPRO0ENDD D-Flash HW protect 0 end address 0 32 read FIHPRO0ENDI I-Flash HW Protect 0 End Address 0x24 32 read-write n HPRO0ENDI I-Flash HW protect 0 end address 0 32 read FIHPRO0STRD D-Flash HW Protect 0 Start Address 0x30 32 read-write n HPRO0STRD D-Flash HW protect 0 start address 0 32 read FIHPRO0STRI I-Flash HW Protect 0 Start Address 0x20 32 read-write n HPRO0STRI I-Flash HW protect 0 start address 0 32 read FIHPRO1ENDD D-Flash HW Protect 1 End Address 0x3C 32 read-write n HPRO1ENDD D-Flash HW protect 1 end address 0 32 read FIHPRO1ENDI I-Flash HW Protect 1 End Address 0x2C 32 read-write n HPRO1ENDI I-Flash HW protect 1 end address 0 32 read FIHPRO1STRD D-Flash HW Protect 1 Start Address 0x38 32 read-write n HPRO1STRD D-Flash HW protect 1 start address 0 32 read FIHPRO1STRI I-Flash HW Protect 1 Start Address 0x28 32 read-write n HPRO1STRI I-Flash HW protect 1 start address 0 32 read FINSWAPREG Swap Switching Register 0xE0 32 read-write n KEY_CODE Register Key 8 16 read-write NSWAPON Boot sector swap setting 0 1 read-write __reserve0 0 is always read out. 1 8 read __reserve1 0 is always read out. 16 32 read FIPEADR Rewriting Destination Address Register 0xC 32 read-write n PEADR Rewriting (write/erase) address 0 32 read-write FISPROEND SW Protect End Address 0x1C 32 read-write n SPROEND SW protect end address 0 32 read-write FISPROSTR SW Protect Start Address 0x18 32 read-write n SPROSTR SW protect start address 0 32 read-write FIWDATA0 Writing Data Register 0 0x10 32 read-write n WDATA0 Set the data to be written to the flash memory. This is the lower 4 bytes of the data to be rewritten (8 bytes). 0 32 read-write FIWDATA1 Writing Data Register 1 0x14 32 read-write n WDATA1 Set the data to be written to the flash memory. This is the upper 4 bytes of the data to be rewritten (8 bytes). 0 32 read-write INTC Interrupt Controller INTC 0x0 0x0 0x20016 registers n G0 0 G1 1 G2 2 G3 3 G4 4 G5 5 G6 6 G7 7 G8 8 G9 9 G10 10 G11 11 G12 12 G13 13 G14 14 G15 15 G16 16 G17 17 G18 18 G19 19 INTCDETENCLR Condition Specification Interrupt Enable Clear Register 0x84 32 read-write n ENCLR0 Group 0 interrupt enable clear bit 0 1 read-write ENCLR1 Group 1 interrupt enable clear bit 1 2 read-write ENCLR10 Group 10 interrupt enable clear bit 10 11 read-write ENCLR11 Group 11 interrupt enable clear bit 11 12 read-write ENCLR12 Group 12 interrupt enable clear bit 12 13 read-write ENCLR13 Group 13 interrupt enable clear bit 13 14 read-write ENCLR14 Group 14 interrupt enable clear bit 14 15 read-write ENCLR15 Group 15 interrupt enable clear bit 15 16 read-write ENCLR16 Group 16 interrupt enable clear bit 16 17 read-write ENCLR17 Group 17 interrupt enable clear bit 17 18 read-write ENCLR18 Group 18 interrupt enable clear bit 18 19 read-write ENCLR19 Group 19 interrupt enable clear bit 19 20 read-write ENCLR2 Group 2 interrupt enable clear bit 2 3 read-write ENCLR20 Group 20 interrupt enable clear bit 20 21 read-write ENCLR21 Group 21 interrupt enable clear bit 21 22 read-write ENCLR22 Group 22 interrupt enable clear bit 22 23 read-write ENCLR23 Group 23 interrupt enable clear bit 23 24 read-write ENCLR24 Group 24 interrupt enable clear bit 24 25 read-write ENCLR25 Group 25 interrupt enable clear bit 25 26 read-write ENCLR26 Group 26 interrupt enable clear bit 26 27 read-write ENCLR27 Group 27 interrupt enable clear bit 27 28 read-write ENCLR28 Group 28 interrupt enable clear bit 28 29 read-write ENCLR29 Group 29 interrupt enable clear bit 29 30 read-write ENCLR3 Group 3 interrupt enable clear bit 3 4 read-write ENCLR30 Group 30 interrupt enable clear bit 30 31 read-write ENCLR4 Group 4 interrupt enable clear bit 4 5 read-write ENCLR5 Group 5 interrupt enable clear bit 5 6 read-write ENCLR6 Group 6 interrupt enable clear bit 6 7 read-write ENCLR7 Group 7 interrupt enable clear bit 7 8 read-write ENCLR8 Group 8 interrupt enable clear bit 8 9 read-write ENCLR9 Group 9 interrupt enable clear bit 9 10 read-write __reserve0 This bit must be set to 0 . 31 32 read-write INTCDETENSET Condition Specification Interrupt Enable Set Register 0x80 32 read-write n ENSET0 Group 0 interrupt enable set bit 0 1 read-write ENSET1 Group 1 interrupt enable set bit 1 2 read-write ENSET10 Group 10 interrupt enable set bit 10 11 read-write ENSET11 Group 11 interrupt enable set bit 11 12 read-write ENSET12 Group 12 interrupt enable set bit 12 13 read-write ENSET13 Group 13 interrupt enable set bit 13 14 read-write ENSET14 Group 14 interrupt enable set bit 14 15 read-write ENSET15 Group 15 interrupt enable set bit 15 16 read-write ENSET16 Group 16 interrupt enable set bit 16 17 read-write ENSET17 Group 17 interrupt enable set bit 17 18 read-write ENSET18 Group 18 interrupt enable set bit 18 19 read-write ENSET19 Group 19 interrupt enable set bit 19 20 read-write ENSET2 Group 2 interrupt enable set bit 2 3 read-write ENSET20 Group 20 interrupt enable set bit 20 21 read-write ENSET21 Group 21 interrupt enable set bit 21 22 read-write ENSET22 Group 22 interrupt enable set bit 22 23 read-write ENSET23 Group 23 interrupt enable set bit 23 24 read-write ENSET24 Group 24 interrupt enable set bit 24 25 read-write ENSET25 Group 25 interrupt enable set bit 25 26 read-write ENSET26 Group 26 interrupt enable set bit 26 27 read-write ENSET27 Group 27 interrupt enable set bit 27 28 read-write ENSET28 Group 28 interrupt enable set bit 28 29 read-write ENSET29 Group 29 interrupt enable set bit 29 30 read-write ENSET3 Group 3 interrupt enable set bit 3 4 read-write ENSET30 Group 30 interrupt enable set bit 30 31 read-write ENSET4 Group 4 interrupt enable set bit 4 5 read-write ENSET5 Group 5 interrupt enable set bit 5 6 read-write ENSET6 Group 6 interrupt enable set bit 6 7 read-write ENSET7 Group 7 interrupt enable set bit 7 8 read-write ENSET8 Group 8 interrupt enable set bit 8 9 read-write ENSET9 Group 9 interrupt enable set bit 9 10 read-write __reserve0 This bit must be set to 0 . 31 32 read-write INTCG0DETMD Group 0 I0terrupt Co0ditio0 Specify Register 0x0 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG100ID Group 100 I100terrupt Detectio100 Register 0x1290 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG100IECLR Group 100 I100terrupt E100able Clear Register 0xE90 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG100IESET Group 100 I100terrupt E100able Set Register 0xA90 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG100IRCLR Group 100 I100terrupt Request Clear Register 0x690 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG100IRSET Group 100 I100terrupt Request Set Register 0x290 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG101ID Group 101 I101terrupt Detectio101 Register 0x1294 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG101IECLR Group 101 I101terrupt E101able Clear Register 0xE94 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG101IESET Group 101 I101terrupt E101able Set Register 0xA94 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG101IRCLR Group 101 I101terrupt Request Clear Register 0x694 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG101IRSET Group 101 I101terrupt Request Set Register 0x294 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG102ID Group 102 I102terrupt Detectio102 Register 0x1298 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG102IECLR Group 102 I102terrupt E102able Clear Register 0xE98 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG102IESET Group 102 I102terrupt E102able Set Register 0xA98 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG102IRCLR Group 102 I102terrupt Request Clear Register 0x698 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG102IRSET Group 102 I102terrupt Request Set Register 0x298 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG103ID Group 103 I103terrupt Detectio103 Register 0x129C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG103IECLR Group 103 I103terrupt E103able Clear Register 0xE9C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG103IESET Group 103 I103terrupt E103able Set Register 0xA9C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG103IRCLR Group 103 I103terrupt Request Clear Register 0x69C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG103IRSET Group 103 I103terrupt Request Set Register 0x29C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG104ID Group 104 I104terrupt Detectio104 Register 0x12A0 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG104IECLR Group 104 I104terrupt E104able Clear Register 0xEA0 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG104IESET Group 104 I104terrupt E104able Set Register 0xAA0 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG104IRCLR Group 104 I104terrupt Request Clear Register 0x6A0 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG104IRSET Group 104 I104terrupt Request Set Register 0x2A0 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG105ID Group 105 I105terrupt Detectio105 Register 0x12A4 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG105IECLR Group 105 I105terrupt E105able Clear Register 0xEA4 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG105IESET Group 105 I105terrupt E105able Set Register 0xAA4 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG105IRCLR Group 105 I105terrupt Request Clear Register 0x6A4 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG105IRSET Group 105 I105terrupt Request Set Register 0x2A4 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG106ID Group 106 I106terrupt Detectio106 Register 0x12A8 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG106IECLR Group 106 I106terrupt E106able Clear Register 0xEA8 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG106IESET Group 106 I106terrupt E106able Set Register 0xAA8 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG106IRCLR Group 106 I106terrupt Request Clear Register 0x6A8 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG106IRSET Group 106 I106terrupt Request Set Register 0x2A8 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG10DETMD Group 10 I10terrupt Co10ditio10 Specify Register 0x28 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG111ID Group 111 I111terrupt Detectio111 Register 0x12BC 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG111IECLR Group 111 I111terrupt E111able Clear Register 0xEBC 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG111IESET Group 111 I111terrupt E111able Set Register 0xABC 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG111IRCLR Group 111 I111terrupt Request Clear Register 0x6BC 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG111IRSET Group 111 I111terrupt Request Set Register 0x2BC 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG112ID Group 112 I112terrupt Detectio112 Register 0x12C0 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG112IECLR Group 112 I112terrupt E112able Clear Register 0xEC0 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG112IESET Group 112 I112terrupt E112able Set Register 0xAC0 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG112IRCLR Group 112 I112terrupt Request Clear Register 0x6C0 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG112IRSET Group 112 I112terrupt Request Set Register 0x2C0 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG115ID Group 115 I115terrupt Detectio115 Register 0x12CC 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG115IECLR Group 115 I115terrupt E115able Clear Register 0xECC 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG115IESET Group 115 I115terrupt E115able Set Register 0xACC 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG115IRCLR Group 115 I115terrupt Request Clear Register 0x6CC 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG115IRSET Group 115 I115terrupt Request Set Register 0x2CC 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG117ID Group 117 I117terrupt Detectio117 Register 0x12D4 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG117IECLR Group 117 I117terrupt E117able Clear Register 0xED4 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG117IESET Group 117 I117terrupt E117able Set Register 0xAD4 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG117IRCLR Group 117 I117terrupt Request Clear Register 0x6D4 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG117IRSET Group 117 I117terrupt Request Set Register 0x2D4 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG119ID Group 119 I119terrupt Detectio119 Register 0x12DC 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG119IECLR Group 119 I119terrupt E119able Clear Register 0xEDC 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG119IESET Group 119 I119terrupt E119able Set Register 0xADC 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG119IRCLR Group 119 I119terrupt Request Clear Register 0x6DC 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG119IRSET Group 119 I119terrupt Request Set Register 0x2DC 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG11DETMD Group 11 I11terrupt Co11ditio11 Specify Register 0x2C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG121ID Group 121 I121terrupt Detectio121 Register 0x12E4 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG121IECLR Group 121 I121terrupt E121able Clear Register 0xEE4 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG121IESET Group 121 I121terrupt E121able Set Register 0xAE4 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG121IRCLR Group 121 I121terrupt Request Clear Register 0x6E4 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG121IRSET Group 121 I121terrupt Request Set Register 0x2E4 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG123ID Group 123 I123terrupt Detectio123 Register 0x12EC 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG123IECLR Group 123 I123terrupt E123able Clear Register 0xEEC 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG123IESET Group 123 I123terrupt E123able Set Register 0xAEC 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG123IRCLR Group 123 I123terrupt Request Clear Register 0x6EC 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG123IRSET Group 123 I123terrupt Request Set Register 0x2EC 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG125ID Group 125 I125terrupt Detectio125 Register 0x12F4 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG125IECLR Group 125 I125terrupt E125able Clear Register 0xEF4 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG125IESET Group 125 I125terrupt E125able Set Register 0xAF4 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG125IRCLR Group 125 I125terrupt Request Clear Register 0x6F4 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG125IRSET Group 125 I125terrupt Request Set Register 0x2F4 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG126ID Group 126 I126terrupt Detectio126 Register 0x12F8 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG126IECLR Group 126 I126terrupt E126able Clear Register 0xEF8 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG126IESET Group 126 I126terrupt E126able Set Register 0xAF8 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG126IRCLR Group 126 I126terrupt Request Clear Register 0x6F8 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG126IRSET Group 126 I126terrupt Request Set Register 0x2F8 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG12DETMD Group 12 I12terrupt Co12ditio12 Specify Register 0x30 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG133ID Group 133 I133terrupt Detectio133 Register 0x1314 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG133IECLR Group 133 I133terrupt E133able Clear Register 0xF14 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG133IESET Group 133 I133terrupt E133able Set Register 0xB14 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG133IRCLR Group 133 I133terrupt Request Clear Register 0x714 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG133IRSET Group 133 I133terrupt Request Set Register 0x314 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG134ID Group 134 I134terrupt Detectio134 Register 0x1318 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG134IECLR Group 134 I134terrupt E134able Clear Register 0xF18 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG134IESET Group 134 I134terrupt E134able Set Register 0xB18 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG134IRCLR Group 134 I134terrupt Request Clear Register 0x718 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG134IRSET Group 134 I134terrupt Request Set Register 0x318 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG135ID Group 135 I135terrupt Detectio135 Register 0x131C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG135IECLR Group 135 I135terrupt E135able Clear Register 0xF1C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG135IESET Group 135 I135terrupt E135able Set Register 0xB1C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG135IRCLR Group 135 I135terrupt Request Clear Register 0x71C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG135IRSET Group 135 I135terrupt Request Set Register 0x31C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG137ID Group 137 I137terrupt Detectio137 Register 0x1324 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG137IECLR Group 137 I137terrupt E137able Clear Register 0xF24 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG137IESET Group 137 I137terrupt E137able Set Register 0xB24 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG137IRCLR Group 137 I137terrupt Request Clear Register 0x724 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG137IRSET Group 137 I137terrupt Request Set Register 0x324 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG139ID Group 139 I139terrupt Detectio139 Register 0x132C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG139IECLR Group 139 I139terrupt E139able Clear Register 0xF2C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG139IESET Group 139 I139terrupt E139able Set Register 0xB2C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG139IRCLR Group 139 I139terrupt Request Clear Register 0x72C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG139IRSET Group 139 I139terrupt Request Set Register 0x32C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG13DETMD Group 13 I13terrupt Co13ditio13 Specify Register 0x34 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG140ID Group 140 I140terrupt Detectio140 Register 0x1330 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG140IECLR Group 140 I140terrupt E140able Clear Register 0xF30 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG140IESET Group 140 I140terrupt E140able Set Register 0xB30 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG140IRCLR Group 140 I140terrupt Request Clear Register 0x730 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG140IRSET Group 140 I140terrupt Request Set Register 0x330 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG144ID Group 144 I144terrupt Detectio144 Register 0x1340 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG144IECLR Group 144 I144terrupt E144able Clear Register 0xF40 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG144IESET Group 144 I144terrupt E144able Set Register 0xB40 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG144IRCLR Group 144 I144terrupt Request Clear Register 0x740 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG144IRSET Group 144 I144terrupt Request Set Register 0x340 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG145ID Group 145 I145terrupt Detectio145 Register 0x1344 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG145IECLR Group 145 I145terrupt E145able Clear Register 0xF44 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG145IESET Group 145 I145terrupt E145able Set Register 0xB44 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG145IRCLR Group 145 I145terrupt Request Clear Register 0x744 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG145IRSET Group 145 I145terrupt Request Set Register 0x344 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG146ID Group 146 I146terrupt Detectio146 Register 0x1348 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG146IECLR Group 146 I146terrupt E146able Clear Register 0xF48 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG146IESET Group 146 I146terrupt E146able Set Register 0xB48 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG146IRCLR Group 146 I146terrupt Request Clear Register 0x748 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG146IRSET Group 146 I146terrupt Request Set Register 0x348 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG147ID Group 147 I147terrupt Detectio147 Register 0x134C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG147IECLR Group 147 I147terrupt E147able Clear Register 0xF4C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG147IESET Group 147 I147terrupt E147able Set Register 0xB4C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG147IRCLR Group 147 I147terrupt Request Clear Register 0x74C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG147IRSET Group 147 I147terrupt Request Set Register 0x34C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG148ID Group 148 I148terrupt Detectio148 Register 0x1350 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG148IECLR Group 148 I148terrupt E148able Clear Register 0xF50 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG148IESET Group 148 I148terrupt E148able Set Register 0xB50 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG148IRCLR Group 148 I148terrupt Request Clear Register 0x750 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG148IRSET Group 148 I148terrupt Request Set Register 0x350 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG149ID Group 149 I149terrupt Detectio149 Register 0x1354 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG149IECLR Group 149 I149terrupt E149able Clear Register 0xF54 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG149IESET Group 149 I149terrupt E149able Set Register 0xB54 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG149IRCLR Group 149 I149terrupt Request Clear Register 0x754 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG149IRSET Group 149 I149terrupt Request Set Register 0x354 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG14DETMD Group 14 I14terrupt Co14ditio14 Specify Register 0x38 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG150ID Group 150 I150terrupt Detectio150 Register 0x1358 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG150IECLR Group 150 I150terrupt E150able Clear Register 0xF58 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG150IESET Group 150 I150terrupt E150able Set Register 0xB58 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG150IRCLR Group 150 I150terrupt Request Clear Register 0x758 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG150IRSET Group 150 I150terrupt Request Set Register 0x358 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG151ID Group 151 I151terrupt Detectio151 Register 0x135C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG151IECLR Group 151 I151terrupt E151able Clear Register 0xF5C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG151IESET Group 151 I151terrupt E151able Set Register 0xB5C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG151IRCLR Group 151 I151terrupt Request Clear Register 0x75C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG151IRSET Group 151 I151terrupt Request Set Register 0x35C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG152ID Group 152 I152terrupt Detectio152 Register 0x1360 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG152IECLR Group 152 I152terrupt E152able Clear Register 0xF60 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG152IESET Group 152 I152terrupt E152able Set Register 0xB60 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG152IRCLR Group 152 I152terrupt Request Clear Register 0x760 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG152IRSET Group 152 I152terrupt Request Set Register 0x360 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG153ID Group 153 I153terrupt Detectio153 Register 0x1364 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG153IECLR Group 153 I153terrupt E153able Clear Register 0xF64 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG153IESET Group 153 I153terrupt E153able Set Register 0xB64 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG153IRCLR Group 153 I153terrupt Request Clear Register 0x764 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG153IRSET Group 153 I153terrupt Request Set Register 0x364 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG154ID Group 154 I154terrupt Detectio154 Register 0x1368 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG154IECLR Group 154 I154terrupt E154able Clear Register 0xF68 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG154IESET Group 154 I154terrupt E154able Set Register 0xB68 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG154IRCLR Group 154 I154terrupt Request Clear Register 0x768 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG154IRSET Group 154 I154terrupt Request Set Register 0x368 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG15DETMD Group 15 I15terrupt Co15ditio15 Specify Register 0x3C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG16DETMD Group 16 I16terrupt Co16ditio16 Specify Register 0x40 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG17DETMD Group 17 I17terrupt Co17ditio17 Specify Register 0x44 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG18DETMD Group 18 I18terrupt Co18ditio18 Specify Register 0x48 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG19DETMD Group 19 I19terrupt Co19ditio19 Specify Register 0x4C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG1DETMD Group 1 I1terrupt Co1ditio1 Specify Register 0x4 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG20DETMD Group 20 I20terrupt Co20ditio20 Specify Register 0x50 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG21DETMD Group 21 I21terrupt Co21ditio21 Specify Register 0x54 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG22DETMD Group 22 I22terrupt Co22ditio22 Specify Register 0x58 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG23DETMD Group 23 I23terrupt Co23ditio23 Specify Register 0x5C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG24DETMD Group 24 I24terrupt Co24ditio24 Specify Register 0x60 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG25DETMD Group 25 I25terrupt Co25ditio25 Specify Register 0x64 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG26DETMD Group 26 I26terrupt Co26ditio26 Specify Register 0x68 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG27DETMD Group 27 I27terrupt Co27ditio27 Specify Register 0x6C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG28DETMD Group 28 I28terrupt Co28ditio28 Specify Register 0x70 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG29DETMD Group 29 I29terrupt Co29ditio29 Specify Register 0x74 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG2DETMD Group 2 I2terrupt Co2ditio2 Specify Register 0x8 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG30DETMD Group 30 I30terrupt Co30ditio30 Specify Register 0x78 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG31ID Group 31 I31terrupt Detectio31 Register 0x117C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG31IECLR Group 31 I31terrupt E31able Clear Register 0xD7C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG31IESET Group 31 I31terrupt E31able Set Register 0x97C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG31IRCLR Group 31 I31terrupt Request Clear Register 0x57C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG31IRSET Group 31 I31terrupt Request Set Register 0x17C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG32ID Group 32 I32terrupt Detectio32 Register 0x1180 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG32IECLR Group 32 I32terrupt E32able Clear Register 0xD80 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG32IESET Group 32 I32terrupt E32able Set Register 0x980 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG32IRCLR Group 32 I32terrupt Request Clear Register 0x580 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG32IRSET Group 32 I32terrupt Request Set Register 0x180 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG33ID Group 33 I33terrupt Detectio33 Register 0x1184 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG33IECLR Group 33 I33terrupt E33able Clear Register 0xD84 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG33IESET Group 33 I33terrupt E33able Set Register 0x984 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG33IRCLR Group 33 I33terrupt Request Clear Register 0x584 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG33IRSET Group 33 I33terrupt Request Set Register 0x184 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG34ID Group 34 I34terrupt Detectio34 Register 0x1188 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG34IECLR Group 34 I34terrupt E34able Clear Register 0xD88 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG34IESET Group 34 I34terrupt E34able Set Register 0x988 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG34IRCLR Group 34 I34terrupt Request Clear Register 0x588 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG34IRSET Group 34 I34terrupt Request Set Register 0x188 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG35ID Group 35 I35terrupt Detectio35 Register 0x118C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG35IECLR Group 35 I35terrupt E35able Clear Register 0xD8C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG35IESET Group 35 I35terrupt E35able Set Register 0x98C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG35IRCLR Group 35 I35terrupt Request Clear Register 0x58C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG35IRSET Group 35 I35terrupt Request Set Register 0x18C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG3DETMD Group 3 I3terrupt Co3ditio3 Specify Register 0xC 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG4DETMD Group 4 I4terrupt Co4ditio4 Specify Register 0x10 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG5DETMD Group 5 I5terrupt Co5ditio5 Specify Register 0x14 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG6DETMD Group 6 I6terrupt Co6ditio6 Specify Register 0x18 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG7DETMD Group 7 I7terrupt Co7ditio7 Specify Register 0x1C 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG80ID Group 80 I80terrupt Detectio80 Register 0x1240 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG80IECLR Group 80 I80terrupt E80able Clear Register 0xE40 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG80IESET Group 80 I80terrupt E80able Set Register 0xA40 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG80IRCLR Group 80 I80terrupt Request Clear Register 0x640 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG80IRSET Group 80 I80terrupt Request Set Register 0x240 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG87ID Group 87 I87terrupt Detectio87 Register 0x125C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG87IECLR Group 87 I87terrupt E87able Clear Register 0xE5C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG87IESET Group 87 I87terrupt E87able Set Register 0xA5C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG87IRCLR Group 87 I87terrupt Request Clear Register 0x65C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG87IRSET Group 87 I87terrupt Request Set Register 0x25C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG88ID Group 88 I88terrupt Detectio88 Register 0x1260 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG88IECLR Group 88 I88terrupt E88able Clear Register 0xE60 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG88IESET Group 88 I88terrupt E88able Set Register 0xA60 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG88IRCLR Group 88 I88terrupt Request Clear Register 0x660 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG88IRSET Group 88 I88terrupt Request Set Register 0x260 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG89ID Group 89 I89terrupt Detectio89 Register 0x1264 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG89IECLR Group 89 I89terrupt E89able Clear Register 0xE64 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG89IESET Group 89 I89terrupt E89able Set Register 0xA64 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG89IRCLR Group 89 I89terrupt Request Clear Register 0x664 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG89IRSET Group 89 I89terrupt Request Set Register 0x264 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG8DETMD Group 8 I8terrupt Co8ditio8 Specify Register 0x20 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCG90ID Group 90 I90terrupt Detectio90 Register 0x1268 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG90IECLR Group 90 I90terrupt E90able Clear Register 0xE68 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG90IESET Group 90 I90terrupt E90able Set Register 0xA68 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG90IRCLR Group 90 I90terrupt Request Clear Register 0x668 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG90IRSET Group 90 I90terrupt Request Set Register 0x268 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG91ID Group 91 I91terrupt Detectio91 Register 0x126C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG91IECLR Group 91 I91terrupt E91able Clear Register 0xE6C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG91IESET Group 91 I91terrupt E91able Set Register 0xA6C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG91IRCLR Group 91 I91terrupt Request Clear Register 0x66C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG91IRSET Group 91 I91terrupt Request Set Register 0x26C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG92ID Group 92 I92terrupt Detectio92 Register 0x1270 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG92IECLR Group 92 I92terrupt E92able Clear Register 0xE70 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG92IESET Group 92 I92terrupt E92able Set Register 0xA70 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG92IRCLR Group 92 I92terrupt Request Clear Register 0x670 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG92IRSET Group 92 I92terrupt Request Set Register 0x270 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG93ID Group 93 I93terrupt Detectio93 Register 0x1274 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG93IECLR Group 93 I93terrupt E93able Clear Register 0xE74 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG93IESET Group 93 I93terrupt E93able Set Register 0xA74 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG93IRCLR Group 93 I93terrupt Request Clear Register 0x674 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG93IRSET Group 93 I93terrupt Request Set Register 0x274 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG94ID Group 94 I94terrupt Detectio94 Register 0x1278 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG94IECLR Group 94 I94terrupt E94able Clear Register 0xE78 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG94IESET Group 94 I94terrupt E94able Set Register 0xA78 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG94IRCLR Group 94 I94terrupt Request Clear Register 0x678 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG94IRSET Group 94 I94terrupt Request Set Register 0x278 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG95ID Group 95 I95terrupt Detectio95 Register 0x127C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG95IECLR Group 95 I95terrupt E95able Clear Register 0xE7C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG95IESET Group 95 I95terrupt E95able Set Register 0xA7C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG95IRCLR Group 95 I95terrupt Request Clear Register 0x67C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG95IRSET Group 95 I95terrupt Request Set Register 0x27C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG96ID Group 96 I96terrupt Detectio96 Register 0x1280 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG96IECLR Group 96 I96terrupt E96able Clear Register 0xE80 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG96IESET Group 96 I96terrupt E96able Set Register 0xA80 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG96IRCLR Group 96 I96terrupt Request Clear Register 0x680 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG96IRSET Group 96 I96terrupt Request Set Register 0x280 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG97ID Group 97 I97terrupt Detectio97 Register 0x1284 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG97IECLR Group 97 I97terrupt E97able Clear Register 0xE84 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG97IESET Group 97 I97terrupt E97able Set Register 0xA84 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG97IRCLR Group 97 I97terrupt Request Clear Register 0x684 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG97IRSET Group 97 I97terrupt Request Set Register 0x284 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG98ID Group 98 I98terrupt Detectio98 Register 0x1288 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG98IECLR Group 98 I98terrupt E98able Clear Register 0xE88 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG98IESET Group 98 I98terrupt E98able Set Register 0xA88 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG98IRCLR Group 98 I98terrupt Request Clear Register 0x688 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG98IRSET Group 98 I98terrupt Request Set Register 0x288 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG99ID Group 99 I99terrupt Detectio99 Register 0x128C 32 read-write n ID0 The logical AND of GnIE[0] and GnIR[0] is read out. 0 1 read ID1 The logical AND of GnIE[1] and GnIR[1] is read out. 1 2 read ID10 The logical AND of GnIE[10] and GnIR[10] is read out. 10 11 read ID11 The logical AND of GnIE[11] and GnIR[11] is read out. 11 12 read ID12 The logical AND of GnIE[12] and GnIR[12] is read out. 12 13 read ID13 The logical AND of GnIE[13] and GnIR[13] is read out. 13 14 read ID14 The logical AND of GnIE[14] and GnIR[14] is read out. 14 15 read ID15 The logical AND of GnIE[15] and GnIR[15] is read out. 15 16 read ID16 The logical AND of GnIE[16] and GnIR[16] is read out. 16 17 read ID17 The logical AND of GnIE[17] and GnIR[17] is read out. 17 18 read ID18 The logical AND of GnIE[18] and GnIR[18] is read out. 18 19 read ID19 The logical AND of GnIE[19] and GnIR[19] is read out. 19 20 read ID2 The logical AND of GnIE[2] and GnIR[2] is read out. 2 3 read ID20 The logical AND of GnIE[20] and GnIR[20] is read out. 20 21 read ID21 The logical AND of GnIE[21] and GnIR[21] is read out. 21 22 read ID22 The logical AND of GnIE[22] and GnIR[22] is read out. 22 23 read ID23 The logical AND of GnIE[23] and GnIR[23] is read out. 23 24 read ID24 The logical AND of GnIE[24] and GnIR[24] is read out. 24 25 read ID25 The logical AND of GnIE[25] and GnIR[25] is read out. 25 26 read ID26 The logical AND of GnIE[26] and GnIR[26] is read out. 26 27 read ID27 The logical AND of GnIE[27] and GnIR[27] is read out. 27 28 read ID28 The logical AND of GnIE[28] and GnIR[28] is read out. 28 29 read ID29 The logical AND of GnIE[29] and GnIR[29] is read out. 29 30 read ID3 The logical AND of GnIE[3] and GnIR[3] is read out. 3 4 read ID30 The logical AND of GnIE[30] and GnIR[30] is read out. 30 31 read ID31 The logical AND of GnIE[31] and GnIR[31] is read out. 31 32 read ID4 The logical AND of GnIE[4] and GnIR[4] is read out. 4 5 read ID5 The logical AND of GnIE[5] and GnIR[5] is read out. 5 6 read ID6 The logical AND of GnIE[6] and GnIR[6] is read out. 6 7 read ID7 The logical AND of GnIE[7] and GnIR[7] is read out. 7 8 read ID8 The logical AND of GnIE[8] and GnIR[8] is read out. 8 9 read ID9 The logical AND of GnIE[9] and GnIR[9] is read out. 9 10 read INTCG99IECLR Group 99 I99terrupt E99able Clear Register 0xE8C 32 read-write n IECLR0 GnIRQ No.0 interrupt enable clear bit 0 1 read-write IECLR1 GnIRQ No.1 interrupt enable clear bit 1 2 read-write IECLR10 GnIRQ No.10 interrupt enable clear bit 10 11 read-write IECLR11 GnIRQ No.11 interrupt enable clear bit 11 12 read-write IECLR12 GnIRQ No.12 interrupt enable clear bit 12 13 read-write IECLR13 GnIRQ No.13 interrupt enable clear bit 13 14 read-write IECLR14 GnIRQ No.14 interrupt enable clear bit 14 15 read-write IECLR15 GnIRQ No.15 interrupt enable clear bit 15 16 read-write IECLR16 GnIRQ No.16 interrupt enable clear bit 16 17 read-write IECLR17 GnIRQ No.17 interrupt enable clear bit 17 18 read-write IECLR18 GnIRQ No.18 interrupt enable clear bit 18 19 read-write IECLR19 GnIRQ No.19 interrupt enable clear bit 19 20 read-write IECLR2 GnIRQ No.2 interrupt enable clear bit 2 3 read-write IECLR20 GnIRQ No.20 interrupt enable clear bit 20 21 read-write IECLR21 GnIRQ No.21 interrupt enable clear bit 21 22 read-write IECLR22 GnIRQ No.22 interrupt enable clear bit 22 23 read-write IECLR23 GnIRQ No.23 interrupt enable clear bit 23 24 read-write IECLR24 GnIRQ No.24 interrupt enable clear bit 24 25 read-write IECLR25 GnIRQ No.25 interrupt enable clear bit 25 26 read-write IECLR26 GnIRQ No.26 interrupt enable clear bit 26 27 read-write IECLR27 GnIRQ No.27 interrupt enable clear bit 27 28 read-write IECLR28 GnIRQ No.28 interrupt enable clear bit 28 29 read-write IECLR29 GnIRQ No.29 interrupt enable clear bit 29 30 read-write IECLR3 GnIRQ No.3 interrupt enable clear bit 3 4 read-write IECLR30 GnIRQ No.30 interrupt enable clear bit 30 31 read-write IECLR31 GnIRQ No.31 interrupt enable clear bit 31 32 read-write IECLR4 GnIRQ No.4 interrupt enable clear bit 4 5 read-write IECLR5 GnIRQ No.5 interrupt enable clear bit 5 6 read-write IECLR6 GnIRQ No.6 interrupt enable clear bit 6 7 read-write IECLR7 GnIRQ No.7 interrupt enable clear bit 7 8 read-write IECLR8 GnIRQ No.8 interrupt enable clear bit 8 9 read-write IECLR9 GnIRQ No.9 interrupt enable clear bit 9 10 read-write INTCG99IESET Group 99 I99terrupt E99able Set Register 0xA8C 32 read-write n IESET0 GnIRQ No.0 interrupt enable set bit 0 1 read-write IESET1 GnIRQ No.1 interrupt enable set bit 1 2 read-write IESET10 GnIRQ No.10 interrupt enable set bit 10 11 read-write IESET11 GnIRQ No.11 interrupt enable set bit 11 12 read-write IESET12 GnIRQ No.12 interrupt enable set bit 12 13 read-write IESET13 GnIRQ No.13 interrupt enable set bit 13 14 read-write IESET14 GnIRQ No.14 interrupt enable set bit 14 15 read-write IESET15 GnIRQ No.15 interrupt enable set bit 15 16 read-write IESET16 GnIRQ No.16 interrupt enable set bit 16 17 read-write IESET17 GnIRQ No.17 interrupt enable set bit 17 18 read-write IESET18 GnIRQ No.18 interrupt enable set bit 18 19 read-write IESET19 GnIRQ No.19 interrupt enable set bit 19 20 read-write IESET2 GnIRQ No.2 interrupt enable set bit 2 3 read-write IESET20 GnIRQ No.20 interrupt enable set bit 20 21 read-write IESET21 GnIRQ No.21 interrupt enable set bit 21 22 read-write IESET22 GnIRQ No.22 interrupt enable set bit 22 23 read-write IESET23 GnIRQ No.23 interrupt enable set bit 23 24 read-write IESET24 GnIRQ No.24 interrupt enable set bit 24 25 read-write IESET25 GnIRQ No.25 interrupt enable set bit 25 26 read-write IESET26 GnIRQ No.26 interrupt enable set bit 26 27 read-write IESET27 GnIRQ No.27 interrupt enable set bit 27 28 read-write IESET28 GnIRQ No.28 interrupt enable set bit 28 29 read-write IESET29 GnIRQ No.29 interrupt enable set bit 29 30 read-write IESET3 GnIRQ No.3 interrupt enable set bit 3 4 read-write IESET30 GnIRQ No.30 interrupt enable set bit 30 31 read-write IESET31 GnIRQ No.31 interrupt enable set bit 31 32 read-write IESET4 GnIRQ No.4 interrupt enable set bit 4 5 read-write IESET5 GnIRQ No.5 interrupt enable set bit 5 6 read-write IESET6 GnIRQ No.6 interrupt enable set bit 6 7 read-write IESET7 GnIRQ No.7 interrupt enable set bit 7 8 read-write IESET8 GnIRQ No.8 interrupt enable set bit 8 9 read-write IESET9 GnIRQ No.9 interrupt enable set bit 9 10 read-write INTCG99IRCLR Group 99 I99terrupt Request Clear Register 0x68C 32 read-write n IRCLR0 GnIRQ No.0 interrupt request clear bit 0 1 read-write IRCLR1 GnIRQ No.1 interrupt request clear bit 1 2 read-write IRCLR10 GnIRQ No.10 interrupt request clear bit 10 11 read-write IRCLR11 GnIRQ No.11 interrupt request clear bit 11 12 read-write IRCLR12 GnIRQ No.12 interrupt request clear bit 12 13 read-write IRCLR13 GnIRQ No.13 interrupt request clear bit 13 14 read-write IRCLR14 GnIRQ No.14 interrupt request clear bit 14 15 read-write IRCLR15 GnIRQ No.15 interrupt request clear bit 15 16 read-write IRCLR16 GnIRQ No.16 interrupt request clear bit 16 17 read-write IRCLR17 GnIRQ No.17 interrupt request clear bit 17 18 read-write IRCLR18 GnIRQ No.18 interrupt request clear bit 18 19 read-write IRCLR19 GnIRQ No.19 interrupt request clear bit 19 20 read-write IRCLR2 GnIRQ No.2 interrupt request clear bit 2 3 read-write IRCLR20 GnIRQ No.20 interrupt request clear bit 20 21 read-write IRCLR21 GnIRQ No.21 interrupt request clear bit 21 22 read-write IRCLR22 GnIRQ No.22 interrupt request clear bit 22 23 read-write IRCLR23 GnIRQ No.23 interrupt request clear bit 23 24 read-write IRCLR24 GnIRQ No.24 interrupt request clear bit 24 25 read-write IRCLR25 GnIRQ No.25 interrupt request clear bit 25 26 read-write IRCLR26 GnIRQ No.26 interrupt request clear bit 26 27 read-write IRCLR27 GnIRQ No.27 interrupt request clear bit 27 28 read-write IRCLR28 GnIRQ No.28 interrupt request clear bit 28 29 read-write IRCLR29 GnIRQ No.29 interrupt request clear bit 29 30 read-write IRCLR3 GnIRQ No.3 interrupt request clear bit 3 4 read-write IRCLR30 GnIRQ No.30 interrupt request clear bit 30 31 read-write IRCLR31 GnIRQ No.31 interrupt request clear bit 31 32 read-write IRCLR4 GnIRQ No.4 interrupt request clear bit 4 5 read-write IRCLR5 GnIRQ No.5 interrupt request clear bit 5 6 read-write IRCLR6 GnIRQ No.6 interrupt request clear bit 6 7 read-write IRCLR7 GnIRQ No.7 interrupt request clear bit 7 8 read-write IRCLR8 GnIRQ No.8 interrupt request clear bit 8 9 read-write IRCLR9 GnIRQ No.9 interrupt request clear bit 9 10 read-write INTCG99IRSET Group 99 I99terrupt Request Set Register 0x28C 32 read-write n IRSET0 GnIRQ No.0 interrupt request set bit 0 1 read-write IRSET1 GnIRQ No.1 interrupt request set bit 1 2 read-write IRSET10 GnIRQ No.10 interrupt request set bit 10 11 read-write IRSET11 GnIRQ No.11 interrupt request set bit 11 12 read-write IRSET12 GnIRQ No.12 interrupt request set bit 12 13 read-write IRSET13 GnIRQ No.13 interrupt request set bit 13 14 read-write IRSET14 GnIRQ No.14 interrupt request set bit 14 15 read-write IRSET15 GnIRQ No.15 interrupt request set bit 15 16 read-write IRSET16 GnIRQ No.16 interrupt request set bit 16 17 read-write IRSET17 GnIRQ No.17 interrupt request set bit 17 18 read-write IRSET18 GnIRQ No.18 interrupt request set bit 18 19 read-write IRSET19 GnIRQ No.19 interrupt request set bit 19 20 read-write IRSET2 GnIRQ No.2 interrupt request set bit 2 3 read-write IRSET20 GnIRQ No.20 interrupt request set bit 20 21 read-write IRSET21 GnIRQ No.21 interrupt request set bit 21 22 read-write IRSET22 GnIRQ No.22 interrupt request set bit 22 23 read-write IRSET23 GnIRQ No.23 interrupt request set bit 23 24 read-write IRSET24 GnIRQ No.24 interrupt request set bit 24 25 read-write IRSET25 GnIRQ No.25 interrupt request set bit 25 26 read-write IRSET26 GnIRQ No.26 interrupt request set bit 26 27 read-write IRSET27 GnIRQ No.27 interrupt request set bit 27 28 read-write IRSET28 GnIRQ No.28 interrupt request set bit 28 29 read-write IRSET29 GnIRQ No.29 interrupt request set bit 29 30 read-write IRSET3 GnIRQ No.3 interrupt request set bit 3 4 read-write IRSET30 GnIRQ No.30 interrupt request set bit 30 31 read-write IRSET31 GnIRQ No.31 interrupt request set bit 31 32 read-write IRSET4 GnIRQ No.4 interrupt request set bit 4 5 read-write IRSET5 GnIRQ No.5 interrupt request set bit 5 6 read-write IRSET6 GnIRQ No.6 interrupt request set bit 6 7 read-write IRSET7 GnIRQ No.7 interrupt request set bit 7 8 read-write IRSET8 GnIRQ No.8 interrupt request set bit 8 9 read-write IRSET9 GnIRQ No.9 interrupt request set bit 9 10 read-write INTCG9DETMD Group 9 I9terrupt Co9ditio9 Specify Register 0x24 8 read-write n IRQEG Both edge detect selection 2 3 read-write IRQTG External interrupt n trigger settings 0 2 read-write __reserve0 This bit must be set to 0 . 3 8 read-write INTCGNMIRCLR Group Non-maskable Interrupt Request Clear Register 0x1504 32 read-write n IRCLR0 Watchdog timer error detection interrupt request clear bit 0 1 read-write IRCLR1 Clock error detection interrupt request clear bit 1 2 read-write __reserve0 0 is always read out. 2 32 read INTCGNMIRSET Group Non-maskable Interrupt Request Set Register 0x1500 32 read-write n IRSET0 Watchdog timer error detection interrupt request set bit 0 1 read-write IRSET1 Clock error detection interrupt request set bit 1 2 read-write __reserve0 0 is always read out. 2 32 read PFLPSELA Pin Protection Factor Trigger Selection Register A 0x20000 16 read-write n IRQ00PSEL External interrupt 00 detect polarity selection 0 1 read-write IRQ01PSEL External interrupt 01 detect polarity selection 1 2 read-write IRQ08PSEL External interrupt 08 detect polarity selection 2 3 read-write IRQ09PSEL External interrupt 09 detect polarity selection 3 4 read-write IRQ14PSEL External interrupt 14 detect polarity selection 4 5 read-write IRQ15PSEL External interrupt 15 detect polarity selection 5 6 read-write IRQ18PSEL External interrupt 18 detect polarity selection 6 7 read-write IRQ19PSEL External interrupt 19 detect polarity selection 7 8 read-write __reserve0 0 is always read out. 8 16 read PFLPSELB Pin Protection Factor Trigger Selection Register B 0x20002 16 read-write n CMP00PSEL Comparator 00 detect polarity selection 0 1 read-write CMP01PSEL Comparator 01 detect polarity selection 1 2 read-write CMP10PSEL Comparator 10 detect polarity selection 2 3 read-write CMP11PSEL Comparator 11 detect polarity selection 3 4 read-write CMP20PSEL Comparator 20 detect polarity selection 4 5 read-write CMP21PSEL Comparator 21 detect polarity selection 5 6 read-write CMP30PSEL Comparator 30 detect polarity selection 6 7 read-write CMP31PSEL Comparator 31 detect polarity selection 7 8 read-write CMP40PSEL Comparator 40 detect polarity selection 8 9 read-write CMP41PSEL Comparator 41 detect polarity selection 9 10 read-write __reserve0 0 is always read out. 10 16 read PFLSTATA Pin Protection Trigger Detection Register A 0x20010 16 read-write n IRQ00DET External interrupt 00 detection state 0 1 read-write IRQ01DET External interrupt 01 detection state 1 2 read-write IRQ08DET External interrupt 08 detection state 2 3 read-write IRQ09DET External interrupt 09 detection state 3 4 read-write IRQ14DET External interrupt 14 detection state 4 5 read-write IRQ15DET External interrupt 15 detection state 5 6 read-write IRQ18DET External interrupt 18 detection state 6 7 read-write IRQ19DET External interrupt 19 detection state 7 8 read-write __reserve0 0 is always read out. 8 16 read PFLSTATB Pin Protection Trigger Detection Register B 0x20012 16 read-write n AD0ERRADET Detection state of A/D0 conversion error detection 10 11 read-write AD0ERRBDET Detection state of A/D0 conversion error detection B 11 12 read-write AD1ERRADET Detection state of A/D1 conversion error detection 12 13 read-write AD1ERRBDET Detection state of A/D1 conversion error detection B 13 14 read-write AD2ERRADET Detection state of A/D2 conversion error detection 14 15 read-write AD2ERRBDET Detection state of A/D2 conversion error detection B 15 16 read-write CMP00PSEL Detection state of comparator 00 detection 0 1 read-write CMP01PSEL Detection state of comparator 01 detection 1 2 read-write CMP10PSEL Detection state of comparator 10 detection 2 3 read-write CMP11PSEL Detection state of comparator 11 detection 3 4 read-write CMP20PSEL Detection state of comparator 20 detection 4 5 read-write CMP21PSEL Detection state of comparator 21 detection 5 6 read-write CMP30PSEL Detection state of comparator 30 detection 6 7 read-write CMP31PSEL Detection state of comparator 31 detection 7 8 read-write CMP40PSEL Detection state of comparator 40 detection 8 9 read-write CMP41PSEL Detection state of comparator 41 detection 9 10 read-write LIN lin LIN 0x0 0x0 0xD registers n G114 114 LINERRSTAT LIN Error Status Register 0x4 8 read-write n BITERR Bit error detection(*3) 0 1 read CHKSERR Check sum error detection(*1)(*2) 2 3 read __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 3 8 read LINRXCHKS LIN Reception Check sum Register 0x9 8 read-write n RXCHKS Check sum value for the reception data is read out. 0 8 read LINRXCTR LIN Reception Control Register 0x1 8 read-write n LINEN LIN communication enable 0 1 read-write RXCHSST Check sum operation for reception 5 6 read-write SBFBSY Synch Break field reception busy 3 4 read SBFREC Wake up signal and Synch Break field reception enable 1 2 read-write SFBSY Synch field reception busy 4 5 read SFREC Synch field reception enable 2 3 read-write TMIOSEL Selection of clock source for Timer 0 7 8 read-write __reserve0 This bit must be set to 0 . 6 7 read-write LINTXCHKS LIN Transmission Check sum Register 0x8 8 read-write n TXCHKS Check sum value for the transmission data is read out. 0 8 read LINTXCTR LIN Transmission Control Register 0x0 8 read-write n BITERREN Bit error detection function selection 5 6 read-write SBFEN Synch Break field transmission trigger/monitor(*1) 3 4 read-write SBFSEL Synch Break field transmission width selection 0 3 read-write TXCHSST Check sum operation for transmission 4 5 read-write __reserve0 0 is always read out. 6 8 read MAP RAM-ECC MAP 0x0 0x0 0x60 registers n TCMD0MBEA D0TCM 2-bit Error Address Register 0x20 32 read-write n MBEADD The 2-bit error or hard error address [D0TCM] 0 32 read TCMD0SBEA D0TCM 1-bit Error Address Register 0x10 32 read-write n SBEADD The 1-bit error address [D0TCM] 0 32 read TCMD1MBEA D1TCM 2-bit Error Address Register 0x24 32 read-write n MBEADD The 2-bit error or hard error address [D1TCM] 0 32 read TCMD1SBEA D1TCM 1-bit Error Address Register 0x14 32 read-write n SBEADD The 1-bit error address [D1TCM] 0 32 read TCMDCBEN D0TCM/D1TCM Check Bit Control Register 0x8 32 read-write n D0CBEN Check bit read/write enable [D0TCM] 0 1 read-write D1CBEN Check bit read/write enable [D1TCM] 1 2 read-write KEY_CODE When TCMDCBEN.KEY_CODE is set to 0x3CA5 , TCMDCBEN is updating. 16 32 read-write __reserve0 0 is always read out. 2 16 read TCMDECCCNT D0TCM/D1TCM ECC Control Register 0x0 32 read-write n ECCMOD ECC enable [D0TCM, D1TCM] 0 1 read-write KEY_CODE When TCMDECCCNT.KEY_CODE is set to 0x3CA5 , TCMDECCCNT is updating. 16 32 read-write __reserve0 0 is always read out. 1 16 read TCMDMBECLR D0TCM/D1TCM 2-bit Error Detection Clear Register 0x2C 8 read-write n D0MBECLR Clear the 2-bit error and hard error detection [D0TCM] 0 1 read-write D1MBECLR Clear the 2-bit error and hard error detection [D1TCM] 1 2 read-write __reserve0 0 is always read out. 2 3 read __reserve1 0 is always read out. 3 8 read TCMDMBEDET D0TCM/D1TCM 2-bit Error Detection Register 0x28 16 read-write n D0HDE Hard error detection bit [D0TCM] 1 2 read D0MASTER Memory access at 2-bit error [D0TCM] 4 8 read D0MBE 2-bit error detection bit [D0TCM] 0 1 read D1HDE Hard error detection bit [D1TCM] 9 10 read D1MASTER Memory access at 2-bit error[D1TCM] 12 16 read D1MBE 2-bit error detection bit [D1TCM] 8 9 read __reserve0 0 is always read out. 2 4 read __reserve1 0 is always read out. 10 12 read TCMDSBECLR D0TCM/D1TCM 1-bit Error Detection Clear Register 0x1C 8 read-write n D0SBECLR Clear the 1-bit error detection [D0TCM] 0 1 read-write D1SBECLR Clear the 1-bit error detection [D1TCM] 1 2 read-write __reserve0 0 is always read out. 2 8 read TCMDSBEDET D0TCM/D1TCM 1-bit Error Detection Register 0x18 16 read-write n D0MASTER Memory access at 1-bit error [D0TCM] 4 8 read D0SBE 1-bit error detection bit [D0TCM] 0 1 read D1MASTER Memory access at 1-bit error[D1TCM] 12 16 read D1SBE 1-bit error detection bit [D1TCM] 8 9 read __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 9 12 read TCMDWAIT D0TCM/D1TCM Wait Setting Register 0x4 8 read-write n WAIT Wait setting [D0TCM, D1TCM] 0 1 read-write __reserve0 0 is always read out. 1 8 read TCMICBEN ITCM Check Bit Control Register 0x38 32 read-write n CBEN Check bit read/write enable [ITCM] 0 1 read-write KEY_CODE When TCMICBEN.KEY_CODE is set to 0xA5C3 , TCMICBEN is updating. 16 32 read-write __reserve0 0 is always read out. 1 16 read TCMIECCCNT ITCM ECC Control Register 0x30 32 read-write n ECCMOD ECC enable [ITCM] 0 1 read-write KEY_CODE When TCMIECCCNT.KEY_CODE is set to 0xA5C3 , TCMIECCCNT is updating. 16 32 read-write __reserve0 0 is always read out. 1 16 read TCMIMBEA ITCM 2-bit Error Address Register 0x50 32 read-write n MBEADD The 2-bit error or hard error address [ITCM] 0 32 read TCMIMBECLR ITCM 2-bit Error Detection Clear Register 0x5C 8 read-write n MBECLR Clear the 2-bit error and hard error detection [ITCM] 0 1 read-write __reserve0 0 is always read out. 1 8 read TCMIMBEDET ITCM 2-bit Error Detection Register 0x58 8 read-write n HDE Hard error detection bit [ITCM] 1 2 read MASTER Memory access at 2-bit error [ITCM] 4 8 read MBE 2-bit error detection bit [ITCM] 0 1 read __reserve0 0 is always read out. 2 4 read TCMISBEA ITCM 1-bit Error Address Register 0x40 32 read-write n SBEADD The 1bit error address [ITCM] 0 32 read TCMISBECLR ITCM 1-bit Error Detection Clear Register 0x4C 8 read-write n SBECLR Clear the 1-bit error detection [ITCM] 0 1 read-write __reserve0 0 is always read out. 1 8 read TCMISBEDET ITCM 1-bit Error Detection Register 0x48 8 read-write n MASTER Memory access at 1-bit error [ITCM] 4 8 read SBE 1-bit error detection bit [ITCM] 0 1 read __reserve0 0 is always read out. 1 4 read TCMIWAIT ITCM Wait Setting Register 0x34 8 read-write n WAIT Wait setting [ITCM] 0 1 read-write __reserve0 0 is always read out. 1 8 read MFA Multi Feedback Assist MFA 0x0 0x0 0x2DC registers n LEBCMP00CNT CMP00 Bla00ki00g Co00trol Register 0x240 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP00SET CMP00 Bla00ki00g set Register 0x244 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP00TGTSEL CMP00 Bla00ki00g Target Port set Register 0x248 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP01CNT CMP01 Bla01ki01g Co01trol Register 0x250 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP01SET CMP01 Bla01ki01g set Register 0x254 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP01TGTSEL CMP01 Bla01ki01g Target Port set Register 0x258 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP10CNT CMP10 Bla10ki10g Co10trol Register 0x260 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP10SET CMP10 Bla10ki10g set Register 0x264 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP10TGTSEL CMP10 Bla10ki10g Target Port set Register 0x268 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP11CNT CMP11 Bla11ki11g Co11trol Register 0x270 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP11SET CMP11 Bla11ki11g set Register 0x274 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP11TGTSEL CMP11 Bla11ki11g Target Port set Register 0x278 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP20CNT CMP20 Bla20ki20g Co20trol Register 0x280 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP20SET CMP20 Bla20ki20g set Register 0x284 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP20TGTSEL CMP20 Bla20ki20g Target Port set Register 0x288 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP21CNT CMP21 Bla21ki21g Co21trol Register 0x290 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP21SET CMP21 Bla21ki21g set Register 0x294 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP21TGTSEL CMP21 Bla21ki21g Target Port set Register 0x298 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP30CNT CMP30 Bla30ki30g Co30trol Register 0x2A0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP30SET CMP30 Bla30ki30g set Register 0x2A4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP30TGTSEL CMP30 Bla30ki30g Target Port set Register 0x2A8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP31CNT CMP31 Bla31ki31g Co31trol Register 0x2B0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP31SET CMP31 Bla31ki31g set Register 0x2B4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP31TGTSEL CMP31 Bla31ki31g Target Port set Register 0x2B8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP40CNT CMP40 Bla40ki40g Co40trol Register 0x2C0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP40SET CMP40 Bla40ki40g set Register 0x2C4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP40TGTSEL CMP40 Bla40ki40g Target Port set Register 0x2C8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBCMP41CNT CMP41 Bla41ki41g Co41trol Register 0x2D0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBCMP41SET CMP41 Bla41ki41g set Register 0x2D4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBCMP41TGTSEL CMP41 Bla41ki41g Target Port set Register 0x2D8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ00CNT IRQ00 Bla00ki00g Co00trol Register 0x100 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ00SET IRQ00 Bla00ki00g set Register 0x104 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ00TGTSEL IRQ00 Bla00ki00g Target Port set Register 0x108 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ01CNT IRQ01 Bla01ki01g Co01trol Register 0x110 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ01SET IRQ01 Bla01ki01g set Register 0x114 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ01TGTSEL IRQ01 Bla01ki01g Target Port set Register 0x118 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ02CNT IRQ02 Bla02ki02g Co02trol Register 0x120 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ02SET IRQ02 Bla02ki02g set Register 0x124 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ02TGTSEL IRQ02 Bla02ki02g Target Port set Register 0x128 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ03CNT IRQ03 Bla03ki03g Co03trol Register 0x130 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ03SET IRQ03 Bla03ki03g set Register 0x134 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ03TGTSEL IRQ03 Bla03ki03g Target Port set Register 0x138 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ04CNT IRQ04 Bla04ki04g Co04trol Register 0x140 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ04SET IRQ04 Bla04ki04g set Register 0x144 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ04TGTSEL IRQ04 Bla04ki04g Target Port set Register 0x148 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ05CNT IRQ05 Bla05ki05g Co05trol Register 0x150 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ05SET IRQ05 Bla05ki05g set Register 0x154 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ05TGTSEL IRQ05 Bla05ki05g Target Port set Register 0x158 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ08CNT IRQ08 Bla08ki08g Co08trol Register 0x180 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ08SET IRQ08 Bla08ki08g set Register 0x184 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ08TGTSEL IRQ08 Bla08ki08g Target Port set Register 0x188 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ09CNT IRQ09 Bla09ki09g Co09trol Register 0x190 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ09SET IRQ09 Bla09ki09g set Register 0x194 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ09TGTSEL IRQ09 Bla09ki09g Target Port set Register 0x198 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ10CNT IRQ10 Bla10ki10g Co10trol Register 0x1A0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ10SET IRQ10 Bla10ki10g set Register 0x1A4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ10TGTSEL IRQ10 Bla10ki10g Target Port set Register 0x1A8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ11CNT IRQ11 Bla11ki11g Co11trol Register 0x1B0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ11SET IRQ11 Bla11ki11g set Register 0x1B4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ11TGTSEL IRQ11 Bla11ki11g Target Port set Register 0x1B8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ12CNT IRQ12 Bla12ki12g Co12trol Register 0x1C0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ12SET IRQ12 Bla12ki12g set Register 0x1C4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ12TGTSEL IRQ12 Bla12ki12g Target Port set Register 0x1C8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ13CNT IRQ13 Bla13ki13g Co13trol Register 0x1D0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ13SET IRQ13 Bla13ki13g set Register 0x1D4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ13TGTSEL IRQ13 Bla13ki13g Target Port set Register 0x1D8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ14CNT IRQ14 Bla14ki14g Co14trol Register 0x1E0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ14SET IRQ14 Bla14ki14g set Register 0x1E4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ14TGTSEL IRQ14 Bla14ki14g Target Port set Register 0x1E8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ15CNT IRQ15 Bla15ki15g Co15trol Register 0x1F0 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ15SET IRQ15 Bla15ki15g set Register 0x1F4 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ15TGTSEL IRQ15 Bla15ki15g Target Port set Register 0x1F8 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ16CNT IRQ16 Bla16ki16g Co16trol Register 0x200 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ16SET IRQ16 Bla16ki16g set Register 0x204 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ16TGTSEL IRQ16 Bla16ki16g Target Port set Register 0x208 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ17CNT IRQ17 Bla17ki17g Co17trol Register 0x210 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ17SET IRQ17 Bla17ki17g set Register 0x214 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ17TGTSEL IRQ17 Bla17ki17g Target Port set Register 0x218 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ18CNT IRQ18 Bla18ki18g Co18trol Register 0x220 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ18SET IRQ18 Bla18ki18g set Register 0x224 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ18TGTSEL IRQ18 Bla18ki18g Target Port set Register 0x228 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read LEBIRQ19CNT IRQ19 Bla19ki19g Co19trol Register 0x230 16 read-write n LEBEN Blanking function operation enable 0 1 read-write __reserve0 0 is always read out. 1 16 read LEBIRQ19SET IRQ19 Bla19ki19g set Register 0x234 16 read-write n LEBSET Set Blanking period. 0 10 read-write __reserve0 0 is always read out. 10 16 read LEBIRQ19TGTSEL IRQ19 Bla19ki19g Target Port set Register 0x238 32 read-write n GPWM00EN GPWM00 output blanking target pin selection 0 1 read-write GPWM01EN GPWM01 output blanking target pin selection 1 2 read-write GPWM10EN GPWM10 output blanking target pin selection 2 3 read-write GPWM11EN GPWM11 output blanking target pin selection 3 4 read-write GPWM20EN GPWM20 output blanking target pin selection 4 5 read-write GPWM21EN GPWM21 output blanking target pin selection 5 6 read-write GPWM30EN GPWM30 output blanking target pin selection 6 7 read-write GPWM31EN GPWM31 output blanking target pin selection 7 8 read-write GPWM40EN GPWM40 output blanking target pin selection 8 9 read-write GPWM41EN GPWM41 output blanking target pin selection 9 10 read-write GPWM50EN GPWM50 output blanking target pin selection 10 11 read-write GPWM51EN GPWM51 output blanking target pin selection 11 12 read-write GPWM60EN GPWM60 output blanking target pin selection 12 13 read-write GPWM61EN GPWM61 output blanking target pin selection 13 14 read-write GPWM70EN GPWM70 output blanking target pin selection 14 15 read-write GPWM71EN GPWM71 output blanking target pin selection 15 16 read-write GPWM80EN GPWM80 output blanking target pin selection 16 17 read-write GPWM81EN GPWM81 output blanking target pin selection 17 18 read-write GPWM90EN GPWM90 output blanking target pin selection 18 19 read-write GPWM91EN GPWM91 output blanking target pin selection 19 20 read-write __reserve0 0 is always read out. 24 32 read MFAADC0ASTLMT A/D0A Co0Aversio0A Start Trigger Avoida0Ace Limit Set Register 0xD0 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAADC0BSTLMT A/D0B Co0Bversio0B Start Trigger Avoida0Bce Limit Set Register 0xD4 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAADC1ASTLMT A/D1A Co1Aversio1A Start Trigger Avoida1Ace Limit Set Register 0xD8 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAADC1BSTLMT A/D1B Co1Bversio1B Start Trigger Avoida1Bce Limit Set Register 0xDC 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAADC2ASTLMT A/D2A Co2Aversio2A Start Trigger Avoida2Ace Limit Set Register 0xE0 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAADC2BSTLMT A/D2B Co2Bversio2B Start Trigger Avoida2Bce Limit Set Register 0xE4 16 read-write n ADnSTLMT Set avoidance limit period of A/Dn conversion start trigger 0 10 read-write __reserve0 0 is always read out. 10 16 read MFACNT Conflict Detection Control Register 0x60 16 read-write n CMPTEN Operation enable of Conflict detection/Automatic avoidance function 0 1 read-write __reserve0 0 is always read out. 1 16 read MFAGPWM0CPTC GPWM0 Co0flict Detectio0 Period set Register 0x80 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM0DLY GPWM0 Sy0chro0ous Start Timi0g set Register 0x10 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM1CPTC GPWM1 Co1flict Detectio1 Period set Register 0x84 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM1DLY GPWM1 Sy1chro1ous Start Timi1g set Register 0x14 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM2CPTC GPWM2 Co2flict Detectio2 Period set Register 0x88 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM2DLY GPWM2 Sy2chro2ous Start Timi2g set Register 0x18 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM3CPTC GPWM3 Co3flict Detectio3 Period set Register 0x8C 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM3DLY GPWM3 Sy3chro3ous Start Timi3g set Register 0x1C 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM4CPTC GPWM4 Co4flict Detectio4 Period set Register 0x90 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM4DLY GPWM4 Sy4chro4ous Start Timi4g set Register 0x20 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM5CPTC GPWM5 Co5flict Detectio5 Period set Register 0x94 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM5DLY GPWM5 Sy5chro5ous Start Timi5g set Register 0x24 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM6CPTC GPWM6 Co6flict Detectio6 Period set Register 0x98 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM6DLY GPWM6 Sy6chro6ous Start Timi6g set Register 0x28 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM7CPTC GPWM7 Co7flict Detectio7 Period set Register 0x9C 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM7DLY GPWM7 Sy7chro7ous Start Timi7g set Register 0x2C 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM8CPTC GPWM8 Co8flict Detectio8 Period set Register 0xA0 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM8DLY GPWM8 Sy8chro8ous Start Timi8g set Register 0x30 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGPWM9CPTC GPWM9 Co9flict Detectio9 Period set Register 0xA4 16 read-write n GPWMnCPTC Set conflict detection period of GPWMn output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFAGPWM9DLY GPWM9 Sy9chro9ous Start Timi9g set Register 0x34 16 read-write n GPWMnDST Set the count value of the global timer that starts GPWMn. 0 16 read-write MFAGTIMERSET Global timer cycle set register 0x8 16 read-write n GTIMERST Set global timer count cycle 0 16 read-write MFAPOUTENA Conflict Detection Timer Output Selection Register A 0x70 32 read-write n GPWM00EN GPWM00 output conflict detection target pin selection 0 1 read-write GPWM01EN GPWM01 output conflict detection target pin selection 1 2 read-write GPWM10EN GPWM10 output conflict detection target pin selection 2 3 read-write GPWM11EN GPWM11 output conflict detection target pin selection 3 4 read-write GPWM20EN GPWM20 output conflict detection target pin selection 4 5 read-write GPWM21EN GPWM21 output conflict detection target pin selection 5 6 read-write GPWM30EN GPWM30 output conflict detection target pin selection 6 7 read-write GPWM31EN GPWM31 output conflict detection target pin selection 7 8 read-write GPWM40EN GPWM40 output conflict detection target pin selection 8 9 read-write GPWM41EN GPWM41 output conflict detection target pin selection 9 10 read-write GPWM50EN GPWM50 output conflict detection target pin selection 10 11 read-write GPWM51EN GPWM51 output conflict detection target pin selection 11 12 read-write GPWM60EN GPWM60 output conflict detection target pin selection 12 13 read-write GPWM61EN GPWM61 output conflict detection target pin selection 13 14 read-write GPWM70EN GPWM70 output conflict detection target pin selection 14 15 read-write GPWM71EN GPWM71 output conflict detection target pin selection 15 16 read-write GPWM80EN GPWM80 output conflict detection target pin selection 16 17 read-write GPWM81EN GPWM81 output conflict detection target pin selection 17 18 read-write GPWM90EN GPWM90 output conflict detection target pin selection 18 19 read-write GPWM91EN GPWM91 output conflict detection target pin selection 19 20 read-write __reserve0 This bit must be set to 0 . 24 25 read-write __reserve1 0 is always read out. 25 32 read MFAPOUTENB Conflict Detection Timer Output Selection Register B 0x74 16 read-write n TM20AOEN TM20AO output conflict detection target pin selection 0 1 read-write TM20BOEN TM20BO output conflict detection target pin selection 1 2 read-write TM21AOEN TM21AO output conflict detection target pin selection 2 3 read-write TM21BOEN TM21BO output conflict detection target pin selection 3 4 read-write TM22AOEN TM22AO output conflict detection target pin selection 4 5 read-write TM22BOEN TM22BO output conflict detection target pin selection 5 6 read-write TM23AOEN TM23AO output conflict detection target pin selection 6 7 read-write TM23BOEN TM23BO output conflict detection target pin selection 7 8 read-write TM24AOEN TM24AO output conflict detection target pin selection 8 9 read-write TM24BOEN TM24BO output conflict detection target pin selection 9 10 read-write TM25AOEN TM25AO output conflict detection target pin selection 10 11 read-write TM25BOEN TM25BO output conflict detection target pin selection 11 12 read-write __reserve0 0 is always read out. 12 16 read MFASTAT Conflict Detection Status Register 0x68 16 read-write n AD0TALMT Delay status of A/D0 conversion start trigger A 8 9 read AD0TASTAT Conflict detection of A/D0 conversion start trigger A 0 1 read AD0TBLMT Delay status of A/D0 conversion start trigger B 9 10 read AD0TBSTAT Conflict detection of A/D0 conversion start trigger B 1 2 read AD1TALMT Delay status of A/D1 conversion start trigger A 10 11 read AD1TASTAT Conflict detection of A/D1 conversion start trigger A 2 3 read AD1TBLMT Delay status of A/D1 conversion start trigger B 11 12 read AD1TBSTAT Conflict detection of A/D1 conversion start trigger B 3 4 read AD2TALMT Delay status of A/D2 conversion start trigger A 12 13 read AD2TASTAT Conflict detection of A/D2 conversion start trigger A 4 5 read AD2TBLMT Delay status of A/D2 conversion start trigger B 13 14 read AD2TBSTAT Conflict detection of A/D2 conversion start trigger B 5 6 read __reserve0 0 is always read out. 6 8 read __reserve1 0 is always read out. 14 16 read MFASYNCNT Synchronous Start Control Register 0x0 16 read-write n GTMRCKSEL Selection of count clock at global timer 1 2 read-write GTMRSTART Global timer operation enable 0 1 read-write __reserve0 0 is always read out. 2 16 read MFASYNTGT Synchronous Start Target Selection Register 0x4 32 read-write n GPWM0SYST GPWM0 synchronous start selection 0 1 read-write GPWM1SYST GPWM1 synchronous start selection 1 2 read-write GPWM2SYST GPWM2 synchronous start selection 2 3 read-write GPWM3SYST GPWM3 synchronous start selection 3 4 read-write GPWM4SYST GPWM4 synchronous start selection 4 5 read-write GPWM5SYST GPWM5 synchronous start selection 5 6 read-write GPWM6SYST GPWM6 synchronous start selection 6 7 read-write GPWM7SYST GPWM7 synchronous start selection 7 8 read-write GPWM8SYST GPWM8 synchronous start selection 8 9 read-write GPWM9SYST GPWM9 synchronous start selection 9 10 read-write TM20SYST Timer 20 synchronous start selection 16 17 read-write TM21SYST Timer 21 synchronous start selection 17 18 read-write TM22SYST Timer 22 synchronous start selection 18 19 read-write TM23SYST Timer 23 synchronous start selection 19 20 read-write TM24SYST Timer 24 synchronous start selection 20 21 read-write TM25SYST Timer 25 synchronous start selection 21 22 read-write __reserve0 This bit must be set to 0 . 12 13 read-write __reserve1 0 is always read out. 13 16 read __reserve2 0 is always read out. 22 32 read MFATGT Conflict Detection A/D Conversion Start Trigger Selection Register 0x64 16 read-write n AD0TATGT Selection of conflict detection and avoidance operation of A/D0 conversion start trigger A 0 2 read-write AD0TBTGT Selection of conflict detection and avoidance operation of A/D0 conversion start trigger B 2 4 read-write AD1TATGT Selection of conflict detection and avoidance operation of A/D1 conversion start trigger A 4 6 read-write AD1TBTGT Selection of conflict detection and avoidance operation of A/D1 conversion start trigger B 6 8 read-write AD2TATGT Selection of conflict detection and avoidance operation of A/D2 conversion start trigger A 8 10 read-write AD2TBTGT Selection of conflict detection and avoidance operation of A/D2 conversion start trigger B 10 12 read-write __reserve0 0 is always read out. 12 16 read MFATM20CPTC Timer 20 Co20flict Detectio20 Period set Register 0xB0 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM20DLY Timer 20 Sy20chro20ous Start Timi20g set Register 0x40 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write MFATM21CPTC Timer 21 Co21flict Detectio21 Period set Register 0xB4 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM21DLY Timer 21 Sy21chro21ous Start Timi21g set Register 0x44 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write MFATM22CPTC Timer 22 Co22flict Detectio22 Period set Register 0xB8 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM22DLY Timer 22 Sy22chro22ous Start Timi22g set Register 0x48 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write MFATM23CPTC Timer 23 Co23flict Detectio23 Period set Register 0xBC 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM23DLY Timer 23 Sy23chro23ous Start Timi23g set Register 0x4C 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write MFATM24CPTC Timer 24 Co24flict Detectio24 Period set Register 0xC0 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM24DLY Timer 24 Sy24chro24ous Start Timi24g set Register 0x50 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write MFATM25CPTC Timer 25 Co25flict Detectio25 Period set Register 0xC4 16 read-write n TMnCPTC Set conflict detection period of Timer n output 0 10 read-write __reserve0 0 is always read out. 10 16 read MFATM25DLY Timer 25 Sy25chro25ous Start Timi25g set Register 0x54 16 read-write n TMnDST Set the count value of the global timer that starts Timer n. 0 16 read-write NF Noise Filter NF 0x0 0x0 0x4C registers n NFCK0 Sampling Clock Setting Register 0 0x0 32 read-write n CK0 Sampling clock frequency selection for IRQ00 0 3 read-write CK1 Sampling clock frequency selection for IRQ01 4 7 read-write CK2 Sampling clock frequency selection for IRQ02 8 11 read-write CK3 Sampling clock frequency selection for IRQ03 12 15 read-write CK4 Sampling clock frequency selection for IRQ04 16 19 read-write CK5 Sampling clock frequency selection for IRQ05 20 23 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK1 Sampling Clock Setting Register 1 0x4 32 read-write n CK0 Sampling clock frequency selection for IRQ08 0 3 read-write CK1 Sampling clock frequency selection for IRQ09 4 7 read-write CK2 Sampling clock frequency selection for IRQ10 8 11 read-write CK3 Sampling clock frequency selection for IRQ11 12 15 read-write CK4 Sampling clock frequency selection for IRQ12 16 19 read-write CK5 Sampling clock frequency selection for IRQ13 20 23 read-write CK6 Sampling clock frequency selection for IRQ14 24 27 read-write CK7 Sampling clock frequency selection for IRQ15 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK2 Sampling Clock Setting Register 2 0x8 32 read-write n CK0 Sampling clock frequency selection for IRQ16 0 3 read-write CK1 Sampling clock frequency selection for IRQ17 4 7 read-write CK2 Sampling clock frequency selection for IRQ18 8 11 read-write CK3 Sampling clock frequency selection for IRQ19 12 15 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 32 read-write NFCK4 Sampling Clock Setting Register 4 0x10 32 read-write n CK0 Sampling clock frequency selection for TM00A 0 3 read-write CK1 Sampling clock frequency selection for TM00B 4 7 read-write CK2 Sampling clock frequency selection for TM01A 8 11 read-write CK3 Sampling clock frequency selection for TM01B 12 15 read-write CK4 Sampling clock frequency selection for TM02A 16 19 read-write CK5 Sampling clock frequency selection for TM02B 20 23 read-write CK6 Sampling clock frequency selection for TM03A 24 27 read-write CK7 Sampling clock frequency selection for TM03B 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK5 Sampling Clock Setting Register 5 0x14 32 read-write n CK0 Sampling clock frequency selection for TM04A 0 3 read-write CK1 Sampling clock frequency selection for TM04B 4 7 read-write CK2 Sampling clock frequency selection for TM05A 8 11 read-write CK3 Sampling clock frequency selection for TM05B 12 15 read-write CK4 Sampling clock frequency selection for TM06A 16 19 read-write CK5 Sampling clock frequency selection for TM06B 20 23 read-write CK6 Sampling clock frequency selection for TM07A 24 27 read-write CK7 Sampling clock frequency selection for TM07B 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK6 Sampling Clock Setting Register 6 0x18 32 read-write n CK0 Sampling clock frequency selection for TM08A 0 3 read-write CK1 Sampling clock frequency selection for TM08B 4 7 read-write CK2 Sampling clock frequency selection for TM09A 8 11 read-write CK3 Sampling clock frequency selection for TM09B 12 15 read-write CK4 Sampling clock frequency selection for TM10A 16 19 read-write CK5 Sampling clock frequency selection for TM10B 20 23 read-write CK6 Sampling clock frequency selection for TM11A 24 27 read-write CK7 Sampling clock frequency selection for TM11B 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK7 Sampling Clock Setting Register 7 0x1C 32 read-write n CK0 Sampling clock frequency selection for TM12A 0 3 read-write CK1 Sampling clock frequency selection for TM12B 4 7 read-write CK2 Sampling clock frequency selection for TM13A 8 11 read-write CK3 Sampling clock frequency selection for TM13B 12 15 read-write CK4 Sampling clock frequency selection for TM20A 16 19 read-write CK5 Sampling clock frequency selection for TM20B 20 23 read-write CK6 Sampling clock frequency selection for TM21A 24 27 read-write CK7 Sampling clock frequency selection for TM21B 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCK8 Sampling Clock Setting Register 8 0x20 32 read-write n CK0 Sampling clock frequency selection for TM22A 0 3 read-write CK1 Sampling clock frequency selection for TM22B 4 7 read-write CK2 Sampling clock frequency selection for TM23A 8 11 read-write CK3 Sampling clock frequency selection for TM23B 12 15 read-write CK4 Sampling clock frequency selection for TM24A 16 19 read-write CK5 Sampling clock frequency selection for TM24B 20 23 read-write CK6 Sampling clock frequency selection for TM25A 24 27 read-write CK7 Sampling clock frequency selection for TM25B 28 31 read-write __reserve0 0 is always read out. 3 4 read-write __reserve1 0 is always read out. 7 8 read-write __reserve2 0 is always read out. 11 12 read-write __reserve3 0 is always read out. 15 16 read-write __reserve4 0 is always read out. 19 20 read-write __reserve5 0 is always read out. 23 24 read-write __reserve6 0 is always read out. 27 28 read-write __reserve7 0 is always read out. 31 32 read-write NFCNT0 Noise Filter Control Register 0 0x40 32 read-write n CNT0 Noise filter enabled/disabled selection for IRQ0 0 1 read-write CNT1 Noise filter enabled/disabled selection for IRQ1 1 2 read-write CNT10 Noise filter enabled/disabled selection for IRQ10 10 11 read-write CNT11 Noise filter enabled/disabled selection for IRQ11 11 12 read-write CNT12 Noise filter enabled/disabled selection for IRQ12 12 13 read-write CNT13 Noise filter enabled/disabled selection for IRQ13 13 14 read-write CNT14 Noise filter enabled/disabled selection for IRQ14 14 15 read-write CNT15 Noise filter enabled/disabled selection for IRQ15 15 16 read-write CNT16 Noise filter enabled/disabled selection for IRQ16 16 17 read-write CNT17 Noise filter enabled/disabled selection for IRQ17 17 18 read-write CNT18 Noise filter enabled/disabled selection for IRQ18 18 19 read-write CNT19 Noise filter enabled/disabled selection for IRQ19 19 20 read-write CNT2 Noise filter enabled/disabled selection for IRQ2 2 3 read-write CNT3 Noise filter enabled/disabled selection for IRQ3 3 4 read-write CNT4 Noise filter enabled/disabled selection for IRQ4 4 5 read-write CNT5 Noise filter enabled/disabled selection for IRQ5 5 6 read-write CNT8 Noise filter enabled/disabled selection for IRQ8 8 9 read-write CNT9 Noise filter enabled/disabled selection for IRQ9 9 10 read-write __reserve0 0s are always read out. 20 32 read-write NFCNT1 Noise Filter Control Register 1 0x44 32 read-write n CNT0 Noise filter enabled/disabled selection for TM00A 0 1 read-write CNT1 Noise filter enabled/disabled selection for TM00B 1 2 read-write CNT10 Noise filter enabled/disabled selection for TM05A 10 11 read-write CNT11 Noise filter enabled/disabled selection for TM05B 11 12 read-write CNT12 Noise filter enabled/disabled selection for TM06A 12 13 read-write CNT13 Noise filter enabled/disabled selection for TM06B 13 14 read-write CNT14 Noise filter enabled/disabled selection for TM07A 14 15 read-write CNT15 Noise filter enabled/disabled selection for TM07B 15 16 read-write CNT16 Noise filter enabled/disabled selection for TM08A 16 17 read-write CNT17 Noise filter enabled/disabled selection for TM08B 17 18 read-write CNT18 Noise filter enabled/disabled selection for TM09A 18 19 read-write CNT19 Noise filter enabled/disabled selection for TM09B 19 20 read-write CNT2 Noise filter enabled/disabled selection for TM01A 2 3 read-write CNT20 Noise filter enabled/disabled selection for TM10A 20 21 read-write CNT21 Noise filter enabled/disabled selection for TM10B 21 22 read-write CNT22 Noise filter enabled/disabled selection for TM11A 22 23 read-write CNT23 Noise filter enabled/disabled selection for TM11B 23 24 read-write CNT24 Noise filter enabled/disabled selection for TM12A 24 25 read-write CNT25 Noise filter enabled/disabled selection for TM12B 25 26 read-write CNT26 Noise filter enabled/disabled selection for TM13A 26 27 read-write CNT27 Noise filter enabled/disabled selection for TM13B 27 28 read-write CNT28 Noise filter enabled/disabled selection for TM20A 28 29 read-write CNT29 Noise filter enabled/disabled selection for TM20B 29 30 read-write CNT3 Noise filter enabled/disabled selection for TM01B 3 4 read-write CNT30 Noise filter enabled/disabled selection for TM21A 30 31 read-write CNT31 Noise filter enabled/disabled selection for TM21B 31 32 read-write CNT4 Noise filter enabled/disabled selection for TM02A 4 5 read-write CNT5 Noise filter enabled/disabled selection for TM02B 5 6 read-write CNT6 Noise filter enabled/disabled selection for TM03A 6 7 read-write CNT7 Noise filter enabled/disabled selection for TM03B 7 8 read-write CNT8 Noise filter enabled/disabled selection for TM04A 8 9 read-write CNT9 Noise filter enabled/disabled selection for TM04B 9 10 read-write NFCNT2 Noise Filter Control Register 2 0x48 32 read-write n CNT0 Noise filter enabled/disabled selection for TM22A 0 1 read-write CNT1 Noise filter enabled/disabled selection for TM22B 1 2 read-write CNT2 Noise filter enabled/disabled selection for TM23A 2 3 read-write CNT3 Noise filter enabled/disabled selection for TM23B 3 4 read-write CNT4 Noise filter enabled/disabled selection for TM24A 4 5 read-write CNT5 Noise filter enabled/disabled selection for TM24B 5 6 read-write CNT6 Noise filter enabled/disabled selection for TM25A 6 7 read-write CNT7 Noise filter enabled/disabled selection for TM25B 7 8 read-write __reserve0 0s are always read out. 8 32 read-write PORT I/O Port PORT 0x0 0x0 0xE9 registers n IOP0CLR Port 0 Output Clear Register 0x10 8 read-write n P00CLR Clear P00OUT 0 1 write P01CLR Clear P01OUT 1 2 write P02CLR Clear P02OUT 2 3 write P03CLR Clear P03OUT 3 4 write P04CLR Clear P04OUT 4 5 write P05CLR Clear P05OUT 5 6 write IOP0IE Port 0 Input Enable Register 0x60 8 read-write n P00IE P00 input enable 0 1 read-write P01IE P01 input enable 1 2 read-write P02IE P02 input enable 2 3 read-write P03IE P03 input enable 3 4 read-write P04IE P04 input enable 4 5 read-write P05IE P05 input enable 5 6 read-write IOP0ILV Port 0 Input Level Selection Register 0xE0 8 read-write n __reserve0 0 is always read out. 0 6 read IOP0IN Port 0 Input Register 0x40 8 read-write n P00IN Input data of P00 is read out. 0 1 read P01IN Input data of P01 is read out. 1 2 read P02IN Input data of P02 is read out. 2 3 read P03IN Input data of P03 is read out. 3 4 read P04IN Input data of P04 is read out. 4 5 read P05IN Input data of P05 is read out. 5 6 read IOP0MD Port 0 Mode Register 0x80 32 read-write n P00MD P00 function selection 0 4 read-write P01MD P01 function selection 4 8 read-write P02MD P02 function selection 8 12 read-write P03MD P03 function selection 12 16 read-write P04MD P04 function selection 16 20 read-write P05MD P05 function selection 20 24 read-write IOP0ODC Port 0 Nch Open-drain Control Register 0x70 8 read-write n __reserve0 0 is always read out. 0 6 read IOP0OE Port 0 Output Enable Register 0x50 8 read-write n P00OE P00 output enable 0 1 read-write P01OE P01 output enable 1 2 read-write P02OE P02 output enable 2 3 read-write P03OE P03 output enable 3 4 read-write P04OE P04 output enable 4 5 read-write P05OE P05 output enable 5 6 read-write IOP0OUT Port 0 Output Register 0x0 8 read-write n P00OUT Set output data of P00 0 1 read-write P01OUT Set output data of P01 1 2 read-write P02OUT Set output data of P02 2 3 read-write P03OUT Set output data of P03 3 4 read-write P04OUT Set output data of P04 4 5 read-write P05OUT Set output data of P05 5 6 read-write IOP0PLU Port 0 Pull-up Control Register 0xC0 8 read-write n P00PLU P00 pull-up resistor selection 0 1 read-write P01PLU P01 pull-up resistor selection 1 2 read-write P02PLU P02 pull-up resistor selection 2 3 read-write P03PLU P03 pull-up resistor selection 3 4 read-write P04PLU P04 pull-up resistor selection 4 5 read-write P05PLU P05 pull-up resistor selection 5 6 read-write IOP0SET Port 0 Output Set Register 0x20 8 read-write n P00SET Set P00OUT 0 1 write P01SET Set P01OUT 1 2 write P02SET Set P02OUT 2 3 write P03SET Set P03OUT 3 4 write P04SET Set P04OUT 4 5 write P05SET Set P05OUT 5 6 write IOP0TGL Port 0 Output Toggle Register 0x30 8 read-write n P00TGL Invert P00OUT 0 1 write P01TGL Invert P01OUT 1 2 write P02TGL Invert P02OUT 2 3 write P03TGL Invert P03OUT 3 4 write P04TGL Invert P04OUT 4 5 write P05TGL Invert P05OUT 5 6 write IOP1CLR Port 1 Output Clear Register 0x11 8 read-write n P10CLR Clear P10OUT 0 1 write P11CLR Clear P11OUT 1 2 write P12CLR Clear P12OUT 2 3 write P13CLR Clear P13OUT 3 4 write P14CLR Clear P14OUT 4 5 write P15CLR Clear P15OUT 5 6 write IOP1IE Port 1 Input Enable Register 0x61 8 read-write n P10IE P10 input enable 0 1 read-write P11IE P11 input enable 1 2 read-write P12IE P12 input enable 2 3 read-write P13IE P13 input enable 3 4 read-write P14IE P14 input enable 4 5 read-write P15IE P15 input enable 5 6 read-write IOP1ILV Port 1 Input Level Selection Register 0xE1 8 read-write n P12ILV P12 Input level selection 2 3 read-write P13ILV P13 Input level selection 3 4 read-write P14ILV P14 Input level selection 4 5 read-write P15ILV P15 Input level selection 5 6 read-write __reserve0 0 is always read out. 0 2 read __reserve1 0 is always read out. 6 8 read IOP1IN Port 1 Input Register 0x41 8 read-write n P10IN Input data of P10 is read out. 0 1 read P11IN Input data of P11 is read out. 1 2 read P12IN Input data of P12 is read out. 2 3 read P13IN Input data of P13 is read out. 3 4 read P14IN Input data of P14 is read out. 4 5 read P15IN Input data of P15 is read out. 5 6 read IOP1MD Port 1 Mode Register 0x84 32 read-write n P10MD P10 function selection 0 4 read-write P11MD P11 function selection 4 8 read-write P12MD P12 function selection 8 12 read-write P13MD P13 function selection 12 16 read-write P14MD P14 function selection 16 20 read-write P15MD P15 function selection 20 24 read-write IOP1ODC Port 1 Nch Open-drain Control Register 0x71 8 read-write n P10ODC P10 Nch open-drain selection 0 1 read-write __reserve0 0 is always read out. 1 8 read IOP1OE Port 1 Output Enable Register 0x51 8 read-write n P10OE P10 output enable 0 1 read-write P11OE P11 output enable 1 2 read-write P12OE P12 output enable 2 3 read-write P13OE P13 output enable 3 4 read-write P14OE P14 output enable 4 5 read-write P15OE P15 output enable 5 6 read-write IOP1OUT Port 1 Output Register 0x1 8 read-write n P10OUT Set output data of P10 0 1 read-write P11OUT Set output data of P11 1 2 read-write P12OUT Set output data of P12 2 3 read-write P13OUT Set output data of P13 3 4 read-write P14OUT Set output data of P14 4 5 read-write P15OUT Set output data of P15 5 6 read-write IOP1PLU Port 1 Pull-up Control Register 0xC1 8 read-write n P10PLU P10 pull-up resistor selection 0 1 read-write P11PLU P11 pull-up resistor selection 1 2 read-write P12PLU P12 pull-up resistor selection 2 3 read-write P13PLU P13 pull-up resistor selection 3 4 read-write P14PLU P14 pull-up resistor selection 4 5 read-write P15PLU P15 pull-up resistor selection 5 6 read-write IOP1SET Port 1 Output Set Register 0x21 8 read-write n P10SET Set P10OUT 0 1 write P11SET Set P11OUT 1 2 write P12SET Set P12OUT 2 3 write P13SET Set P13OUT 3 4 write P14SET Set P14OUT 4 5 write P15SET Set P15OUT 5 6 write IOP1TGL Port 1 Output Toggle Register 0x31 8 read-write n P10TGL Invert P10OUT 0 1 write P11TGL Invert P11OUT 1 2 write P12TGL Invert P12OUT 2 3 write P13TGL Invert P13OUT 3 4 write P14TGL Invert P14OUT 4 5 write P15TGL Invert P15OUT 5 6 write IOP2CLR Port 2 Output Clear Register 0x12 8 read-write n P20CLR Clear P20OUT 0 1 write P21CLR Clear P21OUT 1 2 write P22CLR Clear P22OUT 2 3 write P24CLR Clear P24OUT 4 5 write P25CLR Clear P25OUT 5 6 write P26CLR Clear P26OUT 6 7 write P27CLR Clear P27OUT 7 8 write __reserve0 0 is always read out. 3 4 read IOP2IE Port 2 Input Enable Register 0x62 8 read-write n P20IE P20 input enable 0 1 read-write P21IE P21 input enable 1 2 read-write P22IE P22 input enable 2 3 read-write P24IE P24 input enable 4 5 read-write P25IE P25 input enable 5 6 read-write P26IE P26 input enable 6 7 read-write P27IE P27 input enable 7 8 read-write __reserve0 0 is always read out. 3 4 read IOP2ILV Port 2 Input Level Selection Register 0xE2 8 read-write n P20ILV P20 Input level selection 0 1 read-write P21ILV P21 Input level selection 1 2 read-write __reserve0 0 is always read out. 2 8 read IOP2IN Port 2 Input Register 0x42 8 read-write n P20IN Input data of P20 is read out. 0 1 read P21IN Input data of P21 is read out. 1 2 read P22IN Input data of P22 is read out. 2 3 read P24IN Input data of P24 is read out. 4 5 read P25IN Input data of P25 is read out. 5 6 read P26IN Input data of P26 is read out. 6 7 read P27IN Input data of P27 is read out. 7 8 read __reserve0 0 is always read out. 3 4 read IOP2MD Port 2 Mode Register 0x88 32 read-write n P20MD P20 function selection 0 4 read-write P21MD P21 function selection 4 8 read-write P22MD P22 function selection 8 12 read-write P24MD P24 function selection 16 20 read-write P25MD P25 function selection 20 24 read-write P26MD P26 function selection 24 28 read-write P27MD P27 function selection 28 32 read-write __reserve0 0 is always read out. 12 16 read IOP2ODC Port 2 Nch Open-drain Control Register 0x72 8 read-write n P25ODC P25 Nch open-drain selection 5 6 read-write P26ODC P26 Nch open-drain selection 6 7 read-write P27ODC P27 Nch open-drain selection 7 8 read-write __reserve0 0 is always read out. 0 5 read IOP2OE Port 2 Output Enable Register 0x52 8 read-write n P20OE P20 output enable 0 1 read-write P21OE P21 output enable 1 2 read-write P22OE P22 output enable 2 3 read-write P24OE P24 output enable 4 5 read-write P25OE P25 output enable 5 6 read-write P26OE P26 output enable 6 7 read-write P27OE P27 output enable 7 8 read-write __reserve0 0 is always read out. 3 4 read IOP2OUT Port 2 Output Register 0x2 8 read-write n P20OUT Set output data of P20 0 1 read-write P21OUT Set output data of P21 1 2 read-write P22OUT Set output data of P22 2 3 read-write P24OUT Set output data of P24 4 5 read-write P25OUT Set output data of P25 5 6 read-write P26OUT Set output data of P26 6 7 read-write P27OUT Set output data of P27 7 8 read-write __reserve0 0 is always read out. 3 4 read IOP2PLU Port 2 Pull-up Control Register 0xC2 8 read-write n P20PLU P20 pull-up resistor selection 0 1 read-write P21PLU P21 pull-up resistor selection 1 2 read-write P22PLU P22 pull-up resistor selection 2 3 read-write P24PLU P24 pull-up resistor selection 4 5 read-write P25PLU P25 pull-up resistor selection 5 6 read-write P26PLU P26 pull-up resistor selection 6 7 read-write P27PLU P27 pull-up resistor selection 7 8 read-write __reserve0 0 is always read out. 3 4 read IOP2SET Port 2 Output Set Register 0x22 8 read-write n P20SET Set P20OUT 0 1 write P21SET Set P21OUT 1 2 write P22SET Set P22OUT 2 3 write P24SET Set P24OUT 4 5 write P25SET Set P25OUT 5 6 write P26SET Set P26OUT 6 7 write P27SET Set P27OUT 7 8 write __reserve0 0 is always read out. 3 4 read IOP2TGL Port 2 Output Toggle Register 0x32 8 read-write n P20TGL Invert P20OUT 0 1 write P21TGL Invert P21OUT 1 2 write P22TGL Invert P22OUT 2 3 write P24TGL Invert P24OUT 4 5 write P25TGL Invert P25OUT 5 6 write P26TGL Invert P26OUT 6 7 write P27TGL Invert P27OUT 7 8 write __reserve0 0 is always read out. 3 4 read IOP3CLR Port 3 Output Clear Register 0x13 8 read-write n P30CLR Clear P30OUT 0 1 write P31CLR Clear P31OUT 1 2 write P32CLR Clear P32OUT 2 3 write P34CLR Clear P34OUT 4 5 write P35CLR Clear P35OUT 5 6 write P36CLR Clear P36OUT 6 7 write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3IE Port 3 Input Enable Register 0x63 8 read-write n P30IE P30 input enable 0 1 read-write P31IE P31 input enable 1 2 read-write P32IE P32 input enable 2 3 read-write P34IE P34 input enable 4 5 read-write P35IE P35 input enable 5 6 read-write P36IE P36 input enable 6 7 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3IN Port 3 Input Register 0x43 8 read-write n P30IN Input data of P30 is read out. 0 1 read P31IN Input data of P31 is read out. 1 2 read P32IN Input data of P32 is read out. 2 3 read P34IN Input data of P34 is read out. 4 5 read P35IN Input data of P35 is read out. 5 6 read P36IN Input data of P36 is read out. 6 7 read __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3MD Port 3 Mode Register 0x8C 32 read-write n P30MD P30 function selection 0 4 read-write P31MD P31 function selection 4 8 read-write P32MD P32 function selection 8 12 read-write P34MD P34 function selection 16 20 read-write P35MD P35 function selection 20 24 read-write P36MD P36 function selection 24 28 read-write __reserve0 0 is always read out. 12 16 read __reserve1 0 is always read out. 28 32 read IOP3ODC Port 3 Nch Open-drain Control Register 0x73 8 read-write n P30ODC P30 Nch open-drain selection 0 1 read-write P31ODC P31 Nch open-drain selection 1 2 read-write P34ODC P34 Nch open-drain selection 4 5 read-write P35ODC P35 Nch open-drain selection 5 6 read-write __reserve0 0 is always read out. 2 4 read __reserve1 0 is always read out. 6 8 read IOP3OE Port 3 Output Enable Register 0x53 8 read-write n P30OE P30 output enable 0 1 read-write P31OE P31 output enable 1 2 read-write P32OE P32 output enable 2 3 read-write P34OE P34 output enable 4 5 read-write P35OE P35 output enable 5 6 read-write P36OE P36 output enable 6 7 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3OUT Port 3 Output Register 0x3 8 read-write n P30OUT Set output data of P30 0 1 read-write P31OUT Set output data of P31 1 2 read-write P32OUT Set output data of P32 2 3 read-write P34OUT Set output data of P34 4 5 read-write P35OUT Set output data of P35 5 6 read-write P36OUT Set output data of P36 6 7 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3PLU Port 3 Pull-up Control Register 0xC3 8 read-write n P30PLU P30 pull-up resistor selection 0 1 read-write P31PLU P31 pull-up resistor selection 1 2 read-write P32PLU P32 pull-up resistor selection 2 3 read-write P34PLU P34 pull-up resistor selection 4 5 read-write P35PLU P35 pull-up resistor selection 5 6 read-write P36PLU P36 pull-up resistor selection 6 7 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3SET Port 3 Output Set Register 0x23 8 read-write n P30SET Set P30OUT 0 1 write P31SET Set P31OUT 1 2 write P32SET Set P32OUT 2 3 write P34SET Set P34OUT 4 5 write P35SET Set P35OUT 5 6 write P36SET Set P36OUT 6 7 write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP3TGL Port 3 Output Toggle Register 0x33 8 read-write n P30TGL Invert P30OUT 0 1 write P31TGL Invert P31OUT 1 2 write P32TGL Invert P32OUT 2 3 write P34TGL Invert P34OUT 4 5 write P35TGL Invert P35OUT 5 6 write P36TGL Invert P36OUT 6 7 write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read IOP4CLR Port 4 Output Clear Register 0x14 8 read-write n P44CLR Clear P44OUT 4 5 write P45CLR Clear P45OUT 5 6 write P46CLR Clear P46OUT 6 7 write __reserve0 0 is always read out. 3 4 read IOP4IE Port 4 Input Enable Register 0x64 8 read-write n P44IE P44 input enable 4 5 read-write P45IE P45 input enable 5 6 read-write P46IE P46 input enable 6 7 read-write __reserve0 0 is always read out. 3 4 read IOP4IN Port 4 Input Register 0x44 8 read-write n P44IN Input data of P44 is read out. 4 5 read P45IN Input data of P45 is read out. 5 6 read P46IN Input data of P46 is read out. 6 7 read __reserve0 0 is always read out. 3 4 read IOP4MD Port 4 Mode Register 0x90 32 read-write n P44MD P44 function selection 16 20 read-write P45MD P45 function selection 20 24 read-write P46MD P46 function selection 24 28 read-write __reserve0 0 is always read out. 12 16 read IOP4ODC Port 4 Nch Open-drain Control Register 0x74 8 read-write n P44ODC P44 Nch open-drain selection 4 5 read-write P45ODC P45 Nch open-drain selection 5 6 read-write __reserve0 0 is always read out. 2 4 read __reserve1 0 is always read out. 6 7 read IOP4OE Port 4 Output Enable Register 0x54 8 read-write n P44OE P44 output enable 4 5 read-write P45OE P45 output enable 5 6 read-write P46OE P46 output enable 6 7 read-write __reserve0 0 is always read out. 3 4 read IOP4OUT Port 4 Output Register 0x4 8 read-write n P44OUT Set output data of P44 4 5 read-write P45OUT Set output data of P45 5 6 read-write P46OUT Set output data of P46 6 7 read-write __reserve0 0 is always read out. 3 4 read IOP4PLU Port 4 Pull-up Control Register 0xC4 8 read-write n P44PLU P44 pull-up resistor selection 4 5 read-write P45PLU P45 pull-up resistor selection 5 6 read-write P46PLU P46 pull-up resistor selection 6 7 read-write __reserve0 0 is always read out. 3 4 read IOP4SET Port 4 Output Set Register 0x24 8 read-write n P44SET Set P44OUT 4 5 write P45SET Set P45OUT 5 6 write P46SET Set P46OUT 6 7 write __reserve0 0 is always read out. 3 4 read IOP4TGL Port 4 Output Toggle Register 0x34 8 read-write n P44TGL Invert P44OUT 4 5 write P45TGL Invert P45OUT 5 6 write P46TGL Invert P46OUT 6 7 write __reserve0 0 is always read out. 3 4 read IOP5CLR Port 5 Output Clear Register 0x15 8 read-write n P50CLR Clear P50OUT 0 1 write P51CLR Clear P51OUT 1 2 write P52CLR Clear P52OUT 2 3 write P53CLR Clear P53OUT 3 4 write P54CLR Clear P54OUT 4 5 write P55CLR Clear P55OUT 5 6 write P56CLR Clear P56OUT 6 7 write P57CLR Clear P57OUT 7 8 write IOP5IE Port 5 Input Enable Register 0x65 8 read-write n P50IE P50 input enable 0 1 read-write P51IE P51 input enable 1 2 read-write P52IE P52 input enable 2 3 read-write P53IE P53 input enable 3 4 read-write P54IE P54 input enable 4 5 read-write P55IE P55 input enable 5 6 read-write P56IE P56 input enable 6 7 read-write P57IE P57 input enable 7 8 read-write IOP5ILV Port 5 Input Level Selection Register 0xE5 8 read-write n P52ILV P52 Input level selection 2 3 read-write P53ILV P53 Input level selection 3 4 read-write __reserve0 0 is always read out. 0 2 read __reserve1 0 is always read out. 4 8 read IOP5IN Port 5 Input Register 0x45 8 read-write n P50IN Input data of P50 is read out. 0 1 read P51IN Input data of P51 is read out. 1 2 read P52IN Input data of P52 is read out. 2 3 read P53IN Input data of P53 is read out. 3 4 read P54IN Input data of P54 is read out. 4 5 read P55IN Input data of P55 is read out. 5 6 read P56IN Input data of P56 is read out. 6 7 read P57IN Input data of P57 is read out. 7 8 read IOP5MD Port 5 Mode Register 0x94 32 read-write n P50MD P50 function selection 0 4 read-write P51MD P51 function selection 4 8 read-write P52MD P52 function selection 8 12 read-write P53MD P53 function selection 12 16 read-write P54MD P54 function selection 16 20 read-write P55MD P55 function selection 20 24 read-write P56MD P56 function selection 24 28 read-write P57MD P57 function selection 28 32 read-write IOP5ODC Port 5 Nch Open-drain Control Register 0x75 8 read-write n P50ODC P50 Nch open-drain selection 0 1 read-write P52ODC P52 Nch open-drain selection 2 3 read-write P53ODC P53 Nch open-drain selection 3 4 read-write P55ODC P55 Nch open-drain selection 5 6 read-write P56ODC P56 Nch open-drain selection 6 7 read-write P57ODC P57 Nch open-drain selection 7 8 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 5 read IOP5OE Port 5 Output Enable Register 0x55 8 read-write n P50OE P50 output enable 0 1 read-write P51OE P51 output enable 1 2 read-write P52OE P52 output enable 2 3 read-write P53OE P53 output enable 3 4 read-write P54OE P54 output enable 4 5 read-write P55OE P55 output enable 5 6 read-write P56OE P56 output enable 6 7 read-write P57OE P57 output enable 7 8 read-write IOP5OUT Port 5 Output Register 0x5 8 read-write n P50OUT Set output data of P50 0 1 read-write P51OUT Set output data of P51 1 2 read-write P52OUT Set output data of P52 2 3 read-write P53OUT Set output data of P53 3 4 read-write P54OUT Set output data of P54 4 5 read-write P55OUT Set output data of P55 5 6 read-write P56OUT Set output data of P56 6 7 read-write P57OUT Set output data of P57 7 8 read-write IOP5PLU Port 5 Pull-up Control Register 0xC5 8 read-write n P50PLU P50 pull-up resistor selection 0 1 read-write P51PLU P51 pull-up resistor selection 1 2 read-write P52PLU P52 pull-up resistor selection 2 3 read-write P53PLU P53 pull-up resistor selection 3 4 read-write P54PLU P54 pull-up resistor selection 4 5 read-write P55PLU P55 pull-up resistor selection 5 6 read-write P56PLU P56 pull-up resistor selection 6 7 read-write P57PLU P57 pull-up resistor selection 7 8 read-write IOP5SET Port 5 Output Set Register 0x25 8 read-write n P50SET Set P50OUT 0 1 write P51SET Set P51OUT 1 2 write P52SET Set P52OUT 2 3 write P53SET Set P53OUT 3 4 write P54SET Set P54OUT 4 5 write P55SET Set P55OUT 5 6 write P56SET Set P56OUT 6 7 write P57SET Set P57OUT 7 8 write IOP5TGL Port 5 Output Toggle Register 0x35 8 read-write n P50TGL Invert P50OUT 0 1 write P51TGL Invert P51OUT 1 2 write P52TGL Invert P52OUT 2 3 write P53TGL Invert P53OUT 3 4 write P54TGL Invert P54OUT 4 5 write P55TGL Invert P55OUT 5 6 write P56TGL Invert P56OUT 6 7 write P57TGL Invert P57OUT 7 8 write IOP6CLR Port 6 Output Clear Register 0x16 8 read-write n P60CLR Clear P60OUT 0 1 write P61CLR Clear P61OUT 1 2 write P62CLR Clear P62OUT 2 3 write IOP6IE Port 6 Input Enable Register 0x66 8 read-write n P60IE P60 input enable 0 1 read-write P61IE P61 input enable 1 2 read-write P62IE P62 input enable 2 3 read-write IOP6IN Port 6 Input Register 0x46 8 read-write n P60IN Input data of P60 is read out. 0 1 read P61IN Input data of P61 is read out. 1 2 read P62IN Input data of P62 is read out. 2 3 read IOP6MD Port 6 Mode Register 0x98 32 read-write n P60MD P60 function selection 0 4 read-write P61MD P61 function selection 4 8 read-write P62MD P62 function selection 8 12 read-write IOP6ODC Port 6 Nch Open-drain Control Register 0x76 8 read-write n P61ODC P61 Nch open-drain selection 1 2 read-write P62ODC P62 Nch open-drain selection 2 3 read-write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 4 8 read IOP6OE Port 6 Output Enable Register 0x56 8 read-write n P60OE P60 output enable 0 1 read-write P61OE P61 output enable 1 2 read-write P62OE P62 output enable 2 3 read-write IOP6OUT Port 6 Output Register 0x6 8 read-write n P60OUT Set output data of P60 0 1 read-write P61OUT Set output data of P61 1 2 read-write P62OUT Set output data of P62 2 3 read-write IOP6PLU Port 6 Pull-up Control Register 0xC6 8 read-write n P60PLU P60 pull-up resistor selection 0 1 read-write P61PLU P61 pull-up resistor selection 1 2 read-write P62PLU P62 pull-up resistor selection 2 3 read-write IOP6SET Port 6 Output Set Register 0x26 8 read-write n P60SET Set P60OUT 0 1 write P61SET Set P61OUT 1 2 write P62SET Set P62OUT 2 3 write IOP6TGL Port 6 Output Toggle Register 0x36 8 read-write n P60TGL Invert P60OUT 0 1 write P61TGL Invert P61OUT 1 2 write P62TGL Invert P62OUT 2 3 write IOP7CLR Port 7 Output Clear Register 0x17 8 read-write n P70CLR Clear P70OUT 0 1 write P71CLR Clear P71OUT 1 2 write IOP7IE Port 7 Input Enable Register 0x67 8 read-write n P70IE P70 input enable 0 1 read-write P71IE P71 input enable 1 2 read-write IOP7IN Port 7 Input Register 0x47 8 read-write n P70IN Input data of P70 is read out. 0 1 read P71IN Input data of P71 is read out. 1 2 read IOP7MD Port 7 Mode Register 0x9C 32 read-write n P70MD P70 function selection 0 4 read-write P71MD P71 function selection 4 8 read-write IOP7OE Port 7 Output Enable Register 0x57 8 read-write n P70OE P70 output enable 0 1 read-write P71OE P71 output enable 1 2 read-write IOP7OUT Port 7 Output Register 0x7 8 read-write n P70OUT Set output data of P70 0 1 read-write P71OUT Set output data of P71 1 2 read-write IOP7PLU Port 7 Pull-up Control Register 0xC7 8 read-write n P70PLU P70 pull-up resistor selection 0 1 read-write P71PLU P71 pull-up resistor selection 1 2 read-write IOP7SET Port 7 Output Set Register 0x27 8 read-write n P70SET Set P70OUT 0 1 write P71SET Set P71OUT 1 2 write IOP7TGL Port 7 Output Toggle Register 0x37 8 read-write n P70TGL Invert P70OUT 0 1 write P71TGL Invert P71OUT 1 2 write IOP8CLR Port 8 Output Clear Register 0x18 8 read-write n P80CLR Clear P80OUT 0 1 write P81CLR Clear P81OUT 1 2 write P82CLR Clear P82OUT 2 3 write P83CLR Clear P83OUT 3 4 write P84CLR Clear P84OUT 4 5 write P85CLR Clear P85OUT 5 6 write IOP8IE Port 8 Input Enable Register 0x68 8 read-write n P80IE P80 input enable 0 1 read-write P81IE P81 input enable 1 2 read-write P82IE P82 input enable 2 3 read-write P83IE P83 input enable 3 4 read-write P84IE P84 input enable 4 5 read-write P85IE P85 input enable 5 6 read-write IOP8IN Port 8 Input Register 0x48 8 read-write n P80IN Input data of P80 is read out. 0 1 read P81IN Input data of P81 is read out. 1 2 read P82IN Input data of P82 is read out. 2 3 read P83IN Input data of P83 is read out. 3 4 read P84IN Input data of P84 is read out. 4 5 read P85IN Input data of P85 is read out. 5 6 read IOP8MD Port 8 Mode Register 0xA0 32 read-write n P80MD P80 function selection 0 4 read-write P81MD P81 function selection 4 8 read-write P82MD P82 function selection 8 12 read-write P83MD P83 function selection 12 16 read-write P84MD P84 function selection 16 20 read-write P85MD P85 function selection 20 24 read-write IOP8OE Port 8 Output Enable Register 0x58 8 read-write n P80OE P80 output enable 0 1 read-write P81OE P81 output enable 1 2 read-write P82OE P82 output enable 2 3 read-write P83OE P83 output enable 3 4 read-write P84OE P84 output enable 4 5 read-write P85OE P85 output enable 5 6 read-write IOP8OUT Port 8 Output Register 0x8 8 read-write n P80OUT Set output data of P80 0 1 read-write P81OUT Set output data of P81 1 2 read-write P82OUT Set output data of P82 2 3 read-write P83OUT Set output data of P83 3 4 read-write P84OUT Set output data of P84 4 5 read-write P85OUT Set output data of P85 5 6 read-write IOP8PLU Port 8 Pull-up Control Register 0xC8 8 read-write n P80PLU P80 pull-up resistor selection 0 1 read-write P81PLU P81 pull-up resistor selection 1 2 read-write P82PLU P82 pull-up resistor selection 2 3 read-write P83PLU P83 pull-up resistor selection 3 4 read-write P84PLU P84 pull-up resistor selection 4 5 read-write P85PLU P85 pull-up resistor selection 5 6 read-write IOP8SET Port 8 Output Set Register 0x28 8 read-write n P80SET Set P80OUT 0 1 write P81SET Set P81OUT 1 2 write P82SET Set P82OUT 2 3 write P83SET Set P83OUT 3 4 write P84SET Set P84OUT 4 5 write P85SET Set P85OUT 5 6 write IOP8TGL Port 8 Output Toggle Register 0x38 8 read-write n P80TGL Invert P80OUT 0 1 write P81TGL Invert P81OUT 1 2 write P82TGL Invert P82OUT 2 3 write P83TGL Invert P83OUT 3 4 write P84TGL Invert P84OUT 4 5 write P85TGL Invert P85OUT 5 6 write IOP9CLR Port 9 Output Clear Register 0x19 8 read-write n P90CLR Clear P90OUT 0 1 write P91CLR Clear P91OUT 1 2 write P92CLR Clear P92OUT 2 3 write P93CLR Clear P93OUT 3 4 write P94CLR Clear P94OUT 4 5 write P95CLR Clear P95OUT 5 6 write IOP9IE Port 9 Input Enable Register 0x69 8 read-write n P90IE P90 input enable 0 1 read-write P91IE P91 input enable 1 2 read-write P92IE P92 input enable 2 3 read-write P93IE P93 input enable 3 4 read-write P94IE P94 input enable 4 5 read-write P95IE P95 input enable 5 6 read-write IOP9IN Port 9 Input Register 0x49 8 read-write n P90IN Input data of P90 is read out. 0 1 read P91IN Input data of P91 is read out. 1 2 read P92IN Input data of P92 is read out. 2 3 read P93IN Input data of P93 is read out. 3 4 read P94IN Input data of P94 is read out. 4 5 read P95IN Input data of P95 is read out. 5 6 read IOP9MD Port 9 Mode Register 0xA4 32 read-write n P90MD P90 function selection 0 4 read-write P91MD P91 function selection 4 8 read-write P92MD P92 function selection 8 12 read-write P93MD P93 function selection 12 16 read-write P94MD P94 function selection 16 20 read-write P95MD P95 function selection 20 24 read-write IOP9OE Port 9 Output Enable Register 0x59 8 read-write n P90OE P90 output enable 0 1 read-write P91OE P91 output enable 1 2 read-write P92OE P92 output enable 2 3 read-write P93OE P93 output enable 3 4 read-write P94OE P94 output enable 4 5 read-write P95OE P95 output enable 5 6 read-write IOP9OUT Port 9 Output Register 0x9 8 read-write n P90OUT Set output data of P90 0 1 read-write P91OUT Set output data of P91 1 2 read-write P92OUT Set output data of P92 2 3 read-write P93OUT Set output data of P93 3 4 read-write P94OUT Set output data of P94 4 5 read-write P95OUT Set output data of P95 5 6 read-write IOP9PLU Port 9 Pull-up Control Register 0xC9 8 read-write n P90PLU P90 pull-up resistor selection 0 1 read-write P91PLU P91 pull-up resistor selection 1 2 read-write P92PLU P92 pull-up resistor selection 2 3 read-write P93PLU P93 pull-up resistor selection 3 4 read-write P94PLU P94 pull-up resistor selection 4 5 read-write P95PLU P95 pull-up resistor selection 5 6 read-write IOP9SET Port 9 Output Set Register 0x29 8 read-write n P90SET Set P90OUT 0 1 write P91SET Set P91OUT 1 2 write P92SET Set P92OUT 2 3 write P93SET Set P93OUT 3 4 write P94SET Set P94OUT 4 5 write P95SET Set P95OUT 5 6 write IOP9TGL Port 9 Output Toggle Register 0x39 8 read-write n P90TGL Invert P90OUT 0 1 write P91TGL Invert P91OUT 1 2 write P92TGL Invert P92OUT 2 3 write P93TGL Invert P93OUT 3 4 write P94TGL Invert P94OUT 4 5 write P95TGL Invert P95OUT 5 6 write IOPACLR Port A Output Clear Register 0x1A 8 read-write n PA0CLR Clear PA0OUT 0 1 write PA1CLR Clear PA1OUT 1 2 write PA2CLR Clear PA2OUT 2 3 write PA3CLR Clear PA3OUT 3 4 write PA4CLR Clear PA4OUT 4 5 write PA5CLR Clear PA5OUT 5 6 write IOPAIE Port A Input Enable Register 0x6A 8 read-write n PA0IE PA0 input enable 0 1 read-write PA1IE PA1 input enable 1 2 read-write PA2IE PA2 input enable 2 3 read-write PA3IE PA3 input enable 3 4 read-write PA4IE PA4 input enable 4 5 read-write PA5IE PA5 input enable 5 6 read-write IOPAIN Port A Input Register 0x4A 8 read-write n PA0IN Input data of PA0 is read out. 0 1 read PA1IN Input data of PA1 is read out. 1 2 read PA2IN Input data of PA2 is read out. 2 3 read PA3IN Input data of PA3 is read out. 3 4 read PA4IN Input data of PA4 is read out. 4 5 read PA5IN Input data of PA5 is read out. 5 6 read IOPAMD Port A Mode Register 0xA8 32 read-write n PA0MD PA0 function selection 0 4 read-write PA1MD PA1 function selection 4 8 read-write PA2MD PA2 function selection 8 12 read-write PA3MD PA3 function selection 12 16 read-write PA4MD PA4 function selection 16 20 read-write PA5MD PA5 function selection 20 24 read-write IOPAOE Port A Output Enable Register 0x5A 8 read-write n PA0OE PA0 output enable 0 1 read-write PA1OE PA1 output enable 1 2 read-write PA2OE PA2 output enable 2 3 read-write PA3OE PA3 output enable 3 4 read-write PA4OE PA4 output enable 4 5 read-write PA5OE PA5 output enable 5 6 read-write IOPAOUT Port A Output Register 0xA 8 read-write n PA0OUT Set output data of PA0 0 1 read-write PA1OUT Set output data of PA1 1 2 read-write PA2OUT Set output data of PA2 2 3 read-write PA3OUT Set output data of PA3 3 4 read-write PA4OUT Set output data of PA4 4 5 read-write PA5OUT Set output data of PA5 5 6 read-write IOPAPLU Port A Pull-up Control Register 0xCA 8 read-write n PA0PLU PA0 pull-up resistor selection 0 1 read-write PA1PLU PA1 pull-up resistor selection 1 2 read-write PA2PLU PA2 pull-up resistor selection 2 3 read-write PA3PLU PA3 pull-up resistor selection 3 4 read-write PA4PLU PA4 pull-up resistor selection 4 5 read-write PA5PLU PA5 pull-up resistor selection 5 6 read-write IOPASET Port A Output Set Register 0x2A 8 read-write n PA0SET Set PA0OUT 0 1 write PA1SET Set PA1OUT 1 2 write PA2SET Set PA2OUT 2 3 write PA3SET Set PA3OUT 3 4 write PA4SET Set PA4OUT 4 5 write PA5SET Set PA5OUT 5 6 write IOPATGL Port A Output Toggle Register 0x3A 8 read-write n PA0TGL Invert PA0OUT 0 1 write PA1TGL Invert PA1OUT 1 2 write PA2TGL Invert PA2OUT 2 3 write PA3TGL Invert PA3OUT 3 4 write PA4TGL Invert PA4OUT 4 5 write PA5TGL Invert PA5OUT 5 6 write IOPBCLR Port B Output Clear Register 0x1B 8 read-write n __reserve0 - 5 6 write IOPBIE Port B Input Enable Register 0x6B 8 read-write n __reserve0 - 5 6 read-write IOPBIN Port B Input Register 0x4B 8 read-write n __reserve0 Undefined value will be read 5 6 read IOPBMD Port B Mode Register 0xAC 32 read-write n __reserve0 - 20 24 read-write IOPBOE Port B Output Enable Register 0x5B 8 read-write n __reserve0 - 5 6 read-write IOPBOUT Port B Output Register 0xB 8 read-write n __reserve0 - 5 6 read-write IOPBPLU Port B Pull-up Control Register 0xCB 8 read-write n __reserve0 - 5 6 read-write IOPBSET Port B Output Set Register 0x2B 8 read-write n __reserve0 - 5 6 write IOPBTGL Port B Output Toggle Register 0x3B 8 read-write n __reserve0 - 5 6 write IOPCCLR Port C Output Clear Register 0x1C 8 read-write n PC4CLR Clear PC4OUT 4 5 write PC5CLR Clear PC5OUT 5 6 write PC6CLR Clear PC6OUT 6 7 write PC7CLR Clear PC7OUT 7 8 write __reserve0 0 is always read out. 0 4 read IOPCIE Port C Input Enable Register 0x6C 8 read-write n PC0IE PC0 input enable 0 1 read-write PC1IE PC1 input enable 1 2 read-write PC2IE PC2 input enable 2 3 read-write PC3IE PC3 input enable 3 4 read-write PC4IE PC4 input enable 4 5 read-write PC5IE PC5 input enable 5 6 read-write PC6IE PC6 input enable 6 7 read-write PC7IE PC7 input enable 7 8 read-write IOPCIN Port C Input Register 0x4C 8 read-write n PC0IN Input data of PC0 is read out. 0 1 read PC1IN Input data of PC1 is read out. 1 2 read PC2IN Input data of PC2 is read out. 2 3 read PC3IN Input data of PC3 is read out. 3 4 read PC4IN Input data of PC4 is read out. 4 5 read PC5IN Input data of PC5 is read out. 5 6 read PC6IN Input data of PC6 is read out. 6 7 read PC7IN Input data of PC7 is read out. 7 8 read IOPCMD Port C Mode Register 0xB0 32 read-write n PC0MD PC0 function selection 0 4 read-write PC1MD PC1 function selection 4 8 read-write PC2MD PC2 function selection 8 12 read-write PC3MD PC3 function selection 12 16 read-write PC4MD PC4 function selection 16 20 read-write PC5MD PC5 function selection 20 24 read-write PC6MD PC6 function selection 24 28 read-write PC7MD PC7 function selection 28 32 read-write IOPCOE Port C Output Enable Register 0x5C 8 read-write n PC4OE PC4 output enable 4 5 read-write PC5OE PC5 output enable 5 6 read-write PC6OE PC6 output enable 6 7 read-write PC7OE PC7 output enable 7 8 read-write __reserve0 0 is always read out. 0 4 read IOPCOUT Port C Output Register 0xC 8 read-write n PC4OUT Set output data of PC4 4 5 read-write PC5OUT Set output data of PC5 5 6 read-write PC6OUT Set output data of PC6 6 7 read-write PC7OUT Set output data of PC7 7 8 read-write __reserve0 0 is always read out. 0 4 read IOPCPLU Port C Pull-up Control Register 0xCC 8 read-write n PC4PLU PC4 pull-up resistor selection 4 5 read-write PC5PLU PC5 pull-up resistor selection 5 6 read-write PC6PLU PC6 pull-up resistor selection 6 7 read-write PC7PLU PC7 pull-up resistor selection 7 8 read-write __reserve0 0 is always read out. 0 4 read IOPCSET Port C Output Set Register 0x2C 8 read-write n PC4SET Set PC4OUT 4 5 write PC5SET Set PC5OUT 5 6 write PC6SET Set PC6OUT 6 7 write PC7SET Set PC7OUT 7 8 write __reserve0 0 is always read out. 0 4 read IOPCTGL Port C Output Toggle Register 0x3C 8 read-write n PC4TGL Invert PC4OUT 4 5 write PC5TGL Invert PC5OUT 5 6 write PC6TGL Invert PC6OUT 6 7 write PC7TGL Invert PC7OUT 7 8 write __reserve0 0 is always read out. 0 4 read IOPDCLR Port D Output Clear Register 0x1D 8 read-write n PD2CLR Clear PD2OUT 2 3 write PD3CLR Clear PD3OUT 3 4 write PD6CLR Clear PD6OUT 6 7 write PD7CLR Clear PD7OUT 7 8 write __reserve0 0 is always read out. 0 2 read IOPDIE Port D Input Enable Register 0x6D 8 read-write n PD0IE PD0 input enable 0 1 read-write PD1IE PD1 input enable 1 2 read-write PD2IE PD2 input enable 2 3 read-write PD3IE PD3 input enable 3 4 read-write PD6IE PD6 input enable 6 7 read-write PD7IE PD7 input enable 7 8 read-write IOPDIN Port D Input Register 0x4D 8 read-write n PD0IN Input data of PD0 is read out. 0 1 read PD1IN Input data of PD1 is read out. 1 2 read PD2IN Input data of PD2 is read out. 2 3 read PD3IN Input data of PD3 is read out. 3 4 read PD6IN Input data of PD6 is read out. 6 7 read PD7IN Input data of PD7 is read out. 7 8 read IOPDMD Port D Mode Register 0xB4 32 read-write n PD0MD PD0 function selection 0 4 read-write PD1MD PD1 function selection 4 8 read-write PD2MD PD2 function selection 8 12 read-write PD3MD PD3 function selection 12 16 read-write PD6MD PD6 function selection 24 28 read-write PD7MD PD7 function selection 28 32 read-write IOPDOE Port D Output Enable Register 0x5D 8 read-write n PD2OE PD2 output enable 2 3 read-write PD3OE PD3 output enable 3 4 read-write PD6OE PD6 output enable 6 7 read-write PD7OE PD7 output enable 7 8 read-write __reserve0 0 is always read out. 0 2 read IOPDOUT Port D Output Register 0xD 8 read-write n PD2OUT Set output data of PD2 2 3 read-write PD3OUT Set output data of PD3 3 4 read-write PD6OUT Set output data of PD6 6 7 read-write PD7OUT Set output data of PD7 7 8 read-write __reserve0 0 is always read out. 0 2 read IOPDPLU Port D Pull-up Control Register 0xCD 8 read-write n PD2PLU PD2 pull-up resistor selection 2 3 read-write PD3PLU PD3 pull-up resistor selection 3 4 read-write PD6PLU PD6 pull-up resistor selection 6 7 read-write PD7PLU PD7 pull-up resistor selection 7 8 read-write __reserve0 0 is always read out. 0 2 read IOPDSET Port D Output Set Register 0x2D 8 read-write n PD2SET Set PD2OUT 2 3 write PD3SET Set PD3OUT 3 4 write PD6SET Set PD6OUT 6 7 write PD7SET Set PD7OUT 7 8 write __reserve0 0 is always read out. 0 2 read IOPDTGL Port D Output Toggle Register 0x3D 8 read-write n PD2TGL Invert PD2OUT 2 3 write PD3TGL Invert PD3OUT 3 4 write PD6TGL Invert PD6OUT 6 7 write PD7TGL Invert PD7OUT 7 8 write __reserve0 0 is always read out. 0 2 read IOPECLR Port E Output Clear Register 0x1E 8 read-write n PE2CLR Clear PE2OUT 2 3 write PE3CLR Clear PE3OUT 3 4 write PE4CLR Clear PE4OUT 4 5 write PE5CLR Clear PE5OUT 5 6 write PE6CLR Clear PE6OUT 6 7 write __reserve0 0 is always read out. 0 2 read IOPEIE Port E Input Enable Register 0x6E 8 read-write n PE0IE PE0 input enable 0 1 read-write PE1IE PE1 input enable 1 2 read-write PE2IE PE2 input enable 2 3 read-write PE3IE PE3 input enable 3 4 read-write PE4IE PE4 input enable 4 5 read-write PE5IE PE5 input enable 5 6 read-write PE6IE PE6 input enable 6 7 read-write IOPEIN Port E Input Register 0x4E 8 read-write n PE0IN Input data of PE0 is read out. 0 1 read PE1IN Input data of PE1 is read out. 1 2 read PE2IN Input data of PE2 is read out. 2 3 read PE3IN Input data of PE3 is read out. 3 4 read PE4IN Input data of PE4 is read out. 4 5 read PE5IN Input data of PE5 is read out. 5 6 read PE6IN Input data of PE6 is read out. 6 7 read IOPEMD Port E Mode Register 0xB8 32 read-write n PE0MD PE0 function selection 0 4 read-write PE1MD PE1 function selection 4 8 read-write PE2MD PE2 function selection 8 12 read-write PE3MD PE3 function selection 12 16 read-write PE4MD PE4 function selection 16 20 read-write PE5MD PE5 function selection 20 24 read-write PE6MD PE6 function selection 24 28 read-write IOPEOE Port E Output Enable Register 0x5E 8 read-write n PE2OE PE2 output enable 2 3 read-write PE3OE PE3 output enable 3 4 read-write PE4OE PE4 output enable 4 5 read-write PE5OE PE5 output enable 5 6 read-write PE6OE PE6 output enable 6 7 read-write __reserve0 0 is always read out. 0 2 read IOPEOUT Port E Output Register 0xE 8 read-write n PE2OUT Set output data of PE2 2 3 read-write PE3OUT Set output data of PE3 3 4 read-write PE4OUT Set output data of PE4 4 5 read-write PE5OUT Set output data of PE5 5 6 read-write PE6OUT Set output data of PE6 6 7 read-write __reserve0 0 is always read out. 0 2 read IOPEPLU Port E Pull-up Control Register 0xCE 8 read-write n PE2PLU PE2 pull-up resistor selection 2 3 read-write PE3PLU PE3 pull-up resistor selection 3 4 read-write PE4PLU PE4 pull-up resistor selection 4 5 read-write PE5PLU PE5 pull-up resistor selection 5 6 read-write PE6PLU PE6 pull-up resistor selection 6 7 read-write __reserve0 0 is always read out. 0 2 read IOPESET Port E Output Set Register 0x2E 8 read-write n PE2SET Set PE2OUT 2 3 write PE3SET Set PE3OUT 3 4 write PE4SET Set PE4OUT 4 5 write PE5SET Set PE5OUT 5 6 write PE6SET Set PE6OUT 6 7 write __reserve0 0 is always read out. 0 2 read IOPETGL Port E Output Toggle Register 0x3E 8 read-write n PE2TGL Invert PE2OUT 2 3 write PE3TGL Invert PE3OUT 3 4 write PE4TGL Invert PE4OUT 4 5 write PE5TGL Invert PE5OUT 5 6 write PE6TGL Invert PE6OUT 6 7 write __reserve0 0 is always read out. 0 2 read IOPFCLR Port F Output Clear Register 0x1F 8 read-write n PF0CLR Clear PF0OUT 0 1 write PF1CLR Clear PF1OUT 1 2 write IOPFIE Port F Input Enable Register 0x6F 8 read-write n PF0IE PF0 input enable 0 1 read-write PF1IE PF1 input enable 1 2 read-write IOPFIN Port F Input Register 0x4F 8 read-write n PF0IN Input data of PF0 is read out. 0 1 read PF1IN Input data of PF1 is read out. 1 2 read IOPFMD Port F Mode Register 0xBC 32 read-write n PF0MD PF0 function selection 0 4 read-write PF1MD PF1 function selection 4 8 read-write IOPFOE Port F Output Enable Register 0x5F 8 read-write n PF0OE PF0 output enable 0 1 read-write PF1OE PF1 output enable 1 2 read-write IOPFOUT Port F Output Register 0xF 8 read-write n PF0OUT Set output data of PF0 0 1 read-write PF1OUT Set output data of PF1 1 2 read-write IOPFPLU Port F Pull-up Control Register 0xCF 8 read-write n PF0PLU PF0 pull-up resistor selection 0 1 read-write PF1PLU PF1 pull-up resistor selection 1 2 read-write IOPFSET Port F Output Set Register 0x2F 8 read-write n PF0SET Set PF0OUT 0 1 write PF1SET Set PF1OUT 1 2 write IOPFTGL Port F Output Toggle Register 0x3F 8 read-write n PF0TGL Invert PF0OUT 0 1 write PF1TGL Invert PF1OUT 1 2 write PPWM Power Control PWM PPWM 0x0 0x0 0xF08 registers n G44 44 G45 45 G46 46 G47 47 G48 48 G49 49 G50 50 G51 51 G52 52 G53 53 G54 54 G55 55 G56 56 G57 57 G58 58 G59 59 G60 60 G61 61 G62 62 G63 63 G64 64 G65 65 G66 66 G67 67 G68 68 G69 69 G70 70 G71 71 G72 72 G73 73 G74 74 G75 75 G76 76 G77 77 G78 78 G79 79 GPWM0ADBC GPWM0 Sy0chro0ous Bi0ary Cou0ter Read Register 0x2C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM0ADIRQCNT GPWM0 A/D Start I0terrupt Output Co0trol Register 0x34 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM0ADST GPWM0 Sy0chro0ous Trigger Setti0g Register 0x28 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM0ADSTSEL GPWM0 Sy0chro0ous Trigger Polarity Selectio0 Register 0x2A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM0BC GPWM0BC Value Read Register 0xC 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM0BCSTR GPWM0BC Status Read Register 0xE 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM0DBUPDATE GPWM0 Double Buffer Updati0g E0able Register 0x50 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM0DDAT GPWM0 Output Shift Amou0t Setti0g Register 0x1A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM0DHRDAT GPWM0 High Resolutio0 Output Shift Amou0t Setti0g Register 0x18 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM0DTMCNT GPWM0 Dead Time Co0trol Register 0x20 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM0DTMSETA GPWM0 Dead Time Setti0g Register A 0x24 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM0DTMSETB GPWM0 Dead Time Setti0g Register B 0x26 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM0DUTYTRGA GPWM0 Duty Cut Factor Selectio0 Register A 0x48 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM0DUTYTRGB GPWM0 Duty Cut Factor Selectio0 Register B 0x4A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM0HRSET GPWM0 High Resolutio0 Cycle Setti0g Register 0x10 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM0IRQCNT GPWM0 UDF/OVF I0terrupt Output Co0trol Register 0x30 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM0MD GPWM0 Mode Register 0x0 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM0OFF GPWM0 Pi0 Protectio0 Co0trol Register 0x38 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM0OFFIRQA GPWM0 Pi0 Protectio0 Factor Selectio0 Register A 0x3C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM0OFFIRQB GPWM0 Pi0 Protectio0 Factor Selectio0 Register B 0x3E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM0OUTMD GPWM0 Output Polarity Co0trol Register 0x4 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM0PERITRGA GPWM0 Period Cut Factor Selectio0 Register A 0x4C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM0PERITRGB GPWM0 Period Cut Factor Selectio0 Register B 0x4E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM0PULSECNT GPWM0 Pulse Co0trol Register 0x40 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM0PULSEST GPWM0 Pulse Co0trol Status Register 0x44 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM0SEL GPWM0 Output Co0trol Register 0x8 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM0SET GPWM0 Cycle Setti0g Register 0x12 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM0TCMP GPWM0 Phase Compariso0 Setti0g Register 0x16 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM0TCMPHR GPWM0 High Resolutio0 Phase Compariso0 Setti0g Register 0x14 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM1ADBC GPWM1 Sy1chro1ous Bi1ary Cou1ter Read Register 0x12C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM1ADIRQCNT GPWM1 A/D Start I1terrupt Output Co1trol Register 0x134 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM1ADST GPWM1 Sy1chro1ous Trigger Setti1g Register 0x128 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM1ADSTSEL GPWM1 Sy1chro1ous Trigger Polarity Selectio1 Register 0x12A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM1BC GPWM1BC Value Read Register 0x10C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM1BCSTR GPWM1BC Status Read Register 0x10E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM1DBUPDATE GPWM1 Double Buffer Updati1g E1able Register 0x150 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM1DDAT GPWM1 Output Shift Amou1t Setti1g Register 0x11A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM1DHRDAT GPWM1 High Resolutio1 Output Shift Amou1t Setti1g Register 0x118 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM1DTMCNT GPWM1 Dead Time Co1trol Register 0x120 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM1DTMSETA GPWM1 Dead Time Setti1g Register A 0x124 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM1DTMSETB GPWM1 Dead Time Setti1g Register B 0x126 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM1DUTYTRGA GPWM1 Duty Cut Factor Selectio1 Register A 0x148 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM1DUTYTRGB GPWM1 Duty Cut Factor Selectio1 Register B 0x14A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM1HRSET GPWM1 High Resolutio1 Cycle Setti1g Register 0x110 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM1IRQCNT GPWM1 UDF/OVF I1terrupt Output Co1trol Register 0x130 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM1MD GPWM1 Mode Register 0x100 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM1OFF GPWM1 Pi1 Protectio1 Co1trol Register 0x138 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM1OFFIRQA GPWM1 Pi1 Protectio1 Factor Selectio1 Register A 0x13C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM1OFFIRQB GPWM1 Pi1 Protectio1 Factor Selectio1 Register B 0x13E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM1OUTMD GPWM1 Output Polarity Co1trol Register 0x104 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM1PERITRGA GPWM1 Period Cut Factor Selectio1 Register A 0x14C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM1PERITRGB GPWM1 Period Cut Factor Selectio1 Register B 0x14E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM1PULSECNT GPWM1 Pulse Co1trol Register 0x140 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM1PULSEST GPWM1 Pulse Co1trol Status Register 0x144 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM1SEL GPWM1 Output Co1trol Register 0x108 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM1SET GPWM1 Cycle Setti1g Register 0x112 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM1TCMP GPWM1 Phase Compariso1 Setti1g Register 0x116 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM1TCMPHR GPWM1 High Resolutio1 Phase Compariso1 Setti1g Register 0x114 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM2ADBC GPWM2 Sy2chro2ous Bi2ary Cou2ter Read Register 0x22C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM2ADIRQCNT GPWM2 A/D Start I2terrupt Output Co2trol Register 0x234 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM2ADST GPWM2 Sy2chro2ous Trigger Setti2g Register 0x228 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM2ADSTSEL GPWM2 Sy2chro2ous Trigger Polarity Selectio2 Register 0x22A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM2BC GPWM2BC Value Read Register 0x20C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM2BCSTR GPWM2BC Status Read Register 0x20E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM2DBUPDATE GPWM2 Double Buffer Updati2g E2able Register 0x250 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM2DDAT GPWM2 Output Shift Amou2t Setti2g Register 0x21A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM2DHRDAT GPWM2 High Resolutio2 Output Shift Amou2t Setti2g Register 0x218 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM2DTMCNT GPWM2 Dead Time Co2trol Register 0x220 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM2DTMSETA GPWM2 Dead Time Setti2g Register A 0x224 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM2DTMSETB GPWM2 Dead Time Setti2g Register B 0x226 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM2DUTYTRGA GPWM2 Duty Cut Factor Selectio2 Register A 0x248 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM2DUTYTRGB GPWM2 Duty Cut Factor Selectio2 Register B 0x24A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM2HRSET GPWM2 High Resolutio2 Cycle Setti2g Register 0x210 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM2IRQCNT GPWM2 UDF/OVF I2terrupt Output Co2trol Register 0x230 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM2MD GPWM2 Mode Register 0x200 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM2OFF GPWM2 Pi2 Protectio2 Co2trol Register 0x238 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM2OFFIRQA GPWM2 Pi2 Protectio2 Factor Selectio2 Register A 0x23C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM2OFFIRQB GPWM2 Pi2 Protectio2 Factor Selectio2 Register B 0x23E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM2OUTMD GPWM2 Output Polarity Co2trol Register 0x204 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM2PERITRGA GPWM2 Period Cut Factor Selectio2 Register A 0x24C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM2PERITRGB GPWM2 Period Cut Factor Selectio2 Register B 0x24E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM2PULSECNT GPWM2 Pulse Co2trol Register 0x240 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM2PULSEST GPWM2 Pulse Co2trol Status Register 0x244 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM2SEL GPWM2 Output Co2trol Register 0x208 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM2SET GPWM2 Cycle Setti2g Register 0x212 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM2TCMP GPWM2 Phase Compariso2 Setti2g Register 0x216 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM2TCMPHR GPWM2 High Resolutio2 Phase Compariso2 Setti2g Register 0x214 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM3ADBC GPWM3 Sy3chro3ous Bi3ary Cou3ter Read Register 0x32C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM3ADIRQCNT GPWM3 A/D Start I3terrupt Output Co3trol Register 0x334 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM3ADST GPWM3 Sy3chro3ous Trigger Setti3g Register 0x328 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM3ADSTSEL GPWM3 Sy3chro3ous Trigger Polarity Selectio3 Register 0x32A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM3BC GPWM3BC Value Read Register 0x30C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM3BCSTR GPWM3BC Status Read Register 0x30E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM3DBUPDATE GPWM3 Double Buffer Updati3g E3able Register 0x350 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM3DDAT GPWM3 Output Shift Amou3t Setti3g Register 0x31A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM3DHRDAT GPWM3 High Resolutio3 Output Shift Amou3t Setti3g Register 0x318 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM3DTMCNT GPWM3 Dead Time Co3trol Register 0x320 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM3DTMSETA GPWM3 Dead Time Setti3g Register A 0x324 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM3DTMSETB GPWM3 Dead Time Setti3g Register B 0x326 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM3DUTYTRGA GPWM3 Duty Cut Factor Selectio3 Register A 0x348 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM3DUTYTRGB GPWM3 Duty Cut Factor Selectio3 Register B 0x34A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM3HRSET GPWM3 High Resolutio3 Cycle Setti3g Register 0x310 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM3IRQCNT GPWM3 UDF/OVF I3terrupt Output Co3trol Register 0x330 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM3MD GPWM3 Mode Register 0x300 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM3OFF GPWM3 Pi3 Protectio3 Co3trol Register 0x338 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM3OFFIRQA GPWM3 Pi3 Protectio3 Factor Selectio3 Register A 0x33C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM3OFFIRQB GPWM3 Pi3 Protectio3 Factor Selectio3 Register B 0x33E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM3OUTMD GPWM3 Output Polarity Co3trol Register 0x304 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM3PERITRGA GPWM3 Period Cut Factor Selectio3 Register A 0x34C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM3PERITRGB GPWM3 Period Cut Factor Selectio3 Register B 0x34E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM3PULSECNT GPWM3 Pulse Co3trol Register 0x340 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM3PULSEST GPWM3 Pulse Co3trol Status Register 0x344 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM3SEL GPWM3 Output Co3trol Register 0x308 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM3SET GPWM3 Cycle Setti3g Register 0x312 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM3TCMP GPWM3 Phase Compariso3 Setti3g Register 0x316 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM3TCMPHR GPWM3 High Resolutio3 Phase Compariso3 Setti3g Register 0x314 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM4ADBC GPWM4 Sy4chro4ous Bi4ary Cou4ter Read Register 0x42C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM4ADIRQCNT GPWM4 A/D Start I4terrupt Output Co4trol Register 0x434 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM4ADST GPWM4 Sy4chro4ous Trigger Setti4g Register 0x428 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM4ADSTSEL GPWM4 Sy4chro4ous Trigger Polarity Selectio4 Register 0x42A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM4BC GPWM4BC Value Read Register 0x40C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM4BCSTR GPWM4BC Status Read Register 0x40E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM4DBUPDATE GPWM4 Double Buffer Updati4g E4able Register 0x450 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM4DDAT GPWM4 Output Shift Amou4t Setti4g Register 0x41A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM4DHRDAT GPWM4 High Resolutio4 Output Shift Amou4t Setti4g Register 0x418 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM4DTMCNT GPWM4 Dead Time Co4trol Register 0x420 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM4DTMSETA GPWM4 Dead Time Setti4g Register A 0x424 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM4DTMSETB GPWM4 Dead Time Setti4g Register B 0x426 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM4DUTYTRGA GPWM4 Duty Cut Factor Selectio4 Register A 0x448 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM4DUTYTRGB GPWM4 Duty Cut Factor Selectio4 Register B 0x44A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM4HRSET GPWM4 High Resolutio4 Cycle Setti4g Register 0x410 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM4IRQCNT GPWM4 UDF/OVF I4terrupt Output Co4trol Register 0x430 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM4MD GPWM4 Mode Register 0x400 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM4OFF GPWM4 Pi4 Protectio4 Co4trol Register 0x438 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM4OFFIRQA GPWM4 Pi4 Protectio4 Factor Selectio4 Register A 0x43C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM4OFFIRQB GPWM4 Pi4 Protectio4 Factor Selectio4 Register B 0x43E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM4OUTMD GPWM4 Output Polarity Co4trol Register 0x404 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM4PERITRGA GPWM4 Period Cut Factor Selectio4 Register A 0x44C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM4PERITRGB GPWM4 Period Cut Factor Selectio4 Register B 0x44E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM4PULSECNT GPWM4 Pulse Co4trol Register 0x440 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM4PULSEST GPWM4 Pulse Co4trol Status Register 0x444 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM4SEL GPWM4 Output Co4trol Register 0x408 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM4SET GPWM4 Cycle Setti4g Register 0x412 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM4TCMP GPWM4 Phase Compariso4 Setti4g Register 0x416 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM4TCMPHR GPWM4 High Resolutio4 Phase Compariso4 Setti4g Register 0x414 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM5ADBC GPWM5 Sy5chro5ous Bi5ary Cou5ter Read Register 0x52C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM5ADIRQCNT GPWM5 A/D Start I5terrupt Output Co5trol Register 0x534 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM5ADST GPWM5 Sy5chro5ous Trigger Setti5g Register 0x528 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM5ADSTSEL GPWM5 Sy5chro5ous Trigger Polarity Selectio5 Register 0x52A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM5BC GPWM5BC Value Read Register 0x50C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM5BCSTR GPWM5BC Status Read Register 0x50E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM5DBUPDATE GPWM5 Double Buffer Updati5g E5able Register 0x550 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM5DDAT GPWM5 Output Shift Amou5t Setti5g Register 0x51A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM5DHRDAT GPWM5 High Resolutio5 Output Shift Amou5t Setti5g Register 0x518 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM5DTMCNT GPWM5 Dead Time Co5trol Register 0x520 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM5DTMSETA GPWM5 Dead Time Setti5g Register A 0x524 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM5DTMSETB GPWM5 Dead Time Setti5g Register B 0x526 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM5DUTYTRGA GPWM5 Duty Cut Factor Selectio5 Register A 0x548 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM5DUTYTRGB GPWM5 Duty Cut Factor Selectio5 Register B 0x54A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM5HRSET GPWM5 High Resolutio5 Cycle Setti5g Register 0x510 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM5IRQCNT GPWM5 UDF/OVF I5terrupt Output Co5trol Register 0x530 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM5MD GPWM5 Mode Register 0x500 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM5OFF GPWM5 Pi5 Protectio5 Co5trol Register 0x538 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM5OFFIRQA GPWM5 Pi5 Protectio5 Factor Selectio5 Register A 0x53C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM5OFFIRQB GPWM5 Pi5 Protectio5 Factor Selectio5 Register B 0x53E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM5OUTMD GPWM5 Output Polarity Co5trol Register 0x504 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM5PERITRGA GPWM5 Period Cut Factor Selectio5 Register A 0x54C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM5PERITRGB GPWM5 Period Cut Factor Selectio5 Register B 0x54E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM5PULSECNT GPWM5 Pulse Co5trol Register 0x540 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM5PULSEST GPWM5 Pulse Co5trol Status Register 0x544 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM5SEL GPWM5 Output Co5trol Register 0x508 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM5SET GPWM5 Cycle Setti5g Register 0x512 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM5TCMP GPWM5 Phase Compariso5 Setti5g Register 0x516 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM5TCMPHR GPWM5 High Resolutio5 Phase Compariso5 Setti5g Register 0x514 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM6ADBC GPWM6 Sy6chro6ous Bi6ary Cou6ter Read Register 0x62C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM6ADIRQCNT GPWM6 A/D Start I6terrupt Output Co6trol Register 0x634 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM6ADST GPWM6 Sy6chro6ous Trigger Setti6g Register 0x628 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM6ADSTSEL GPWM6 Sy6chro6ous Trigger Polarity Selectio6 Register 0x62A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM6BC GPWM6BC Value Read Register 0x60C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM6BCSTR GPWM6BC Status Read Register 0x60E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM6DBUPDATE GPWM6 Double Buffer Updati6g E6able Register 0x650 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM6DDAT GPWM6 Output Shift Amou6t Setti6g Register 0x61A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM6DHRDAT GPWM6 High Resolutio6 Output Shift Amou6t Setti6g Register 0x618 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM6DTMCNT GPWM6 Dead Time Co6trol Register 0x620 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM6DTMSETA GPWM6 Dead Time Setti6g Register A 0x624 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM6DTMSETB GPWM6 Dead Time Setti6g Register B 0x626 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM6DUTYTRGA GPWM6 Duty Cut Factor Selectio6 Register A 0x648 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM6DUTYTRGB GPWM6 Duty Cut Factor Selectio6 Register B 0x64A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM6HRSET GPWM6 High Resolutio6 Cycle Setti6g Register 0x610 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM6IRQCNT GPWM6 UDF/OVF I6terrupt Output Co6trol Register 0x630 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM6MD GPWM6 Mode Register 0x600 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM6OFF GPWM6 Pi6 Protectio6 Co6trol Register 0x638 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM6OFFIRQA GPWM6 Pi6 Protectio6 Factor Selectio6 Register A 0x63C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM6OFFIRQB GPWM6 Pi6 Protectio6 Factor Selectio6 Register B 0x63E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM6OUTMD GPWM6 Output Polarity Co6trol Register 0x604 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM6PERITRGA GPWM6 Period Cut Factor Selectio6 Register A 0x64C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM6PERITRGB GPWM6 Period Cut Factor Selectio6 Register B 0x64E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM6PULSECNT GPWM6 Pulse Co6trol Register 0x640 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM6PULSEST GPWM6 Pulse Co6trol Status Register 0x644 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM6SEL GPWM6 Output Co6trol Register 0x608 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM6SET GPWM6 Cycle Setti6g Register 0x612 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM6TCMP GPWM6 Phase Compariso6 Setti6g Register 0x616 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM6TCMPHR GPWM6 High Resolutio6 Phase Compariso6 Setti6g Register 0x614 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM7ADBC GPWM7 Sy7chro7ous Bi7ary Cou7ter Read Register 0x72C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM7ADIRQCNT GPWM7 A/D Start I7terrupt Output Co7trol Register 0x734 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM7ADST GPWM7 Sy7chro7ous Trigger Setti7g Register 0x728 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM7ADSTSEL GPWM7 Sy7chro7ous Trigger Polarity Selectio7 Register 0x72A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM7BC GPWM7BC Value Read Register 0x70C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM7BCSTR GPWM7BC Status Read Register 0x70E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM7DBUPDATE GPWM7 Double Buffer Updati7g E7able Register 0x750 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM7DDAT GPWM7 Output Shift Amou7t Setti7g Register 0x71A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM7DHRDAT GPWM7 High Resolutio7 Output Shift Amou7t Setti7g Register 0x718 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM7DTMCNT GPWM7 Dead Time Co7trol Register 0x720 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM7DTMSETA GPWM7 Dead Time Setti7g Register A 0x724 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM7DTMSETB GPWM7 Dead Time Setti7g Register B 0x726 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM7DUTYTRGA GPWM7 Duty Cut Factor Selectio7 Register A 0x748 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM7DUTYTRGB GPWM7 Duty Cut Factor Selectio7 Register B 0x74A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM7HRSET GPWM7 High Resolutio7 Cycle Setti7g Register 0x710 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM7IRQCNT GPWM7 UDF/OVF I7terrupt Output Co7trol Register 0x730 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM7MD GPWM7 Mode Register 0x700 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM7OFF GPWM7 Pi7 Protectio7 Co7trol Register 0x738 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM7OFFIRQA GPWM7 Pi7 Protectio7 Factor Selectio7 Register A 0x73C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM7OFFIRQB GPWM7 Pi7 Protectio7 Factor Selectio7 Register B 0x73E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM7OUTMD GPWM7 Output Polarity Co7trol Register 0x704 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM7PERITRGA GPWM7 Period Cut Factor Selectio7 Register A 0x74C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM7PERITRGB GPWM7 Period Cut Factor Selectio7 Register B 0x74E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM7PULSECNT GPWM7 Pulse Co7trol Register 0x740 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM7PULSEST GPWM7 Pulse Co7trol Status Register 0x744 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM7SEL GPWM7 Output Co7trol Register 0x708 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM7SET GPWM7 Cycle Setti7g Register 0x712 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM7TCMP GPWM7 Phase Compariso7 Setti7g Register 0x716 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM7TCMPHR GPWM7 High Resolutio7 Phase Compariso7 Setti7g Register 0x714 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM8ADBC GPWM8 Sy8chro8ous Bi8ary Cou8ter Read Register 0x82C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM8ADIRQCNT GPWM8 A/D Start I8terrupt Output Co8trol Register 0x834 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM8ADST GPWM8 Sy8chro8ous Trigger Setti8g Register 0x828 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM8ADSTSEL GPWM8 Sy8chro8ous Trigger Polarity Selectio8 Register 0x82A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM8BC GPWM8BC Value Read Register 0x80C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM8BCSTR GPWM8BC Status Read Register 0x80E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM8DBUPDATE GPWM8 Double Buffer Updati8g E8able Register 0x850 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM8DDAT GPWM8 Output Shift Amou8t Setti8g Register 0x81A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM8DHRDAT GPWM8 High Resolutio8 Output Shift Amou8t Setti8g Register 0x818 16 read-write n HRSTIMn Set high resolution output shift amount 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM8DTMCNT GPWM8 Dead Time Co8trol Register 0x820 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM8DTMSETA GPWM8 Dead Time Setti8g Register A 0x824 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM8DTMSETB GPWM8 Dead Time Setti8g Register B 0x826 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM8DUTYTRGA GPWM8 Duty Cut Factor Selectio8 Register A 0x848 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM8DUTYTRGB GPWM8 Duty Cut Factor Selectio8 Register B 0x84A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM8HRSET GPWM8 High Resolutio8 Cycle Setti8g Register 0x810 16 read-write n HRSETn Set high resolution cycle 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM8IRQCNT GPWM8 UDF/OVF I8terrupt Output Co8trol Register 0x830 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM8MD GPWM8 Mode Register 0x800 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM8OFF GPWM8 Pi8 Protectio8 Co8trol Register 0x838 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM8OFFIRQA GPWM8 Pi8 Protectio8 Factor Selectio8 Register A 0x83C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM8OFFIRQB GPWM8 Pi8 Protectio8 Factor Selectio8 Register B 0x83E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM8OUTMD GPWM8 Output Polarity Co8trol Register 0x804 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM8PERITRGA GPWM8 Period Cut Factor Selectio8 Register A 0x84C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM8PERITRGB GPWM8 Period Cut Factor Selectio8 Register B 0x84E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM8PULSECNT GPWM8 Pulse Co8trol Register 0x840 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM8PULSEST GPWM8 Pulse Co8trol Status Register 0x844 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM8SEL GPWM8 Output Co8trol Register 0x808 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM8SET GPWM8 Cycle Setti8g Register 0x812 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM8TCMP GPWM8 Phase Compariso8 Setti8g Register 0x816 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWM8TCMPHR GPWM8 High Resolutio8 Phase Compariso8 Setti8g Register 0x814 16 read-write n HRTCPn Set phase comparison high resolution 11 16 read-write __reserve0 0 is always read out. 0 11 read GPWM9ADBC GPWM9 Sy9chro9ous Bi9ary Cou9ter Read Register 0x92C 16 read-write n ADBCn Read the binary count for starting GPWMn synchronous A/D. 0 16 read GPWM9ADIRQCNT GPWM9 A/D Start I9terrupt Output Co9trol Register 0x934 16 read-write n ASTCNTn Number of times setting for GPWMn synchronous A/D start interrupt (Second time or later) 0 4 read-write ASTSCNTn Number of times setting for GPWMn synchronous A/D start interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read GPWM9ADST GPWM9 Sy9chro9ous Trigger Setti9g Register 0x928 16 read-write n PASTn Set the value of starting GPWMn synchronous A/D. 0 16 read-write GPWM9ADSTSEL GPWM9 Sy9chro9ous Trigger Polarity Selectio9 Register 0x92A 16 read-write n PASTDNn Set the timing of synchronous trigger generation. 1 2 read-write PASTUPn Set the timing of synchronous trigger generation. 0 1 read-write __reserve0 0 is always read out. 2 16 read GPWM9BC GPWM9BC Value Read Register 0x90C 16 read-write n BCn Read the binary counter value of GPWMn 0 16 read GPWM9BCSTR GPWM9BC Status Read Register 0x90E 16 read-write n STRn GPWMn binary counter's counting status read 0 1 read __reserve0 0 is always read out. 1 16 read GPWM9DBUPDATE GPWM9 Double Buffer Updati9g E9able Register 0x950 16 read-write n DUPn Double buffer updating enable 0 1 read-write __reserve0 0 is always read out. 1 16 read GPWM9DDAT GPWM9 Output Shift Amou9t Setti9g Register 0x91A 16 read-write n STIMn Set GPWMn output shift amount 0 16 read-write GPWM9DTMCNT GPWM9 Dead Time Co9trol Register 0x920 16 read-write n DTENn Dead time insertion 0 1 read-write NORMDn NGPWMn dead time insertion logic 2 3 read-write ORMDn GPWMn dead time insertion logic 1 2 read-write SLFCNTn Dead time width automatic control enable 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM9DTMSETA GPWM9 Dead Time Setti9g Register A 0x924 16 read-write n DTSTAn Set dead time for GPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM9DTMSETB GPWM9 Dead Time Setti9g Register B 0x926 16 read-write n DTSTBn Set dead time for NGPWMn. 0 10 read-write __reserve0 0 is always read out. 10 16 read GPWM9DUTYTRGA GPWM9 Duty Cut Factor Selectio9 Register A 0x948 16 read-write n IRQ00ENn Duty cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Duty cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Duty cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Duty cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Duty cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Duty cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Duty cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Duty cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Duty cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Duty cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Duty cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Duty cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Duty cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Duty cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Duty cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Duty cut start factor selection by External Interrupt 15 15 16 read-write GPWM9DUTYTRGB GPWM9 Duty Cut Factor Selectio9 Register B 0x94A 16 read-write n CMP00ENn Duty cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Duty cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Duty cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Duty cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Duty cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Duty cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Duty cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Duty cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Duty cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Duty cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM9IRQCNT GPWM9 UDF/OVF I9terrupt Output Co9trol Register 0x930 16 read-write n OVFCNTn Number of times setting for GPWMn overflow interrupt (Second time or later) 8 12 read-write OVFSCNTn Number of times setting for GPWMn overflow interrupt (First time) 12 16 read-write UDFCNTn Number of times setting for GPWMn underflow interrupt (Second time or later) 0 4 read-write UDFSCNTn Number of times setting for GPWMn underflow interrupt (First time) 4 8 read-write GPWM9MD GPWM9 Mode Register 0x900 16 read-write n CLKSELn Count clock selection 11 12 read-write DUPENn Double buffer updating enable register selection 5 6 read-write HRPRENn High resolution cycle function enable 3 4 read-write HRSELn High resolution output function enable 2 3 read-write PCRAENn Double buffer load timing enable (GPWMnBC underflow) 7 8 read-write PCRBENn Double buffer load timing enable (GPWMnBC overflow) 6 7 read-write SDIRn Shift direction control 14 15 read-write SDSELAn GPWMnOUTMD buffer mode 9 10 read-write SDSELBn GPWMnSEL buffer mode 8 9 read-write SFTENn PWM output shift function enable 13 14 read-write SYNCENn Synchronous start function (MFA) enable 4 5 read-write TCENn PWM Operation control 1 2 read-write WAVEMDn PWM waveform mode select 0 1 read-write __reserve0 0 is always read out. 10 11 read __reserve1 0 is always read out. 12 13 read __reserve2 0 is always read out. 15 16 read GPWM9OFF GPWM9 Pi9 Protectio9 Co9trol Register 0x938 16 read-write n OUTENn GPWMn pin output enable 0 1 read-write PRT GPWMOUTn output pin protection function 4 6 read-write PRTN NGPWMOUTn output pin protection function 6 8 read-write __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 8 16 read GPWM9OFFIRQA GPWM9 Pi9 Protectio9 Factor Selectio9 Register A 0x93C 16 read-write n AD0ERRAENn Protection factor control by A/D0 Conversion Error Detection 9 10 read-write AD0ERRBENn Protection factor control by A/D0 Conversion Error Detection B 10 11 read-write AD1ERRAENn Protection factor control by A/D1 Conversion Error Detection 11 12 read-write AD1ERRBENn Protection factor control by A/D1 Conversion Error Detection B 12 13 read-write AD2ERRAENn Protection factor control by A/D2 Conversion Error Detection 13 14 read-write AD2ERRBENn Protection factor control by A/D2 Conversion Error Detection B 14 15 read-write IRQ00ENn Protection factor control by External Interrupt 0 0 1 read-write IRQ01ENn Protection factor control by External Interrupt 1 1 2 read-write IRQ08ENn Protection factor control by External Interrupt 8 2 3 read-write IRQ09ENn Protection factor control by External Interrupt 9 3 4 read-write IRQ14ENn Protection factor control by External Interrupt 14 4 5 read-write IRQ15ENn Protection factor control by External Interrupt 15 5 6 read-write IRQ18ENn Protection factor control by External Interrupt 18 6 7 read-write IRQ19ENn Protection factor control by External Interrupt 19 7 8 read-write NMIENn Protection factor control by NMI 8 9 read-write __reserve0 0 is always read out. 15 16 read GPWM9OFFIRQB GPWM9 Pi9 Protectio9 Factor Selectio9 Register B 0x93E 16 read-write n CMP00ENn Protection factor control by Comparator 00 Detection 0 1 read-write CMP01ENn Protection factor control by Comparator 01 Detection 1 2 read-write CMP10ENn Protection factor control by Comparator 10 Detection 2 3 read-write CMP11ENn Protection factor control by Comparator 11 Detection 3 4 read-write CMP20ENn Protection factor control by Comparator 20 Detection 4 5 read-write CMP21ENn Protection factor control by Comparator 21 Detection 5 6 read-write CMP30ENn Protection factor control by Comparator 30 Detection 6 7 read-write CMP31ENn Protection factor control by Comparator 31 Detection 7 8 read-write CMP40ENn Protection factor control by Comparator 40 Detection 8 9 read-write CMP41ENn Protection factor control by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM9OUTMD GPWM9 Output Polarity Co9trol Register 0x904 16 read-write n PXDTn GPWMn output polarity 0 1 read-write PXDTNn NGPWMn output polarity 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM9PERITRGA GPWM9 Period Cut Factor Selectio9 Register A 0x94C 16 read-write n IRQ00ENn Period cut start factor selection by External Interrupt 0 0 1 read-write IRQ01ENn Period cut start factor selection by External Interrupt 1 1 2 read-write IRQ02ENn Period cut start factor selection by External Interrupt 2 2 3 read-write IRQ03ENn Period cut start factor selection by External Interrupt 3 3 4 read-write IRQ04ENn Period cut start factor selection by External Interrupt 4 4 5 read-write IRQ05ENn Period cut start factor selection by External Interrupt 5 5 6 read-write IRQ06ENn Period cut start factor selection by External Interrupt 6 6 7 read-write IRQ07ENn Period cut start factor selection by External Interrupt 7 7 8 read-write IRQ08ENn Period cut start factor selection by External Interrupt 8 8 9 read-write IRQ09ENn Period cut start factor selection by External Interrupt 9 9 10 read-write IRQ10ENn Period cut start factor selection by External Interrupt 10 10 11 read-write IRQ11ENn Period cut start factor selection by External Interrupt 11 11 12 read-write IRQ12ENn Period cut start factor selection by External Interrupt 12 12 13 read-write IRQ13ENn Period cut start factor selection by External Interrupt 13 13 14 read-write IRQ14ENn Period cut start factor selection by External Interrupt 14 14 15 read-write IRQ15ENn Period cut start factor selection by External Interrupt 15 15 16 read-write GPWM9PERITRGB GPWM9 Period Cut Factor Selectio9 Register B 0x94E 16 read-write n CMP00ENn Period cut start factor selection by Comparator 00 Detection 0 1 read-write CMP01ENn Period cut start factor selection by Comparator 01 Detection 1 2 read-write CMP10ENn Period cut start factor selection by Comparator 10 Detection 2 3 read-write CMP11ENn Period cut start factor selection by Comparator 11 Detection 3 4 read-write CMP20ENn Period cut start factor selection by Comparator 20 Detection 4 5 read-write CMP21ENn Period cut start factor selection by Comparator 21 Detection 5 6 read-write CMP30ENn Period cut start factor selection by Comparator 30 Detection 6 7 read-write CMP31ENn Period cut start factor selection by Comparator 31 Detection 7 8 read-write CMP40ENn Period cut start factor selection by Comparator 40 Detection 8 9 read-write CMP41ENn Period cut start factor selection by Comparator 41 Detection 9 10 read-write __reserve0 0 is always read out. 10 16 read GPWM9PULSECNT GPWM9 Pulse Co9trol Register 0x940 16 read-write n DTACTSELn Duty cut start factor polarity selection 1 2 read-write DTCTASELn GPWMn operation selection when the duty cut 2 4 read-write DTCTBSELn NGPWMn operation selection when the duty cut 4 6 read-write DTCTENn Duty Cut enable 0 1 read-write DTOVFRETn Control of the return of duty cut by the overflow 6 7 read-write DTUDFRETn Control of the return of duty cut by the underflow 7 8 read-write PRACTSELn Period cut start factor polarity selection 9 10 read-write PRCTENn Period Cut enable 8 9 read-write PRRETSELn Period cut operation selection 10 11 read-write __reserve0 0 is always read out. 11 16 read GPWM9PULSEST GPWM9 Pulse Co9trol Status Register 0x944 16 read-write n DTCTSTn Duty cut state 0 1 read-write PRCTSTn Period cut state 1 2 read-write __reserve0 0 is always read out. 2 16 read GPWM9SEL GPWM9 Output Co9trol Register 0x908 16 read-write n OTLVn GPWMn High/Low-level output 0 1 read-write OTLVNn NGPWMn High/Low-level output 1 2 read-write PSELn GPWMn output sources 2 3 read-write PSELNn NGPWMn output sources 3 4 read-write __reserve0 0 is always read out. 4 16 read GPWM9SET GPWM9 Cycle Setti9g Register 0x912 16 read-write n SETn Set the cycle to the GPWMn 16-bit counter. 0 16 read-write GPWM9TCMP GPWM9 Phase Compariso9 Setti9g Register 0x916 16 read-write n TCPn Set the timing to change output of GPWMn. 0 16 read-write GPWMC_DBUPALL GPWM Double Buffer Collective Updating Enable Register 0xF00 16 read-write n DUP0 GPWM0 double buffer updating enable 0 1 read-write DUP1 GPWM1 double buffer updating enable 1 2 read-write DUP2 GPWM2 double buffer updating enable 2 3 read-write DUP3 GPWM3 double buffer updating enable 3 4 read-write DUP4 GPWM4 double buffer updating enable 4 5 read-write DUP5 GPWM5 double buffer updating enable 5 6 read-write DUP6 GPWM6 double buffer updating enable 6 7 read-write DUP7 GPWM7 double buffer updating enable 7 8 read-write DUP8 GPWM8 double buffer updating enable 8 9 read-write DUP9 GPWM9 double buffer updating enable 9 10 read-write __reserve0 0 is always read out. 12 16 read GPWMC_PINSEL 3-Phase Output Pin Output Order Register 0xF04 16 read-write n TPWMPINSELA Pin output order change 0 1 read-write TPWMPINSELB Pin output order change 1 2 read-write TPWMPINSELC Pin output order change 2 3 read-write __reserve0 0 is always read out. 4 16 read PWRDET Power Supply Voltage Detection PWRDET 0x0 0x0 0x4 registers n G30 30 LVDMD Power Supply Voltage Detection Control Register 0x0 32 read-write n KEY_CODE Register Key 16 32 write MON Power supply voltage monitor bit 1 2 read NF Selection of power supply voltage detection signal noise filter 4 8 read-write ON Power supply voltage detection function control 0 1 read-write __reserve0 0 is always read out. 2 4 read __reserve1 0 is always read out. 8 16 read SIF_0__6 Serial Interface 0-6 SIF_0__6 0x0 0x0 0xF1C registers n G111 111 G112 112 G113 113 G115 115 G116 116 G117 117 G118 118 G119 119 G120 120 G121 121 G122 122 G123 123 G124 124 BRTM_S01_CK Baud Rate Timer 01 Count Clock Selection Register 0xF04 8 read-write n S0_CK Baud rate timer 0 count clock selection. 0 4 read-write S1_CK Baud rate timer 1 count clock selection. 4 8 read-write BRTM_S0_OC Baud Rate Timer 0 Compare Register 0xF0C 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S1_OC Baud Rate Timer 1 Compare Register 0xF0D 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S23_CK Baud Rate Timer 23 Count Clock Selection Register 0xF05 8 read-write n S3_CK Selection of count clock in baud rate timer 3 4 8 read-write BRTM_S3_OC Baud Rate Timer 3 Compare Register 0xF11 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S45_CK Baud Rate Timer 45 Count Clock Selection Register 0xF08 8 read-write n S4_CK Selection of count clock in baud rate timer 4 0 4 read-write S5_CK Selection of count clock in baud rate timer 5 4 8 read-write BRTM_S4_OC Baud Rate Timer 4 Compare Register 0xF14 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S5_OC Baud Rate Timer 5 Compare Register 0xF15 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S6_CK Baud Rate Timer 6 Count Clock Selection Register 0xF09 8 read-write n S6_CK Selection of count clock in baud rate timer 6 0 4 read-write __reserve0 0 is always read out. 4 8 read-write BRTM_S6_OC Baud Rate Timer 6 Compare Register 0xF18 8 read-write n Sn_OC Set the value to be compared with the counter of baud rate timer n. 0 8 read-write BRTM_S_EN Baud Rate Timer Operation Enable Register 0xF01 8 read-write n S0_EN Baud rate timer 0 operation enable. 0 1 read-write S1_EN Baud rate timer 1 operation enable. 1 2 read-write S3_EN Baud rate timer 3 operation enable. 3 4 read-write S4_EN Baud rate timer 4 operation enable. 4 5 read-write S5_EN Baud rate timer 5 operation enable. 5 6 read-write S6_EN Baud rate timer 6 operation enable. 6 7 read-write __reserve0 0 is always read out. 7 8 read BRTM_S_MODE Baud Rate Timer Operation Mode Setting Register 0xF00 8 read-write n S0_MODE Baud rate timer 0 output clock duty setting (High-level : Low-level) 0 1 read-write S1_MODE Baud rate timer 1 output clock duty setting (High-level : Low-level) 1 2 read-write S3_MODE Baud rate timer 3 output clock duty setting (High-level : Low-level) 3 4 read-write S4_MODE Baud rate timer 4 output clock duty setting (High-level : Low-level) 4 5 read-write S5_MODE Baud rate timer 5 output clock duty setting (High-level : Low-level) 5 6 read-write S6_MODE Baud rate timer 6 output clock duty setting (High-level : Low-level) 6 7 read-write __reserve0 0 is always read out. 7 8 read SC0AD0 Serial 0 Address Setting Register 0 0x8 8 read-write n AD0 Set the slave address. 0 8 read-write SC0MD0 Serial 0 Mode Register 0 0x0 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write DEM Operation after communication error detection selection [IIC Slave communication] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count settings (*2) 0 3 read-write SSC Clock source selection of internal circuit operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous/IIC Master communication](*1) 3 4 read-write SC0MD1 Serial 0 Mode Register 1 0x1 8 read-write n CTM Continuous communication mode selection [Clock-Synchronous] 0 1 read-write IOM Data input pin selection 7 8 read-write MST [Clock-Synchronous] 2 3 read-write SBIS SBIn/SBOn(SDAn) pin input control 5 6 read-write SBOS SBOn(SDAn) pin output control 4 5 read-write SBTS SBTn(SCLn) pin control 6 7 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 3 4 read SC0MD2 Serial 0 Mode Register 2 0x4 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write __reserve0 This bit must be set to 0 . 0 4 read-write __reserve1 0 is always read out. 4 6 read SC0MD3 Serial 0 Mode Register 3 0x5 8 read-write n ACKO [Data transmission in IIC] 0 1 read-write ACKS This bit must be set to 1 . [IIC] 1 2 read-write CMD Communication mode selection 2 3 read-write REX Transmission/Reception mode selection [IIC Master communication] 3 4 read-write STPC Stop condition generation selection [IIC Master communication] 5 6 read-write TMD Communication speed selection [IIC] 4 5 read-write __reserve0 This bit must be set to 0 . 6 7 read-write __reserve1 This bit must be set to 0 . 7 8 read-write SC0RB Serial 0 Reception Data Buffer Register 0x10 8 read-write n RB Reception data is read out. 0 8 read SC0STR0 Serial 0 Status Register 0 0xC 8 read-write n BSY Bus busy detection [Clock-Synchronous] 7 8 read ORE Overrun error detection 0 1 read-write REMP Reception buffer empty 4 5 read TEMP Transmission buffer empty 5 6 read __reserve0 0 is always read out. 1 4 read __reserve1 0 is always read out. 6 7 read SC0STR1 Serial 0 Status Register 1 0xD 8 read-write n ABT_LST Arbitration lost detection [IIC][Master] 6 7 read-write ADD_ACC Slave address match detection [IIC][Slave] 5 6 read BUSBSY Bus busy detection [IIC] 3 4 read DATA_ERR Communication error detection [IIC] 0 1 read-write GCALL General call detection [IIC] 1 2 read IICBSY IIC communication busy detection [IIC] 2 3 read STRT Start condition detection [IIC][Slave] 4 5 read WRS Transmission/reception mode [IIC][Slave] 7 8 read SC0TB Serial 0 Transmission Data Buffer Register 0x11 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC1MD0 Serial 1 Mode Register 0 0x20 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write CTM Continuous communication mode selection [Clock-Synchronous] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count [Clock-Synchronous] (*2) 0 3 read-write SSC Clock source selection as operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous] (*1) 3 4 read-write SC1MD1 Serial 1 Mode Register 1 0x21 8 read-write n CKM Division selection of transfer clock [Clock-Synchronous] 3 4 read-write CMD Communication mode selection 0 1 read-write DIV Division value selection of transfer clock 1 2 read-write IOM Data input pin selection 7 8 read-write MST Master/salve communication selection [Clock-Synchronous] 2 3 read-write SBIS SBIn(RXDn)/SBOn(TXDn) pin input control 5 6 read-write SBOS SBOn(TXDn) pin output control 4 5 read-write SBTS SBTn pin control 6 7 read-write SC1MD2 Serial 1 Mode Register 2 0x24 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 8 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read SC1MD3 Serial 1 Mode Register 3 0x25 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write RSRN [Clock-Synchronous] 4 5 read-write RSTN [Clock-Synchronous] 5 6 read-write __reserve0 0 is always read out. 0 4 read SC1RB Serial 1 Receptio1 Data Buffer Register 0x2C 8 read-write n RB Reception data is read out. 0 8 read SC1STR Serial 1 Status Register 0x28 8 read-write n ERE Reception error detection 0 1 read FEF Framing error detection [UART] 3 4 read ORE Overrun error detection 1 2 read PEK Parity error detection [UART] 2 3 read RBSY Reception busy detection 6 7 read REMP Reception buffer empty 4 5 read TBSY Transmission busy detection 7 8 read TEMP Transmission buffer empty 5 6 read SC1TB Serial 1 Tra1smissio1 Data Buffer Register 0x30 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC3MD0 Serial 3 Mode Register 0 0x60 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write CTM Continuous communication mode selection [Clock-Synchronous] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count [Clock-Synchronous] (*2) 0 3 read-write SSC Clock source selection as operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous] (*1) 3 4 read-write SC3MD1 Serial 3 Mode Register 1 0x61 8 read-write n CKM Division selection of transfer clock [Clock-Synchronous] 3 4 read-write CMD Communication mode selection 0 1 read-write DIV Division value selection of transfer clock 1 2 read-write IOM Data input pin selection 7 8 read-write MST Master/salve communication selection [Clock-Synchronous] 2 3 read-write SBIS SBIn(RXDn)/SBOn(TXDn) pin input control 5 6 read-write SBOS SBOn(TXDn) pin output control 4 5 read-write SBTS SBTn pin control 6 7 read-write SC3MD2 Serial 3 Mode Register 2 0x64 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 8 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read SC3MD3 Serial 3 Mode Register 3 0x65 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write RSRN [Clock-Synchronous] 4 5 read-write RSTN [Clock-Synchronous] 5 6 read-write __reserve0 0 is always read out. 0 4 read SC3MD4 Serial 3 Mode Register 4 0x68 8 read-write n CSLV SBCS3 polarity selection 7 8 read-write SMD Clock-synchronous communication type selection 6 7 read-write __reserve0 0 is always read out. 0 6 read SC3RB Serial 3 Receptio3 Data Buffer Register 0x6C 8 read-write n RB Reception data is read out. 0 8 read SC3STR Serial 3 Status Register 0x69 8 read-write n ERE Reception error detection 0 1 read FEF Framing error detection [UART] 3 4 read ORE Overrun error detection 1 2 read PEK Parity error detection [UART] 2 3 read RBSY Reception busy detection 6 7 read REMP Reception buffer empty 4 5 read TBSY Transmission busy detection 7 8 read TEMP Transmission buffer empty 5 6 read SC3TB Serial 3 Tra3smissio3 Data Buffer Register 0x70 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC4MD0 Serial 4 Mode Register 0 0x80 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write CTM Continuous communication mode selection [Clock-Synchronous] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count [Clock-Synchronous] (*2) 0 3 read-write SSC Clock source selection as operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous] (*1) 3 4 read-write SC4MD1 Serial 4 Mode Register 1 0x81 8 read-write n CKM Division selection of transfer clock [Clock-Synchronous] 3 4 read-write CMD Communication mode selection 0 1 read-write DIV Division value selection of transfer clock 1 2 read-write IOM Data input pin selection 7 8 read-write MST Master/salve communication selection [Clock-Synchronous] 2 3 read-write SBIS SBIn(RXDn)/SBOn(TXDn) pin input control 5 6 read-write SBOS SBOn(TXDn) pin output control 4 5 read-write SBTS SBTn pin control 6 7 read-write SC4MD2 Serial 4 Mode Register 2 0x84 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 8 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read SC4MD3 Serial 4 Mode Register 3 0x85 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write RSRN [Clock-Synchronous] 4 5 read-write RSTN [Clock-Synchronous] 5 6 read-write __reserve0 0 is always read out. 0 4 read SC4MD4 Serial 4 Mode Register 4 0x88 8 read-write n CSLV SBCS3 polarity selection 7 8 read-write SMD Clock-synchronous communication type selection 6 7 read-write __reserve0 0 is always read out. 0 6 read SC4RB Serial 4 Receptio4 Data Buffer Register 0x8C 8 read-write n RB Reception data is read out. 0 8 read SC4STR Serial 4 Status Register 0x89 8 read-write n ERE Reception error detection 0 1 read FEF Framing error detection [UART] 3 4 read ORE Overrun error detection 1 2 read PEK Parity error detection [UART] 2 3 read RBSY Reception busy detection 6 7 read REMP Reception buffer empty 4 5 read TBSY Transmission busy detection 7 8 read TEMP Transmission buffer empty 5 6 read SC4TB Serial 4 Tra4smissio4 Data Buffer Register 0x90 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC5MD0 Serial 5 Mode Register 0 0xA0 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write CTM Continuous communication mode selection [Clock-Synchronous] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count [Clock-Synchronous] (*2) 0 3 read-write SSC Clock source selection as operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous] (*1) 3 4 read-write SC5MD1 Serial 5 Mode Register 1 0xA1 8 read-write n CKM Division selection of transfer clock [Clock-Synchronous] 3 4 read-write CMD Communication mode selection 0 1 read-write DIV Division value selection of transfer clock 1 2 read-write IOM Data input pin selection 7 8 read-write MST Master/salve communication selection [Clock-Synchronous] 2 3 read-write SBIS SBIn(RXDn)/SBOn(TXDn) pin input control 5 6 read-write SBOS SBOn(TXDn) pin output control 4 5 read-write SBTS SBTn pin control 6 7 read-write SC5MD2 Serial 5 Mode Register 2 0xA4 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 8 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read SC5MD3 Serial 5 Mode Register 3 0xA5 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write RSRN [Clock-Synchronous] 4 5 read-write RSTN [Clock-Synchronous] 5 6 read-write __reserve0 0 is always read out. 0 4 read SC5MD4 Serial 5 Mode Register 4 0xA8 8 read-write n UARTMOD [Clock-Synchronous] 0 2 read-write __reserve0 This bit must be set to 0 . 2 3 read-write __reserve1 0 is always read out. 3 8 read SC5RB Serial 5 Receptio5 Data Buffer Register 0xAC 8 read-write n RB Reception data is read out. 0 8 read SC5STR Serial 5 Status Register 0xA9 8 read-write n ERE Reception error detection 0 1 read FEF Framing error detection [UART] 3 4 read ORE Overrun error detection 1 2 read PEK Parity error detection [UART] 2 3 read RBSY Reception busy detection 6 7 read REMP Reception buffer empty 4 5 read TBSY Transmission busy detection 7 8 read TEMP Transmission buffer empty 5 6 read SC5TB Serial 5 Tra5smissio5 Data Buffer Register 0xB0 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC6MD0 Serial 6 Mode Register 0 0x100 8 read-write n CE1 Clock polarity selection [Clock-Synchronous] 7 8 read-write CTM Continuous communication mode selection [Clock-Synchronous] 5 6 read-write DIR Transfer first bit selection 4 5 read-write LNG Transfer bit count [Clock-Synchronous] (*2) 0 3 read-write SSC Clock source selection as operation clock [Clock-Synchronous] 6 7 read-write STE Start condition selection [Clock-Synchronous] (*1) 3 4 read-write SC6MD1 Serial 6 Mode Register 1 0x101 8 read-write n CKM Division selection of transfer clock [Clock-Synchronous] 3 4 read-write CMD Communication mode selection 0 1 read-write DIV Division value selection of transfer clock 1 2 read-write IOM Data input pin selection 7 8 read-write MST Master/salve communication selection [Clock-Synchronous] 2 3 read-write SBIS SBIn(RXDn)/SBOn(TXDn) pin input control 5 6 read-write SBOS SBOn(TXDn) pin output control 4 5 read-write SBTS SBTn pin control 6 7 read-write SC6MD2 Serial 6 Mode Register 2 0x104 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 8 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read SC6MD3 Serial 6 Mode Register 3 0x105 8 read-write n FDC Output level selection after the final bit transmit (SBOn pin) [Clock-Synchronous] 6 8 read-write RSRN [Clock-Synchronous] 4 5 read-write RSTN [Clock-Synchronous] 5 6 read-write __reserve0 0 is always read out. 0 4 read SC6RB Serial 6 Receptio6 Data Buffer Register 0x10C 8 read-write n RB Reception data is read out. 0 8 read SC6STR Serial 6 Status Register 0x108 8 read-write n ERE Reception error detection 0 1 read FEF Framing error detection [UART] 3 4 read ORE Overrun error detection 1 2 read PEK Parity error detection [UART] 2 3 read RBSY Reception busy detection 6 7 read REMP Reception buffer empty 4 5 read TBSY Transmission busy detection 7 8 read TEMP Transmission buffer empty 5 6 read SC6TB Serial 6 Tra6smissio6 Data Buffer Register 0x110 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SCINTSEL Clock Edge Interrupt Setting Register 0xC0 8 read-write n SC0IGC Control of SBT1 falling edge interrupt 0 1 read-write SC2IGC Control of SBT3 falling edge interrupt 2 3 read-write SC3IGC Control of SBT4 falling edge interrupt 3 4 read-write SC4IGC Control of SBT5 falling edge interrupt 4 5 read-write __reserve0 0 is always read out. 5 8 read SIF_7 Serial Interface 7 SIF_7 0x0 0x0 0x510 registers n G125 125 G126 126 BRTM_S7_CK Baud Rate Timer 7 Count Clock Selection Register 0x504 8 read-write n S7_CK Clock selection of baud rate timer 0 0 4 read-write __reserve0 0 is always read out. 4 8 read BRTM_S7_EN Baud Rate Timer 7 Operation Enable Register 0x501 8 read-write n S7_EN Baud rate timer operation enable. 0 1 read-write __reserve0 0 is always read out. 1 8 read BRTM_S7_MODE Baud Rate Timer 7 Operation Mode Setting Register 0x500 8 read-write n S7_MODE Baud rate timer output clock duty setting (High-level : Low-level) 0 1 read-write __reserve0 0 is always read out. 1 8 read BRTM_S7_OC Baud Rate Timer 7 Compare Register 0x50C 8 read-write n S7_OC Set the value to be compared with the counter of baud rate timer. 0 8 read-write SC7CI2C_CTR0 IIC Control Clear Register 0 0x60 8 read-write n ADREXC_SEL Clear SC7I2C_CTR0.ADREXC_SEL bit to 0 5 6 write ADRNG_SEL Clear SC7I2C_CTR0.ADRNG_SEL bit to 0 6 7 write ADROK_SEL Clear SC7I2C_CTR0.ADROK_SEL bit to 0 7 8 write SCL_FIXL Clear SC7I2C_CTR0.SCL_FIXL bit to 0 1 2 write SDA_FIXL Clear SC7I2C_CTR0.SDA_FIXL bit to 0 0 1 write __reserve0 This bit must be set to 0 . 2 3 write __reserve1 This bit must be set to 0 . 3 4 write __reserve2 This bit must be set to 0 . 4 5 write SC7CI2C_CTR1 IIC Control Clear Register 1 0x61 8 read-write n LPW_LMTSEL Clear SC7I2C_CTR1.LPW_LMTSEL bit to 0 . 5 6 write LPW_ON Clear SC7I2C_CTR1.LPW_ONL bit to 0 6 7 write SCLH_ON Clear SC7I2C_CTR1.SCLH_ON bit to 0 . 4 5 write SCLH_SEL Clear SC7I2C_CTR1.SCLH_SEL bit to 0 . 2 4 write TEXT_ON Clear SC7I2C_CTR1.TEXT_ON bit to 0 . 0 1 write TOUT_ON Clear SC7I2C_CTR1.TOUT_ON bit to 0 . 1 2 write __reserve0 This bit must be set to 0 . 7 8 write SC7CI2C_CTR2 IIC Control Clear Register 2 0x62 8 read-write n ACK_SET Set SC7I2C_CTR2.ACK_SETL bit to 0 . 3 4 write RWS_MST Set SC7I2C_CTR2.RWS_MSTL bit to 0 . 4 5 write START_EN Set SC7I2C_CTR2.START_ENL bit to 0 . 6 7 write STOP_EN Set SC7I2C_CTR2.STOP_ENL bit to 0 . 5 6 write TRANS_END Set SC7I2C_CTR2.TRANS_ENDL bit to 0 . 2 3 write __reserve0 This bit must be set to 0 . 0 1 write __reserve1 This bit must be set to 0 . 1 2 write __reserve2 This bit must be set to 0 . 7 8 write SC7CI2C_IRQCTR IIC Interrupt Control Clear Register 0x63 8 read-write n ACKDONE_IE Clear SC7I2C_IRQCTR.ACKDONE_IE bit to 0 . 0 1 write ADRNG_IE Clear SC7I2C_IRQCTR.ADRNG_IE bit to 0 . 4 5 write BYTEDONE_IE Clear SC7I2C_IRQCTR.BYTEDONE_IE bit to 0 . 1 2 write START_IE Clear SC7I2C_IRQCTR.START_IE bit to 0 . 3 4 write STOP_IE Clear SC7I2C_IRQCTR.STOP_IE bit to 0 . 2 3 write TOUT_IE Clear SC7I2C_IRQCTR.TOUT_IE bit to 0 . 5 6 write WKUP_IE Clear SC7I2C_IRQCTR.WKUP_IE bit to 0 . 6 7 write WKUP_SEL Clear SC7I2C_IRQCTR.WKUP_SEL bit to 0 . 7 8 write SC7CSYNC_CTR0 Clock-Synchronous Control Clear Register 0x68 8 read-write n CE1 Clear SC7SYNC_CTR0.CE1 bit to 0 . 3 4 write CKPH Clear SC7SYNC_CTR0.CKPH bit to 0 . 2 3 write FDC This bit must be set to 00 . 4 6 write SBCSEN Clear SC7SYNC_CTR0.SBCSEN bit to 0 . 1 2 write SBCSLV Clear SC7SYNC_CTR0.SBCSLV bit to 0 . 0 1 write __reserve0 This bit must be set to 00 . 6 8 write SC7CUART_CTR UART Control Clear Register 0x6A 8 read-write n BRKE Clear SC7UART_CTR.BRKE bit to 0 0 1 write BRKF This bit must be set to 0 . 1 2 write FM Clear SC7UART_CTR.FM bit to 0 6 7 write NPE Clear SC7UART_CTR.NPE bit to 0 3 4 write PM Clear SC7UART_CTR.PM bit to 0 4 6 write __reserve0 This bit must be set to 0 . 2 3 write __reserve1 This bit must be set to 0 . 7 8 write SC7C_CTR0 Serial 7 Control Clear Register 0 0x6C 8 read-write n CKM Clear SC7_CTR0.CKM bit to 0 . 3 4 write CMD This bit must be set to 00 . 4 6 write DIR Clear SC7_CTR0.DIR bit to 0 . 6 7 write IOM Clear SC7_CTR0.IOM bit to 0 . 2 3 write MST Clear SC7_CTR0.MST bit to 0 . 7 8 write SBIS Clear SC7_CTR0.SBIS bit to 0 . 1 2 write SBOS Clear SC7_CTR0.SBOS bit to 0 . 0 1 write SC7C_CTR1 Serial 7 Control Clear Register 1 0x6D 8 read-write n DIV Clear SC7_CTR1.DIV bit to 0 . 3 4 write LNG This bit must be set to 000 . 4 7 write STREQ This bit must be set to 0 . 0 1 write TRGSEL This bit must be set to 00 . 1 3 write __reserve0 This bit must be set to 0 . 7 8 write SC7C_RST Serial 7 Reset Clear Register 0x6E 8 read-write n RSRN Clear SC7_RST.RSRN bit to 0 1 2 write RSTN Clear SC7_RST.RSTN bit to 0 0 1 write __reserve0 This bit must be set to 0 . 2 8 write SC7I2C_1STADR IIC Slave Address Setting Register 0x6 8 read-write n SLV_ADR Set the slave address. [IIC] (*1)(*2) 1 8 read-write __reserve0 0 is always read out. 0 1 read SC7I2C_CLKH IIC Clock High Level Frequency Setting Register 0x4 8 read-write n SCL_SETH High level period of transfer clock at master communication [IIC] (*1)(*2)(*3) 0 7 read-write __reserve0 0 is always read out. 7 8 read SC7I2C_CLKL IIC Clock Low Level Frequency Setting Register 0x5 8 read-write n SCL_SETL Low level period of transfer clock at master communication [IIC] (*1)(*2)(*3) 0 7 read-write __reserve0 0 is always read out. 7 8 read SC7I2C_CTR0 IIC Control Register 0 0x0 8 read-write n ADREXC_SEL Extension code matching operation select [IIC] (*1)(*2)(*3) 5 6 read-write ADRNG_SEL Slave address receive mode selection [IIC] (*1)(*3) 6 7 read-write ADROK_SEL Slave address receive mode selection [IIC] (*1)(*3) 7 8 read-write SCL_FIXL SCL port LOW level output [IIC] (*3) 1 2 read-write SDA_FIXL SDAport LOW level output [IIC] (*3) 0 1 read-write __reserve0 0 is always read out. 2 3 read __reserve1 This bit must be set to 0 . 3 4 read-write __reserve2 0 is always read out. 4 5 read SC7I2C_CTR1 IIC Control Register 1 0x1 8 read-write n LPW_LMTSEL Bus stop detection period [IIC] (*1) 5 6 read-write LPW_ON Bus stop detection enable [IIC] (*1) 6 7 read-write SCLH_ON Clock High-level period (THIGH) detection enable [IIC] (*1) 4 5 read-write SCLH_SEL Clock High-level period detection time [IIC] (*1) 2 4 read-write TEXT_ON TLOW:MEXT / TLOW:SEXT detection enable [IIC] (*1) 0 1 read-write TOUT_ON Clock Low-level period (TTIMEOUT) detection enable [IIC] (*1) 1 2 read-write __reserve0 0 is always read out. 7 8 read SC7I2C_CTR2 IIC Control Register 2 0x2 8 read-write n ACK_SET Transmission ACK bit selection [IIC] (*4) 3 4 read-write RWS_MST Read/Write mode selection at Master [IIC] (*3)(*4) 4 5 read-write START_EN Start condition generation selection [IIC] (*1)(*4) 6 7 read-write STOP_EN Stop condition generation selection [IIC Master communication] (*2)(*4) 5 6 read-write TRANS_END Communication end setting (*4) 2 3 read-write __reserve0 0 is always read out. 0 1 read __reserve1 0 is always read out. 1 2 read __reserve2 0 is always read out. 7 8 read SC7I2C_IRQCTR IIC Interrupt Control Register 0x3 8 read-write n ACKDONE_IE Enable ACK communication completion interrupt factor [IIC] (*4)(*5) 0 1 read-write ADRNG_IE Enable Slave address mismatch interrupt factor [IIC] (*5) 4 5 read-write BYTEDONE_IE Enable Byte data communication completion interrupt factor [IIC] (*2)(*3)(*5) 1 2 read-write START_IE Enable Start condition detection interrupt factor [IIC] (*5) 3 4 read-write STOP_IE Enable Stop condition interrupt factor [IIC] (*5) 2 3 read-write TOUT_IE Enable Time-out interrupt factor [IIC] (*5) 5 6 read-write WKUP_IE Enable CPU WAKEUP interrupt factor [IIC] (*1)(*5) 6 7 read-write WKUP_SEL Interrupt source selection for exiting CPU standby mode [IIC] (*5) 7 8 read-write SC7I2C_IRQSTS IIC Inteput Status Register 0x16 8 read-write n ACKDONE ACK communication completion detection (*1) [IIC] (*1)(*2) 0 1 read-write ADRNG Slave address mismatch detection [IIC] (*1)(*2) 4 5 read-write BYTEDONE Byte data communication completion detection [IIC] (*1)(*2) 1 2 read-write START Start condition detection [IIC] (*1)(*2)(*3) 3 4 read-write STOP Stop condition detection [IIC] (*1)(*2) 2 3 read-write TOUT Time-out detection [IIC] (*2) 5 7 read WKUP IIC standby status exit detection [IIC] (*1)(*2) 7 8 read-write SC7I2C_STS0 IIC Status Register 0 0x14 8 read-write n ABT_LST Arbitration lost detection [IIC] (*1) 5 6 read-write ADREXC Extension code receive detection [IIC] 6 7 read ADROK Slave address matching detection [IIC] 1 2 read BUSERR Bus error detection [IIC] (*1)(*5) 7 8 read-write BUS_BUSY Bus busy state detection [IIC] (*2) 4 5 read NACK NACK detection [IIC] 2 3 read RWS_SLV Read/ Write mode determination at Master/Slave communication [IIC] (*4) 0 1 read TRANS_BUSY Communication busy state detection [IIC] (*3) 3 4 read SC7I2C_STS1 IIC Status Register 1 0x15 8 read-write n LPW Bus stop detection [IIC] 0 1 read WKUPIE_DET CPU WAKEUP interrupt status [IIC] 2 3 read WKUPIE_JUG WKUP interrupt judgement [IIC] 1 2 read __reserve0 0 is always read out. 3 8 read SC7I2C_TCLKOC IIC Timeout Clock Compare Register 0x7 8 read-write n TCLKOC Time-out clock source division counter compare setting [IIC] (*1)(*2) 0 7 read-write __reserve0 0 is always read out. 7 8 read SC7RB Serial 7 Reception Data Buffer Register 0x10 8 read-write n RB Reception data is read out. 0 8 read SC7SI2C_CTR0 IIC Control Set Register 0 0x30 8 read-write n ADREXC_SEL Set SC7I2C_CTR0.ADREXC_SEL bit to 1 5 6 write ADRNG_SEL Set SC7I2C_CTR0.ADRNG_SEL bit to 1 6 7 write ADROK_SEL Set SC7I2C_CTR0.ADROK_SEL bit to 1 7 8 write SCL_FIXL Set SC7I2C_CTR0.SCL_FIXL bit to 1 1 2 write SDA_FIXL Set SC7I2C_CTR0.SDA_FIXL bit to 1 0 1 write __reserve0 This bit must be set to 0 . 2 3 write __reserve1 This bit must be set to 0 . 3 4 write __reserve2 This bit must be set to 0 . 4 5 write SC7SI2C_CTR1 IIC Control Set Register 1 0x31 8 read-write n LPW_LMTSEL Set SC7I2C_CTR1.LPW_LMTSEL bit to 1 5 6 write LPW_ON Set SC7I2C_CTR1.LPW_ONL bit to 1 6 7 write SCLH_ON Set SC7I2C_CTR1.SCLH_ON bit to 1 4 5 write SCLH_SEL Set SC7I2C_CTR1.SCLH_SEL bit to 1 2 4 write TEXT_ON Set SC7I2C_CTR1.TEXT_ON bit to 1 0 1 write TOUT_ON Set SC7I2C_CTR1.TOUT_ON bit to 1 1 2 write __reserve0 This bit must be set to 0 . 7 8 write SC7SI2C_CTR2 IIC Control Set Register 2 0x32 8 read-write n ACK_SET Set SC7I2C_CTR2.ACK_SETL bit to 1 . 3 4 write RWS_MST Set SC7I2C_CTR2.RWS_MSTL bit to 1 . 4 5 write START_EN Set SC7I2C_CTR2.START_ENL bit to 1 . 6 7 write STOP_EN Set SC7I2C_CTR2.STOP_ENL bit to 1 . 5 6 write TRANS_END Set SC7I2C_CTR2.TRANS_ENDL bit to 1 . 2 3 write __reserve0 This bit must be set to 0 . 0 1 write __reserve1 This bit must be set to 0 . 1 2 write __reserve2 This bit must be set to 0 . 7 8 write SC7SI2C_IRQCTR IIC Interrupt Control Set Register 0x33 8 read-write n ACKDONE_IE Set SC7I2C_IRQCTR.ACKDONE_IE bit to 1 . 0 1 write ADRNG_IE Set SC7I2C_IRQCTR.ADRNG_IE bit to 1 . 4 5 write BYTEDONE_IE Set SC7I2C_IRQCTR.BYTEDONE_IE bit to 1 . 1 2 write START_IE Set SC7I2C_IRQCTR.START_IE bit to 1 . 3 4 write STOP_IE Set SC7I2C_IRQCTR.STOP_IE bit to 1 . 2 3 write TOUT_IE Set SC7I2C_IRQCTR.TOUT_IE bit to 1 . 5 6 write WKUP_IE Set SC7I2C_IRQCTR.WKUP_IE bit to 1 . 6 7 write WKUP_SEL Set SC7I2C_IRQCTR.WKUP_SEL bit to 1 . 7 8 write SC7SI2C_IRQSTS IIC Inteput Clear Status Register 0x46 8 read-write n ACKDONE Clear SC7I2C_IRQSTS.ACKDONE bit to 0 . 0 1 write ADRNG Clear SC7I2C_IRQSTS.ADRNG bit to 0 . 4 5 write BYTEDONE Clear SC7I2C_IRQSTS.BYREDONE bit to 0 . 1 2 write START Clear C7I2C_IRQSTS.START bit to 0 . 3 4 write STOP Clear SC7I2C_IRQSTS.STOP bit to 0 . 2 3 write TOUT This bit must be set to 00 . 5 7 write WKUP Clear SC7I2C_IRQSTS.WKUP bit to 0 . 7 8 write SC7SI2C_STS0 IIC Status Set Register 0 0x44 8 read-write n ABT_LST Clear SC7I2C_STS0.ABT_LST bit to 0 . 5 6 write ADREXC This bit must be set to 0 . 6 7 write ADROK This bit must be set to 0 . 1 2 write BUSERR Clear SC7I2C_STS0.BUSERR bit to 0 . 7 8 write BUS_BUSY This bit must be set to 0 . 4 5 write NACK This bit must be set to 0 . 2 3 write RWS_SLV This bit must be set to 0 . 0 1 write TRANS_BUSY This bit must be set to 0 . 3 4 write SC7SSTR Clock-Synchronous/UART Status Set Register 0x47 8 read-write n ERE This bit must be set to 0 . 0 1 write FEF Clear SC7STR.FEF bit to 0 . 3 4 write ORE Clear SC7STR.ORE bit to 0 . 1 2 write PEK Clear SC7STR.PEK bit to 0 . 2 3 write RBSY This bit must be set to 0 . 6 7 write REMP This bit must be set to 0 . 4 5 write TBSY This bit must be set to 0 . 7 8 write TEMP This bit must be set to 0 . 5 6 write SC7SSYNC_CTR0 Clock-Synchronous Control Set Register 0x38 8 read-write n CE1 Set SC7SYNC_CTR0.CE1 bit to 1 . 3 4 write CKPH Set SC7SYNC_CTR0.CKPH bit to 1 . 2 3 write FDC This bit must be set to 00 . 4 6 write SBCSEN Set SC7SYNC_CTR0.SBCSEN bit to 1 . 1 2 write SBCSLV Set SC7SYNC_CTR0.SBCSLV bit to 1 . 0 1 write __reserve0 This bit must be set to 0 . 6 8 write SC7STR Clock-Synchronous/UART Status Register 0x17 8 read-write n ERE Reception error detection [Clock-Synchronous/UART] 0 1 read FEF Framing error detection [UART](*1) 3 4 read-write ORE Overrun error detection [Clock-Synchronous/UART](*1) 1 2 read-write PEK Parity error detection [UART](*1) 2 3 read-write RBSY Reception busy detection [Clock-Synchronous/UART] 6 7 read REMP Reception buffer empty [Clock-Synchronous/UART] 4 5 read TBSY Transmission busy detection [Clock-Synchronous/UART] 7 8 read TEMP Transmission buffer empty [Clock-Synchronous/UART] 5 6 read SC7SUART_CTR UART Control Set Register 0x3A 8 read-write n BRKE Set SC7UART_CTR.BRKE bit to 1 0 1 write BRKF This bit must be set to 0 . 1 2 write FM Set SC7UART_CTR.FM bit to 1 6 7 write NPE Set SC7UART_CTR.NPE bit to 1 3 4 write PM Set SC7UART_CTR.PM bit to 1 4 6 write __reserve0 This bit must be set to 0 . 2 3 write __reserve1 This bit must be set to 0 . 7 8 write SC7SYNC_CTR0 Clock-Synchronous Control Register 0x8 8 read-write n CE1 Clock polarity selection (SBT7) [Clock-Synchronous] 3 4 read-write CKPH Clock Source Edge Selection [Clock-Synchronous] 2 3 read-write FDC Output level selection after the final bit transmit (SBO7 pin) [Clock-Synchronous] 4 6 read-write SBCSEN SBCSn function selection [Clock-Synchronous] 1 2 read-write SBCSLV SBCS7 polarity selection [Clock-Synchronous] 0 1 read-write __reserve0 0 is always read out. 6 8 read SC7S_CTR0 Serial 7 Control Set Register 0 0x3C 8 read-write n CKM Set SC7_CTR0.CKM bit to 1 . 3 4 write CMD This bit must be set to 00 . 4 6 write DIR Set SC7_CTR0.DIR bit to 1 . 6 7 write IOM Set SC7_CTR0.IOM bit to 1 . 2 3 write MST Set SC7_CTR0.MST bit to 1 . 7 8 write SBIS Set SC7_CTR0.SBIS bit to 1 . 1 2 write SBOS Set SC7_CTR0.SBOS bit to 1 . 0 1 write SC7S_CTR1 Serial 7 Control Set Register 1 0x3D 8 read-write n DIV Set C7_CTR1.DIV bit to 1 . 3 4 write LNG This bit must be set to 000 . 4 7 write STREQ Communication start trigger by software (*1)(*2) 0 1 write TRGSEL This bit must be set to 00 . 1 3 write __reserve0 This bit must be set to 0 . 7 8 write SC7S_RST Serial 7 Reset Set Register 0x3E 8 read-write n RSRN SetSC7_RST.RSRN bit to 1 1 2 write RSTN Set SC7_RST.RSTN bit to 1 0 1 write __reserve0 This bit must be set to 00 . 2 8 write SC7TB Serial 7 Transmission Data Buffer Register 0x12 8 read-write n TB Set the transmission data or the dummy data. 0 8 read-write SC7UART_CTR UART Control Register 0xA 8 read-write n BRKE Break transmission control [UART] 0 1 read-write BRKF Break reception detection [UART] 1 2 read FM The number of character bit and stop bit selection [UART] 6 7 read-write NPE Parity bit selection [UART] 3 4 read-write PM Parity bit function selection [UART] 4 6 read-write __reserve0 0 is always read out. 2 3 read __reserve1 0 is always read out. 7 8 read SC7_CTR0 Serial 7 control register 0 0xC 8 read-write n CKM [Clock-Synchronous] Division selection of transfer clock 3 4 read-write CMD Communication mode selection 4 6 read-write DIR Transfer first bit selection 6 7 read-write IOM Data input pin selection (*2) 2 3 read-write MST [Clock-Synchronous] 7 8 read-write SBIS SBIn/SBOn(SDAn) pin input control (*2) 1 2 read-write SBOS SBOn(SDAn) pin output control (*2) 0 1 read-write SC7_CTR1 Serial 7 control register 1 0xD 8 read-write n DIV Division value selection of transfer clock 3 4 read-write LNG Transfer bit count settings [Clock-Synchronous/UART] 4 7 read-write STREQ Communication start trigger by software (*1)(*2) 0 1 read TRGSEL Selection of communication start factor(*1) 1 3 read-write __reserve0 0 is always read out. 7 8 read SC7_RST Serial 7 Reset Register 0xE 8 read-write n RSRN [Clock-Synchronous] 1 2 read-write RSTN [Clock-Synchronous / IIC] 0 1 read-write __reserve0 00 is always read out. 2 8 read SMBUS SMBus Interface SMBUS 0x0 0x0 0x28 registers n G133 133 G134 134 G135 135 SYTM Clock Generator SYTM 0x0 0x0 0x2018 registers n G31 31 CHIPCKCTR Clock Control Register 0x0 32 read-write n HXOEN External high-speed oscillation (HXO) enable 1 2 read-write KEY_CODE Write enable code 16 32 write __reserve0 1 is always read out. 0 1 read __reserve1 0 is always read out. 2 16 read CHIPCKSEL Clock Selection Register 0x4 32 read-write n BASESEL Clock source selection for basic clock (BASECLK) 0 2 read-write KEY_CODE Write enable code 16 32 write __reserve0 0 is always read out. 2 16 read CHIPCKSTAT Clock Status Register 0x18 16 read-write n BASEST BASECLK operation status 8 11 read HRCEN Internal oscillation (HRC) enable status 4 5 read HRCOK Internal oscillation (HRC) stabilization status 0 1 read HXOEN External oscillation (HXO) enable status 5 6 read HXOOK External oscillation (HXO) stabilization status 1 2 read PLLEN PLL function enable status 6 7 read PLLOK PLL stabilization status 2 3 read __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 7 8 read __reserve2 0 is always read out. 11 16 read CHIPCKWAIT Clock Oscillation Stabilization Wait Register 0xC 32 read-write n HXOWAIT HXO oscillation stabilization wait cycle setting 0 4 read-write KEY_CODE Write enable code 16 32 write __reserve0 0 is always read out. 4 16 read CHIPCPUCKCTR CPU Clock Control Register 0x8 32 read-write n CPUCKDIV Setting of CPUCLK division ratio for BASECLK 0 2 read-write IOCKDIV Setting of IOCLK division ratio for CPUCLK 4 6 read-write KEY_CODE Write enable code 16 32 write __reserve0 0 is always read out. 2 4 read __reserve1 0 is always read out. 6 16 read CHIPCTLPPBL PPB Write Control Register 0x2010 32 read-write n AHBPCR AHBPCR write control 2 3 read-write DTCMCR DTCMCR write control 1 2 read-write ITCMCR ITCMCR write control 0 1 read-write KEY_CODE Write enable code 16 32 write VTOR VTOR write control 3 4 read-write __reserve0 0 is always read out. 4 16 read CHIPDSLEEPMD DEEPSLEEP Mode Control Register 0x1C 32 read-write n BCKEN BASECLK enable for DEEPSLEEP 7 8 read-write HXOEN External oscillation (HXO) enable for DEEPSLEEP 1 2 read-write KEY_CODE Write enable code 16 32 write PLLEN PLL enable for DEEPSLEEP 2 3 read-write __reserve0 1 is always read out. 0 1 read __reserve1 0 is always read out. 3 7 read __reserve2 0 is always read out. 8 16 read CHIPPERICKEN0 Peripheral Clock Enable Register 0 0x20 32 read-write n KEY_CODE Write enable code 16 32 write PECKEN0 Clock supply to GPWM0 0 1 read-write PECKEN1 Clock supply to GPWM1 1 2 read-write PECKEN10 Clock supply to GPWMA 10 11 read-write PECKEN11 Clock supply to GPWMB 11 12 read-write PECKEN13 Clock supply to DMA controller 13 14 read-write PECKEN14 Clock supply to CAN controller 14 15 read-write PECKEN2 Clock supply to GPWM2 2 3 read-write PECKEN3 Clock supply to GPWM3 3 4 read-write PECKEN4 Clock supply to GPWM4 4 5 read-write PECKEN5 Clock supply to GPWM5 5 6 read-write PECKEN6 Clock supply to GPWM6 6 7 read-write PECKEN7 Clock supply to GPWM7 7 8 read-write PECKEN8 Clock supply to GPWM8 8 9 read-write PECKEN9 Clock supply to GPWM9 9 10 read-write __reserve0 This bit must be set to 0 . 12 13 read-write __reserve1 0 is always read out. 15 16 read CHIPPERICKEN1 Peripheral Clock Enable Register 1 0x24 32 read-write n KEY_CODE Write enable code 16 32 write PECKEN0 Clock supply to Timer 0, 1 0 1 read-write PECKEN1 Clock supply to Timer 2, 3 1 2 read-write PECKEN10 Clock supply to Timer 23 10 11 read-write PECKEN11 Clock supply to Timer 24 11 12 read-write PECKEN12 Clock supply to Timer 25 12 13 read-write PECKEN2 Clock supply to Timer 4, 5 2 3 read-write PECKEN3 Clock supply to Timer 6, 7 3 4 read-write PECKEN4 Clock supply to Timer 8, 9 4 5 read-write PECKEN5 Clock supply to Timer 10, 11 5 6 read-write PECKEN6 Clock supply to Timer 12, 13 6 7 read-write PECKEN7 Clock supply to Timer 20 7 8 read-write PECKEN8 Clock supply to Timer 21 8 9 read-write PECKEN9 Clock supply to Timer 22 9 10 read-write __reserve0 0 is always read out. 13 16 read CHIPPERICKEN2 Peripheral Clock Enable Register 2 0x28 32 read-write n KEY_CODE Write enable code 16 32 write PECKEN0 Clock supply to A/D converter0 0 1 read-write PECKEN1 Clock supply to A/D converter1 1 2 read-write PECKEN10 Clock supply to Serial Interface 6 10 11 read-write PECKEN11 Clock supply to Serial Interface 7 11 12 read-write PECKEN14 Clock supply to SMBus controller 1 14 15 read-write PECKEN2 Clock supply to A/D converter2 2 3 read-write PECKEN3 Clock supply to MFA 3 4 read-write PECKEN4 Clock supply to Serial Interface 0 4 5 read-write PECKEN5 Clock supply to Serial Interface 1 5 6 read-write PECKEN6 Clock supply to Serial Interface 2 6 7 read-write PECKEN7 Clock supply to Serial Interface 3 7 8 read-write PECKEN8 Clock supply to Serial Interface 4 8 9 read-write PECKEN9 Clock supply to Serial Interface 5 9 10 read-write __reserve0 0 is always read out. 12 13 read __reserve1 This bit must be set to 0 . 13 14 read-write __reserve2 This bit must be set to 0 . 15 16 read-write CHIPPLLCTR1 PLL Control Register 1 0x10 32 read-write n KEY_CODE Write enable code 16 32 write PLL30M PLL clock output control for Power Control PWM using High-Resolution output 1 2 read-write PLLEN PLL function enable 0 1 read-write __reserve0 0 is always read out. 2 16 read CHIPPLLCTR2 PLL Control Register 2 0x14 32 read-write n KEY_CODE Write enable code 16 32 write PLLIDIV PLL input clock division ratio setting 8 10 read-write PLLMUL PLL multiplier value setting 0 6 read-write PLLODIV PLL output clock division ratio setting 6 7 read-write __reserve0 0 is always read out. 7 8 read __reserve1 0 is always read out. 10 16 read CHIPRSTCLR Reset Flag Clear Register 0x1014 32 read-write n CMONRFCL Clear CHIPRSTFLG.CMONRSTF by writing 5 6 write CSFTRFCL Clear CHIPRSTFLG.CSFTRSTF by writing 2 3 write EXTRFCL Clear CHIPRSTFLG.EXTRSTF by writing 1 2 write KEY_CODE Write enable code 16 32 write LOCRFCL Clear CHIPRSTFLG.LOCRSTF by writing 6 7 write PORFCL Clear CHIPRSTFLG.PORF by writing 0 1 write RRFCL Clear CHIPRSTFLG.RRSTF by writing 7 8 write SSFTRFCL Clear CHIPRSTFLG.SSFTRSTF by writing 3 4 write WDTRFCL Clear CHIPRSTFLG.WDTRSTF by writing 4 5 write __reserve0 0 is always read out. 8 16 read CHIPRSTCTR Reset Control Register 0x1000 32 read-write n KEY_CODE Write enable code 16 32 write RRSTREQ Reserved-at-debug reset request 1 2 read-write RSTREQ System software reset request 0 1 read-write __reserve0 0 is always read out. 2 16 read CHIPRSTFLG Reset Flag Register 0x1010 8 read-write n CMONRSTF Clock error detection reset flag 5 6 read CSFTRSTF CPU software reset flag 2 3 read EXTRSTF Pin reset flag 1 2 read LOCRSTF CPU LOCKUP reset flag 6 7 read PORF Power-on reset (POR) flag 0 1 read RRSTF Reserved-at-debug reset flag 7 8 read SSFTRSTF System software reset flag 3 4 read WDTRSTF WDT error detection reset flag 4 5 read CHIPTRCCKCTR Trace Clock Control Register 0x40 32 read-write n KEY_CODE Write enable code 16 32 write TCKDIV Setting of trace clock division ratio for CPUCLK 0 5 read-write TCKDLY Trace data delay control 8 9 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 9 16 read VGA VGA VGA 0x0 0x0 0x54 registers n VGA00CTR VGA00 Co00trol Register 0x10 8 read-write n EN Control of VGAn 0 1 read-write GAIN Setting of VGAn gain 4 8 read-write SHORT Short control 1 2 read-write __reserve0 0 is always read out. 2 4 read-write VGA01CTR VGA01 Co01trol Register 0x20 8 read-write n EN Control of VGAn 0 1 read-write GAIN Setting of VGAn gain 4 8 read-write SHORT Short control 1 2 read-write __reserve0 0 is always read out. 2 4 read-write VGA02CTR VGA02 Co02trol Register 0x30 8 read-write n EN Control of VGAn 0 1 read-write GAIN Setting of VGAn gain 4 8 read-write SHORT Short control 1 2 read-write __reserve0 0 is always read out. 2 4 read-write VGA1CTR VGA1 Co1trol Register 0x40 8 read-write n EN Control of VGAn 0 1 read-write GAIN Setting of VGAn gain 4 8 read-write SHORT Short control 1 2 read-write __reserve0 0 is always read out. 2 4 read-write VGA2CTR VGA2 Co2trol Register 0x50 8 read-write n EN Control of VGAn 0 1 read-write GAIN Setting of VGAn gain 4 8 read-write SHORT Short control 1 2 read-write __reserve0 0 is always read out. 2 4 read-write VGAC_PWCTR POWER Control Register 0x0 8 read-write n PW0EN Supply of reference current, reference voltage to VGA00, VGA01, VGA02, CMP00, CMP01, CMP10, CMP11, CMP20, CMP21 0 1 read-write PW1EN Supply of reference current, reference voltage to VGA1, CMP30, CMP31 1 2 read-write PW2EN Supply of reference current, reference voltage to VGA2, CMP40, CMP41 2 3 read-write __reserve0 0 is always read out. 3 8 read WDT Watchdog Timer WDT 0x0 0x0 0x18 registers n WDTBC Watchdog Timer Binary Counter 0xC 8 read-write n WDBC Value of WDT binary counter is read out. 0 8 read WDTCLR Watchdog Timer Clear Register 0x8 8 read-write n WDCL Writing 0xA5 clears WDT counter. 0 8 write WDTCTR1 Watchdog Timer Control Register 1 0x0 32 read-write n KEY_CODE Register Key 16 32 write WDCEN WDT count enable 7 8 read-write WDCK Selection of binary counter clock source 0 4 read-write __reserve0 0 is always read out. 4 7 read __reserve1 0 is always read out. 8 16 read WDTCTR2 Watchdog Timer Control Register 2 0x4 32 read-write n KEY_CODE Register Key 16 32 write WDSTB WDT count control in standby mode (SLEEP mode, DEEPSLEEP mode) 4 6 read-write WDWIN Settings of the time WDT counter can be cleared (window open period) 0 3 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 6 16 read WDTERR Watchdog Timer Error Flag Register 0x10 8 read-write n CLRERR Occurrence of WDT clear data error 3 4 read WDOVF Occurrence of WDT overflow error 0 1 read WINERR Occurrence of WDT window error 2 3 read __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read WDTERRCLR Watchdog Timer Error Flag Clear Register 0x14 32 read-write n KEY_CODE Register Key 16 32 write WDERRC Setting bit of WDERRC to 1 clears the corresponding bit of WDTERR. 0 8 write __reserve0 0 is always read out. 8 16 read _16TM 16-bit Timer _16TM 0x0 0x0 0x2F296 registers n G80 80 G81 81 G82 82 G83 83 G84 84 G85 85 G86 86 G87 87 G88 88 G89 89 G90 90 G91 91 G92 92 G93 93 G94 94 G95 95 G96 96 G97 97 G98 98 G99 99 G100 100 G101 101 G102 102 G103 103 G104 104 G105 105 G106 106 TM0BC Timer 0 Bi0ary Cou0ter 0x2F010 16 read-write n BC Value of the binary counter is read out. 0 16 read TM0CA Timer 0 Compare/Capture A Register 0x2F014 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM0CAPASEL Timer 0 Capture A Factor Selectio0 Register 0x2F020 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM0CAPBSEL Timer 0 Capture B Factor Selectio0 Register 0x2F024 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM0CAPCSEL Timer 0 Capture C Factor Selectio0 Register 0x2F028 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM0CB Timer 0 Compare/Capture B Register 0x2F018 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM0CC Timer 0 Compare/Capture C Register 0x2F01C 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM0IRQCNT Timer 0 I0terrupt Output Co0trol Register 0x2F034 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM0MD Timer 0 Mode Register 0x2F000 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM0MDA Timer 0 Compare/Capture A Mode Register 0x2F004 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM0MDB Timer 0 Compare/Capture B Mode Register 0x2F005 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM0MDC Timer 0 Compare/Capture C Mode Register 0x2F008 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM0OFF Timer 0 Pi0 Protectio0 Co0trol Register 0x2F040 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM0OFFSEL Timer 0 Pi0 Protectio0 Factor Selectio0 Register 0x2F044 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM0STR Timer 0 Cou0t Directio0 Status Register 0x2F050 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM0STSEL Timer 0 Start Trigger Factor Selectio0 Register 0x2F030 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM10BC Timer 10 Bi10ary Cou10ter 0x2F1F0 16 read-write n BC Value of the binary counter is read out. 0 16 read TM10CA Timer 10 Compare/Capture A Register 0x2F1F4 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM10CAPASEL Timer 10 Capture A Factor Selectio10 Register 0x2F200 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM10CAPBSEL Timer 10 Capture B Factor Selectio10 Register 0x2F204 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM10CAPCSEL Timer 10 Capture C Factor Selectio10 Register 0x2F208 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM10CB Timer 10 Compare/Capture B Register 0x2F1F8 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM10CC Timer 10 Compare/Capture C Register 0x2F1FC 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM10IRQCNT Timer 10 I10terrupt Output Co10trol Register 0x2F214 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM10MD Timer 10 Mode Register 0x2F1E0 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM10MDA Timer 10 Compare/Capture A Mode Register 0x2F1E4 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM10MDB Timer 10 Compare/Capture B Mode Register 0x2F1E5 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM10MDC Timer 10 Compare/Capture C Mode Register 0x2F1E8 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM10OFF Timer 10 Pi10 Protectio10 Co10trol Register 0x2F220 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM10OFFSEL Timer 10 Pi10 Protectio10 Factor Selectio10 Register 0x2F224 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM10STR Timer 10 Cou10t Directio10 Status Register 0x2F230 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM10STSEL Timer 10 Start Trigger Factor Selectio10 Register 0x2F210 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM11BC Timer 11 Bi11ary Cou11ter 0x2F1F2 16 read-write n BC Value of the binary counter is read out. 0 16 read TM11CA Timer 11 Compare/Capture A Register 0x2F1F6 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM11CAPASEL Timer 11 Capture A Factor Selectio11 Register 0x2F202 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM11CAPBSEL Timer 11 Capture B Factor Selectio11 Register 0x2F206 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM11CAPCSEL Timer 11 Capture C Factor Selectio11 Register 0x2F20A 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM11CB Timer 11 Compare/Capture B Register 0x2F1FA 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM11CC Timer 11 Compare/Capture C Register 0x2F1FE 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM11IRQCNT Timer 11 I11terrupt Output Co11trol Register 0x2F216 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM11MD Timer 11 Mode Register 0x2F1E2 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM11MDA Timer 11 Compare/Capture A Mode Register 0x2F1E6 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM11MDB Timer 11 Compare/Capture B Mode Register 0x2F1E7 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM11MDC Timer 11 Compare/Capture C Mode Register 0x2F1EA 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM11OFF Timer 11 Pi11 Protectio11 Co11trol Register 0x2F222 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM11OFFSEL Timer 11 Pi11 Protectio11 Factor Selectio11 Register 0x2F226 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM11STR Timer 11 Cou11t Directio11 Status Register 0x2F232 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM11STSEL Timer 11 Start Trigger Factor Selectio11 Register 0x2F212 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM12BC Timer 12 Bi12ary Cou12ter 0x2F250 16 read-write n BC Value of the binary counter is read out. 0 16 read TM12CA Timer 12 Compare/Capture A Register 0x2F254 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM12CAPASEL Timer 12 Capture A Factor Selectio12 Register 0x2F260 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM12CAPBSEL Timer 12 Capture B Factor Selectio12 Register 0x2F264 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM12CAPCSEL Timer 12 Capture C Factor Selectio12 Register 0x2F268 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM12CB Timer 12 Compare/Capture B Register 0x2F258 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM12CC Timer 12 Compare/Capture C Register 0x2F25C 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM12IRQCNT Timer 12 I12terrupt Output Co12trol Register 0x2F274 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM12MD Timer 12 Mode Register 0x2F240 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM12MDA Timer 12 Compare/Capture A Mode Register 0x2F244 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM12MDB Timer 12 Compare/Capture B Mode Register 0x2F245 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM12MDC Timer 12 Compare/Capture C Mode Register 0x2F248 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM12OFF Timer 12 Pi12 Protectio12 Co12trol Register 0x2F280 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM12OFFSEL Timer 12 Pi12 Protectio12 Factor Selectio12 Register 0x2F284 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM12STR Timer 12 Cou12t Directio12 Status Register 0x2F290 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM12STSEL Timer 12 Start Trigger Factor Selectio12 Register 0x2F270 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM13BC Timer 13 Bi13ary Cou13ter 0x2F252 16 read-write n BC Value of the binary counter is read out. 0 16 read TM13CA Timer 13 Compare/Capture A Register 0x2F256 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM13CAPASEL Timer 13 Capture A Factor Selectio13 Register 0x2F262 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM13CAPBSEL Timer 13 Capture B Factor Selectio13 Register 0x2F266 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM13CAPCSEL Timer 13 Capture C Factor Selectio13 Register 0x2F26A 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM13CB Timer 13 Compare/Capture B Register 0x2F25A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM13CC Timer 13 Compare/Capture C Register 0x2F25E 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM13IRQCNT Timer 13 I13terrupt Output Co13trol Register 0x2F276 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM13MD Timer 13 Mode Register 0x2F242 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM13MDA Timer 13 Compare/Capture A Mode Register 0x2F246 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM13MDB Timer 13 Compare/Capture B Mode Register 0x2F247 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM13MDC Timer 13 Compare/Capture C Mode Register 0x2F24A 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM13OFF Timer 13 Pi13 Protectio13 Co13trol Register 0x2F282 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM13OFFSEL Timer 13 Pi13 Protectio13 Factor Selectio13 Register 0x2F286 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM13STR Timer 13 Cou13t Directio13 Status Register 0x2F292 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM13STSEL Timer 13 Start Trigger Factor Selectio13 Register 0x2F272 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM1BC Timer 1 Bi1ary Cou1ter 0x2F012 16 read-write n BC Value of the binary counter is read out. 0 16 read TM1CA Timer 1 Compare/Capture A Register 0x2F016 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM1CAPASEL Timer 1 Capture A Factor Selectio1 Register 0x2F022 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM1CAPBSEL Timer 1 Capture B Factor Selectio1 Register 0x2F026 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM1CAPCSEL Timer 1 Capture C Factor Selectio1 Register 0x2F02A 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM1CB Timer 1 Compare/Capture B Register 0x2F01A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM1CC Timer 1 Compare/Capture C Register 0x2F01E 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM1IRQCNT Timer 1 I1terrupt Output Co1trol Register 0x2F036 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM1MD Timer 1 Mode Register 0x2F002 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM1MDA Timer 1 Compare/Capture A Mode Register 0x2F006 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM1MDB Timer 1 Compare/Capture B Mode Register 0x2F007 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM1MDC Timer 1 Compare/Capture C Mode Register 0x2F00A 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM1OFF Timer 1 Pi1 Protectio1 Co1trol Register 0x2F042 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM1OFFSEL Timer 1 Pi1 Protectio1 Factor Selectio1 Register 0x2F046 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM1STR Timer 1 Cou1t Directio1 Status Register 0x2F052 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM1STSEL Timer 1 Start Trigger Factor Selectio1 Register 0x2F032 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM20BC Timer 20 Bi20ary Cou20ter 0x10 16 read-write n BC Value of the binary counter is read out. 0 16 read TM20CA Timer 20 Compare/Capture A Register 0x14 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM20CAPASEL Timer 20 Capture A Factor Selectio20 Register 0x24 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM20CAPBSEL Timer 20 Capture B Factor Selectio20 Register 0x28 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM20CAPCSEL Timer 20 Capture C Factor Selectio20 Register 0x2C 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM20CB Timer 20 Compare/Capture B Register 0x1A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM20CC Timer 20 Compare/Capture C Register 0x20 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM20DTMSET Timer 20 Dead Time Setti20g Register 0x50 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM20IRQCNT Timer 20 I20terrupt Output Co20trol Register 0x34 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM20LEBSET Timer 20 Leadi20g Edge Bla20ki20g Setti20g Register 0x58 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM20MD1 Timer 20 Mode1 Register 0x0 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM20MD2 Timer 20 Mode2 Register 0x4 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM20MDA Timer 20 Compare/Capture A Mode Register 0x8 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM20MDB Timer 20 Compare/Capture B Mode Register 0x9 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM20MDC Timer 20 Compare/Capture C Mode Register 0xC 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM20OFFA Timer 20 Pi20 Protectio20 Co20trol Register 0x40 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM20OFFASEL Timer 20 Pi20 Protectio20 Factor Selectio20 Register 0x44 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM20OFFB Timer 20 Duty Cut/Period Cut Co20trol Register 0x48 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM20OFFBSEL Timer 20 Duty Cut/Period Cut Factor Selectio20 Register 0x4C 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM20OFFSTR Timer 20 Pi20 Protectio20 Status Register 0x64 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM20SFTSET Timer 20 Output Shift Amou20t Setti20g Register 0x54 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM20STR Timer 20 Cou20t Directio20 Status Register 0x60 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM20STSEL Timer 20 Start Trigger Factor Selectio20 Register 0x30 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM20TSKOVFSEL Timer 20 Task Overflow Object Selectio20 Register 0x68 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM21BC Timer 21 Bi21ary Cou21ter 0x12 16 read-write n BC Value of the binary counter is read out. 0 16 read TM21CA Timer 21 Compare/Capture A Register 0x16 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM21CAPASEL Timer 21 Capture A Factor Selectio21 Register 0x26 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM21CAPBSEL Timer 21 Capture B Factor Selectio21 Register 0x2A 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM21CAPCSEL Timer 21 Capture C Factor Selectio21 Register 0x2E 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM21CB Timer 21 Compare/Capture B Register 0x1E 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM21CC Timer 21 Compare/Capture C Register 0x22 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM21DTMSET Timer 21 Dead Time Setti21g Register 0x52 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM21IRQCNT Timer 21 I21terrupt Output Co21trol Register 0x36 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM21LEBSET Timer 21 Leadi21g Edge Bla21ki21g Setti21g Register 0x5A 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM21MD1 Timer 21 Mode1 Register 0x2 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM21MD2 Timer 21 Mode2 Register 0x6 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM21MDA Timer 21 Compare/Capture A Mode Register 0xA 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM21MDB Timer 21 Compare/Capture B Mode Register 0xB 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM21MDC Timer 21 Compare/Capture C Mode Register 0xE 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM21OFFA Timer 21 Pi21 Protectio21 Co21trol Register 0x42 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM21OFFASEL Timer 21 Pi21 Protectio21 Factor Selectio21 Register 0x46 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM21OFFB Timer 21 Duty Cut/Period Cut Co21trol Register 0x4A 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM21OFFBSEL Timer 21 Duty Cut/Period Cut Factor Selectio21 Register 0x4E 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM21OFFSTR Timer 21 Pi21 Protectio21 Status Register 0x66 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM21SFTSET Timer 21 Output Shift Amou21t Setti21g Register 0x56 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM21STR Timer 21 Cou21t Directio21 Status Register 0x62 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM21STSEL Timer 21 Start Trigger Factor Selectio21 Register 0x32 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM21TSKOVFSEL Timer 21 Task Overflow Object Selectio21 Register 0x6A 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM22BC Timer 22 Bi22ary Cou22ter 0x110 16 read-write n BC Value of the binary counter is read out. 0 16 read TM22CA Timer 22 Compare/Capture A Register 0x114 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM22CAPASEL Timer 22 Capture A Factor Selectio22 Register 0x124 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM22CAPBSEL Timer 22 Capture B Factor Selectio22 Register 0x128 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM22CAPCSEL Timer 22 Capture C Factor Selectio22 Register 0x12C 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM22CB Timer 22 Compare/Capture B Register 0x11A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM22CC Timer 22 Compare/Capture C Register 0x120 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM22DTMSET Timer 22 Dead Time Setti22g Register 0x150 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM22IRQCNT Timer 22 I22terrupt Output Co22trol Register 0x134 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM22LEBSET Timer 22 Leadi22g Edge Bla22ki22g Setti22g Register 0x158 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM22MD1 Timer 22 Mode1 Register 0x100 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM22MD2 Timer 22 Mode2 Register 0x104 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM22MDA Timer 22 Compare/Capture A Mode Register 0x108 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM22MDB Timer 22 Compare/Capture B Mode Register 0x109 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM22MDC Timer 22 Compare/Capture C Mode Register 0x10C 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM22OFFA Timer 22 Pi22 Protectio22 Co22trol Register 0x140 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM22OFFASEL Timer 22 Pi22 Protectio22 Factor Selectio22 Register 0x144 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM22OFFB Timer 22 Duty Cut/Period Cut Co22trol Register 0x148 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM22OFFBSEL Timer 22 Duty Cut/Period Cut Factor Selectio22 Register 0x14C 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM22OFFSTR Timer 22 Pi22 Protectio22 Status Register 0x164 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM22SFTSET Timer 22 Output Shift Amou22t Setti22g Register 0x154 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM22STR Timer 22 Cou22t Directio22 Status Register 0x160 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM22STSEL Timer 22 Start Trigger Factor Selectio22 Register 0x130 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM22TSKOVFSEL Timer 22 Task Overflow Object Selectio22 Register 0x168 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM23BC Timer 23 Bi23ary Cou23ter 0x112 16 read-write n BC Value of the binary counter is read out. 0 16 read TM23CA Timer 23 Compare/Capture A Register 0x116 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM23CAPASEL Timer 23 Capture A Factor Selectio23 Register 0x126 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM23CAPBSEL Timer 23 Capture B Factor Selectio23 Register 0x12A 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM23CAPCSEL Timer 23 Capture C Factor Selectio23 Register 0x12E 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM23CB Timer 23 Compare/Capture B Register 0x11E 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM23CC Timer 23 Compare/Capture C Register 0x122 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM23DTMSET Timer 23 Dead Time Setti23g Register 0x152 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM23IRQCNT Timer 23 I23terrupt Output Co23trol Register 0x136 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM23LEBSET Timer 23 Leadi23g Edge Bla23ki23g Setti23g Register 0x15A 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM23MD1 Timer 23 Mode1 Register 0x102 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM23MD2 Timer 23 Mode2 Register 0x106 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM23MDA Timer 23 Compare/Capture A Mode Register 0x10A 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM23MDB Timer 23 Compare/Capture B Mode Register 0x10B 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM23MDC Timer 23 Compare/Capture C Mode Register 0x10E 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM23OFFA Timer 23 Pi23 Protectio23 Co23trol Register 0x142 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM23OFFASEL Timer 23 Pi23 Protectio23 Factor Selectio23 Register 0x146 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM23OFFB Timer 23 Duty Cut/Period Cut Co23trol Register 0x14A 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM23OFFBSEL Timer 23 Duty Cut/Period Cut Factor Selectio23 Register 0x14E 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM23OFFSTR Timer 23 Pi23 Protectio23 Status Register 0x166 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM23SFTSET Timer 23 Output Shift Amou23t Setti23g Register 0x156 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM23STR Timer 23 Cou23t Directio23 Status Register 0x162 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM23STSEL Timer 23 Start Trigger Factor Selectio23 Register 0x132 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM23TSKOVFSEL Timer 23 Task Overflow Object Selectio23 Register 0x16A 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM24BC Timer 24 Bi24ary Cou24ter 0x210 16 read-write n BC Value of the binary counter is read out. 0 16 read TM24CA Timer 24 Compare/Capture A Register 0x214 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM24CAPASEL Timer 24 Capture A Factor Selectio24 Register 0x224 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM24CAPBSEL Timer 24 Capture B Factor Selectio24 Register 0x228 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM24CAPCSEL Timer 24 Capture C Factor Selectio24 Register 0x22C 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM24CB Timer 24 Compare/Capture B Register 0x21A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM24CC Timer 24 Compare/Capture C Register 0x220 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM24DTMSET Timer 24 Dead Time Setti24g Register 0x250 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM24IRQCNT Timer 24 I24terrupt Output Co24trol Register 0x234 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM24LEBSET Timer 24 Leadi24g Edge Bla24ki24g Setti24g Register 0x258 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM24MD1 Timer 24 Mode1 Register 0x200 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM24MD2 Timer 24 Mode2 Register 0x204 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM24MDA Timer 24 Compare/Capture A Mode Register 0x208 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM24MDB Timer 24 Compare/Capture B Mode Register 0x209 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM24MDC Timer 24 Compare/Capture C Mode Register 0x20C 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM24OFFA Timer 24 Pi24 Protectio24 Co24trol Register 0x240 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM24OFFASEL Timer 24 Pi24 Protectio24 Factor Selectio24 Register 0x244 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM24OFFB Timer 24 Duty Cut/Period Cut Co24trol Register 0x248 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM24OFFBSEL Timer 24 Duty Cut/Period Cut Factor Selectio24 Register 0x24C 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM24OFFSTR Timer 24 Pi24 Protectio24 Status Register 0x264 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM24SFTSET Timer 24 Output Shift Amou24t Setti24g Register 0x254 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM24STR Timer 24 Cou24t Directio24 Status Register 0x260 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM24STSEL Timer 24 Start Trigger Factor Selectio24 Register 0x230 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM24TSKOVFSEL Timer 24 Task Overflow Object Selectio24 Register 0x268 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM25BC Timer 25 Bi25ary Cou25ter 0x212 16 read-write n BC Value of the binary counter is read out. 0 16 read TM25CA Timer 25 Compare/Capture A Register 0x216 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM25CAPASEL Timer 25 Capture A Factor Selectio25 Register 0x226 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM25CAPBSEL Timer 25 Capture B Factor Selectio25 Register 0x22A 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM25CAPCSEL Timer 25 Capture C Factor Selectio25 Register 0x22E 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM25CB Timer 25 Compare/Capture B Register 0x21E 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM25CC Timer 25 Compare/Capture C Register 0x222 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM25DTMSET Timer 25 Dead Time Setti25g Register 0x252 16 read-write n DTSTA Dead time setting of Timer A pin 0 8 read-write DTSTB Dead time setting of Timer B pin 8 16 read-write TM25IRQCNT Timer 25 I25terrupt Output Co25trol Register 0x236 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM25LEBSET Timer 25 Leadi25g Edge Bla25ki25g Setti25g Register 0x25A 16 read-write n LEBST Set the blanking amount. 0 10 read-write __reserve0 0 is always read out. 10 16 read TM25MD1 Timer 25 Mode1 Register 0x202 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source selection 0 4 read-write CKEG Clock source edge selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer one-shot operation enable 12 13 read-write PSCNE Pre-scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM25MD2 Timer 25 Mode2 Register 0x206 16 read-write n DTEN Dead time insertion 2 3 read-write LEBEN Leading edge blanking setting enable 8 9 read-write ORMDA Dead time insertion logic (TMnA) 3 4 read-write ORMDB Dead time insertion logic (TMnB) 4 5 read-write OUTMD Output mode 0 1 read-write PXDTA Output polarity of TMnA 6 7 read-write PXDTB Output polarity of TMnB 7 8 read-write SFTEN Output shift control enable 9 10 read-write SLFCNT Dead time width auto control enable 5 6 read-write TSKOVFEN Task overflow detection enable 1 2 read-write __reserve0 This bit must be set to 0. 10 11 read-write __reserve1 0 is always read out. 11 16 read TM25MDA Timer 25 Compare/Capture A Mode Register 0x20A 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM25MDB Timer 25 Compare/Capture B Mode Register 0x20B 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM25MDC Timer 25 Compare/Capture C Mode Register 0x20E 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM25OFFA Timer 25 Pi25 Protectio25 Co25trol Register 0x242 16 read-write n AOFFA TMnA pin output protection 8 10 read-write BOFFA TMnB pin output protection 10 12 read-write PRTAEN Pin protection enable 0 1 read-write PRTASEL Protection factor polarity selection 2 3 read-write PRTASTCLR TMnOFFSTR.PRTAST clear operation 3 4 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 4 8 read __reserve2 0 is always read out. 12 16 read TM25OFFASEL Timer 25 Pi25 Protectio25 Factor Selectio25 Register 0x246 16 read-write n AD0APAE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPAE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APAE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPAE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PAE Protection factor selection by CMP00 9 10 read-write CMP1PAE Protection factor selection by CMP10 10 11 read-write CMP2PAE Protection factor selection by CMP20 11 12 read-write IRQ0PAE Protection factor selection by IRQ00 0 1 read-write IRQ1PAE Protection factor selection by IRQ01 1 2 read-write IRQ2PAE Protection factor selection by IRQ08 2 3 read-write IRQ3PAE Protection factor selection by IRQ09 3 4 read-write IRQ4PAE Protection factor selection by IRQ14 4 5 read-write IRQ5PAE Protection factor selection by IRQ15 5 6 read-write IRQ6PAE Protection factor selection by IRQ18 6 7 read-write IRQ7PAE Protection factor selection by IRQ19 7 8 read-write NMIPAE Protection factor selection by NMI 8 9 read-write TM25OFFB Timer 25 Duty Cut/Period Cut Co25trol Register 0x24A 16 read-write n AOFFB Duty cut function of TMnA pin output 8 10 read-write BOFFB Duty cut function of TMnB pin output 10 12 read-write PRTBEN Duty cut/period cut enable 0 1 read-write PRTBMD Operation selection 1 2 read-write PRTBRLS Return at the end of periodic 4 5 read-write PRTBSEL Duty cut/period cut factor polarity selection 2 3 read-write PRTBSTCLR TMnOFFSTR.PRTBST clear operation 3 4 read-write __reserve0 0 is always read out. 5 8 read __reserve1 0 is always read out. 12 16 read TM25OFFBSEL Timer 25 Duty Cut/Period Cut Factor Selectio25 Register 0x24E 16 read-write n CMP0PBE Duty cut/period cut factor selection by CMP00 8 9 read CMP1PBE Duty cut/period cut factor selection by CMP10 9 10 read-write CMP2PBE Duty cut/period cut factor selection by CMP20 10 11 read-write IRQ0PBE Duty cut/period cut factor selection by IRQ00 0 1 read-write IRQ1PBE Duty cut/period cut factor selection by IRQ01 1 2 read-write IRQ2PBE Duty cut/period cut factor selection by IRQ08 2 3 read-write IRQ3PBE Duty cut/period cut factor selection by IRQ09 3 4 read-write IRQ4PBE Duty cut/period cut factor selection by IRQ14 4 5 read-write IRQ5PBE Duty cut/period cut factor selection by IRQ15 5 6 read-write IRQ6PBE Duty cut/period cut factor selection by IRQ18 6 7 read-write IRQ7PBE Duty cut/period cut factor selection by IRQ19 7 8 read-write __reserve0 0 is always read out. 11 16 read TM25OFFSTR Timer 25 Pi25 Protectio25 Status Register 0x266 16 read-write n PRTAST Pin protection function state 0 1 read PRTBST Duty cut function state 1 2 read __reserve0 0 is always read out. 2 16 read TM25SFTSET Timer 25 Output Shift Amou25t Setti25g Register 0x256 16 read-write n SFTST Set the shift amount of timer pin output. 0 16 read-write TM25STR Timer 25 Cou25t Directio25 Status Register 0x262 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM25STSEL Timer 25 Start Trigger Factor Selectio25 Register 0x232 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM25TSKOVFSEL Timer 25 Task Overflow Object Selectio25 Register 0x26A 16 read-write n TSKOVFE0 Set TMnCA as task overflow judgment object. 0 1 read-write TSKOVFE1 Set TMnCB as task overflow judgment object. 1 2 read-write __reserve0 0 is always read out. 2 16 read TM2BC Timer 2 Bi2ary Cou2ter 0x2F070 16 read-write n BC Value of the binary counter is read out. 0 16 read TM2CA Timer 2 Compare/Capture A Register 0x2F074 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM2CAPASEL Timer 2 Capture A Factor Selectio2 Register 0x2F080 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM2CAPBSEL Timer 2 Capture B Factor Selectio2 Register 0x2F084 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM2CAPCSEL Timer 2 Capture C Factor Selectio2 Register 0x2F088 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM2CB Timer 2 Compare/Capture B Register 0x2F078 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM2CC Timer 2 Compare/Capture C Register 0x2F07C 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM2IRQCNT Timer 2 I2terrupt Output Co2trol Register 0x2F094 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM2MD Timer 2 Mode Register 0x2F060 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM2MDA Timer 2 Compare/Capture A Mode Register 0x2F064 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM2MDB Timer 2 Compare/Capture B Mode Register 0x2F065 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM2MDC Timer 2 Compare/Capture C Mode Register 0x2F068 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM2OFF Timer 2 Pi2 Protectio2 Co2trol Register 0x2F0A0 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM2OFFSEL Timer 2 Pi2 Protectio2 Factor Selectio2 Register 0x2F0A4 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM2STR Timer 2 Cou2t Directio2 Status Register 0x2F0B0 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM2STSEL Timer 2 Start Trigger Factor Selectio2 Register 0x2F090 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM3BC Timer 3 Bi3ary Cou3ter 0x2F072 16 read-write n BC Value of the binary counter is read out. 0 16 read TM3CA Timer 3 Compare/Capture A Register 0x2F076 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM3CAPASEL Timer 3 Capture A Factor Selectio3 Register 0x2F082 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM3CAPBSEL Timer 3 Capture B Factor Selectio3 Register 0x2F086 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM3CAPCSEL Timer 3 Capture C Factor Selectio3 Register 0x2F08A 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM3CB Timer 3 Compare/Capture B Register 0x2F07A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM3CC Timer 3 Compare/Capture C Register 0x2F07E 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM3IRQCNT Timer 3 I3terrupt Output Co3trol Register 0x2F096 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM3MD Timer 3 Mode Register 0x2F062 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM3MDA Timer 3 Compare/Capture A Mode Register 0x2F066 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM3MDB Timer 3 Compare/Capture B Mode Register 0x2F067 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM3MDC Timer 3 Compare/Capture C Mode Register 0x2F06A 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM3OFF Timer 3 Pi3 Protectio3 Co3trol Register 0x2F0A2 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM3OFFSEL Timer 3 Pi3 Protectio3 Factor Selectio3 Register 0x2F0A6 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM3STR Timer 3 Cou3t Directio3 Status Register 0x2F0B2 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM3STSEL Timer 3 Start Trigger Factor Selectio3 Register 0x2F092 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM4BC Timer 4 Bi4ary Cou4ter 0x2F0D0 16 read-write n BC Value of the binary counter is read out. 0 16 read TM4CA Timer 4 Compare/Capture A Register 0x2F0D4 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM4CAPASEL Timer 4 Capture A Factor Selectio4 Register 0x2F0E0 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM4CAPBSEL Timer 4 Capture B Factor Selectio4 Register 0x2F0E4 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM4CAPCSEL Timer 4 Capture C Factor Selectio4 Register 0x2F0E8 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM4CB Timer 4 Compare/Capture B Register 0x2F0D8 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM4CC Timer 4 Compare/Capture C Register 0x2F0DC 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM4IRQCNT Timer 4 I4terrupt Output Co4trol Register 0x2F0F4 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM4MD Timer 4 Mode Register 0x2F0C0 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM4MDA Timer 4 Compare/Capture A Mode Register 0x2F0C4 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM4MDB Timer 4 Compare/Capture B Mode Register 0x2F0C5 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM4MDC Timer 4 Compare/Capture C Mode Register 0x2F0C8 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM4OFF Timer 4 Pi4 Protectio4 Co4trol Register 0x2F100 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM4OFFSEL Timer 4 Pi4 Protectio4 Factor Selectio4 Register 0x2F104 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM4STR Timer 4 Cou4t Directio4 Status Register 0x2F110 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM4STSEL Timer 4 Start Trigger Factor Selectio4 Register 0x2F0F0 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM5BC Timer 5 Bi5ary Cou5ter 0x2F0D2 16 read-write n BC Value of the binary counter is read out. 0 16 read TM5CA Timer 5 Compare/Capture A Register 0x2F0D6 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM5CAPASEL Timer 5 Capture A Factor Selectio5 Register 0x2F0E2 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM5CAPBSEL Timer 5 Capture B Factor Selectio5 Register 0x2F0E6 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM5CAPCSEL Timer 5 Capture C Factor Selectio5 Register 0x2F0EA 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM5CB Timer 5 Compare/Capture B Register 0x2F0DA 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM5CC Timer 5 Compare/Capture C Register 0x2F0DE 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM5IRQCNT Timer 5 I5terrupt Output Co5trol Register 0x2F0F6 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM5MD Timer 5 Mode Register 0x2F0C2 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM5MDA Timer 5 Compare/Capture A Mode Register 0x2F0C6 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM5MDB Timer 5 Compare/Capture B Mode Register 0x2F0C7 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM5MDC Timer 5 Compare/Capture C Mode Register 0x2F0CA 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM5OFF Timer 5 Pi5 Protectio5 Co5trol Register 0x2F102 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM5OFFSEL Timer 5 Pi5 Protectio5 Factor Selectio5 Register 0x2F106 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM5STR Timer 5 Cou5t Directio5 Status Register 0x2F112 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM5STSEL Timer 5 Start Trigger Factor Selectio5 Register 0x2F0F2 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM6BC Timer 6 Bi6ary Cou6ter 0x2F130 16 read-write n BC Value of the binary counter is read out. 0 16 read TM6CA Timer 6 Compare/Capture A Register 0x2F134 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM6CAPASEL Timer 6 Capture A Factor Selectio6 Register 0x2F140 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM6CAPBSEL Timer 6 Capture B Factor Selectio6 Register 0x2F144 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM6CAPCSEL Timer 6 Capture C Factor Selectio6 Register 0x2F148 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM6CB Timer 6 Compare/Capture B Register 0x2F138 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM6CC Timer 6 Compare/Capture C Register 0x2F13C 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM6IRQCNT Timer 6 I6terrupt Output Co6trol Register 0x2F154 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM6MD Timer 6 Mode Register 0x2F120 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM6MDA Timer 6 Compare/Capture A Mode Register 0x2F124 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM6MDB Timer 6 Compare/Capture B Mode Register 0x2F125 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM6MDC Timer 6 Compare/Capture C Mode Register 0x2F128 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM6OFF Timer 6 Pi6 Protectio6 Co6trol Register 0x2F160 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM6OFFSEL Timer 6 Pi6 Protectio6 Factor Selectio6 Register 0x2F164 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM6STR Timer 6 Cou6t Directio6 Status Register 0x2F170 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM6STSEL Timer 6 Start Trigger Factor Selectio6 Register 0x2F150 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM7BC Timer 7 Bi7ary Cou7ter 0x2F132 16 read-write n BC Value of the binary counter is read out. 0 16 read TM7CA Timer 7 Compare/Capture A Register 0x2F136 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM7CAPASEL Timer 7 Capture A Factor Selectio7 Register 0x2F142 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM7CAPBSEL Timer 7 Capture B Factor Selectio7 Register 0x2F146 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM7CAPCSEL Timer 7 Capture C Factor Selectio7 Register 0x2F14A 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM7CB Timer 7 Compare/Capture B Register 0x2F13A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM7CC Timer 7 Compare/Capture C Register 0x2F13E 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM7IRQCNT Timer 7 I7terrupt Output Co7trol Register 0x2F156 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM7MD Timer 7 Mode Register 0x2F122 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM7MDA Timer 7 Compare/Capture A Mode Register 0x2F126 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM7MDB Timer 7 Compare/Capture B Mode Register 0x2F127 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM7MDC Timer 7 Compare/Capture C Mode Register 0x2F12A 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM7OFF Timer 7 Pi7 Protectio7 Co7trol Register 0x2F162 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM7OFFSEL Timer 7 Pi7 Protectio7 Factor Selectio7 Register 0x2F166 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM7STR Timer 7 Cou7t Directio7 Status Register 0x2F172 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM7STSEL Timer 7 Start Trigger Factor Selectio7 Register 0x2F152 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM8BC Timer 8 Bi8ary Cou8ter 0x2F190 16 read-write n BC Value of the binary counter is read out. 0 16 read TM8CA Timer 8 Compare/Capture A Register 0x2F194 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM8CAPASEL Timer 8 Capture A Factor Selectio8 Register 0x2F1A0 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM8CAPBSEL Timer 8 Capture B Factor Selectio8 Register 0x2F1A4 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM8CAPCSEL Timer 8 Capture C Factor Selectio8 Register 0x2F1A8 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM8CB Timer 8 Compare/Capture B Register 0x2F198 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM8CC Timer 8 Compare/Capture C Register 0x2F19C 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM8IRQCNT Timer 8 I8terrupt Output Co8trol Register 0x2F1B4 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM8MD Timer 8 Mode Register 0x2F180 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM8MDA Timer 8 Compare/Capture A Mode Register 0x2F184 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM8MDB Timer 8 Compare/Capture B Mode Register 0x2F185 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM8MDC Timer 8 Compare/Capture C Mode Register 0x2F188 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM8OFF Timer 8 Pi8 Protectio8 Co8trol Register 0x2F1C0 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM8OFFSEL Timer 8 Pi8 Protectio8 Factor Selectio8 Register 0x2F1C4 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM8STR Timer 8 Cou8t Directio8 Status Register 0x2F1D0 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM8STSEL Timer 8 Start Trigger Factor Selectio8 Register 0x2F1B0 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read TM9BC Timer 9 Bi9ary Cou9ter 0x2F192 16 read-write n BC Value of the binary counter is read out. 0 16 read TM9CA Timer 9 Compare/Capture A Register 0x2F196 16 read-write n CA It is a register corresponding to compare A and capture A operation. 0 16 read-write TM9CAPASEL Timer 9 Capture A Factor Selectio9 Register 0x2F1A2 16 read-write n AI0CAE The capture A factor selection of timer n. 10 11 read-write AI1CAE The capture A factor selection of timer n. 11 12 read-write IRQ0CAE The capture A factor selection of timer n. 0 1 read-write IRQ1CAE The capture A factor selection of timer n. 1 2 read-write IRQ2CAE The capture A factor selection of timer n. 2 3 read-write IRQ3CAE The capture A factor selection of timer n. 3 4 read-write IRQ4CAE The capture A factor selection of timer n. 4 5 read-write IRQ5CAE The capture A factor selection of timer n. 5 6 read-write IRQ6CAE The capture A factor selection of timer n. 6 7 read-write IRQ7CAE The capture A factor selection of timer n. 7 8 read-write UDF0CAE The capture A factor selection of timer n. 8 9 read-write UDF1CAE The capture A factor selection of timer n. 9 10 read-write __reserve0 0 is always read out. 12 16 read TM9CAPBSEL Timer 9 Capture B Factor Selectio9 Register 0x2F1A6 16 read-write n BI0CBE The capture B factor selection of timer n 10 11 read-write BI1CBE The capture B factor selection of timer n 11 12 read-write IRQ0CBE The capture B factor selection of timer n 0 1 read-write IRQ1CBE The capture B factor selection of timer n 1 2 read-write IRQ2CBE The capture B factor selection of timer n 2 3 read-write IRQ3CBE The capture B factor selection of timer n 3 4 read-write IRQ4CBE The capture B factor selection of timer n 4 5 read-write IRQ5CBE The capture B factor selection of timer n 5 6 read-write IRQ6CBE The capture B factor selection of timer n 6 7 read-write IRQ7CBE The capture B factor selection of timer n 7 8 read-write UDF0CBE The capture B factor selection of timer n 8 9 read-write UDF1CBE The capture B factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 12 16 read TM9CAPCSEL Timer 9 Capture C Factor Selectio9 Register 0x2F1AA 16 read-write n IRQ0CCE The capture C factor selection of timer n 0 1 read-write IRQ1CCE The capture C factor selection of timer n 1 2 read-write IRQ2CCE The capture C factor selection of timer n 2 3 read-write IRQ3CCE The capture C factor selection of timer n 3 4 read-write IRQ4CCE The capture C factor selection of timer n 4 5 read-write IRQ5CCE The capture C factor selection of timer n 5 6 read-write IRQ6CCE The capture C factor selection of timer n 6 7 read-write IRQ7CCE The capture C factor selection of timer n 7 8 read-write UDF0CCE The capture C factor selection of timer n 8 9 read-write UDF1CCE The capture C factor selection of timer n 9 10 read-write __reserve0 0 is always read out. 10 16 read TM9CB Timer 9 Compare/Capture B Register 0x2F19A 16 read-write n CB It is a register corresponding to compare B and capture B operation. 0 16 read-write TM9CC Timer 9 Compare/Capture C Register 0x2F19E 16 read-write n CC It is a register corresponding to compare C and capture C operation. 0 16 read-write TM9IRQCNT Timer 9 I9terrupt Output Co9trol Register 0x2F1B6 16 read-write n CNT Number of times setting for timer n compare/capture C interrupt (Second time or later) 0 4 read-write SCNT Number of times setting for timer n compare/capture C interrupt (First time) 4 8 read-write __reserve0 0 is always read out. 8 16 read TM9MD Timer 9 Mode Register 0x2F182 16 read-write n CGE Count clock mask enable 10 11 read-write CGESEL Timer count control selection 11 12 read-write CK Clock source Selection 0 4 read-write CKEG Clock Source Edge Selection 5 6 read-write CLE Timer binary counter clear enable 13 14 read-write CNE Time n operation enable(*1) 7 8 read-write LDE Timer n binary counter initialization 6 7 read-write ONE Timer 1-shot operation enable 12 13 read-write PSCNE Pre-Scalar operation enable 4 5 read-write UD Binary counter up/down selection 8 10 read-write XF The action status of the timer n 15 16 read __reserve0 0 is always read out. 14 15 read TM9MDA Timer 9 Compare/Capture A Mode Register 0x2F186 8 read-write n ACE Capture A operation enable 3 4 read-write ACLE Capture counter clear 4 5 read-write ACM Compare A operation mode selection 7 8 read-write AEG Capture factor A edge selection 5 7 read-write AO Timer pin A output waveform selection 0 2 read-write AOP Timer output polarity 2 3 read-write TM9MDB Timer 9 Compare/Capture B Mode Register 0x2F187 8 read-write n BCE Capture B operation enable 3 4 read-write BCLE Capture counter clear 4 5 read-write BCM Compare B operation mode selection 7 8 read-write BEG Capture factor B edge selection 5 7 read-write BO Timer pin A output waveform selection 0 2 read-write BOP Timer output polarity 2 3 read-write TM9MDC Timer 9 Compare/Capture C Mode Register 0x2F18A 8 read-write n ADSTE A/D start trigger enable 2 3 read-write CCE Capture C operation enable 3 4 read-write CCLE Capture counter clear 4 5 read-write CCM Compare C operation mode selection 7 8 read-write CEG Capture factor C edge selection 5 7 read-write __reserve0 0 is always read out. 0 2 read TM9OFF Timer 9 Pi9 Protectio9 Co9trol Register 0x2F1C2 16 read-write n AOFF TMnA pin output protection 2 4 read-write BOFF TMnB pin output protection 4 6 read-write PRTEN Pin protection enable 0 1 read-write __reserve0 0 is always read out. 1 2 read __reserve1 0 is always read out. 6 16 read TM9OFFSEL Timer 9 Pi9 Protectio9 Factor Selectio9 Register 0x2F1C6 16 read-write n AD0APE Protection factor selection by A/D0 conversion error detection interrupt 12 13 read-write AD0BPE Protection factor selection by A/D0 conversion error detection B interrupt 13 14 read-write AD1APE Protection factor selection by A/D1 conversion error detection interrupt 14 15 read-write AD1BPE Protection factor selection by A/D1 conversion error detection B interrupt 15 16 read-write CMP0PE Protection factor selection by CMP00 9 10 read-write CMP1PE Protection factor selection by CMP10 10 11 read-write CMP2PE Protection factor selection by CMP20 11 12 read-write IRQ0PE Protection factor selection by IRQ00 0 1 read-write IRQ1PE Protection factor selection by IRQ01 1 2 read-write IRQ2PE Protection factor selection by IRQ08 2 3 read-write IRQ3PE Protection factor selection by IRQ09 3 4 read-write IRQ4PE Protection factor selection by IRQ14 4 5 read-write IRQ5PE Protection factor selection by IRQ15 5 6 read-write IRQ6PE Protection factor selection by IRQ18 6 7 read-write IRQ7PE Protection factor selection by IRQ19 7 8 read-write NMIPE Protection factor selection by NMI 8 9 read-write TM9STR Timer 9 Cou9t Directio9 Status Register 0x2F1D2 16 read-write n BCSTR The count direction of binary counter 0 1 read __reserve0 0 is always read out. 1 16 read TM9STSEL Timer 9 Start Trigger Factor Selectio9 Register 0x2F1B2 16 read-write n STE Timer n start trigger enable 0 1 read-write STEG Start trigger factor edge selection 1 3 read-write STSEL Start trigger factor selection 4 8 read-write __reserve0 0 is always read out. 3 4 read __reserve1 0 is always read out. 8 16 read